As you say, CDC 6600 and its successor CDC 7600 have many of the characteristics of the RISC CPUs.

Compared with the IBM System/360, which was introduced around the same time, the instruction set of CDC 6600 was very simple.

Having hardware floating-point is something that is orthogonal with being RISC.

The goal of the RISC methodology of designing CPUs was not to create crippled CPUs that are so slow as to be unusable for practical purposes. The goal was to create a higher performance CPU by removing some features with great cost and little benefit.

Hardware floating-point is not one of those features. Removing the hardware floating-point unit from a CPU cannot increase its performance, it just makes the CPU useless for floating-point applications, because the speed of software FP implementations is much too slow.

The first RISC and MIPS projects did not have a FPU because they were student projects and designing a FPU would have required too much work. When commercial CPUs have been derived from those projects, they had to add hardware FPUs to become viable for the workstation market.

Also the width of the registers is something orthogonal with being RISC.

The same can be said about the partition of the registers into a set of address registers and a set of data registers. Depending on the ISA, such a partition can result in a simpler hardware than for a unified set of registers, e.g. by allowing the use of less read-write ports on the registers. Simpler hardware is a RISC goal.

There have been a large number of early computers with no microcode and with fixed-length instructions. Many have also been pipelined in various degrees.

However no early computer had a large number of registers, because the registers were very expensive when made with discrete components, so only a few computers had 8 registers or at most 16, but the majority had less registers than that.

With only a few registers, having only register-register operations and load/store operations would have been inconvenient, so I do not remember any early computer where most of the computation was done with register-register operations, before CDC 6600.

The splitting of the load from the operation that uses its value, either as distinctly encoded instructions or as micro-operations, has become necessary only when the CPU became faster than the main memory, like in CDC 6600, or in monolithic CPUs after 1980. In the slower CPUs, this would not have been a simplification.

A more precise formulation of the purpose of the large register set is not "to compensate for the lack of memory operands", but to allow the fast execution of the instructions despite the high latency of the loads from memory, by splitting the register-memory operations into register-register operations and separate loads. This split has the added bonus of enabling more efficient instruction encodings within the constraints of a fixed-length instruction format.

So a part of the RISC characteristics were present in the early computers, but having a large number of registers and doing computations only with register-register operations are choices that lead to a simpler CPU only in a certain technological context, which became available for cheap computers only around 1980, when the initial RISC projects were launched.