My first impression is that the RPi foundation has finally jumped the shark. There is a vast, vast number of microcontrollers available in every possible configuration. How can this chip possibly differentiate? How is custom silicon necessary to make a microcontroller dev board? How does this support their educational mission? I'm starting to come around.

The chip is interesting: it's as if they were listening to my (silent) complaints about the microcontroller industry. Dual core micros exist but dual core, low end, low power is more unique. Having multiple cores can actually simplify firmware since you can dedicate a core to a polling event loop rather than having to design, configure, and debug an interrupt based state machine within the hardware's limitations. The PIO peripherals are very interesting as well and look like a lot of fun. These two features are a half step towards something like the Parallax Propeller. The on board peripherals don't begin to approach the vast quantity and complexity that other manufacturers have accumulated over the years, but the PIO and extra core help to overcome this.

The peripheral to GPIO mapping is not quite any-to-any but it is very flexible. The pinout was specifically designed to be easily and logically broken out on a single layer. These issues are near to my heart since I'm in process of fighting to work around ST's almost random pin assignment and inflexible GPIO alternate functions on a much larger chip. ST does seem to be learning, though, with their newer STM32G0 series.

As expected the RPi foundation put a lot of work into documentation, both beginner level and the datasheet. The datasheet looks quite good, though it's hard to say if it's better than ST's until I use it in anger.

Not having on-board flash feels a bit old fashioned but it's cheap and easy to interface an external SPI flash. As I understand it FLASH can be difficult and expensive to integrate on-die due to the relatively high voltages required for programming (~20V). It takes up a lot of die space and then you need more die space for the programming, read-out, addressing, and control logic [0]. ST's blurb about their manufacturing process always talks about their proprietary on-die FLASH technology which goes to show how big of a manufacturing optimization challenge it is. It makes a lot of sense to avoid for their first chip.

The RPi Foundation has always had one foot in the proprietary world. I've excused this before as a necessity required for them to make hardware, and they've done little bits to push the hardware world in a more open direction. I'm still disappointed that this non-profit has essentially created their own "Intel MKL" of optimized subroutines rather than contributing them back upstream. Even the Intel MKL is licensed to work on other compatible processors.

It's hard to overstate how limiting it feels to only have one chip available in a microcontroller series. The chip part number explanation in the datasheet suggests that they'll release other variants with different numbers of GPIO, different packages, different number of cores and RAM. The foundation will never approach the breadth of the big boys, however. It helps to be part of the ARM ecosystem where at least the code, core peripherals, and debug interface are portable. It's the rest of the custom peripherals that get you stuck, but using a HAL helps with at least the basic functionality of the common peripherals. Also peripherals and configuration aren't always completely identical across a manufacturer's lineup so you should expect a baseline level of porting effort anyway.

So it's a neat chip and I'm glad they're making it. Adding microcontroller-level tech to their curriculum definitely helps their mission, but as the Arduino and BBC Micro:bit have shown it's not necessary to make a custom chip to achieve that goal. It may even be detrimental as students are learning a chip which is less relevant in industry - modulo the mitigating factors in the previous paragraph. However, this is a good first independent project for the RPi chip design team which could be a step towards releasing a better or more open mainline RPi with a fully custom SoC in the future. There's also a point where their volume is so high they don't need that much of a justification.

[0]: http://electronupdate.blogspot.com/2018/08/espressif-esp32-t...