His idea that AVX-512 is something that's exclusively for floating-point is completely off-base, AVX has included integer operations since AVX2. Widely used in JIT, database, etc.

Furthermore, AVX-512 is about much more than doubling the vector width, it is a significant overhaul to the instruction set and adds many new operations and "fills in gaps" that were missing from previous instruction sets. It in fact would be perfectly valid and good to implement AVX-512 with a 256-bit unit that takes twice as long to run 512-bit width instructions. This completely negates all his points about die space utilization right from the start - AVX-512 support does not imply a significantly larger use of space than previous AVX instructions. This would also fix some of the power-related problems on Skylake-SP - after all if you go from 2 512-bit wide units to 2x256 gangable units or 1x256 running at half-rate, that reduces power correspondingly and you no longer need to drop clocks so strongly to offset this, but you keep the functionality added in AVX-512.

Furthermore, it's not like there are massive gains in general IPC that haven't been tapped. AVX-512 has taken 25% of the die area in some instances, if you dropped that to AVX2 (assume 12.5% of die area) then it's not like the processor would be 12.5% faster in general, that would translate to maybe 2-3% faster in general and a 30%+ loss in specialty applications. Once you've mostly explored general-purpose gains and are into diminishing returns territory (which modern processors certainly are), it makes sense to start looking at "specialty units", like AVX, or on GPUs you've got tensor cores and BVH traversal units, and so on. These can provide big speedups in key tasks at the cost of very little "general" performance (since that's already in diminishing returns territory).

The biggest thing slowing down AVX-512 adoption has been, yet again, 10nm. Right now it is only available on Skylake-X and Skylake-SP products, and more recently Ice Lake (which came out September of last year, in only the ultrabook segment, supplemented by 14nm in the mobile workstation segment as well as the ultrabook segment). So right now it is available in less than 1% of the desktop "fleet" and probably less than 1/8th of the laptop "fleet". There is very little reason to implement code paths for an instruction set that nobody can execute. Over time, as Ice Lake and Tiger Lake build share of the laptop "fleet", Rocket Lake implements it on desktop, and AMD implements it whenever, it will see more usage, just like prior AVX sets.

It really is wider-market than people realize. I have seem many people scoff and say "well you'll never see it used in games or whatever", but for many years now there have been games that simply will not run if you don't have AVX (notably many Ubisoft titles), there is no fallback SSE/scalar codepath. In another 10 years you will probably have AVX-512 mandatory games as well.

With all due respect to his long career in software engineering, that doesn't necessarily translate to processor design. This is just one person's opinion and you are under no obligation to accept it as gospel just because it's Torvalds'. See also: his weird ZFS rant.

(This seems to be a common thing with software engineers in particular, including many on this site - can't count how many "one weird fix from a software engineer to fix [complex domain problem] in [chemical/materials/aerospace engineering]" I've seen. I of course have no particular expertise in processor design either, but the engineers at Intel presumably do, and they thought it was a good idea.