I need to post a major correction to my comment above.

All my power numbers here were off by three orders of magnitude. The MSP430 uses almost a nanojoule per instruction, not almost a picojoule.¹ The Pentium used 10 nanojoules per instruction, not 10 picojoules.² The STM32L011x3/4 uses 0.23 nJ per instruction, not 0.23 pJ.³ The LPC1110 uses 0.3 nJ per instruction, not 0.3 pJ.⁴ Research CPUs using exotic logic families have reached 0.01 nJ per instruction in 2008 and 0.0026 nJ per instruction in 2006, not below 0.05 pJ.⁵

Also, I should have mentioned the GreenArrays chips, which are actually fast; they're not mainstream not because they're slow but because you can't program them in C. Each core has 64 words of RAM and no PROM, so the only practical way to program them is in Forth. But they use 8 pJ per instruction, i.e. 0.008 nJ.

¹ TI's 2012 whitepaper http://www.ti.com/general/docs/lit/getliterature.tsp?baseLit... http://www.ti.com/lit/wp/slay015/slay015.pdf claims the MSP430F2001 can run a million instructions per second on 300 microamps on a 3-volt power supply, which works out to 900 μW, or 900 pJ/insn. GreenArrays published a whitepaper http://www.greenarraychips.com/home/documents/greg/WP003-100... comparing an MSP430F5xx at 8MHz to a GreenArrays chip; they claim that TI publication SLAS655A claims that the MSP430 uses 330 pJ per instruction or 2310 pJ per 16×16-bit multiply, while the GreenArrays core consumed 8 pJ per instruction or 450 pJ per 16×16 multiply.

² http://www.newscientist.com/blog/technology/2006/08/explodin... (WABAC machine link: http://web.archive.org/web/20161228045915/www.newscientist.c...) says that the Pentium from 1993, Pentium Ms from 2003, and Core Duos from 2006 all use 10 to 13 nanojoules per 32-bit instruction.

³ According to the ST datasheet for the STM32L011x3 and STM32L011x4 (DocID027973 Rev 5), these chips typically use 1.95 mA at 16MHz on range 2 (Vcore = 1.5 V, VOS[1:0] = 10) on the HSI16 clock source with Dhrystone-equivalent data processing code executed from RAM, Flash switched OFF, in Run mode (Table 24 on p.55 in §6.3.4, "Supply Current Characteristics"), and they claim 0.95 Dhrystone MIPS per MHz on the front page. This is with Vdd = 3.0 V (according to p. 52) but the extra 1.5 V is just burned in a linear voltage regulator, so the current consumption should be almost exactly the same anywhere in the operational range from 1.65 V to 3.6 V. If we assume 1.8 V, which is probably close to the lowest safe voltage, we get 1.8V · 1.95 mA = 3.51 mW. Dividing this by 0.95 · 16 MHz, we get 231 pJ per instruction; presumably in real life the number would vary anywhere from 200 to 1000. Both higher and lower clock speeds use more energy per instruction, as does running from Flash.

⁴ The LPC1110 datasheet http://www.nxp.com/documents/data_sheet/LPC111X.pdf claims it can run at 48 MHz at 1.8 V and just under 8 mA, which works out to 300 pJ per instruction. It's probably using an earlier version of the same IP core in the ST chip.

⁵ http://www-mtl.mit.edu/researchgroups/icsystems/pubs/confere... is A 10-pJ/instruction, 4-MIPS Micropower DSP for Sensor Applications, Ickes et al., MIT, 2008; http://web.eecs.umich.edu/~taustin/papers/VLSI06-sublim.pdf is A 2.60pJ/Inst Subthreshold Sensor Processor for Optimal Energy Efficiency, Zhai et. al., poster, 2006. I'm not totally clear on whether these processors were actually fabricated or not.