I've honestly been waiting for this since for YEARS.

I've had a vision for "the future of computing". FPGAs that reconfigure themselves (<-these exist) to become whatever macro-level hardware assets your computer needs. Running tons of SHA-256 encryptions per second? The CPU/OS/OpenSSL (or whatever) detects this condition and switches from hand-coded ones, to an IP core that comes with the CPU. The CPU flashes the FPGA's to become SHA-256 "CoreS" and now you're running 4096x the output with less heat. (As CPUs are designed for one thing "few, large, complex cases" while FPGAs are perfect for many, parallel simple cases" even more than a GPU.) Now, you shutdown your encoding and switch to video encoding, or Doom 2019 and your CPU reflashes (Alteria specialized in PARTIALLY flashable FPGAs so you don't have to nuke the entire FPGA, only sections) and adds cores for video, or physics, or "shader units".

This would be hard for a single person, but any large company could handle making this. You can even do it with off-the-shelf FPGAs. The biggest problems are 1) bandwidth. The "macro" function size needs to be bigger than the latency hit you take for asking the FPGA over computing it internally. (Intel's on-CPU FPGA would be insanely fast access.) and the other one is 2) How do you get people to use it! The simplist is of course, only supporting people who actually request it. But, you can take libraries that perform common, encapsulated macro functionality, like OpenGL, a physics library, or OpenSSL, where people don't care about the inner code ("how it gets done") but instead the result. Asking for floats to be multiplied would be bad. But asking for a cross-product would be much faster. Asking for an SHA-512 key would be super.

And the benefit here is, you don't have to hardcode that functionality into a CPU. The FPGA can have NEW or improved IP cores downloaded with Windows Update every week.

Back when I was in college, I actually bought a Lattice dev kit with a PCI Express card, dual-gigabit ethernet, DDR3, and an near top-of-the-line FPGA on the board and it cost a mere $100. Unfortunately, I was a more software guy so I really got in over my head (plus health issues set me back and have never let up since), so I never got a working prototype built.

But it's still there! A huge opportunity waiting to be seized that could really become another tier of "the standard PC." In the same way we think of SSDs as "almost RAM" scratchpads, or GPUs as "CPUs for massive amounts of simple decisions." Well an FPGA is the "GPU of GPUs". Even simpler decisions and insanely fast and parallel even at "low" (by CPU standard) clockrates of 400 MHz.

Here's an older (2009) project/research article that inspired me called the 512 FPGA cube.

http://cc.doc.ic.ac.uk/projects/prj_cube/Welcome.html

http://cc.doc.ic.ac.uk/projects/prj_cube/spl09cube.pdf

And here's a direct link to the data table results between FPGA, FPGA cube, and Xeon (and cluster of Xeons) trying to do the same work:

https://i.imgur.com/byjmEDG.png

Those are massive differences in numbers in both power efficiency and compute rate. 72,000 Watts of Xeons to get the speed of a single 832 watt cube. That's two orders-of-a-magnitude!

I mean, imagine a world if they bothered to make FPGA's you could plug into Ethernet, and make them configure themselves according to a simple programming tool that was "easy" for normal programmers to exploit instead of requiring intense understanding of logic gates, propagation delay, and so on. A tool that wasn't "as fast as" a dedicated engineer, but 90% (or even 70%) as fast at zero cost and effort. All a sudden you could run tons of programs and macro-sized functions like you had personally stamped them into a printed circuit yourself, but without spending millions on development.

I'm honestly not sure why this hasn't already happened. I can't be the only "smart" person who came up with this idea. And the research (and practice with bitcoin miners) all points to a huge opportunity to be exploited if they could lower the knowledge barrier-to-entry so you can basically "push a button" and unleash an FPGA at a problem. Imagine LAPACK and BLAS with FPGA support.