"You're obviously more in tune with the project than I am. I never worked at Intel, but a lot of my friends did (mostly in implementation rather than architecture)."

Nah, I just read the Wikipedia articles, the chapter from the capability systems book, and the other papers I linked. I'm digging history out piece by piece like anyone else.

"As for Colwell's critique, Intel must have liked it so much that they hired him. :) I attended a number of Colwell's public presentations on various x86 chips, and he seemed like a smart, approachable, down-to-earth guy."

Oh hell! Didn't know he got hired. That's cool. Good to hear that about his character, too, because that makes him a worthwhile consultant on clean-slate chips if he's still alive and in the field.

"So I'm sure there was lots of internal politics going on at Siemens also."

Politics and trying to do everything at once from what I gather. Along with picking safe languages like Ada again with market rejection. Gotta at least support whatever is popular. Additionally, there was the backward compatibility effect: need to virtualize prior ISA so apps aren't thrown away. IBM's capability system (System/38->AS/400) was doing that while Intel's didn't.

So, a number of reasons these things failed.

"One other thing that confuses me with various wiki entries of all this is that Wiki mentions Fred Pollack more prominently, whereas the name I heard more was Justin Rattner."

That is weird. Someone should try to get to the bottom of that sometime. Meanwhile, a quick Google led to this:

https://en.wikipedia.org/wiki/Justin_Rattner

Tells us little but notice that the patents' functionality correspond to subsystems of i432. The first 3 at least because the 4th is ambiguous. He could've been one of the bright HW people on the team coming up with the tech while Pollack led the project.

"perhaps something more architecturally advanced should be considered. Who cares if it's only 25% of the performance of the x86. The tradeoffs in terms of security etc might make it worth while. At least for high reliability applications."

You see, I agree but they've tried and failed this before. The only one you didn't link was Itanium: the third attempt to clean-slate CPU's for higher performance, reliability, and security. Itanium had enough RAS features for use in mainframe-style SMP systems and its security features could have been used for very secure systems. One company did with its CTO being the Itanium designer probably having something to do with that. ;)

https://www-ssl.intel.com/content/dam/www/public/us/en/docum...

Anyway, VLIW part and disconnect from legacy meant little uptake despite around $200 million spent. At this point, Intel may have been burned too many times by the market to try too hard. The next step is to go for the legacy + accelerator model which has paid off for them with GPU's and custom instructions. Dedicated hardware or onboard FPGA's can give a performance boost while supporting legacy app.

I'd also consider mixing clean-slate and legacy CPU's in the same system where legacy app can run on one with accelerators running on other with smooth, function-call-level integration. They could have the same endianess, ABI, data-types, etc to make it easier. The rest is different for better parallelism, less bloat, enhanced security (eg pointer protection), fault-tolerance, and so on.

Many possibilities but Intel will be careful given billions invested in nothing so far.