Search query: A floating gate and its application to memory devices

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abstract: A structure has been proposed and fabricated in which semipermanent charge storage is possible. A floating gate is placed a small distance from an electron source. When an appropriately high field is applied through an outer gate, the floating gate charges up. The charges are stored even after the removal of the charging field due to much lower back transport probability. Stored charge density of the order of 1012/cm2 has been achieved and detected by a structure similar to an metal insulator semiconductor (MIS) field effect transistor. Such a device functions as a bistable memory with nondestructive read out features. The memory holding time observed was longer than one hour. These preliminary results are in fair agreement with a simple analysis.
author_names: Dawon Kahng

Simon M Sze
title: A floating gate and its application to memory devices
year: 1967

author_names: K Kahng

Simon M Sze
title: A floating gate and its application to memory devices
year: 1967

abstract: Non volatile memories (NVM) are playing a very important role in the semiconductor market, thanks in particular to Flash technology, that is used mainly in cellular phones and other types of electronic portable equipment (mobile PCs, mp3 players, digital cameras and so on) This trend will continue in the coming years and it is expected that portable systems will demand even more from NVM either with high density and very high writing throughput for data storage application, or with fast random access for code execution in place. Although Flash memory technology has been able to follow the evolution of the semiconductor roadmap, since its introduction in late 1980s, and further scaling down is forecasted to continue into the coming years, there are some physical limitations to be faced and the downscaling beyond the 45 nm technology node is still considered critical. Hence other technologies, alternative to floating gate devices, have been proposed and are under investigation. These new proposals exploit different physical mechanisms to store the information, like magnetism, ferroelectricity, solid electrolysis, and phase change. Among the different NVM based on these mechanisms, apart from the floating gate concept, phase change memories (PCM) also called ovonic unified memories (OUM) are one of the most promising candidates to become a mainstream NVM, having the potentiality to improve the performance compared to Flash random access time, read throughput, direct write, bit granularity, endurance as well as to be scalable beyond Flash technology.
author_names: Roberto Bez

A Pirovano

Fabio Pellizzer
title: Phase change Memories
year: 2005

abstract: Among the many possible device confi gurations of fl ash memory, fi eld effect transistor (FET) based memory with a fl oating gate architecture is considered to be a promising candidate towards the ultimate goal of fl ash memory due to its single transistor realization, non destructive read out, and compatibility with complementary metal oxide semiconductor (CMOS) devices. 1 5 Floating gate FET memory with metal nanoparticles (NPs) embedded in the gate dielectric is a way to replace planar fl oating gates to meet the requirements of fast data access and high density for the next generation of fl ash memory. 6 12 However, poor charge retention time induced by the thin tunneling dielectric layer is a drawback for NP fl oatinggate memory devices. 13 Simply increasing the thickness of the tunneling dielectric layer would degrade the program/ erase speed and increase the power consumption. 12 On this regard, as an alternative approach, the double NP fl oating gate structure has been proposed to achieve better retention properties. 13 15 In previous reports, double NP fl oating gates have generally been made with the same materials. The retention time could be improved by preventing the trapped charge carriers leaking back to the channel through the energy barrier arising between the upper and lower fl oating gates. Nevertheless, most double NP fl oating gates consisting of two layers of NPs fabricated by chemical synthesis or thermal evaporation could not form NP pairs in the vertical direction. Additionally, the double NP fl oating gate structure may result in a poor interface between the NPs and the dielectric layer, which would have an adverse impact on the overall device performance. Therefore, developing an appropriate upper fl oating gate material with the following properties is necessary for technological applications: i) a suitable work function to set up an energy barrier so a long retention time is obtained; ii) a large area to achieve an accurate spatial distribution on the lower fl oating gate; and iii) a fl attened surface to improve the interface quality between the double fl oating gate and the dielectric layer. As one of the thinnest materials ever known in the universe, graphene
author_names: Su-Ting Han

Ye Zhou

Chundong Wang

Lifang He

Wenjun Zhang

Vellaisamy A L Roy
title: Layer by layer assembled reduced graphene oxide/gold nanoparticle hybrid double floating gate structure for low voltage flexible flash memory.
venue: Advanced materials
year: 2013

abstract: In this work we explore the use of extension less doping schemes for fully depleted devices [two dimensional (2D) ultra thin body and buried oxide layer (BOX) planar devices (UTBB) three dimensional (3D) multi gate field effect transistor devices with the conduction channels wrapped around silicon (Si) fins (FinFETs) and built on bulk Si or silicon on insulator (SOI) substrates] suitable for advanced logic, memory and dense circuit applications. We demonstrate that by using Si epitaxial raised source (S)/drain (D) (SEG) followed by highly doped drain (HDD) only implantations (I/I) or by using doped SEG and no I/I: 1) lower off state current (IOFF) and drain induced barrier lowering effect (DIBL) 2) steeper sub threshold slope (SS) 3) higher on state/off state currents ratio (ION/IOFF) and 4) higher retention times [for floating body random access memory (FBRAM) on UTBB] can be obtained, while reducing cost and cycle time with less critical I/I photos. SEG facet formation can be controlled by the spacers shape and epi pre clean step and its impact on device characteristics for logic and FBRAM applications is also analyzed.
author_names: Anabela Veloso

A De Keersgieter

Marc Aoulaiche

Malgorzata Jurczak

Aaron Voon-Yew Thean

Naoto Horiguchi
title: Two and Three Dimensional Fully Depleted Extension Less Devices for Advanced Logic and Memory Applications
year: 2013

abstract: Abstract In this work we explore the use of extension less doping schemes for fully depleted devices [2D: ultra thin body and BOX (UTBB) planar devices; 3D: FinFETs on bulk Si or SOI substrates] suitable for advanced logic, memory and dense circuit applications. We demonstrate that by using Si epitaxial raised S/D (SEG) followed by HDD only implantations (I/I) or by using doped SEG and no I/I: 1) lower IOFF and DIBL; 2) steeper sub threshold slope (SS) 3) higher ION/IOFF ratio; and 4) higher retention times (UTBBFBRAM) can be obtained, while reducing cost cycle time with less critical I/I photos. SEG facet formation can be controlled by the spacers shape and epi pre clean step and its impact on device characteristics for logic and FBRAM applications is also analyzed. Introduction Ultra thin body fully depleted devices [planar on ultra thin BOX (UTBB) and FinFET based multi gate structures (MuGFETs) have long been considered an attractive option for enabling further CMOS scaling beyond the 22nm technology node, thanks to their improved electrostatics and steeper sub threshold slopes (SS) with reduced VT variability due to lower channel dopants concentration [1 8] For both architectures, however, the extremely thin body poses new integration challenges, namely for junction engineering and the extendibility of conventional doping techniques such as ion implantation (with tilt angle restrictions due to resist shadowing at tight pitch) parasitics and series resistance (RS/D) control. Improved morphology of the c Si body and near zero tolerance Si loss is required. In this paper, several extension less strategies for scaled UTBB and FinFET devices are evaluated for improved performance, short channel effects (SCE) and variability control. Increased interest in potential memory architecture alternatives to DRAM, such as one transistor floating body RAM (1T FBRAM) [9,10] will also be addressed in this work through the use of a process flow fully compatible with UTBB logic technology. Device fabrication A schematic of the process flow used for fully depleted devices fabrication is shown in Fig.1, for both 2D (UTBB planar) and 3D (FinFETs on bulk Si or SOI substrates) Extension less devices were fabricated with a narrower 1 spacer (CD15nm after SEG) followed by SEG HDD I/I RTA as illustrated in Fig.2. An alternative I/I free approach consists in doing doped SEG RTA. Reference devices include extensions I/I prior to SEG HDD I/I RTA, for both 2D and 3D architectures, with total spacer width prior to silicidation similar for all devices. Gate stack consists of (HfSiON or HfO2)/TiN for logic, 5nm SiO2/TiN for 1T FBRAM. Device results and discussion Fig.3 shows lower IOFF values for extension less SOI FinFET devices, consistent with the expected reduced gate overlap. 7tilt I/I was used here for all devices under comparison to enable pitch scaling without resist shadowing effects. These devices also exhibit excellent SCE behavior with the ID VG curves in Fig.4 highlighting the lower off state current obtained with extension less (SEG HDD I/I RTA) vs. reference (Extension I/I SEG HDD I/I RTA) implant strategies, corresponding to a lower DIBL~36mV/V and SS~70mV/dec. Furthermore, it is important to mention the better quality, defect free SEG less Rout variability) expected to be obtained when starting from undoped fins [3,5] as is the case with the extension less I/I approach. An alternative extension less and I/I free doping technique is illustrated in Fig.5, where a RTA anneal is used to drive dopants from the in situ doped SEG grown on the S/D areas of a bulk FinFET device. The RTA condition used determines the dopant (As in Fig.5) diffusion profile and resulting doping contours in the top and vertical channels. Benchmarking with reference devices (bulk FinFETs with conformal doping by I/I) TCAD simulations were performed for assessing the impact of several process parameters changes, such as spacer width variations, on junctions profile and device characteristics. Overall, as observed before for extension less devices built with [SEG HDD I/I RTA] steeper SS, smaller DIBL, lower IOFF and higher ION/IOFF ratio values are also obtained for these I/I free devices (Figs.6,7) Wider offset (1) spacers translate into reduced gate overlap and a further increase on the difference for these parameters with regards to the implantedreference, with a compromise needed to also keep high absolute values for ION. Fig.8 shows that increasing the Si recess depth (10 40nm) prior to SEG growth leads to higher drive currents due to a more effective fin doping, but at the expense of a reduction in the ION/IOFF ratio and a small (eventually leveling off) DIBL increase. TEM image and schematics of UTBB planar devices fabricated for use as 1T FBRAM are shown in Fig.9, with 14nm thick Si channel and 18nm thick BOX. Also in this case, improved DIBLLgate behavior is measured for extension less devices built with the I/I sequence: SEG HDD I/I RTA (Fig.10) Fig.11 shows devices with and without SEG faceting, depending on the spacers bottom shape and the HF time used in epi pre clean. A faceted SEG in S/D has been shown to reduce RS/D and minimize gate toS/D parasitic capacitance [4,6] Its impact on the lateral electric field for a Lgate70nm device in the hold "0" state is shown in Fig.12. A lower maximum field at gate edges was simulated for extension less devices, more so if SEG has no facets. This results in a 5 retention time improvement for 1T FBRAM extensionless devices with faceted SEG, with further improvement expected to occur with facet less SEG due to its even lower maximum field (Fig.13) Retention is determined by the "0" state degradation (holes generation occurring during "0" state hold) with band toband tunneling and trap assisted tunneling mechanisms limiting the retention time [11] and responsible for the field dependence seen here. At the same time, Fig.13 shows that similar retention time distributions are obtained for the different type of devices evaluated suggesting similar traps, and generation/recombination (GR) centers distributions. For logic UTBB planar devices (see Fig.14) the two doping approaches (with and without extensions I/I) yield results in line with those obtained for FinFETs and for 1T FBRAM UTBB devices. This is illustrated by the simulation results plotted in Figs.15 and 16. Overall, lower IOFF, steeper SS, and smaller DIBL values can be obtained for extension less devices with optimized 1 spacers width. Again, careful balance between IOFF reduction and ION increase is needed, depending on final device application, including 6T SRAM for which lower IOFF values are of the uttermost importance. Figs.15,16 also show that, for similar HDD only I/I conditions, SEG faceting results in considerably improved drive currents with no significant IOFF penalty, though at the expense of higher DIBL and SS values. Conclusions A comprehensive evaluation of two extension less doping schemes suitable for scaled 2D and 3D fully depleted devices for logic and memory applications was reported: HDD only I/I after SEG or I/I free, doped SEG, both followed by RTA. Results show: lower IOFF and DIBL, steeper SS, higher ION/IOFF ratio, and higher retention times (UTBB FBRAM) with reduced cost cycle time. SEG faceting control, key for parasitics and variability reduction, leads to improved performance for logic and memory. References [1] J. Kavalieros et al. VLSI Tech. Dig. 2006, 62; [2] H. Kawasaki et al. IEDM Tech. Dig. 2008, 237; [3] T. Merelle et al. IEDM Tech. Dig. 2008, 241; [4] K. Cheng et al. VLSI Tech. Dig. 2009, 212; [5] A. Veloso et al. IEDM Tech. Dig. 2009, 301; [6] K. Cheng et al. VLSI Tech. Dig. 2011, 128; [7] A. Veloso et al. Jpn. J. Appl. Phys. 50, 04DC16, 2011; [8] http:/newsroom.intel.com/docs/DOC2032; [9] I. Ban et al. VLSI Tech. Dig. 2008, 92; [10] Z. Lu et al. IEDM Tech. Dig. 2010, 288; [11] O. K. B. Lui et al. Solid State Elect. 41(4) 575, 1997.
author_names: Anabela Veloso

A De Keersgieter

Marc Aoulaiche

Malgorzata Jurczak

Aaron Voon-Yew Thean

Naoto Horiguchi
title: 2D and 3D Fully Depleted Extension less Devices for Advanced Logic and Memory Applications
year: 2012

abstract: This paper describes the narrow and non spread distribution of threshold voltage in MONOS (Metal oxide nitride oxide semiconductor) memory cell array. We fabricated 4 Mbit MONOS memory test chip using 0.25 /spl mu/m technology. The gate length of the memory cell is shrunk to 0.18 /spl mu/m. The distributions of threshold voltage in many operations are evaluated. As a result range of the distribution of threshold voltage keeps narrow in program and erase operation. It also keeps narrow in heat treatment of 300/spl deg/C. These characteristics are also good advantages of MONOS memory device for multi bit memory applications. It is also shown that there is a possibility to achieve non verify operation in both program and erase cycle. The MONOS memory device is a promising form of nonvolatile memory for use in cheaper than floating gate (FG) yet highly reliable embedded applications.
author_names: Toshio Terano

Hiroyuki Moriya

Akihiro Nakamura

H Kosaka

A Hashiguchi

Kazumasa Nomoto

I Fttjlwara

Tsukasa Kobayashi
title: Narrow distribution of threshold voltages in 4 Mbit MONOS memory cell arrays and its impact on cell operation
venue: International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)
year: 2001

abstract: The quest for mass storage and the diversity of end user applications led to an aggressive scaling of the NAND Flash memory. A key factor to its success is the high density integration potential, which allows fabrication of large memory arrays. Reduction of the feature size below 40 nm may, however, require modifications of the conventional floating gate (FG) cell architecture, due to lack of physical space between neighboring cells [1] which no longer allows wrapping of the control gate (CG) over the floating gate (FG) This has consequences on both intraas well as inter cell levels.
author_names: Bogdan Govoreanu

Jorge A Kittl

Joeri de Vos

A Rothschild

Pieter Blomme

Dirk Wellekens

D Ruiz Aguado

Malgorzata Jurczak

Jan Van Houdt
title: The Flash Memory Cell for the Nodes to Come: Material Requirements from a Device Perspective
year: 2009

abstract: Nanocrystal (NC) floating gate flash memory is considered to be one of the most promising candidates to replace conventional highly doped polysilicon floating gate flash memory technology widely used today. [1] Metal NCs is more desirable compared to its semiconductors to work as charge storage storage node, because metals usually have large work function and can be engineered down to 1 nm without decreasing potential well depth. [2, 3] However, most metal NCs are easily oxidized and diffuse into the surrounding dielectric under high temperature process conditions, resulting in bad NC dielectric interface quality and the degradation of the memory performance.[4] In this paper, for the first time, we present an approach using Ruthenium (Ru) NC buried in HfO2 matrix to work as charge storage nodes, which can create a robust NC high K dielectric interface. Combined with some advantages of Ruthenium, good memory device performance can be achieved. Device Fabrication: The device fabrication started with a P type silicon substrate with the resistivity about 1 10 .cm. After a standard RCA clean and a 1:40 HF solution dip to remove native oxide, about 43A HfO2 was deposited by atomic layer deposition (ALD) as tunneling oxide. Then a thin Ruthenium film was deposited by physical vapor deposition process. After that, the Ruthenium nanocrysal matrix was formed by a rapid RTPDA process of the samples in N2. Then 150 A HfO2 control oxide was deposited by reactive DC sputtering in an Ar/O2 ambient, and finally 2000 A TaN electrode deposited by reactive DC sputtering was deposited as electrode. A control sample without Ruthenium nanocrystals was also fabricated to check for charge trapping in the dielectrics. Device Structure Verification and Electrical Measurements: The memory cell diagram is shown in figure 1. Atomic force Microscopy was used to check the results of the Ruthenium nanocrystal formation by RTPDA process. In our study, it shows that the RTPDA process parameters, including annealing temperature(T) and annealing time(t) and original film thickness(d) has deep impact on the formation of Ruthenium nanocrystal on HfO2 surface. Figure 2 shows the Ruthenium nanocrystal formation results under different conditions: (a) d=2 nm, T=600 C q t=30 S, (b) d=5 nm, T=700 C
author_names: Hai Liu

Domingo A Ferrer

Sanjay K Banerjee
title: Student Paper Formation of Ruthenium Nanocrystals Buried in HfO2 Matrix for Nonvolatile Memory Applications
year: 2009

abstract: Nanocrystal (NC) floating gate flash memory is considered to be one of the most promising candidates to replace conventional highly doped polysilicon floating gate flash memory technology widely used today. [1] Metal NCs is more desirable compared to its semiconductors to work as charge storage storage node, because metals usually have large work function and can be engineered down to 1 nm without decreasing potential well depth. [2, 3] However, most metal NCs are easily oxidized and diffuse into the surrounding dielectric under high temperature process conditions, resulting in bad NC dielectric interface quality and the degradation of the memory performance.[4] In this paper, for the first time, we present an approach using Ruthenium (Ru) NC buried in HfO2 matrix to work as charge storage nodes, which can create a robust NC high K dielectric interface. Combined with some advantages of Ruthenium, good memory device performance can be achieved.
author_names: Hai Liu

Domingo A Ferrer

Sanjay K Banerjee
title: Formation of Ruthenium nanocrystals buried in HfO2 matrix for nonvolatile memory applications
venue: 2009 International Semiconductor Device Research Symposium
year: 2009