Search query: On-chip Optical Interconnect Roadmap: Challenges and Critical Directions

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abstract: Intrachip optical interconnects (OIs) have the potential to outperform electrical wires and to ultimately solve the communication bottleneck in high performance integrated circuits. Performance targets and critical directions for ICs progress are yet to be fully explored. In this paper, the International Technology Roadmap for Semiconductors (ITRS) is used as a reference to explore the requirements that silicon based ICs must satisfy to successfully outperform copper electrical interconnects (IEs) Considering the state of the art devices, these requirements are extended to specific IC components
author_names: Mikhail Haurylau

Guoqing Chen

Hui Chen

Jidong Zhang

Nicholas Nelson

David H Albonesi

Eby G Friedman

Philippe M Fauchet
title: On Chip Optical Interconnect Roadmap: Challenges and Critical Directions
venue: IEEE Journal of Selected Topics in Quantum Electronics
year: 2006

abstract: Intrachip optical interconnects can outperform electrical wires but the required parameters for optical components are yet unknown. Here the ITRS is used as a reference point to derive the requirements that optical components must meet.
author_names: Mikhail Haurylau

Hui Chen

Jidong Zhang

Guoqing Chen

Nicholas Nelson

David H Albonesi

Eby G Friedman

Philippe M Fauchet
title: On chip optical interconnect roadmap: challenges and critical directions
year: 2005

abstract: Intrachip optical interconnects(OIs) have the potential to outperform electrical wires and to ultimately solve the communication bottleneck in high performance integrated circuits. Performance targets and critical directions for Ics progress are yet to be fully explored. In this paper, the International Technology Roadmap for Semiconductors (ITRS) is used as a reference to explore the requirements that silicon based Ics must satisfy to successfully outperform copper electrical interconnects (IEs) Consiering the state of art devices, these requirements are extended to specific IC components.
author_names: Nemi Chand Neel

Ajay Kumar Banyal

Manu Sharma

Mikhail Haurylau

G Chen

John X J Zhang

E G Fried

Philippe M Fauchet
title: On Chip High Speed Optical Interconnect with RLCG Electrical Interconnect: Challenges and Dimensions
year: 2013

abstract: VLSI/ULSI and the evolutions being driven by the International Technology Roadmap for Semiconductors (ITRS) are once again presenting severe challenges to the metal interconnect. Clock skew and other timing delays are becoming application critical design factors. The RC induced delays as well as parasitics (due to the trace density) are causing severe limitations to designs. Unfortunately these issues are very difficult to deal with using conventional computer aided design tools although efforts are being made, notably via DARPA funded programmes. We shall review techniques (and design elements) for on chip optical communications. Through this we will present a new proposition for optical interconnects integrated upon otherwise conventional CMOS devices. We believe that the illustrated methodologies can be developed to provide very effective optical functionality appropriate to alleviating high speed communications and timing issues.
author_names: Terry V Clapp

Laurence W Cahill
title: Applications of CMOS processing to realize functional on chip optical interconnects for VLSI
venue: SPIE OPTO
year: 2003

abstract: We present a computing microsystem that uniquely leverages the bandwidth, density, and latency ad vantages of silicon photonic interconnect to enable highly compact supercomputer scale systems. We describe and justify single node and multinode systems interconnected with wave length routed optical links, quantify their benefits vis a` vis electrically connected systems, analyze the constituent optical component and system requirements, and provide an overview of the critical technologies needed to fulfill this system vision. This vision calls for more than a hundredfold reduction in energy to communicate an optical bit of information. We explore the power dissipation of a photonic link, suggest a roadmap to lower the energy per bit of silicon photonic interconnects, and identify the challenges that will be faced by device and circuit designers towards this goal.
author_names: Ashok V Krishnamoorthy

Ron Ho

Xuezhe Zheng

Herb Schwetman

Jon K Lexau

Pranay Koka

Guoliang Li

Ivan Shubin

John E Cunningham
title: Computer Systems Based on Silicon Photonic Interconnects A proposed supercomputer on a chip with optical interconnections between processing elements will require development of new lower energy optical components and new circuit architectures that match electrical datapaths to complementary optical
year: 2009

abstract: Emerging telecommunication and data routing applications anticipate a photonic roadmap leading to ultra compact photonic integrated circuits. Consequently, photonic devices will soon have to meet footprint and efficiency requirements similar to their electronic counterparts calling for extreme capabilities to create, guide, modulate, and detect deep subwavelength optical fields. For active devices such as modulators, this means fulfilling optical switching operations within light propagation distances of just a few wavelengths. Plasmonics, or metal optics, has emerged as one potential solution for integrated on chip circuits that can combine both high operational speeds and ultra compact architectures rivaling electronics in both speed and critical feature sizes. This article describes the current status, challenges, and future directions of the various components required to realize plasmonic integrated circuitry.
author_names: Volker J Sorger

Rupert F Oulton

Ren-Min Ma

Xiang Zhang
title: Toward integrated plasmonic circuits
year: 2012

abstract: High density interconnect microelectronics emphasizes the effective integration of several critical and complex electronic packages and technologies. This Roadmap introduces current technologies in use, related strategic issues and trends, and research recommendations for space applications. Electronic packages are optimized for low cost, portability, robustness, high speed, power efficiency, and for small size and low weight. Satisfying these increasing demands will require enhanced electronic performance with an associated improvement in packaging performance and better relief from thermal and mechanical stresses. Technical challenges and directions for high density interconnect microelectronics packaging include understanding latent electromigration and dendritic growth, multilayer board hole wall wicking reliability issues, and characterization of reworkable inexpensive underfill. Current research directions include Vertical Cavity Surface Emitting Laser (VCSEL) packaging for low cost optical interconnects, high density vias, and stencil printing with conductive adhesives for direct chip attach. Technology challenges are described first for components. Forecasts and recommendations for research direction are given for components, materials, and packaging.
author_names: Stephen R Bolin

Loren Rideout
title: HIGH DENSITY MICROELECTRONICS PACKAGING ROADMAP FOR SPACE APPLICATIONS
year: 2001

abstract: Severe information latency and power consumption are key technology challenges facing the traditional copper interconnects which impose tremendous constraints to keep up with the performance roadmap driven by the Moore's Law. Converging electronic and photonic integrated circuits (EPIC) on a single chip platform to enable functional diversification emerges as one promising approach which could be realized by taking the advantage of low energy and huge data capacity of optical interconnects. By leveraging on the wealth of CMOS technology know how and infrastructures, the fundamental photonics building blocks constructing the EPIC platform have been successfully developed in this work. We present an overview on the current status of this critical technology development and provide an outlook for the monolithic integration of Si microand nano photonics. It is our belief that a seamless integration of EPIC is poised to become a promising technology to meet the bandwidth and energy requirements of future data communication.
author_names: G Q Lo

Kah-Wee Ang

Tsung-Yang Liow

Qing Fang

Jinsong Zhang

Shiyang Zhu

Junfeng Song

Yong-Zhong Xiong

F F Ren

Mingbin Yu

Dim Lee Kwong
title: (Invited) Silicon Photonics Technologies for Monolithic Electronic Photonic Integrated Circuit
year: 2010

abstract: We report on migrating multiple lane link into an L band VCSEL based WDM system. Experimental validation achieves successful transmission over 10 km of SMF at 4x14Gbps. Inter channel crosstalk penalty is observed to be less than 0.5 dB and a transmission penalty around 1 dB. The power budget margin ranges within 6 dB and 7 dB. (c) 2012 Optical Society of America OCIS codes: (060.0060) Fiber optics and optical communications; (200.4650) Optical interconnects. References and links 1. H. Liu, C. F. Lam, and C. Johnson, "Scaling optical interconnects in datacenter networks opportunities and challenges for WDM," in Proceedings of the 18th Annual Symposium on High Performance Interconnects, 2010, 113 116. 2. A. Vahdat, H. Liu, X. Zhao, and C. Johnson, "The emerging optical data center" in Proceedings of OFC/NOEFC '11, Los Angeles Convention Center, Los Angeles, CA, 2011, OTuH2. 3. C. Kachris and I. Tomkos, "Power consumption evaluation of hybrid WDM PON networks for data centers," in Proceedings of the 16th European Conference on Networks and Optical Communication (NOC) 2011, 118 121. 4. DatacenterDynamics (DCD) white paper, "The 2011 census," (DCD Industry CENSUS, 2011) 5. InfiniBand Trade Association, 2012. http:/www.infinibandta.org/index.php. 6. Fiber Channel Industry Association, 2012.http:/www.fibrechannel.org/roadmaps. 7. H. S. Hamza and J. S. Deogun, "WDM optical interconnects: a balanced design approach," IEEE/ACM Trans. Netw. 15(6) 1565 1578 (2007) 8. J. Cheng, "Topics in VCSEL based high speed WDM optical interconnects," in IEEE Avionics, Fiber Optics and Photonics Technology Conference, 2008, 65 66. 9. M. Haurylau, G. Chen, H. Chen, J. Zhang, N. A. Nelson, D. H. Albonesi, E. G. Friedman, and P. M. Fauchet, "On chip optical interconnect roadmap: challenges and critical directions," IEEE J. Sel. Top. Quantum Electron. 12(6) 1699 1705 (2006) 10. R. Rodes, J. Estaran, B. Li, M. Mueller, J. B. Jensen, T. Grundl, M. Ortsiefer, C. Neumeyr, J. Rosskopf, K. J. Larsen, M. Amann, and I. Tafur Monroy, "100 Gb/s single VCSEL data transmission link," in OFC/NOEFC'12, OSA Technical Digest (Optical Society of America, 2012) paper PDP5D.10. 11. L. Chrostowski, C. H. Chang, R. Stone, and C. J. Chang Hasnain, "Demonstration of long wavelength directly modulated VCSEL transmission using SOAs," IEEE Photon. Technol. Lett. 14(9) 1369 1371 (2002) 12. R. J. Stone, R. F. Nabiev, J. Boucart, W. Yuen, P. Kner, G. S. Li, R. Carico, L. Scheffel, M. Jansen, D. P. Worland, and C. J. Chang Hasnain, "50 km error free 10 Gbit/s WDM transmission using directly modulated long wavelength VCSELs," Electron. Lett. 36(21) 1793 1794 (2000) 13. FP7 European project GigaWam, "Next generation WDM PON enabling gigabit per user data bandwidth" http:/www.gigawam.org/ 14. J. C. Charlier and S. Kruger, "Long wavelength VCSELs ready to benefit 40/100 GbE modules," Lightwave(r) 2012.http:/www.lightwaveonline.com/articles/print/volume 28/issue 6/technology/long wavelength vcseltechnology improves.html. 15. A. Ran, IEEE P802.3bj 100 Gb/s Backplane and Copper Cable TaskForce 14 January 2012. 16. F. Chang, K. Onohara, and T. Mizuochi, "Forward error correction for 100 G transport networks," IEEE Commun. Mag. 48(3) S48 S55 (2010) #177306 $15.00 USD Received 1 Oct 2012; revised 17 Nov 2012; accepted 19 Nov 2012; published 10 Dec 2012 (C) 2012 OSA 17 December 2012 Vol. 20, No. 27 OPTICS EXPRESS 28524
author_names: Jose Manuel Estaran

Roberto Rodes

T T Pham

Markus Ortsiefer

Christian Neumeyr

J Rosskopf

Idelfonso Tafur Monroy
title: Quad 14Gbps L band VCSEL based system for WDM migration of 4 lanes 56 Gbps optical data links
year: 2014

abstract: In this paper we present a computing system that uniquely leverages the bandwidth, density, and latency advantages of silicon photonic interconnects to enable highly compact supercomputerscale systems. We present the details of an optically enabled "macrochip" which is a set of contiguous, optically interconnected chips that deploy wavelength division multiplexed (WDM) enabled by silicon photonics. We describe the system architecture and the WDM point to point network implementation of a "macrochip" providing bisection bandwidth of 10 TBps and discuss system and device level challenges, constraints, and the critical technologies needed to implement this system. We present a roadmap to lowering the energy per bit of a silicon photonic interconnect and highlight recent advances in silicon photonics under the UNIC program that facilitate implementation of a "macrochip" system made of arrayed chips.
author_names: Kannan Raj

John E Cunningham

Ron Ho

Xuezhe Zheng

Herb Schwetman

Pranay Koka

Michael O McCracken

Jon K Lexau

Guoliang Li

Hiren D Thacker

Ivan Shubin

Ying Luo

Jin Yao

Mehdi Asghari

Thierry Pinguet

James G Mitchell

Ashok V Krishnamoorthy
title: "Macrochip" computer systems enabled by silicon photonic interconnects
venue: OPTO
year: 2010