Search query: replacement gate flash memory

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abstract: The invention relates to an integrated circuit (IC) including, a flash memory device region, including a pair of split gate flash memory cells arranged over a semiconductor substrate. The pair of split gate flash memory cells respectively have a control gate (CG) including a polysilicon gate and an overlying silicide layer. A periphery circuit including, one or more high k metal gate (HKMG) transistors are arranged over the semiconductor substrate at a position laterally offset from the flash memory device region. The one or more HKMG transistors have a metal gate electrode with an upper surface that is lower than an upper surface of the silicide layer. A method of manufacturing the IC is also provided. The invention further relates to a structure and method to reduce polysilicon loss from flash memory devices during a replacement gate (RPG) process in integrated circuits.
title: Structure and method to reduce polysilicon loss from flash memory devices during replacement gate (RPG) process in integrated circuits
year: 2015

abstract: The impact of fluorine [F] amount generated from conventional WCVD process and ALD WCVD process on SONOS charge trapping 3D NAND memory are investigated. The damage degree of blocking oxide is an index for fluorine penetration through TiN/Al2O3 then further impacts the voltage break down (VBD) of ONO device characteristics. As compared to conventional WCVD process, ALD WCVD process with laminar 2D sequential growth can provide much better fill in performance at word line, less fluorine trap at grain boundaries, damage free of blocking oxide, minimal stress, and low resistance replacement gate to 3D NAND Flash.
author_names: Tuung Luoh

YuKai Huang

Chimin Chen

Yung-Tai Hung

Lin-Wuu Yang

Tahone Yang

Kuang-Chao Chen
title: Tungsten Gate Replacement Process Optimization in 3D NAND Memory
venue: 2019 Joint International Symposium on e Manufacturing Design Collaboration(eMDC) Semiconductor Manufacturing (ISSM)
year: 2019

abstract: Reduced multilayer graphene (rMLG) is investigated as a charge storage layer (CSL) in conventional floating gate (FG) flash memory structure. A large memory window of 9.4 V at 20 V program/erase and robust 10 years data retention at 150degC is demonstrated. Significant over erase observed in these memory devices signifies hole storage in the rMLG sheets. Fast programming and clear saturation of the program transients observed with the rMLG CSL memory devices suggest reduced ballistic transport in the plane perpendicular to the graphene. Activation energies for programmed and erased state retention losses are calculated as 1.05 and 1.11 eV, respectively. These observations establish the potential of rMLG sheets as a replacement of conventionally used polycrystalline silicon FG.
author_names: Abhishek Mishra

A Janardanan

Manali Khare

Hemen Kalita

Anil Kottantharayil
title: Reduced Multilayer Graphene Oxide Floating Gate Flash Memory With Large Memory Window and Robust Retention Characteristics
venue: IEEE Electron Device Letters
year: 2013

abstract: By storing multibit per cell, multilevel cell (MLC) NAND flash memory achieves high storage capacity, but sacrificing data reliability. Error correction codes, such as Bose Chaudhuri Hocquenghem (BCH) codes, are widely used to ensure data reliability. However, high raw bit error rates induced by interference noises make BCH codes become insufficient to guarantee data reliability. Low density parity check (LDPC) codes are considered as the replacement due to the stronger error correction capability. Nevertheless, directly exploiting LDPC codes introduces a concern about decoding latency because of their iterative decoding in the soft decision process. To develop effective LDPC decoding algorithms, it is necessary to have a more profound understanding on flash failure patterns. This paper first observes the pair bit errors (PBEs) characteristic of MLC NAND flash memory on a real field programmable gate array testing platform, then proposes a PBE aware LDPC (PAL) decoding scheme based upon this observation, in which PBE provides the promotion information for LDPC decoding to reduce decoding latency. Simulation results show that the decoding latency can be reduced by up to 54% compared with the conventional LDPC codes.
author_names: Meng Zhang

Fei Wu

Yajuan Du

Weihua Liu

Changsheng Xie
title: Pair Bit Errors Aware LDPC Decoding in MLC NAND Flash Memory
venue: IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
year: 2019

abstract: Current bottleneck to the development of advanced 28nm and beyond nonvolatile memory is limited by the further scaling of existing flash memory, e.g. floating gate (FG) and SONOS, as a result of the scaling limit of the tunnel oxide as well as the retention issue. On the other hand, there is a strong demand to develop a memory cell which is compatible with the advanced logic HKMG CMOS generations for the embedded applications. In this talk, we will provide a solution on how to develop a replacement of FG and SONOS memories based on the resistive switching. This switching nonvolatile memory, named 1T NVM, comprises a simple MIM structure on the top of the transistor gate while the readout is taken from the transistor Vth or Id, similar to that of flash memory. A bilayer MIM is preferable for quality performance. Experimental results demonstrated that this memory exhibits good endurance, retention, and can solve the sneak path, forming issues in conventional crossbar ReRAM. The architecture of this basic NVM is especially useful for the embedded design in high k metal gate logic CMOS with 28nm and beyond. It has great potential for both NOR and NAND memory, and in particular for embedded applications.
author_names: S Chung
title: Embedded Resistive Switching Non Volatile Memory Technology for 28nm and Beyond High k Metal Gate Generations
venue: 2019 IEEE 11th International Memory Workshop (IMW)
year: 2019

abstract: Summary form only given. In this work we investigated vertical flash memory devices with Al2O3 as control oxide with protein mediated self assembled PbSe nanocrystals used as floating gate. The introduction of high k dielectric as control oxide provides lower voltage/faster operation and hence less power consumption compared with the devices fabricated with SiO2 as control oxide. For appropriate memory operation the dielectric permittivity, conduction/valence band offset and thickness of the high k material have to be properly engineered. Higher permittivity ensures better capacitance and scalability; higher band offset improves retention and programming window. Al2O3 has the potential to be the high k replacement of inter poly oxide due to its relatively high electron and hole barrier heights and high permittivity.
author_names: Fahmida Ferdousi

J Sarkar

S Tang

Davood Shahrjerdi

Tank Akyol

Joseph Patrick Donnelly

Emanuel Tutuc

S K Banerjee
title: Vertical Flash memory devices with Protein assembled Nanocrystal floating gate and A12O3 control oxide
venue: 2008 Device Research Conference
year: 2008

abstract: The nitride based SONOS cell, for its excellent scalability and process simplicity, is the candidate to push the scaling roadmap for FLASH memories beyond the limit imposed on floating gate memories by the electrostatic interference between adjacent cells. The traditional SONOS cell consists of a nitride layer (the storage element) encapsulated by two SiO2 layers which isolate the nitride layer from the Si substrate and the poly Si gate (Poly Si/SiO2/Si3N4/SiO2/c Si) However, the thick tunnel oxide necessary to meet the retention requirements imposes a severe limit on the erase performance because of the erase saturation phenomenon. One possibility to guarantee both the erase and the retention performance is the replacement of the top SiO2 layer with materials of higher dielectric constant (high k dielectric) The presence of a high k dielectric reduces the electric field across the top dielectric, thus decreasing the unwanted parasitic electron injection from the gate during the erase operation. This will allow the cell to erase deep so to meet a basic requirement for Gigabit multilevel NAND memories. The introduction of high k materials in the SONOS stack is unfortunately not straightforward. One problem is the Fermi level pinning at the poly Si/high k interface. Another problem is the morphological changes the high k material undergoes during the device fabrication thermal budget. These changes can modify the k value and affect the band offset between gate and high k material. The results may, in both cases, be the decrease of the barrier for electron injection from the gate and, as a consequence, the deterioration of the erase performance. In this paper we study the effect of gate material and of the morphological transformation associated with the high k post deposition anneal on the erase and the retention behaviour of nitride based cells. Two different high k dielectrics are investigated: Al2O3 (which has already been found to be able to significantly improve the erase operation, guaranteeing at the same time excellent endurance and sufficient bake retention) and HfAlO. We show that both for Al2O3 and HfAlO a trade off exists between erase and retention, higher PDA temperatures being beneficial for erase but detrimental for retention. We also discuss the effect of Fermi level pinning and poly Si depletion on the erase behaviour and compare the erase performances of several PVD and AVD deposited metal gates.
author_names: Antonio Cacciato

Laurent Breuil

Geert Van den Bosch

Olivier Richard

A Rothschild

Arnaud Furnemont

Hugo Bender

Jorge A Kittl

Jan Van Houdt
title: Effect of Top Dielectric Morphology and Gate Material on the Performance of Nitride based FLASH Memory Cells
year: 2008

abstract: In this paper, we have investigated the effect of rare earth materials in tunnel dielectric to improve the trade off between erase speed and retention. Here, rare earth materials have low valence band offset with high permittivity to enhance both erase speed and retention in bandgap engineered silicon oxide nitride oxide silicon (BE SONOS) In addition, we observed higher program speed due to lower conduction band offset as compared to SiO2. Silicate of scandate of rare earth element, GdScSiO (Gd=Gadolinium) is investigated as SiN replacement in tunnel dielectric (SiO2/SiN/SiO2) of BE SONOS. Further, rare earth aluminates, GdAlO and LuAlO (Lu=Lutetium) are used to replace the SiO2 layer in tunnel oxide. Also, gate length is scaled down and we have observed the effect of aforementioned materials in tunnel barrier, however, for the same effective oxide thickness (EOT) We found that the scaling down of gate length has negligible impact on the reliability of the devices. As a consequence, various investigated tunnel oxide stacks possess good memory characteristics with a negligible charge loss (at 25 degC) after a period of ten years and a considerable charge loss at an elevated temperature of 150 degC.
author_names: Mansimran Kaur

Deepika Gupta

Vikas Vijayvargiya

Santosh Kumar Vishvakarma

Vaibhav Neema
title: Characterization of BE SONOS flash memory using rare earth materials in tunnel barrier with improved memory dynamics
venue: 2015 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)
year: 2015

abstract: Abstract Flash memories are now widely used in many portable electronic devices, in embedded systems and are even as replacement for computer hard disks. In flash memory systems, high voltages (up to about 10 V) are indispensable for programming operations. In many cases, however, such programming voltages are not directly available from the supply, and are usually generated by embedded voltage converting or charge pumping circuits. These circuits produce the required programming voltage from available external supplies with voltages in the approximate range of 1 5 V. The power conversion efficiency, the chip size, the voltage regulation, as well as the loading characteristics have been the major concerns for such circuits. The present paper discusses some recently proposed charge pumping circuits for flash memory applications. We focus on the effects of the dynamic gate control, the 4 phase gate boosting and cross coupled configuration for enhancing the performance of the charge pump circuits. Several different charge pumps operated under different working conditions are then investigated in detail.
author_names: Oi-Ying Wong

Hei Wong

Wing-Shan Tam

C W Kok
title: A comparative study of charge pumping circuits for flash memory applications
venue: Microelectron. Reliab.
year: 2012

abstract: This paper describes the novel process/device technology for high speed sub halfmicron flash memories with 0.4 /spl mu/m design rules. Some new structures and operating methods for future flash memories have been proposed. However, the most suitable structure to realize large memory capacity for magnetic disk replacement will be different from that for fast random access speed for EPROM replacement, flash memory embedded logic devices, and other high speed applications. To realize high speed random access operation, conventional NOR type flash memory technology with CHE program and source erase scheme will be the most suitable because of its simple fabrication process, relatively small cell size, sufficiently high read current, and relatively low operation voltages for program and erase procedures. The low voltage program/erase operation results in high performance peripheral transistors. On the other hand, NAND flash EEPROM will be the most suitable for low cost large memory capacity applications. This paper, for the first time, demonstrates the scalability of cell gate length down to 0.4 /spl mu/m for simple stacked gate NOR flash cell.<ETX>
author_names: Seiichi Mori

Eiji Sakagami

Yuichiro Yamaguchi

Eiji Kamiya

Masao Tanimoto

Hiroaki Tsunoda

Kohei Hisatomi

H Egawa

N Arai

Y Hiura

Kuniyoshi Yoshikawa

Koji Hashimoto
title: High speed sub halfmicron flash memory technology with simple stacked gate structure cell
venue: Proceedings of 1994 VLSI Technology Symposium
year: 1994