Search query: Wafer-edge yield engineering in leading-edge DRAM manufacturing

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abstract: Introduction In today's business climate, continuous i n n ova t i o n a n d p ro d u c t i v i t y improvements are essential to the survival of any company. In the semiconductor industry, productivity improvement is generally accomplished using decreased cost per function, economy of scale, increased wafer diameter, process simplification and yield enhancement. The challenges for extreme edge dies increased with the conversion from 200mm to 300mm wafer processing, and will be further increased by the transition to 450mm [3] Increasingly sophisticated and more expensive equipment is required for technology shrinks, making the acquisition of funds for capacity expansion ever more difficult. Process simplification can only be done to a certain extent. Emphasis is therefore placed on fast yield learning, which claims the biggest financial leverage. Due to the narrower process windows at smaller technology nodes, centerto edge uniformity over the wafer is crucial for yield [4] Consequently, wafer edge and bevel induced yield loss were introduced as critical elements to the International Technology Roadmap for Semiconductors (ITRS) in 2005 and are still considered challenging [5, 6] The ITRS also highlights the importance of r im problems in the wafer edge exclusion guideline. A recent repor t descr ibed the economically optimized technology transfer and ramp methodology from development to a mass production site within a global fabrication cluster [7] This paper outlines the wafer edge yield engineering methodology, which was essential for the reported steep production ramp.
author_names: Oguz Yavas

Ernst-christian Richter

Christian Kluthe

Markus Sickmoeller
title: Wafer edge yield engineering in leading edge DRAM manufacturing
year: 2009

abstract: In leading edge patterning processes, overlay is now entangled with CD including OPC residuals and stochastics. This combined effect is a serious challenge for continued shrink and can be characterized with an Edge Placement Error (EPE) budget containing multi domain components: global and local CD, local placement errors, overlay errors, etch biases and OPC. EPE defines process capability and ultimately relates to device yield. Understanding the EPE budget leads to efficient ways to monitor process capability and optimize it using EPE based process control applications. We examine a critical EPE use case on a leading edge DRAM node. We start by constructing and verifying the EPE Budget via densely sampled on product in device local, global CD and Overlay metrology after the etch process step. EPE budget contributors are ranked according to their impact to overall EPE performance and later with simulated EPE performance improvements per component. A cost/benefit analysis is shown to help choose the most HVM friendly solutions.
author_names: Jaeseung Jeong

Jinho Lee

Jinsun Kim

Sun Young Yea

Chan Hwang

Seung Yoon Lee

Jeongjin Lee

Joonsoo Park

Peter Nikolsky

Daniel Park

Antonio Corradi

Hyun-Woo Yu

Sunji Jung

Denis Ovchinnikov

Vadim Timoshkov

Isabel de la Fuente Valentin

Yuxiang Yin

Kaustubh Padhye

Wim Tjibbo Tel

Harm Dillen

Koen Thuijs

Daan Slotboom

Miao Wang

Rhys Su

Marc Kea

Jin-Woo Lee

Yun-a Sung

Sang-Uk Kim

Youngjo Song

James Lee

Oh-Sung Kwon
title: Understanding advanced DRAM edge placement error budget and opportunities for control
venue: Advanced Lithography
year: 2020

abstract: High Performance Computing systems can employ leading edge Heterogeneous Integration (HI) technology including Fan Out Wafer Level Packaging (FOWLP) and high density Redistribution Layers (RDL) to maximize system bandwidth and performance. These More than Moore strategies are growing in importance and present unique challenges that must be overcome to enable mainstream adoption. FOWLP roadmaps for interconnections between SoC (System on Chip) and DRAM (Dynamic Random Access Memory) split die FPGA (Field Programmable Gate Array) and image sensors and SoC are driving RDL scaling and aggressive FOWLP processes are targeting $0.8\ \mu \mathrm{m} design rules. High resolution lithography is required for high density, fine RDL applications and the main lithography challenge is to provide a large Depth of Focus (DoF) to reliably pattern sub micron RDL traces across a large exposure field. This paper details an analysis of candidate optical conditions for sub micron imaging including data demonstrating the DoF performance of an optimized lithography system (stepper) To meet the high resolution requirements of fine RDL processes, Canon developed the FPA 5520iV HR [20iV HR] i line stepper that employs a new projection optical system featuring a maximum 0.24 Numerical Aperture (NA) and a 52 x 34 mm field size. We will present data illustrating that 0.24 NA steppers can provide excellent resolution and pattern fidelity throughout each exposure field across the entire wafer. High density FOWLP wafers can also display extreme die shift, warpage and topography that must be addressed to enable high yield and high productivity processes. Die placement error in FOWLP wafers creates orders of magnitude more alignment error versus traditional silicon wafers and advanced alignment compensation is required to improve overlay matching. Alignment solutions for processing distorted FOWLP wafers include the Grid PA system that automatically corrects the wafer loading position based on die grid sampling, and Enhanced Advanced Global Alignment (EAGA) that allows the stepper to measure and compensate for shift, rotation and intra field magnification errors on a die by die basis. FOWLP reconstituted wafers can also experience large warpage that can decrease productivity and DoF and to combat these challenges, our steppers have been designed to handle wafers with over 5 mm of warpage and are also based on a Front End Of the Line (FEOL) stepper platform that offers die by die tilt and focus measurement and compensation to maximize focus accuracy and DoF. This paper provides an analysis of key lithography challenges facing aggressive FOWLP and fine RDL processes details of stepper technology that helps enable high density integration in mass production. We remain committed to enabling innovation through lithography system performance upgrades and development of original options supporting current and future FOWLP and fine RDL processes.
author_names: Doug Shelton

Ken-ichiro Mori

Yoshio Goto

Hiromi Suda
title: Solutions for Advanced Heterogeneous Integrtion and Fan Out Processes
venue: 2019 International Wafer Level Packaging Conference (IWLPC)
year: 2019

abstract: As device sizes continue to increase on devices at 2x nm design rule and beyond and high wafer stress is worsening due to multi film stacking in the vertical memory process, we observe an increasing trend in edge yield issues worldwide. Wafer edge inspection and metrology become thus critical to drive root cause analysis for improving the yield during a new technology ramp. Nowadays, wafer defectivity correlation to edge is also key for production monitoring, but not without challenges due to the diverse sensitivity demands for the wafer front side, as compared to the wafer edge and back side. In this paper we are able to demonstrate that a cluster inspection platform with the proper balance of sensitivity and throughput is a key enabler for production monitoring. The study required high resolution imaging of the wafer front side, accurate metrology and defect binning capability at the wafer edge, and unique capability to isolate issues that matter in the wafer backside all in a single inspection cluster tool platform. This setup allows for faster time to decisions and eliminates the need to rely on other sources of inspection data. We present several examples of defectivity correlation between the wafer edge and both front and back side, with scanning electron microscope (SEM) examples showing same defect types captured. The root cause for edge defectivity is very often found to be in the crossover of edge bead removal (EBR) lines from successive steps. High quality and accurate EBR metrology is thus essential on many process steps including on backend layers where many EBR lines are found and need to be distinguished. Likewise, anomalies in metrology data of the edge profile can also act as an important indicator of possible defectivity on the wafer. Keywords Wafer Edge, Inspection, Metrology, Defect correlation, Root cause analysis
author_names: Tae-Heon Kim

Jaehyoung Oh
title: Criticality of Wafer Edge Inspection and Metrology Data to All Surface Defectivity Root Cause and Yield Analysis
year: 2016

abstract: A novel 65nm Dynamic Random access memory (DRAM) cell, namely capacitor less RectFET based DRAM cell (CLRDC) is explored in silicon on insulator (SoI) wafer for embedded DRAM (eDRAM) for system on chip (SoC) applications with Rectangular FET (RectFET) as its pass transistor (PT) This CLRDC exploits its parasitic surround buried oxide capacitance (SBC) of SoI wafer around RectFET (source) for realizing its 'charge storage capacitance (Cs) For Cs=30fF (femtoFarad) target, it's found to need an area factor of 4.3um2 with 5nm thick SoI buried oxide. This SoI wafer is explored to yield a capacitance density Cbuox=6.91 fF/um2. The DC parameters of the PT are found to be very sensitive to process anneal temperature (Ta) and so are its DC characteristics too. A 2% increase in the Ta from a nominal 1000oC has resulted in an increase of 30% and 1.1% in the RectFET's leakage (Idsat off=I off) and on state (Idsat on=I on) currents respectively. The CLRDC cell transfer ratio T is also found to be a function of small signal frequency (f) Ta, and source/drain bias voltages Vs/Vd, respectively. And finally the retention characteristics of this CLRDC is again found to be a function of I off and I on currents of RectFET, when studied at RectFET's (drain) supply voltage VDD=1.2V.
author_names: G Malleshaiah

H C Srinivasaiah
title: A Novel DRAM Cell Structure with Parasitic Storage Capacitance for SoCs on SoI Wafer in 65nm Planar MOS Technology
year: 2018

abstract: This article discusses the transition of a form of nanoimprint lithography technology, known as Jet and Flash Imprint Lithography (J FIL) from research to a commercial fabrication infrastructure for leading edge semiconductor integrated circuits (ICs) Leading edge semiconductor lithography has some of the most aggressive technology requirements, and has been a key driver in the 50 year history of semiconductor scaling. Introducing a new, disruptive capability into this arena is therefore a case study in a "high risk high reward" opportunity. This article first discusses relevant literature in nanopatterning including advanced lithography options that have been explored by the IC fabrication industry, novel research ideas being explored, and literature in nanoimprint lithography. The article then focuses on the J FIL process, and the interdisciplinary nature of risk, involving nanoscale precision systems, mechanics, materials, material delivery systems, contamination control, and process engineering. Next, the article discusses the strategic decisions that were made in the early phases of the project including: (i) choosing a step and repeat process approach; (ii) identifying the first target IC market for J FIL; (iii) defining the product scope and the appropriate collaborations to share the risk reward landscape; and (iv) properly leveraging existing infrastructure, including minimizing disruption to the widely accepted practices in photolithography. Finally, the paper discusses the commercial J FIL stepper system and associated infrastructure, and the resulting advances in the key lithographic process metrics such as critical dimension control, overlay, throughput, process defects, and electrical yield over the past 5 years. This article concludes with the current state of the art in J FIL technology for IC fabrication, including description of the high volume manufacturing stepper tools created for advanced memory manufacturing.
author_names: S V Sreenivasan
title: Nanoimprint lithography steppers for volume fabrication of leading edge semiconductor integrated circuits
venue: Microsystems nanoengineering
year: 2017

abstract: Single crystal silicon has played the fundamental role in electronic industry since the second half of the 20th century and still remains the most widely used material. Electronic devices and integrated circuits are fabricated on single crystal silicon wafers which are produced from silicon crystals grown primarily by the Czochralski (CZ) technique. Various defects are formed in the growing crystal as well as in the wafers during their processing. This chapter deals with the topic of engineering of crystal defects in the technology of manufacturing silicon single crystals and silicon wafers for the electronic industry. A basic overview of crystal defects found in semiconductor grade silicon is provided and mechanisms of their formation are introduced. The impact of crystal defects on the manufacturing and performance of electronic devices is outlined and some of the methods of defect analyses are described. Finally, the most important methods for control of defect formation are summarized.
author_names: Lukas Valek

Jan Sik
title: Defect Engineering During Czochralski Crystal Growth and Silicon Wafer Manufacturing
year: 2012

abstract: Cutting edge high performance systems demand larger and denser processors, but future lithographic nodes are expected to introduce higher manufacturing costs and yield challenges. Die level integration technologies like passive interposer based 2.5D have demonstrated the potential for cost reductions through die partitioning and yield improvement, but system performance and scalability may be impacted. Alternatively, active interposer technology, the intersection of 3D and 2.5D methodologies, can provide higher performance interconnect networks to integrate chiplets, but the active interposer die is itself subject to cost and yield concerns. In this work, we perform a cost and performance comparison between traditional monolithic 2D SoCs, 2.5D passive interposers, and 2.5D/3D active interposers to demonstrate the trade offs between the interposer types for current and future high performance systems. This work introduces a multi die core binning cost model to demonstrate the yield improvements from interposer based die partitioning of large multi core processors. The relative cost and performance scaling trade offs of passive and active interposer dies are then compared for the target systems, demonstrating that both methodologies can indeed provide cost effective integration for different system requirements. Finally, this work demonstrates how the extra "prepaid" silicon area of the interposers can be leveraged for fault tolerance to improve yield and cost effectiveness. In summary, this work concludes that both active and passive interposers can cost effectively improve the functional and parametric yield of high performance systems, together providing a cost versus performance space to meet a range of design requirements.
author_names: Dylan Stow

Yuan Xie

Taniya Siddiqua

Gabriel H Loh
title: Cost effective design of scalable high performance systems using active and passive interposers
venue: 2017 IEEE/ACM International Conference on Computer Aided Design (ICCAD)
year: 2017

abstract: Semiconductor industry has increasingly resorted to strain as a means of realizing the required node to node transistor performance improvements. Straining silicon fundamentally changes the mechanical, electrical (band structure and mobility) and chemical (diffusion and activation) properties. As silicon is strained and subjected to high temperature thermal processing, it undergoes mechanical deformations that create defects, which may significantly limit yield. Engineers have to manipulate these properties of silicon to balance the performance gains against defect generation. This paper will elucidate the current understanding and ongoing published efforts on all these critical properties in bulk strained silicon. The manifestation of these properties in CMOS transistor performance and designs that successfully harness strain is reviewed in the last section. Current manufacturable strained silicon technologies are reviewed with particular emphasis on scalability. A detailed case study on recessed silicon germanium transistors illustrates the application of the fundamentals to optimal transistor design.
author_names: Periannan Chidambaram

C Bowen

S Chakravarthi

Charles F Machala

R Wise
title: Fundamentals of silicon material properties for successful exploitation of strain engineering in modern CMOS manufacturing
venue: IEEE Transactions on Electron Devices
year: 2006

abstract: Moore's law in the semiconductor industry came to mean regular, predictable introductions of new manufacturing technology that enabled denser electronics. Adoption of new manufacturing technology, and its effect on silicon wafer processing costs, determined how rapidly transistor manufacturing costs declined. In recent years, both cost decline rates and other economically valuable technical benefits flowing from use of the newest chip making technology seem to have substantially diminished.
author_names: Kenneth Flamm
title: Has Moore's Law Been Repealed? An Economist's Perspective
venue: Computing in Science Engineering
year: 2017