Search query: On chip–package stress interaction

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abstract: In this paper, the interaction between chip and package is investigated. A series of experiments are conducted to investigate the effect of the package type on occurrence of passivation cracks in IC structures. Virtual prototyping is used to generate more accurate and efficient stress design rules for IC backend structures, in combination with packaging processes and geometry. The addressed failure mode of passivation cracks is found to depend on the package type or family: for exposed pad packages this failure mode is easier to occur. It is demonstrated that for successful development of IC backend structures and processes, it is essential to take into account the influence of the package in the earlier phase of IC backend development. The so called integral design rules, accounting for all the major loading sources and history of the complete product creation process has to be used for the development of new generation semiconductors devices.
author_names: Willem D van Driel

Dao-Guo Yang

G Q Zhang
title: On chip package stress interaction
venue: Microelectron. Reliab.
year: 2008

abstract: In this paper, CPI (chip package interaction) reliability of WLP (wafer level package) was investigated. PBO (Polybenzoxazole) based RDL (redistribution layer) structure was the primary focus. Firstly, the stress distribution for PBO structures was studied by simulation. Secondly, two types of the chip with different PBO structures completed the accelerating experiments. Based on our investigation, the results of CPI reliability tests are coincident with the simulation data. It can be applied to the early prediction for the risk level of CPI reliability. Additionally, failure mechanisms were figured out for different PBO structures. Design A has the potential risk to suffer corrosion damage owing to exposed SR (seal ring) and CAS (crack stop) Design B has a four times failure rate in THT (Temperature and Humidity Test) which related to hotspots around SR. These results suggest that protecting SR and relieving hotspots effect will effectively enhance CPI reliability performance of WLP.
author_names: Chong Qin

Ying Li

Haiyang Mao
title: Effect of Different PBO Based RDL Structures on Chip Package Interaction Reliability of Wafer Level Package
venue: IEEE Transactions on Device and Materials Reliability
year: 2020

abstract: Microelectronic components used in automotive applications have to meet very strict reliability requirements. In addition to the mechanical or thermomechanical stresses resulting from manufacturing and application conditions, also chemical processes have to be considered if the systems are exposed to harsh environmental conditions. In these cases, mechanical stresses do not only determine the risk of deformation induced failure and cracking but can also affect the diffusion kinetics of any chemical species, e.g. humidity and corrosive compounds. This paper addresses chip package interaction effects that determine the probability of chip damage by corrosion. The effects of mechanical stress resulting from both the package and from additional external loading on humidity diffusion kinetics, and finally on the resulting failure probability were investigated using finite element analysis (FEA) The simulation results were compared to the experimentally determined failure risk. Further the derived numerical results showed a distinct correlation with the experimentally detected failure risks provoked by different accelerated reliability tests. To validate the correlation between stress supported diffusion and the occurrence of corrosive failures, a specific dedicated experimental test setup was created. The results showed a very good correlation of corrosive failure modes in the active die structures to the mechanical stresses at the critical regions determined from the accompanying FEA package simulation. In addition, scanning electron microscope investigations revealed that the corrosive chip damage started at locations that were also in accordance with the simulation results.
author_names: G Lorenz

Michel Simon-Najasek

A Lindner
title: The Combined Effect of Mechanical Package Stress and Humidity on Chip Corrosion Probability
venue: 2017 IEEE 67th Electronic Components and Technology Conference (ECTC)
year: 2017

abstract: Novel approach for assessment of the effect of temperature and chip package interaction (CPI) induced stress on performance and reliability of ICs with 2.5D/3D architectures is presented. A developed physics based model and a multiphysics EDA tool prototype analyze thermal, and thermomechanical problems during package assembly and chip operation. The tool employs effective anisotropic thermalmechanical properties methodology that accurately represents non uniformity within a die or a layer, and significantly boosts computational performance by avoiding complex geometries. An implemented link between layout analysis tools and the multiphysics thermal mechanical tool enables to perform reliability check within the design flow. The developed stress simulation flow takes into account multiscale stress variations from a package macro scale to an interconnect segment and transistor nano scale. The obtained across chip temperature and stress fields are used for calculating the variations in transistors electrical characteristics, and for analysis of potential cracking locations in the interconnect layers.
author_names: Valeriy Sukharev

Armen Kteyan

Jun-Ho Choy
title: An Accurate Assessment of Chip Package Interaction is a Key Factor for Designing Resilient 3D IC Systems
venue: 2019 International 3D Systems Integration Conference (3DIC)
year: 2019

abstract: Abstract Distinct temperature and process dependent deformation behaviors under packaging temperature cycles are characterized for various packaging materials. Substrate and underfill deformations are described using Maxwell viscoelasticity model. Solder bump deformation is represented by incremental plasticity model. Anisotropic deformation in silicon and orthotropic deformation in substrate are also considered. The material deformation effects on stress evolutions during fabrication and under chip package interaction (CPI) are analyzed for a large package structure. Complex geometries spread over a large range of length scales are simulated using multi level and multiscale sequential submodeling technique. Global package simulations show that substrate orthotropy has a significant impact on the package warpage during the assembly process. Sequential package assembly simulations are performed to examine the residual stresses at package, bump and interconnect scales. The results show that the package mate.
author_names: Aditya P Karmarkar

Xiaopeng Xu

Karim Gamal El-Sayed
title: Temperature and Process Dependent Material Characterization and Multiscale Stress Evolution Analysis for Performance and Reliability Management under Chip Package Interaction
year: 2017

abstract: To enable higher computing power in a single chip, there is demand for increasing die size for high performance applications in advanced nodes. Due to the weak mechanical properties of the low k and ultra low k (ULK) dielectrics in advanced technology nodes, the backend of line (BEOL) stacks are more prone to thermal mechanical failures, resulting in increased semiconductor assembly processes and reliability challenges. This is further exacerbated by the transition of lead (Pb) based solders to Pb free solders (higher melting temperatures) as well as the transition to copper pillar bump (less malleable deformable) These changes bring more package stress which can potentially be transferred to the BEOL stack, increasing chip package interaction (CPI) failure risks. With the increased distance to neutral point (DNP) in large dies, the package to die stress also increases significantly. Therefore, CPI risks in large die applications in advanced nodes are especially challenging. This paper discusses in detail the different CPI reliability challenges of large dies with size up to 25mm x 25mm in flip chip ball grid array (fcBGA) packages in an advanced CMOS technology node. One of the key findings from this study is the impact of kerf width (crack stop to crack stop distance) on CPI performance. While it is well known that narrow kerfs are more subject to dicing damage risks, it is less recognized that wide kerf poses unique CPI challenges. Both narrow and wide kerf were assessed in this work. It is observed that narrow and wide kerf can drive different failure mechanisms. A wide kerf is especially challenging for CPI due to increased energy release rate of cracks if present. By understanding the physics and mechanics of failures, key CPI sensitive parameters can be defined to ensure products are robust to successfully meet various industry standard CPI stress qualification.
author_names: Zhuo-Jie Wu

Charles Carey

Samantha Donavan

Doug Hunt

Patrick Justison

Theo Anemikos

John Cincotta

Hugues C Gagnon

Oswaldo Chacon

Robert Martel

Thomas A Wassick
title: Chip Package Interaction Challenges for Large Die Applications
venue: 2018 IEEE 68th Electronic Components and Technology Conference (ECTC)
year: 2018

abstract: Chip package interaction (CPI) is a key area for achieving robust copper bump interconnection in flip chip packages. Polyimide (PI) has been widely used in electronic package products to provide structural support to protect electronic devices from excessive stress. Passivation crack and LK/ELK delamination are two polyimide related failures in flip chip packages and pose significant challenges to achieving robust CPI design. A 3D finite element model was developed to evaluate the stress impact with the role of polyimide. For the passivation crack, a failure metric, radial passivation stress has been proposed to understand the passivation crack risk. The simulation shows that the in plane radial stress of passivation layer is well correlated with the test results. The location of passivation crack matches the peak radial stress location within the passivation layer. The simulation compared the in plane radial stress between package with and without PI and found the in plane radial stress of passivation of packages with PI was significantly reduced compared with packages without PI layer. The simulation demonstrates PI can provide structural protection against tensile in plane radial stress caused by thermal cooling after chip mass reflow. For ELK delamination, the ELK peel stress is correlated with experimental data. The simulation shows PI opening (PIO) has a big impact on the ELK peel stress. It has been found PIO plays a different role in ELK peel stress due to in plane shear deformation and out of plane thermal expansion. When stress is induced due to in plane shear deformation, smaller PIO and stiffer PI can provide better stress buffer on ELK layers. Larger PIO and stiffer PI can help to reduce the ELK peel stress induced by out of plane deformation. This study presents two failure stress metrics from fracture mechanics perspective and further understand the role of PI in flip chip Cu pillar packages.
author_names: Weiqi Wang

Dingyou Zhang

YangYang Sun

David F Rae

Lily Zhao

Jiantao Zheng

Mark Andre Schwarz

Milind Shah

Ahmer Syed
title: Study of Polyimide in Chip Package Interaction for Flip Chip Cu Pillar Packages
venue: 2018 IEEE 68th Electronic Components and Technology Conference (ECTC)
year: 2018

abstract: In order to address the Chip Package Interaction (CPI) risks associated with advanced silicon packaging, GLOBALFOUNDRIES has developed Finite Element (FE) models to simulate the mechanical stress in the Backend of Line (BEoL) and Far Back End of Line (FBEoL) during the flip chip assembly process and multiple reflow (MR) cycling test. This paper discusses the complexity involved in the CPI mechanical performance and use of various modeling methods to assess and mitigate the CPI failure risk. The paper also highlights the quantitative package model validation against experimental data based on newly developed Cohesive Zone Material (CZM) modeling methodology.
author_names: Kashi Vishwanath Machani

Frank Kuechenmeister

Dirk Breuer

Jens Paul
title: Chip Package Interaction (CPI) Stress Modeling
venue: 2020 21st International Conference on Thermal, Mechanical and Multi Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE)
year: 2020

abstract: Abstract This paper describes major contributing factors to the CPI risk and reveals the mitigation strategy successfully applied jointly by GLOBALFOUNDRIES as the silicon supplier and Qualcomm Technologies, Inc. as the customer responsible for packaging. This strategy involves thermo mechanical modelling, data collection on wafer level using shear test to assess the BEoL stability, Cu Pillar process development and optimization. The qualification of these process changes had been completed and implemented in volume production. The paper also discusses mechanical wafer level and thermo mechanical package modeling approaches. A model has been applied to determine the critical factors on BEoL stress/strain during the flip chip assembly reflow process. These factors include for instance the Cu Pillar bump geometry and stack up. The results of the modelling work were used to set up experiments to further mitigate CPI related failure modes in BEoL on the package level. GLOBALFOUNDRIES and Qualcomm Technologie.
author_names: Frank Kuechenmeister

Dirk Breuer

Holm Geisler

Bjoern Boehme

Kashi Vishwanath Machani

Michael Hecker

Sven Kosgalwies

Jae Kyu Cho

Dongming He

Xuefeng Zhang

Lily Zhao
title: Chip Package Interaction: Understanding of Contributing Factors in Back End of Line (BEoL) Silicon, Cu Pillar Design and Applied Process Improvements
year: 2018

abstract: In this work CPI induced mechanical stress for 3D stacks and 3D interposer packages is studied. The stress built during package assembly has been obtained using finite element modeling (FEM) For the package layout and materials properties chosen for this work, the results shown that the stresses induced during the processing of a 3D stacks and 3D interposer configuration are similar when they are assembled in a Flip Chip Ball Grid Array (fcBGA) package. Furthermore, the interconnection between the different silicon dies assured with the use of mbumps were analyzed with different interconnect densities and configurations. Results shown that stress induced around the mbumps increases by increasing the mbump pitch. Different molding configurations for the fcBGA packages were investigated, including high power (exposed die) and low power (embedded dies) packages. The results showed that exposed die packages present lower out of plane deformation due to a reduction of the epoxy mold compound (EMC) thickness. It is very important to accurately calculate the residual stresses that each processing steps of the assembly induced on the die. Mass reflow and thermo compression bonding process assembly have been investigated. Results showed that solder joint reflow is the bottleneck for mass reflow process assembly, high stress in this step indicate that failures can occur. In this work we showed that low CTE laminate is a good alternative to reduce until 60% stress at flip chip reflow step.
author_names: Melina Lofrano

Mario Gonzalez

Wei Tong Guo

Geert Van der Plas
title: Chip package interaction: A stress analysis on 3D IC's packages
venue: 2015 16th International Conference on Thermal, Mechanical and Multi Physics Simulation and Experiments in Microelectronics and Microsystems
year: 2015