Search query: Wafers and Transistors

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abstract: Metal oxide semiconductor (MOS) devices and integrated circuits can only be realised with semiconductor materials. The substrate material on which they are built plays a very dominant role in their performance and reliability. Aware of this fact, Lilienfeld used copper sulphide as a semiconductor starting material in 1930. Germanium was used during the early 1950s. Until 1960, however, usable MOS transistors could not be manufactured. During the 1960s, the move from germanium to silicon was made in which the transistor channel is a thin conductive layer, which is realised electrically. Table 8.1 shows a comparison of a few germanium (Ge) and silicon (Si) material constants, which clearly shows a few reasons why silicon is used today. For example, the circuits designed in the 65 nm CMOS node use transistors with a channel length close to 60 nm while operating at 1.2 V. This causes an electric field in the channel of 20 V/mm, which is much more than the maximum breakdown field in germanium but still less than that in silicon. Another reason is the widely accepted military spec, which can be met with this material. This spec requires products to function correctly at a maximum operating temperature of 125 degC. The maximum operating temperature of germanium is only 70 degC, while that of silicon is 150 degC. A major reason for these maximum temperatures is that, for many applications, the leakage currents become unacceptably large above these temperatures. Another advantage of silicon is that it is cheap because it is widely available as (beach) sand.
author_names: Harry J M Veendrick
title: Wafers and Transistors
year: 2019

abstract: This letter introduces a type of thin film transistor that uses aligned arrays of thin (submicron) ribbons of single crystal silicon created by lithographic patterning and anisotropic etching of bulk silicon (111) wafers. Devices that incorporate such ribbons printed onto thin plastic substrates show good electrical properties and mechanical flexibility. Effective device mobilities, as evaluated in the linear regime, were as high as 360cm2V 1s 1, and on/off ratios were >103. These results may represent important steps toward a low cost approach to large area, high performance, mechanically flexible electronic systems for structural health monitors, sensors, displays, and other applications.
author_names: Shawn Mack

Matthew A Meitl

Alfred J Baca

Zhengtao Zhu

John A Rogers
title: Mechanically flexible thin film transistors that use ultrathin ribbons of silicon derived from bulk wafers
year: 2006

abstract: This letter presents a simple method for transferring epitaxial sheets of graphene on silicon carbide to other substrates. The graphene was grown on the (0001) face of 6H SiC by thermal annealing at 1550 degC in a hydrogen atmosphere. Transfer was accomplished using a peeling process with a bilayer film of gold/polyimide, to yield graphene with square millimeters of coverage on the target substrate. Raman spectroscopy provided evidence that the transferred material is single layer. Back gated field effect transistors fabricated on oxidized silicon substrates with Cr/Au as source drain electrodes exhibited ambipolar characteristics with hole mobilities of ~100 cm2/V s, and negligible influence of resistance at the contacts.
author_names: Sakulsuk Unarunotai

Yuya Murata

Cesar E Chialvo

Hoon-sik Kim

Scott Maclaren

Nadya Mason

Ivan Petrov

John A Rogers
title: Transfer of graphene layers grown on SiC wafers to other substrates and their integration into field effect transistors
year: 2009

abstract: This letter presents a method to fabricate single crystal silicon wires from (100) wafer and print them onto thin plastic substrates for high performance, mechanically flexible, thin film transistors by dry transfer printing. Electrical measurements indicate excellent performance, with a per ribbon mobility of 580 cm2/V s, subthreshold voltage of 100 mV/dec and on/off ratios >107. The inverter shows good performance and voltage gains of ~2.5 at 3 V supply voltage. In addition, these devices revealed stable performance at bending configuration, an important feature essential for flexible electronic systems.
author_names: Seoung-Ki Lee

Houk Jang

Musarrat Hasan

Jae Bon Koo

Jong-Hyun Ahn
title: Mechanically flexible thin film transistors and logic gates on plastic substrates by use of single crystal silicon wires from bulk wafers
year: 2010

abstract: A new technique is presented for separating the threshold voltage shift of an MOS transistor into shifts due to interface states and trapped oxide charge. Using this technique, the radiation responses of MOS capacitors and transistors fabricated on the same wafer are compared. A good correlation is observed between p substrate capacitors and n channel transistors irradiated at 10 V, as well as between n substrate capacitors and p channel transistors irradiated at 0 V. These correlations were verified for samples having large variations in the amount of radiation induced trapped holes and interface states. An excellent correlation is also observed between n channel capacitors and n substrate transistors irradiated under positive bias. The use of capacitors separately fabricated on control wafers for potential use in process development or monitoring is clearly demonstrated.
author_names: Peter S Winokur

J R Schwank

Paul J McWhorter

Paul V Dressendorfer

Daniel Turpin
title: Correlating the Radiation Response of MOS Capacitors and Transistors
venue: IEEE Transactions on Nuclear Science
year: 1984

abstract: Obtaining a subthreshold swing (SS) below the thermionic limit of 60 mV dec 1 by exploiting the negative capacitance (NC) effect in ferroelectric (FE) materials is a novel effective technique to allow the reduction of the supply voltage and power consumption in field effect transistors (FETs) At the same time, two dimensional layered semiconductors, such as molybdenum disulfide (MoS2) have been shown to be promising candidates to replace silicon MOSFETs in sub 5 nm channel technology nodes. In this paper, we demonstrate NC MoS2 FETs by incorporating a ferroelectric Al doped HfO2 (Al HfO2) a technologically compatible material, in the FET gate stack. Al HfO2 thin films were deposited on Si wafers by atomic layer deposition. Voltage amplification up to 1.25 times was observed in a FE bilayer stack of Al HfO2/HfO2 with a Ni metallic intermediate layer. The minimum SS (SSmin) of the NC MoS2 FET built on the FE bilayer improved to 57 mV dec 1 at room temperature, compared with SSmin 67 mV dec 1 for the MoS2 FET with only HfO2 as a gate dielectric.
author_names: Amirhasan Nourbakhsh

Ahmad Zubair

Sameer Joglekar

Mildred S Dresselhaus

Tomas Palacios
title: Subthreshold swing improvement in MoS2 transistors by the negative capacitance effect in a ferroelectric Al doped HfO2/HfO2 gate dielectric stack.
venue: Nanoscale
year: 2017

abstract: This paper presents an innovative approach for wafer scale transfer of ultrathin silicon chips on flexible substrates. The methodology is demonstrated with various devices (ultrathin chip resistive samples, metal oxide semiconductor (MOS) capacitors and n channel metal oxide semiconductor field effect transistors (MOSFETs) on wafers up to 4' diameter. This is supported by extensive electromechanical characterization and theoretical analysis, including finite element simulation, to evaluate the effect of bending and the critical breaking radius of curvature. The ultrathin chips on polyimide did not break until the radius of curvature of 1.437 mm. In the case of MOS capacitors the measured capacitance increases with increase in bending load. The changes in the transfer and output characteristics of ultrathin MOSFETs closely match with the theoretical model utilizing empirically determined parameters. Overall, the work demonstrates the efficacy of the new methodology presented here for wafer scale transfer of ultrathin chips on flexible substrates. The presented research will be useful for obtaining high performance and compact circuits needed in many futuristic flexible electronics applications such as implantable electronics and flexible displays. Further, it will open new avenues for realizing multilayered multimaterial (foil to foil) integrated bendable electronics.
author_names: William Taube Navaraj

Shoubhik Gupta

Leandro Lorenzelli

Ravinder S Dahiya
title: Wafer Scale Transfer of Ultrathin Silicon Chips on Flexible Substrates for High Performance Bendable Systems
year: 2018

abstract: This paper describes the details of a novel strained transistor architecture which is incorporated into a 90nm logic technology on 300mm wafers. The unique strained PMOS transistor structure features an epitaxially grown strained SiGe film embedded in the source drain regions. Dramatic performance enhancement relative to unstrained devices are reported. These transistors have gate length of 45nm and 50nm for NMOS and PMOS respectively, 1.2nm physical gate oxide and Ni salicide. World record PMOS drive currents of 700/spl mu/A//spl mu/m (high V/sub T/ and 800/spl mu/A//spl mu/m (low V/sub T/ at 1.2V are demonstrated. NMOS devices exercise a highly tensile silicon nitride capping layer to induce tensile strain in the NMOS channel region. High NMOS drive currents of 1.26mA//spl mu/m (high VT) and 1.45mA//spl mu/m (low VT) at 1.2V are reported. The technology is mature and is being ramped into high volume manufacturing to fabricate next generation Pentium/spl reg/ and Intel/spl reg/ Centrino/spl trade/ processor families.
author_names: Tahir Ghani

Mark Armstrong

Chris Auth

M Bost

Peter K Charvat

Glenn A Glass

T Hoffmann

K L Johnson

C Kenyon

J Klaus

B Mcintyre

Kaizad Mistry

Anand Portland Murthy

Justin S Sandford

Mark Silberstein

S Sivakumar

P Smith

Keith Zawadzki

Scott E Thompson

Mark T Bohr
title: A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors
venue: IEEE International Electron Devices Meeting 2003
year: 2003

abstract: This paper presents a subthreshold voltage reference in which the output voltage is scalable depending on the number of stacked PMOS transistors. A key advantage is that its output voltage can be higher than that obtained with conventional low power subthreshold voltage references. The proposed reference uses native NMOS transistors as a current source and develops a reference voltage by stacking one or more PMOS transistors. The temperature coefficient of the reference voltage is compensated by setting the size ratio of the native NMOS and stacked pMOS transistors to cancel temperature dependence of transistor threshold voltage and thermal voltage. Also, the transistor size is determined considering the trade off between diode current between n well and p sub and process variation. Prototype chips are fabricated in a 0.18 <inline formula> <tex math notation="LaTeX"\mu \text{m} /tex math>/inline formula> CMOS process. Measurement results from three wafers show <inline formula> <tex math notation="LaTeX"$3\sigma /tex math>/inline formula> inaccuracy of 1.0% from 0 degC to 100 degC after a single room temperature trim. The proposed voltage reference achieves a line sensitivity of 0.31%/V and a power supply rejection of 41 dB while consuming 35 pW from 1.4 V at room temperature.
author_names: Inhee Lee

Dennis Sylvester

David Blaauw
title: A Subthreshold Voltage Reference With Scalable Output Voltage for Low Power IoT Systems
venue: IEEE Journal of Solid State Circuits
year: 2017

abstract: Ultra thin MoS2 has recently emerged as a promising two dimensional semiconductor for electronic and optoelectronic applications. Here, we report high mobility >60 cm2/Vs at room temperature) field effect transistors that employ unencapsulated single layer MoS2 on oxidized Si wafers with a low level of extrinsic contamination. While charge transport in the sub threshold regime is consistent with a variable range hopping model, monotonically decreasing field effect mobility with increasing temperature suggests band like transport in the linear regime. At temperatures below 100 K, temperature independent mobility is limited by Coulomb scattering, whereas, at temperatures above 100 K, phonon limited mobility decreases as a power law with increasing temperature.
author_names: Deep Jariwala

Vinod K Sangwan

Dattatray J Late

James E Johns

Vinayak P Dravid

Tobin J Marks

Lincoln J Lauhon

Mark C Hersam
title: Band like transport in high mobility unencapsulated single layer MoS 2 transistors
year: 2013