Search query: designing shift register using D flip flop, which stores 2 bit information

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abstract: Quantum dot Cellular Automata (QCA) is emerging nanotechnology that can represent binary information using quantum cells without current flows. It is known as a promising alternative of Complementary Metal Oxide Semiconductor (CMOS) to solve its drawbacks. On the other hand, the shift register is one of the most widely used practical devices in digital systems. Also, QCA has the potential to achieve attractive features than transistor based technology. However, very small scale and Nano fabrication limits impose a hurdle to the design of QCA based circuits and necessitate for fault tolerant analysis is appeared. Therefore, the aim of this paper is to design and simulate an optimized a D flip flop (as the main element of the shift register) based on QCA technology, which is extended to design an optimized 2 bit universal shift register. This paper evaluates the performance of the designed shift register in the presence of the QCA fault. Collected results using QCADesigner tool demonstrate the fault tolerant feature of the proposed design with minimum clocking and area consumption.
author_names: G Prakash

Mehdi Darbandi

Nadia Gafar

Noor Hafidzah Jabarullah

Mohammad Reza Jalali
title: A New Design of 2 Bit Universal Shift Register Using Rotated Majority Gate Based on Quantum Dot Cellular Automata Technology
venue: International Journal of Theoretical Physics
year: 2019

abstract: Quantum dot cellular automata (QCA) represent an alternative technology for implementing various computations and high performance, low power consumption digital circuits at nanoscale. Meanwhile, an universal shift register (USR) with guaranteed free position shift and parallel input and transfer of the stored bit value of the register is an essential element in the design of the circuit. Therefore, we propose an USR circuit based on QCA (QUSR) which can be configured by combining the shift register with a multiplexer (Mux) to select the function of the register. In this study, we propose a 2 to 1 Mux based on the electronic correlations between the cells, and then extend this to a 4 to 1 Mux. We also propose a new D flip flop, and design a shift register by connecting these. Finally, we propose a QUSR with an extremely optimized area and latency, by connecting four 4 to 1 Muxes and a four bit shift register. The proposed QUSR is highly efficient, in terms of the space, time complexity and energy dissipation. All proposed structures are simulated by QCADesigner to demonstrate the clarity of the motion and efficiency. We also measured and compared the energy dissipation in three tunneling levels by QCAPro.
author_names: Jun-Cheol Jeon
title: Low complexity QCA universal shift register design using multiplexer and D flip flop based on electronic correlations
venue: The Journal of Supercomputing
year: 2019

abstract: A novel concept of multi bit flip flops has been proved to be an effective way in processing multiple bits simultaneously. In this paper we propose a way of using multi bit flip flop technique in designing various digital circuits. By sharing the inverters in the flip flops, the total number of inverters can be reduced in a multi bit flip flop. So, here, we have designed a shift register which is an important memory element in digital systems, using 2 bit flip flop. Experimental results reveal that our approach is very efficient, which can be effortlessly incorporated in modern vlsi circuit designs.
author_names: Shefali Sharma

Bipan Kaushal
title: Shift register design using two bit flip flop
venue: 2014 Recent Advances in Engineering and Computational Sciences (RAECS)
year: 2014

abstract: In co planar QCA fabrication, QCA wire crossing is a challenging task as defects appear to be inherent due to two cell types in single layout structure. In this paper, a compact 2:1 multiplexer is presented which occupies a minimum area in QCA technology. This work also showcases a successful implementation and simulation of 4:1 multiplexer, level trigger D flip flop and 4 bit shift register using QCADesigner tool. The 4:1 multiplexer and shift register are more robust and enjoy single layer wire crossing, which requires only one type of cells. The comparison results show superiority of the proposed designs over the previous designs in terms of complexity and delay.
author_names: Trailokya Nath Sasamal

Ashutosh Kumar Singh

Umesh Ghanekar
title: An Efficient Single Layer Crossing Based 4 Bit Shift Register Using QCA
year: 2018

abstract: D flip flops are the basic memory element which is used in many of the applications. Due to increase in demand of portable devices the research in low power has tremendously increased. In this we have discussed about the existing 18T latch and proposed a new 14T flip flop with that latch which has reduced area and power when compared to the existing ones. With this proposed and existing flip flop an asynchronous up/down counter was designed. Power comparison was made between the counters where the asynchronous counter designed using proposed flip flop gives low power consumption when compared to the existing one. Latch is an electronic device which is used to store one bit of data information. When the clock pin at positive edge the output of the D flip flop takes the state of the D input and delays it by one clock cycle. Hence it is known as delay flip flop. Latches are used as buffers but flip flops are used as a registers. Flip flop is the basic memory cell which is used to store the value on the data line. It has an advantage that the output is being synchronized by a lock. Many logic synthesis tools use only D latch and D flip flop. The power consumption and area are the main criterion"s considered while designing it. In today"s world power dissipation became a major thing. In today"s world power dissipation is the major problem as the high power dissipation leads to reduced time of operation, reduced mobility, high efforts of cooling, operational costs and reduced reliability. As the portable devices needs a good battery life time the low power consumption is needed. In digital systems counter circuits are used for many purposes. The number of occurrences of certain events is counted by using the counters and they generate timing intervals for control of various tasks in a system, keep track of time elapsed between specific events, Frequency synthesizers, frequency dividers and so on. Different types of counters are used in a variety of circuits. Here in this paper a 18 transistor D latch was discussed and from which a 14 transistor D flip flop is proposed and both the designs are compared and an asynchronous up/down counter was designed by using the existing and proposed D flip flop. Asynchronous counters are also called ripple counters because of the way the clock pulse ripples it way through the flip flops and they do not have a global clock like synchronous counter. The proposed and conventional designs are simulated and analyzed in MICROWIND at 1 GHz (90 nm CMOS)
author_names: K Miranji

Vidya R Suryanarayana

N Syam Kumar
title: Power Efficient Design of 4 Bit Asynchronous Up Counter Using D Flip Flop
year: 2014

abstract: A shift register is a basic building block in VLSI circuits. Shift registers are commonly used in many applications, such as digital filters, communication receivers and image processing. The architecture of a shift registers is quite simple. An N bit shift register is composed of a series connected N data flip flops. The speed of the flip flop is less important than the area and power consumption. Because there is no circuit between flip flop in the shift register. The smallest flip flop is suitable for the shift register to reduce the area and power consumption. Recently, pulsed latches are replaced flip flops in many applications, because a pulsed latch is much smaller than a flip flop and it cannot be used in a shift register due to the timing problem between pulsed latches. To overcome this problem, multiple non overlap delayed pulsed clock signals are used instead of the conventional single pulsed clock signal. The shift registers use a small number of the pulsed clock signals by grouping the latches to several sub shifter registers and using additional temporary storage latches. A 256_bit shift register using pulsed latches have been fabricated using a 0.18mm CMOS process with VDD=1.8V.The core of the area is 1483mm 2 The power consumption is 1.2mW at a 100MHz clock frequency. The above work was carried out using Microwind software. The multiple non overlap delayed pulsed clock signals saves 66% area and 80% power compared to the conventional shift register with flip flops. Keywords Area efficient, flip flop, pulsed clock, pulsed latch I.INTRODUCTION In digital circuits, a shift register is a cascade of flip flops. Its sharing the same clock, in which the output of each flipflop is connected to the data input of the next flip flop. As resulting in a circuit that shifts by one position the bit array stored in it, shifting in the data present at its input and shifting out the last bit in the array, at each transition of the clock input. A shift register may be multidimensional, such that its data in and stage outputs are themselves bit arrays this is implemented simply by running several shift registers of the same bit length in parallel. These are often configured as serial in parallel out (SIPO) or parallel in serial out (PISO) There are also bidirectional shift registers which allow shifting in both directions. The serial input and last output of a shift register can also be connected to create a circular shift register. In digital design flip flops and latches are basic storage element. Flip flops are timing elements in digital circuits. which have a great impact on speed and power consumption. In VLSI chip design reducing power has become an important consideration of a performance and area. The Shift register is a type of sequential circuit it is mainly used for storage or transfer digital data. An M bit shift register consists of M data flip flops which are connected in series form. The implementation of the Mdata flip flop is less important element to regulate the capability of the total synchronous circuit than the area and power consumption as a result there is no circuit present between flip flops within the register. To reduce the area and power consumption, the smaller flip flop is used for the register. In this flip flops the transistor are more compared to pulsed latches so that the circuit has more switching and power consumption are high. Flip flops are replaced by pulsed latches in several applications, because pulsed latches are smaller than flip flops. The use of multiple non overlap delay pulsed clock signals by the single pulsed clock signals by this design solves the timing problem in pulsed latches [4] The shift register uses a less number of the pulsed clock signals and combine the latches to many sub shift registers and exploitation further temporary storage latches. The data string is presented at Data in, and it is shifted right one stage each time Data Advance is brought high. At each advance, the bit on the far left is shifted into the first flip flop's output. The bit on the far right is shifted out and lost. The data are stored after each flip flop on the 'Q' output, so there are four storage. Hence it is a 4 bit Register. To give an idea of the shifting pattern, imagine that the register holds 0000. As Data in10110000 presents to the register. The left hand column corresponds to the left most flip flop's output pin. So the serial output of the entire register is 10110000. It can be seen that if data were to be continued to input, it would get exactly what was put in, but offset by four Data Advance cycle. This arrangement is the hardware equivalent of a queue. Also at any time, the whole register can be set to zero by bringing the reset (R) pins high. This arrangement performs destructive readout each datum is lost once it has been shifted out of the right most bit. ISSN: 2455 2631 (c) March 2017 IJSDR Volume 2, Issue 3 IJSDR1703015 International Journal of Scientific Development and Research (IJSDR) www.ijsdr.org 89 II. ARCHITECTURE A. Previous work for Shift Register A master slave flip flop using two latches can be replaced by a pulsed latch. It consists of a latch and a pulsed clock signal [6].All pulsed latches share the pulse generation circuit for the pulsed clock signal. The area and power consumption of the pulsed latch is small. The pulsed latch cannot be used in shift register due to timing problem, output signal of the first latch (out1) changes correctly because the input signal of the first latch (in1) is constant during the clock pulse width. But the second latch has an uncertain output signal (out2) because its input signal (out1) changes during the clock pulse width. Fig.1 Schematic of Shift Register with latches and a pulsed clock signal Fig.1a Timing Diagram of Shift Register with latches and a pulsed clock signal One solution for the timing problem is to add delay circuits between latches as shown in Fig.2. The occurrence of the clock pulse is delayed version of the previous latch as shown in Fig.2a.The output signals of the first and second latches (out1 and out2) changes during the clock pulse, but the input signals of the second and third latches become the same as the output signals of the first and second latches after the clock pulse. All latches have constant input signals during the clock pulse and no timing problem occurs between the latches. As a result, the delay circuits cause large area and power overheads. Fig.2 Schematic of Shift Register with latches, delay circuits and a pulsed clock signal ISSN: 2455 2631 (c) March 2017 IJSDR Volume 2, Issue 3 IJSDR1703015 International Journal of Scientific Development and Research (IJSDR) www.ijsdr.org 90 Fig.2a Timing Diagram of Shift Register with latches, delay circuits and a pulsed clock signal Another solution is to overcome the timing problem is to use multiple non overlap delayed pulsed clock signals, are generated when a pulsed clock signal goes through delay circuits. Each latch uses a pulsed clock signal which is delayed from the pulsed clock signal used in its next latch. As a result, each latch has a constant input during its clock pulse and no timing problem occurs between latches. This solution also requires many delay circuits. Fig.3 Schematic of Shift Register with latches and delayed pulsed clock signals Fig.3a Timing Diagram of Shift Register with latches and delayed pulsed clock signals The Shift Register is divided into M sub shift registers in order to reduce the number of delayed pulsed clock signals. A 4 bit sub shifter register consists of five latches and it performs shift operations with five non overlapped delayed pulsed clock signals. In the 4 bit sub shift register #1, four latches store 4 bit data (q1 q4) and the last latch stores 1 bit temporary data (T1) which will be stored in the first latch (q5) of the 4 bit sub shift register #2. The area and power consumption of the 256 bit shift ISSN: 2455 2631 (c) March 2017 IJSDR Volume 2, Issue 3 IJSDR1703015 International Journal of Scientific Development and Research (IJSDR) www.ijsdr.org 91 register according to M, if N=256 and M=4 sub module, each single latch consists of 1 bit. So, total number of latches is 320 and 64 sub module. Fig.4 Schematic of Sub shifter Register for 4 bit module The Shift Register is divided into M sub shift registers in order to reduce the number of delayed pulsed clock signals. A 8 bit sub shifter register consists of nine latches and it performs shift operations with nine non overlapped delayed pulsed clock signals. In the 8 bit sub shift register #1, eight latches store 8 bit data (q1 q8) and the last latch stores 1 bit temporary data (T1) which will be stored in the first latch (q9) of the 8 bit sub shift register #2. The area and power consumption of the 256 bit shift register according to M, if N=256 and M=8 sub module, each single latch consists of 1 bit. So, total number of latches is 288 and 32 sub module. So, compare to 4 bit sub module (M=4) area and power gets reduced. Fig.5 Schematic of sub shifter Register for 8 bit module ISSN: 2455 2631 (c) March 2017 IJSDR Volume 2, Issue 3 IJSDR1703015 International Journal of Scientific Development and Research (IJSDR) www.ijsdr.org 92 Fig.6 Schematic of Delayed pulsed clock generator The numbers of latches and clock pulse circuits change according to the word length of the sub shift register (M) M is selected by considering the area, power consumption, speed. The area optimization can be performed as follows, when the circuit areas are normalized with a latch, the area of a latch and a clock pulse circuit are 1 and aA, respectively. The total area becomes aA x (M+1) N (1+1/M) The power optimization is similar to the area optimization. Each latch consumes power for data transition and clock loading. When the circuit powers are normalized with a latch, the power consumption of a latch and a clock pulse circuit are 1 and aP, respect
title: EFFICIENT DESIGN OF SHIFT REGISTER FOR AREA AND POWER REDUCTION USING PULSED LATCH
year: 2017

abstract: One of the novel technologies in the implementation of digital circuits is Quantum Dot Cellular Automata (QCA) nanotechnology. This technology, which has been introduced over two decades ago, can be a great alternative to today's CMOS chips. The main advantages of this technology include low occupation area and ultra low power consumption. This paper presents an effective design and arrangement of one of the methods of pseudo random bit generator which is called linear feedback shift register (LFSR) in the technology of quantum cellular automata. In this research, using the D latch and level to edge converter, a flip flop is designed. The proposed D flip flop and an XOR gate are used to design three new LFSR circuits in QCA technology. The simulation results show that the proposed designs have stable and useful structures in terms of area, latency and complexity. Simulations show that the first proposed 3 bit pseudo random code design has 233 cells, 4 clock delay cycles, and 0.27mm 2 occupied area while the second proposed 3 bit design has 175 cells, 4 clock delay cycles, and 0.23 mm 2 occupied area. In addition, the third proposed 3 bit LFSR has 188 cells, latency of 4 clock cycle and occupied area of 0.24 mm 2 Power analysis are done for all of the designs.
author_names: Zaman Amirzadeh

M Gholami
title: Analysis and Design of the Pseudo Random Bit Generator in the Technology of Quantum Dot Cellular Automata
venue: International Journal of Theoretical Physics
year: 2019

abstract: QCA (Quantum dot Cellular Automata) is an alternative technology for CMOS that has a low power consumption and high density. QCA extensively supports the new plans in the field of nanotechnology. Applications of QCA technology as an alternative method for CMOS technology in nano scale have a hopeful future. This paper presents the successful design, implementation and simulation of 2 to 1, 4 to 1 and 8 to 1 multiplexer with the minimum area as compared to the previous models in QCA technology. In this paper, by means of 4 to 1 multiplexers including D Flip Flop (D FF) structure in QCA, we present an 8 bit universal shift register. The structure of the 8 bit universal register is extendable to 16 bit, 32 bit and etc. In this paper, the successful simulation of 2 to 1, 4 to 1 and 8 to 1 multiplexers, including D FF and finally 8 bit universal register structure in QCADesigner is provided. The multiplexers and D FF presented in this paper have the minimum complexity, area and delay compared to the previous models. In this paper, the implementation of 8 bit universal shift register, by means of 4 to 1 multiplexers and D FF are presented in QCA technique which have the minimum complexity and delay. In the proposed design of the 8 bit universal shift register, the faults are likely to occur at 2 to 1 multiplexers and D FF. In this article, 2 to 1 multiplexers and D FF are investigated from the cell missing and possible defects. Considering the pipeline being the virtue of QCA, the 8 bit universal shift register has a high speed function. This 8 bit universal shift register may be used in the high speed processors as well as cryptography circuits.
author_names: Reza Sabbaghi-Nadooshan

Moein Kianpour
title: A novel QCA implementation of MUX based universal shift register
year: 2014

abstract: In Integrated circuits a gargantuan portion of chip power is expended by clocking system which comprises of timing elements such as flip flops, latches and clock distribution network. This paper enumerates power efficient design of shift registers using D flip flops along with Clock and Power gating integration. Clock gating and power gating proves to be very effective solutions for reducing dynamic and active leakage power respectively. The two techniques are coupled in such a way that the clock gating information is used to drive the control signal of power gating circuitry. In this paper, an activity driven fine grained clock and power gating is proposed. First, a technique named Optimized Bus Specific Clock Gating (OBSC) is introduced which reduces the problem of gated flip flop selection by appropriate selection of subset of flip flops. Then another technique named Run Time Power Gating (RTPG) is proposed for power gating the combinational logics performing redundant operations. The proposed method is simulated in T Spice. The proposed OBSC and stacking PG method reduces the dynamic and leakage power while compare with existing CG and PG method.
author_names: T

B G
title: Designing Analysis of Flip Flops using OBSC and RTPG Integration for Efficient Low Power
year: 2014

abstract: In the modern information society, security techniques (cryptography, authentication) are very important when we exchange secret/private information. In our laboratory, block cipher systems using nonlinear feedback shift register (NFSR) have been proposed and their performance has been evaluated. The NFSR is one of pseudorandom number generators, which is composed of D flip flops and a combinational logic circuit. In this paper, we improve the NFSR based 64 bit block cipher systems with ring structure for security enhancement.
author_names: Toshihiro Ichiki

Akio Tsuneda
title: Study on Security Enhancement of 64 Bit NFSR based Block Cipher Systems with Ring Structure
venue: 2018 International Conference on Information and Communication Technology Convergence (ICTC)
year: 2018