Search query: Inspection in automobike manufacturing

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abstract: As the semiconductor industry advances to ever smaller nodes with finer feature sizes and more complex mask designs, reticle quality and reticle defects continue to be a top mask yield risk. The primary reticle defect quality requirement is defined as "no reticle defects causing 10% or larger CD error on wafer" Beginning at around the 7 nm Logic node, EUV lithography will start pilot production in several leading fabs. EUV masks stress reticle defectivity requirements for mask shops even more than optical masks due to the larger printing impact from a similar size defect on the mask, and the greater cost and longer cycle time for EUV masks. In a mask shop, generally there are three use cases for a blank inspection system, which are used to monitor and improve mask defectivity; 1) Inspecting process monitor masks, which are used to partition the mask process and identify defect excursions, 2) inspecting 'witness' blanks, which are used to measure and control defectivity in each process tool chamber and 3) inspecting incoming mask blanks to ensure defect free starting materials for advanced optical and EUV reticles. Traditionally, mask shops have been using bright field confocal technology to perform these tasks. However, due to more stringent defect requirements and the flexibility necessary to support these varied use cases, the industry requires a new approach to drive yield improvements in mask manufacturing. In this paper, we report on the introduction of a new system that provides superior sensitivity, with very high throughput and the flexibility to adapt to many different use cases in a production environment.
author_names: Gregg Inderhees

Bill Kalsbeck

Alexander Tan

Paul D H Chung

Jiuk Hur

Eric Kwon

Min Choo

Wonil Cho

Chan-Uk Jeon

Ilyong Jang

In-Yong Kang

Jeonghun Seo

Suein Son
title: Improving mask yield by implementing an advanced mask blank inspection system
venue: Photomask Technology
year: 2018

abstract: EUV lithography has been delayed due to well known issues such as source power, debris, pellicle, etc. for high volume manufacturing. For this reason, conventional optical lithography has been developed to cover more generations with various kinds of Resolution Enhancement Techniques (RETs) and new process technology like Multiple Patterning Technology (MPT) Presently, industry lithographers have been adopting two similar techniques of the computational OPC scheme such as Inverse Lithography Technology (ILT) and Source Mask Optimization (SMO) [1] Sub 20 nm node masks including these technologies are very difficult to fabricate due to many small features which are near the limits of mask patterning process. Therefore, these masks require the unseen level of difficulty for inspection. In other words, from the viewpoint of mask inspection, it is very challenging to maintain maximum sensitivities on main features and minimum detection rates on the Sub Resolution Assist Features (SRAFs) This paper describes the proper technique as the alternative solution to overcome these critical issues with Aerial Imaging (AI) inspection and High Resolution (HR) imaging inspection.
author_names: Sang Hoon Han

Hong Yul Jung

Sun Pyo Lee

In-Yong Kang

Gi-sung Yoon

Dong-Hoon Chung

Chan-Uk Jeon

Yulia Brand

Yair Eran

Yoad Bar-Shean

Alexander Chereshnya

Chung ki Lyu
title: Study of high sensitivity DUV inspection for sub 20nm devices with complex OPCs
venue: Photomask Technology
year: 2014

abstract: The availability of defect free masks remains one of the key challenges for inserting extreme ultraviolet lithography (EUVL) into high volume manufacturing, yet little data is available for understanding native defects on real masks. In this paper, a full field EUV mask is fabricated to investigate the printability of various defects on the mask. The printability of defects and identification of their source from mask fabrication to handling were studied using wafer inspection. The printable blank defect density excluding particles and patterns is 0.63/cm2. Mask inspection is shown to have better sensitivity than wafer inspection. The sensitivity of wafer inspection must be improved using through focus analysis and a different wafer stack.
author_names: Sungmin Huh

Liping Ren

David Chan

Stefan Wurm

Kenneth A Goldberg

Iacopo Mochi

Toshio Nakajima

M Kishimoto

Byungsup Ahn

In-Yong Kang

Joo-on Park

Kyoungyong Cho

Sang-in Han

Thomas Laursen
title: A study of defects on EUV masks using blank inspection, patterned mask inspection, and wafer inspection
venue: Advanced Lithography
year: 2010

abstract: The ITER first wall (FW) includes beryllium armor tiles joined to a CuCrZr heat sink. The FWs are one of the critical components in an ITER machine with a surface heat flux of 4.7 MW/m2 or above. The small scale mockup shall be a part of the qualification tests and used to validate the performance of the dominant manufacturing technologies before the production of larger scale components, and this mockup shall be equipped with a hypervapotron heat sink and manufacturing processes developed for a semiprototype design. The small scale mockup includes 48 beryllium armor tiles (12 mm x 12 mm) capable of withstanding the specified heat flux values. The tile thickness shall be 6 mm to minimize the beryllium surface temperature and evaporation under high thermal loads. The detailed fabrication process of semiprototype small scale mockups was developed for a qualification test in Korea. For the CuCrZr and stainless steel, the canned materials are processed into an hot isostatic pressing (HIP) device. In the case of beryllium to CuCrZr joining, the HIP was conducted at 580degC and 100 MPa. For nondestructive tests of the fabricated semiprototypes, visual and dimension inspections were performed whenever needed during the fabrication process, and ultrasonic tests were performed using ultrasonic probes. Destructive tests for the qualification semiprototype were performed on a small scale mockup, which was fabricated together with semiprototypes. The Korea heat load test facility using an electron beam system was constructed with an electron gun (maximum electric power of 800 kW) for a high heat flux application with a 300 kW high voltage power supply and maximum accelerating voltage of 60 kV. This facility was operated to evaluate the performance test of plasma facing components. A cyclic heat flux test will be performed to evaluate the ITER qualification program.
author_names: Suk-Kwon Kim

Hyung Gon Jin

Kyu In Shin

Bo Guen Choi

Eo Hwak Lee

Jae Sung Yoon

Yang-Il Jung

Dong Won Lee

Duck-Hoi Kim
title: Manufacturing and Examination for ITER Blanket First Wall Small Scale Mockups With KoHLT EB in Korea
venue: IEEE Transactions on Plasma Science
year: 2014

abstract: ABSTRACT Perfluorinated compounds (PFCs) are used in manufacturing food contact materials, including non stick cookware coatings and oil and moisture resistant paper coatings. The chemical stability of PFCs poses an issue for human safety, as they do not degrade well naturally and hence may accumulate in the body. In terms of food safety, since dietary intake is thought to be a major source of exposure to PFCs, it is necessary to assess the migration of PFCs from food packaging articles to food under typical cooking and storage conditions. An analytical method was developed for assessing the migration of 16 PFCs from food contact materials to food simulants using liquid chromatography tandem mass spectrometry. The applicability of the method for regular inspection was assessed by monitoring 312 samples. Based on the results of the exposure assessment, all food contact materials deemed to be safe for use, which evaluated migrated concentrations and dietary food intake.
author_names: Heeju Choi

In-Ae Bae

Jae Chun Choi

Se-Jong Park

MeeKyung Kim
title: Perfluorinated compounds in food simulants after migration from fluorocarbon resin coated frying pans, baking utensils, and non stick baking papers on the Korean market
venue: Food additives contaminants. Part B, Surveillance
year: 2018

abstract: In semiconductor manufacturing processes, monitoring the quality of wafers is one of the most important steps to quickly detect process faults and significantly reduce yield loss. Fail bit maps (FBMs) represent the failed cell count during wafer functional tests and have been popularly used as one of the diagnosis tools in semiconductor manufacturing for process monitoring, root cause analysis, and yield improvements. However, the visual inspection process is costly and time consuming. Therefore, this paper proposes an automated classification procedure for failure patterns on FBMs in dynamic random access memory (DRAM) wafers. The novel matrix factorization approach, called regularized singular value decomposition, is proposed to decompose binarized FBMs into several eigen images to extract features that can provide the characteristics of the failure patterns on FBMs. By using the extracted features, k nearest neighbor classifier is employed to classify feature patterns on FBMs into single bit failure maps and non single bit failure ones. The proposed procedure is tested on real life DRAM wafer data set provided by a semiconductor manufacturing industry, and promising results have been obtained for the automatic classification of single bit and non single bit failure maps.
author_names: Byung-Hoon Kim

Young-Seon Jeong

Seung Hoon Tong

In-Kap Chang

Myong-Kee Jeongyoung
title: A Regularized Singular Value Decomposition Based Approach for Failure Pattern Classification on Fail Bit Map in a DRAM Wafer
venue: IEEE Transactions on Semiconductor Manufacturing
year: 2015

abstract: The objective of this paper is to experimentally validate the previously proposed diffuse ultrasonic technique for measuring crack depth in concrete structures. The validation ultrasonic measurements are performed on real cracks that are formed in full scale reinforced concrete beams. Three reinforced concrete beams are designed and manufactured, and then placed under four point bending to create vertical cracks on the top surface of the beams. Diffuse ultrasonic measurements are conducted on these cracks using the procedure and instrumentation developed in the previous research. The measured crack depth results are compared with the results of side surface visual inspection and direct stereo microscopy measurements on cores extracted from the cracked areas. In all cases considered, the crack depths measured by the diffuse ultrasonic method appear to deviate by about 1 cm when compared to those of the core results. The possible causes of this deviation are discussed. However, the overall results show that the diffuse ultrasonic method provides consistent and reasonably accurate crack depth measurement in concrete beams.
author_names: Chi-Won In

Kevin Arne

Jin-Yeon Kim

Kimberly E Kurtis

Laurence J Jacobs
title: Estimation of Crack Depth in Concrete Using Diffuse Ultrasound: Validation in Cracked Concrete Beams
year: 2016

abstract: The availability of defect free masks remains one of the key challenges for inserting extreme ultraviolet lithography (EUVL) into high volume manufacturing. Recently both blank suppliers achieved 1 digit number of defects at 60nm in size using their M1350s. In this paper, a full field EUV mask with Teron 61X blank inspection is fabricated to see the printability of various defects on the blank using NXE 3100. Minimum printable blank defect size is 23nm in SEVD using real blank defect. Current defect level on blank with Teron 61X Phasur has been up to 70 in 132 X 132mm2. More defect reduction as well as advanced blank inspection tools to capture all printable defects should be prepared for HVM. 3.6X reduction of blank defects per year is required to achieve the requirement of HVM in the application of memory device with EUVL. Furthermore, blank defect mitigation and compensational repair techniques during mask process needs to be developed to achieve printable defect free on the wafer.
author_names: Sungmin Huh

In-Yong Kang

Chang Young Jeong

Jihoon Na

Dong Ryul Lee

Hwan-seok Seo

Seong-Sue Kim

Chan-Uk Jeon

Jonggul Doh

Gregg Inderhees

Jinho Ahn
title: Printability and inspectability of defects on EUV blank for 2xnm hp HVM application
venue: Advanced Lithography
year: 2012

abstract: The availability of defect free masks remains one of the key challenges for inserting extreme ultraviolet lithography (EUVL) into high volume manufacturing, yet little data is available for understanding native defects on real masks. In this paper, a full field EUV mask is fabricated to see the printability of various defects on the mask. Programmed pit defect shows that minimum printable size of pits could be 17 nm of SEVD from the AIT. However 23.1nm in SEVD is printable from the EUV ADT. Defect printability and identification of its source along from blank fabrication to mask fabrication were studied using various inspection tools. Capture ratio of smallest printable defects was improved to 80% using optimized stack of metrical on wafer and state of art wafer inspection tool. Requirement of defect mitigation technology using fiducial mark are defined.
author_names: Sungmin Huh

In-Yong Kang

Sang-Hyun Kim

Hwan-seok Seo

Dongwan Kim

Joo-on Park

Seong-Sue Kim

Han-Ku Cho

Kenneth A Goldberg

Iacopo Mochi

Tsutomu Shoki

Gregg Inderhees
title: Printability and inspectability of defects on the EUV mask for sub 32nm half pitch HVM application
venue: Advanced Lithography
year: 2011

abstract: The computational lithography such as inverse lithography technique (ILT) or source mask optimization (SMO) is considered as the necessary technique for the extremely low k1 lithography process of sub 20nm node. The ideal curvilinear mask design for computational lithography gives the impacts and requires many changes on the photomask fabrication from mask data preparation to measurement and inspection. In this paper, we present the current status and new requirements for the computational lithography mask in viewpoint of the manufacturability for mass production. The manufacturability of computational lithography mask can be realized by the predictable and manageable patterning quality. Here, we have proposed new data flow for ILT which covers what the preferred target design is for ILT, new verification method, required mask model accuracy, and resolution improvement method. Furthermore, considering acceptable writing time <24 hours) and computation limit on convolution, the current ILT technique is shown to have the limit of application area.
author_names: Jin Choi

In-Yong Kang

Ji Soong Park

In-kyun Shin

Chan-Uk Jeon
title: Manufacturability of computation lithography mask: current limit and requirements for sub 20nm node
venue: Advanced Lithography
year: 2013