Search query: Linearization of Voltage-Controlled Oscillators Using Floating-Gate Transistors

Related papers:

abstract: This brief presents a linearization method for the voltage to current (V to I) stage of voltage controlled oscillators (VCOs) A floating gate transistor is utilized at the VCO's input stage as a low overhead method for V to I linearization. The resulting VCO is a ring oscillator with an extended linear voltage to frequency range. The ring oscillator VCO (RO VCO) has also been included in a VCO based analog to digital converter (VCO ADC) to showcase how the linearization technique can be leveraged to improve system performance. The measured results from the linearized RO VCO are compared to current state of the art designs, and the VCO ADC is compared to a standard architecture. The circuits were fabricated in a standard $0.35~\mu \text{m} complementary metal oxide semiconductor (CMOS) process.
author_names: Steven Andryzcik

David W Graham
title: Linearization of Voltage Controlled Oscillators Using Floating Gate Transistors
venue: IEEE Transactions on Circuits and Systems II: Express Briefs
year: 2021

abstract: This paper investigates the use of the body terminal of MOS transistors to improve the linearity of some key circuits used to implement analog and mixed signal circuits integrated in Fully Depleted Silicon on Insulator (FD SOI) CMOS. This technology allows to increase the body factor with respect to conventional (bulk) CMOS processes. This effect is analyzed in basic analog building blocks such as switches, simple stage transconductors and Voltage Controlled Ring Oscillators (VCROs) Approximated expressions are derived for the nonlinear characteristics and harmonic distortion of some of these circuits. As an application, transistor level simulations of two VCRO based \Sigma \Delta modulators designed in a 28 nm FD SOI CMOS technology are shown in order to demonstrate the benefits of the presented techniques.
author_names: Javad Ahmadi-Farsani

Virginia Zuniga-Gonzalez

Teresa Serrano-Gotarredona

Bernabe Linares-Barranco

Jose M de la Rosa
title: Enhanced Linearity in FD SOI CMOS Body Input Analog Circuits Application to Voltage Controlled Ring Oscillators and Frequency Based SD ADCs
venue: IEEE Transactions on Circuits and Systems I: Regular Papers
year: 2020

abstract: We demonstrate a novel transistor structure comprising three gate electrodes: top gate, floating gate, and bottom gate. The floating gate electrode is located between the top and bottom gates. The tri gate structure enables post fabrication V TH control by sharing the dominance of both the top and bottom gates in the floating gate without affecting the semiconductor layer. V TH is controlled for a wide range of over 3.5 V, and the experimental results of V TH controllability coincide strongly with the theoretical analysis. The capacitance ratio between either the top or bottom gate and the floating gate is investigated, and a linear relation of V TH control is achieved without changing other transistor parameters such as the subthreshold swing, on/off ratio, or carrier mobility.
author_names: Sunghoon Lee

Tomoyuki Yokota

Takao Someya
title: Threshold voltage control for organic thin film transistors using a tri gate structure with capacitive coupling
year: 2017

abstract: Objective: This research paper presents a review on performance comparison of different types of Voltage Controlled Oscillators to analyze power dissipation and frequency response. Methods: Designs from Ring Oscillator, Current Starved VCO, VCO with gates of PMOS transistors grounded, VCO with PMOS transistors as diode connected load, VCO with Source voltage applied to both PMOS and NMOS transistors and VCO with NMOS transistors as diode connected load are designed on 45nm CMOS Technology using Cadence Virtuoso Tool. Findings: The performance of different circuits as Transient response, Frequency Response, Stability, Power has been comparatively analyzed through different simulations. Current Starved VCO is concluded as most linear design. All design procedures, Circuit and simulation results are illustrated.
author_names: Sajotra Deepak

Dhariwal Sandeep

M Ravi Shankar
title: Comparative Analysis of Voltage Controlled Oscillator using CMOS
year: 2016

abstract: This paper reports a new design of CMOS voltage controlled oscillator (VCO) using three transistor XOR gate and inversion mode MOSFET varactor tuning concept. Output frequency in the VCO has been varied by varying the output node capacitance with the use of inversion mode MOSFET tuning and back gate tuning. Further, variation in the output frequency has been obtained with the power supply tuning for different value of back gate voltages. Inversion mode MOSFET tuning has been achieved by varying the source/drain voltage from 0.6 to 2.2 V which provides the frequency variation from 1.630 to 1.232 GHz with power consumption of 296.393 \upmu \hbox {W}$mW for inversion mode MOS varactor width of 5 \upmu \hbox {m}$mm. Results have also been obtained with inversion mode MOS varactor widths of 8 and 10 \upmu \hbox {m}$mm. Output frequency, power consumption and phase noise results have also been reported for the different values of back gate and power supply voltages. A tuning range of 27.8, 32.7 and 34.3% has been achieved with the source/drain tuning for inversion mode MOS varactor width of 5, 8 and 10 \upmu \hbox {m}$mm, respectively. Moreover in power supply tuning the tuning range of approximately 134% has been obtained for different widths of inversion mode MOS varactor. VCO is showing the phase noise of ,97.216$ 97.216 dBc/Hz with an offset of 1 MHz from the carrier. Proposed VCO shows a linear tuning, low power consumption and good phase noise performance.
author_names: M Kumar
title: Design of Linear Low Power Voltage Controlled Oscillator with I MOS Varactor and Back Gate Tuning
venue: Circuits Syst. Signal Process.
year: 2018

abstract: Abstract This paper can be divided into two parts. The first part contains a comprehensive survey on the applications of voltage controlled oscillators and the innovations in their designs. The second part presents a voltage controlled ring oscillator (VCRO) based on using a floating gate metal oxide semiconductor (FGMOS) transistor in its delay element. According to this VCRO, there are no extra elements; instead, the control behavior is included in the delay element itself. The presented VCRO is analyzed quantitatively with the expressions of the oscillation frequency in terms of the control voltage and the average power consumption derived. The presented VCRO has a good linearity over the full range from 0 V to the power supply voltage and doesn't suffer from the need to turn on the MOS transistor. The effects of the process, voltage, and temperature (PVT) variations and the technology scaling on the performance of this VCRO are also investigated. The performance of the presented VCRO is compared with that of other schemes by simulation adopting the Berkeley predictive technology model (BPTM) of the 45 nm CMOS technology with a power supply voltage, VDD, equal to 1 V.
author_names: Sherif M Sharroush
title: A voltage controlled ring oscillator based on an FGMOS transistor
venue: Microelectron. J.
year: 2017

abstract: Abstract A VCO based ADC is a time based ADC architecture that is highly digital with regard to its composition. In this paper, we analyze the performance of an organic voltage controlled oscillator (VCO) employing different delay elements and investigate their suitability for use in a VCO based analog to digital converter (ADC) An equation to calculate the theoretical limit of the resolution of the VCO based ADC from the voltage versus frequency characteristics of the VCO was formulated. Using this equation we analysed various VCO architectures to realize the VCO based ADC. We also investigated the impact of jitter and 1/f noise on the performance of the ADC. We have employed a ring oscillator based VCO in our design. The investigated single ended delay elements were analyzed with respect to the linearity in their voltage versus frequency characteristics. This measure of linearity governs the resolution of the VCO and the VCO being the critical part of a VCO based ADC, determines the maximum possible resolution of the whole VCO based ADC. The resolution of all the investigated delay cells were calculated. Based on these results it was found out that the diode load inverter delay cell is the most promising option to realize the VCO based ADC. For such a VCO based ADC using diode load inverter delay stages, the measured results show that a maximum possible resolution of 5.8 bits can be achieved. In addition to the diode load inverter based VCO, we also measured the VCO circuit using cut off load inverter delay stages. The OTFTs use poly 3 hexylthiophene (P3HT) as the P type semiconductor. Furthermore, the circuits were fabricated in a clean room process that is compatible with printing processes for mass production.
author_names: Ramkumar Ganesan

Jurgen Krumm

Klaus Ludwig

Manfred Glesner
title: Investigation of voltage controlled oscillator circuits using organic thin film transistors (OTFT) for use in VCO based analog to digital converters
year: 2014

abstract: This paper describes the possibility of using an Electrically Programmable Analog Device (EPAD) as a gamma radiation sensor. Zero biased EPAD has the lowest fading and the highest sensitivity in the 300 Gy dose range. Dynamic bias of the control gate during irradiation was presented for the first time; this method achieved higher sensitivity compared to static biased EPADs and better linear dependence. Due to the degradation of the transfer characteristics of EPAD during irradiation, a function of the safe operation area has been found that determines the maximum voltage at the control gate for the desired dose, which will not lead to degradation of the transistor. Using an energy band diagram, it was explained why the zero biased EPAD has higher sensitivity than the static biased EPAD.
author_names: Stefan Ilic

Aleksandar Jevtic

Srboljub Stankovic

Goran S Ristic
title: Floating Gate MOS Transistor with Dynamic Biasing as a Radiation Sensor
venue: Sensors
year: 2020

abstract: A voltage controlled ring oscillator is implemented with double gate complementary transistors where both the n and p channel semiconductors are deposited by inkjet printing. Top gates added to transistors in conventional ring oscillator circuits control not only threshold voltages of the constituent transistors but also the oscillation frequencies of the ring oscillators. The oscillation frequency increases or decreases linearly with applied top gate potential. The field effect transistor materials system that yields such linear behavior has not been previously reported. In this work, we demonstrate details of a material system (gate insulator, p and n channel semiconductors) that results in very linear frequency changes with control gate potential. Our use of a double layer top dielectric consisting of a combination of solution processed P(VDF TrFE) and Al2O3 deposited by atomic layer deposition leads to low operating voltages and near optimal device characteristics from a circuit standpoint. Such functional blocks will enable the realization of printed voltage controlled oscillator based analog to digital converters.
author_names: Bongjun Kim

Jaeyoung Park

Michael L Geier

Mark C Hersam

Ananth Dodabalapur
title: Voltage Controlled Ring Oscillators Based on Inkjet Printed Carbon Nanotubes and Zinc Tin Oxide.
venue: ACS applied materials interfaces
year: 2015

abstract: Voltage controlled ring oscillators (VCROs) are the fundamental module in the field of wireless communication systems. It is basically an amplifier with the positive feedback loop in which frequency is the linear function of voltage. To fulfill low power requirement with less noise perturbation in high speed clock recovery circuits, differential voltage controlled ring oscillator (DVCRO) plays vital role. The proposed circuit is designed in differential topology for even number of stages using active load in cross coupled configuration. By minimizing the amount of noise current during high to low and low to high signal transition noise performance is improved. The frequency of oscillation can be achieved by controlling gate source voltage of control transistors. The major attributes are the linearity, stability and wide tuning range which make system design more efficient and highly attractive. The circuit is implemented using 250 nm, 180 nm and 90 nm CMOS technologies at the supply voltage of 1V and control voltage ranges from 0.01 V to 0.08 V. The circuit operates at 38.9408 GHz frequency at power consumption of 0.02341 mW with optimized phase noise performance of 150.9768 dBm/Hz which is obtained best at 90nm technology.
author_names: Tripti Kackar

Shruti Suman

P K Ghosh
title: Design of improved performance differential voltage controlled ring oscillator
venue: 2016 International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT)
year: 2016