Search query: Metal interconnection of semiconductor device and forming method

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abstract: Ben Fa Ming Gong Kai Liao Yi Chong Ban Dao Ti Qi Jian De Jin Shu Hu Lian Ji Qi Xing Cheng Fang Fa ,Qi Zhong ,Tong Guo Dan Hua Ceng De "Zi Zu Zhi "Gong Neng Bi Mian Guo Shi Ke He Qian Shi Ke ,Yi Fang Zhi Tong Hu Lian Zhong De Duan Lu He Kong Xi De Fa Sheng ,Bing Huo De Heng Ding De Gou Dao Shen Du Gai Fang Fa Bao Gua Yi Xia Bu Zou :Tong Guo Chu Bu Tui Huo Zai Ban Dao Ti Chen Di Shang Xing Cheng Dan Hua Mo ,Ban Dao Ti Chen Di Ju You Di Yi IMDMo He Wu Cha Tou ;Zai Qi Shang Xing Cheng You Dan Hua Mo De Ban Dao Ti Chen Di Shang Chen Ji Di Er IMDMo ;Zai Di Er IMDMo Shang Chen Ji Guang Ke Xiao ,Bing Shi Guang Ke Xiao Xing Cheng Tu Yang ;Li Yong Xing Cheng Tu Yang De Guang Ke Xiao Shi Ke Di Er IMDMo ,Yong Yu Xing Cheng Gou Dao ;Li Yong Hua Xue Zhi Pin Qu Chu Dan Hua Mo ;Zai Cong Zhong Qu Chu Liao Dan Hua Wu Mo De Gou Dao Zhong Chen Ji Tong Zu Dang Jin Shu Mo He Tong Jing Chong Ceng ,Ran Hou Chen Ji Tong ;Jiang Qi Shang Chen Ji You Tong De Chen Di Er Ci Tui Huo ;Yi Ji Tong Guo Hua Xue Ji Jie Pao Guang Shi Yi Er Ci Tui Huo De Chen Di Ping Tan Hua
title: Metal interconnection of semiconductor device and forming method
year: 2005

abstract: The present invention relates to a semiconductor device and a method of forming a metal interconnection in the semiconductor device. The method is formed: in the damascene process, typically only formed on the lower metal interconnect overlying the barrier metal layer to prevent metal atoms from the lower to the upper diffusion interconnect dielectric layer. The barrier metal layer covering increased effective dielectric constant between the metal surrounding the lower portion of the lower metal interconnect dielectric layer can be prevented, and to reduce the resistance of the metal interconnection, thereby improving the reliability of the semiconductor device, the speed and or other properties.
title: Method for forming metal interconnection of semiconductor device and semiconductor device
year: 2007

abstract: A method of fabricating semiconductor is disclosed. The method includes a step of depositing a low k dielectric layer, a step of forming a trench in the low dielectric layer, a step of forming a barrier layer in the trench, a step of filling the barrier layer with metal, a planarization step for the metal, and a step of forming a capping layer on the planarized metal. The capping layer comprises at least two layers. It is possible to deposit a thin film with excellent hermetic features for protecting the low k dielectric layer.
title: Method of forming metal interconnection and method of fabricating semiconductor device using the same
year: 2016

abstract: PURPOSE: A method for forming a metal interconnection of a semiconductor device and a contact structure manufactured thereby are provided to selectively form a metal film for interconnection inside a groove in a uniform manner and provide a contact structure manufactured by the metal interconnection forming method. CONSTITUTION: An inter layer dielectric is formed on a semiconductor substrate. A predetermined region of the inter layer dielectric is etched to form an inter layer dielectric pattern(105) having a recessed region. A barrier metal film(109) is formed on a front surface of the resultant on which the inter layer dielectric pattern(105) is formed. A material film(111) is formed on the semiconductor substrate on which the barrier metal film is formed to expose the barrier metal film within the recessed region. An anti nucleation layer(113) is formed by performing a native oxidation to the material film in vacuum condition. A metal film is formed to fill a region surrounded by the exposed barrier metal film. Before the barrier metal film is formed, a resistant metal layer is formed on the front surface of the resultant on which the inter layer dielectric pattern is formed.
author_names: Gil Hyeon Choi

Byeong Hui Kim

Jong Myeong Lee

Sang-In Lee

Hyeon-Seok Lim
title: Method for forming metal interconnection of semiconductor device and contact structure manufactured thereby
year: 2000

abstract: The invention discloses a method for forming a metal structure in a semiconductor device, and a manufacturing method for an interconnection layer. The method for forming the metal structure in the semiconductor device comprises the steps: employing one time or repeated electroplating to forming the metal structure, wherein the additive of electroplate liquid used at one time is an inorganic additive. The method not only prevents organic residues from being generated in a process of forming the metal structure when the electroplate liquid taking the inorganic additive as the additive is employed, and but also can fill a hole generated in the metal structure in the electroplating process, thereby reducing the defects generated in the metal structure, and improving the stability of the semiconductor device.
title: Method for forming metal structure in semiconductor device, and manufacturing method for interconnection layer
year: 2014

abstract: PURPOSE: A method for manufacturing a metal interconnection of a semiconductor device is provided to completely fill a contact hole or groove of a highly integrated semiconductor device, by selectively forming a metal deposition blocking layer exposing the inside of the contact hole or groove of the semiconductor device having a high aspect ratio. CONSTITUTION: An interlayer dielectric is formed on a semiconductor substrate. A predetermined region of the interlayer dielectric is etched to form an interlayer dielectric pattern(105) having a recess region. A barrier metal layer(109) is formed on the resultant structure having the interlayer dielectric pattern. An insulating metal deposition blocking layer(113) exposing the barrier metal layer in the recess region is selectively deposited on the barrier metal layer. A metal plug(117) filling a region surrounded by the exposed barrier metal layer in the recess region is selectively deposited. A metal layer is formed on the entire surface of the semiconductor substrate on which the metal plug is deposited.
title: Method for forming metal interconnection of semiconductor device
year: 1997

abstract: The invention first annealing (anneal under as, more particularly, in the metal wiring formation method of a semiconductor device, the first IMD layer and a tungsten contact holes a nitrogen atmosphere on a semiconductor substrate provided on the method of forming a metal wiring of a semiconductor device by forming a nitride film; The step of claim 2 IMD deposition film on a substrate on which the nitride film is formed; Applying and patterning the second photoresist film 2 IMD thereon; Forming a trench by etching the first 2 IMD film with the patterned photoresist; Removing by using the nitride film Chemical; Depositing a copper barrier metal film and the copper seed layer on said nitride film is removed, the trench and the deposition of copper; The method comprising the second annealing the substrate with the copper deposition; And to a metal wiring method for forming a semiconductor device characterized by made of an step of planarizing the second annealing the substrate in a copper CMP process. Therefore, the metal wiring formation method of a semiconductor device of the present invention is self terminated etch of the nitride film (Self Stop) using Functionality over (Over) etching or under (Under) (Open) the anti etching the copper wiring and the fine space since void) it is possible to prevent the defect such as, to obtain a constant trench structure (trench Dimension) has to obtain a uniform metal wiring resistance effect. Damascene, self etching termination layer, the rapid thermal annealing, copper metal line
title: Method for forming the metal interconnection of semiconductor device
year: 2004

abstract: Technologies related to forming metal lines of a semiconductor device are disclosed. A method of forming metal lines of a semiconductor device may include forming at least one interlayer insulating layer on a semiconductor substrate, forming via holes and trenches in the at least one interlayer insulating layer, forming an anti diffusion film on the via holes and the trenches, depositing a seed Cu layer on the anti diffusion film, after the seed Cu layer is deposited, depositing rhodium (Rh) and forming Cu line on the deposited Rh. The Rh improves an adhesive force between Cu layers and prevents oxide materials or a corrosion phenomenon from occurring on the seed Cu layer. Accordingly, occurrence of delamination in subsequent processes (for example, annealing and CMP) can be prevented or reduced.
title: Semiconductor device and method of forming metal interconnection layer thereof
year: 2008

title: Method for forming metal interconnection of semiconductor device
year: 1996

abstract: PURPOSE: A method for forming a metal interconnection layer of a semiconductor device is provided to prevent formation of a metal oxide layer on a conductive layer in a process of removing a photoresist pattern, and prevent an ashing damage and profile fail of a via hole. CONSTITUTION: A stopper layer is formed on a semiconductor substrate. An insulation layer is formed on the stopper layer. A hard mask is formed on the insulation layer. A first photoresist pattern having a first aperture is formed to expose an upper partial portion of the hard mask. A partial via hole having a first width is formed by etching partially the hard mask and the insulation layer with the use of the first photoresist pattern as a mask. The first photoresist pattern is removed. An organic material layer is coated to fill the partial via hole. A second photoresist pattern having a second aperture is formed on the substrate comprised of the organic layer. The organic layer and hard mask layer are etched by using the second photoresist pattern as a mask and the second photoresist pattern and organic layer are removed. An interconnection region having the second width and a via hole having the first width are formed by etching the insulation layer with the use of the hard mask layer as an etch mask.
title: Method for forming metal interconnection layer of semiconductor device
year: 2002