Search query: Thermal and electrical performance for wafer level package

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abstract: CSP (Chip Size Package) is expected to be widely used in D RDRAM (Direct Rambus DRAM) for its higher electrical performance as well as in PDA (Personal Digital Assistant) applications for its smaller size and lighter weight. Especially wafer level CSP (WL CSP) has received great attention from semiconductor industries because of its minimal electrical parasitic parameter and thermal resistance. In this study, the thermal and electrical performance of WL CSP having a high potential for DRAM applications is compared with that of the current TSOP. The thermal performance of WL CSP was evaluated by means of a thermal model utilizing Finite Element Method (FEM) and Computational Fluid Dynamics (CFD) The results show the excellent thermal performance of WL CSP at the range of 0.5 2.0 W of a dissipation power. The AC/DC thermo electrical performance of 64M SDRAM WL CSP was investigated under various ambient temperatures. The WL CSP showed the excellent thermo electrical performance that its access time was max. 5.5 nsec at 90/spl deg/C at the range of 3.3/spl plusmn/0.3 V of VCC. To evaluate the electrical performance of WL CSP, we designed the three type of WL CSP with a different redistribution layer design. Their RLC parameters and AC/DC characteristics are measured and compared with the simulation result in order to verify the validity of the simulation result. This result shows that there is a good agreement between the simulation and measurement, and the WL CSP has better electrical performance than the TSOP.
author_names: Sang Wook Park

Jae Myun Kim

Hyung Gil Baik

Sang Ha Kim

Joon Ki Hong

Heung Sup Chun
title: Thermal and electrical performance for wafer level package
venue: 2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)
year: 2000

abstract: A novel embedded silicon fan out wafer level packaging (eSiFO) which was proposed by Huatian Technology in 2015 and now in production, has a relatively simple manufacturing process eliminating molding and de bonding process compared to typical fan out process. This paper briefly introduces eSiFO technology at first, and then mainly studies its electrical and thermal performance, as well as RDL reliability. This study finds that eSiFO technology has a good package performance, and can further provide optimal performance for mobile electronics and potential IoT and 5G applications.
author_names: Cheng Chen

Daquan Yu

Lixi Wan
title: Electrical, Thermal and Mechanical Simulation for Embedded Silicon Fan out Wafer Level Packaging
venue: 2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)
year: 2018

abstract: Fan out package has advantages such as higher I/O density, higher electrical performance, ultra thin and low power consumption. However, Fan out package have some issues caused by warpage induced by difference of coefficient of thermal expansion between epoxy mold compound (EMC) and Si die. Therefore, the warpage behavior of the FOWLP component molded with three kinds of EMCs were investigated by using shadow moire method and finite element method analysis. The environmental reliability of fan out package component was evaluated by thermal shock test and temperature humidity test. The warpage behavior of fan out package component changed from convex to concave with increasing the temperature. The warpage of fan out package component molded by EMC with lower CTE was reduced because of smaller CTE mismatch between chip and EMC at room temperature. However, the warpage of FOWLP component molded by EMC with lower modulus was reduced the warpage even though CTE of EMC was higher than others due to stress strain relaxation at 260degC. The electrical resistance of fan out package component increased with increasing aging time and cycles during temperature humidity test and thermal shock test.
author_names: Haksan Jeong

Kwang-Ho Jung

Choong-Jae Lee

Kyung Deuk Min

Seung-Boo Jung
title: Thermomechanical Properties of Fan Out Wafer Level Package Fabricated with Various Epoxy Mold Compound
venue: 2019 22nd European Microelectronics and Packaging Conference Exhibition (EMPC)
year: 2019

abstract: The recent interest of Fan out wafer level packaging technology (FOWLP) comes from such benefits, thin package, board fan out capability, high I/O, good thermal resistance, and electrical performance. However, its application is limited due to the difficulty in the warpage control of FOWLP. In order to control this difficulty, modulating the epoxy molding compound's properties is necessary. In this paper, we introduce our recent progresses in an evaluation tool and its use for tuning EMC properties.
author_names: Kihyeok Kwon

Joo Young Chung

Donghwan Lee

Sang Kyun Kim
title: Wafer warpage control by epoxy molding compounds for wafer level package
venue: 2018 China Semiconductor Technology International Conference (CSTIC)
year: 2018

abstract: Embedded wafer level ball grid array (eWLB) or FO WLP (Fan out wafer level packaging) is investigated as a package for MMICs (Monolithic Microwave Integrated Circuit) for automotive radar applications in the 77GHz range. Special focus is put on the thermo mechanical performance to achieve automotive quality targets. The typical fatigue modes "solder ball fatigue" and "copper fatigue" evolving during thermo mechanical stress like cycling on board will be discussed. Simulation as well as experimental preparation results for typical fatigue levels are given. In addition, several influencing parameters are listed and rated regarding their effectiveness. The theoretical framework why solder ball fatigue is the only failure mode causing electrical failure is provided. The impact of different thermo mechanically driven fatigue modes is discussed. The two important parameters to be considered for the functionality of the Radar system are RF (Radio Frequency) and thermal performance. For elaborating the RF performance with present fatigue modes, the phase shift between different channels and pads is analyzed by full wave EM (Electromagnetic) simulation. It is found that for fatigue levels up to 90% the phase shift stays below specification for single fatigue modes and may approach specification only for an unlikely combination of all 90% fatigue modes. For assessing the thermal performance with present fatigue modes, thermal simulation as well as thermal measurements are used. Assuming 50% degradation in average for all thermal balls, an increase in RTH of up to about 30% is seen. On average for all thermal measurements, the deviation between measurement and simulation is within 1degC.
author_names: Walter Hartner

Markus Fink

Gerhard Haubner

Christian Geissler

Johannes Lodermeyer

Martin Richard Niessner

Francesca Arcioni

Maciej Wojnowski
title: Reliability and Performance of Wafer Level Fan Out Package for Automotive Radar
venue: 2019 International Wafer Level Packaging Conference (IWLPC)
year: 2019

abstract: The 3D package technology has been developed higher performance, higher functionality, smaller and thinner devices for mobile, wearable and IoTs in recent years. Among advanced packaging technologies, advantages of fan out wafer level package (FOWLP) are its higher I/O density, higher electrical performance, ultra thin and low power consumption. However, the FOWLP has some mechanical issues about the warpage caused by different coefficient of thermal expansion(CTE) between the various packaging material constituents. We investigated the warpage behavior of FOWLP component with various chip and EMC thickness. The FOWLP component was fabricated by the mold first process. The 8 x 8 mm2 Si chips (chip thickness: 50, 75 and 100 ?m) were taken placed on the carrier wafer. After that, compression mold (EMC mold thickness: 300 and 460 ?m) was used to fabricate the molded wafer. Redistribution layer (RDL) was fabricated on the molded chip by photolithography. The warpage behavior of the FOWLP component was analyzed from room temperature to 260 degC using shadow moire method. The environmental reliability of FOWLP component were evaluated by temperature humidity bias test and thermal shock test. The warpage property depended on ratio of Si chip to EMC thickness. The warpage of FOWLP component with 300 ?m EMC mold and 100 ?m chip thickness whose ratio of Si chip to EMC thickness is 0.33 is about 100 ?m. However, the warpage of other FOWLP component, ratio of Si chip to mold thickness is less than 0.25, is more than 200 ?m. Electrical resistance of FOWLP component were 1.9~2.6 m? and 1.6~2.2 m? after temperature humidity bias test and thermal shock test, respectively. The electrical resistance of FOWLP component at all sample increased by more than 1.2 times after temperature humidity bias test and thermal shock test. Warpage was affected by the ratio of chip to EMC thickness.
author_names: Haksan Jeong

Woo-Ram Myung

Kwang-Ho Jung

Seung-Boo Jung
title: Thermomechanical Properties of Fan Out Wafer Level Package with Various Chip and Mold Thickness
venue: 2018 IEEE 68th Electronic Components and Technology Conference (ECTC)
year: 2018

abstract: A good solution to meet the need of miniaturization and low cost for micro electronics packaging is wafer level package technology. But thermal mechanical reliability problem which generated from the coefficient of thermal expansion (CTE) mismatch between the chip and the PCB limit the application of larger size wafer level package. To solve this problem, the prototype of compliant package is proposed in International Technology Roadmap for Semiconductors (ITRS) Firstly, a novel compliant bump structure with embedded air gaps proposed by Fraunhofer IZM is introduced. Then the process flow of compliant wafer level package (CWLP) with embedded air gaps is described. The embedded air gaps are fabricated by MEMS sacrificial layer process, which can adapt certain deformation in the direction of Z axis. On the plane X Y, both geometry and size of copper interconnection are optimized and developed, which works as the micro spring to absorb the deformation in the plane X Y. Subsequently,four structures of micro spring, i.e. straight line sharp, S sharp, M sharp and J sharp, are designed and simulated by the application of HFSS and Q3D softwares under the frequency from 1 to 10GHz. Electrical parameters of the package, i.e. resistance, capacitance and inductance, are computed. The electrical parasites of micro spring are evaluated and compared among four structures mentioned above. Further, the SI, such as return loss, insertion loss, near end crosstalk and far end crosstalk are evaluated and compared. The conclusion is that the J sharp micro spring is better than others in comprehensive performance for CWLP. Finally, effects of geometric parameters on electrical parasitic are studied with Ansoft's Q3D for J shape micro spring.
author_names: Jing Liu

Kailin Pan

Jiaopin Wang

Jing Huang
title: Electrical performance analysis of compliant wafer level package (CWLP) with embedded air gaps
venue: 2010 11th International Conference on Electronic Packaging Technology High Density Packaging
year: 2010

abstract: Fan out (FO) packages are widely used in handheld, mobile consumer, and Internet of Things (IoT) devices due to the facility they provide for a greater I/O density and the integration of multiple components in a single package. Various types of FO package are available, including embedded wafer level BGA (eWLB) fully molded (FM) and a flip chip based structure referred to as a fan out chip last package (FOCLP) In this paper, ANSYS simulations are performed to examine the warpage, extreme low $k$ (ELK) interconnect stress and board level solder joint reliability of the various package types. The validity of the simulation model is confirmed by comparing the numerical results for the warpage of the eWLB and FM packages with the experimental observations. Further simulations are then performed to investigate the heat dissipation performance and electrical crosstalk properties of the three packages. Taguchi experiments are conducted to examine the effects of eight control factors [namely, the inclusion (or otherwise) of a backside laminate film, the board thickness, the joint standoff distance, the ball joint diameter, the under bump metallurgy (UBM) diameter, the joint pitch, the die thickness, and the Cu pillar height] on the thermomechanical reliability of the FM package under accelerated thermal cycling testing. Finally, the Taguchi analysis results are used to determine the optimal geometry design of the FM package.
author_names: M K Shih

Chih-Yi Huang

Tsan-Hsien Chen

Chen-Chao Wang

David Tarng
title: Electrical, Thermal, and Mechanical Characterization of eWLB, Fully Molded Fan Out Package, and Fan Out Chip Last Package
venue: IEEE Transactions on Components, Packaging and Manufacturing Technology
year: 2019

abstract: In the current mobile electronics market, there is a great demand of electronics products with better performance, smaller foot print and greater package functionality with a lower manufacturing cost. Smart phones and tablets are some of the portable electronics devices that require more functions, smaller form factor and reduced power consumption requirements [1] To address these requirements, the Multi Chip Fan Out Wafer Level Package (FOWLP) technology promises an alternative technology for high performance and multi die packaging in FOWLP technology [2] In conventional flip chip assembly, the advantages of using Cu pillar and solder micro bumps are mainly because of it allows for fine pitch applications and superior power management in terms of thermal and electrical [3] The major difference in using copper pillar with solder micro bumps is that the solder volume are significantly reduced on each solder bump. Furthermore, the lesser solder volume on the Cu pillar bumps makes it difficult for solder self alignment during solder reflow process [4] Hence it is critical that good chip placement accuracy is needed in the flip chip bonder for good solder interconnect formation especially for our work in the new RDL first FOWLP technology with multiple die and high pin count applications [5] In this paper, we present the chip to wafer assembly for multiple die on the RDL First FOWLP approach. Chip to Wafer assembly is a promising technology for high density package application to overcome the limitation of Wafer to Wafer boding in terms of die stacking process yield and bonding placement accuracy on wafers. Our test vehicle is a large multi chip package of 20x20mm2 fabricated using the RDL First FOWLP approach. There are 2400 I/Os on the FOWLP package. The C2W flip chip process is done to attach the 3 test chips onto the 3 layers RDL film onto the 12 inch glass carrier with sacrificial layer using the mass reflow method. The assembly process was optimized and samples are built to subject to JEDEC Moisture Sensitivity Test Level 3 for reliability assessment.
author_names: Sharon Pei Siang Lim

S C Chong

Mian Zhi Ding

Vempati Srinivasa Rao
title: Development of Chip to Wafer (C2W) bonding process for high density I/Os Fan Out Wafer Level Package (FOWLP)
venue: 2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)
year: 2016

abstract: Fan out wafer level packaging technology (FOWLP) is one of the advanced packages in semiconductor industry. Recently, its interest has been raised due to the benefits such as thin package, board fan out capability, high I/O, substrate less process, integration of passives into structure, good thermal resistance, and electrical performance. Despite these many advantages, FOWLP is reluctant to be applied packaging industries due to the difficulty of controlling wafer warpage. Its broad molding area causes warpage control of FOWLP to be more difficult than other packages. The relationship between molding area and warpage have trade offs, which have to be optimized beforehand in order to ensure successful subsequent processing. In order to control both factors, it is necessary to study the properties of Young's modulus, coefficient of thermal expansion (CTE) glass transition temperature (Tg) and flow ability for wafer level mold compounds of interest. In this paper, our group introduces an evaluation tool based on all above parameters and explains how to optimize warpage of FOWLP based on this tool.
author_names: Kihyeok Kwon

Yoon Kyung Lee

Junghwa Kim

Joo Young Chung

Kyunghag Jung

Yong-Yeop Park

Donghwan Lee

Sang Kyun Kim
title: Compression Molding Encapsulants for Wafer Level Embedded Active Devices: Wafer Warpage Control by Epoxy Molding Compounds
venue: 2017 IEEE 67th Electronic Components and Technology Conference (ECTC)
year: 2017