Search query: Silicon wafer thinning, the singulation process, and die strength

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abstract: In recent years, the realization of the IoT (Internet of Things) society, in which anyone can connect to the network to search for anything at anytime from anywhere, is approaching. For the IoT to progress, semiconductor devices (chips) such as various types of sensors and communication and memory devices, manufactured by forming a circuit on the silicon wafer, are essential. In general, both "thinning" and "minimizing" are required. On the other hand, die strength improvement is also very important for improving the yield of the manufacturing process and enhancing the endurance of the final product. This review explains the die strength of the CMP and DP stress relief wafer thinning processes and the DBG singulation process.
title: Silicon wafer thinning, the singulation process, and die strength
year: 2016

abstract: Abstract In this paper, we have studied the characteristics of silicon dice, singulated using a high power high repetition rate femtosecond laser. The die strength and surface roughness, of the die side walls, are evaluated for different laser parameters such as pulsewidth and repetition rate. Since, the 80 mm thick wafers used in this study were polished on both sides, die edge roughness plays a decisive factor in determining the die strength when compared to backside roughness and wafer thickness as is the case in other studies. Excellent side wall average surface roughness of 0.35 mm is obtained at pulsewidth of 214 fs and repetition rate of 4.33 MHz using an average laser power of 15.5 W. Die strength is measured via the 3 point bending test. Strength reduction, due to die side wall surface defects that are induced through the wafer dicing process, is evaluated through die strength and surface roughness analysis. Die strength of a silicon dice is characterized as the first step in prediction and prevention of die failure during the package assembly, reliability test and working life. Improvement in the die side wall surface roughness is observed with the usage of nitrogen gas assist as compared to that obtained in air.
author_names: Nitin Sudani

Krishnan Venkatakrishnan

Bo Tan
title: Laser singulation of thin wafer: Die strength and surface roughness analysis of 80 mm silicon dice
year: 2009

abstract: Driven by the ever growing desire for more compact electronic devices, the semiconductor industry has moved toward thinner silicon wafers. Simultaneously, the semiconductor industry has introduced new and better materials to facilitate the size shrinking. These factors introduce serious limitation in current saw blade semiconductor wafer dicing technology and needs new processing tools. Although nanosecond laser dicing overcomes most of the issues related to saw blade dicing, the dicing throughput remains below the current industrial requirement. In this paper a novel dual focus mechanism is introduced to increase the throughput of laser wafer dicing. Experimental results proved that dual focus increases the dicing speed, reduces the kerf width, eliminates the debris and enhances the die fracture strength. Cutting strategy and laser parameters, such as back focus power, repetition rate and wavelength, that influence the machining efficiency and quality, were studied in detail. The industrial implement of laser singulation is discussed.
author_names: Krishnan Venkatakrishnan

Bo Tan
title: Thin silicon wafer dicing with a dual focused laser beam
year: 2007

abstract: Current mechanical wafer dicing process adopting diamond grit shows advantages of low cost and high productivity. However, mechanical process for ultra thin wafers would induce residual stress or mechanical damage, which can lead to wafer broken and die cracking. With the development of laser technology, laser precision micromachining has been employed for thin semiconductor wafer singulation, which shows advantages of no chipping, small kerf width, and high throughput over mechanical blade dicing. However, thermal damage to the chip induced by laser ablation results in die strength degradation. For ultra thin chip, low die strength tends to induce die crack in packaging process. Thus, thermal damage to the chip needs to be studied. In this study, first we made a comparison between mechanical blade sawing and laser ablation processes. Die strength and microstructure changes were studied by means of bending test and transmission electron microscope (TEM) analysis, respectively. Die strength results showed that the die strength obtained by laser dicing was far lower than that obtained by blade sawing. TEM analysis demonstrated that formation of microcracks and porosities in laser diced face, caused the die strength degradation. In addition, significant deviation between frontside and backside die strength was found in the laser micromachinned dies. The reason for this deviation was clarified as the defects density difference existing in top and bottom layer of the chip sidewalk Experiments results showed that the die strength obtained by laser dicing can not meet the demand of the packaging process. It tends to crack or fracture in the die attach or wire bonding process. Thus, it is essential to improve the die strength. Thus, in this investigation, etching processes including wet etch and dry etch were attempted to recover the die strength by removing the chip side wall damage. SEM and TEM images indicated that, before etching, the laser diced side walls were with rough surfaces, voids and microcracks. After etching, the surfaces got smooth and most of the voids and microcracks were removed. Chip strength measurement also verified the partial die strength recovery after etching process.
author_names: Jianhua Li

Hyeon Hwang

Eunchul Ahn

Qiang Chen

Pyoung-Wan Kim

Teakhoon Lee

Myeongkee Chung

Taegyeong Chung
title: Laser Dicing and Subsequent Die Strength Enhancement Technologies for Ultra thin Wafer
venue: 2007 Proceedings 57th Electronic Components and Technology Conference
year: 2007

abstract: As semiconductor based devices are manufactured on ever thinner silicon substrates, the required associated die break strength has to increase commensurately to maintain pick yields. In this study, the influence of laser processing parameters on the die break strength in laser dicing of silicon oxide coated silicon wafers and silicon based memory devices is investigated experimentally using ultraviolet lasers spanning a wide range of pulse width, from 400 fs to 150 ns. It is found that the net fluence, an accumulated pulse energy per surface area, is a meaningful process metric for damage induced by heat affect zone to compare lasers processes with a large variety of pulse widths, laser scan speed, average powers, and repetition rates. Optimized process conditions for both nanosecond and femtosecond pulse widths are identified for achieving the highest die break strength in the target devices. The dependence of heat affected zone on pulse width and net fluence during nanosecond laser processing is further.
author_names: D Finn

Zhibin Lin

Jan Kleinert

Michael Darwin

Haibin Zhang
title: Study of die break strength and heat affected zone for laser processing of thin silicon wafers
year: 2015

abstract: Let us have a look at the main spheres for silicon chips: The processors you find in your PCs, memory chips used in nearly every electronic module, the power devices your car is full of and the smart labels found in access cards, tickets and labeling applications which make our daily life easier. For each of these applications the chips are going thin. What is the driving force of this development, why are we going thin? For processors the main advantage of thin substrates is improved heat dissipation. Stacking of memory chips needs also thin silicon. For power devices it is reduction in electrical resistance. For smart cards and related applications the main feature is the flexibility of thin silicon, which makes the IC chip capable of surviving daily use. The question is: what are the mechanical properties after thinning and chip singulation? What are their root causes? We have done investigations to find and evaluate causes of the mechanical damage in thin chips. We begin with a search for the stability necessary for a safe and reliable handling of the chips. We demonstrate the resulting threshold for chip stability and some processes to reach this limit. In a next step we show the influence of chip separation technologies. Influences to the chip side wall can result in mechanical damage or change stability. Our paper shows results regarding back side hardness and also the differences in mechanical properties between blank chips and processed devices. We present results of our investigations regarding dicing quality and influences to the product chips. Especially the resulting side wall surface of the chips is characteristic for the separating technology applied. Looking at silicon from a material point of view it is hard, stable and brittle. Thus the wafers made of silicon show certain fragility. Especially during wafer thinning, the wafers are stressed mechanically. The reduced stability on wafer level is one of the reasons for wafer breakage. But for back end processes and product applications the stability on chip level is of more importance. Pre Assembly is showing the major influence on mechanical properties of silicon chips. The two main process groups here are wafer thinning and chip separation. Also in final applications stresses, coming from e.g. temperature changes, have to be balanced by excellent mechanical performance. Besides the features needed for the chip applications, chip stability is also necessary for the process chain from chip separation to packaging. We did investigations in dicing quality looking at kerf width, residues, side wall damage and chip stability. As a result we can judge the different root causes influencing chip damage and stability
author_names: W Kroninger

Franco Mariani
title: Thinning and singulation of silicon: root causes of the damage in thin chips
venue: 56th Electronic Components and Technology Conference 2006
year: 2006

abstract: Singulation can be the most damaging step in electronic manufacturing where individual dice are freed from a brittle silicon wafer. So much torque and force is applied to the silicon during this process that if precautionary steps are not taken, the freed die may exhibit low strength due to chipping damage. For medical devices, this is particularly a problem because medical devices must be specially shaped and assembled so that they can fit into small implantable or insertable units for the human body. Insertable medical products require that dice have unusually high aspect ratios in order to fit into tubular shaped instruments. For this paper, we have emulated a medical device using blank silicon wafers cut to >3.60 mm long 0.36 mm wide and 0.100 mm thick. The aspect ratios of 10:1 will be compared with lower as well as high aspect ratios for dicing quality and die integrity. With standard dicing parameters with standard blades, the singulation yield would be as low as zero. Even the use of step cut which in most cases would alleviate chipping, but for such high aspect ratio dice, the yield improved to only 50% This paper will present comparative yield results of various dicing setups to find the process with the best yield on singulated dice. 100% yield for singulation resulting in higher strength devices can be obtained using properly selected blades with the correct dicing parameters. Newer, stronger and narrower blades are allowing dice with high aspect ratios to be sawn without chipping yield loss. Also special dicing programs are required to produce chip free dies without resorting to laser saws.
author_names: Annette Teng

Finn Wilhelmsen
title: Medical Device Wafer Singulation
venue: 2007 32nd IEEE/CPMT International Electronic Manufacturing Technology Symposium
year: 2007

abstract: In support of improved productivity for the semiconductor and optoelectronics manufacturing industry, new work is presented on the development of a plasma based die singulation process technique for thin Si wafers. It is shown that the technique leads to a significant gain in productivity through reduced process times and increased available good die per wafer. Some additional related key benefits are increased yield, die strength, and the potential of nonorthogonal die.
author_names: Kenneth D Mackenzie

David Pays-Volard

Linnell Martinez

Chris W Johnson

Thierry Lazerand

Russell Westerman
title: Plasma based die singulation processing technology
venue: 2014 IEEE 64th Electronic Components and Technology Conference (ECTC)
year: 2014

abstract: Plasma Dicing uses Deep Reactive Ion Etch (DRIE) also known as The Bosch Process. This is a well established "front end" technology, used in silicon MEMS micromachining and via etching in 3D packaging, which is now finding a new home as a dicing technology in the "back end" of semiconductor processing. This paper will discuss the key issues and integration challenges. This is not only in wafer design and preparation, but also how the process flow is not disrupted to the extent where it becomes a hindrance to the adoption of a technology that offers so many potential benefits.
author_names: Richard Barnett
title: Plasma Dicing 300mm Framed Wafers Analysis of Improvement in Die Strength and Cost Benefits for Thin Die Singulation
venue: 2017 IEEE 67th Electronic Components and Technology Conference (ECTC)
year: 2017

abstract: Thin silicon die (100 um or less) are required for a number of applications, including stacked die packages and three dimensional integrated circuits (3D IC) The wafer thinning process is conceptually simple, but requires optimization of the backside finish and dicing to ensure high die strength. High die strength is required to minimize yield loss during assembly and to ensure high reliability during device operation. In this paper, we describe process optimization for thin wafers and thin die, and how these processes affect the fracture strength of silicon.
author_names: Jeff P Gambino
title: Thin silicon wafer processing and strength characterization
venue: Proceedings of the 20th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)
year: 2013