Search query: HZO W  FERAM

Related papers:

abstract: The HfZrOx (HZO) ferroelectric material is a promising material for ferroelectric memory and is compatible with the semiconductor process for ferroelectric random access memory (FeRAM) and negative capacitance field effect transistor. However, defects often exist in the grain boundary to influence the performance or reliability of devices. In addition, uniformity between devices must be considered when they are mass produced. Therefore, the grain size will become important in determining the performance and reliability. In this study, we use electrical measurements of current voltage, capacitance voltage, and polarization voltage measurements to test high and low temperature deposition devices, with a transmission electron microscope (TEM) image to confirm the grain size. Finally, we propose a model to explain the phenomenon and provide a method to obtain better ferroelectric memory.
author_names: Wen-Chung Chen

Yong-Ci Zhang

Yu-Hsuan Yeh

Kao-Yuan Wang

Tsung-Ming Tsai

Jen-Wei Huang
title: Performance Improvement by Modifying Deposition Temperature in HfZrOx Ferroelectric Memory
venue: IEEE Transactions on Electron Devices
year: 2021

abstract: The potential of thickness scaling in ferroelectric Hf0.5Zr0.5O2 (HZO) is investigated by a systematic study on MFM capacitors with HZO thickness from 9.5 nm down to 2.8 nm. We establish the thickness temperature mapping indicating a clear tradeoff between the thickness scaling and crystallization temperature, which has to be taken into account in the implementation as back end of line (BEOL) FeRAM. Utilizing the thickness scaling and high field wake up without reliability loss, we demonstrate 4 nm thick HZO having low crystallization temperature (500degC) excellent ferroelectricity (2Pr 25 mC/cm2) low operating voltage (0.7 1.2 V) and high read/write endurance (projected to 1014)
author_names: Kento Tahara

Kasidit Toprasertpong

Yukinobu Hikosaka

Mitsuru Takenaka

Shinichi Takagi
title: Strategy Toward HZO BEOL FeRAM with Low Voltage Operation 1.2 V) Low Process Temperature, and High Endurance by Thickness Scaling
venue: 2021 Symposium on VLSI Technology
year: 2021

abstract: This paper experimentally demonstrates fundamental memory array operation of a ferroelectric HfO2 based 1 T1 C FeRAM. Metal/ferroelectric/metal (MFM) capacitors consisting of a TiN/ \mathrm{Hf}_{0.5}\mathrm{Zr}_{0.5}\mathrm{O}_{2}\mathrm{HZO}/TiN stack were optimized for a sub 500degC process. Structures revealed excellent performance such as remanent polarization $2\mathrm{P}_{\mathrm{r} 4\vert \mu\mathrm{C}\mathrm{cm}{2} endurance> 1011 cycles, and 10 years data retention at 85degC. Furthermore, the MFM capacitors were successfully integrated into a 64 kbit 1T1C FeRAM array including our dedicated circuit for array operation. Back end of line (BEOL) wiring showed no degradation of the underlying CMOS logic. Program and read operation were properly controlled resulting in 100 bit functionality at an operation voltage of2.5 Vand operating speed at 14 ns. This technology matches requirements of last level cash (LLC) and embedded non volatile memory (NVM) in low power System on a Chip (SoC) for IoT applications.
author_names: Jun Okuno

Takafumi Kunihiro

Kenta Konishi

Hideki Maemura

Yusuke Shute

Fumitaka Sugaya

Monica Materano

Tarek Ali

Kati Kuehnel

Konrad Seide

Uwe Schroeder

Thomas Mikolajick

Masanori Tsukamoto

Taku Umebayashi
title: SoC compatible 1 T1 C FeRAM memory array based on ferroelectric Hf0.5Zr0.5O2
venue: 2020 IEEE Symposium on VLSI Technology
year: 2020

abstract: We demonstrate successful scalability of conventional 100mm diameter TiN/HZO/TiN capacitors down to 300nm by successfully co integrating them for the first time in the Back End Of Line of 130nm CMOS technology. Excellent performance are reported on those scaled bitcells, such as remnant polarization 2.PR 40mC/cm2, endurance 1011 cycles, switching speeds 100ns, operating voltages 4V, and data retention at 125degC. Presented results pave the way to 10fJ/bit ultra low power FeRAM for IoT applications.
author_names: Thomas Francois

C Pellissier

Stefan Slesazeck

Viktor Havel

Claudia Richter

Adam Makosiej

Bastien Giraud

Evelyn T Breyer

Monica Materano

Philippe Chiquet

Marc Bocquet

Laurent Grenouillet

Etienne Nowak

Uwe Schroeder

F Gaillard

Jean Coignus

Philippe Blaise

C Carabasse

Nicolas Vaxelaire

Thomas Magis

F Aussenac

Virginie Loup
title: Demonstration of BEOL compatible ferroelectric Hf0.5Zr0.5O2 scaled FeRAM co integrated with 130nm CMOS for embedded NVM applications
venue: 2019 IEEE International Electron Devices Meeting (IEDM)
year: 2019

abstract: The recent discovery of ferroelectric behavior in doped hafnia based dielectrics, attributed to a non centrosymmetric orthorhombic phase, has potential for use in attractive applications such as negative differential capacitance field effect transistors (NCFET) and ferroelectric random access memory devices (FeRAM) Alloying with similar oxides like ZrO 2 doping with specific elements such as Si, novel processing methods, encapsulation and annealing schemes are also some of the techniques that are being explored to target structural modifications and stabilization of the non centrosymmetric phase. In this study, we utilized synchrotron based x ray diffraction in the grazing incidence in plane geometry (GIIXRD) to determine the crystalline phases in hafnia zirconia (HZO) compositional alloys deposited by atomic layer deposition (ALD) Here we compare and contrast the structural phases and ferroelectric properties of mechanically confined HZO films in metal insulator metal (MIM) and metal insulator semiconductor (MIS) structures. Both MIM and MIS structures reveals a host of reflections due to non monoclinic phases in the d spacing region between 1.75A to 4A. The non monoclinic phases are believed to consist of tetragonal and orthorhombic phases. Compared to the MIS structures a suppression of the monoclinic phase in MIM structures with 50% zirconia or less was observed. The correlation of the electrical properties with the structural analysis obtained by GIIXRD highlights the importance of understanding the effects of the underlying substrate (metal vs. Si) for different target applications.
author_names: Vineetha Mukundan

Karsten Beckmann

Kandabara Tapily

Steven Consiglio

Robert Clark

Gert J Leusink

Nathaniel C Cady

Alain C Diebold
title: Structural Correlation of Ferroelectric Behavior in Mixed Hafnia Zirconia High k Dielectrics for FeRAM and NCFET Applications
venue: MRS Advances
year: 2019

abstract: A novel 64 kbit one transistor one capacitor (1T1C) ferroelectric random access memory (FeRAM) array based on ferroelectric Hf0.5Zr0.5O2 (HZO) was proposed in a prior report. However, this array requires a low operation voltage for integration into advanced technology nodes, and its practical endurance remains unclear. To address these limitations, this study experimentally demonstrates the improved characteristics of a ferroelectric HfO2 based 1T1C FeRAM array. Thickness scaling of the ferroelectric HZO contributes to low voltage operation of 1T1C FeRAMs, yielding 100% bit functionality at an operation voltage of 2.0 V and operating speed of 16 ns. Furthermore, the endurance performance of the 1T1C FeRAM memory array was investigated for the first time. Excellent cycling endurance >108 cycles) at an accelerated stress voltage of 3.5 V at 85degC was experimentally observed. The 1 ppm RBER at 2.0 V, 100 ns, and 85degC operation was predicted to be >1018 cycles, based on the dependence of time to breakdown on the stress voltage. This technology matches the requirements of last level cache and low power systems on chips for Internet of things applications.
author_names: Jun Okuno

Takafumi Kunihiro

Kenta Konishi

Hideki Maemura

Yusuke Shuto

Fumitaka Sugaya

Monica Materano

Tarek Ali

Maximilian Lederer

Kati Kuehnel

Konrad Seidel

Uwe Schroeder

Thomas Mikolajick

Masanori Tsukamoto

Taku Umebayashi
title: High Endurance and Low Voltage operation of 1T1C FeRAM Arrays for Nonvolatile Memory Application
venue: 2021 IEEE International Memory Workshop (IMW)
year: 2021

abstract: Hf0.5Zr0.5O2 (HZO) ferroelectric random access memory (FeRAM) has been demonstrated in 130nm node with 1T1C structure. To scale FeRAM to 28nm or beyond, a high aspect ratio embedded DRAM like 3D cylinder capacitor is expected to ensure sufficient cell capacitance and sense margin. In this work, we investigate an alternative approach with 2T1C structure that takes advantages of a back end of line (BEOL) oxide channel writing transistor, a small planar ferroelectric capacitor, and a silicon logic reading transistor. Firstly, the proof of concept of 2T1C bit cell was experimentally demonstrated. Then, the scalability towards 28nm was simulated with array level parasitics. Thanks to the transconductance reading out mechanism, a 784 nm2 ferroelectric capacitor in 2T1C could significantly reduce energy consumption 6.5 11x compared to the traditional 1T1C FeRAM with similar cell area at 28nm.
author_names: Jae Hur

Yuan-Chun Luo

Wonbo Shim

Asif Islam Khan

Shimeng Yu
title: A Technology Path for Scaling Embedded FeRAM to 28nm with 2T1C Structure
venue: 2021 IEEE International Memory Workshop (IMW)
year: 2021

abstract: Abstract The quest for non volatile memories has attracted tremendous attention, especially in mature ferroelectric random access memory (FeRAM) with properties of high read/write speed and low power consumption. Strain engineering of multiferroic BiFeO 3 (BFO) has recently become the subject of broad research interest because of its intriguing properties. In this study, we demonstrate the switchable diode characteristics in highly strained BFO thin films. Using a unique in situ electrical transmission electron microscopy (TEM) we verify the correlation between ferroelectric resistive switching with multilevel states and polarization reversal. Structural investigation confirms that the phase transition from mixed phase to pure T like phase, accompanying with the polarization reversal by external bias, is the origin of the multilevel states. The switchable diode with multilevel resistive switching can be explained in terms of the variation of the barrier height, governed by ferroelectric polarization and polarity of the external bias. This research model, i.e. engineering of the room inside, can offer an approach toward high density memories.
author_names: C H Chiu

Chun-Wei Huang

Ying-Hui Hsieh

Jui-Yuan Chen

Chia-Fu Chang

Y H Chu

Wen-Wei Wu
title: In situ TEM observation of Multilevel Storage Behavior in low power FeRAM device
year: 2017

abstract: Energy efficient, high throughput, noise immune, high density HZO FeFET Computation in Memory (CiM) is proposed. Local Multiply Global Accumulate Array is realized by source follower read, which multiplies neural network inputs and weights (FeFET VTH) and charge sharing, which accumulates multiplied values. Proposed CiM is immune to read disturb. After 10 year data retention, 3 bit/cell FeFET is feasible. x64 energy efficient, 66 TOPS/W, reliable multiply accumulate (MAC) operation is achieved.
author_names: Chihiro Matsui

Kasidit Toprasertpong

Shinichi Takagi

Ken Takeuchi
title: Energy Efficient Reliable HZO FeFET Computation in Memory with Local Multiply Global Accumulate Array for Source Follower Charge Sharing Voltage Sensing
venue: 2021 Symposium on VLSI Circuits
year: 2021

abstract: Energy efficient, high throughput, noise immune, high density HZO FeFET Computation in Memory (CiM) is proposed. Local Multiply Global Accumulate Array is realized by source follower read, which multiplies neural network inputs and weights (FeFET VTH) and charge sharing, which accumulates multiplied values. Proposed CiM is immune to read disturb. After 10 year data retention, 3 bit/cell FeFET is feasible. x64 energy efficient, 66 TOPS/W, reliable multiply accumulate (MAC) operation is achieved.
author_names: Chihiro Matsui

Kasidit Toprasertpong

Shinichi Takagi

Ken Takeuchi
title: Energy Efficient Reliable HZO FeFET Computation in Memory with Local Multiply Global Accumulate Array for Source Follower Charge Sharing Voltage Sensing
venue: 2021 Symposium on VLSI Technology
year: 2021