Search query: Operation of a silicon quantum processor unit cell above one kelvin

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abstract: Quantum computers are expected to outperform conventional computers in several important applications, from molecular simulation to search algorithms, once they can be scaled up to large numbers typically millions of quantum bits (qubits) 1 3 For most solid state qubit technologies for example, those using superconducting circuits or semiconductor spins scaling poses a considerable challenge because every additional qubit increases the heat generated, whereas the cooling power of dilution refrigerators is severely limited at their operating temperature (less than 100 millikelvin) 4 6 Here we demonstrate the operation of a scalable silicon quantum processor unit cell comprising two qubits confined to quantum dots at about 1.5 kelvin. We achieve this by isolating the quantum dots from the electron reservoir, and then initializing and reading the qubits solely via tunnelling of electrons between the two quantum dots 7 9 We coherently control the qubits using electrically driven spin resonance 10 11 in isotopically enriched silicon 12 28 Si, attaining single qubit gate fidelities of 98.6 per cent and a coherence time of 2 microseconds during 'hot' operation, comparable to those of spin qubits in natural silicon at millikelvin temperatures 13 16 Furthermore, we show that the unit cell can be operated at magnetic fields as low as 0.1 tesla, corresponding to a qubit control frequency of 3.5 gigahertz, where the qubit energy is well below the thermal energy. The unit cell constitutes the core building block of a full scale silicon quantum computer and satisfies layout constraints required by error correction architectures 8 17 Our work indicates that a spin based quantum computer could be operated at increased temperatures in a simple pumped 4 He system (which provides cooling power orders of magnitude higher than that of dilution refrigerators) thus potentially enabling the integration of classical control electronics with the qubit array 18 19 A scalable silicon quantum processor unit cell made of two qubits confined to quantum dots operates at about 1.5 K, achieving 98.6% single qubit gate fidelities and a 2 ms coherence time.
author_names: C H Yang

Ross C C Leon

J C C Hwang

Andre Saraiva

Tuomo Tanttu

W Huang

Julien Camirand Lemyre

K W Chan

K Y Tan

Fay E Hudson

Kohei M Itoh

Andrea Morello

Michel Pioro-Ladriere

Arne Laucht

Andrew S Dzurak
title: Operation of a silicon quantum processor unit cell above one kelvin
venue: Nature
year: 2020

abstract: Quantum computers are expected to outperform conventional computers for a range of important problems, from molecular simulation to search algorithms, once they can be scaled up to large numbers of quantum bits (qubits) typically millions. For most solid state qubit technologies, e.g. those using superconducting circuits or semiconductor spins, scaling poses a significant challenge as every additional qubit increases the heat generated, while the cooling power of dilution refrigerators is severely limited at their operating temperature below 100 mK. Here we demonstrate operation of a scalable silicon quantum processor unit cell, comprising two qubits confined to quantum dots (QDs) at \sim$1.5 Kelvin. We achieve this by isolating the QDs from the electron reservoir, initialising and reading the qubits solely via tunnelling of electrons between the two QDs. We coherently control the qubits using electrically driven spin resonance (EDSR) in isotopically enriched silicon {28}$Si, attaining single qubit gate fidelities of 98.6% and coherence time $T_2^ 2$\mu$s during `hot' operation, comparable to those of spin qubits in natural silicon at millikelvin temperatures. Furthermore, we show that the unit cell can be operated at magnetic fields as low as 0.1 T, corresponding to a qubit control frequency of 3.5 GHz, where the qubit energy is well below the thermal energy. The unit cell constitutes the core building block of a full scale silicon quantum computer, and satisfies layout constraints required by error correction architectures. Our work indicates that a spin based quantum computer could be operated at elevated temperatures in a simple pumped ^4$He system, offering orders of magnitude higher cooling power than dilution refrigerators, potentially enabling classical control electronics to be integrated with the qubit array.
author_names: C H Yang

Ross C C Leon

J C C Hwang

Andre Saraiva

Tuomo Tanttu

W Huang

Julien Camirand Lemyre

K W Chan

K Y Tan

Fay E Hudson

Kohei M Itoh

Andrea Morello

Michel Pioro-Ladriere

Arne Laucht

Andrew S Dzurak
title: Silicon quantum processor unit cell operation above one Kelvin.
year: 2019

abstract: The researchers' proof of concept quantum processor unit cell, on a silicon chip, works at 1.5 Kelvin 15 times warmer than the main competing chip based technology being developed by Google, IBM, and others, which uses superconducting qubits. "This is still very cold, but is a temperature that can be achieved using just a few thousand dollars' worth of refrigeration, rather than the millions of dollars needed to cool chips to 0.1 Kelvin," explains Dzurak.
author_names: Andrew S Dzurak
title: Hot qubits break one of the biggest constraints to practical quantum computers
year: 2020

abstract: Spins confined in Metal Oxide Silicon (MOS) quantum dot devices are promising qubits in a quantum processor, demonstrating long coherence times, a large valley splitting, and coherent interactions with donor qubits. Furthermore, the mature fabrication infrastructure of the CMOS industry offers a tantalizing roadmap towards scaling to extremely large quantum systems on a single silicon chip. Despite the incredible advances in materials and fabrication developed by the classical CMOS industry and continued by the silicon quantum electronics community, many challenges remain in building a silicon quantum processor. One of the biggest challenges impeding the scaling of large quantum dot systems is the presence of disorder and shallow electron traps at the Si/SiO2 interface. The purpose of this thesis is to illuminate mechanisms of disorder at the Si/SiO2 interface relevant to quantum dot devices, develop a framework for understanding and quantifying shallow electron traps in terms of electron spin resonance and transport measurements, and to pave a path forward for scaling MOS quantum dot devices. This thesis is organized into three sections: first, we develop a fabrication process in silicon MOSFETs yielding a low disorder Si/SiO2 interface in order to leverage this process as a platform for fabricating low disorder quantum dot devices. One of the challenges in working with silicon oxide is that high energy processes and mobile ionic contamination during the fabrication process can create electron traps and disorder at the Si/SiO2 interface. Using the low temperature (4.2 K) electron mobility as a proxy for the Si/SiO2 interface quality, we study the effect of various processing parameters on the Si/SiO2 interface disorder and ultimately arrive at a fully optimized process yielding the highest reported mobility (23,000 cm/Vs) thin oxide =30 nm) silicon MOSFET. Secondly, we study the annealing of shallow electron traps created by electronbeam (e beam) lithography. E beam lithography is a necessary tool in defining nanoiii scale electrostatic gates which define the quantum dot potential, but the high energy electrons and photons created in the process create electron traps at the interface. We directly probe shallow electron traps using electron spin resonance (ESR) and demonstrate that 1) a standard forming gas anneal is sufficient to passivate electron traps created by the e beam exposure, and 2) that our lowest temperature ESR measurements agree with transport measurements of the devices' percolation threshold, demonstrating agreement between two independent methods of characterizing the Si/SiO2 interface. Finally, leveraging the above process optimizations, we fabricate and characterize a low disorder double quantum dot device. We demonstrate agreement between the dots' charging energy and lithographic size, concluding that our dots are lithographically defined and not dominated by random disorder. Charge sensing measurements indicate regular quantum dot transitions over a wide parameter range down to the single electron regime, with evidence of few defects in the vicinity of the quantum dots, and the controllable formation of a quantum double dot. Noise spectroscopy measurements of the dot indicate a 1/f like power spectral density that is comparable in magnitude to other Si quantum dot devices measured at 300 mK. Finally, magneto spectroscopy measurements of the first and second electron transitions yield a valley splitting of 110+ 26 meV, large enough to support high fidelity spin selective operations. With this work, we demonstrate a method of fabricating low disorder, highmobility silicon MOSFETs, a framework for studying disorder in quantum dot devices in the low electron density regime, and a promising platform for MOS qubits in a lowdisorder quantum dot device architecture.
author_names: Jin-Sung Kim
title: Development and Characterization of Low Disorder Metal Oxide Silicon Quantum Dot Devices
year: 2018

abstract: Even the quantum simulation of an apparently simple molecule such as Fe2S2 requires a considerable number of qubits of the order of 106, while more complex molecules such as alanine (C3H7NO2) require about a hundred times more. In order to assess such a multimillion scale of identical qubits and control lines, the silicon platform seems to be one of the most indicated routes as it naturally provides, together with qubit functionalities, the capability of nanometric, serial, and industrial quality fabrication. The scaling trend of microelectronic devices predicting that computing power would double every 2 years, known as Moore's law, according to the new slope set after the 32 nm node of 2009, suggests that the technology roadmap will achieve the 3 nm manufacturability limit proposed by Kelly around 2020. Today, circuital quantum information processing architectures are predicted to take advantage from the scalability ensured by silicon technology. However, the maximum amount of quantum information per unit surface that can be stored in silicon based qubits and the consequent space constraints on qubit operations have never been addressed so far. This represents one of the key parameters toward the implementation of quantum error correction for fault tolerant quantum information processing and its dependence on the features of the technology node. The maximum quantum information per unit surface virtually storable and controllable in the compact exchange only silicon double quantum dot qubit architecture is expressed as a function of the complementary metal oxide semiconductor technology node, so the size scale optimizing both physical qubit operation time and quantum error correction requirements is assessed by reviewing the physical and technological constraints. According to the requirements imposed by the quantum error correction method and the constraints given by the typical strength of the exchange coupling, we determine the workable operation frequency range of a silicon complementary metal oxide semiconductor quantum processor to be within 1 and 100 GHz. Such constraint limits the feasibility of fault tolerant quantum information processing with complementary metal oxide semiconductor technology only to the most advanced nodes. The compatibility with classical complementary metal oxide semiconductor control circuitry is discussed, focusing on the cryogenic complementary metal oxide semiconductor operation required to bring the classical controller as close as possible to the quantum processor and to enable interfacing thousands of qubits on the same chip via time division, frequency division, and space division multiplexing. The operation time range prospected for cryogenic control electronics is found to be compatible with the operation time expected for qubits. By combining the forecast of the development of scaled technology nodes with operation time and classical circuitry constraints, we derive a maximum quantum information density for logical qubits of 2.8 and 4 Mqb/cm2 for the 10 and 7 nm technology nodes, respectively, for the Steane code. The density is one and two orders of magnitude less for surface codes and for concatenated codes, respectively. Such values provide a benchmark for the development of fault tolerant quantum algorithms by circuital quantum information based on silicon platforms and a guideline for other technologies in general.
author_names: Davide Rotta

Fabio Sebastiano

Edoardo Charbon

Enrico Prati
title: Quantum information density scaling and qubit operation time constraints of CMOS silicon based quantum computer architectures
year: 2017

abstract: Quantum computation requires many qubits that can be coherently controlled and coupled to each other 1 Qubits that are defined using lithographic techniques have been suggested to enable the development of scalable quantum systems because they can be implemented using semiconductor fabrication technology 2 5 However, leading solid state approaches function only at temperatures below 100 millikelvin, where cooling power is extremely limited, and this severely affects the prospects of practical quantum computation. Recent studies of electron spins in silicon have made progress towards a platform that can be operated at higher temperatures by demonstrating long spin lifetimes 6 gate based spin readout 7 and coherent single spin control 8 However, a high temperature two qubit logic gate has not yet been demonstrated. Here we show that silicon quantum dots can have sufficient thermal robustness to enable the execution of a universal gate set at temperatures greater than one kelvin. We obtain single qubit control via electron spin resonance and readout using Pauli spin blockade. In addition, we show individual coherent control of two qubits and measure single qubit fidelities of up to 99.3 per cent. We demonstrate the tunability of the exchange interaction between the two spins from 0.5 to 18 megahertz and use it to execute coherent two qubit controlled rotations. The demonstration of 'hot' and universal quantum logic in a semiconductor platform paves the way for quantum integrated circuits that host both the quantum hardware and its control circuitry on the same chip, providing a scalable approach towards practical quantum information processing. Lithographically defined qubits are shown to support full two qubit logic at temperatures above one kelvin by using electron spin states in silicon quantum dots.
author_names: L Petit

H G J Eenink

Maximilian Russ

W I L Lawrie

Nico W Hendrickx

S G J Philips

James S Clarke

Lieven M K Vandersypen

Menno Veldhorst
title: Universal quantum logic in hot silicon qubits
venue: Nature
year: 2020

abstract: Individual impurity atoms in silicon can make superb individual qubits, but it remains an immense challenge to build a multi qubit processor: there is a basic conflict between nanometre separation desired for qubit qubit interactions and the much larger scales that would enable control and addressing in a manufacturable and fault tolerant architecture. Here we resolve this conflict by establishing the feasibility of surface code quantum computing using solid state spins, or 'data qubits' that are widely separated from one another. We use a second set of 'probe' spins that are mechanically separate from the data qubits and move in and out of their proximity. The spin dipole dipole interactions give rise to phase shifts; measuring a probe's total phase reveals the collective parity of the data qubits along the probe's path. Using a protocol that balances the systematic errors due to imperfect device fabrication, our detailed simulations show that substantial misalignments can be handled within fault tolerant operations. We conclude that this simple 'orbital probe' architecture overcomes many of the difficulties facing solid state quantum computing, while minimising the complexity and offering qubit densities that are several orders of magnitude greater than other systems. Scientists in the UK propose a solution for the miniaturization of quantum computers utilizing movable read out stages. A team led by Simon Benjamin of Oxford University and John Morton of University College London aimed to resolve the difficulty inherent in interacting with many qubits within a scalable quantum computer based on impurity atoms in silicon. The researchers propose a device architecture based on two moving silicon chips, where impurity atoms embedded in a movable silicon 'probe stage' hover above a silicon 'data stage' to control and access the qubits. The architecture arranges the impurities in a checkerboard pattern and is optimized for the 'surface code' a method of protecting qubits from errors in a device of any size. This represents a promising approach for developing scalable quantum computers.
author_names: Joe O'Gorman

Naomi Nickerson

Philipp Ross

John J L Morton

Simon C Benjamin
title: A silicon based surface code quantum computer
year: 2014

abstract: Abstract. One way for solar cell efficiencies to overcome the Shockley Queisser limit is downconversion of high energy photons using singlet fission (SF) in polyacenes like tetracene (Tc) SF enables generation of multiple excitons from the high energy photons, which can be harvested in combination with Si. In this work, we investigate the use of lead sulfide quantum dots (PbS QDs) with a band gap close to Si as an interlayer that allows Forster resonant energy transfer (FRET) from Tc to Si, a process that would be spin forbidden without the intermediate QD step. We investigate how the conventional FRET model, most commonly applied to the description of molecular interactions, can be modified to describe the geometry of QDs between Tc and Si and how the distance between QD and Si, and the QD bandgap affects the FRET efficiency. By extending the acceptor dipole in the FRET model to a 2 D plane, and to the bulk, we see a relaxation of the distance dependence of transfer. Our results indicate that FRET efficiencies from PbS QDs to Si well above 50% are possible at very short but possibly realistic distances of around 1 nm, even for QDs with relatively low photoluminescence quantum yield.
author_names: Stefan W Tabernig

Benjamin Daiber

T Wang

Bruno Ehrler
title: Enhancing silicon solar cells with singlet fission: the case for Forster resonant energy transfer using a quantum dot intermediate
year: 2018

abstract: One way to surpass the Shockley Queisser limit is the use of a downconversion mechanism to obtain two excitons from an initial excitation by a high energy photon. Singlet fission is such a downconversion process, enabling separation of a singlet state exciton into two triplet state excitons. Tetracene is a material that exhibits singlet fission and the energy of the triplet exciton (1.25 eV) lies above the bandgap of Si (1.12 eV) This means that if energy transfer from Tc to Si can be achieved, the high energy range of the solar spectrum can be harvested much more efficiently by adding a Tc layer on top of a Si solar cell. One way to achieve this energy transfer is by introducing PbS QDs as an intermediate. This geometry makes use of efficiently working Dexter energy transfer between Tc and PbS QDs. However, the mechanism for the subsequent transfer step from the PbS QDs to Si has not yet been identified. Here, we investigate Forster resonance energy transfer as a possible mechanism and use its theoretical framework to obtain a Forster model for our geometry. Furthermore, we compare this model with experiment by investigating the dependence of the QD PL lifetime on the QD Si separation. The results show that energy transfer with an efficiency of up to 15.3 is possible. However, the data does not allow to draw a final conclusion regarding the underlying transfer mechanism.
author_names: E Burke
title: Forster resonance energy transfer from PbS quantum dots to silicon
year: 2018

abstract: Silicon spin qubits have emerged as a promising path to large scale quantum processors. In this prospect, the development of scalable qubit readout schemes involving a minimal device overhead is a compelling step. Here we report the implementation of gate coupled rf reflectometry for the dispersive readout of a fully functional spin qubit device. We use a p type double gate transistor made using industry standard silicon technology. The first gate confines a hole quantum dot encoding the spin qubit, the second one a helper dot enabling readout. The qubit state is measured through the phase response of a lumped element resonator to spin selective interdot tunneling. The demonstrated qubit readout scheme requires no coupling to a Fermi reservoir, thereby offering a compact and potentially scalable solution whose operation may be extended above 1 K.Gate reflectometry is a recently demonstrated measurement technique for single spin states in silicon. It is potentially able to perform quantum non demolition measurements and uses compact circuitry that can be scaled up to larger quantum computers. Crippa et al. successfully combine gate reflectometry qubit readout and coherent control.
author_names: Alessandro Crippa

R Ezzouch

Agostino Apra

A Amisse

R Lavieville

Louis Hutin

Benoit Bertrand

Maud Vinet

Matias Urdampilleta

Tristan Meunier

Marc Sanquer

Xavier Jehl

Romain Maurand

Silvano de Franceschi
title: Gate reflectometry dispersive readout and coherent control of a spin qubit in silicon
venue: Nature Communications
year: 2019