Search query: Electrostatic design of vertical tunneling field-effect transistors

Related papers:

abstract: Tunneling field effect transistors (TFETs) have created excitement for their potential to overcome the 60 mV/decade thermal limit of the subthreshold swing for conventional devices enabling lower power electronics. However, as shown in the TFET review by Seabaugh and Zhang [1] experimental subthreshold characteristics have not achieved the steepness of theoretical predictions. Possible explanations for the non abrupt turn on of experimental devices include long band tails (exacerbated by doping) that extend into the semiconductor band gap, mid gap and interface trap states, inhomogeneity of the semiconductor composition, strain and/or thickness, and non optimal electrostatic design of the transistor structure. This paper focuses on improving the electrostatic design of vertical tunneling structures (where tunneling occurs vertically toward the gate) in order to better experimental turn on characteristics.
author_names: James T Teherani

Tao Yu

Dimitri A Antoniadis

Judy L Hoyt
title: Electrostatic design of vertical tunneling field effect transistors
venue: 2013 Third Berkeley Symposium on Energy Efficient Electronic Systems (E3S)
year: 2013

abstract: Abstract Total ionizing dose (TID) and transient dose rate (TDR) effects on planar and vertical ferroelectric tunneling field effect transistors (TFET) are investigated using TCAD simulations. First, two types of TFET structures are constructed numerically. Then the electrical properties of these devices are studied under different irradiation doses, demonstrating that they are slightly affected by TID effects, especially for the vertical transistor. The maximum photocurrents under different operation voltage (VD) and dose rate are extremely small with respect to the conventional bulk transistors. Physical mechanisms of device performance degradation are investigated in detail. The results suggest that the vertical ferroelectric TFET, which shows better electrical performance and radiation hard characteristics compared with the planar one, is useful for the design of very large scale logic circuits for applications in harsh radiation environments.
author_names: Gangping Yan

Gaobo Xu

Jinshun Bi

Guoliang Tian

Qiuxia Xu

Huaxiang Yin

Yongliang Li
title: Accumulative total ionizing dose (TID) and transient dose rate (TDR) effects on planar and vertical ferroelectric tunneling field effect transistors (TFET)
year: 2020

abstract: Tunneling field effect transistors (TFETs) have been proposed as energy efficient switches for low power integrated circuits. In this letter, we present the first reconfigurable black phosphorus vertical TFET. The device exhibits a record high ON current <inline formula> <tex math notation="LaTeX"{I}_{\text {ON} /tex math>/inline formula> among all 2D TFETs of <inline formula> <tex math notation="LaTeX"$15.2~\mu \text{A}\mu \text{m} /tex math>/inline formula> at <inline formula> <tex math notation="LaTeX"{V}_{\text {DS} {1} /tex math>/inline formula> V and a subthreshold swing (SS) of 187 mV/dec at <inline formula> <tex math notation="LaTeX"$V_{\text {DS} {0.3} /tex math>/inline formula> V. By tuning the electrostatic doping with multiple gates, the device can be reconfigured to operate in the TFET mode or the MOSFET mode and can be tuned to behave like an n type or p type FET. Moreover, negative differential resistance (NDR) is observed in the forward bias of the TFET at room temperature, providing unambiguous evidence of band to band tunneling in our devices.
author_names: Peng Wu

Joerg Appenzeller
title: Reconfigurable Black Phosphorus Vertical Tunneling Field Effect Transistor With Record High ON Currents
venue: IEEE Electron Device Letters
year: 2019

abstract: Dear editor, Ferroelectric tunneling FETs (FeTFETs) are the increasingly significant research topics on novel low power electronic devices [1, 2] because ferroelectric materials' negative capacitance effect is helpful to boost the channel potential and increase the on state current in TFETs. Ferroelectric materials show radiation hard performance against radiation, which is helpful for devices based on this type of material utilized in harsh environment [3, 4] Single event transient (SET) effects are caused by high energy particles in space or terrestrial radiation environment, which may increase the probability of soft error or even lead to catastrophic accidents in the spacecraft [5, 6] Research on the irradiation effects of FeTFETs under heavy ion strike is therefore extremely important to evaluate use of these devices for potential missions in space environments. In order to boost the devices' performance, we propose a new silicon oninsulator double gate FeTFET (SOI DG FeTFET) with the Si:HfO2 ferroelectric gate dielectric. The single event transient effects in SOI DG FeTFET were investigated using a synopsys sentaurus technology computer aided design (TCAD) simulator [7] Device structure and simulation setup. The two dimensional (2D) architecture of the SOI DGFeTFET considered in the simulation is shown in Figure 1(a) In this structure, 10 nm thick Si:HfO2 ferroelectric layer is used as the gate dielectric, and amorphous HfO2 film with 2 nm thickness is used as a gate insulator between the poly crystalline Si:HfO2 layer and Si substrate. The detailed geometry parameters for SOI DG FeTFET are given in Figure 1(b) Complete device structure was built in the simulation, with left and right drains part of the same node. Because the structure is symmetrical, the right half of the device is chosen as the incident position of heavy ions. Ions strike in the middle of the body in the right half of the device with linear energy transfer (LET) ranges from 10 to 100 MeV*cm/mg. Collection charge in the complete device structure is taken into consideration. The ion trajectories have a Gaussian radial distribution with characteristic radius of 5 nm. The SOI DG FeTFET in TCAD simulation is biased to off state (Vg 0 V) with the drain terminal at 0.5 V, while the substrate and source electrodes are grounded. Results and discussion. Figure 1(c) shows the SET drain current for SOI DG FeTFET with different LETs at Vd 0.5 V. The drain transient leakage current gradually increases to a max
author_names: Guoliang Tian

Jinshun Bi

Gaobo Xu

Kai Xi

Xueqin Yang

Majumdar Sandip

Huaxiang Yin

Qiuxia Xu

Wenwu Wang
title: Single event transient effects in silicon on insulator ferroelectric double gate vertical tunneling field effect transistors
year: 2020

abstract: We demonstrate improved performance due to enhanced electrostatic control achieved by diameter scaling and gate placement in vertical InAs GaSb tunneling field effect transistors integrated on Si substrates. The best subthreshold swing, 68 mV/decade at VDS 0.3 V, was achieved for a device with 20 nm InAs diameter. The ON current for the same device was 35 mA/mm at VGS 0.5 V and VDS 0.5 V. The fabrication technique used allow downscaling of the InAs diameter down to 11 nm with a flexible gate placement.
author_names: Elvedin Memisevic

Johannes Svensson

Markus Hellenbrand

Erik Lind

Lars-Erik Wernersson
title: Scaling of Vertical InAs GaSb Nanowire Tunneling Field Effect Transistors on Si
venue: IEEE Electron Device Letters
year: 2016

abstract: Subthreshold characteristics of vertical tunneling field effect transistors (VTFETs) with an n+ pocket in the p+ source are studied by simulating the transfer characteristics with a commercial device simulator. Three types of subthreshold characteristics are demonstrated for the device with different pocket thicknesses and doping concentrations. Band diagram analysis shows that such a VTFET can be treated as a gate controlled tunnel diode connected in series with a conventional n channel metal oxide semiconductor FET. This VTFET can work either as a TFET or an n MOSFET in the subthreshold region, depending on the turn on sequence of these two components. To our knowledge, this is the first time such a device model has been used to explain the subthreshold characteristics of this kind of VTFET and the simulation results demonstrate that such a device model is convictive and valid. Our results indicate that the design of the n+ pocket is crucial for such a VTFET in order to achieve ultra steep turn on characteristics.
author_names: Han Zhongfang

Ru Guo-Ping

Ruan Gang
title: Analysis of the subthreshold characteristics of vertical tunneling field effect transistors
year: 2013

abstract: The effect of interface traps on InGaAs based vertical gate all around (GAA) tunneling field effect transistors (TFETs) has been investigated using technology computer aided design (TCAD) simulation. The interface traps distributed within different energy levels (Et) in the energy bandgap of a semiconductor material exhibit various influences on the device performances. In this work, InGaAs based TFETs are simulated to analyze the effects on the on state current (Ion) off state current (Ioff) threshold voltage (Vth) subthreshold swing (SS) and the ambipolar characteristics according to Et and type of the interface traps. We have confirmed that Ioff and SS are degraded by the interface traps. Further, it can be shown that Ion is mainly affected by the acceptor like traps and ambipolar behavior is affected by the donor like traps. All the effects increase as Et becomes closer to the midgap. The effects of the interface traps with gate underlap and overlap at the source channel region also have been investigated, considering the device fabrication. Additionally, the analysis of the effect of junction trap created at the source channel junction has been performed.
author_names: Won Douk Jang

Young Jun Yoon

Min Su Cho

Bo Gyeong Kim

D In Man Kang
title: Effect of Interface Traps on the Device Performance of InGaAs Based Gate All Around Tunneling Field Effect Transistors.
venue: Journal of nanoscience and nanotechnology
year: 2019

abstract: Doping organic semiconductors has become a key technology to increase the performance of organic light emitting diodes, solar cells, or field effect transistors (OFETs) However, doping can be used.
author_names: Shiyi Liu

Max Lutz Tietze

Akram Al-Shadeedi

Vikash Kaphle

Changmin Keum

Bjorn Lussem
title: Vertical Organic Tunnel Field Effect Transistors
venue: ACS Applied Electronic Materials
year: 2019

abstract: A structure of a tunneling field effect transistor (TFET) featuring an extremely thin body, a double gated vertical channel, and a source design to maximize the drive current is proposed and optimized on the basis of technology computer aided design (TCAD) simulation. The field coupling effect at the double gated thin body channel and an engineered tunneling barrier are implemented to maximize the operation current of the device. Weak current drivability under a small drain bias and the directionality of current flow are the expected challenges in building logic circuits with TFETs. A co integration scheme to build vertical channel TFETs and metal oxide semiconductor field effect transistors (MOSFETs) is proposed as the solution. A new low power design using the co integration scheme is suggested.
author_names: Min-Chul Sun

Sang Wan Kim

Hyun Woo Kim

Garam Kim

Hyungjin Kim

Jongho Lee

Hyungcheol Shin

Byung-Gook Park
title: Design of Thin Body Double Gated Vertical Channel Tunneling Field Effect Transistors for Ultralow Power Logic Circuits
year: 2012

abstract: In this work, design optimization of vertical double gate (VDG) tunneling field effect transistors (TFETs) with hetero gate dielectric (HG) materials has been performed. High k materials such as Si3N4, HfO2, and ZrO2 were used for the HG structure. The optimized parameters for maximizing the device performances were the length of the high k material (Lhigh k) and the thickness of silicon channel (tSi) For HfO2, the subthreshold swing (SS) and on current were optimized at a Lhigh k of 11 nm and a tSi of 5 nm. The optimized device had an on current (Ion) of 151 uA/um and a SS of 46.6 mV/dec. In addition, to improve the on current level of the optimized device, we inserted a thin n doped layer into the channel near the source side, and we analyzed the performance. The on current level of the device with an n doped layer was nearly double that of the device without an n doped layer.
author_names: Young Jun Yoon

Sung Yun Woo

Jae Hwa Seo

Jae-Sung Lee

Yun Soo Park

Jung-Hee Lee

In Man Kang
title: Design optimization of vertical double gate tunneling field effect transistors
year: 2012