Search query: SiC MOSCAP high k oxides

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abstract: Aluminum based high permittivity (high k) gate dielectrics and suitable metal electrodes were systematically designed for advanced SiC power metal oxide semiconductor field effect transistors (MOSFETs) Although electron injection into alumina (Al2O3) was significantly suppressed by nitrogen incorporation (aluminum oxynitride: AlON) gate leakage current under negative gate bias and hole trapping into the dielectrics were observed. Adding hafnium into the AlON (HfAlON) was investigated to overcome these drawbacks, and an atomic layer deposition based method for HfAlON was developed in terms of permittivity, energy bandgap, and hole conduction under negative stressing conditions. Consequently, the reliability of metal/high k gate stacks under both positive and negative bias temperature stresses was improved by using an optimized HfAlON gate dielectric in combination with a high work function TiN gate electrode. Thanks to the higher permittivity of HfAlON, peak transconductance was successfully enhanced up to 3.4 times with an acceptable reliability margin in the state of the art trench SiC MOSFETs by implementing a TiN/HfAlON gate stack.
author_names: Takuji Hosoi

Shuji Azumo

Yusaku Kashiwagi

Shigetoshi Hosaka

Kenji Yamamoto

Masatoshi Aketa

Hirokazu Asahara

Takashi Nakamura

Tsunenobu Kimoto

Takayoshi Shimura

Heiji Watanabe
title: Comprehensive and systematic design of metal/high k gate stack for high performance and highly reliable SiC power MOSFET
year: 2020

abstract: We report on a novel method of stacking multiple oxide layers on 4H SiC 20 kV IGBT. Instead of SiO2/SiC interface which is common for any SiC based MOS device, we found that the AlN/SiC interface would yield better results. We have performed 2D numerical simulations to analyze static characteristics for three combinations of dielectric stacks on IGBT: HfO2 SiO2, HfO2 AlN, and HfO2 SiO2 AlN (by maintaining the same equivalent oxide thickness value) In addition to higher transconductance (gm) and lower subthreshold swing (SS) the device with AlN/SiC interface offer comparatively lower RSP,ON and higher mobility with respect to temperature. Nevertheless, with a partial compromise on device characteristics improvement, insertion of SiO2 in the dielectric stack helps in suppressing the subthreshold current owing to higher band offset with respect to SiC. The turn off characteristics of the device is analysed using a clamped inductive circuit. Device with AlN/SiC has shown better dIc/dt and fall time compared to SiO2/SiC interface.
author_names: Siva Kotamraju

Pavan Vudumula
title: Improved Device Characteristics Obtained Using a Novel High K Dielectric Stack for 4H SiC n IGBT: HfO2 SiO2 AlN
venue: Materials Science Forum
year: 2019

abstract: Abstract We report promising results regarding the possible use of AlN or Al2O3 as a gate dielectric in 4H SiC MISFETs. The crystalline AlN films are grown by hot wall metal organic chemical vapor deposition (MOCVD) at 1100 degC. The amorphous Al2O3 films are grown by repeated deposition and subsequent low temperature (200 degC) oxidation of thin Al layers using a hot plate. Our investigation shows a very low density of interface traps at the AlN/4H SiC and the Al2O3/4H SiC interface estimated from capacitance voltage (CV) analysis of MIS capacitors. Current voltage (IV) analysis shows that the breakdown electric field across the AlN or Al2O3 is 3 MV/cm or 5 MV/cm respectively. By depositing an additional SiO2 layer by plasma enhanced chemical vapor deposition at 300 degC on top of the AlN or Al2O3 layers, it is possible to increase the breakdown voltage of the MIS capacitors significantly without having pronounced impact on the quality of the AlN/SiC or Al2O3/SiC interfaces.
author_names: Rabia Yasmin Khosa

J T Chen

Michael Winters

K Palsson

Robin Karhu

Jawad Ul Hassan

Niklas Rorsman

E O Sveinbjornsson
title: Electrical characterization of high k dielectrics for 4H SiC MIS devices
venue: Materials Science in Semiconductor Processing
year: 2019

abstract: Abstract The GaSb on GaAs growth was optimized for the fabrication of metal oxide semiconductor (MOS) capacitors (Caps) with low interface state trap density D it using in situ deposited amorphous silicon (a Si) interface passivation layer (IPL) and high k oxides. The best top surface with the average roughness R a =0.37 nm and with spiral type "step flow" growth mode was observed in the GaSb structure with the initial 0.5 mm grown at 410 degC and the top 0.5 mm grown at 485 degC. N and p type GaSb MOSCaps with reasonable capacitance voltage(C V) characteristics at room temperature (RT) were demonstrated using all in situ 0.5 nm a Si IPL and 10 nm Al 2 O 3 +HfO 2 or Al 2 O 3 A Si IPL was found essential for n MOSCaps but not in the case of p MOSCaps where comparable C V characteristics with a similarly low D it =1 2x10 12 cm 2 eV 1 were demonstrated without IPL.
author_names: Vadim Tokranov

Shailesh Madisetti

Michael Yakimov

Padmaja Nagaiah

Nikolai N Faleev

Serge Oktyabrsky
title: All in situ GaSb MOS structures on GaAs (001) Growth, passivation and high k oxides
year: 2013

abstract: Abstract A novel method of stacking dielectric layers on top of Silicon carbide (SiC) is proposed to address the most common Silicon dioxide (SiO2) SiC interface issues in SiC based metal oxide semiconductor (MOS) devices. Aluminum nitride (AlN) as an interfacial layer, instead of SiO2, between hafnium oxide (HfO2) and SiC showed improved device characteristics. However, incorporating SiO2 along with AlN as an interfacial layer is found to be the best way of stacking dielectric layers. This is concluded, based on the changes observed in the electrical characteristics of the device by intentionally varying lattice temperature (T) interface trap density (Dit) and junction field effect transistor (JFET) width. All the investigations are done in 4H SiC half cell planar n channel MOS field effect transistor (MOSFET) using commercially available technology computer aided design (TCAD) software sentaurus device. Theoretical calculations show good agreement with the simulated results, and are compared with the published results.
author_names: V S K Reddy

Siva Kotamraju
title: Improved device characteristics obtained in 4H SiC MOSFET using high k dielectric stack with ultrathin SiO2 AlN as interfacial layers
year: 2018

abstract: Due to its high Baliga and Johnson FoMs [1] [2] (Table I) GaN is a promising material for high voltage power and high frequency, high power RF applications [3] [6] Epitaxial integration of GaN on foreign substrates such as SiC [7] [14] [30] [32] sapphire [15] [16] and vastly lattice mismatched substrates including Si(111) [17] [24] Si(110) [25] [26] and miscut Si(100) [27] [29] have already been demonstrated to achieve similarly outstanding mobility, 2DEG charge density and sheet resistance, \mathrm{R}_{\mathrm{sh} (Fig. 1) Therefore, to realize compact integration of energy efficient applications such as integrated voltage regulators and RFFE power amplifiers for e.g. in lower power system on chip (SoC) it comes down to more than just a choice of the type of substrate, but more importantly, choosing the right transistor architecture. Such a GaN transistor will need to operate in enhancement mode (e mode) with low \mathrm{I}_{\mathrm{OFF} at 0V gate voltage, low gate leakage and provide high performance, i.e. low ON resistance \mathrm{R}_{\mathrm{ON} high drive current, good RF output power, and power efficiency, all at lower SoC compatible voltages [31] [32] As such, high k gate dielectric is needed to enable low gate leakage in e mode and scale the oxide \mathrm{T}_{\mathrm{oxe} to improve DIBL and \mathrm{I}_{\mathrm{OFF} and regrown n+ source/drain is needed for high performance [30] [32]
author_names: Han Wui Then

Sansaptak Dasgupta

Marko Radosavljevic

S Gardner

Seung Hoon Sung

Paul Fischer
title: High K Gate Dielectric GaN MOS HEMTs with Regrown n+ InGaN Source/Drain (Invited Paper)
venue: 2019 Device Research Conference (DRC)
year: 2019

abstract: Considerable challenges are encountered with polysilicon gate as the channel length and gate oxide thickness is aggressively reduced in case of CMOS devices when scaled into submicron regime. Metal gates and alternative gate dielectrics with high permittivity shows promising results to overcome the limitations like high gate resistance, high gate tunneling leakage current and boron penetration into the channel region. Therefore, there is immense interest in electrical characterization of a metaloxide semiconductor (MOS) capacitor structure with high K dielectrics. Here capacitance Voltage (C V) characteristics of metal oxide semiconductor (MOS) capacitor is plotted for high k dielectric materials such as, Aluminum Oxide (Al2O3) Hafnium Oxide (HfO2) Titanium Oxide (TiO2) Yttrium Oxide (Y2O3) as oxide material, Si as substrate and compared it with conventional SiO2 based MOS device. The MOSCAP structure was simulated to obtain the C V characteristics using TCAD. From the results various parameters such as threshold voltage, flat band voltage, interface trap density etc. were calculated. The simulation results were then verified with the reported experimental values.
author_names: Barnana Dutta

Shilpa Jaiswal

Sweta Kumari Jha

Divya Sharma

Manoj Mishra
title: Interface Trap Analysis of HIGH K MOSCAP Using T CAD
year: 2018

abstract: MOS Capacitors are demonstrated on 4H SiC using an octahedral ABO3 ferroic thin film as a dielectric prepared on several buffer layers. Five samples were prepared: ABO3 on SiC, ABO3 on SiC with a SiO2 buffer (10 nm and 40 nm) and ABO3 on SiC with an Al2O3 buffer (10nm and 40 nm) Depending on the buffer material the oxide forms in either the pyrochlore or perovskite phase. A better lattice match with the Al2O3 buffer yields a perovskite phase with internal switchable dipoles. Hysteresis polarization voltage loops show an oxide capacitance of 0.2 mF/cm2 in the accumulation region indicating a dielectric constant of ~120.
author_names: Stephen A O Russell

M R Jennings

T Dai

Fan Li

Dean Hamilton

Craig A J Fisher

Yogesh Kumar Sharma

Philip A Mawby

Amador Perez-Tomas
title: Functional Oxide as an Extreme High k Dielectric towards 4H SiC MOSFET Incorporation
venue: 2016 European Conference on Silicon Carbide Related Materials (ECSCRM)
year: 2016

abstract: In this report, we demonstrate a novel high temperature Hall effect sensor that is based on quasi free standing monolayer graphene epitaxially grown on high purity semiinsulating (SI) on axis 4H SiC(0001) substrate in a chemical vapor deposition process. To ensure statistical perspective, characteristics of 23 elements are determined as a function of temperature ranging from 300 to 770 K. Passivated with a 100 nm thick atomic layer deposited aluminum oxide, the sensor offers current mode sensitivity of 80 V/AT with thermal stability of 0.02%/K within the range between 300 and 573 K, and 0.06%/K between 573 and 770 K. The sensor's room temperature output voltage is monitored in the magnetic field from 300 to +300 mT and its offset voltage at 0 T is assessed. Its high temperature electrical properties are explained through a double carrier transport involving spontaneous polarization induced holes in the graphene layer and thermally activated electrons emitted from a deep acceptor level related to silicon vacancy \text{V}_{\textsf {Si}\textsf {1 /2 occupying the {k} site of the 4H SiC lattice. The sensor is compared with a previously reported one on vanadium compensated SI on axis 6H SiC(0001) The new sensor's applicability to magnetic field detection at high temperatures is verified.
author_names: Tymoteusz Ciuk

Beata Stanczyk

Krystyna Przyborowska

Dariusz Czolak

Artur Dobrowolski

Jakub Jagiello

Wawrzyniec Kaszub

Michal Kozubal

R W H Kozlowski

Pawel Kaminski
title: High Temperature Hall Effect Sensor Based on Epitaxial Graphene on High Purity Semiinsulating 4H SiC
venue: IEEE Transactions on Electron Devices
year: 2019

abstract: Top gated field effect transistors have been created from bilayer epitaxial graphene samples that were grown on SiC substrates by a vacuum sublimation approach. A high quality dielectric layer of Al2O3 was grown by atomic layer deposition to function as the gate oxide, with an e beam evaporated seed layer utilized to promote uniform growth of Al2O3 over the graphene. Electrical characterization has been performed on these devices, and temperature dependent measurements yielded a rise in the maximum transconductance and a significant shifting of the Dirac point as the operating temperature of the transistors was increased.
author_names: T Hopf

Konstantin Vassilevski

Enrique Escobedo-Cousin

Peter J B King

Nicolas G Wright

Anthony O'Neill

Alton B Horsfall

Jonathan P Goss

George Wells

Michael R C Hunt
title: Electrical Characterization of Epitaxial Graphene Field Effect Transistors with High k Al2O3 Gate Dielectric Fabricated on SiC Substrates
year: 2015