Search query: Adaptive Power Control Using Current Adjustment for Watt-Level Power Amplifiers in CMOS SOI

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abstract: This brief demonstrates the effectiveness of utilizing a 4 bit current steering digital to analog converter (DAC) as an adaptive power controller to adjust the dc quiescent current of a linear power amplifier as a function of the input signal power. A custom made metal semiconductor field effect transistor (MESFET) which is used as the amplifying transistor, and a current steering DAC have been integrated on the same substrate to minimize the power amplifier's form factor and mismatches between the power tracker and the MESFET. This design has been implemented in a 45 nm CMOS SOI global foundries (GFs) process with a nominal supply voltage of 0.9 V and provides 31.8 dBm of output power, 45% peak efficiency and 24 dB maximum power gain. Measurement results at 70 MHz reveal about 10% efficiency improvement at 6 dB power back off with continuous wave and 5% for standard 16 PSK EDGE modulated signals. The amplifier shows error vector magnitude of 5% and ACPR of 56.9 dBc at 400 kHz offset from the carrier frequency without digital pre distortion, while transmitting 27 dBm of modulated output power.
author_names: Soroush Moallemi

Payam Mehr

Kevin Grout

Trevor J Thornton

Jennifer Kitchen
title: Adaptive Power Control Using Current Adjustment for Watt Level Power Amplifiers in CMOS SOI
venue: IEEE Transactions on Circuits and Systems II: Express Briefs
year: 2020

abstract: Linear PA Design. Conventional High Efficiency Amplifier Modes. Class AB PAs at GHz Frequencies. Practical Design of Class AB PAs. Overdrive and the Class F Mode. Switching Mode Amplifiers for RF Applications. Switching PA Modes at GHz Frequencies. Signals, Modulation Systems, and PA Nonlinearities. Efficiency Enhancement Techniques. Power Amplifier Bias Circuit Design. Power Amplifier Architecture. PA Linearization Techniques.
author_names: Steve C Cripps
title: RF Power Amplifiers for Wireless Communications
year: 1999

abstract: Off state leakage is static power, current that leaks through transistors even when they are turned off. The other source of power dissipation in today's microprocessors, dynamic power, arises from the repeated capacitance charge and discharge on the output of the hundreds of millions of gates in today's chips. Until recently, only dynamic power has been a significant source of power consumption, and Moore's law helped control it. However, power consumption has now become a primary microprocessor design constraint; one that researchers in both industry and academia will struggle to overcome in the next few years. Microprocessor design has traditionally focused on dynamic power consumption as a limiting factor in system integration. As feature sizes shrink below 0.1 micron, static power is posing new low power design challenges.
author_names: Nam Sung Kim

Todd M Austin

David Blaauw

Trevor N Mudge

Krisztian Flautner

Jie S Hu

Mary Jane Irwin

Mahmut T Kandemir

Narayanan Vijaykrishnan
title: Leakage Current: Moore's Law Meets Static Power
venue: Computer
year: 2003

abstract: Advances in low power VLSI design, along with the potentially low duty cycle of wireless sensor nodes open up the possibility of powering small wireless computing devices from scavenged ambient power. A broad review of potential power scavenging technologies and conventional energy sources is first presented. Low level vibrations occurring in common household and office environments as a potential power source are studied in depth. The goal of this paper is not to suggest that the conversion of vibrations is the best or most versatile method to scavenge ambient power, but to study its potential as a viable power source for applications where vibrations are present. Different conversion mechanisms are investigated and evaluated leading to specific optimized designs for both capacitive MicroElectroMechancial Systems (MEMS) and piezoelectric converters. Simulations show that the potential power density from piezoelectric conversion is significantly higher. Experiments using an off the shelf PZT piezoelectric bimorph verify the accuracy of the models for piezoelectric converters. A power density of 70 @mW/cm^3 has been demonstrated with the PZT bimorph. Simulations show that an optimized design would be capable of 250 @mW/cm^3 from a vibration source with an acceleration amplitude of 2.5 m/s^2 at 120 Hz.
author_names: Shad Roundy

Paul K Wright

Jan M Rabaey
title: A study of low level vibrations as a power source for wireless sensor nodes
venue: Comput. Commun.
year: 2003

abstract: A nonlinear capacitance compensation technique is developed to help improve the linearity of CMOS class AB power amplifiers. The method involves placing a PMOS device alongside the NMOS device that works as the amplifying unit, such that the overall capacitance seen at the amplifier input is a constant, thus improving linearity. The technique is developed with the help of computer simulations and Volterra analysis. A prototype two stage amplifier employing the scheme is fabricated using a 0.5 /spl mu/m CMOS process, and the measurements show that an improvement of approximately 8 dB in both two tone intermodulation distortion (IM3) and adjacent channel leakage power (ACP1) is obtained for a wide range of output power. The linearized amplifier exhibits an ACP1 of 35 dBc at the designed output power of 24 dBm, with a power added efficiency of 29% and a gain of 23.9 dB, demonstrating the potential utility of the design approach for 3GPP WCDMA applications.
author_names: Mani Vaidyanathan

Lawrence E Larson
title: A capacitance compensation technique for improved linearity in CMOS class AB power amplifiers
venue: IEEE Journal of Solid State Circuits
year: 2004

abstract: A 45 GHz active phase shift Doherty PA is proposed and implemented in 45 nm SOI CMOS. The quarter wave length transmission line at the input of the auxiliary amplifier is replaced by an amplifier, increasing the gain and PAE by more than 1 dB and 5% while reducing the die area. Use of slow wave coplanar waveguides (S CPW) improves the PAE and gain by approximately 3% and 1 dB, and further reduces the die area. Two stack FET amplifiers are used as the main and auxiliary amplifiers, allowing a supply voltage of 2.5 V and increasing the output power. The active phase shift Doherty amplifier demonstrates a peak power gain and PAE of 8 dB and 20% at 45 GHz. It occupies 0.45 mm2, and at 6 dB back off power, the PAE is 21%
author_names: Amir Agah

Hayg Dabag

Bassel Hanafi

Peter M Asbeck

James F Buckwalter

Lawrence E Larson
title: Active Millimeter Wave Phase Shift Doherty Power Amplifier in 45 nm SOI CMOS
venue: IEEE Journal of Solid State Circuits
year: 2013

abstract: Recent work in field of neuroprosthetics has demonstrated that by observing the simultaneous activity of many neurons in specific regions of the brain, it is possible to produce control signals that allow animals or humans to drive cursors or prosthetic limbs directly through thoughts. As neuroprosthetic devices transition from experimental to clinical use, there is a need for fully implantable amplification and telemetry electronics in close proximity to the recording sites. To address these needs, we developed a prototype integrated circuit for wireless neural recording from a 100 channel microelectrode array. The design of both the system level architecture and the individual circuits were driven by severe power constraints for small implantable devices; chronically heating tissue by only a few degrees Celsius leads to cell death. Due to the high data rate produced by 100 neural signals, the system must perform data reduction as well. We use a combination of a low power ADC and an array of "spike detectors" to reduce the transmitted data rate while preserving critical information. The complete system receives power and commands (at 6.5 kb/s) wirelessly over a 2.64 MHz inductive link and transmits neural data back at a data rate of 330 kb/s using a fully integrated 433 MHz FSK transmitter. The 4.7times5.9 mm2 chip was fabricated in a 0.5 mum 3M2P CMOS process and consumes 13.5 mW of power. While cross chip interference limits performance in single chip operation, a two chip system was used to record neural signals from a Utah Electrode Array in cat cortex and transmit the digitized signals wirelessly to a receiver
author_names: Reid R Harrison

Paul T Watkins

Ryan J Kier

Robert O Lovejoy

Daniel J Black

Bradley Greger

Florian Solzbacher
title: A Low Power Integrated Circuit for a Wireless 100 Electrode Neural Recording System
venue: IEEE Journal of Solid State Circuits
year: 2007

abstract: The use of the fast Fourier transform in power spectrum analysis is described. Principal advantages of this method are a reduction in the number of computations and in required core storage, and convenient application in nonstationarity tests. The method involves sectioning the record and averaging modified periodograms of the sections.
author_names: Peter D Welch
title: The use of fast Fourier transform for the estimation of power spectra: A method based on time averaging over short, modified periodograms
year: 1967

abstract: A linearization technique based on the phase correction is proposed for a CMOS stacked FET power amplifier (PA) The linearizer employs a phase injection circuit as a main linearizer. The phase injection circuit presents envelope reshaped capacitance to the gate of a driver amplifier to correct for phase compression near saturation. It also helps with AM AM linearization. Hybrid bias circuit consisting of a diode and a resistor is also employed for static adaptive biasing, which allows the PA to meet stringent linearity requirement across the entire power range. Two stacked FET linear PAs with the proposed linearizers have been designed using a silicon on insulator (SOI) CMOS process at 1.88 and 0.9 GHz. The fabricated PAs show adjacent channel leakage ratios (ACLRs) better than 39 dBc with peak power added efficiencies (PAEs) of 44.3 and 49.2% at 1.88 and 0.9 GHz, respectively, using 3GPP uplink W CDMA signal.
author_names: Unha Kim

Youngwoo Kwon
title: A High Efficiency SOI CMOS Stacked FET Power Amplifier Using Phase Based Linearization
venue: IEEE Microwave and Wireless Components Letters
year: 2014

abstract: This paper describes the key technology and circuit design issues facing the design of an efficient linear RF CMOS power amplifier for modern communication standards incorporating high peak to average ratio signals. We show that most important limitations arise from the limited breakdown voltage of nanoscale CMOS devices and the large back off requirements to achieve the required linearity, both of which result in poor average efficiency. Two fundamentally different approaches to tackle these problems are presented along with silicon prototype measurements. In the first approach, transformer power combining and bias point optimization are used to increase the output power and linearity of the "analog" amplifier. In the second approach, a mixed signal "digital" polar architecture is employed, wherein the amplitude modulation is formed through an RF DAC structure.
author_names: Ali M Niknejad

Debopriyo Chowdhury

Jiashu Chen
title: Design of CMOS Power Amplifiers
venue: IEEE Transactions on Microwave Theory and Techniques
year: 2012