Search query: margin fail SRAM

Related papers:

abstract: As the semiconductor technology continues to scale, the stability and performance of embedded SRAM are growing concerns during the design and analysis stages. Maintaining an acceptable Static Noise Margin (SNM) in the embedded SRAM while scaling the minimum feature size and supply voltage of the integrated circuit (IC) becomes increasingly challenging. As a result, the manufacturing process window continues to shrink. This increases the difficulty for the failure analysis as many soft failures are induced by the reducing process margin. In this paper, a case study on an advanced technology node embedded SRAM soft fail was analyzed. Nanoprobing was employed at the room temperature to do SNM analysis at Metal 1 on the suspected location. Abnormal SNM window was observed at the room temperature analysis. Further analysis at high temperature on the same bit confirmed the soft failure bit. This correlates to the testing failure mode result. This case study is a good example for others who encounter same kind of the embedded SRAM soft failure.
author_names: C Q Chen

P T Ng

Francis Rivai

Y Z Ma

Pik Kee Tan

H Tan

Jeffery Lam

Zhihong Mai
title: Nanoprobing on the SRAM static noise margin (SNM) soft fail analysis
venue: 2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)
year: 2016

abstract: Static random access memory (SRAM) blocks occupy major chip area and are the primary contributors to leakage power in many modern systems. Scaling the supply voltage of SRAM macros is an efficient method to reduce total chip power. It is difficult to achieve an SRAM cell with stable operation at lowvoltage due to increasing variations in process, voltage and temperature. In the sub threshold region, conventional 6 T SRAMs fail to deliver density and yield requirements due to reduced static noise margin (SNM) poor writability, limited number of cells per bit line, and reduced bit line sensing margin. This paper reviews state of the art bit cell structures with good stability under sub threshold condition in terms of technology parameters.
author_names: Dr E Jebamalar Leavline
title: Survey on Stability of Low Power SRAM Bit Cells
year: 2017

abstract: A feasibility study on Ferroelectric Shadow SRAMs (FE SRAMs) was performed using circuit simulations. To take into account design constraints set by the cell transistor variability, a simple operation margin search algorithm was proposed and used, which requires only pass/fail information from multiple transient simulations. It was found that stable dynamic recall operations can be achieved by using small enough ferroelectric capacitors, and that non volatile write energy of well below 10 fJ/bit can be expected, adding minimal area penalty and performance degradation to the base SRAM cell. Scalability to advanced technology nodes is also anticipated. The results show that the FE SRAM would be an ideal non volatile memory solution for ultra low power applications, such as sensor networks powered by energy harvesting.
author_names: Kiyoshi Takeuchi

Masaharu Kobayashi

Toshiro Hiramoto
title: A Feasibility Study on Ferroelectric Shadow SRAMs Based on Variability Aware Design Optimization
venue: IEEE Journal of the Electron Devices Society
year: 2019

abstract: A method for achieving variability aware design for ferroelectric shadow SRAM (FE SRAM) is proposed, which makes it possible to determine the operation margin against random VTH variation by only using pass/fail information from multiple transient circuit simulations. A systematic study using this method predicts that properly designed FE SRAMs using Hf based ferroelectric capacitors, will have sufficient operation margin and scalability.
author_names: Kiyoshi Takeuchi

Masaharu Kobayashi

Toshiro Hiramoto
title: A Feasibility Study on Ferroelectric Shadow SRAMs Using a New Variability Design Scheme
venue: 2019 Electron Devices Technology and Manufacturing Conference (EDTM)
year: 2019

abstract: A deconvolution error avoidance technique in Richardson Lucy deconvolution (RLdeconv) is proposed, which is used for inversely analysing the SRAM margin variations caused by the Random Telegraph Noise (RTN) The proposed technique reduces the phase difference between the deconvoluted RTN distribution and feedback gain in the maximum likelihood (MLE) gradient iteration cycles. This avoids an unwanted positive feedback, resulting in a significant decrease in probability of ringing occurrence. The effects of the proposed technique on the deconvolution process are demonstrated. A quicker convergence benefit of the RLdeconv algorithm is also observed. It has been demonstrated that the proposed technique reduces its relative deconvolution errors by 100 times compared with the conventional RL deconv. This provides an increase in accuracy of the fail bit count prediction by over 2 orders of magnitude while accelerating its convergence speed by 33times of the conventional one.
author_names: Hiroyuki Yamauchi

Worawit Somha
title: A Deconvolution Error Avoidance Technique in Richardson Lucy Method
year: 2017

abstract: Negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI) cause SRAM stability degradation during its lifetime. Hence, some of the SRAM cells that are functional initially may fail due to aging after usage. This causes field failures of the shipped chips. In this paper we focus on screening out these SRAM cells which may fail after aging during post fabrication testing. We propose wordline overdriving test (WODT) a novel predictive testing method for SRAMs. During the test we overdrive the SRAM wordline to simulate the effect of aging, hence we are able to detect the cells that will fail after aging over a desired lifetime. We compare our proposed method with low VDD test, and show that WODT outperforms low VDD test with a large margin by achieving dramatically lower quality loss.
author_names: Jizhe Zhang

Sandeep Kumar Gupta
title: Wordline overdriving test: An effective predictive testing method for SRAMs against BTI aging
venue: 2017 18th International Symposium on Quality Electronic Design (ISQED)
year: 2017

abstract: This letter evaluates and analyzes the impacts of random variations on cell stability and write ability of low voltage SRAMs using monolayer and bilayer transition metal dichalcogenide (TMD) devices based on ITRS 2028 (5.9 nm) node with the aid of atomistic TCAD mixed mode simulations. Our study indicates that, for 6T SRAM, the monolayer/bilayer TMD devices may fail to provide the 6s yield requirement for read static noise margin (RSNM) due to severe metal gate work function variation in spite of their excellent electrostatics, and hence circuit techniques, such as bootstrapped dynamic power rails or the standard 8T cell, are needed. Besides, RSD as a major concern of TMDs should be less of an issue for near /sub threshold SRAMs for ultra low power applications. For the standard 8T cell structure, the RSNMs of both monolayer and bilayer 8T SRAMs improve significantly, and the bilayer 8T SRAM exhibits better write static noise margin (WSNM) In addition, write assist techniques (including negative bit line, boosted word line, and lower cell supply) for improving WSNM are examined and shown to be more effective for monolayer 8T SRAMs than the bilayer counterparts.
author_names: Chang-Hung Yu

Pin Su

Ching-Te Chuang
title: Impact of Random Variations on Cell Stability and Write Ability of Low Voltage SRAMs Using Monolayer and Bilayer Transition Metal Dichalcogenide (TMD) MOSFETs
venue: IEEE Electron Device Letters
year: 2016

abstract: In this paper, we develop an analytical PUF model based on a compact FinFET transistor model that calculates the PUF stability (i.e. PUF static noise margin (PSNM) for FinFET based SRAMs. The model enables a quick design space exploration and may be used to identify critical parameters that affect the PSNM. The analytical model is validated with SPICE simulations. In our experiments, we analyze the impact of process variation, technology, and temperature on the PSNM. The results show that the analytical model matches very well with the simulation model. From the experiments we conclude the following: (1) nFET variations have a larger impact on the PSNM than pFET (1.5% higher PSNM in nFET variations than pFET variations at 25degC) (2) high performance SRAM cells are more skewed (1.3% higher PSNM) (3) the reproducibility increases with smaller technology nodes (0.8% PSNM increase from 20 to 14 nm) (4) increasing the temperature from 10degC to 120degC leads to a PSNM change of approximately 1.0% for an extreme nFET channel length.
author_names: Shayesteh Masoumian

Georgios N Selimis

Roel Maes

Geert Jan Schrijen

Said Hamdioui

Mottaqiallah Taouil
title: Modeling Static Noise Margin for FinFET based SRAM PUFs
venue: 2020 IEEE European Test Symposium (ETS)
year: 2020

abstract: In recent years improvement in the design of SRAM cell increases drastically. The two major factors which have to be taken care are power dissipation and the noise margin of the SRAM cell. The power is subdivided into two groups that are switching power and standby power. The leakage current plays an important role in the power dissipation and has to be taken care. The noise margin also categorized as read margin and write margin. The purpose of this paper is to analyze and optimize the SRAM cell operation with respect to power and also measure the noise margin. The results show the low power operation of SRAM cell with relatively improved noise margin.
author_names: Sunil Kumar Ojha

O P Singh

G R Mishra

P R Vaya
title: Analysis of SRAM Cell for Low Power Operation and Its Noise Margin
year: 2019

abstract: Decreasing the power consumption and growing the noise margin have turn out to be two imperative topics in the artwork SRAM design. Recent works have proven that the traditional 6T SRAM suffer stability degradation, as a consequence,8T and 10T designs had been implemented to enhancing the cellular stability. The objective of this work is to describe the design and cadence implementation of a 256 byte SRAM using 90nm CMOS technology with 3 different architectures (1)6T SRAM (2)8T SRAM (3) 10T SRAM and their comparison is done on the factor of static noise margin. By using this analysis, we can clarify the stability of memory cells.
author_names: Anjana R Krishnan

G Shekar
title: Static Noise Margin Analysis of Various SRAM Array
venue: 2020 International Conference on Communication and Signal Processing (ICCSP)
year: 2020