Search query: layout MOS matching

Related papers:

abstract: This article describes an experimental comparative study of the matching between the Octo conventional (octagonal gate geometry) and Conventional (rectangular gate shape) n channel Metal Oxide Semiconductor (MOS) Field Effect Transistors (MOSFETs) which were manufactured in an 130 nm Silicon Germanium Bulk Complementary MOS (CMOS) Integrated Circuits (ICs) technology and exposed to different X rays Total Ionizing Doses (TIDs) under the on state bias conditions. The results indicate that the Octo layout style with alpha \alpha angle equal to 90deg and a cut factor of 50% for MOSFETs is capable of boosting the device matching by at least 56.1% on average, regarding the electrical parameters studied (Threshold Voltage and Subthreshold Swing) as compared to those found in the Conventional MOSFET counterparts, considering that they present the same bias conditions and regarding different TIDs. This happens due to the Longitudinal Corner Effect (LCE) Parallel MOSFETs with Different Channel Length Effect (PAMDLE) and Deactivation of Parasitic MOSFETs in the Bird's Beak Regions Effect (DEPAMBBRE) which are present in the Octo MOSFETs. Therefore, the Octagonal layout style can be considered as an alternative hardness by design (HBD) layout strategy to boost the electrical performance and TID tolerance of MOSFETs enabling analog or radio frequency CMOS ICs applications.
author_names: Vinicius Vono Peruzzi

William Souza da Cruz

Gabriel Augusto da Silva

Eddy Simoen

Cor Claeys

Salvador Pinillos Gimenez
title: Using the Octagonal Layout Style for MOSFETs to Boost the Device Matching in Ionizing Radiation Environments
venue: IEEE Transactions on Device and Materials Reliability
year: 2020

abstract: Digital Object Identifier 10.29292/jics.v15i2.185 Abstract This paper describes an experimental comparative study of the mismatching between the Diamond (hexagonal gate geometry) and Conventional (rectangular gate shape) n channel Metal Oxide Semiconductor (MOS) Field Effect Transistors (MOSFETs) which were manufactured in an 130 nm Silicon Germanium Bulk Complementary MOS (CMOS) technology and exposed to different X rays Total Ionizing Doses (TIDs) The results indicate that the Diamond layout style with an alpha angle equal to 90 for MOSFETs is capable of reducing the device mismatching by at least 17% regarding the electrical parameters studied as compared to the Conventional MOSFET (CnM) counterparts. Therefore, the Diamond layout style can be considered an alternative hardness by design (HBD) layout strategy to boost the electrical performance and TID tolerance of MOSFETs.
author_names: Vinicius Vono Peruzzi

William Souza da Cruz

Gabriel Augusto da Silva

Eddy Simoen

Cor Claeys

Salvador Pinillos Gimenez
title: Using the Hexagonal Layout Style for MOSFETs to Boost the Device Matching in Ionizing Radiation Environments
year: 2020

abstract: This paper introduces a novel layout style with a reasonable generation algorithm for MOS analog modules in order to guarantee complete routing and perfect matching of devices. The introduced layout style is applicable to a variety of essential MOS analog circuits. To the transistor layout, we introduce a symmetrical row based structure where all transistors are transformed to matched pairs by duplicating sub netlists or decomposing into sub transistors. Further to these transistors, a generation algorithm is proposed to maximize the diffusion sharing along the current paths. Several design examples are used to demonstrate the effectiveness of the algorithm.
author_names: Bo Liu

Shigetoshi Nakatake

Bo Yang

Gong Chen
title: Twin row style for MOS analog layout
venue: 2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)
year: 2016

abstract: The accuracy and performance of analog integrated circuits often depends on the accuracy of component matching.Matching accuracy is guaranteed by the manufacturing process and layout design,which directly affect the performance of the final circuit.Based on analysis of CMOS analog layout design matching mechanism and study of common matching methods in paper,design methods is deeply discussed on the MOS transistor's common centroid layout of interdigitated structure.a basic amplifier layout is designed,and the detailed matching of input differential transistors and the current mirror are designed.
author_names: Li Liang
title: A CMOS Amplifier Layout Design Based on Matching Technology
year: 2012

abstract: A test chip with NMOS transistor pairs with different layout styles to study its influence on matching is presented. Common centroid structures are found to have much better matching performance than finger style structures. They show no systematic mismatch, and have a matching dependence on the channel area which is in agreement with measurement results on simple rectangle structures. Under die stress induced by packaging, finger style transistor pairs show a spread on transistor matching up to 5 times higher than the value predicted by only considering random fluctuation of the channel area.
author_names: J Bastos

Michel S J Steyaert

B Graindourze

Willy M C Sansen
title: Matching of MOS transistors with different layout styles
venue: Proceedings of International Conference on Microelectronic Test Structures
year: 1996

abstract: A new methodology for statistical mismatch analysis of MOS transistor pairs is presented. Size and shape, as well as placement and partitioning of devices are taken into account by using a statistical approach based on stochastic process theory. The method depends on device geometry and mutual distances between devices and has been developed by first defining a transformation which maps the statistical behavior of the technological parameters considered as sources of errors into the behavior of device parameters. A useful expression for the parameter mismatch variance depending on the layout has been derived by assuming a particular form for the autocorrelation function of process parameters. Finally, the method has been used to analyze and compare the mismatch effect on several interdigitated and common centroid structures.
author_names: Massimo Conti

Paolo Crippa

Simone Orcioni

Claudio Turchetti
title: Layout based statistical modeling for the prediction of the matching properties of MOS transistors
year: 2002

abstract: Two1 novel automatic generation methods for analog layout a symmetrical twin row method for MOS transistors and a twisted common centroid method for capacitor arrays are introduced. Based on the proposed layout styles and the corresponding algorithms, the symmetry and common centroid placement patterns for analog devices are realized to guarantee matching properties. On this basis, as the most prominent contribution of this article, channel routing based algorithms for the proposed layout styles are presented and could achieve 100% routability due to well arranged devices and corresponding low routing complexity. The algorithms benefits include a small layout area that maximizes the diffusion sharing of MOS transistors and less routing layer usage for common centroid device arrays. Moreover, we successfully applied our algorithms to the layout designs of two typical analog modules including a two stage operating amplifier and a Successive Approximation Register Analog to Digital Converter (SAR ADC) The generated layouts and the circuit simulation results demonstrate the effectiveness of our algorithms in terms of their routability and matching properties. Our algorithms can also be extended to apply to a variety of essential MOS analog circuits.
author_names: Bo Liu

Gong Chen

Bo Yang

Shigetoshi Nakatake
title: Routable and Matched Layout Styles for Analog Module Generation
venue: ACM Trans. Design Autom. Electr. Syst.
year: 2018

abstract: Analysis of two layout designs used in the realization of MOS continuous time integrated filters is presented. The effect of MOS parasitic capacitances is thoroughly studied and compared in the two layout design techniques. It is found that one layout method performs well at high frequencies or high Q, at the expense of increased harmonic distortion in comparison with the other method. A tradeoff between transistor matching and sensitivity to MOS intrinsic parasitic capacitances is revealed. A set of performance graphs are developed with the ratio of parasitic to integrating capacitance, C/sub P//C, as a parameter. These graphs are useful in the design of high performance MOS continuous time integrated filters.
author_names: S V Smith

Chung-Chih Hung

Shu-Chuan Huang
title: Layout design considerations in MOS continuous time integrated filters
venue: Proceedings of APCCAS'94 1994 Asia Pacific Conference on Circuits and Systems
year: 1994

abstract: A sensefet monitoring is used for overload, open load detection and load current analog feedback. The sensefet matching properties to the main power mos represent the main quality factor of the device. Its current should be proportional to the main power one, maintaining the same coefficient over the entire temperature and biasing working range. In this work the effects of the edge cells layout and process are analyzed by the help of 3D device simulations. The causes for the real to theoretical ratio mismatch and the drift behavior versus the temperature are put into evidence. The corrective actions allow to reach 1/2% of drift in the range 40degC to 150degC. Only technological considerations are here faced, concerning the construction and optimization of the structure.
author_names: Rosalia Germana
title: Power mos current sensefet temperature drift study and improvement by the help of 3D simulations
venue: 2012 24th International Symposium on Power Semiconductor Devices and ICs
year: 2012

abstract: Based on existing low voltage BCD technology,a 1mm 600VBCD process was developed in co operation with CSMC.In this process,600VLDMOS and high voltage isolation islands were integrated.A high voltage MOS gate drive circuit was designed and fabricated based on the process.With two independent inputs,the driver circuit had 1ms deadtime.Over current and under voltage protection circuit were integrated into the circuit.A double pulse level shifter was used to shift level from 15Vto 615V,and the layout of high side was reduced by 12%.Tape out results showed that the circuit had a floating bias voltage up to 750V,a rise time of 50ns at both high and low output,a delay matching time of 150ns,and maximum output current above 2A.The chip had rapid response and high reliability.
author_names: Fang Jian
title: High Voltage MOS Gate Drive Circuit Based on 1mm 600 V BCD Process
year: 2013