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abstract: Semiconductor Device Physics and Designprovides a fresh and unique teaching tool. Over the last decade device performances are driven by new materials, scaling, heterostructures and new device concepts. Semiconductor devices have mostly relied on Si but increasingly GaAs, InGaAs and heterostructures made from Si/SiGe, GaAs/AlGaAs etc have become important. Over the last few years one of the most exciting new entries has been the nitride based heterostructures. New physics based on polar charges and polar interfaces has become important as a result of the nitrides. Nitride based devices are now used for high power applications and in lighting and display applications. For students to be able to participate in this exciting arena, a lot of physics, device concepts, heterostructure concepts and materials properties need to be understood. It is important to have a textbook that teaches students and practicing engineers about all these areas in a coherent manner. Semiconductor Device Physics and Designstarts out with basic physics concepts including the physics behind polar heterostructures and strained heterostructures.Important devices ranging from p n diodes to bipolar and field effect devices is then discussed. An important distinction users will find in this book is the discussion presented on device needs from the perspective of various technologies. For example, how much gain is needed in a transistor, how much power, what kind of device characteristics are needed. Not surprisingly the needs depend upon applications. The needs of an A/D or D/A converter will be different from that of an amplifier in a cell phone. Similarly the diodes used in a laptop will place different requirements on the device engineer than diodes used in a mixer circuit. By relating device design to device performance and then relating device needs to system use the student can see how device design works in real world. This book is comprehensive without being overwhelming.The focus was to make this a useful text book so that the information contained is cohesive without including all aspects of device physics. The lesson plans demonstrated how this book could be used in a 1 semester or 2 quarter sequence.
author_names: Umesh K Mishra

Jasprit Singh
title: Semiconductor Device Physics and Design
year: 2007

author_names: Mary Yvonne Lanzerotti

Robert W Keyes
title: Introductory Semiconductor Device Physics for Chip Design and Manufacturing
year: 2018

abstract: OF DISSERTATION NANOSTRUCTURED SEMICONDUCTOR DEVICE DESIGN IN SOLAR CELLS We demonstrate the use of embedded CdS nanowires in improving spectral transmission loss and the low mechanical and electrical robustness of planar CdS window layer and thus enhancing the quantum efficiency and the reliability of the CdS CdTe solar cells. CdS nanowire window layer enables light transmission gain at 300nm 550nm. A nearly ideal spectral response of quantum efficiency at a wide spectrum range provides an evidence for improving light transmission in the window layer and enhancing absorption and carrier generation in absorber. Nanowire CdS/CdTe solar cells with Cu/graphite/silver paste as back contacts, on SnO2/ITO soda lime glass substrates, yield the highest efficiency of 12% in nanostructured CdS CdTe solar cells. Reliability is improved by approximately 3 times over the cells with the traditional planar CdS counterpart. Junction transport mechanisms are delineated for advancing the basic understanding of device physics at the interface. Our results prove the efficacy of this nanowire approach for enhancing the quantum efficiency and the reliability in windowabsorber type solar cells (CdS CdTe, CdS CIGS and CdS CZTSSe etc) and other optoelectronic devices. We further introduce MoO3 x as a transparent, low barrier back contact. We design nanowire CdS CdTe solar cells on flexible foils of metals in a superstrate device structure, which makes low cost roll to roll manufacturing process feasible and greatly reduces the complexity of fabrication. The MoO3 layer reduces the valence band offset relative to the CdTe, and creates improved cell performance. Annealing as deposited MoO3 in N2 reduces series resistance from 9.98 O/cm to 7.72 O/cm, and hence efficiency of the nanowire solar cell is improved from 9.9% to 11% which efficiency comparable to efficiency of planar counterparts. When the nanowire solar cell is illuminated from MoO3 x /Au side, it yields an efficiency of 8.7% This reduction in efficiency is attributed to decrease in Jsc from 25.5mA/cm 2 to 21mA/cm due to light transmission loss in the MoO3 x /Au electrode. Even though these nanowire solar cells, when illuminated from back side exhibit better performance than that of nanopillar CdS CdTe solar cells, further development of transparent back contacts of CdTe could enable a low cost roll to roll fabrication process for the superstrate structure nanowire solar cells on Al foil substrate.
author_names: Hongmei Dang
title: Nanostructured Semiconductor Device Design in Solar Cells
year: 2019

abstract: A physics based compact gallium nitride power semiconductor device model is presented in this work, which is the first of its kind. The model derivation is based on the classical drift diffusion model of carrier transport, which expresses the channel current as a function of device threshold voltage and externally applied electric fields. The model is implemented in the Saber(r) circuit simulator using the MAST hardware description language. The model allows the user to extract the parameters from the dc I V and C V characteristics that are also available in the device datasheets. A commercial 80 V EPC GaN HEMT is used to demonstrate the dynamic validation of the model against the transient device characteristics in a double pulse test and a boost converter circuit configuration. The simulated versus measured device characteristics show good agreement and validate the model for power electronics design and applications using the next generation of GaN HEMT devices.
author_names: Ramchandra M Kotecha

Yuzhi Zhang

Arman Ur Rashid

Nan Zhu

Tom Vrotsos

Homer Alan Mantooth
title: A physics based compact gallium nitride power semiconductor device model for advanced power electronics design
venue: 2017 IEEE Applied Power Electronics Conference and Exposition (APEC)
year: 2017

abstract: IEGTs are one of the promising candidates for replacing GTOs in high voltage applications in 4.5 kV range. The injection enhancement effect of IEGT structure with the deep trench MOS gate and/or the wide cell design successfully reduces the voltage drop in the N base. In this paper, we discuss the device physics and design concept of the injection enhancement effect for not only the trench structure but also the planar structure.
author_names: Ichiro Omura

Tsuneo Ogura

Koichi Sugiyama

H Ohashi
title: Carrier injection enhancement effect of high voltage MOS devices device physics and design concept
venue: Proceedings of 9th International Symposium on Power Semiconductor Devices and IC's
year: 1997

abstract: In this paper, process, device, and electromagnetic simulations are combined to produce a distributed nonlinear model for an LDMOS RF power transistor. The simulation challenges are handled by using multiple simulators, each with a suitable role in the modeling process. Semiconductor fabrication and device operation are performed through the process and device technology computer aided design (TCAD) tool. The outcome from the TCAD simulations are used to generate a nonlinear compact model for a small section of the device. To form the complete transistor model, many small sections of the compact model are connected by a large scale interconnect network, which is modeled based on electromagnetic (EM) simulations. For convenient use in circuit simulator, the distributed nonlinear model is implemented by a script generated comprehensive netlist. It is demonstrated that this purely simulation based model can accurately predict device behavior under DC, small signal, and large signal tests, and is useful for first pass computer aided design before wafer fabrication.
author_names: Dan Lamey

Lei Zhang

Hernan Rueda

Humayun Kabir

Rick Sweeney

Kevin Kim
title: Device physics and EM simulation based modeling methodology for LDMOS RF power transistors
venue: 2017 IEEE MTT S International Conference on Numerical Electromagnetic and Multiphysics Modeling and Optimization for RF, Microwave, and Terahertz Applications (NEMO)
year: 2017

abstract: Abstract We introduce a new platform called KdotPsoft, to model and simulate semiconductor quantum wells (QWs) and multiple QW (MQW) systems. It is suitable to design and study quantum cascaded lasers, vertical cavity surface emitting laser, etc in conjunction with experiment and fabrication. For fundamental physics and device physics applications, KdotPsoft is an ideal platform to model, simulate and study semiconductors QWs and MQW structures for fundamental physics and device physics applications. It can study MQW based structures such as quantum cascaded lasers (QCL) vertical cavity surface emitting laser (VCSEL) etc. KdotPsoft is based on the 16 band k*p perturbation theory model and it supports all conventional semiconductor materials, and also can works for dilute nitride and bismide doped semiconductors. As a demonstration, we will show a study an example case of lattice matched GaNBiAs/GaAs QWs and show its major results, such as the energy dispersion curves, optical gain spectra and electron hole wave functions. At a larger scale, it can be used to comprehensively study the band lineups, energy dispersion relation, DOS, polarization dependent transition matrix element strengths, optical gain/absorption spectra, spontaneous emission rate, radiative current density, electric field effects on the QW, etc. Advanced users may note that the development of the platform was done using Fortran and Python. We will strive to make KdotPsoft available as a independent platform or a Matlab toolbox in the future.
author_names: Sumanta Bose

Zhigang Song

Weijun Fan

Dawei Zhang
title: KdotPsoft: Modelling and Simulation of Semiconductors and Device Physics
year: 2017

abstract: Abstract As one of the most appealing two dimensional materials, graphene (Gr) has attracted tremendous research interest in optoelectronic device applications for its plenty of exceptional electrical and optical properties. The emergence of Gr/semiconductor hybrid heterostructures provides a promising platform for assembling high performance optoelectronic devices that can overcome intrinsic limitations of Gr. However, although significant achievements have been made, many challenges still exist. Here, we comprehensively review the progress in the development of various optoelectronic devices based on Gr/semiconductor hybrid heterostructures, including /group II VI nanostructures, /group III V semiconductors, /group IV semiconductors, /metal oxides and /other semiconductors, in terms of the device design, device performance and physics, processing techniques for performance optimization, etc. In the final section, conclusions of the existing techniques are presented and future challenges in optoelectronic applications of Gr/semiconductor hybrid heterostructures are addressed.
author_names: Chao Xie

Yi Wang

Zhi-Xiang Zhang

Di Wang

Lin-Bao Luo
title: Graphene/Semiconductor Hybrid Heterostructures for Optoelectronic Device Applications
year: 2018

abstract: The requirements of high speed and performance and cost effectiveness demand of VLSI chips a continuing push in miniaturization. As a consequence, the design rule (or the effective gate length) has been reduced from several microns down to 0.1 mm envisioned within a few years. While the expected 256 Mb chip requires the use of quarter micron design rules, it is expected that we will need 0.1 0.15 mm rules for gigabit chips, and the extrapolation of the down scaling trends will extend the design rules to sub 0.1 mm for a terabit memory chip in the near future. With this scenario for VLSI technology development, the deep understanding of the device physics governing device operation is the key to successful device design, as different physical mechanism impose different level of effects on different device scales.
author_names: J Zhou

David K Ferry
title: 3D Discrete Dopant Effects on Small Semiconductor Device Physics
year: 1996

abstract: Experimental facilities for measuring noise were developed. These included the fabrication of a test station for measuring noise at low frequency <100 kHz) in both high and low impedance devices and at high frequency <18 GHz) These new test stations are being used to study current noise in quantum cascade lasers. In addition to noise measurements under DC operation, a 12 Gb/s bit error rate tester (BERT) was installed and used to test the noise models for surface emitting lasers.
author_names: Dr Holger Schmidt Rajeev J Ram

M Abraham

Harry L T Lee

Steven Gregory Patterson

Kevin P Pipe

Mehmet Fatih Yanik

Margaret Wang
title: Semiconductor Lasers Device Physics and Applications
year: 2000