Search query: microchip technology flash

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abstract: Stencil Printing Technology is currently a high throughput process for solder or adhesive materials deposition used in SMT and bumping process. With growth of heterogenous integration in the advanced semiconductor packaging is driving more stringent fine pitch application requirements. Disadvantages of Stencil Printing Technology for ultrafine pitch application, i.e. MicroLED Chip Attach, is restricted by stencil design (opening size) which resulted in frequent clogging of stencil and thus increase cost. Hence a "stencil less" technology for solder paste deposition via novel tape or film transfer process will be studied in this work. The paste transfer under development will require the use of low temperature profile to enable paste to deposit onto the substrate (receiver) and maintain structural integrity, probably in a semi state of paste form which can be subjected for Si die or microchip attach for reflow soldering to complete good solder interconnection during mass assemblies process.
author_names: Yam Lip Huei

Lo Yee Ting

Chong Kim Hui

B Senthil Kumar

Chan Li-san
title: Solder Paste Transfer Via Pattern Tape Technology
venue: 2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)
year: 2020

abstract: This paper presents a brief review on smart grids. Environmental destruction that is marked by high CO2 level or green house gas emissions due to excessive use of fossil fuels is a serious challenge that must be minimized immediately. One of the most prominent impact is the destruction of natural ecosystems such as forest fires due to very high temperature, rising sea level, flash flood, melting of iceberg in the north and south poles and uncertain natural climates. From the energy sec tor that contribute most to global warming is the power generation sector. Currently there are still many power plants that use fossil fuels such as petroleum and coal as the main source of turbine drive in generating electrical energy. Renewable energy is capable of generating electrical energy without generating and increasing greenhouse gases. Current renewable energy utilization trends continue to increase which contributes to the birth of the smart grid concept. Current electricity transmission and distribution networks can be categorized as conventional electricity networks because they have not been able to provide excellent service and present real time data. This network has not been able to provide reliability, safety and efficiency in supplying electrical energy even not yet have the flexibility to be integrated with the generation of renewable energy or microgrid. So the introduction of smart grid technology is a necessity to reduce the impact of global warming while encouraging efficiency, reliability and effective governance in the supply of electrical energy.
author_names: Alicia Tang Yee Chong

Moamin A Mahmoud

Fung-Cheng Lim

Hairoladenan Kasim
title: A review of Smart Grid Technology, Components, and Implementation
venue: 2020 8th International Conference on Information Technology and Multimedia (ICIMU)
year: 2020

abstract: 3D NAND flash memory has become a state of the art technology of non volatile memory. Different from planar 2D NAND flash memory, polysilicon channel is adopted by 3D NAND flash memory. Because of grain boundaries, device suffers from significant performance variation. This work investigates the effect of grain boundary on MONOS structured NAND flash memory performance by TCAD simulation. The variability of electrical performance was demonstrated under random grain boundary structure. To further understand the grain boundary effect on device performance, grain size, grain boundary position and grain boundary angle was investigated. When grain size is smaller than gate length, it shows a larger threshold voltage variation. When grain size is big enough, the position of grain boundary matters. When grain boundary locates right below the middle of the gate, threshold voltage shifts the most. Moreover, comparing to vertical grain boundaries, the threshold voltage shifts up for grain boundaries in parallel to channel. This work includes a comprehensive study about the effect of grain boundary on 3D NAND flash memory performance. It could be used for the optimization of polysilicon process technology.
author_names: Sinan Yang

Xuan Tian

Jinghan Zhang

Zhe Song

Liang Li

Ming Li

Liming Gao
title: Investigation of Grain Boundaries Effect on 3D NAND Flash by TCAD Simulation
venue: 2020 21st International Conference on Electronic Packaging Technology (ICEPT)
year: 2020

abstract: Scaling prospects and challenges of the embedded split gate SuperFlash(r)(ESF) memory technology to 28 nm and smaller process nodes are presented. We further propose a novel process integration scheme to build SuperFlash(r) memory with a 14nm process node. On going scaling and optimization of ESF memory technology continues to enable new applications such as machine learning in which an ESF memory array is used to implement vector matrix multiplications for neural networks. To demonstrate this use case, the capability and performance of 40 and 28 nm split gate SuperFlash(r) cells in low power sub threshold region is presented.
author_names: Nhan Do

Steven Lemke

Hieu Van Tran

Vipin Tiwari

Mark Reiten
title: Scaling of Split Gate Flash Memory for Embedded Controllers and Machine Learning Applications
venue: 2020 International Symposium on VLSI Technology, Systems and Applications (VLSI TSA)
year: 2020

abstract: Hardware based neural networks are expected to be a new computing breakthrough beyond conventional von Neumann architecture because of their low power operations. In this work, we introduce operation scheme of neural networks using NAND flash memory cell as analogue and binary state synaptic devices. We report that NAND flash memory has excellent density and low error rate when compared to the results of RRAM.
author_names: Sungtae Lee

Jongho Lee
title: Neuromorphic Technology Utilizing Nand Flash Memory Cells
venue: 2020 China Semiconductor Technology International Conference (CSTIC)
year: 2020

abstract: NOR Flash has stopped scaling for many years. However, recently there are increasingly new demands of NOR Flash in various 5G and IoT applications or wearable devices that strongly require new technology advancement of NOR. In this work, we developed a new vertical 2T (V2T) NOR Flash architecture that provides not only scaling capability but also low power solutions. We leveraged the process of standard 3D NAND to develop a vertical 2T NOR that produces even smaller cell size than conventional planar 1T NOR. Advanced high K metal gate (HK/MG) integration is developed to provide high performance BE MANOS charge trapping device with excellent 1M endurance and retention reliability. The 2T NOR architecture provides low voltage read ~1V) that is compatible with advanced CMOS circuits without charge pumping to save power. We also suggest future technology extensions of the V2T NOR by adopting the ferroelectric memory devices (FeFET) and the 3DIC chiplets integration to broaden the applications fields of NOR technology in embedded Flash and computing in memory (CIM)
author_names: Hang-Ting Lue

Tzu-Hsuan Hsu

Teng-hao Yeh

Wei-Chen Chen

Chieh Roger Lo

Chiatze Huang

Guan-Ru Lee

Chia-Jung Chiu

Keh-Chung Wang

Chih-Yuan Lu
title: A Vertical 2T NOR (V2T) Architecture to Enable Scaling and Low Power Solutions for NOR Flash Technology
venue: 2020 IEEE Symposium on VLSI Technology
year: 2020

abstract: The flash industry has continuously produced game changing innovations in density, latency, and form factors resulting in large cost performance benefits. To address the wide spectrum of storage demands coming from phone/IoT devices, mobile compute, up to data centers, new flash architectures are essential to handle these next generation applications. Future technology must include not only new architectures and more layers in flash chip designs, but also a roadmap for QLC flash and beyond, new memories, new classes of SSDs, and new software technologies. They must all come together to enable and accelerate the next wave of applications including the real time analytics, AI (Artificial Intelligence)/ML (Machine Learning) high performance computing, IoT, and virtual and augmented reality.
author_names: Shigeo Ohshima
title: Empowering Next Generation Applications through FLASH Innovation
venue: 2020 IEEE Symposium on VLSI Technology
year: 2020

abstract: 2.5D multichip module packaging technology for higher end devices like CPU, GPU, 3D NAND flash memory and High Bandwidth Memory (HBM) require two major molding process solutions: higher thermal performance and narrow gap underfill. Apic Yamada Corporation of Japan, as a semiconductor back end total solution provider, proposes technology solutions utilizing advanced molding technologies which enable chip surface exposure and Mold Underfill (MUF) for narrow gaps.With conventional molding technology, the mold resin on the top surface of the chip is removed by a grinding process after the molding process in order to improve thermal resistance thja. However, the latest transfer molding technology enables chip exposure without a grinding process. This technology can be applied to a wide range of higher end advanced packaging technologies such as 2.5D, 3D and others. The conventional chip exposure molding method using elastic release film, which covers the inside of the mold cavity, can absorb chip height variations. In addition, the most advanced available chip exposure molding system applies reduced pressure and lower mechanical stress to the chip. This low stress molding process comprises several new system technologies including chip height measurement using a laser displacement sensor, which is self calculating to provide the optimum cavity level for chip exposure, by adjusting the cavity block position each cycle.In this study, solutions for chip height variation such as 20um and height control range within 300um with low stress will be presented. In addition, we propose newly developed vacuum molding technology and movable air vent technology for MUF with void less filling of narrow gap spaces under the chips. Proper mold resin material selection to achieve high filling, optimal heat shrinkage and minimized warpage is one of the key factors. The new technology also provides economic advantages due to reduced process steps and shorter process time compared to the Capillary Underfill (CUF) process which is widely used in the marketplace.In order to achieve a reliable MUF process targeting less than 8um gaps and less than 15um pitch, Apic Yamada's molding system has tighter control for discharging internal air and generated gas to the outside. This is accomplished while also controlling vacuum conditions, using chip volume measurement by laser displacement sensor and 3D image measurement which calculates the resin flow front on each shot.
author_names: Takashi Saito

Tokuyuki Kitajima

Makoto Kawaguchi

Shinya Tajima

Masashi Okamoto
title: New Molding Technology Enabling Advanced Packaging Technology
venue: 2020 IEEE 70th Electronic Components and Technology Conference (ECTC)
year: 2020

abstract: In this paper, mobility model for poly Si based macaroni structure in 3 D NAND Flash memory is presented. String current was calibrated with technology computer aided design (TCAD) simulation at room temperature (25degC) with U shaped trap distribution. Then, unit word line (WL) I V curve was extracted, and effective mobility was extracted from these data using analytical equation. Mobility model is based on Meyer Neldel Rule (MNR) We extracted grain boundary barrier height \varphi_{\mathrm{b} and fitted with our model. Finally, we fitted effective mobility \mu_{\mathrm{eff} with our model and fitted string current with SPICE simulation.
author_names: Hyungjun Jo

Juhyun Kim

Minsoo Kim

Hyungcheol Shin
title: Extraction of Mobility in 3 D NAND Flash Memory with Poly Si Based Macaroni Structure
venue: 2020 4th IEEE Electron Devices Technology Manufacturing Conference (EDTM)
year: 2020

abstract: We investigated process variation effect of 3D NAND flash memory cell, especially about geometric variation using a machine learning (ML) model. Geometric variability sources impact on variation of device's electrical parameters such as threshold voltage \mathbf{V}_{\mathbf{t} subthreshold swing (SS) transconductance \mathbf{g}_{\mathbf{m} and on current \mathbf{I}_{\mathbf{on} All these data were analyzed with 3D stochastic Technology Computer Aided Design (TCAD) simulation and trained through ML model, which is composed of artificial neural network (ANN) The model has multi input and multi output (MIMO) structure and deep hidden layers to train and predict complex data of process variation. In order to make ML model more accurate, simulation for constructing training data set was carried out with a large number of random unit cells, which are cut from various strings. The completed ML model was tested with random test data set which had not been used for training to prove its accuracy. Through the test process, ML model showed the error of up to 5% and proved the accuracy of prediction.
author_names: Jang Kyu Lee

Kyul Ko

Hyungcheol Shin
title: Analysis on Process Variation Effect of 3D NAND Flash Memory Cell through Machine Learning Model
venue: 2020 4th IEEE Electron Devices Technology Manufacturing Conference (EDTM)
year: 2020