Search query: Emerging CMOS Compatible Magnetic Memories and Logic

Related papers:

abstract: As scaling of electronic semiconductor devices the main driving force behind an outstanding increase of computing power of modern electronic circuits displays signs of saturation, the main focus of engineering research in microelectronics shifts towards finding new computing paradigms. The future solutions must be scalable and energy efficient while delivering high computational performance, superior to that of CMOS based circuits. In order to benefit from the outstanding potential of highly advanced silicon processing technology, the emerging solutions must be CMOS compatible. Emerging nonvolatile memories, including magnetoresistive memories, satisfy the necessary requirements: Purely electrically addressable magnetoresistive random access memories yield all aforementioned conditions. They possess a simple structure, require fewer extra masks for fabrication, and offer endurance and speed superior to those of flash memory. Fast operation of magnetoresistive memories makes them a viable contender to static random access memory and flash memory for embedded applications in Systems on Chip. Having nonvolatile memory very close to CMOS removes the necessity of the energy intensive data transfer from the main memory to the CPU and offers a prospect of data processing in the nonvolatile segment, where the same elements are used to store and to process the information. This opens perspectives for conceptually new low power and highperformance computing paradigms based on logic in memory and in memory computing.
author_names: Viktor Sverdlov

Simone Fiorentini

Johannes Ender

Wolfgang Goes

Roberto L De Orio

Siegfried Selberherr
title: Emerging CMOS Compatible Magnetic Memories and Logic
venue: 2020 IEEE Latin America Electron Devices Conference (LAEDC)
year: 2020

abstract: With an ever increasing demand for energy efficiency, processors with instant on and zero leakage features are highly appreciated in energy harvesting as well as "normally off" applications. Recently, zero standby power and fast switching nonvolatile processors (NVPs) have been proposed based on emerging nonvolatile memories (NVMs) such as ferroelectric RAM or spin transfer torque magnetic RAM. However, previous NVPs store all data to NVM upon every power interruption, resulting in high energy consumption and degraded NVM endurance. This paper presents a 65 nm fully CMOS logic compatible ReRAM based NVP supporting time space domain adaption. It incorporates adaptive nonvolatile controller, nonvolatile flip flops, and nonvolatile static random access memory (nvSRAM) with self write termination. Data redundancy in both time and space domain is fully exploited to reduce store/restore time/energy and boost clock frequency. The NVP operates at >100 MHz and achieves 20 ns/0.45 nJ restore time/energy, realizing >6 \times and >6000 \times higher speed and energy efficiency of restore and >4 \times faster operating frequency compared with that of state of the art.
author_names: Zhibo Wang

Yongpan Liu

Albert Lee

Fang Su

Chieh-Pu Lo

Zhe Yuan

Jinyang Li

Chien-Chen Lin

Wei-Hao Chen

Hsiao-Yun Chiu

Wei-En Lin

Ya-Chin King

Chrong Jung Lin

Pedram Khalili Amiri

Kang L Wang

Meng-Fan Chang

Huazhong Yang
title: A 65 nm ReRAM Enabled Nonvolatile Processor With Time Space Domain Adaption and Self Write Termination Achieving 4x Faster Clock Frequency and 6x Higher Restore Speed
venue: IEEE J. Solid State Circuits
year: 2017

abstract: With CMOS transistors' scaling showing signs of saturation, an exploration of new working principles suitable for emerging microelectronic devices accelerates. The electron spin is attractive for new device applications as a complement and a possible replacement of the electron charge currently employed by CMOS. The electron spin displays the two well defined projections on an axis and is thus suitable for digital applications. In magnetic tunnel junctions (MTJs) the free magnetic layer possesses two orientations relative to the fixed layer: parallel and antiparallel. As the parallel and antiparallel magnetization configurations are characterized by different resistances, the thereby stored information can be read. MTJs enable a spin based type of non volatile magnetoresistive memory. MTJs are fabricated with a CMOS friendly process and are quite CMOS compatible. The relative magnetization configuration can be written by means of a spin transfer torque (STT) or a spin orbit torque (SOT) acting on the free layer. The torques are caused by spin polarized electrical currents and not by a magnetic field. Electrically addressable non volatile magnetoresistive memories are attractive for stand alone and embedded applications. The state of the art concepts of STT and SOT memory, in particular the required modeling approaches, are reviewed, with a particular focus on a fast external magnetic field free switching in advanced SOT MRAM.
author_names: Viktor Sverdlov

Siegfried Selberherr
title: CMOS Technology Compatible Magnetic Memories
venue: 2019 8th International Symposium on Next Generation Electronics (ISNE)
year: 2019

abstract: As the technology node shrinks down to 90 nm and below, high power becomes one of the major critical issues for CMOS high speed computing circuits (e.g. logic and cache memory) due to the increasing leakage currents and data traffic. Emerging non volatile memories are under intense investigation to bring the non volatility into the logic circuits and then eliminate completely the standby power issue. Thanks to its quasi infinite endurance, high speed and easy 3D integration at the back end process of CMOS IC fabrication, Magnetic RAM (MRAM) is considered as one of the most promising candidates. A number of hybrid MRAM/CMOS logic circuits have been proposed and prototyped successfully in the last years. In this introduction paper for the invited special session at NEWCAS 2013, we present an overview and current status of these logic circuits and discuss their potential applications in the future.
author_names: Weisheng Zhao

Guillaume Prenat

Jacques-Olivier Klein

Bernard Dieny

Claude Chappert

Dafine Ravelosona
title: Emerging hybrid logic circuits based on non volatile magnetic memories
venue: 2013 IEEE 11th International New Circuits and Systems Conference (NEWCAS)
year: 2013

abstract: With CMOS device scaling slowing down, exploring new devices' working principles becomes paramount. The electron spin, as a complement to the charge, attracts much attention. The electron spin is characterized by the two well defined projections on a given axis and is suitable for digital applications. Magnetic tunnel junctions (MTJs) feature different resistances in parallel and antiparallel magnetization configuration and enable spin based types of non volatile magnetic memories. MTJs are quite CMOS compatible as they are fabricated with a CMOS friendly process. The relative magnetization configuration is manipulated by means of a spin transfer torque (STT) acting on the free layer. The electrically addressable non volatile STT memory is nearing mass production for stand alone and embedded applications. The current status and modeling approaches of state of the art STT and spin orbit torque memory are briefly reviewed.
author_names: Viktor Sverdlov

Siegfried Selberherr
title: Spin Based CMOS Compatible Memories
venue: 2019 IEEE 9th International Nanoelectronics Conferences (INEC)
year: 2019

abstract: For many decades CMOS devices have been successfully scaled down to achieve higher speed and increased performance of integrated circuits at lower cost. Today's charge based CMOS electronics encounters two major challenges: power dissipation and variability. Spintronics is a rapidly evolving research and development field, which offers a potential solution to these issues by introducing novel 'more than Moore' devices. Spin based magnetoresistive random access memory (MRAM) is already recognized as one of the most promising candidates for future universal memory. Magnetic tunnel junctions, the main elements of MRAM cells, can also be used to build logic in memory circuits with non volatile storage elements on top of CMOS logic circuits, as well as versatile compact on chip oscillators with low power consumption. We give an overview of CMOS compatible spintronics applications. First, we present a brief introduction to the physical background considering such effects as magnetoresistance, spin transfer torque (STT) spin Hall effect, and magnetoelectric effects. We continue with a comprehensive review of the state of the art spintronic devices for memory applications (STT MRAM, domain wallmotion MRAM, and spin orbit torque MRAM) oscillators (spin torque oscillators and spin Hall nano oscillators) logic (logic in memory, all spin logic, and buffered magnetic logic gate grid) sensors, and random number generators. Devices with different types of resistivity switching are analyzed and compared, with their advantages highlighted and challenges revealed. CMOScompatible spintronic devices are demonstrated beginning with predictive simulations, proceeding to their experimental confirmation and realization, and finalized by the current status of application in modern integrated systems and circuits. We conclude the review with an outlook, where we share our vision on the future applications of the prospective devices in the area.
author_names: Alexander Makarov

Thomas Windbacher

Viktor Sverdlov

Siegfried Selberherr
title: CMOS compatible spintronic devices: a review
year: 2016

abstract: Spin orbit torque (SOT) magnetic random access memory (MRAM) is an emerging non volatile memory that offers efficient and reliable sub ns switching. It is considered as a promising candidate to tackle the replacement of SRAM memories in low level caches (L1 3) In this paper, we review the fundamentals of spin orbit torque and we describe full scale integration of perpendicular magnetized SOT MRAM devices on 300mm wafers, using manufacturable methods and CMOS compatible processes. We demonstrate state of the art properties of W based top pinned magnetic tunnel junction (MTJ) with perpendicularly magnetic anisotropy (PMA) that possess large endurance >1011) and that can be switched at subnanosecond regimes (210ps) with power as low as 130pJ on 60nm devices. We conclude by opening current research focus and recent progress made by our team.
author_names: Kevin Garello

Farrukh Yasin

Gouri Sankar Kar
title: Spin Orbit Torque MRAM for ultrafast embedded memories: from fundamentals to large scale technology integration
venue: 2019 IEEE 11th International Memory Workshop (IMW)
year: 2019

abstract: The recent advent of spin transfer torque (STT) has shed a new light on MRAM with the promises of much improved performances and greater scalability to very advanced technology nodes. As a result, MRAM is now viewed as a credible solution for stand alone and embedded applications where the combination of non volatility, speed and endurance is key. Whereas the technology is nearing maturity for DRAM replacement, with the exception of process scaling to sub 20nm which remains a challenge, circuit designers are now actively looking at SoCs where MRAM could bring in better performance and lower power consumption in data intensive applications as well as instant on capability in mobile applications. In this paper we present a review of the MRAM technology and a methodology for ASIC design using a custom full digital hybrid CMOS/Magnetic Process Design Kit. We finish by a few examples showing that magnetic memories can be efficiently integrated in logic designs, for both safety and low power purposes.
author_names: Guillaume Prenat

Gregory di Pendina

Christophe Layer

Olivier Goncalves

K Jaber

Bernard Dieny

Ricardo C Sousa

Ioan Lucian Prejbeanu

Jean Pierre Nozieres
title: Magnetic memories: From DRAM replacement to ultra low power logic chips
venue: DATE
year: 2014

abstract: Spintronics is a continuously expending area of research and development at the merge between magnetism and electronics. It aims at taking advantage of the quantum characteristic of the electrons, i.e. its spin, to create new functionalities and new devices. Spintronic devices typically rely on the Magneto Resistive (MR) effects, which consists in a dependence of the electrical resistance upon the magnetic configuration. These devices can be used to conceive innovative nonvolatile memories, high perfomance logic circuits, RF oscillators or field/current sensors. We present here how these hybrid CMOS/Magnetic logic circuits can help circumventing some of the limits of CMOS only microelectronics in terms of reliability or power consumption as well as the tools required to design such circuits.
author_names: Guillaume Prenat

Bernard Dieny

Gregory di Pendina

Kholdoun Torki
title: Hybrid CMOS Magnetic Process Design Kit and application to the design of reliable and low power non volatile logic circuits
year: 2014

abstract: of the Thesis Energy Performance Characterization of CMOS/Magnetic Tunnel Junction (MTJ) Hybrid Logic Circuits by Fengbo Ren Master of Science in Electrical Engineering University of California, Los Angeles, 2011 Professor Dejan Markovic, Chair Magnetic Tunnel Junction (MTJ) devices are CMOS compatible with high stability, high reliability and non volatility. All these features are promising for building non volatile CMOS/MTJ hybrid logic circuits that do not consume offstate leakage current and that supports ultra low power operation. However, most existing proposals for this purpose so far lack an energy performance analysis and a comparison to CMOS circuits. In this work, we analyze and compare the energy performance characteristics of a wide range of CMOS/MTJ hybrid circuits over the device, circuit and architectural levels. This will include device switching energies, logic in memory MTJ (LIM MTJ) logic circuit, two MTJ reading circuits and two CMOS/MTJ hybrid lookup table (LUT) architectures. Our analysis shows that the existing LIM MTJ logic style has no advantage in energy performance over its equivalent CMOS design, and that with the switching energy of MTJ considered, the CMOS/MTJ hybrid circuit requiring frequent MTJ switching is hardly energy efficient. Our simulation results also show that the cross coupled inverter based MTJ reading circuit has 4 times greater perfor
author_names: Fengbo Ren

Kang L Wang

Chih-Kong Ken Yang

Dejan Markovic
title: Energy Performance Characterization of CMOS Magnetic Tunnel Junction MTJ Hybrid Logic Circuits
year: 2011