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abstract: A valuable reference for the most vital microelectronic components in the marketplace DRAMs are the technology drivers of high volume semiconductor fabrication processes for new generation products that, in addition to computer markets, are finding increased usage in automotive, aviation, military and space, telecommunications, and wireless industries. A new generation of high density and high performance memory architectures evolving for mass storage devices, including embedded memories and nonvolatile flash memories, are serving a diverse range of applications. Comprehensive and up to date, Advanced Semiconductor Memories: Architectures, Designs, and Applications offers professionals in the semiconductor and related industries an in depth review of advanced semiconductor memories technology developments. It provides details on: Static Random Access Memory technologies including advanced architectures, low voltage SRAMs, fast SRAMs, SOI SRAMs, and specialty SRAMs (multiport, FIFOs, CAMs) High Performance Dynamic Random Access Memory DDRs, synchronous DRAM/SGRAM features and architectures, EDRAM, CDRAM, Gigabit DRAM scaling issues and architectures, multilevel storage DRAMs, and SOI DRAMs Applications specific DRAM architectures and designs VRAMs, DDR SGRAMs, RDRAMs, SLDRAMs, 3 D RAM Advanced Nonvolatile Memory designs and technologies, including floating gate cell theory, EEPROM/flash memory cell design, and multilevel flash FRAMs and reliability issues Embedded memory designs and applications, including cache, merged processor, DRAM architectures, memory cards, and multimedia applications Future memory directions with megabytes to terabytes storage capacities using RTDs, single electron memories, etc. A continuation of the topics introduced in Semiconductor Memories: Technology, Testing, and Reliability, the author's earlier work, Advanced Semiconductor Memories: Architectures, Designs, and Applications offers a much needed reference to the major developments and future directions of advanced semiconductor memory technology.
author_names: Ashok K Sharma
title: Advanced Semiconductor Memories: Architectures, Designs, and Applications
year: 2009

abstract: Memory modeling functional testing: reduced functional RAM chip model functional RAM chip testing functional ROM chip testing functional memory array testing functional memory board testing electrical testing: parametric testing dynamic testing on chip testing conclusions: address line scrambling various proofs software package.
author_names: Ad Van De Goor
title: Testing Semiconductor Memories: Theory and Practice
year: 1998

abstract: Three dimensional integration enables stacking memory directly on top of a microprocessor, thereby significantly reducing wire delay between the two. Previous studies have examined the performance benefits of such an approach, but all of these works only consider commodity 2D DRAM organizations. In this work, we explore more aggressive 3D DRAM organizations that make better use of the additional die to die bandwidth provided by 3D stacking, as well as the additional transistor count. Our simulation results show that with a few simple changes to the 3D DRAM organization, we can achieve a 1.75x speedup over previously proposed 3D DRAM approaches on our memory intensive multi programmed workloads on a quad core processor. The significant increase in memory system performance makes the L2 miss handling architecture (MHA) a new bottleneck, which we address by combining a novel data structure called the Vector Bloom Filter with dynamic MSHR capacity tuning. Our scalable L2 MHA yields an additional 17.8% performance improvement over our 3D stacked memory architecture.
author_names: Gabriel H Loh
title: 3D Stacked Memory Architectures for Multi core Processors
venue: 2008 International Symposium on Computer Architecture
year: 2008

abstract: The once ephemeral radiation induced soft error has become a key threat to advanced commercial electronic components and systems. Left unchallenged, soft errors have the potential for inducing the highest failure rate of all other reliability mechanisms combined. This article briefly reviews the types of failure modes for soft errors, the three dominant radiation mechanisms responsible for creating soft errors in terrestrial applications, and how these soft errors are generated by the collection of radiation induced charge. The soft error sensitivity as a function of technology scaling for various memory and logic components is then presented with a consideration of which applications are most likely to require soft error mitigation.
author_names: Robert C Baumann
title: Radiation induced soft errors in advanced semiconductor technologies
venue: IEEE Transactions on Device and Materials Reliability
year: 2005

abstract: This paper presents a state of the art review of error correcting codes for computer semiconductor memory applications. The construction of four classes of error correcting codes appropriate for semiconductor memory designs is described, and for each class of codes the number of check bits required for commonly used data lengths is provided. The implementation aspects of error correction and error detection are also discussed, and certain algorithms useful in extending the error correcting capability for the correction of soft errors such as a particle induced errors are examined in some detail.
author_names: Chin-Long Chen

Mu Yue Hsiao
title: Error Correcting Codes for Semiconductor Memory Applications: A State of the Art Review
venue: IBM J. Res. Dev.
year: 1984

abstract: We survey recent developments in the design of large capacity content addressable memory (CAM) A CAM is a memory that implements the lookup table function in a single clock cycle using dedicated comparison circuitry. CAMs are especially popular in network routers for packet forwarding and packet classification, but they are also beneficial in a variety of other applications that require high speed table lookup. The main CAM design challenge is to reduce power consumption associated with the large amount of parallel active circuitry, without sacrificing speed or memory density. In this paper, we review CAM design techniques at the circuit level and at the architectural level. At the circuit level, we review low power matchline sensing techniques and searchline driving approaches. At the architectural level we review three methods for reducing power consumption.
author_names: Kostas Pagiamtzis

Ali Sheikholeslami
title: Content addressable memory (CAM) circuits and architectures: a tutorial and survey
venue: IEEE Journal of Solid State Circuits
year: 2006

abstract: Signal integrity has become the key issue in most high performance digital designs. Now, from the foremost experts in the field, this book leverages theory and techniques from non related fields such as applied physics, communications, and microwave engineering and applies them to the field of high speed digital design. This approach creates an optimal combination of theory and practice that is meaningful to practicing engineers and graduate students alike.
author_names: Stephen H Hall

Howard Heck
title: Advanced Signal Integrity for High Speed Digital Designs
year: 2009

abstract: Keywords: thermodynamique lois fondamentales exergie reversibilite reaction chimique energie energie solaire cycles refrigeration Reference Record created on 2005 11 18, modified on 2016 08 08
author_names: Adrian Bejan
title: Advanced Engineering Thermodynamics
year: 1988

abstract: Preface. Introduction. PART I: SEMICONDUCTOR PHYSICS. Energy Bands and Carrier Concentration in Thermal Equilibrium. Carrier Transport Phenomena. PART II: SEMICONDUCTOR DEVICES. p n Junction. Bipolar Transistor and Related Devices. MOSFET and Related Devices. MESFET and Related Devices. Microwave Diodes, Quantum Effect, and Hot Electron Devices. Photonic Devices. PART III: SEMICONDUCTOR TECHNOLOGY. Crystal Growth and Epitaxy. Film Formation. Lithography and Etching. Impurity Doping. Integrated Devices. Appendix A: List of Symbols. Appendix B: International Systems of Units (SI Units) Appendix C: Unit Prefixes. Appendix D: Greek Alphabet. Appendix E: Physical Constants. Appendix F: Properties of Important Element and Binary Compound Semiconductors at 300 K. Appendix G: Properties of Si and GaAs at 300 K. Appendix H: Derivation of the Density of States in Semiconductor. Appendix I: Derivation of Recombination Rate for Indirect Recombination. Appendix J: Calculation of the Transmission Coefficient for a Symmetric Resonant Tunneling Diode. Appendix K: Basic Kinetic Theory of Gases. Appendix L: Answers to Selected Problems. Index.
author_names: S M Sze
title: Semiconductor Devices: Physics and Technology
year: 1985

abstract: Year 2009 marks the completion of 50 years of the invention of CORDIC (coordinate rotation digital computer) by Jack E. Volder. The beauty of CORDIC lies in the fact that by simple shift add operations, it can perform several computing tasks such as the calculation of trigonometric, hyperbolic and logarithmic functions, real and complex multiplications, division, square root, solution of linear systems, eigenvalue estimation, singular value decomposition, QR factorization and many others. As a consequence, CORDIC has been utilized for applications in diverse areas such as signal and image processing, communication systems, robotics and 3 D graphics apart from general scientific and technical computation. In this article, we present a brief overview of the key developments in the CORDIC algorithms and architectures along with their potential and upcoming applications.
author_names: Pramod Kumar Meher

Javier Valls-Coquillat

Tso-Bing Juang

Krishnamurthy Sridharan

Koushik Maharatna
title: 50 Years of CORDIC: Algorithms, Architectures, and Applications
venue: IEEE Transactions on Circuits and Systems I: Regular Papers
year: 2009