Search query: Optimum Spacing Comparator PLL

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abstract: One of the nonlinear components in PLL is Phase Frequency Detector (PFD),the purpose is to compare two input frequencies in terms of their phase and frequency. In this process jitter will be introduced to the PLL system by PFD. proposed PFD is the preferred approach for detecting weak signals as from a deep space profile. The increase of MOS devices on a single chip will consume more power. Various applications of the PLL such as wireless communication systems, digital circuits, and receivers, targets optimum PFD Design. Optimized PFD reduces jitter effect on PLL and enhances the performance of PLL by increasing the locking range, reducing the phase error variance, reducing the acquisition time and reducing the power consumption. The power consumption in the design of PFD is dependent on CMOS logic of the gates In this paper we propose CMOS PFD, where the performance of the result will be analyzed by using Tanner EDA Tool by considering 45nm technology. CMOS technology is the semiconductor technology used in the transistors that are manufactured in the present days .Nowadays it is a mark able invention for the electronic designers to integrate all the components in a single chip in a system. The new invention towards the technology implementation is speed of the increase of memory, cost decreases and reduction of size of the devices. The transistor occupies less space. The integration of MOS transistors in the design of large multiprocessors, the leakage current in MOS transistors becoming a severe problem. The variations of leakage current increases with the power consumption in MOS transistors. The MOS devices work with only switching voltages in terms of power consumption. The significance of analog signals represents different conversion parameters takes place in different devices in CMOS technology. The chip designers uses cmos technology based on speed and performance criteria. Phased locked loop are widely used in different applications in analog and digital systems for desired control voltage operating devices.PLL was first described in early 1930s.Frequency modulation is one of the application in the PLL design, used in many devices. The feedback control circuit changes the output according to the desired application by locking the phase of input signal. For instances, the analog signal is implemented by a digital signal with different types of devices i.e. Analog to digital conversion in the design of PFD. Example, comparator takes the analog input signal and it will be change as digital signal by flip flop and counters. The analog signals used in many different practical applications needs conversion of discrete digital signal in advance such as charge pump. In the design of PFD both analog and digital signal are used, different logics are applied in the design. The knowledge of signals makes the PFD more synthesized, challenging environment. II. PHASE LOCKED LOOP Negative feedback system in the design of PLL locks the clock signal, generated by the oscillator of the phase and frequency locked to a reference signal. A reference signal is usually retrieved from a oscillator. When the PLL gets locked the phase error between output and input signal is zero or should remain at a consistant phase error.PLL is configured with integrated circuit. The PLL design problems can be approached using the Laplace transform technique. It is a feedback system that includes a vco, phase detector, with in its loop. The locking property of the PLL is numerous applications such as frequency, or phase modulation and demodulation. The standard analog PLL implementation is problematic in many application. Analog signal conversion is a challenging process in the design of PFD in the sense of clock. PLL synchronizes VCO frequency to input reference frequency through feedback.
author_names: Syed Shameem
title: OPTIMUM RESOLUTION OF PHASE FREQUENCY DETECTOR BY CMOS TECHNOLOGY FOR PLL
year: 2016

abstract: Methods to detect and correct timing errors of oscillators are very important to achieve the low jitter performance of a ring DCO (RDCO) digital PLL (DPLL) A TDC is widely used to quantize these timing errors. The higher the resolution of a TDC, the lower the quantization noise becomes. However, such TDCs require large power to cover a sufficiently wide dynamic range. Instead, [1] [2] presented jitter minimization techniques that used a bang bang phase detector (BBPD) and the background optimization of the proportional gain of the loop, KP (top left of Fig. 17.1.1) This approach is effective for low power designs but is limited in reducing the output jitter, since the information of timing errors by the BBPD is just binary. To overcome this limit, [3] used three parallel BBPDs, each of which had a different time threshold, tTH. While maintaining the optimal spacing between the tTHS (instead of decreasing it unconditionally) along with the calibration of KP, the DPLL in [3] succeeded in decreasing the jitter. Despite these efforts, previous DPLLs [1] [3] had a fundamental limit to minimizing the jitter since they optimized only KP based on an incorrect assumption that the RDCO jitter was "white" Gaussian while ignoring flicker noise. However, different from thermal noise, the energy of flicker noise is concentrated at low frequency offsets near DC, and its effect appears as a random drift of the RDCO frequency over time [4] Thus, to suppress flicker noise and further reduce the overall jitter, the flicker induced frequency drifts (fDS) must be calibrated by adjusting the gain of the integral path, K1, as well as KP.
author_names: Yongsun Lee

Taeho Seong

Jeonghyun Lee

Hangi Park

Jae-hyouk Choi
title: 17.1 A 240dB FoMjitter and 115dBc/Hz PN 100kHz, 7.7GHz Ring DCO Based Digital PLL Using P/I Gain Co Optimization and Sequence Rearranged Optimally Spaced TDC for Flicker Noise Reduction
venue: 2020 IEEE International Solid State Circuits Conference (ISSCC)
year: 2020

abstract: This paper presents a novel analysis of a self compensating, low noise, low power Phase Locked Loop circuit design implemented 45 nm technology node. The basic Phase Locked Loop (PLL) circuit prescribed in the literature comprises a Phase Detector or comparator followed by a low pass filter and a voltage controlled oscillator. The individual circuit elements have been separately designed in Virtuoso Analog Design Environment of Cadence Design System and analyzed for achieving optimum performance and then combined in cascade to form a feedback network. Simulation results obtained for the individual components have been critically investigated in the later half of the paper, which shows considerable improvement in frequency stability and power consumption of the PLL design. Finally, conclusions have been drawn based upon the integrated design and stress has been laid upon future scopes of work in this area.
author_names: Agnish Mal

Akshat Chitransh

Harsh Srivastava

Suraj Kumar Saw

Vijay Nath
title: Analysis of a Self compensating, Low Noise, Low Power PLL Circuit 45 nm Technology Node
year: 2017

abstract: One of the approaches for the next fifth generation (5G) is to utilize millimeter wave (mmWave) spectrum in order to satisfy the future expected requirements, such as super high bit rate. For this, it will need to use high channel spacing. This paper presents a [81 86] GHz Integer A frequency synthesizer using ultra wide bandwidth of channel spacing (1GHz) for 5G wireless communications systems. This work is focused on the impact of the phase margin loop filter on mm Wave PLL frequency synthesizer performances. The choice of this parameter is an important criterion for the loop stability. It has an effect on the closed loop response, FM response and involves the design tradeoffs between the response time and the reference spurs. However, the obtained results of 45deg phase margin and 50 MHz comparison frequency indicate a noise density of 73 dBc, 89 dBc and 99 dBc at 50 MHz, 100 MHz and 150 MHz respectively, with 844fs RMS phase Jitter and temporal response of 936,631 ns.
author_names: Berber Zakia

Kameche Samir Kameche Samir
title: Optimal choice for phase margin on mm Wave PLL frequency synthesizer for 5G wireless communications systems
venue: 2018 Fifth International Conference on Software Defined Systems (SDS)
year: 2018

abstract: The generation of mm wave (mmW) signals that have ultra low phase noise (PN) is very important for the design of RF transceivers (TRXs) for high data rate 5G systems. Direct RF sampling TRXs also require high frequency clock signals, having extremely low integrated PN (IPN) [1] To satisfy such stringent noise requirements, the rms jitter of mmW band signals must be reduced to sub 100fs. Recently, a charge pump (CP) PLL in [1] achieved a very low rms jitter of less than 60fs at 14GHz. However, to suppress the in band PN of PLL building blocks, that design used a reference clock that had an impractically high frequency, $f_{\mathrm{REF} of 500MHz. To avoid the use of such a high $f_{\mathrm{REF} while minimizing in band PN, sub sampling PLLs (SSPLLs) are seen as a promising solution. However, conventional SSPLLs are not suitable for generating mmW band signals directly, since, as the frequency increases, the capture range of their sampling operation is reduced rapidly, thereby hindering the reliable operation. To extend the capture range, a prescaler can be used after the VCO [2] but it increases the in band PN and power consumption. Direct mmW SSPLLs are limited even at suppressing out of band PN, since their PN skirt is determined by an mmW VCO that has a relatively low Q. To overcome the problems of analog SSPLLs, such as a large area and a PVT sensitive loop gain, digital SSPLLs using ADCs to digitize the sampled voltage have been developed recently [3] However, digital SSPLLs suffer from another problem in that, to reduce the quantization noise (Q noise) and improve the overall IPN, they must use high performance ADCs that concurrently have high sampling frequencies, fine resolutions, and wide dynamic ranges. Thus, they demand high power and occupy larger area.
author_names: Juyeop Kim

Heein Yoon

Younghyun Lim

Yongsun Lee

Yoonseo Cho

Taeho Seong

Jaehyouk Choi
title: 16.2 A 76fsrms Jitter and 40dBc Integrated Phase Noise 28 to 31GHz Frequency Synthesizer Based on Digital Sub Sampling PLL Using Optimally Spaced Voltage Comparators and Background Loop Gain Optimization
venue: 2019 IEEE International Solid State Circuits Conference (ISSCC)
year: 2019

abstract: This article presents a cascaded architecture of a frequency synthesizer to generate ultra low jitter output signals in a millimeter wave (mmW) frequency band from 28 to 31 GHz. The mmW band injection locked frequency multiplier (ILFM) placed at the second stage has a wide bandwidth so that the performance of the jitter of this frequency synthesizer is determined by the GHz band, digital subsampling phase locked loop (SSPLL) at the first stage. To suppress the quantization noise of the digital SSPLL while using a small amount of power, the optimally spaced voltage comparators (OSVCs) are presented as a voltage quantizer. This article was designed and fabricated using 65 nm CMOS technology. In measurements, this prototype frequency synthesizer generated output signals in the range of 28 31 GHz, with an rms jitter of less than 80 fs and an integrated phase noise (IPN) of less than 40 dBc. The active silicon area was 0.32 mm2, and the total power consumption was 41.8 mW.
author_names: Juyeop Kim

Younghyun Lim

Heein Yoon

Yongsun Lee

Hangi Park

Yoonseo Cho

Taeho Seong

Jaehyouk Choi
title: An Ultra Low Jitter, mmW Band Frequency Synthesizer Based on Digital Subsampling PLL Using Optimally Spaced Voltage Comparators
venue: IEEE Journal of Solid State Circuits
year: 2019

abstract: Here we describe methods of detection of Code Division Multiple Access signal against Gaussian noise. We transmit differentially encoded signal and in the receiver, we do signal processing to reduce noise injected by the mixer or RF front end. Similar noise reduction method is also proposed for carrier recovery and hence the demodulator works. The detector is followed by BCH decoding which is syndrome based. 1.0 INTRODUCTION Direct sequence code division multiple access is currently used in data communication IEEE standard 802.11 and for voice band by Qualcomm. It has several advantages like lower noise than FSK, higher cell capacity and soft hand off. Qualcomm uses orthogonal code to spread the data sequence at the transmitter and despread it at the receiver. The optimum detection of synchronous and asynchronous CDMA with PRN sequence was first proposed in reference [1] Here we optimize the signal to noise ratio in analog domain. The decoding of BCH code which is used to protect against fading is different. Also we do not use any analog to digital conversion or any sampling of signal avoiding injection of noise. There is no exponential increase in calculation like in maximum likelihood method [2] There was a lot of research activity to use MUD detector in digital domain to reduce the crosscorrelation from different users [3] A method is used here which could be inspired by the reference [4] Near far problem, once was the focus of research activity, is resolved here using separate demodulator for each user in asynchronous transmission of uplink. Adaptive detector is avoided here as its power consumption is high. The demodulator described here is most suitable for low power application. The detector was proposed in reference [5][6] for GPS receiver and radar detector, except we propose a coding by BCH code against noise and fading [7] Section I introduces the subject and section II describes the basic principle followed in this paper to achieve lowest noise possible. Section III explains the requirement of carrier and data clock recovery. The next section explains the signal path in the demodulator. This is followed by the section on Asynchronous CDMA. We conclude the paper in the following section. 2.0 PRINCIPLE OF OPTIMUM DETECTION Here we propose few demodulators for synchronous and asynchronous CDMA with Walsh Hadamard Code or Pseudo random sequence as the spreading code. We use same open loop gain for carrier recovery and the demodulator in analog domain, so that the performance is balanced. Moreover, we do not use sampling and use comparator as detector followed by a syndrome decoder for BCH code in digital domain. As we avoid using analog to digital conversion or MUD detector we reduce noise injection and power consumption. We have found that an integrator for a high pass filtered signal reduces the noise variance [5] To get that in synchronous CDMA, we transmit where Cn,i is the chip sequence coded with data bit for n user and i time. As it is synchronized in chip as well as in data bit, it is linear and we decode it by individual chip sequence at the hand set as it is downlink. When we correlate by the chip sequence, we do not use integrate and dump circuit, but a simple integrator. Thus we get double integration. The variance will be assuming a White (AWGN) noise spectrum which is flat. If we block the dc, then we get reduced noise variance. Similarly, we can use the method of triple integration, which uses double difference Ci+2 2Ci+1 Ci This may produce a transmission which is 4 times than normal amplitude. Here, we should get the increased power of transmission for noise reduction in integration. Hence we do not consider this case any further. We use Manchester coded data, which when integrated comes to zero all the time. We compare it with zero voltage and latch it at a delay flip flop at the data clock, avoiding a AtoD. Then in digital domain we do decoding of BCH code. International Journal of All Research Education and Scientific Methods (IJARESM) ISSN: 2455 6211, Volume 4, Issue 3, March 2016 2 3.0 CARRIER AND DATA CLOCK RECOVERY The carrier recovery PLL has a mathematical form (s+a)(s+b)s+k] which is stable with second order response to a step jump in phase. The root locus could be found in [8] from which we can find the maximum gain K for optimum second order response. The carrier recovery and data clock recovery block diagram is shown in Figure 1 [9] Figure 1. Carrier recovery and demodulation of synchronous CDMA The phase locked loop can be explained as: the mixer has one input A(t)cos(wct)+noise like data, where A(t) could be sinusoidal waveform. The voltage controlled oscillator generates sin(wct) term which is used to frequency divide to generate A(t) and they are mixed. This signal is used in the main mixer. So the output of the mixer is sin(wct)*cos(wct)+noise*sin(wct) which is double integrated to VCO input.
author_names: Amit Kumar Dutta
title: Optimum Detection of CDMA
year: 2016

abstract: [Abstract] also independently stably operates manufacturing variations at a low voltage, and jitter characteristic is good. A delay element control circuit 2 detects a delay value of the output signal based on the error signal of the difference between the reference signal of the output signal received from the phase frequency comparator circuit 1 delay elements of the oscillator 3 by the delay value generating a digital control signal for controlling. Each series connected delay elements 31~3m setting the delay value in the oscillator 3, the optimum delay value received by each delay circuit to control the plurality of digital control signal has a delay circuit composed of a plurality of transistors in can be activated. Therefore, in combination with the logical configuration of the delay element 31~3m each delay circuit configuration as the digital control signal of the delay element control circuit 2, the optimum with a delay value of the short intervals by the minimum number of delay elements 31~3m It can form a circuit.
author_names: Da Tian Zhe Ye

Shan Kou Tong Zheng
title: Digital pll circuit and the oscillator of the delay elements
year: 1998

abstract: Abstract One method of estimating the direction of an electromagnetic source is based on phase comparison. In this thesis the design and fabrication of a prototype antenna to demonstrate a new DF antenna architecture is described. Four antenna elements are grouped into three pairs with element spacing according to a set of symmetrical number system pairwise relatively prime moduli (m1 3, m2 4, m3=5) The phase difference between each pair of elements is a symmetrical folding waveform that is determined using a mixer. The output voltage from each pair is amplitude analyzed using a small comparator ladder. In each channel, the symmetrically folding waveform, folds in accordance with the channel modulus and thus, only requires a precision according to that modulus. A high resolution DF is achieved after the N different SNS moduli are used and the results of these low precision channels are recombined to yield the direction of arrival. The frequency of operation of the prototype is 8.5 GHz. Results based on measured and simulated data are resented.
author_names: Panayiotis Papandreou
title: Design and prototype development of an optimum symmetrical number system direction finding array
year: 1997

abstract: Conventional phase locked loops (PLL's) lack speed, because ordinary phase comparators cannot achieve time continuous phase detection, introducing equivalent time delays into the loops. This paper presents a PLL reconstructed to derive time optimal responses. First, VCO's and filters are replaced by time discrete ones, eliminating the stability problem caused by the time delay. Second, period rather than frequency is employed as the controlled variable for utilizing digital phase comparators as linear time comparators. A prototype consisting of about 20 IC's is tested.
author_names: Fuminori Kobayashi

Yasuhiko Sakamoto

Michio Nakano
title: High speed PLL and frequency synthesizer for low frequencies
year: 1984