Search query: Solder Joints in PCB Assembly and Semiconductor Packaging

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abstract: Assembly and reliability of lead free solder joints are very important topics in electronic manufacturing. There are many books [1 69] and papers [70 315] written on them. In this book, the assembly of lead free solder joints such as prevailing lead free materials, soldering processes, advanced specialty flux design, and characterization of lead free solder joints will be discussed, respectively in Chaps. 2 5. The reliability of lead free solder joints such as reliability testing and data analyses, design for reliability, and failure analyses of lead free solder joints will be discussed, respectively in Chaps. 6 8. The special features of this book are the materials covered are not only for electronic manufacturing services (EMS) on the second level interconnects, but also for packaging assembly on the first level interconnects and for the semiconductor back end on the 2.5D and 3D IC integration interconnects as shown in Fig. 1.1. The solder joints in various plated through hole (PTH) and surface mount technology (SMT) printed circuit board (PCB) assemblies, and semiconductor packages will be discussed in this chapter.
author_names: John H Lau

Ning-Cheng Lee
title: Solder Joints in PCB Assembly and Semiconductor Packaging
year: 2020

abstract: In high reliability Surface Mount Technology (SMT) assembly applications, the ability to inspect the solder joints visually has been standard and has been key factors in providing confidence in solder joint reliability. Inspection techniques such as X ray can be used to detect gross manufacturing defects such as solder bridging, but are not suitable for detection of other defects such as cracks. Temperature cycling test (TCT) is a standard solder joint reliability assessment method in semiconductor reliability for ball grid array (BGA) packaging. SMT reflow process and CTE (coefficient of thermal expansion) between solder materials, PCB and BGA package have high influence in solder joint reliability. A careful experimental investigation was undertaken to evaluate the reliability of solder joints of SAC BGA components formed using Sn 2Ag Cu Ni solder paste. This evaluation specifically looked at the impact of time above liquidus, peak temperature and thermal interface material (TIM) on solder joint reliability. Four types of samples prepared with the peak temperature of 2500C and no TIM, 2500C with TIM, time above liquidus (TAL) 90 seconds and no TIM and TAL 90 seconds with TIM. A total of 60 drives were assembled and subjected to accelerated thermal cycling (ATC) test in the temperature range of 00C to 1000C for a maximum of 2000 cycles with reference to JESD22 A104 standard. Based on the results from the deisgn of experiment (DOE) TAL 90s profile have demonstrated better TCT reliability margin compared to peak temperature of 2500C.
author_names: Mohammad Zainudeen Moideen

Chong Leong Gan
title: Solder joint reliability enhancement through surface mounting solder joint reflow optimization in enterprise grade solid state drives (SSDs)
venue: 2016 IEEE 37th International Electronics Manufacturing Technology (IEMT) 18th Electronics Materials and Packaging (EMAP) Conference
year: 2016

abstract: In high reliability Surface Mount Technology (SMT) assembly applications, the ability to inspect the solder joints visually has been standard and has been key factors in providing confidence in solder joint reliability. Inspection techniques such as X ray can be used to detect gross manufacturing defects such as solder bridging, but are not suitable for detection of other defects such as cracks. Temperature cycling test (TCT) is a standard solder joint reliability assessment method in semiconductor reliability for ball grid array (BGA) packaging. SMT reflow process and CTE (coefficient of thermal expansion) between solder materials, PCB and BGA package have high influence in solder joint reliability. A careful experimental investigation was undertaken to evaluate the reliability of solder joints of SAC BGA components formed using Sn 2Ag Cu Ni solder paste. This evaluation specifically looked at the impact of time above liquidus, peak temperature and thermal interface material (TIM) on solder joint reliability. Four types of samples prepared with the peak temperature of 2500C and no TIM, 2500C with TIM, time above liquidus (TAL) 90 seconds and no TIM and TAL 90 seconds with TIM. A total of 60 drives were assembled and subjected to accelerated thermal cycling (ATC) test in the temperature range of 00C to 1000C for a maximum of 2000 cycles with reference to JESD22 A104 standard. Based on the results from the deisgn of experiment (DOE) TAL 90s profile have demonstrated better TCT reliability margin compared to peak temperature of 2500C.
author_names: Mohammad Zainudeen Moideen

Chong Leong Gan
title: Solder joint reliability enhancement through surface mounting solder joint reflow optimization in enterprise grade solid state drives (SSDs)
venue: 2016 IEEE 37th International Electronics Manufacturing Technology (IEMT) 18th Electronics Materials and Packaging (EMAP) Conference
year: 2016

abstract: Fan out wafer level packaging (FOWLP) is one of the latest technologies to meet the requirements of high performance and thin form factor, especially for mobile application processors. To achieve a simple path way and thinner package form, many outsourced semiconductor assembly and test (OSAT) suppliers and foundries provide FOWLP capabilities. Most solutions are limited to the bottom 2D package area with a package on package (PoP) stacking structure to communicate logic to memory or a peripheral chip beyond the 2D distribution area. This means that communication between heterogeneous chips has more power and signal loss by PoP interconnection to reach hetero chip functions through bulk solder ball joints and printed circuit board (PCB) laminated routing with more coarse trace pattern than a fan out (FO) redistribution layer (RDL pattern) To improve this situation, high performance heterogeneous integration has been simulated and successfully realized with the novel 3D Silicon Wafer Integrated Fan out Technology (SWIFT(r) prototype as chip stackable, ultra thin, high flexibility FOWLP for the first ultimate 3D packaging. Also, this has been proven to be a highly flexible and cost effective structure with a low risk process flow, low package warpage, stable electrical performance, and good reliability performance. The form factor of the 3D SWIFT design with various structure options is as much as 45% thinner than PoP technology.
author_names: WonMyoung Ki

Wongeol Lee

In Su Mok

Ilbok Lee

WonChul Do

Mohammed Kolbehdari

Alex Copia

Suresh Jayaraman

Curtis Zwenger

KangWook Lee
title: Chip Stackable, Ultra thin, High Flexibility 3D FOWLP (3D SWIFT(r) Technology) for Hetero Integrated Advanced 3D WL SiP
venue: 2018 IEEE 68th Electronic Components and Technology Conference (ECTC)
year: 2018

abstract: Due to environmental concerns, the need for lead free solutions in electronic components and systems is receiving increasing attention within the semiconductor and electronics industries. Sn Ag Cu systems are some of the more promising materials to replace the eutectic Sn Pb solder. In this paper, a chip scale package assembled on board test and a notebook motherboard surface mount assembly were used to investigate the characteristics of Sn 3.0 Ag 0.5 Cu solder alloy from three different companies. One eutectic tin lead solder was included for comparison. For the chip scale package, the PCB's surface finish included OSP (organic solderability preservatives) and electroless Ni/immersion Au. OSP and immersion Ag PCB surface finish was used in the notebook motherboard surface mount assembly. In circuit test and function test were used to evaluate the properties. Thermal cycling test was used to evaluate the reliability of the solder joints. Failure modes of Sn Ag Cu solder and Sn Pb solder alloys were also investigated. Scanning electron microscope (SEM) and optical microscope (OM) were utilized to observe the fracture morphology; energy dispersive spectrometer (EDS) was employed to analyze the distribution of the elements and the intermetallic compounds (IMCs) formed at the interface. All the chip scale package samples passed the electrical test after 2500 thermal cycles. All Sn Pb and Sn Ag Cu solder joints of CSP possess good board level reliability. But the TCT results of notebook motherboard assembled by Sn Ag Cu were not so good. About one half of samples didn't pass the function test after 500 thermal cycles. By failure analyses, we found some cracks in the joints and all the failed components were made by ceramic based chip.
author_names: Jian-Shu Wu

Shan-Pu Yu

I-Hsuan Peng

Jong-Lih Wang

B Chung
title: Board level reliability of lead free SnAgCu solder joint
venue: Proceedings of the 4th International Symposium on Electronic Materials and Packaging, 2002.
year: 2002

abstract: Technologies are focusing on empowering consumers with more functionalities into compact assemblies such as ball grid array (BGA) and Chip Scale Packaging (CSP) offering small form factors to enable high density semiconductor applications. Reliable performance under drop test conditions is of paramount importance for components targeted for some hand held applications. Drop testing per JESD22 B111, prescribed by the Joint Electronic Device Engineering Council (JEDEC) is an industrial standard to characterize mechanical reliability of solder joints subject to drop impact under the specified test conditions. This specification was recently revised to JESD22 B111A version, with intent to provide homogenous stress distribution for all components mounted on the newly prescribed PCB layout. The objective of this paper is to assess the impact of these test board changes on drop test performance of solder interconnects and failure modes generated. It is carried out by recording the board dynamic response upon drop impact for test boards with three different form factors. It is complemented well with the Finite Element Modelling (FEM) developed for the studied drop test settings. The investigation is supported by targeted experiments on some prominent package styles. The drop test results show increased characteristic lifetime of solder joints when dropped using the square shaped test board defined by JESD22 B111A as compared to the outstanding studied specifications. This observation is linked to the impact of changing drop impact pulse, PCB form factor and build up construction on the board dynamics such as resonance frequency modes and PCB deformation.
author_names: Varun Thukral

Jeroen J M Zaal

R Roucou

J Jalink

R T H Rongen
title: Understanding the Impact of PCB Changes in the Latest Published JEDEC Board Level Drop Test Method
venue: 2018 IEEE 68th Electronic Components and Technology Conference (ECTC)
year: 2018

abstract: Solid state lighting (SSL) which is based 0n semiconductor Lighting Emitting Diode (LED) is the most promising and reliable energy saving solution for future lighting applications. Since a bare LED die can hardly survive without a package, one of the most import function of the LED package is to facilitate the electrical connection and heat dissipation of the light engine mounted on a printed circuit board (PCB) by Land Grid Array (LGA) solder joints. These joints have been proven to be one of the most vulnerable link in the system. Therefore, evaluating the reliability of solder joints becomes vital to ensure the long term reliability of this new lighting product. A combined theoretical and experimental approach based on Finite Element (FE) calculations is a fast and commonly adopted way of estimating the solder reliability in microelectronics industry. However, there is no fatigue model that is particularly suitable for Land Grid Array (LGA) solder joints, which are mostly employed in board level LED packages. Additionally, it would be desirable to have cruder engineering guidelines to quickly estimate the effect of the various geometries and dimensions for new trial LGA configurations. On the other hand, relatively accurate lifetime predictions still required Accelerated Life Tests (ALT) However, current reliability testing methods based on the detection of final catastrophic failure generally require very long test time (up to 9000 hours or 55 weeks) which does not meet the industrial target to limit the testing time to 6 12 weeks. A test method that is capable of carefully separating and in situ monitoring the fatigue damages may be able to resolve the issue by offering the possibility of early termination of the test once enough information is collected to predict final and catastrophic failure. In addition, this capability can be attractive to make more accurate Remaining Useful Lifetime prognostic of solder joint in many critical electronics in other systems. In Chapter 2, it was demonstrated that the widely accepted fatigue model for predicting the lifetime of BGA solder joint no longer valid for assessing reliability of solder joint in a LGA assembly due to its inappropriate critical elements selection method. Therefore, a more suitable critical element selection method for LGA assemblies is proposed based on statistical analysis of creep energy density distribution for elements in the vicinity of the likely crack initiation point. By adopting this new critical element selection method, a new energy based fatigue model for predicting LGA solder life times has been established by combining lifetime measurements with corresponding Finite Element Method (FEM) simulations for different material combinations and different LED package configurations. The model has a much better predictive power than the model based on the BGA approach. In chapter 3, a phenomenological response surface model is derived for a fast qualification of the reliability of LED packages with different designs by conducting a series of FEM simulations. It seems that a smaller carrier size and larger solder standoff height in general will result in better solder reliability. This trend is more pronounced in solder with smaller carrier size and larger stand off height. Additionally, solder reliability decreases rapidly with solder coverage decreasing. The ratio between thermal solder area and electrical solder area AR has a significant influence on solder joint reliability in a SSL system. The optimal AR value is also observed to relate to carrier size and solder coverage. In general, the optimal AR value increases with increasing carrier size, and this phenomenon is more pronounced in packages with smaller solder coverage. When the chip carrier size is relative small, it is advisable to make the thermal pad and electrical pad comparable. The proposed methodology in this work, a combination of energy based fatigue modeling and FEM modeling proves to be very valuable for solder reliability optimization for LED packages. This methodology can also be applied to optimize the package configuration in terms of thermal performance, electrical performance, cost and combinations thereof. The predictive power and the limitations of the approach are also discussed in Chapter 3. The advantages of in situ high precision damage monitor during ALT are demonstrated, which offers great potential to save testing time. In Chapter 4, precise fatigue damage monitoring is proven to be achievable by conducting in situ high precision (apx. 80 n? electrical resistance measurement of each individual solder joint during testing. The method was shown to be capable of capturing viscoplastic deformation accumulation, resulted crack initiation and sequenced crack propagation in an isothermal fatigue test. Moreover, in Chapter 5, it is demonstrated that using dedicated electrode configurations, different types of fatigue damages can be separated from each other or highlighted depending on the testing purpose. The effect of viscoplastic deformation can best be separated from those due to crack formation in one electrode configuration whereby progressive viscoplastic deformation induces resistance decay, whereas crack initiation and propagation provokes resistance increasing. It allows a rather precise yet conservative estimation of the crack initiation point. The other two configurations studied demonstrated superior sensitivity to crack opening and closure during fatigue cycling, which gives saw teeth shaped signal patterns, in which case the measured resistance increases with both progressive viscoplastic deformation and propagating crack. The experimental findings agree with results from FEA simulation and periodic tomographic analyses. However, even for very high resolution of the electrical resistance measurements as in the present work, identification of the very early stages of crack initiation (less than 5% of the joint contact zone) remains not really feasible. In Chapter 6, the knowledge gained for monitoring failure under isothermal conditions is transferred to the testing of solder joints subjected to thermo mechanical loading, employing a different crack initiation identification method. Accelerated temperature cycling test was done to four LED like board level ceramic packages with in situ periodic high precision electrical resistance monitoring for each solder joint inside. Not the actual electrical resistance values but the change in Temperature Coefficient of Resistance (TCRc) of the solder joint was correlated to fatigue damage evolution in the joint. Both viscoplastic deformation accumulation and crack propagation increase the TCR. A method to identify the crack initiation point based on the noise analysis of in situ TCRc monitoring signal of individual solder joint is presented. It is observed that once a major crack is present in the joint the noise level increases significantly, and the rate of TCR increase increases with further crack growth. The crack initiation point as determined from the electrical resistance data using a built in variance analysis tool in Matlab, was verified by micro tomographic results and FEM simulation predictions. The new method as developed can be a very attractive technique for both solder accelerated test and RUL prognostics.
author_names: Jianshan Zhang
title: Fast Qualification of Solder Reliability in Solid state Lighting System
year: 2015

abstract: The solder joint reliability of semiconductor package interconnects is critical to product durability. A dominant failure mode is solder fatigue due to the CTE mismatch between BGA component and PCB at thermal cycling. It is well known that besides thermal expansion mismatch of component and board, the solder joint geometry has a great impact on fatigue behavior and time to failure. In this study, a combination of Surface Evolver and finite element analysis are use to predict the solder joint shapes for the assembly of medium pin count BGA's and to estimate the reliability at accelerated temperature cycling conditions. Results of Surface Evolver are compared with the assumption of a truncated sphere. The solder shape predictions are applied for a subsequent thermo mechanical analysis of the BGA assembly. Inelastic creep deformation is evaluated for critical solder balls, and the Coffin Manson relation is used to estimate the solder joint lifetime. The entire simulation procedure will be demonstrated for a.
author_names: Betty Yeung

Torsten Hauck

Brett Wilkerson

T Koschmieder
title: Thermal Cycling Analysis of BGA Solder Joint Reliability
year: 2012

abstract: Trends in the packaging of semiconductors are towards miniaturization and high functionality. The package on package (PoP) with increasing demands is beneficial in cost and space saving. This study conducts the assembly of the PoP component through the stacking process. Samples are subject to thermal cycling test condition, 0degC to 100degC. The failure of samples is defined as when the measured resistance is above 3D. The cross section and dye penetrate analysis are used to investigate the failure modes. Results shows that majority of failure occurred to bottom components. The failure location is at interface between component pad and the solder joint due to the CTE mis match between bottom chip and the PCB. The warpage of PoP substrate has resulted in variation in standoff height across the components. Failure data is verified to follow a Weibull distribution. The parameters of the Weibull distribution are identified. The expected life for the PoP solder joint is determined to be 5600 cycles in the temperature range of 0degC to 100degC.
author_names: Jimmy Yang

Jay Cy Huang

K C Li

J L Ku

Andrew Lee
title: Reliability assessment for the PoP lead free solder joint through temperature cycling test
venue: 2010 5th International Microsystems Packaging Assembly and Circuits Technology Conference
year: 2010

abstract: Recently, handheld electronic products are prone to being dropped during their useful service life because of their size and weight. Board level solder joint reliability performance of IC packages during drop impact becomes a great concern to semiconductor and electronic product manufacturers. The packages are susceptible to solder joint failures, induced by a combination of PCB bending and mechanical shock during impact. Therefore, board level drop testing is an effective method to characterize the solder joint reliability performance of miniature handheld products. In this study, we examine and compare simulation the board level drop test of SSD. Applying the JEDEC (JESD22 B111) standard present a finite element modeling of the BGA package assembly was performed to study the stress and strain behavior of the solder joints during drop test. The simulation revealed that maximum stress was located at the outermost solder ball in the PCB or Package side, which consisted well with the location of crack initiation observed in the failure analysis after drop reliability tests.
author_names: Tae Min Kang

Yong Chang Lee

Byung Kwon Bae

Won Seob Song

Jae Sung Lee
title: A study on the correlation between experiment and simulation board level drop test for SSD
venue: 2017 18th International Conference on Thermal, Mechanical and Multi Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE)
year: 2017