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abstract: Abstract Rapid developments in semiconductor technology have substantially increased the computational capability of computers. As a result of this and recent developments in theory, machine learning (ML) techniques have become attractive in many new applications. This trend has also inspired researchers working on integrated circuit (IC) design and optimization. ML based design approaches have gained importance to challenge/aid conventional design methods since they can be employed at different design levels, from modeling to test, to learn any nonlinear input output relationship of any analog and radio frequency (RF) device or circuit; thus, providing fast and accurate responses to the task that they have learned. Furthermore, employment of ML techniques in analog/RF electronic design automation (EDA) tools boosts the performance of such tools. In this paper, we summarize the recent research and present a comprehensive review on ML techniques for analog/RF circuit modeling, design, synthesis, layout, and test.
author_names: Engin Afacan

Nuno C Lourenco

Ricardo Martins

Gunhan Dundar
title: Review: Machine learning techniques in analog/RF integrated circuit design, synthesis, layout, and test
venue: Integr.
year: 2021

abstract: Transient stability analysis (TSA) plays an important role in power system analysis to investigate the stability of power system. Traditionally, transient stability analysis methods have been developed using time domain simulation by means of numerical integration method. In this paper, a new approach is proposed to model power systems as an integrated circuit and simulate the power system dynamic behavior by integrated circuit simulator as preliminary exploration for the ambition of using very large scale integrated circuit chip to mimic power system behaviors. The proposed method modeled power grid, generator, governor, and exciter with high fidelity. The power system dynamic simulation accuracy and efficiency of the proposed approach are verified and demonstrated by case study on an IEEE standard system.
author_names: Renchang Dai

Peng Wei

Yijing Liu

Zhiwei Wang
title: Power System Transient Modeling and Simulation using Integrated Circuit
venue: ArXiv
year: 2021

abstract: We present Simphony, a free and open source software toolbox for abstracting and simulating photonic integrated circuits, implemented in Python. The toolbox is both fast and easily extensible; plugins can be written to provide compatibility with existing layout tools, and device libraries can be easily created without a deep knowledge of programming. We include several examples of photonic circuit simulations with novel features and demonstrate a speedup of more than 20x over a leading commercially available software tool.
author_names: Sequoia Ploeg

Hyrum Gunther

Ryan M Camacho
title: Simphony: An Open Source Photonic Integrated Circuit Simulation Framework
venue: Computing in Science Engineering
year: 2021

abstract: This paper presents our proposed methods to ICDAR 2021 Robust Reading Challenge Integrated Circuit Text Spotting and Aesthetic Assessment (ICDAR RRCICTEXT 2021) For the text spotting task, we detect the characters on integrated circuit and classify them based on yolov5 detection model. We balance the lowercase and non lowercase by using SynthText, generated data and data sampler. We adopt semi supervised algorithm and distillation to furtherly improve the model's accuracy. For the aesthetic assessment task, we add a classification branch of 3 classes to differentiate the aesthetic classes of each character. Finally, we make model deployment to accelerate inference speed and reduce memory consumption based on NVIDIA Tensorrt. Our methods achieve 59.1 mAP on task 3.1 with 31 FPS and 306M memory (rank 1) 78.7% F2 score on task 3.2 with 30 FPS and 306M memory (rank 1)
author_names: Qiyao Wang

Li Zhu

Yi Niu
title: 1st Place Solution to ICDAR 2021 RRC ICTEXT End to end Text Spotting and Aesthetic Assessment on Integrated Circuit
venue: ArXiv
year: 2021

abstract: A miniaturized Ka band bandpass filter (BPF) is presented by using monolithic microwave integrated circuit (MMIC) technology in this brief. Aiming at low cost and high integration, small die area of MMIC BPFs is significantly required for RF front end modules.However, the filtering performance of BPFs is negatively correlated to its miniaturization. To this end, the folded hybrid resonator is investigated in this brief, which is composed of a quasi lumped capacitor and a distributed microstrip line. To realize miniaturization, two metal layers of GaAs process are fully utilized. For low loss, the distributed inductor is designed on the top thick layer, while the quasi lumped capacitor is on the lower metal layer of high sheet resistance. To reduce the unwanted mutual coupling between adjacent quasi lumped capacitors, shielding structures are added into BPFs, resulting in a 5 dB and 12 dB enhancement to the lower and upper stopbands, respectively. Based on the mixed electric magnetic coupling topology, a second order MMIC bandpass filter is designed and fabricated by using GaAs process. Small die area, low loss, high selectivity, and wide stopband are simultaneously obtained, indicating a promising application of the proposed miniaturized MMIC bandpass filters.
author_names: Guangxu Shen

Wenquan Che

Wenjie Feng

Yongrong Shi

Yiming Shen
title: A Miniaturized Ka Band Bandpass Filter Using Folded Hybrid Resonators Based on Monolithic Microwave Integrated Circuit Technology
venue: IEEE Transactions on Circuits and Systems II: Express Briefs
year: 2021

abstract: In this study, for two cases of monolithic 3 dimensional integrated circuit (M3DIC) consisting of vertically stacked feedback field effect transistors (FBFETs) the variation of electrical characteristics of the FBFET was presented in terms of electrical coupling by using technology computer aided design (TCAD) simulation. In the Case 1, the M3DIC was composed with an N type FBFET in an upper tier (tier2) and a P type FBFET in a lower tier (tier1) and in the Case 2, it was composed with the FBFETs of opposite type of the Case 1 on each tier. To utilize the FBFET as a logic device, the study on optimal structure of FBFET was first performed in terms of reducing a memory window. Based on the N type FBFET, the memory window was investigated with different values of doping concentration and length of channel region divided into two regions. The threshold voltage, capacitance, and transconductance of two cases of M3DIC composed with proposed FBFET were investigated for different thickness of an interlayer dielectric (TILD) In the Case 1, only for reverse sweep, the threshold voltage of FBFET in the tier2 was changed significantly at TILD 15 nm, and the capacitance and transconductance of FBFET in the tier2 changed significantly at TILD 20 nm, as bottom gate voltage applied with 0 and 1 V. In the Case 2, the electrical characteristics of FBFET in the tier2 changed greater than Case 1 with different TILD.
author_names: Jong Hyeok Oh

Yun Seop Yu
title: Electrical Coupling for Monolithic 3 D Integrated Circuit Consisting of Feedback Field Effect Transistors.
venue: Journal of nanoscience and nanotechnology
year: 2021

abstract: Miniaturized implantable devices play a crucial role in neural interfaces by monitoring and modulating neural activities on the peripheral and central nervous systems. Research efforts toward a compact wireless closed loop system stimulating the nerve automatically according to the user's condition have been maintained. These systems have several advantages over open loop stimulation systems such as reduction in both power consumption and side effects of continuous stimulation. Furthermore, a compact and wireless device consuming low energy alleviates foreign body reactions and risk of frequent surgical operations. Unfortunately, however, the miniaturized closed loop neural interface system induces several hardware design challenges such as neural activity recording with severe stimulation artifact, real time stimulation artifact removal, and energy efficient wireless power delivery. Here, we will review recent approaches toward the miniaturized closed loop neural interface system with integrated circuit (IC) techniques.
author_names: Jaeouk Cho

Geunchang Seong

Yonghee Chang

Chul-Woong Kim
title: Energy Efficient Integrated Circuit Solutions Toward Miniaturized Closed Loop Neural Interface Systems
venue: Frontiers in Neuroscience
year: 2021

abstract: In this work, we present a significant step toward in vivo ophthalmic optical coherence tomography and angiography on a photonic integrated chip. The diffraction gratings used in spectral domain optical coherence tomography can be replaced by photonic integrated circuits comprising an arrayed waveguide grating. Two arrayed waveguide grating designs with 256 channels were tested, which enabled the first chip based optical coherence tomography and angiography in vivo three dimensional human retinal measurements. Design 1 supports a bandwidth of 22 nm, with which a sensitivity of up to 91 dB (830 uW and an axial resolution of 10.7 um was measured. Design 2 supports a bandwidth of 48 nm, with which a sensitivity of 90 dB (480 uW and an axial resolution of 6.5 um was measured. The silicon nitride based integrated optical waveguides were fabricated with a fully CMOS compatible process, which allows their monolithic co integration on top of an optoelectronic silicon chip. As a benchmark for chip based optical coherence tomography, tomograms generated by a commercially available clinical spectral domain optical coherence tomography system were compared to those acquired with on chip gratings. The similarities in the tomograms demonstrate the significant clinical potential for further integration of optical coherence tomography on a chip system. The goal of an optical coherence tomography (OCT) imaging system that is integrated on a photonic chip has taken a step closer to reality. Elisabet Rank and coworkers from Austria have shown that arrayed waveguide gratings (AWGs) integrated optical devices commonly used to separate different wavelength channels in an optical communications system, can be used to replace diffraction gratings in an OCT system. Several designs of silicon nitride AWGs with 256 channels in the near infrared were fabricated and then tested in an OCT system which was able to capture in vivo tomograms and angiography of the human eye's retina, with comparable quality to a conventional system. The next stage of the OCT on a chip research will focus on exploring the use of multimode interference structures, integrated photodiodes, and compact light sources.
author_names: Elisabet Rank

Ryan Sentosa

Danielle J Harper

Matthias Salas

Anna Gaugutz

Dana Seyringer

Stefan Nevlacsil

Alejandro Maese-Novo

Moritz Eggeling

Paul Muellner

Rainer Hainberger

Martin Sagmeister

Jochen Kraft

Rainer A Leitgeb

Wolfgang Drexler
title: Toward optical coherence tomography on a chip: in vivo three dimensional human retinal imaging using photonic integrated circuit based arrayed waveguide gratings
venue: Light, science applications
year: 2021

abstract: We demonstrate an ultra sensitive waveguide enhanced Raman sensor for low concentration organic compounds dissolved in water. The spectra are obtained using silicon nitride slot waveguides coated with a thin film of hexamethyldisilazane modified mesoporous silica. Enriched locally by 600 fold within the coating, a micromolar level of cyclohexanone is probed. The sensor is also capable of simultaneous quantification of multiple analytes, and the adsorbed analytes can be completely released from the coating. These properties make this on chip Raman sensor promising for diverse applications, especially for the monitoring of non polar organics and biomolecules in aqueous environments.
author_names: Zuyang Liu

Haolan Zhao

Bettina Baumgartner

Bernhard Lendl

Andim Stassen

Andre G Skirtach

Nicolas Le Thomas

Roel Baets
title: Ultra sensitive slot waveguide enhanced Raman spectroscopy for aqueous solutions of non polar compounds using a functionalized silicon nitride photonic integrated circuit.
venue: Optics letters
year: 2021

abstract: Recycling of used ICs as new replacement parts in maintaining older electronic systems is a serious reliability concern. This paper presents a novel approach to estimate the operational age of CMOS chips by measuring IDDQ, the quiescent current from power supply or the total leakage current in steady state. This current decreases as the circuit ages, largely due to the increase in the magnitude of the PMOS transistor threshold voltage caused by negative bias temperature instability (NBTI) We exploit the fact that the impact of NBTI on an individual transistor depends upon the operational stress based upon the duration of its ON state. Novelty of our technique is a normalized difference, I, computed from current measurements at two input test patterns and is proposed as a self referencing circuit age indicator. The first pattern is chosen such that its IDDQ is controlled by a large number of minimally stressed PMOS transistors; for the other the IDDQ is controlled by approximately equal number of highly stressed PMOS transistors. The difference between these two IDDQ values increases with the circuit age. This approach requires no hardware modification in the circuit and, hence, can be applied to legacy ICs. Simulation results show that we can reliably identify recycled ICs that have been used for as little as six months. Prattay Chowdhury E mail: prattay.chowdhury@utdallas.edu Ujjwal Guin E mail: ujjwal.guin@auburn.edu Adit D. Singh E mail: adsingh@auburn.edu Vishwani D. Agrawal E mail: agrawvd@auburn.edu 1Department of Electrical and Computer Engineering, University of Texas at Dallas, Richardson, TX 75080, USA 2Department of Electrical and Computer Engineering, Auburn University, Auburn, AL 36849, USA
author_names: Prattay Chowdhury

Ujjwal Guin

Adit D Singh

Vishwani D Agrawal
title: Estimating Operational Age of an Integrated Circuit
venue: J. Electron. Test.
year: 2021