Search query: gate dielectric high-k

Related papers:

abstract: A newly synthesized high k polymeric insulator for use as gate dielectric layer for organic field effect transistors (OFETs) obtained by grafting poly(methyl methacrylate) (PMMA) in poly(vinylidene fluoride trifluoroethylene) (P(VDF TrFE) via atom transfer radical polymerization transfer is reported. This material design concept intents to tune the electrical properties of the gate insulating layer (capacitance, leakage current, breakdown voltage, and operational stability) of the high k fluorinated polymer dielectric without a large increase in operating voltage by incorporating an amorphous PMMA as an insulator. By controlling the grafted PMMA percentage, an optimized P(VDF TrFE) g PMMA with 7 mol% grafted PMMA showing reasonably high capacitance (23 30 nF cm 2) with low voltage operation and negligible current hysteresis is achieved. High performance low voltage operated top gate/bottom contact OFETs with widely used high mobility polymer semiconductors, poly[[2,5 bis(2 octyldodecyl) 2,3,5,6 tetrahydro 3,6 dioxopyrrolo [3,4 c]pyrrole 1,4 diyl] alt [2,2' (2,5 thiophene)bis thieno(3,2 b)thiophene] 5,5' diyl] (DPPT TT) and poly([N,N' bis(2 octyldodecyl) naphthalene 1,4,5,8 bis(dicarboximide) 2,6 diyl] alt 5,5' (2,2' bithiophene) are demonstrated here. DPPT TT OFETs with P(VDF TrFE) g PMMA gate dielectrics exhibit a reasonably high field effect mobility of over 1 cm2 V 1 s 1 with excellent operational stability.
author_names: Eul-Yong Shin

Hye Jin Cho

Sungwook Jung

Changduk Yang

Yong-Young Noh
title: A High k Fluorinated P(VDF TrFE) g PMMA Gate Dielectric for High Performance Flexible Field Effect Transistors
year: 2018

abstract: In this work, low temperature fabrication of a sputtered high k HfO2 gate dielectric for flexible a IGZO thin film transistors (TFTs) on polyimide substrates was investigated. The effects of Ar pressure during the sputtering process and then especially the post annealing treatments at low temperature =200 degC) for HfO2 on reducing the density of defects in the bulk and on the surface were systematically studied. X ray reflectivity, UV vis and X ray photoelectron spectroscopy, and micro wave photoconductivity decay measurements were carried out and indicated that the high quality of optimized HfO2 film and its high dielectric properties contributed to the low concentration of structural defects and shallow localized defects such as oxygen vacancies. As a result, the well structured HfO2 gate dielectric exhibited a high density of 9.7 g/cm3, a high dielectric constant of 28.5, a wide optical bandgap of 4.75 eV, and relatively low leakage current. The corresponding flexible a IGZO TFT on polyimide exhibited an optimal device performance with a saturation mobility of 10.3 cm2 V 1 s 1, an Ion/Ioff ratio of 4.3 x 107, a SS value of 0.28 V dec 1, and a threshold voltage (Vth) of 1.1 V, as well as favorable stability under NBS/PBS gate bias and bending stress.
author_names: Rihui Yao

Zheng Zeke

Mei Xiong

Zhang Xiaochen

Liu Xiaoqing

Honglong Ning

Zhiqiang Fang

Weiguang Xie

Xubing Lu

Junbiao Peng
title: Low temperature fabrication of sputtered high k HfO2 gate dielectric for flexible a IGZO thin film transistors
year: 2018

abstract: Enhancement mode GaN MOS HEMTs with a uniform threshold voltage <inline formula> <tex math notation="LaTeX"{V}_{\text {th}\sim \text {2.2 \pm \text {0.25} /tex math>/inline formula> V at <inline formula> <tex math notation="LaTeX"{I}_{D} \text {1}\mu \text{A} /tex math>/inline formula>/mm) have been achieved by a recess free barrier engineering technique in conjunction with a high <inline formula> <tex math notation="LaTeX"{k} /tex math>/inline formula> gate dielectric. The design includes an ultrathin ~6 nm) Al<sub>0.2</sub>Ga<sub>0.8</sub>N barrier preserving the two dimensional electron gas (2DEG) mobility underneath the gate and a selective area barrier regrowth to restore the 2DEG at the access regions. A high <inline formula> <tex math notation="LaTeX"{k} /tex math>/inline formula> ZrO<sub>2</sub> gate dielectric was employed to enhance the gate control over the channel. The common issue of recess induced damage was mitigated. The high quality gate stack results not only in a highly uniform and large <inline formula> <tex math notation="LaTeX"{V}_{\text {th} /tex math>/inline formula> but also small hysteresis, minimal gate lag, low on resistance, and high output current in the E MOS HEMTs.
author_names: Huaxing Jiang

Chak Wah Tang

Kei May Lau
title: Enhancement Mode GaN MOS HEMTs With Recess Free Barrier Engineering and High {k} ZrO2 Gate Dielectric
venue: IEEE Electron Device Letters
year: 2018

abstract: Abstract This paper investigates the performance of 6 T SRAM cell using high K gate dielectric based junctionless silicon nanotube FET (JLSiNTFET) It is observed that the use of high K gate dielectric enhances the delay performance of the JLSiNTFET based 6 T SRAM cell. Read access time (RAT) and write access time (WAT) improves by ~18% and ~20% when TiO 2 is used as gate dielectric instead of SiO 2 The hold, read, and write SNMs (static noise margin) of the 6 T SRAM cell also improves marginally by the use of high K gate dielectric. Furthermore, it is also observed that the improvement in hold SNM (HSNM) read SNM (RSNM) and write SNM (WSNM) can be boosted by using higher interfacial layer thickness (T I However, the improvement in read access times (RAT) write access time (WAT) degrades at higher T I Thus, high K gate dielectrics with high interfacial layer thickness are more suitable for JLSiNT FET based 6 T SRAM cell.
author_names: Shubham Tayal

Ashutosh Nandi
title: Study of 6T SRAM cell using High K gate dielectric based junctionless silicon nanotube FET
year: 2017

abstract: MoS2 and other atomic level thick layered materials have been shown to have a high potential for outperforming Si transistors at the scaling limit. In this work, we demonstrate a MoS2 transistor with a low voltage and high ON/OFF ratio. A record small equivalent oxide thickness of ~1.1 nm has been obtained by using ultra high k gate dielectric Pb(Zr0.52Ti0.48)O3. The low threshold voltage <0.5 V) is comparable to that of the liquid/gel gated MoS2 transistor. The small sub threshold swing of 85.9 mV dec( 1) the high ON/OFF ratio of ~10(8) and the negligible hysteresis ensure a high performance of the MoS2 transistor operating at 1 V. The extracted field effect mobility of 1 10 cm(2) V( 1) s( 1) suggests a high crystalline quality of the CVD grown MoS2 flakes. The combination of the two dimensional layered semiconductor and the ultra high k dielectric may enable the development of low power electronic applications.
author_names: Changjian Zhou

Xinsheng Wang

Salahuddin Raju

Ziyuan Lin

D Villaroman

Baoling Huang

Helen L W Chan

Mansun Chan

Yang Chai
title: Low voltage and high ON/OFF ratio field effect transistors based on CVD MoS2 and ultra high k gate dielectric PZT.
venue: Nanoscale
year: 2015

abstract: Black phosphorus (BP) is the most stable allotrope of phosphorus which exhibits strong in plane anisotropic charge transport. Discovering its interface properties between BP and high k gate dielectric is fundamentally important for enhancing the carrier mobility and electrostatics control. Here, we investigate the impact of interface engineering on the transport properties of BP transistors with an ultra thin hafnium dioxide (HfO2) gate dielectric of ~3.4 nm. A high hole mobility of ~536 cm2V 1s 1 coupled with a near ideal subthreshold swing (SS) of ~66 mV/dec were simultaneously achieved at room temperature by improving the BP/HfO2 interface quality through thermal treatment. This is attributed to the passivation of phosphorus dangling bonds by hafnium (Hf) adatoms which produces a more chemically stable interface, as evidenced by the significant reduction in interface states density. Additionally, we found that an excessively high thermal treatment temperature (beyond 200 degC) could detrimentally modify the BP crystal structure, which results in channel resistance and mobility degradation due to charge impurities scattering and lattice displacement. This study contributes to an insight for the development of high performance BP based transistors through interface engineering.
author_names: Zhi Peng Ling

Juntao Zhu

Xinke Liu

Kah-Wee Ang
title: Interface Engineering for the Enhancement of Carrier Transport in Black Phosphorus Transistor with Ultra Thin High k Gate Dielectric
venue: Scientific reports
year: 2016

abstract: The microstructure, optical and electrical properties of HfTiO high k gate dielectric thin films deposited on Si substrate and quartz substrate by RF magnetron sputtering have been investigated. Based on analysis from x ray diffraction (XRD) measurements, it has been found that the as deposited HfTiO films remain amorphous regardless of the working gas pressure. Meanwhile, combined with characterization of ultraviolet visible spectroscopy (UV vis) and spectroscopy ellipsometry (SE) the deposition rate, band gap and optical properties of sputtered HfTiO gate dielectrics were determined. Besides, by means of the characteristic curves of high frequency capacitance voltage (C V) and leakage current density voltage (J V) the electrical parameters, such as permittivity, total positive charge density, border trap charge density, and leakage current density, have been obtained. The leakage current mechanisms are also discussed. The energy band gap of 3.70 eV, leakage current density of 1.39x10 5 A/cm2 at bias voltage of 2 V, and total positive charge density and border trap charge density of 9.16x1011 cm 2 and 1.3x1011 cm 2, respectively render HfTiO thin films deposited at 0.6 Pa, potential high k gate dielectrics in future CMOS devices.
author_names: S S Jiang

Gang He

J S Gao

D Q Xiao

P Jin

Weijie Li

Jianguo Lv

Meng Liu

Yanmei Liu

Zhaoqi Sun
title: Microstructure, optical and electrical properties of sputtered HfTiO high k gate dielectric thin films
year: 2016

abstract: Abstract Flexible OFET memory devices of semiconducting poly(9,9 dioctylfluorene alt bithiophene) (F8T2) on PEN substrates were fabricated and characterized using a high k poly(vinylidene fluoride co trifluoroethylene) (P(VDF TrFE) gate dielectric combined with donor acceptor polyimide electrets of (poly[2,5 bis(4 aminophenylenesulfanyl)selenophene hexafluoroisopropylidene diphthalimide] (APSP 6FDA) or poly[2,5 bis(4 aminophenylenesulfanyl)thiophene hexafluoroisopropylidenediphthalimide] (APST 6FDA) All the polymer thin films, including gate dielectric, charge storage, and semiconducting layer, possessed a smooth surface to form good contact adhesion between each layer, as confirmed by atomic force microscopy. The flexible OFET device could be operated using low gate voltage 3 The data storage characteristic was mainly attributed to the charge trapping in polyimide layer under a positive or negative gate bias. The studied flexible memories, moreover, exhibited stable electrical parameters, such as charge carrier mobility, threshold voltage change, and memory window, under a bending radius of 10 mm with 1000 repeating cycles, resulting in reproducible and reliable device characteristics. The experimental results indicated that a low voltage operated non volatile flexible OFET memory device could be simply integrated using all polymer components, including gate dielectric, charge storage electret, and semiconductor.
author_names: Mao-Shen Lu

Hung-Chin Wu

Yu-Wei Lin

Mitsuru Ueda

Wen-Chang Chen
title: Low voltage operation of non volatile flexible OFET memory devices using high k P(VDF TrFE) gate dielectric and polyimide charge storage layer
year: 2016

abstract: Now a days, high k dielectrics have been investigated as an alternative to Silicon dioxide (SiO"2) based gate dielectric for nanoscale semiconductor devices. This paper is an attempt to characterize the analog and RF performance of the high k metal gate (HKMG) double gate (DG) metal oxide semiconductor field effect transistor (MOSFET) in nanoscale through 2 D device simulation. The results demonstrates the impact of high k oxide layer as single and gate stack (GS) The key idea behind this investigation is to provide a physical explanation for the improved analog and RF performance exhibited by the device. The major figures of merit (FOMs) studied in this paper are transconductance (g"m) output conductance (g"d) transconductance generation factor (g"m/I"D) early voltage (V"E"A) intrinsic gain (A"V) cut off frequency (f"T) transconductance frequency product (TFP) gain frequency product (GFP) and gain transconductance frequency product (GTFP) The effects of downscaling of channel length (L) on analog performance of the proposed devices have also been presented. It has been observed that the performance enhancement of GS configurations (k=7.5 i.e device D5 in the study) is encouraging as far as the nanoscale DG MOSFET is concerned. Also it significantly reduces the short channel effects (SCEs) Parameters like DC gain of (91.257dB, 43.436dB) nearly ideal values (39.765V^ ^1, 39.589V^ ^1) of TGF, an early voltage of (2.73V, 16.897V) cutoff frequency (294GHz, 515.5GHz) and GTFP of (5.14x10^5GHz/V, 1.72x10^5GHz/V) for two different values of V"D"S=0.1V and 0.5V respectively are found to be close to ideal values. Analysis shows an opportunity for realizing high performance analog and RF circuits with the device proposed in this paper i.e. device D5.
author_names: Kumar Prasannajit Pradhan

Sushanta Kumar Mohapatra

Prasanna Kumar Sahu

D K Behera
title: Impact of high k gate dielectric on analog and RF performance of nanoscale DG MOSFET
venue: Microelectron. J.
year: 2014

abstract: Solution processed low voltage organic thin film transistors (OTFTs) were fabricated using the high mobility donor acceptor copolymer semiconductor indacenodithiophene co benzothiadiazole (IDTBT) and large permittivity (high k) relaxor ferroelectric polymer poly (vinylidene fluoride trifluoroethylene chlorofloroethylene) It is shown that, with the face on molecule packing in as deposited IDTBT films, the close interfacing between the backbone and the dielectric layer causes significant mobility degradation of the fabricated OTFTs due to dipole effects. By inserting a thin, low polar dielectric layer between the high k one and the channel, the dipole field can be effectively screened and the devices present a high mobility similar to that of previously reported high voltage IDTBT OTFTs. With the bilayer gate dielectric and the IDTBT semiconductor, low voltage OTFTs are achieved with the average mobility of 1.4 cm2/V* s and ON/OFF current ratio larger than 106, which is among the best reported performance so far for solution processed low voltage OTFTs.
author_names: Wei Tang

Jinhua Li

Jiaqing Zhao

Weimin Zhang

Feng Yan

Xiaojun Guo
title: High Performance Solution Processed Low Voltage Polymer Thin Film Transistors With Low $k$ /High $k$ Bilayer Gate Dielectric
venue: IEEE Electron Device Letters
year: 2015