Search query: capping HfO2 for CMOS

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abstract: Dear editor, High k/metal gate (HKMG) stacks with fully gatelast processing have become the primary solution for sub 22 nm volume manufacturing with the development of complementary oxide semiconductor (CMOS) technology [1] In the HKMG stack, titanium nitride (TiN) is observed to play an important role as a work function metal and an HK capping layer. Instead of the physical vapor deposition of TiN, the atomic layer deposition (ALD) of TiN has been extensively applied owing to its improved step coverage and filling capability with respect to the nanoscale trenches, particularly in case of nonplanar devices such as fin field effect transistors (FinFETs) As a work function metal electrode, thick ALD TiN layers have been reported to reduce the gate leakage and improve the reliability of the bias temperature instability (BTI) [2] However, few studies have reported the impact of ultrathin ALD TiN as a capping layer for HK dielectrics with respect to the electrical characteristics of the advanced HKMG CMOS devices, particularly in case of a positive BTI (PBTI) [3, 4] This study intends to investigate the impact of an ultrathin ALD TiN capping layer on the PBTI of n type FinFETs; we prepared two n type FinFET samples with and without an ALD TiN capping layer on a HfO2 HK dielectric. Further, the electrical measurements were performed under a constant electrical field and fixed gate bias (Vg) stresses, and energy dispersive spectrometry (EDS) analysis was conducted to verify the physical origin of the defects in the HK material.
author_names: Hong Yang

Luwei Qi

Yanbo Zhang

Bo Tang

Qianqian Liu

Hao Xu

Xueli Ma

Xiaolei Wang

Yongliang Li

Huaxiang Yin

Junfeng Li

Huilong Zhu

Chao Zhao

Wenwu Wang

Tianchun Ye
title: Influence of an ALD TiN capping layer on the PBTI characteristics of n FinFET with ALD HfO2/TiN capping/TiAl gate stacks
venue: Science China Information Sciences
year: 2020

abstract: Extreme scaling of CMOS devices has led to a number of challenges for characterization and analysis at high spatial resolution. Along with continued shrinking of feature size, such as channel length, contact size and gate oxide thickness, there is a concomitant deployment of new materials such as high dielectric constant (K) gate oxides, metal gate electrodes, and strained or high mobility channels. Future generation structures will likely include migration to 3D architectures. The focus of this study is a model gate stack which is comprised of a TiN metal gate electrode, a metal doped HfO2 high K dielectric and a very thin lower K interfacial SiO2 layer on Si. Metallic dopants in high K dielectrics, such as Al, La, Dy, or Ba, are often used to modify device threshold voltage (Vt) and/or increase K. In this study a thin <1nm) Ba capping layer is deposited onto HfO2 <2.5nm) which following an anneal leads to a large flat band voltage shift of 750mV relative to a Ba free stack desirable for low Vt n channel transistors, and an equivalent oxide thickness of 9A. Adding dopants to HfO2 for scaling is associated with increasing the dielectric constant of the SiO2 or the stabilization of higher K crystalline phases of HfO2 [1,2] The chief challenge for microanalysis for this system is the detection of metallic dopants without significant radiation damage. Empirically, a 3A 30pA probe (typical for a conventional FEG STEM) leads to visible damage after ~5s suggesting a critical dose of ~2nC/nm at 200kV. This implies exposure times of 0.16s should be possible for 1A 100pA Cs corrected probes. The dependence on kV and dose rate on the loss of chemical species during the irradiation has not yet been fully studied. For a 20nm thick sample the number of Ba atoms at 5at. in HfO2 is ~6 in a 3A probe and <1 in a 1A probe. The detection sensitivity by EELS for 5at.%Ba in HfO2 is estimated using "EELS Advisor" Using the 3A 30pA probe, detection requires an exposure time of ~2s. Evaluation of the maximum dose necessary to detect dopants when the sampled volume contains on average less than 1 requires only that single atom sensitivity is achieved. For the 1A 100pA probe this is accomplished with an 80ms exposure time, i.e. a factor of 2 less than would generate damage. FIG1 shows an HREM image of the Ba doped HfO2 and the interface layer. Diffractogram analysis of several HfO2 grains yields lattice spacings consistent with the higher K polymorphs (cubic, orthorhombic or tetragonal) rather than the common monoclinic structure. An EELS line profile analysis recorded using an FEI F20 STEM is shown in FIG2. The max Ba/O ratio measured is 0.07+ 0.02 which is equivalent to 5 at assuming either an HfO2 or SiO2 matrix. SNR of the extracted raw line profile is 12, consistent with "EELS advisor" value of 11 for 5at% Ba. To understand the Vt shift mechanism requires high resolution dopant distribution across the gate stack. A series of line profiles were recorded using the 1A Cs corrected NION SuperSTEM1 operating at 100kV. In this case we observe the Ba distribution being weighted towards the IL with relatively little remaining at the TiN/HfO2 interface Images before and after the line profile indicate modest damage. It is observed as a slight shoulder in the intensity profile in SiO2 layer. To extract the fractional amount of dopant in the IL and High K we assess the influence of elastic scattering on the signal strength. Acquisition of a low loss spectrum profiles indicates that correction factor is less 1892 doi:10.1017/S1431927610059738 Microsc. Microanal. 16 (Suppl 2) 2010 (c) Microscopy Society of America 2010
author_names: J Bruley

Martin M Frank

Vijay Narayanan

Budhika G Mendis

Mhairi H Gass
title: Structure and Composition of Metal Doped HfO2 Gate Oxides in CMOS Devices Studied by High Resolution STEM and EELS
year: 2010

abstract: Abstract High k materials have attracted great attention for their applications in nano scaled CMOS structures and memory. However, with the trend of scaling down in International Technology Roadmap for Semiconductors (ITRS) seeking for higher k dielectric oxides will be the key to meet the requirement for 22 nm and 15 nm node of CMOS technology. Lanthanum titanate (LTO) had been reported to have high dielectric constant and high crystallization temperature, which is taking the merit of TiO2 in high permittivity and La2O3 in thermal stability. Thus the higher k dielectric LTO is expected to have its potential in future high k dielectric. The LTO films is deposited on HfO2 in stacks structure via atomic layer deposition (ALD) technique in this study. The precursor systems used for deposition of lanthanum titanates were Tetrakis(dimethylamino) Titanium (TDMAT) water and tris(N N' diisopropylformamidinato) Lanthanum (La(iPr2 FMD)3) oxygen plasma. The electrical characteristics were measured in C V and I V relations, and the microstructure of thin films was inspected by transmission electron microscopy (TEM) X ray diffraction (XRD) X ray reflectivity (XRR) and X ray photoelectron spectroscopy (XPS) The LTO film is observed to diffuse in HfO2 through heat treatment, and yield in a new high k material which exhibits better properties than traditional HfO2 thin film and displays higher permittivity of 34.5 and lower equivalent oxide thickness (EOT) of 0.69 nm with a low leakage current of 10 2 A/cm2.
title: The Effect of higher k Lanthanum Titanate capping on HfO2 gate oxide via Atomic Layer Deposition
year: 2010

abstract: High k dielectrics are crucial in scaled CMOS technology because their large physical thickness can suppress gate tunneling leakage current at a scaled equivalent oxide thickness (EOT) For the past decade, hafnium based gate dielectrics (HfO2 or Hf based oxides) have been introduced to mass production by commercial chip makers. In the meantime, metal gates were also explored to improve the poly Si depletion effect polysilicon gate electrodes in high performance logic devices at 45 nm node technology and beyond. However, the development of metal gates with Fermi level near the Si band edges has been difficult on Hf based gate dielectrics, which can be attributed to several possible factors including Fermi level pinning and interfacial dipole formation.[1,2] Recently, the use of thin cap layers that are inserted between the gate metal and dielectric has been shown to cause negative flatband voltage (Vfb) shift and stabilize low VTH simultaneously. A major challenge with cap layers is to achieve adequate effective work function shifts without large increases in EOT (DEOT) Atomic layer deposition (ALD) La2O3 cap layer is a promising candidate for n channel devices due to its relatively high dielectric constant of ~17 [3] and strong bond polarization. Essentially, ALD is one precursor dominated process [4] successful applications of ALD in advanced CMOS technology should depend on whether appropriate precursor can be utilized. In this work, effects of the La2O3 cap layer interposed in Si/SiO2/HfO2/TiN high k gate dielectric stacks prepared from two different ALD lanthanum precursors, La(fAMD)3 and La(thd)3, in tuning Vfb and DEOT are investigated. The values of DVfb and DEOT as high as 0.45 V and 0.055 nm were achieved by a 1 nm thick La2O3 cap layer.
author_names: Chen Kuo Chiang

H -Y Huang

C -H Wu

J F Lin

C C Liu

C -L Yang

Jy Wu

S -J Wang
title: Flatband voltage tuning and EOT reduction for SiO2/HfO2/TiN gate stacks via lanthanum oxide capping layers using two different lanthanum precursors
venue: 68th Device Research Conference
year: 2010

abstract: The compatibility of HfO 2 gate dielectric films using polysilicon deposited under varying conditions as gate electrode has been systematically studied. Gate leakage current of capacitors was monitored as a metric for compatibility. Measurements after activation anneals show that for HfO 2 films, low temperature amorphous depositions show low leakage while with crystalline polySi depositions shorted capacitors resulted. For the HfO 2 films covered by a capping layer, the crystalline poly depositions show lower leakage than amorphous depositions. The high leakage with crystalline polysilicon electrodes is speculated as being due to the presence of weak spots or defects in the film which in the presence of a reducing ambient during polySi deposition become high leakage conduction paths. The presence of Si within the HfO 2 film detected by TOF SIMS supports this hypothesis.
author_names: Vidya Kaushik

S Degendt

Matty Caymax

E Young

Erika Rohr

Sven Van Elshocht

Annelies Delabie

Martine Claes

X Shi

Jerry Chen

Richard J Carter

T Canard

Wilfried Vandervorst

Marc Schaekers

Marc M Heyns
title: Compatibility of polysilicon with HFO2 BASED gate dielectrics for CMOS applications
year: 2003

abstract: Silicon doped hafnium oxide has been shown to exhibit ferroelectric properties under the certain small thicknesses with appropriate applied stress and annealing conditions. Utilizing Si:HfO2 as the dielectric with a TiN capping layer in a ferroelectric field effect transistor (FeFET) is promising as a potential emerging memory device due to the ease in integration with standard CMOS process flows. The process developed at RIT was successful in fabricating n channel FeFETs of varying dimensions. The work done here utilizes a 10 nm thick ALD Si:HfO2 film that has a remnant polarization of 10.34 mC/cm and an average memory window of 572.3 mV The subthreshold characteristics were consistent in both the on and off state with a calculated subthreshold swing around 110 mV/dec. Keywords Ferroelectric Memory, Hafnium Dioxide, FeFET.
author_names: Joe F Mcglone
title: Ferroelectric HfO2 Thin Films for FeFET Memory Devices
year: 2016

abstract: PBTI improvement in HfO2 nFETs achieved by a controlled insertion of La.Anomalous negative DVTH due to charge exchange between high k and metal gate.Anomalous and conventional PBTI components are decoupled and studied separately.Analytical model including both components for lifetime extrapolation is presented. Incorporation of rare earth capping layers in the gate stack is an effective technique to tune the threshold VTH voltage of advance CMOS technologies. Furthermore, a reduction of the positive VTH drift (instability) has been reported for rare earth doped nFETs under positive gate bias stress at high temperature. However, a non optimized process can lead to an anomalous VTH behavior. We demonstrate that two independent components are responsible for this anomalous behavior which can be decoupled, individually studied, and then projected for meaningful lifetime extrapolations.
author_names: Maria Toledano-Luque

Ben Kaczer

Marc Aoulaiche

Alessio Spessot

Philippe J Roussel

Romain Ritzenthaler

Tom Schram

Aaron Voon-Yew Thean

Guido Groeseneken
title: Analytical model for anomalous Positive Bias Temperature Instability in La based HfO2 nFETs based on independent characterization of charging components
year: 2013

abstract: In this paper, a low cost and low leakage gate first high k metal gate CMOS integration compatible with the high thermal budget used in a 2x node dynamic random access memory process flow is reported. The metal inserted polysilicon stack is based on HfO2 coupled with Al2O3 capping for pMOS devices, and with a TiN/Mg/TiN stack together with As ion implantation for nMOS. It is demonstrated that n and pMOS performance of 400 and 200 mA/mm can be obtained for an OFF state current of 10 10 A/mm, while maintaining gate and junction leakages compatible with low power applications. Reliability and matching properties are aligned with logic gate stacks, and the proposed solution is outperforming the La cap based solutions in terms of thermal stability.
author_names: Romain Ritzenthaler

Tom Schram

Alessio Spessot

Christian Caillat

Marc Aoulaiche

Moonju Cho

Kyoung Bong Noh

Y Son

H -J Na

Thomas Kauerauf

Bastien Douhard

Aftab Nazir

Soon Aik Chew

A Milenin

Efrain Altamirano-Sanchez

Geert Schoofs

Johan Albert

Farid Sebai

E Vecchio

V Paraschiv

Wilfried Vandervorst

Sun-Ghil Lee

Nadine Collaert

Pierre Fazan

Naoto Horiguchi

Aaron Voon-Yew Thean
title: A Low Power HKMG CMOS Platform Compatible With Dram Node 2x and Beyond
venue: IEEE Transactions on Electron Devices
year: 2014

abstract: Integration of high k interfacial layers in CMOS technology has been proposed to overcome the scaling limitations of the SiOx/HfO2 dielectric stack. Candidate high k interfacial layers have to be compatible with strict requirements in terms of EOT, inversion layer mobility, threshold voltage control and device reliability. We have previously demonstrated a CMOS compatible process for integration of thulium silicate (TmSiO) as interfacial layer, providing advantages in terms of EOT and channel mobility. This work demonstrates the compatibility of the TmSiO/HfO2 stack with the threshold voltage control techniques commonly employed in gate last and gate first integration schemes, namely the use of a dual metal process and the integration of dielectric capping layers. We show that the flatband voltage can be set from 1V to +0.5V by proper choice of gate metal, while a shift of 150 400 mV is achievable by means of integration of Al2O3 or La2O3 capping layers.
author_names: Eugenio Dentoni Litta

P -E Hellstrom

Mikael Ostling
title: Effective workfunction control in TmSiO/HfO2 high k/metal gate stacks
venue: 2014 15th International Conference on Ultimate Integration on Silicon (ULIS)
year: 2014

abstract: Wearable bio sensing devices are considered promising for ubiquitous heath monitoring. To accurately read out small bio signals, the development of high performance flexible front end circuits is crucial. Oxide semiconductors are considered one of the most promising active channel materials for on polymeric foil electronics. In this article, a high gain flexible complementary metal oxide semiconductor (CMOS) inverter with a beta ratio of 1, a desirable feature for device miniaturization, was demonstrated by monolithically integrating a top gated n type indium gallium zinc oxide (IGZO) thin film transistor (TFT) and a bottom gated p type SnO TFT on a 5.5 \mu \text{m} thick polyimide substrate. The influence of atomic layer deposited (ALD) HfO2 capping layer on the properties of oxide active channels has been analyzed. The flexible inverter exhibited a high static voltage gain of 370 V/V and balanced noise margins (noise margin high of 4.8 V, noise margin low of 4.7 V) for a supply voltage of 10 V. In addition, the voltage transfer characteristics remained virtually unchanged when the device was subjected to an outward or an inward bending radius of 2.5 mm, indicating the complementary oxide TFT based inverter is practical for flexible electronics applications.
author_names: Shu-Ming Hsu

Dung-Yue Su

Feng Yu Tsai

Jian-Zhang Chen

I-Chun Cheng
title: Flexible Complementary Oxide Thin Film Transistor Based Inverter With High Gain
venue: IEEE Transactions on Electron Devices
year: 2021