Search query: International Technology Roadmap of Semiconductors 2020

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abstract: The new Heterogeneous Integration Roadmap (HIR) provides a long term vision for the electronics industry, identifying difficult future challenges and potential solutions. Under the sponsorship of SEMI, ASME, and three IEEE Societies, the roadmap offers professionals, industry, academia, and research institutes a comprehensive view of the landscape and strategic technology requirements for the electronics industry's evolution over the next 15 years, and provides a 25 year vision for the heterogeneous integration of emerging devices and emerging materials with longer research and development timelines. The purpose is to stimulate precompetitive collaboration and thereby accelerate the pace of progress. The International Technology Roadmap for Semiconductors (ITRS) set the cadence for the Moore's Law scaling that has been the norm for the semiconductor industry. However, because of scaling, cost and power dissipation issues, as well as the laws of physics, the final ITRS was issued in 2015. The HIR pulls together many strands of that earlier Roadmap, to focus on microelectronics design, materials and packaging issues. The current version covers 2.5D, 3D, and wafer level packaging, integrated photonics, MEMS and sensors, and system in package (SiP) support areas such as test, thermal, simulation, co design, and interconnects; as well as application areas such as high performance computing, 5G, medical, aerospace, automotive, and mobile detailing both near term and longer term metrics and goals. It identifies difficult future challenges and proposes potential solutions. Comprising the output of 22 Technical Working Groups with worldwide participation, it will be substantially updated every two years. Version 1.0 is available freely for download, as well as in the form of a printed softbound book. Details for accessing this new Roadmap are presented. An invitation is made for involvement in version 2.0, now under preparation.
author_names: Paul B Wesling
title: The Heterogeneous Integration Roadmap: Enabling Technology for Systems of the Future
venue: 2020 Pan Pacific Microelectronics Symposium (Pan Pacific)
year: 2020

abstract: The international technology roadmap of semiconductors (ITRS) is approaching the historical end point and we observe that the semiconductor industry is driving complementary metal oxide semiconductor (CMOS) further towards unknown zones. Today's transistors with 3D structure and integrated advanced strain engineering differ radically from the original planar 2D ones due to the scaling down of the gate and source/drain regions according to Moore's law. This article presents a review of new architectures, simulation methods, and process technology for nano scale transistors on the approach to the end of ITRS technology. The discussions cover innovative methods, challenges and difficulties in device processing, as well as new metrology techniques that may appear in the near future.
author_names: Henry H Radamson

Huilong Zhu

Zhenhua Wu

Xiaobin He

Hongxiao Lin

Jinbiao Liu

Jinjuan Xiang

Zhenzhen Kong

Wenjuan Xiong

Junjie Li

Hushan Cui

Jian-feng Gao

Hong Yang

Yong Du

Buqing Xu

Ben Li

Xuewei Zhao

Jiahan Yu

Yan Dong

Guilei Wang
title: State of the Art and Future Perspectives in Advanced CMOS Technology
venue: Nanomaterials
year: 2020

abstract: Abstract Previous studies on open innovation have primarily adopted the perspective of single firms. Against this background we explore how open innovation is managed at the network level for the case of the International Technology Roadmap for Semiconductors (ITRS) Using a longitudinal case study, we report on how the ITRS deals with a technological discontinuity affecting the whole industry, namely the pursuit of an existing technological paradigm using a well established collaborative practice set against a novel and unknown future technological paradigm to be opened up in parallel, even though the necessary knowledge about the ensuing disruption is lacking. This challenge is characterized not only by extreme technological uncertainty, but also by partner related and procedural uncertainty concerning the key activity of ITRS, namely the setting of future technological milestones (roadmapping) We discuss attempts by the ITRS network to overcome these uncertainties and manage technological discontinuities by extending the well established practice of roadmapping to an unknown technological paradigm. We introduce the concept of 'stretching practice' to highlight this phenomenon, and we contribute to the debate on the open innovation and technological discontinuities that arise when venturing beyond firm centric approaches.
author_names: Jorg Sydow

Gordon Muller-Seitz
title: Open innovation at the interorganizational network level Stretching practices to face technological discontinuities in the semiconductor industry
venue: Technological Forecasting and Social Change
year: 2020

abstract: As Si based electronic devices rapidly reach their scaling limits, novel two dimensional (2D) semiconductors, such as graphene nanoribbon, transition metal dichalcogenides, phosphorene, are becoming promising channel materials. Antimonene has been proved suitable for ultra scaled field effect transistors (FETs) benefiting from its superior semiconducting properties. Considering that antimonene shows different effective mass from 0deg (zigzag) to 30deg (armchair) we have calculated the anisotropic transport property of monolayer (ML) antimonene metal oxide semiconductor FET (MOSFETs) including on state current, subthreshold swing, effective mass, intrinsic delay time and power dissipation. Encouragingly, 0deg (zigzag) and 19.1deg directions ML antimonene MOSFETs with 4 nm gate length and 1 nm underlap achieve International Technology Roadmap for Semiconductors (ITRS) high performance (HP) goal in 2028. The performance of ML antimonene MOSFETs still can fulfill the ITRS HP goal, when the spin orbit coupling effect is considered. The magnitude of on state currents in all calculations generally vary inversely with the effective mass. Therefore, we predict that other transmission directions with effective masses between 0.291 m0 to 0.388 m0 can also achieve ITRS HP goal, which enables antimonene to be a promising channel material.
author_names: Yiheng Yin

Chen Shao

Can Zhang

Zhaofu Zhang

Xuewei Zhang

John Robertson

Yuzheng Guo
title: The Anisotropic Transport Property of Antimonene MOSFETs.
venue: ACS applied materials interfaces
year: 2020

abstract: Exploring the device performance limits is meaningful for guiding practical device fabrication. We propose archetype tunneling field effect transistors (TFETs) with negative capacitance (NC) and use the rigorous ab initio quantum transport simulation to explore the device performance limits of the TFETs based on monolayer (ML) GeSe and GeTe along with their NC counterparts. With the ferroelectric dielectric acting as a negative capacitance material, the device performances of both the ML GeSe and GeTe NCTFETs outperform their TFET counterparts, particularly for the on state current (Ion) Ion of the optimal ML GeSe and GeTe TFETs fulfills the demands of the International Technology Roadmap for Semiconductors (ITRS 2015 version) for low power (LP) and high performance (HP) devices, at the "6/5" node range, while with the aid of 80 nm and 50 nm thickness of ferroelectric SrBi2Nb2O9, both their NC counterparts extend the fulfillments at the "4/3" node range.
author_names: Peipei Xu

Jiakun Liang

Hong Li

Fengbin Liu

Jun Tie

Zhiwei Jiao

Jingyao Luo

Jing Lu
title: Device performance limits and negative capacitance of monolayer GeSe and GeTe tunneling field effect transistors
year: 2020

abstract: Group III VI family MX (M Ga and In, and X S, Se, and Te) monolayers have attracted global interest for their potential applications in electronic devices due to their unexpectedly high carrier mobility. Herein, via density functional theory calculations as well as ab initio quantum transport simulations, we investigated the performance limits of MX monolayer metal oxide semiconductor field effect transistors (MOSFETs) at the sub 10 nm scale. Our results highlighted that the MX monolayers possessed good structural stability and mechanical isotropy with large ultimate strains and low Young's modulus, which are intensely anticipated in the next generation flexible devices. More importantly, the MX monolayer MOSFETs show excellent device performance under optimal schemes. The on state current, delay time, and power dissipation of the MX monolayer MOSFETs satisfy the International Technology Roadmap for Semiconductors (ITRS) 2013 requirements for high performance devices. Interestingly, the sub threshold swings were in a very low range from 68 mV dec 1 to 108 mV dec 1, which indicated the favorable gate control ability for fast switching. Therefore, we believe that our findings shed light on the design and application of MX monolayer based MOSFETs in next generation flexible electronic devices.
author_names: Jianhui Chen

Shuchang Cai

Rui Xiong

Baisheng Sa

Cuilian Wen

Bo Wu

Zhimei Sun
title: High performance III VI monolayer transistors for flexible devices.
venue: Physical chemistry chemical physics PCCP
year: 2020

abstract: With the scaling limits of silicon based MOS technology, the critical and challenging issue is to explore more and more alternative materials to improve the performance of devices. Two dimensional (2D) semiconductor WSe2 with proper bandgap and inherent stability under ambient conditions make it be the potential channel materials for realizing the new generation field effect transistors (FETs) In light of the low on state current of the experimental sub 10 nm 2D MoS2 FETs, we explore the limitation of the monolayer (ML) WSe2 device performance by using accurate ab initio quantum transport simulation. We find that the sub 10 nm 2D WSe2 FETs apparently outperform their MoS2 counterpart. The on state current of the optimized p type ML WSe2 FETs can satisfy the criteria of the International Technology Roadmap for Semiconductors (ITRS) on both the high performance (HP) and low power (LP) device until the gate length is scaled down to 2 and 3 nm, respectively. By the aid of the NC (negative capacitance) effect, even the 1 nm gate length WSe2 MOSFETs can satisfy both the HP and LP requirements in the ITRS 2028 completely. Remarkably, the ML WSe2 MOSFET owns the highest theoretical on current in the LP application among the examined 2D MOSFETs at the 5 nm gate length to our knowledge.
author_names: Xiaotian Sun

Li-wen Xu

Yuanwei Zhang

Weizhou Wang

Shiqi Liu

Chen Yang

Zhiyong Zhang

Jing Lu
title: Performance Limit of Monolayer WSe2 Transistors: Significantly Outperform their MoS2 Counterpart.
venue: ACS applied materials interfaces
year: 2020

abstract: Van der Waals (vdW) type metallic/semiconducting heterostructures have attracted much attention for applications like nanoelectronics. The electronic properties of graphene/SnSe2 vdW heterostructure are investigated by the first principles calculation. The band dispersions of both the graphene and SnSe2 layers are well preserved in the graphene/SnSe2 vdW heterostructure. Notably, n type Ohmic contact is found at the graphene/SnSe2 vdW interface so that graphene is a fantastic electrode for the SnSe2 Schottky barrier field effect transistor (SBFET) The on state current of the 10 nm gate long ML SnSe2 SBFET with graphene electrode is 1535 uA/um for high performance (HP) application, which is twice that of the ML MoS2 SBFET with bulk Ti electrode and exceeds the requirement of the International Technology Roadmap for Semiconductors for HP devices.
author_names: Hongjun Li

Peipei Xu

Jiakun Liang

Fengbin Liu

Jingyao Luo

Jing Lu
title: Ohmic contact in graphene/SnSe2 Van Der Waals heterostructures and its device performance from ab initio simulation
venue: Journal of Materials Science
year: 2020

abstract: ABSTRACT In this work, we utilized a digital integrated circuit (IC) testing model (DITM) based on a statistical simulation method, to evaluate the test yield and test quality of semiconductor products. A circuit or chip has multiple parameters and the relationships among these parameters at different levels are complicated. To simply express numerous and complex interrelated IC or chip manufacturing and testing parameters, we assumed a normal distribution of manufacturability and then standardized and related all other parameters. On applying the Digital integrated circuit testing model (DITM) to data on Accuracy Requirements in At Speed Functional Test and International technology roadmap for semiconductors (ITRS Roadmap) the simulated results clearly indicated that when the threshold value of a quality control test is determined, the DITM can accurately and effectively predict future Yt (Test Yield)
author_names: Chung-Huang Yeh

Jwu-E Chen
title: Test yield and quality analysis models of chips
year: 2020

abstract: Using ab initio quantum transport simulations, we studied the intrinsic transfer characteristics and benchmarks of the ballistic performance of 5.1 nm double gated Schottky barrier field effect transistors (SBFETs) consisting of in plane (IP) heterojunctions of metallic phase (1T or 1T' MTe2 (M Ti, Zr, Hf, Cr, Mo, W) and semiconducting phase (2H) WSe2, WTe2 and Janus WSeTe. The 2H phase Janus WSeTe is a semiconductor with an indirect bandgap (1.26 eV) which is less than the bandgap of 2H phase WSe2 (1.64 eV) and is greater than the bandgap of 2H phase WTe2 (1.02 eV) The band alignments show that all IP 1T/2H contacts are Schottky barrier contacts with the Fermi levels of 1T or 1T' MTe2 (M Ti, Zr, Hf, Cr, Mo, W) located within the bandgaps of 2H WSe2, WTe2 and Janus WSeTe. Although double gated IP WSe2 SBFETs can satisfy the OFF current requirement, their ON currents all fall below the requirements of the high performance transistor outlined by the ITRS (International Technology Roadmap for Semiconductors, 2013 version) for the production year 2028. Double gated IP WTe2 SBFETs cannot overcome the short channel effect leading to minimum drain currents all beyond the OFF current requirement of ITRS (2013 version) for the production year 2028. Fortunately, double gated IP WSeTe SBFETs with 1T MoTe2 or 1T' WTe2 electrodes can overcome the short channel effect and satisfy the requirements of the high performance transistor outlined by the ITRS (2013 version) for the production year 2028.
author_names: Z Q Fan

Zhen-Hua Zhang

Shenghui Yang
title: High performance 5.1 nm in plane Janus WSeTe Schottky barrier field effect transistors.
venue: Nanoscale
year: 2020