Search query: Tunnel field-effect transistor without gate-drain overlap

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abstract: Tunnel field effect transistors are promising successors of metal oxide semiconductor field effect transistors because of the absence of short channel effects and of a subthreshold slope limit. However, the tunnel devices are ambipolar and, depending on device material properties, they may have low on currents resulting in low switching speed. The authors have generalized the tunnel field effect transistor configuration by allowing a shorter gate structure. The proposed device is especially attractive for vertical nanowire based transistors. As illustrated with device simulations, the authors' more flexible configuration allows of the reduction of ambipolar behavior, the increase of switching speed, and the decrease of processing complexity.
author_names: Anne S Verhulst

William G Vandenberghe

Karen Maex

Guido Groeseneken
title: Tunnel field effect transistor without gate drain overlap
year: 2007

abstract: This paper investigates a method to suppress the ambipolar current I a m b effectively, enhance the device performance with higher on current I o n lower off current I o f f lower inverse subthreshold slope SS and simultaneously improve the RF performance. Starting with a conventional double gate TFET structure, the device optimization reported in this work has led to the gradual improvement in device performance in terms of higher I o n lower I o f f higher I o n I o f f ratio and lower SS The RF parameters of the optimized GOTFET, such as the mutual transconductance g m gate to drain C G D and gate to source C G S capacitances and unity gain cut off frequency f T are analyzed. We have optimized the tunnel FET device using the industry standard synopsys R \text {synopsys}\circledR TCAD tools by studying the impact of various device parameters and dimensions on performance. We demonstrated that at high negative voltages, the proposed nGOTFET would completely suppress the ambipolar behavior of the device without deteriorating the device performance. We have compared the ambipolar current I a m b I o f f I o n SS with 45 nm technology MOSFET and the TFETs reported earlier in literature. For the first time, we have proposed a GOTFET which completely suppresses the ambipolar current at high negative biases, without compromising the high I o n (1.04 mA/ m m) and low I o f f (0.27 pA/ m m) and low SS (32 mV/dec) at room temperature.
author_names: Ramakant Yadav

Surya Shankar Dan

Sanjay Vidhyadharan

Simhadri Hariprasad
title: Suppression of Ambipolar Behavior and Simultaneous Improvement in RF Performance of Gate Overlap Tunnel Field Effect Transistor (GOTFET) Devices
venue: Silicon
year: 2020

abstract: To improve the ambipolar behavior, Dielectric Pocket (DP) is incorporated in the Double Gate Tunnel Field Effect Transistor (DGTFET) The DP plays a key role in the ambipolar conduction of TFET. The proposed device Dielectric Pocket DGTFET (DP DGTFET) has been demonstrated using a 2D TCAD simulator. The DP length and thickness are optimized to increase the minimum tunneling width near the channel drain junction, which indeed reduces the ambipolar conduction of the device without affecting the ON state current, subthreshold swing, and the output characteristics. Moreover, using a high k material instead of low k as a dielectric pocket, enhance the device performance in terms of ambipolar behavior. Additionally, the analog performance of the proposed device was also investigated. It is observed that the presence of DP enhances the device performance by reducing the gate to drain capacitance (Cgd) whereas, the presence of gate to drain overlap has a negative impact (increases Cgd) on the proposed device. It is demonstrated that the gate on drain overlap along with the DP in DGTFET enhances the DC performance of the device by reducing the ambipolar current.
author_names: Radhe Gobinda Debnath

Srimanta Baishya
title: Impact of Dielectric Pocket on the Performance of Double Gate TFET
venue: 2020 IEEE Calcutta Conference (CALCON)
year: 2020

abstract: Abstract In this work, a hetero junction fully depleted (FD) Silicon on Insulator (SOI) Tunnel Field Effect Transistor (TFET) nanostructure with oxide overlap on the Germanium source region is proposed. Investigations using Synopsys Technology Computer Aided Design (TCAD) simulation tools reveal that the simple oxide overlap on the Germanium source region increases the tunneling area as well as the tunneling current without degrading the band to band tunneling (BTBT) and improves the device performance. More importantly, the improvement is independent of gate overlap. Simulation study shows improvement in ON current, subthreshold swing (SS) OFF current, I ON I OFF ration, threshold voltage and transconductance. The proposed device with hafnium oxide (HfO 2 /Aluminium Nitride (AlN) stack dielectric material offers an average subthreshold swing of 22 mV/decade and high I ON I OFF ratio ~10 10 at V DS 0.4 V. Compared to conventional TFET, the Miller capacitance of the device shows the enhanced performance. The impact of the drain voltage variation on different parameters such as threshold voltage, subthreshold swing, transconductance, and I ON I OFF ration are also found to be satisfactory. From fabrication point of view also it is easy to utilize the existing CMOS process flows to fabricate the proposed device.
author_names: Sweta Chander

Brinda Bhowmick

Srimanta Baishya
title: Heterojunction fully depleted SOI TFET with oxide/source overlap
year: 2015

abstract: In this paper, we propose and simulate a novel double gate tunnel field effect transistor (DG TFET) employing a metallic drain and a gate drain underlap. The use of a metallic drain and an underlap results in complete ambipolar suppression in the proposed TFET. A 2D calibrated simulation studies have revealed that ambipolar current suppression of 5 orders, without affecting the on state current of the device, when the gate voltage is varied between 1 V and 1 V, is achieved in the proposed device in comparison to the conventional DG TFET. The complete ambipolar reduction is attributed to the reduced band to band tunneling (BTBT) rate because of the Schottky barrier formation at the channel/drain interface. Further, the use of gate/drain underlap suppresses the ambipolarity completely in the proposed device in comparison to the conventional one. An ON current (I ON and OFF current (I OFF ratio (I ON /I OFF of 10 12 with a subthreshold slope (SS) of 63 mV/decade is achieved in the proposed device. Further, the effect of change of various parameters on the performance of the proposed device has been thoroughly studied. It has been observed that the performance can be optimized further by using the optimum value of these parameters. A process flow for the fabrication of the proposed device has also been given
author_names: Anam Khan

Sajad A Loan
title: Metal Drain Double Gate Tunnel Field Effect Transistor with Underlap: Design and Simulation
venue: Silicon
year: 2020

abstract: In this research, we investigate the ambipolar current in germanene nanoribbon tunneling field effect transistor (GeNRTFET) using combination of density functional theory (DFT) and non equilibrium Green's function method (NEGF) We propose two different methods to reduce the ambipolar current in the GeNR TFET: using overlapped gate metal to cover part of the drain side and the other idea is to decrease the doping density in the drain side. The results show that by extension of the metal gate on the drain region, the hole current from the drain to channel reduces and it is possible to reduce this current more by using longer overlapping length. Also, results prove that by decreasing the doping density in the drain side compared with the source region, the ambipolar current declines. We obtain that by mixing two proposed ways, the ambipolar current can significantly be reduced. Suppression of this ambipolar current is an important challenge in digital circuit design.
author_names: Amir Hossein Bayani

Daryoosh Dideban

Negin Moezi
title: Reducing Ambipolar Current in Germanene Nanoribbon Tunneling Field Effect Transistor (GeNR TFET) using Gate Drain Overlap and Decreasing Doping Density in the Drain Side
year: 2020

abstract: Effects of the spacer drain overlap on the performance parameters of the double gate tunnel field effect transistor is proposed and investigated in this paper. By proper fabrication of the spacer drain overlap, we can obtain a lower sub threshold swing, smaller short channel effect (SCEs) i.e. drain induced barrier lowering (DIBL) higher ON state current (ION) and considerably less OFF state current (IOFF) Here we also measure effects of the channel length variation of the device. In this paper, we compare the proposed device with single gate tunnel FET with spacer drain overlap using vertical tunneling concept. So we can observed, that the proposed device gives better performance parameters.
author_names: Sapna Singh

Sudakar Singh Chauhan
title: TCAD simulations of double gate tunnel field effect transistor with spacer drain overlap base on vertical Tunneling
venue: 2017 International conference of Electronics, Communication and Aerospace Technology (ICECA)
year: 2017

abstract: We present a two dimensional (2 D) analytical modeling of the surface potential of a double gate vertical t shaped tunnel field effect transistor (TFET) considering the inherit dual modulation effect in such devices. This effect explains the control of the surface potential by both bias voltages, which are used to calculate the tunneling depletion width at the source and drain junctions. A model of the tunneling current in the device is derived based on the surface potential model. The parabolic approximation is used to solve the 2 D Poisson equation with appropriate boundary conditions. The dependence of the surface potential profile on different parameters is analyzed by varying the gate source potential, drain source potential, gate oxide dielectric constant, gate metal work function, and different materials used. Finally, expressions for the surface potential of the channel along with the tunneling current are obtained, accurately capturing their variation with the gate and drain biases. The proposed method is verified by the agreement between its analytical results and technology computer aided design (TCAD) simulation results.
author_names: Shailendra Singh

Balwinder Raj
title: Two dimensional analytical modeling of the surface potential and drain current of a double gate vertical t shaped tunnel field effect transistor
year: 2020

abstract: Purpose: A TFET (Tunnel Field Effect Transistor) is a potential candidate to replace CMOS in deep submicron region due to its lower SS (subthreshold swing, <60 mV/decade) at room temperature. However, the conventional TFET suffers from low tunneling current and high ambipolar current. To overcome these two drawbacks a new structure, known as Hetero dielectric gate TFET (HDG TFET) has been proposed in the literature. Method: To analyze the electrical characteristics of this structure, a closed form of analytical expression of current is required. This paper presents the closed form of compact analytical current model for HDG TFET structure without using any iterative method. Result: The developed compact analytical models show a good agreement with 2 D TCAD simulator results. The model is used to study in depth about the electrical behavior of the device under various physical variation as well as bias variation. Conclusion: The proposed model can be incorporated into SPICE to describe the behavior of HDG TFET faster.
author_names: Tan Chun Fui

Lim Way Soong
title: Drain Current Model for a Single Gate Tunnel Field Effect Transistor with Hetero Dielectric Gate (HDG)
year: 2021

abstract: This paper proposes a tunnel field effect transistor (TFET) with an additional field plate over the drain region in the device. Using 2 D device simulations, it is shown that, by introducing a field plate with an appropriate work function, placed on the top of the drain region, the ambipolar current of the device can be effectively suppressed. Furthermore, it is demonstrated that when a field plate is placed at an appropriate height on the drain region, the gate to drain capacitance of the device does not increase significantly. Using simulations, it is shown that, compared to the gate on drain overlap technique, the proposed technique results in a substantial decrease in the gate to drain capacitance. Consequently, the fan out of four (FO4) inverter delay is 22% smaller in the circuit realized using the proposed device compared to the circuit realized using TFETs having gate on drain overlap.
author_names: Subhadip Poria

Shelly Garg

Sneh Saurabh
title: Suppression of Ambipolar current in Tunnel Field Effect Transistor using Field Plate
venue: 2020 24th International Symposium on VLSI Design and Test (VDAT)
year: 2020