Search query: SET/CMOS universal literal gate-based Analog-to-Digital converter.

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abstract: In this paper, we propose an analog to digital converter (ADC) using a hybrid single electron transistor/complementary metal oxide semiconductor (SET/CMOS) universal literal gate based on the Coulomb oscillation phenomenon of a SET. The SET/CMOS universal literal gate consists of the SET/resistor inverter and the CMOS inverter, whose input is connected to the output of SET/resistor inverter. Because the CMOS inverter has the high input impedance and the low output impedance, the proposed circuit makes it possible to overcome the disadvantage of the high output impedance of a SET/resistor inverter by connecting its output to any input of CMOS circuit. The circuit has shown high immunity on temperature and can eliminate the background charge effect as applied to ADC. Using SPICE macromodel of SET at 30 K, we demonstrated the performance of a 4 bit ADC, composed of SET/CMOS universal literal gate and capacitive divider. These results can be simply extended to multi bit ADC.
author_names: Myung-Jo Chun

Yoon-Ha Jeong
title: SET/CMOS universal literal gate based analog to digital converter
venue: 2003 Third IEEE Conference on Nanotechnology, 2003. IEEE NANO 2003.
year: 2003

abstract: We propose a novel analog/digital (A/D) converter based on single electron transistors (SETs) in this paper. In the proposed A/D converter, the core cell is a SET module, composed of capacitive dividers and SET based universal literal gates. The SET based universal literal gate is similar to the well known Tucker's inverter (J.R. Tucker, J. Appl. Phys. vol. 72, no. 9, pp. 4399 4413, 1992) but here it acts as digital conversion and the inputs of upper SET and lower SET are two opposite voltages. In the SET based universal literal gate, by adjusting the some parameters, the output having about 50% duty ratio of square wave like and zero output for zero input (in contrast, high voltage output for zero input in Tucker's inverter) is obtained, where we fully utilize the periodic oscillation of SETs on gate voltage /spl I.bar/V/sub G/=e/C/sub G/ We demonstrate the basic function of a 4 bit SET based A/D converter using the MOSES program developed by K.K. Likharev's group, which is based on the so called orthodox theory and Monte Carlo method. The results may be easily extended to higher bit A/D converters.
author_names: Chaohong Hu

J F Jiang

Q Y Cai
title: A single electron transistor based analog/digital converter
venue: Proceedings of the 2nd IEEE Conference on Nanotechnology
year: 2002

abstract: Analog circuits and systems research and education can benefit from the flexibility provided by large scale Field Programmable Analog Arrays (FPAAs) This demonstration will present visitors with the hardware and software infrastructure supporting the use of a family of floating gate based FPAAs being developed at Georgia Tech [1] A picture of the programming and control hardware that will be demonstrated is found in Figure la. Figure lb shows the software flow that will be demonstrated [2] The infrastructure is compact and portable and provides the user with a comprehensive set of tools for custom analog circuit design and implementation. The infrastructure includes the FPAA integrated circuit (IC) discrete analog to digital converters (ADC) digital to analog converters (DAC) and amplifier ICs; a 32 Bit ARM based microcontroller (mC) for interfacing the FPAA with a laptop computer; and Matlab and targeting software. The FPAA hardware communicates with Matlab over a Universal Serial Bus (USB) connection. The USB connection also provides the hardware's power. The software tools in the demonstration include three major systems: a Matlab Simulink FPAA program, a SPICE to FPAA compiler called GRASPER, and a visualization tool called RAT. Figure 2 shows a block diagram of the Programming and Control board and demonstration setup.
author_names: Scott Koziol

Craig Schlottmann

Arindam Basu

Stephen Brink

Csaba Petre

Brian P Degnan

Shubha Ramakrishnan

Paul E Hasler

Aurele Balavoine
title: Live demonstration: Hardware and software infrastructure for a family of floating gate based FPAAs
venue: Proceedings of 2010 IEEE International Symposium on Circuits and Systems
year: 2010

abstract: A new digital quantizer structure is proposed based on single electron box (SEB) The structure exploits SEB which constitutes the simplest single electron device with one capacitor and one tunnel junction. Specifically, the quantizer is composed of two SEB's and one differential amplifier. Since the order of tunnel junction and capacitor determines the output characteristics in the single electron box, the quantized signal is achieved by adjusting the value of capacitance. The usefulness of digital quantizer is demonstrated by implementing the 4 bit analog to digital converter (ADC) The ADC consists of the proposed quantizer block, capacitive divider and universal literal gate. The result shows almost no delay and good performance. The ADC with proposed digital quantizer docs not require latching blocks, rendering thereby the entire circuit much simpler. All the simulations have been performed with Monte Carlo based simulator called SIMON.
author_names: Sung-Woo Jung

Bong-Hoon Lee

Yoon-Ha Jeong
title: Digital quantizer based on single electron box for multi valued logic circuits
venue: 5th IEEE Conference on Nanotechnology, 2005.
year: 2005

abstract: Digital pulse processing has developed rapidly during recent years. Moreover, it has been widely applied in many fields. In this study, we introduce a digital pulse processing method for 2pa and 2pb emitter measurement. Our digital pulse processing method for 2pa and 2pb emitter measurement is comprised of a field programmable gate array based acquisition card and a pulse height analysis routine. We established two channels (one for the a emitter and one for the b emitter) on an acquisition board using an analog to digital converter with a 16 bit resolution at a speed of 100 million samples per second. In this study, we used captured and stored data to analyze emission rate counts and spectrums. The method we established takes into account noise cancelation, dead time correction, background subtraction, and zero energy extrapolation. We carefully designed control procedures in order to simplify pulse width fitting and threshold level setting. We transmitted data and commands through a universal serial bus between the acquisition board and the computer. The results of our tests prove that our method performs well in pulse reconstruction fidelity and amplitude measurement accuracy. Compared with the current standard method for measuring 2pa and 2pb emission rates, our system demonstrates excellent precision in emission rate counting.
author_names: Zheng Tu

Ke-Zhu Song

Ming Zhang

Zhi-Jie Yang

Zhi-Guo Ding

Hongyan Yu

Juncheng Liang

Haoran Liu
title: A new digital pulse processing method for 2pa and 2pb emitter measurement
year: 2016

abstract: The invention discloses an FPGA (Field Programmable Gate Array) based high speed data acquisition system comprising a differential amplification unit for receiving a simulation signal, an A/D (Analog/Digital) conversion unit connected with the differential amplification unit, an FPGA processing unit connected with the A/D conversion unit and a microprocessor connected with the FPGA processing unit, wherein the microprocessor is connected with an upper computer through a communication interface. The FPGA based high speed data acquisition system disclosed by the invention has the characteristics of high sampling speed, high precision, high storage capacity, high uploading speed, and the like; parallel alternating real time sampling is used as a sampling mode; two A/D converters with the sampling speed of 125MSPS (Multiphase Serial Parallel Serial Storage) are adopted to sample one path of signal in an alternating and parallel way and realize the sampling speed of 250MSPS; and the sampling precision can reach 12bits and sampling points are 1 25K. The FPGA based high speed data acquisition system has a hardware cumulative function, the cumulative frequency of 1 250K and the bandwidth of 200MHz and supports USB (Universal Serial Bus) 2.0 full speed communication; the input range of signals is 2Vp p; and the FPGA based high speed data acquisition system can be widely applied to the fields of acquisition of multi path signals having higher requirement on the speed, the precision and the storage capacity of data acquisition.
title: FPGA (Field Programmable Gate Array) based high speed data acquisition system
year: 2010

abstract: This paper presents a digital signal processing system specially designed for eddy currents non destructive testing. This new system has a field programmable gate array based processing core, communication interfaces, data conversion and analog devices to interface the probes. Communication with personal computers is ensured by Ethernet 10/100 and universal serial bus 2.0 high speed interfaces. The proposed architecture enables to set several combinations of peripherals cards to generate or acquire probe signals. Also, the new system allows the digital generation and analysis of the probe signals through multiple digital signal processing algorithms. Two different peripheral cards have been developed to meet the needs for the new IOnic concept of eddy currents probe. The IOnic acquisition card is composed by a programmable gain amplifier and a high speed analog to digital converter. The current stimulus generation is achieved with a digital to analog converter and a high output current transconductance amplifier. Together, the two peripherals are able to operate the probe from 10 kHz up to 10 MHz. An additional peripheral card to interface stepper motors was designed for sensor positioning.
author_names: Luis Filipe Soldado Granadeiro Rosado

Moises Simoes Piedade

Pedro M Ramos

Telmo G Santos

Pedro Vilaca
title: A reconfigurable digital signal processing system for eddy currents non destructive testing
venue: 2010 IEEE Instrumentation Measurement Technology Conference Proceedings
year: 2010

abstract: Devices that combine single electron and metal oxide semiconductor (MOS) transistors are newly proposed as basic components of multiple valued (MV) logic, such as a universal literal gate and a quantizer. We verified their operation using single electron and MOS transistors fabricated on the same wafer by pattern dependent oxidation of silicon. We also discuss their application to an analog to digital converter, a MV adder, and MV static random access memory.
author_names: Hiroshi Inokawa

Akira Fujiwara

Yasuo Takahashi
title: A multiple valued logic and memory with combined single electron and metal oxide semiconductor transistors
year: 2003

abstract: This paper proposes smart universal multiple valued (MV) logic gates by transferring single electrons (SEs) The logic gates are based on mosfet based SE turnstiles that can accurately transfer SEs with high speed at high temperature. The number of electrons transferred per cycle by the SE turnstile is a quantized function of its gate voltage, and this characteristic is fully exploited to compactly finish MV logic operations. First, we build arbitrary MV literal gates by using pairs of SE turnstiles. Then, we propose universal MV logic to value conversion gates and MV analog digital conversion circuits. We propose a SPICE model to describe the behavior of the mosfet based SE turnstile. We simulate the performances of the proposed gates. The MV logic gates have small number of transistors and low power dissipations.
author_names: Wancheng Zhang

Nan-Jian Wu
title: Smart Universal Multiple Valued Logic Gates by Transferring Single Electrons
venue: IEEE Transactions on Nanotechnology
year: 2008

abstract: Proposes merged single electron and MOS devices that serve as basic components of multiple valued logic, such as a universal literal gate and a quantizer. We verified their operation by using single electron transistors and MOSFETs fabricated on the same wafer by pattern dependent oxidation process. We also discuss their application to an analog to digital converter and a multiple valued adder.
author_names: Hiroshi Inokawa

Akira Fujiwara

Y Takahashi
title: A multiple valued logic with merged single electron and MOS transistors
venue: International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)
year: 2001