Search query: Nanoscale Memristor Device as Synapse in Neuromorphic Systems

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abstract: A memristor is a two terminal electronic device whose conductance can be precisely modulated by charge or flux through it. Here we experimentally demonstrate a nanoscale silicon based memristor device and show that a hybrid system composed of complementary metal oxide semiconductor neurons and memristor synapses can support important synaptic functions such as spike timing dependent plasticity. Using memristors as synapses in neuromorphic circuits can potentially offer both high connectivity and high density required for efficient computing.
author_names: Sung-Hyun Jo

Ting Chang

Idongesit E Ebong

Bhavitavya Bhadviya

Pinaki Mazumder

Wei Yang Lu
title: Nanoscale memristor device as synapse in neuromorphic systems.
venue: Nano letters
year: 2010

abstract: Neuromorphic systems consist of a framework of spiking neurons interconnected via plastic synaptic junctures. The discovery of a two terminal passive nanoscale memristive device has spurred great interest in the realization of memristive plastic synapses in neural networks. In this work, a synapse structure is presented that utilizes a pair of memristors, to implement both positive and negative weights. The working scheme of this synapse as an electrical interlink between neurons is explained, and the relative timing of their spiking events is analyzed, which leads to a modulation of the synaptic weight in accordance with the spike timing dependent plasticity (STDP) rule. A digital pulse width modulation technique is proposed to achieve these variable changes to the synaptic weight. The synapse architecture presented is shown to have high accuracy when used in neural networks for classification tasks. Lastly, the energy requirement of the system during various phases of operation is presented.
author_names: Md Musabbir Adnan

Sagarvarma Sayyaparaju

Garrett S Rose

Catherine D Schuman

Bon Woong Ku

Sung Kyu Lim
title: A Twin Memristor Synapse for Spike Timing Dependent Learning in Neuromorphic Systems
venue: 2018 31st IEEE International System on Chip Conference (SOCC)
year: 2018

abstract: This paper is a review paper of a promising study towards the creation of artificial synaptic networks using memristor based synapse devices and other promising research in the field of neuromorphic circuit development. In 2010, Lu et. al utilized Ag/Si memristors incorporated into crossbar synapse networks with CMOS based pre and post synaptic neurons to effectively demonstrate that changes in both pulse height and width from CMOS neurons caused corresponding changes in memductance of memristor synapse. This proved the memristor neuromorphic circuit exhibited behavior analogous to spike timing dependant plasticity, a process which governs strength of interconnects between neurons and vital to learning and memory processes. In this paper we will present overview of the memristor device, and its applications to mimic the neurological processing.
author_names: Nathan Serafino

Mona E Zaghloul
title: Review of nanoscale memristor devices as synapses in neuromorphic systems
venue: 2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS)
year: 2013

abstract: The memristive device is a nanoscale nonlinear passive two terminal fourth fundamental circuit element in addition to the three previously known passive fundamental circuit elements namely resistor, capacitor, and inductor. However aside from its non volatile memory nature, this memristor resistance/ memristance controlled in the circuit operation by the amount of charge applied between its terminals. The memristor device SPICE modeling is significant for memristive circuit and neuromorphic system design. Nowadays probabilistic switching behavior observed in many fabricated memristor devices that inspired stochastic learning rule for memristor based neuromorphic learning system application. In this paper, a stochastic metastable switch memristor model (MSSs) is used for binary weighted memristor based artificial synapse circuitry presentation. Using this MSSs memristor SPICE model a binary weighted memristor based artificial synapse circuit presented. The presented circuit shows a binary response to the signal given to the memristor implemented in the binary synaptic circuit using a stochastic memristor device model. The authors left the implementation of the proposed binary synaptic circuit in a memristor based artificial neural network that functions through the clipped perceptron (CP) learning algorithm as future work.
author_names: Melaku Nigus

Rashmi Priyadarshini

Rakesh Mehra
title: Binary Weighted Synaptic Circuit for Neuromorphic Learning System Using Stochastic Memristor SPICE Model
venue: 2019 International Conference on Computing, Communication, and Intelligent Systems (ICCCIS)
year: 2019

abstract: The ability to vary the conductance of a valence change memristor in a continuous manner makes it a prime choice as an artificial synapse in neuromorphic systems. Because synapses are the most numerous components in the brain, exceeding the neurons by several orders of magnitude, the scalability of artificial synapses is crucial to the development of large scale neuromorphic systems but is an issue which is seldom investigated. Leveraging on the conductive atomic force microscopy method, we found that the conductance switching of nanoscale memristors ~25 nm2) is abrupt in a majority of the cases examined. This behavior is contrary to the analoglike conductance modulation or plasticity typically observed in larger area memristors. The result therefore implies that plasticity may be lost when the device dimension is scaled down. The contributing factor behind the plasticity behavior of a large area memristor was investigated by current mapping, and may be ascribed to the disruption of the plurality of conductive filaments happening at different voltages, thus yielding an apparent continuous change in conductance with voltage. The loss of plasticity in scaled memristors may pose a serious constraint to the development of large scale neuromorphic systems.
author_names: Diing Shenp Ang

Y Zhou

Kwang Sing Yew

Dan Berco
title: On the area scalability of valence change memristors for neuromorphic computing
venue: Applied Physics Letters
year: 2019

abstract: Neuromorphic computing brainlike computing in hardware typically requires myriad CMOS spiking neurons interconnected by a dense mesh of nanoscale plastic synapses. Memristors are frequently cited as strong synapse candidates due to their statefulness and potential for low power implementations. To date, plentiful research has focused on the bipolar memristor synapse, which is capable of incremental weight alterations and can provide adaptive self organisation under a Hebbian learning scheme. In this paper we consider the Unipolar memristor synapse a device capable of switching between only two states (conductive and resistive) through application of a suitable input voltage and discuss its suitability for neuromorphic systems. A self adaptive evolutionary process is used to autonomously find highly fit network configurations. Experimentation on a dynamic reward scenario shows that unipolar memristor networks evolve task solving controllers faster than both generic bipolar memristor networks and networks containing nonplastic connections whilst performing comparably.
author_names: Gerard David Howard

Larry Bull

Ben de Lacy Costello
title: Evolving Unipolar Memristor Spiking Neural Networks
venue: ACALCI
year: 2015

abstract: Neuromorphic computing brain like computing in hardware typically requires myriad complimentary metal oxide semiconductor spiking neurons interconnected by a dense mesh of nanoscale plastic synapses. Memristors are frequently cited as strong synapse candidates due to their statefulness and potential for low power implementations. To date, plentiful research has focused on the bipolar memristor synapse, which is capable of incremental weight alterations and can provide adaptive self organisation under a Hebbian learning scheme. In this paper, we consider the unipolar memristor synapse a device capable of non Hebbian switching between only two states (conductive and resistive) through application of a suitable input voltage and discuss its suitability for neuromorphic systems. A self adaptive evolutionary process is used to autonomously find highly fit network configurations. Experimentation on two robotics tasks shows that unipolar memristor networks evolve task solving controllers faster than both bipolar memristor networks and networks containing constant non plastic connections whilst performing at least comparably.
author_names: Gerard David Howard

Larry Bull

Ben de Lacy Costello
title: Evolving unipolar memristor spiking neural networks
venue: Connect. Sci.
year: 2015

abstract: Modeling and related characterization of memristive neurodynamic systems becomes a critical pathway towards neuromorphic system designs. This paper presents a general class of memristive neural networks with time varying delays. Some improved algebraic criteria for global exponential stability of memristive neural networks are obtained. The criteria improve some previous results and are easy to be verified with the physical parameters of system itself. The proposed framework for theoretical analysis of memristive neurodynamic systems may be useful in developing nanoscale memristor device as synapse in neuromorphic computing architectures.
author_names: Ailong Wu

Zhigang Zeng
title: Improved conditions for global exponential stability of a general class of memristive neural networks
venue: Commun. Nonlinear Sci. Numer. Simul.
year: 2015

abstract: Memristors are nanoscale devices that have recently been proposed for use as a synapse in brain inspired computing systems. In this paper, we present a synapse architecture that utilizes two memristors to implement a non volatile synaptic weight that can be configured as both positive and negative. The weight of the proposed synapse has an inherent exponential like dependence on the change in the memristance of the devices, a property that we have capitalized to implement spike timing dependent plasticity (STDP) for on chip learning in spiking neural networks. We discretize the neuron's spike in time and voltage and show that learning rate can be controlled by the clock frequency used. We show that by modulating the duty cycle of the clock, we can alleviate the detrimental effects of switching rate mismatch in the devices. We also simulated a 3 x 3 crossbar structure and presented the weight updates observed therein, hence demonstrating the feasibility of a crossbar with our synapse. We evaluated the energy consumption per spike of our approach and compared it with those in literature.
author_names: Sagarvarma Sayyaparaju

Sherif Amer

Garrett S Rose
title: A bi memristor synapse with spike timing dependent plasticity for on chip learning in memristive neuromorphic systems
venue: 2018 19th International Symposium on Quality Electronic Design (ISQED)
year: 2018

abstract: Abstract The nanoscale memristor device SPICE modeling is significant for memristive circuits and neuromorphic system design applications. In this paper, a novel modified piece wise linear (PWL) window function proposed for the nonlinear property of the memristor SPICE model. The PWL window function used here can address the shortcoming of the parabola and Heaviside step function based typical window functions proposed in the literature, those are established by symmetrical functions. However, in most of the typical window functions, the monotonically increasing and the asymmetrical functions have not been addressed. Also, using this PWL window function based memristor model, a binary weighted memristor based artificial synaptic circuit has been designed. The performance of the device model demonstrated by the efficiency of designed artificial synapse sensitivity to the external input signal.
author_names: Melaku Nigus Getachew

Rashmi Priyadarshini

R M Mehra
title: SPICE model of HP memristor using PWL window function for neuromorphic system design application
year: 2020