Search query: Applying machine learning to semiconductor manufacturing

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abstract: The generalized ID3 (GID3) algorithm, which takes a training set of experimental data and produces a decision tree that predicts the outcome of future experiments under various, more general conditions, is described. The tree can then be translated into a set of rules for an expert system. Two extensions to GID3MmRIST, and KARSM that deal with the problems of noisy data and the limited availability of training data are discussed. The application of GID3 to reactive ion etching manufacturing process diagnosis and optimization and to knowledge acquisition for an expert system is described.<ETX>
author_names: Keki B Irani

Jie Cheng

Usama M Fayyad

Zhaogang Qian
title: Applying machine learning to semiconductor manufacturing
venue: IEEE Expert
year: 1993

abstract: Raw material quality control is one of the most important missions in the foundry manufacturing process. Therefore, how to effectively detect abnormality at the early stage of raw material incoming or even at supplier ends has become a challenging topic. Currently, most semiconductor manufacturing FABs use COA (Certificate of Assurance) as the accepted criteria for raw material suppliers, however raw materials with accepted COA still perform differently after hundreds of manufacturing processes.
author_names: Chien-Hui Leu

Demeter Chen
title: Applying Machine Learning for COA data analytics of raw materials on Semiconductor Manufacturing
venue: 2018 International Symposium on Semiconductor Manufacturing (ISSM)
year: 2018

abstract: A learning based scheduling framework for semiconductor manufacturing system is studied in this paper. This framework obtains a dynamic scheduling model by applying machine learning algorithm based on optimal data samples, through which an approximate optimal scheduling strategy under a certain production state can be acquired on time. And then an implementation of a dynamic scheduling model based on extreme learning machine (ELM) is proposed. In order to improve efficiency, a hybrid feature selection and classification algorithm is suggested, which combines filter feature selection method and wrapper feature selection method. Finally, the proposed dynamic scheduling model is tested in a real semiconductor manufacturing system to compare and analysis between the algorithm performance and production performance. The result indicates that the learning based scheduling method is superior to single scheduling rules and it also meets the requirements of real time manufacturing scheduling.
author_names: Yumin Ma

Fei Qiao

Jianfeng Lu
title: Learning based dynamic scheduling of semiconductor manufacturing system
venue: 2016 IEEE International Conference on Automation Science and Engineering (CASE)
year: 2016

abstract: While semiconductor manufacturing is moving towards the 14nm node using immersion lithography, the overlay requirements are tightened to below 5nm. Next to improvements in the immersion scanner platform, enhancements in the overlay optimization and process control are needed to enable these low overlay numbers. Whereas conventional overlay control methods address wafer and lot variation autonomously with wafer pre exposure alignment metrology and post exposure overlay metrology, we see a need to reduce these variations by correlating more of the TWINSCAN system's sensor data directly to the post exposure YieldStar metrology in time. In this paper we will present the results of a study on applying a real time control algorithm based on machine learning technology. Machine learning methods use context and TWINSCAN system sensor data paired with post exposure YieldStar metrology to recognize generic behavior and train the control system to anticipate on this generic behavior. Specific for this study, the data concerns immersion scanner context, sensor data and on wafer measured overlay data. By making the link between the scanner data and the wafer data we are able to establish a real time relationship. The result is an inline controller that accounts for small changes in scanner hardware performance in time while picking up subtle lot to lot and wafer to wafer deviations introduced by wafer processing.
author_names: Emil Schmitt-Weaver

Michael Kubis

Wolfgang Henke

Daan Slotboom

Tomoko Hoogenboom

Jan Mulkens

Martyn Coogans

Peter ten Berge

Dick Verkleij

Frank van de Mast
title: Overlay improvements using a real time machine learning algorithm
venue: Advanced Lithography
year: 2014

abstract: In the semiconductor manufacturing industry, Automatic Defect Classification (ADC) plays an important role in maintaining high wafer inspection quality and reducing yield loss. ADC performance has benefitted from using machine learning (ML) algorithms; however, performance is negatively affected by the data imbalance and limited amounts of training data. Synthetic Minority Oversampling Technique (SMOTE) is an oversampling technique to adjust the skewed class distribution of a dataset so that the bias of the majority class is reduced. This paper shows that applying SMOTE achieved higher accuracy and purity on two imbalanced datasets, consisting of scanning electron microscopy (SEM) images collected with ASML HMI eP(tm) and eScan(r) series inspection tools. The ML models are also less sensitive to the selection of hyperparameters when SMOTE is applied. We also show that better classification results can be obtained with less training samples with SMOTE; we conducted an experiment where a ML model trained on only 25% of samples with SMOTE achieved a higher ADC accuracy and purity performance compared to the same ML model trained on all samples but without SMOTE. In another experiment using a highly imbalanced SEM dataset with very few counts of the defect of interest (DOI) the combination of SMOTE and random undersampling of the majority class improves the accuracy by up to 5x while maintaining the same level of purity.
author_names: Po-Hsuan Lee

Zhe Wang

Cho-Huak Teh

Yi-Sing Hsiao

Wei Fang
title: Automated semiconductor wafer defect classification dealing with imbalanced data
venue: Advanced Lithography
year: 2020

abstract: Wafer defect detection using an intelligent system is an approach of quality improvement in semiconductor manufacturing that aims to enhance its process stability, increase production capacity, and improve yields. Occasionally, only few records that indicate defective units are available and they are classified as a minority group in a large database. Such a situation leads to an imbalanced data set problem, wherein it engenders a great challenge to deal with by applying machine learning techniques for obtaining effective solution. In addition, the database may comprise overlapping samples of different classes. This paper introduces two models of evolutionary fuzzy ARTMAP (FAM) neural networks to deal with the imbalanced data set problems in a semiconductor manufacturing operations. In particular, both the FAM models and hybrid genetic algorithms are integrated in the proposed evolutionary artificial neural networks (EANNs) to classify an imbalanced data set. In addition, one of the proposed EANNs incorporates a facility to learn overlapping samples of different classes from the imbalanced data environment. The classification results of the proposed evolutionary FAM neural networks are presented, compared, and analyzed using several classification metrics. The outcomes positively indicate the effectiveness of the proposed networks in handling classification problems with imbalanced data sets.
author_names: Shing Chiang Tan

Junzo Watada

Zuwairie Ibrahim

Marzuki Khalid
title: Evolutionary Fuzzy ARTMAP Neural Networks for Classification of Semiconductor Defects
venue: IEEE Transactions on Neural Networks and Learning Systems
year: 2015

abstract: Wafer fabrication is considered the most complex and costly challenge in the semiconductors industry. Cycle Time (CT) which denotes flow time, is one of its key performance measures. This work develops CT prediction models by applying Machine Learning (ML) and Data Mining (DM) methods. The models can assist in improving manufacturing and supply chain efficiency. They rely on historical production line data taken from the fab's Manufacturing Execution System (MES) and include wafer lot processing details of various operations. The prediction is done for an average CT of a single lot, processed through a single operation step. Two types of classification techniques are used. The best fitted Decision Trees (DT) model achieves 76.5% accuracy, and the best Neural Network (NN) model (two hidden layers) achieves 87.6% accuracy. The significance of this study is in establishing dynamic CT prediction models, which can be used to predict CT of a single operation step, a line segment or a complete production line.
author_names: Israel Tirkel
title: Cycle time prediction in wafer fabrication line by applying data mining methods
venue: 2011 IEEE/SEMI Advanced Semiconductor Manufacturing Conference
year: 2011

abstract: In most industrial processing scenarios the value of a product increases over time in the value chain. To avoid unnecessary processing steps, it is of immense importance to detect defects as early as possible in the value creating process. These situations of interest can be distinguished as specified and unspecified situations, dependent on whether the cause effect relation is known and defined or not. In this article we describe ongoing work on a proactive disruption management system for manufacturing environments, which helps being prepared for the unexpected by applying a combination of unsupervised and supervised machine learning for the identification and prediction of unspecified situations and adopting data mining techniques to derive predictive patterns for specified situations. We also introduce a real world use case from the field of semiconductor manufacturing and present first preliminary results.
author_names: Suad Sejdovic

Yvonne Hegenbarth

Gerald H Ristow

Roland Schmidt
title: Proactive disruption management system: how not to be surprised by upcoming situations
venue: DEBS
year: 2016

abstract: Semiconductor fabrication lines have become extremely costly, and achieving a good return from such a high capital investment requires efficient utilization of these expensive facilities. It is highly desirable to shorten processing development time, increase fabrication yield, enhance flexibility, improve quality, and minimize downtime. We propose that these ends can be achieved by applying recent advances in the areas of artificial neural networks, fuzzy logic, machine learning, and genetic algorithms. We use the term neural manufacturing to describe such applications. This paper describes our use of artificial neural networks to improve the monitoring and control of semiconductor process.
author_names: Chi Yung Fu

Loren Petrich

Benjamin Law
title: Neural manufacturing: a novel concept for processing modeling, monitoring, and control
venue: Advanced Lithography
year: 1995

abstract: Fault diagnosis of Integrated Circuits (ICs) has grown into a special field of interest in the Semiconductor Industry. Fault diagnosis is very useful at the design stage for debugging purposes, at high volume manufacturing for obtaining feedback about the underlying fault mechanisms and improving the design and layout in future IC generations, and in cases where the IC is part of a larger safety critical system (e.g. automotive, aerospace) for identifying the root cause of failure and for applying corrective actions that will prevent failure reoccurrence and, thereby, will expand the safety features. In this summary paper, we present a methodology for fault modeling and fault diagnosis of analog circuits based on machine learning. A defect filter is used to recognize the type of fault (parametric or catastrophic) inverse regression functions are used to locate and predict the values of parametric faults, and multi class classifiers are used to list catastrophic faults according to their likelihood of occurrence. The methodology is demonstrated on both simulation and high volume manufacturing data showing excellent overall diagnosis rate.
author_names: Ke Huang

Haralampos-G D Stratigopoulos

Salvador Mir
title: Fault modeling and diagnosis for nanometric analog circuits
venue: 2013 IEEE International Test Conference (ITC)
year: 2013