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abstract: Ndubuisi Ekekwe Introduction Most modern entertainment gadgets, equipment and tools incorporate integrated circuits that perform some specific functions that make the entertainment experience fascinating for users. From the simple toys for toddlers to the complex game studios in casinos, hardware forms a major component of entertainment technology. With the advent of integrated circuits, and subsequent development of CMOS (complementary oxide semiconductor) technologies, there has been remarkable success in the number of application specific integrated chips (ASIC) tailored for gaming and general entertainment. And from programmable micro controllers to field programmable gate arrays (FPGAs) chips are common tools to both computer scientist and engineer. Consequently, understanding the fascinating processes used in making these chips which are programmed and used in circuit boards could be interesting for all stakeholders in the field of entertainment technology. The design of integrated circuit is perhaps one of the most complex stages in the development process of game and entertainment infrastructure forming a vital part of the entertainment technology. Increasingly, chip designers are discovering ways of implementing functions hitherto done with massive codes of computer programs inside integrated circuits. Integrated circuits are circuits that could contain millions of transistors and other circuit elements on a single die (a piece of silicon that contains active devices and input and output interfaces) [1] They are made on special materials called semiconductors with silicon and gallium arsenide (GaAs) the most common. Its evolution is a major milestone in the history of modern industry as it has driven a revolution in computing capability due to a long trend in performance, density gains, and cost with scaling [1,2] Remarkably, these circuits could be made using different technologies. But over time, complementary metal oxide semiconductor (CMOS) technology has become the industry de facto and the most prevalent method of choice. Its major advantages over other technologies are its ease of integration of circuit components and low static power consumption [3] This is the main technology used to make analog to digital converters, micro controllers, FPGA (an integrated circuit that contains an array of identical cells with programmable interconnections) microprocessors and host of others that are used while developing entertainment hardware. Its continuous improvements has driven reduction in size of game gadgets, better performance, more efficient battery management for battery operated devices, cost as well as hardware ergonomics. Integrated circuit could be digital, analog or mixed signal (a combination of both analog and digital) While the digital chip
title: Introduction Integrated Circuit Design

abstract: The article provides a review of the state of art non destructive testing (NDT) methods used for evaluation of integrated circuit (IC) packaging. The review identifies various types of the defects and the capabilities of most common NDT methods employed for defect detection. The main aim of this paper is to provide a detailed review on the common NDT methods for IC packaging addressing their principles of operation, advantages, limitations and suggestions for improvement. The current methods such as, X ray, scanning acoustic microscopy (SAM) infrared thermography (IRT) magnetic current imaging (MCI) and surface acoustic waves (SAW) are explicitly reviewed. The uniqueness of the paper lies in comprehensive comparison of the current NDT methods, recommendations for the improvements, and introduction of new candidate NDT technologies, which can be adopted for IC packaging.
author_names: Pouria Aryan

Santhakumar Sampath

Hoon Sohn
title: An Overview of Non Destructive Testing Methods for Integrated Circuit Packaging Inspection
venue: Sensors
year: 2018

abstract: Abstract An introduction to the exciting and continuously growing topic of IC packaging is presented herein. This review starts with a beginner's level introduction to microelectronic packaging and its essential functions. These functions include environmental protection, mechanical stability, thermal management, and electrical connection. Important methods and process techniques for satisfying these essential functions are included. Knowledge of this material is important to understand the history and advancements of packaging technology. The history is reviewed in the context of technology advancement drivers and how they have ultimately led to 3D packaging. 3D packaging is the modern milestone in packaging technology, and it is described in detail. 3D packaging technology poses many advantageous but there are also serious design challenges to overcome. 3D packaging architecture, advantages, processing, and current challenges become the focus in the second half of this paper.
author_names: Austin Lancaster

Manish Keswani
title: Integrated circuit packaging review with an emphasis on 3D packaging
venue: Integr.
year: 2018

abstract: Point of care personalized medicine and home diagnostics are emerging topics that can help to master the challenges of aging societies. Magnetic resonance spectroscopy is one of the most promising sensing principles because it enables the detection of proteins, metabolites, and reactive oxygen species, which play crucial roles in a large number of diseases, with high specificity. To provide a self contained introduction to the topic, this article starts with a description of the basic working principle of magnetic resonance spectroscopy, highlighting the similarities and differences compared to conventional impedance spectroscopy methods. Focusing on the two specific techniques of NMR and ESR spectroscopy, we explain how miniaturized systems co integrating detectors and the signal processing electronics on a single chip are a key enabler for portable, low cost spectrometry systems. These systems bear many similarities to conventional communication transceivers and can therefore largely benefit from recent advances in communication circuits as well as entirely new detection principles such as VCObased detection, which are enabled by the use of modern nanometer scaled integrated circuit technologies. An overview of the current state of the art of such miniaturized magnetic resonance spectrometers is presented, which both highlights the excellent new possibilities associated with these systems and at the same time outlines the current challenges and future research directions in this emerging field of research.
author_names: Jonas Handwerker

Benedikt Schlecker

Maurits Ortmanns

Jens Anders
title: Integrated Circuit Technology for Next Generation Point of Care Spectroscopy Applications
venue: IEEE Communications Magazine
year: 2017

abstract: Introduction of a dual beam (DB) millisecond (mSec) or nanosecond (nSec laser annealing in contact module results in a drastic reduction of contact resistivity. Dependence of this benefit on laser annealing parameters is detailed. The annealing power/temperature condition needed for initiating solid or liquid phase epitaxy (SPE, LPE defines a lower process boundary, while impact of laser annealing on transistor parameters, such as Vt and gate stack, defines an upper process boundary and translates to with in die (WID Vt variation. Combining DB laser annealing technique with process friendly layouts enables contact resistance benefit without degrading product level variability.
author_names: Zuoguang Liu

Oleg Gluschenkov

Hiro Niimi

Bei Liu

Jun-tao Li

James John Demarest

Shogo Mochizuki

Praneet Adusumilli

Mark V Raymond

Adra V Carr

Shaoyin Chen

Yun Ran Wang

Hemanth Jagannathan

Tenko Yamashita
title: Dual beam laser annealing for contact resistance reduction and its impact on VLSI integrated circuit variability
venue: 2017 Symposium on VLSI Technology
year: 2017

abstract: Growing demand for bandwidth in Datacom optical links and High Performance Computers (HPC) has recently led to new optoelectronic modules based on Silicon Photonics Integrated Circuits [1] One of the intrinsic capabilities of this technology is its scalability in terms of aggregated data rate, due to the possibility of combining Space Division Multiplexing, Wavelength Division Multiplexing, and the use of advanced modulation formats such as PAM4 or QPSK [2] As a result, standard commercial modules using Silicon Photonics Integrated Circuits (Si PIC) typically providing 10 to 25 Gbps (OOK) per channel over several singlemode fibers, will evolve up to and beyond 400 Gbps and more aggregated data rate in the coming years. In this paper, we demonstrate the introduction of Wavelength Division Multiplexing in a multichannel photoreceiver module using a Si PIC, at a data rate of 25 Gbps per channel.
author_names: Stephane Bernabe

Benoit Charbonnier

B Blampey

Stephane Malhouitre

Olivier Castany

Enrico Temporiti

Gabriele Minoia

Daniele Baldi

Matteo Repossi

Gabriel Pares

Paul Gindre

Sylvie Menezo

Christophe Kopp
title: A fully packaged 25 Gbps/channel WDM photoreceiver module based on a Silicon Photonic Integrated Circuit and a flip chipped CMOS quad transimpedance amplifier
venue: 2016 IEEE Optical Interconnects Conference (OI)
year: 2016

author_names: Richard A Soref
title: Introduction: The Opto Electronic Integrated Circuit
year: 2008

author_names: Hubert Kaeslin
title: Digital Integrated Circuit Design: Introduction to Microelectronics
year: 2008

abstract: The four articles in this special issue focus on failure analysis of integrated circuit devices and packages. The articles are briefly summarized here.
author_names: Deepak Kumar Goyal
title: Introduction to the Special Issue on Failure Analysis of Integrated Circuit Devices and Packages
year: 2007

abstract: Abstract Utilizing a database containing all US patents issued to integrated circuit (IC) manufacturers from 1975 to 1994 we analyze a firm's decision to pursue a technology across varying levels of technological turbulence. We examine the effects of the value of a firm's technological advancement, the newness of its technology, and industry turbulence on the probability of failure. We find during periods of low technological turbulence, firms utilizing new technologies to create significant technological advances, face a higher probability of failure. During periods of high technological turbulence, firms using older technology to develop significant technological advancements face lower probabilities of failure.
author_names: Edward Levitas

M Ann McFadyen

David Loree
title: Survival and the introduction of new technology: A patent analysis in the integrated circuit industry
year: 2006