Search query: A CMOS implement-ation of controller based all digital phase locked loop (ADPLL)

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abstract: Purpose Biomedical radio frequency (RF) transceivers require miniaturized forms with long battery life and low power consumption. The medical implant communication service (MICS) band in the frequency range of 402 405 MHz is widely used for medical RF transceivers because the MICS band signals have reasonable propagation characteristics and are suited to achieve good results. The implementation of the RF front end for medical devices has many challenges as these dictate low power consumption. In particular, phase locked loop is one of the most critical blocks of the RF front end. The purpose of this paper is to the design of controller based all digital phase locked loop (ADPLL) in a 45 nm CMOS process. Design/methodology/approach Initially, an open loop architecture phase frequency detector (PFD) is designed. Then based on the concept of differential buffer, a differential ring oscillator (RO) is built using capacitive boosting technique. After that, the frequency controller block is built by proper mathematical modeling that does the job of loop filter, which behaves like a phase interpolator. Frequency controller block has tuning register block, tuning word register. The tuning block is built using the Metal Oxide Semiconductor (MOS) caps. Finally, the integration of all the blocks is done and the ADPLL architecture that locks at 402 MHz is achieved. Findings The designed PFD is dead zone free that operates at 1 GHz. The differential RO oscillates at 495 MHz. The proposed ADPLL operates at 402 MHz with measured phase noise of 98.36 at 1 MHz offset. This ADPLL exhibits rms jitter of 4.626 ps with a total power consumption of 216.5 uW. Research limitations/implications A time to digital converter (TDC) less controller based low power ADPLL covering the MICS frequency band for biomedical applications has been designed in 45 nm/0.68 V CMOS technology. The ADPLL proposed in this draft uses differential oscillator with capacitively boosted technique which reduced the operating voltage to as low as 0.68 V. This ADPLL has a bandwidth of 20 kHz and works at reference frequency of 20 MHz consumed power of 216.5 uW, while generating an output frequency of 402 MHz. The tuning range is from 375 to 428 MHz. With the phase noise of 98.36 dbc/Hz at 1 MHz, a frequency controller block replaces the usage of TDC. Social implications The designed ADPLL will definitely pave way to greater research arena in the field of biomedical field. This ADPLL is a unique combination that combines electronics and biomedical field. The designed ADPLL is itself a broader application to biomedical field that will have a positive impact on the society. Originality/value The implementation of open loop PFD and RO using the capacitive boosting technique is a unique combination. This is comprehended well with frequency controller block that eliminates the usage of TDC and behaves as phase interpolator. The entire design of ADPLL which suits the application of MICS band of frequency has been designed carefully to work at low power.
author_names: Vikas Balikai

Harish Mallikarjun Kittur
title: A CMOS implementation of controller based all digital phase locked loop (ADPLL)
year: 2020

abstract: A design procedure of an all digital phase locked loop (ADPLL) based on phase selection mechanism with loop stability independent of process, supply voltage and temperature is presented. A poly phase filter and a phase interpolator are used to generate multiple phases to reduce the phase error. The modeling of proposed ADPLL structure is extensively investigated and mathematically described. For a phase and a frequency step input change, the closed loop system of the proposed ADPLL eliminates phase error. Time domain response of the behavioral level simulation of the proposed structure on 130 nm CMOS technology with 0.7V supply voltage reveals the presented analytical model.
author_names: Saichandrateja Radhapuram

Jung-Nam Bae

Ikkyun Jo

Weimin Wang

Toshimasa Matsuoka
title: ANALYSIS OF A CONTROLLER BASED ALL DIGITAL PHASE LOCKED LOOP
year: 2015

abstract: This paper presents a 2.57GHz All Digital Phase Locked Loop(ADPLL) Based on the digital controlled Ring Oscillator, which uses a frequency and phase detector controller architecture with high resolution and wide locking range. In order to speed up the phase locking, reduce the instantaneous phase locked differential, this dissertation adopts a forward prediction method. The DCO uses 3 stage ring oscillator, the oscillator frequency is controlled by the coarse tune words(CTW) and the fine tune words(FTW) the CTW to control the output frequency fast approaching the target frequency and the FTW to control the final target frequency, in addition, in order to make the DCO work in a linear zone, a normal open oscillation circuit is designed. The layout of the ADPLL circuit is completed by 0.18um CMOS process, which area is 0.3416 mm2 (including pad) The post simulation results show that the maximum output clock frequency is over 2.57GHZ.
author_names: Ruan Weihua

Wang Haipeng
title: A 2.57GHz All Digital Phase Locked Loop Based on the digital controlled Ring Oscillator
venue: 2019 11th International Conference on Information Technology and Electrical Engineering (ICITEE)
year: 2019

abstract: This paper presents a design of All Digital Phase Locked Loop (ADPLL) for wireless applications. It is designed using master and slave Dflipflop for linear phase detector, counter based loop filter and ring oscillator based Digital controlled oscillator(DCO) The programmable divider is used in the feed back loop which is used has a frequency synthesizer for wireless applications. It is implemented in 180nm CMOS technology in Cadence EDA tool. The proposed ADPLL has locking period of 50ps and the operating frequency range of 4.7GHz and power consumption of 26mW.
author_names: Ravikanti Swetha

J Manjula

A Ruhan Bevi
title: Design of All Digital Phase Locked Loop for Wireless Applications
year: 2018

abstract: A low voltage controller based all digital phase locked loop (ADPLL) utilized in the medical implant communication service (MICS) frequency band was designed in this study. In the proposed design, controller based loop topology is used to control the phase and frequency to ensure the reliable handling of the ADPLL output signal. A digitally controlled oscillator with a delta sigma modulator was employed to achieve high frequency resolution. The phase error was reduced by a phase selector with a 64 phase signal from the phase interpolator. Fabricated using a 130 nm CMOS process, the ADPLL has an active area of 0.64 mm2, consumes 840 mW from a 0.7 V supply voltage, and has a settling time of 80 ms. The phase noise was measured to be 114 dBc/Hz at an offset frequency of 200 kHz. key words: all digital phase locked loop, controller, digitally controlled oscillator, phase interpolator, CMOS, MICS
author_names: Jung-Nam Bae

Saichandrateja Radhapuram

Ikkyun Jo

Weimin Wang

Takao Kihara

Toshimasa Matsuoka
title: A Design of 0.7 V 400 MHz All Digital Phase Locked Loop for Implantable Biomedical Devices
venue: IEICE Trans. Electron.
year: 2016

abstract: This paper presents a power efficient sub sampling all digital phase locked loop with less than 90fsrms jitter performance. A stochastic flash time to digital converter is utilized and obtains sub picosecond effective resolution. A "folded" common mode resonator is included within the digitally controlled oscillator to enhance performance while maintaining a compact design. The ADPLL covers 9 to 12.1 GHz (29.4% fractional tuning range) Measured phase noise of 105.2/ 109/ 124.85 dBc/Hz at 10.6 GHz for 0.1/1/10 MHz frequency offset respectively. Integrated phase noise lower than 45 dBc was recorded for the whole tuning range for an integration range between 10 KHz to 40 MHz. The ADPLL consumes 15.5 mA from a 0.8 V analog supply and 7 mA from a 0.7 V digital supply, for a total power consumption of 17.3 mW and a peak jitter power figure of merit (FoMj) of 248 dB. Fabricated in 16nm FinFet CMOS, the silicon area is 0.24 mm2.
author_names: Run Levinger

Evgeny Shumaker

A Farber

S Bershansky

Nir Geron

Ofir B Degani

Ashoke Ravi

Rotem Banin

E Banin

J Kadry

Gil Horovitz
title: A 9 to 12.1 GHz Sub Sampling ADPLL based on a Stochastic Flash TDC and a DCO with a "Folded" Common Mode Resonator Exhibiting less than 90fs Jitter and a peak FoMj of 248 dB in 16nm FinFet CMOS
venue: 2020 50th European Microwave Conference (EuMC)
year: 2021

abstract: In this article, we introduce a fractional N all digital phase locked loop (ADPLL) architecture based on a single LC tank, featuring an ultra wide tuning range (TR) and optimized for ultra low area in 10 nm FinFET CMOS. Underpinned by excellent switches in the FinFET technology, a high turn on/off capacitance ratio of LC tank switched capacitors, in addition to an adjustable magnetic coupling technique, yields almost an octave TR from 10.8 to 19.3GHz. A new method to compensate for the tracking bank resolution can maintain its quantization noise level over this wide TR. A new scheme is adopted to overcome the metastability resolution problem in a fractional N ADPLL operation. A low complexity TDC gain estimator reduces the digital core area by progressive averaging and time division multiplexing. Among the published fractional N PLLs with an area smaller than 0.1mm2, this work achieves an rms jitter of 725fs in an internal fractional N mode of ADPLL's phase detector (2.7 4.825GHz) yielding the best overall jitter figure of merit (FOM) of 232dB. This topology features small area (0.034mm2) wide TR (56.5% and good supply noise rejection (1.8%/V) resulting in FOMs with normalized TR (FOMT) of 247dB, and normalized TR and area (FOMTA) of 262dB.
author_names: Min-Shueh Yuan

Chia-Chun Liao

Chih-Hsien Chang

Yu-Tso Lin

Tsung-Hsien Tsai

Tien-Chien Huang

Hsien-Yuan Liao

Chung-Ting Lu

Hung-Yi Kuo

Augusto Ronchini Ximenes

Robert Bogdan Staszewski
title: A Compact Transformer Based Fractional N ADPLL in 10 nm FinFET CMOS
venue: IEEE Transactions on Circuits and Systems I: Regular Papers
year: 2021

abstract: This dissertation presents a proposed all digital phase locked loop and a digitally controlled oscillator with low power consumption for fractional N frequency synthesis applications. The basic operation of the conventional PLL based frequency synthesizers is first briefly reviewed, followed by the literature review of some reported digital PLL based frequency synthesizer. An all digital PLL is thus proposed, including the system architecture and implementations of its sub blocks. In the proposed all digital PLL, the PFD TDC pair used in many reported digital PLLs is replaced by a customized time to digital converter. A novel Schmitt trigger based digital controlled oscillator is proposed to achieve a wide linear tuning range with low power consumption. The novel locking process of the proposed ADPLL is separated into frequency and phase acquisition. Instead of "ahead" or "behind" comparison, the time todigital converter is used to measure the frequency difference accurately, which greatly reduces the lock in time. The phase acquisition only takes two reference clocks. One cycle for resetting the DCO and the other cycle for updating the control considering the path delay. To further prove the feasibility of the novel ADPLL, a fractional N frequency synthesizer is implemented based on the proposed ADPLL. An extra TDC is applied to obtain the fractional value avoiding the use of fractional divider, which is the main source of fractional spur in a fractional N frequency synthesizer. The proposed Fractional N frequency synthesizer is implemented using a 0.9V 32nm Practical Transistor Model. The phase noise performance, the frequency locking speed as well as the tuning range of the digitally controlled oscillator was measured and well agrees with the theoretical analysis.
author_names: A Master Thesis Presented

Jun Zhao
title: A Low Power CMOS Design of An All Digital Phase Locked Loop
year: 2011

abstract: A low voltage controller based all digital phase locked loop (ADPLL) utilized in the medical implant communication service (MICS) frequency band is designed. The controller based loop topology is used to control the phase and frequency for reliable handling of the ADPLL output signal. The digitally controlled oscillator with the delta sigma modulator is employed to achieve high frequency resolution. The phase error is reduced by the phase selector with 64 phase signal from the phase interpolator. Fabricated in a 130 nm CMOS process, the ADPLL has an active area of 0.64 mm2. It consumes 840 mW from a 0.7 V supply voltage and has a settling time of 80 ms. The measured phase noise is 114.6 dBc/Hz at 200 kHz offset frequency.
author_names: Jung-Nam Bae

Saichandrateja Radhapuram

Ikkyun Jo

Takao Kihara

Toshimasa Matsuoka
title: A low voltage design of controller based ADPLL for implantable biomedical devices
venue: 2015 IEEE Biomedical Circuits and Systems Conference (BioCAS)
year: 2015

abstract: In this paper, we apply various area reduction techniques on an inductor capacitor (LC) tank oscillator in order to make its size comparable to that of ring oscillators (ROs) while still retaining its salient features of excellent phase noise and low sensitivity to supply variations. The resulting oscillator employs a proposed ultracompact split transformer topology that provides a 1:2 passive voltage gain and is less susceptible to common mode electromagnetic interference than are regular high quality factor LC tanks, thus making it desirable in system on a chip environments. The oscillator, together with a proposed dc coupled buffer, is incorporated within an all digital phase locked loop (ADPLL) intended for wireline, digital clocking, and less stringent wireless systems. The ADPLL architecture introduces a look ahead time to digital converter that exploits a deterministic phase prediction to reduce power consumption and phase detection complexity. The ADPLL is realized in 40 nm CMOS and has the smallest reported area of 0.0625 mm2 among LC tank oscillators while providing fractional N operation, wide tuning range of 45% (from 9.4 to 14.8 GHz) very low voltage supply sensitivity of 80 MHz/V, and integrated figure of merit jitter (FoMjitter) better than 230 dB. A separate identical ADPLL was implemented using an RO instead, for completeness and systematic comparisons.
author_names: Augusto Ronchini Ximenes

Gerasimos Vlachogiannakis

Robert Bogdan Staszewski
title: An Ultracompact 9.4 14.8 GHz Transformer Based Fractional N All Digital PLL in 40 nm CMOS
venue: IEEE Transactions on Microwave Theory and Techniques
year: 2017