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abstract: Advanced beyond silicon electronic technology requires both channel materials and also ultralow resistance contacts to be discovered1,2. Atomically thin two dimensional semiconductors have great potential for realizing high performance electronic devices1,3. However, owing to metal induced gap states (MIGS)4 7, energy barriers at the metal semiconductor interface which fundamentally lead to high contact resistance and poor current delivery capability have constrained the improvement of two dimensional semiconductor transistors so far2,8,9. Here we report ohmic contact between semimetallic bismuth and semiconducting monolayer transition metal dichalcogenides (TMDs) where the MIGS are sufficiently suppressed and degenerate states in the TMD are spontaneously formed in contact with bismuth. Through this approach, we achieve zero Schottky barrier height, a contact resistance of 123 ohm micrometres and an on state current density of 1,135 microamps per micrometre on monolayer MoS2; these two values are, to the best of our knowledge, the lowest and highest yet recorded, respectively. We also demonstrate that excellent ohmic contacts can be formed on various monolayer semiconductors, including MoS2, WS2 and WSe2. Our reported contact resistances are a substantial improvement for two dimensional semiconductors, and approach the quantum limit. This technology unveils the potential of high performance monolayer transistors that are on par with state of the art three dimensional semiconductors, enabling further device downscaling and extending Moore's law.
author_names: Pin-Chun Shen

Cong Su

Yuxuan Lin

Ang-Sheng Chou

Chao-Ching Cheng

Ji-Hoon Park

Ming-Hui Chiu

Ang-Yu Lu

Hao-Ling Tang

Mohammad Mahdi Tavakoli

Gregory Pitner

Xiang Ji

Zhengyang Cai

Nannan Mao

Jiangtao Wang

Vincent C Tung

Ju Li

Jeffrey Bokor

Alex Zettl

Chih-I Wu

Tomas Palacios

Lain-Jong Li

Jing Kong
title: Ultralow contact resistance between semimetal and monolayer semiconductors.
venue: Nature
year: 2021

abstract: In the post Moore era, it is well known that contact resistance has been a critical issue in determining the performance of complementary metal oxide semiconductor (CMOS) reaching physical limits. Conventional Ohmic contact techniques, however, have hindered rather than helped the development of CMOS technology reaching its limits of scaling. Here, a novel conductive filament metal interlayer semiconductor (CF MIS) contact which achieves ultralow contact resistance by generating CFs and lowering Schottky barrier height (SBH) is investigated for potential applications in various nanodevices in lieu of conventional Ohmic contacts. This universal and innovative technique, CF MIS contact, forming the CFs to provide a quantity of electron paths as well as tuning SBH of semiconductor is first introduced. The proposed CF MIS contact achieves ultralow specific contact resistivity, exhibiting up to ~x700 000 reduction compared to that of the conventional metal semiconductor contact. This study proves the viability of CF MIS contacts for future Ohmic contact schemes and that they can easily be extended to mainstream electronic nanodevices that suffer from significant contact resistance problems.
author_names: Seung-Hwan Kim

Gwang-Sik Kim

June Park

Changmin Lee

Hyoungsub Kim

Jiyoung Kim

Joon Hyung Shim

Hyun-Yong Yu
title: Novel Conductive Filament Metal Interlayer Semiconductor Contact Structure for Ultralow Contact Resistance Achievement.
venue: ACS applied materials interfaces
year: 2018

abstract: We report on the electrical and microstructural characterization of Au free Ti/Al/Ti/TiN contacts for AlGaN/GaN heterostructures. Ultra low Au free ohmic contact has been obtained with contact resistance and specific contact resistivity as low as <inline formula> <tex math notation="LaTeX"$0.21~\Omega \cdot \text{mm} /tex math>/inline formula> and <inline formula> <tex math notation="LaTeX"{1.16}\times {10} 6} \Omega \cdot \text{cm}{2} /tex math>/inline formula> respectively. The ohmic alloy temperature is reduced as low as 550 degC by pre ohmic recess of the AlGaN barrier and optimization of the thickness of bottom Ti layer. We found that interfacial layer formation of AlN between the ohmic metal and AlGaN surface is crucial to realize a low contact resistance with reduced low annealing temperature by a combination of electrical <inline formula> <tex math notation="LaTeX"{I} /tex math>/inline formula> <inline formula> <tex math notation="LaTeX"{V} /tex math>/inline formula> characterization and high resolution transmission electron microscopy analysis. Furthermore, we suggest a hypothesis that the bottom Ti layer plays a catalytic role for the Al N reaction with optimized thickness.
author_names: Jinhan Zhang

Xuanwu Kang

Xinhua Wang

Sen Huang

C Chen

Ke Wei

Yingkui Zheng

Qi Zhou

Wanjun Chen

Bo Zhang

Xinyu Liu
title: Ultralow Contact Resistance Au Free Ohmic Contacts With Low Annealing Temperature on AlGaN/GaN Heterostructures
venue: IEEE Electron Device Letters
year: 2018

abstract: The electrical performance of graphene based devices is largely limited by substantial contact resistance at the heterodimensional graphene metal junctions. A laser assisted nanowelding technique is developed to reduce graphene metal (G M) contact resistance and improve carrier injection in suspended graphene devices. Selective breakdown of CC bonds and formation of structural defects are realized through laser irradiation at the edges of graphene within the G M contact regions in order to increase the chemical reactivity of graphene, facilitate G M bonding, and, therefore, maximize interfacial carrier transportation. Through this method, significantly reduced G M contact resistances, as low as 2.57 O um are obtained. In addition, it is demonstrated that the location of laser induced defects within the contact areas significantly impacts the interfacial properties and the carrier mobility of graphene devices. A fourfold increase in photocurrent is observed in the suspended graphene photodetectors with treated G M interfaces as compared to ordinary ones. This contact free and position selective technique minimizes the degradation of the graphene channels and maintains the superior performance of graphene devices, making it a promising approach for reducing G M resistance in the fabrication of graphene based devices.
author_names: Kamran Keramatnejad

Yunsheng Zhou

Dawei Li

Hossein Rabiee Golgir

Xi Huang

Qi Ming Zhou

Jingfeng Song

Stephen Ducharme

Yongfeng Lu
title: Laser Assisted Nanowelding of Graphene to Metals: An Optical Approach toward Ultralow Contact Resistance
year: 2017

abstract: Heteroepitaxial growth of Cr metal on Nb doped SrTiO3(001) is accompanied by Cr diffusion to interstitial sites within the first few atomic planes, an anchoring of the Cr film to the substrate, charge transfer from Cr to Ti, and metallization of the near surface region, as depicted in the figure. The contact resistance of the resulting interface is exceedingly low.
author_names: Scott A Chambers

Meng Gu

Peter V Sushko

Hao Yang

Chongmin Wang

Nigel D Browning
title: Ultralow contact resistance at an epitaxial metal/oxide heterojunction through interstitial site doping.
venue: Advanced materials
year: 2013

abstract: We show that the parasitic contact resistance in staggered organic thin film transistors employing a solid electrolyte as the gate dielectric is around RC=10 O cm, two orders of magnitude lower than in conventional devices. Moreover, this parameter is only weakly dependent on the thickness of the semiconductor and on the nature of the metal/semiconductor pair. This unique feature of an electrolyte gated transistor results from the electrochemical doping of the active layer occurring under the influence of the applied gate bias.
author_names: Daniele Braga

Min-Woo Ha

Wei Xie

C Daniel Frisbie
title: Ultralow contact resistance in electrolyte gated organic thin film transistors
year: 2010

abstract: Abstract Low dimensional silicon based materials have shown a great potential for thermoelectric applications due to their enhanced figure of merit ZT and high technology compatibility. However, their implementation in real devices remains highly challenging due to the associated large contact resistances (thermal and electrical) Herein we demonstrate ultralow contact resistance silicon nanowires epitaxially grown on scalable devices with enhanced ZT. Temperature dependent figure of merit was fully determined for monolithically integrated individual silicon nanowires achieving a maximum value of ZT 0.2 at 620 K. Sidewise, this work accounts for the first time nearly zero thermal and electrical contact resistances in monolithically integrated bottom up nanowires.
author_names: Gerard Gadea Diez

Jose Manuel Sojo Gordillo

Merce Pacios Pujado

Marc Salleras

Luis Fonseca

Alex Morata

Albert Tarancon Rubio
title: Enhanced thermoelectric figure of merit of individual Si nanowires with ultralow contact resistances
year: 2020

abstract: A metal resistance aware transmission line model (MRA TLM) is developed to eliminate the parasitic metal resistance from the extraction of specific contact resistivity <inline formula> <tex math notation="LaTeX"\rho _{c} /tex math>/inline formula> in the metal/semiconductor contact. The proposed MRA TLM is verified by Synopsys technology computer aided design (TCAD) simulation, and a superior extraction accuracy as compared to the conventional TLM based method is achieved. The proposed MRA TLM is experimentally demonstrated in the metal/p<sup>/sup> Ge<sub>0.95</sub>Sn<sub>0.05</sub> (p<sup>/sup> GeSn) contacts. Ultralow <inline formula> <tex math notation="LaTeX"\rho _{c} /tex math>/inline formula> values of <inline formula> <tex math notation="LaTeX"{7.5} \times {10} {10} /tex math>/inline formula> and <inline formula> <tex math notation="LaTeX"{2.1} \times {10} {9} \Omega \cdot \text {cm}{2} /tex math>/inline formula> are extracted by MRA TLM for Ni/p<sup>/sup> GeSn and Ti/p<sup>/sup> GeSn contacts, respectively, which are in good agreement with <inline formula> <tex math notation="LaTeX"{9.5} \times {10} {10} /tex math>/inline formula> and <inline formula> <tex math notation="LaTeX"{2.6} \times {10} {9} \Omega \cdot \text {cm}{2} /tex math>/inline formula> extracted numerically by the two layer distributed resistor network model (TDM) qualifying the proposed MRA TLM for the extraction of ultralow <inline formula> <tex math notation="LaTeX"\rho _{c} /tex math>/inline formula> down to sub <inline formula> <tex math notation="LaTeX"$10^ {9}\Omega \cdot \text {cm}{2} /tex math>/inline formula> regime. In contrast, the <inline formula> <tex math notation="LaTeX"\rho _{c} /tex math>/inline formula> extracted by the conventional TLM based method is more than three times higher due to the parasitic metal resistance.
author_names: Ying Wu

Haiwen Xu

Xiao Gong

Yee-Chia Yeo
title: Elimination of the Parasitic Metal Resistance in Transmission Line Model for Extraction of Ultralow Specific Contact Resistivity
venue: IEEE Transactions on Electron Devices
year: 2019

abstract: Ultralow contact resistance of metal silicide n+ Si contact has been achieved by a novel contact metallization process employing Ta silicidation of a n+ Si contact surface by a Si capping silicidation technique. The Si capping silicidation has been employed to realize an ultraclean silicidation. The as deposited Ta surface is in situ covered with a very thin Si protection layer in order to prevent the metal surface from being oxidized or contaminated. By combining the oxide layer free Si/metal on Si deposition process and an ultraclean ion implantation for mixing, metal silicide n+Si structure has been formed by low temperature thermal annealing in an ultraclean Ar gas. As a result, an ultralow contact resistivity of 5.8x10 9 (O cm2) has been achieved.
author_names: Keiichi Yamada

Kazuo Tomita

Tadahiro Ohmi
title: Formation of metal silicide silicon contact with ultralow contact resistance by silicon capping silicidation technique
year: 1994

abstract: In this brief, the high quality carbon nanotubes (CNTs) is grown by a chemical vapor deposition (CVD) method, and it is used as an ultrafine flip chip interconnection material in the proposed 3 D integrated circuit (3DIC) system. We show a patterned growth of multiwalled CNTs on the substrate with prestructured bond pads including a complete metallization system for an electrical characterization. We succeeded in achieving reliable flip chip connections between CNT covered contact pads and metal pads during the room temperature bonding process. The goal is a reversible electrical and mechanical chip assembly with CNT bumps. Based on the current voltage <inline formula> <tex math notation="LaTeX"{I} /tex math>/inline formula> <inline formula> <tex math notation="LaTeX"{V} /tex math>/inline formula> measurements, the resistivity <inline formula> <tex math notation="LaTeX"\rho /tex math>/inline formula> of the grown CNTs is found to be close to <inline formula> <tex math notation="LaTeX"\sim 10^ {6}\sf \Omega \text{m} /tex math>/inline formula> With the proposed 3DIC process flow, the vertically electrical connection between two different Si substrates is demonstrated successfully. The connection resistance in the full 3 D system is very promising <inline formula> <tex math notation="LaTeX"\sim 2.43~\sf \Omega /tex math>/inline formula> compared with other's work <inline formula> <tex math notation="LaTeX"\sim 12~\sf \Omega /tex math>/inline formula> The different bonding materials (In versus Sn) and bonding times are also investigated systemically and further optimized. This brief provides a useful solution for the future electrical connection in the high performance and high dense 3 D integrated devices.
author_names: M -H Liao

P Y Lu

W -J Su

S -C Chen

H T Hung

C Robert Kao

W -C Pu

C -C A Chen

M -H Lee
title: The Demonstration of Carbon Nanotubes (CNTs) as Flip Chip Connections in 3 D Integrated Circuits With an Ultralow Connection Resistance
venue: IEEE Transactions on Electron Devices
year: 2020