Search query: Edge and Bevel Automated Defect Inspection for 300mm Production Wafers in Manufacturing

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abstract: In this paper, we describe a solution for wafer edge and bevel apex defect inspection for a 300 mm semiconductor automated fab. Traditionally, we have used an advanced macro inspection solution for topside wafer inspection. The automated tool revealed that defects surfacing after the back end of line (BEOL) copper chemical mechanical polish planarization (Cu CMP) process were significantly impacting yields. We suspected that particles and film on the edge and bevel were flaking off on to the top of the wafers, causing the yield degradation. However, we needed more information from the edge to confirm our hypothesis. Since offline manual edge analysis was not cost effective for larger wafer sampling, we sought to develop an inline bevel inspection at the CMP sector that was fast, cost effective, and integrated with the advanced macro inspection tool. We also established a long term goal of expanding the process into an all surfaces inspection within one manufacturing operation step. This paper describes how we integrated the top down macro and edge bevel inspection into a single automated operation, enhancing data collection and our ability to take corrective action. The process includes full top and complete edge bevel inspection of less than 10 percent of each lot. Although we ran sample tests to inspect edges after numerous processes, this paper focuses on BEOL Cu CMP inspection, including data collection and corrective actions. We also highlight the benefits of edge inspection, and the new level of automated process control. As a result of edge inspection, we have taken corrective actions that have reduced defects on the edge bevel, and improved wafer final test yields by 10 percent from the baseline
author_names: Jesus Morillo

Thomas Houghton

J Bauer

Rob Smith

Richard F Shay
title: Edge and bevel automated defect inspection for 300mm production wafers in manufacturing
venue: IEEE/SEMI Conference and Workshop on Advanced Semiconductor Manufacturing 2005.
year: 2005

abstract: As 3D TSV technology based solutions are moving into volume manufacturing, monitoring of the processed device wafer through temporary bonding, thinning, TSV reveal, metallization and de bonding processes remains a key yield concern. Edge chipping, micro cracks, device carrier misalignment, adhesive residue at edge and delamination during device wafer thinning and later process steps are some of the process challenges. Monitoring of device wafer edge for bond process defects and device carrier concentricity is critical to ramp up yields and reduce the overall cost of ownership of the TSV process flow. Additionally, to get the highest yield from temporary bonding process, thickness and TTV (total thickness variation) measurements from different layers of the bonded stack as well as detecting bonding voids in one single measurement run is vital. In this contribution, we will discuss the main factors affecting edge yield of temporary bonded and thinned device wafers and demonstrate the use of automated edge inspection and metrology for process control and yield improvement.
author_names: Jie Gong

Sumant Sood

Rohit Bhat

Sina Jahanbin

Prashant A Aji

Thomas Uhrmann

Julian Bravin

Jurgen Burggraf

Markus Wimplinger

Paul Lindner
title: Wafer edge defect study of temporary bonded and thin wafers in TSV process flow
venue: 2015 IEEE 65th Electronic Components and Technology Conference (ECTC)
year: 2015

abstract: As device sizes continue to increase on devices at 2x nm design rule and beyond and high wafer stress is worsening due to multi film stacking in the vertical memory process, we observe an increasing trend in edge yield issues worldwide. Wafer edge inspection and metrology become thus critical to drive root cause analysis for improving the yield during a new technology ramp. Nowadays, wafer defectivity correlation to edge is also key for production monitoring, but not without challenges due to the diverse sensitivity demands for the wafer front side, as compared to the wafer edge and back side. In this paper we are able to demonstrate that a cluster inspection platform with the proper balance of sensitivity and throughput is a key enabler for production monitoring. The study required high resolution imaging of the wafer front side, accurate metrology and defect binning capability at the wafer edge, and unique capability to isolate issues that matter in the wafer backside all in a single inspection cluster tool platform. This setup allows for faster time to decisions and eliminates the need to rely on other sources of inspection data. We present several examples of defectivity correlation between the wafer edge and both front and back side, with scanning electron microscope (SEM) examples showing same defect types captured. The root cause for edge defectivity is very often found to be in the crossover of edge bead removal (EBR) lines from successive steps. High quality and accurate EBR metrology is thus essential on many process steps including on backend layers where many EBR lines are found and need to be distinguished. Likewise, anomalies in metrology data of the edge profile can also act as an important indicator of possible defectivity on the wafer. Keywords Wafer Edge, Inspection, Metrology, Defect correlation, Root cause analysis
author_names: Tae-Heon Kim

Jaehyoung Oh
title: Criticality of Wafer Edge Inspection and Metrology Data to All Surface Defectivity Root Cause and Yield Analysis
year: 2016

abstract: Monitoring detectivity of the wafer edge, bevel and apex the areas beyond the pattern is becoming increasingly important in the yield enhancement efforts of high end fabs. In this paper we present a methodology for root cause analysis of edge and bevel defects, based on inline SEM review and EDX based material analysis.
author_names: Ronnie Porat

Kfir Dotan

Shirley Hemar

Lior Levin

K Li

G Sung
title: SEM based methodology for root cause analysis of wafer edge and bevel defects
venue: 2008 IEEE/SEMI Advanced Semiconductor Manufacturing Conference
year: 2008

abstract: 3D integration requires innovative process control solutions to ensure the integrity of the device wafers that are bonded, thinned and then de bonded before permanent bonding. Right now, most 3D TSV pilot lines use a number of semi auto or manual inspection tools: Microscopes, interferometers, profilometers and acoustic microscopes. Other sites use automated scanning inspection tools that are not adapted to detect specific 3D integration defectivity. Leading the field, IMEC and Nanda Tech partnered to tailor the Spark platform to the requirements of 3D integration process control. From the pilot line to the high volume manufacturing fabs, Spark provides a flexible process control platform, adapted to handling bonded wafers and finding the defects of interest that will affect expensive customer wafers.
author_names: Pierre-Yves Guittet

Lars Markwort

Greg Savage

Christoph Kappel

Sandip Halder

Alain Phommahaxay

Anne Jourdain

Andy Miller
title: High speed full wafer monitoring of surface, edge and bonding interface for 3Dstacking
venue: 2011 IEEE 13th Electronics Packaging Technology Conference
year: 2011

abstract: Introduction In today's business climate, continuous i n n ova t i o n a n d p ro d u c t i v i t y improvements are essential to the survival of any company. In the semiconductor industry, productivity improvement is generally accomplished using decreased cost per function, economy of scale, increased wafer diameter, process simplification and yield enhancement. The challenges for extreme edge dies increased with the conversion from 200mm to 300mm wafer processing, and will be further increased by the transition to 450mm [3] Increasingly sophisticated and more expensive equipment is required for technology shrinks, making the acquisition of funds for capacity expansion ever more difficult. Process simplification can only be done to a certain extent. Emphasis is therefore placed on fast yield learning, which claims the biggest financial leverage. Due to the narrower process windows at smaller technology nodes, centerto edge uniformity over the wafer is crucial for yield [4] Consequently, wafer edge and bevel induced yield loss were introduced as critical elements to the International Technology Roadmap for Semiconductors (ITRS) in 2005 and are still considered challenging [5, 6] The ITRS also highlights the importance of r im problems in the wafer edge exclusion guideline. A recent repor t descr ibed the economically optimized technology transfer and ramp methodology from development to a mass production site within a global fabrication cluster [7] This paper outlines the wafer edge yield engineering methodology, which was essential for the reported steep production ramp.
author_names: Oguz Yavas

Ernst-christian Richter

Christian Kluthe

Markus Sickmoeller
title: Wafer edge yield engineering in leading edge DRAM manufacturing
year: 2009

abstract: The defect density reduction is one of the main challenges to increase the yield. This article presents a mechanism of defect formation specific to the STI module. This defect flake like appears during HDP CVD process deposition. It comes from oxide bubbles localised at the bevel of the substrate. The suppression of this defect consists into the bevel shape optimization. Moreover, process improvement as resist strip post etch contributes to clean the bevel from polymer and reduces strongly the flakes density.
author_names: Virginie Dureuil

Jean-Luc Baltzinger

Kevin Tastets

L Vallier

N Wlodarczyk

O Bernaud

J Leroueille

C Mouroux
title: Wafer bevel shape inducing high defect density in shallow trench isolation process
venue: 2010 IEEE/SEMI Advanced Semiconductor Manufacturing Conference (ASMC)
year: 2010

abstract: This paper describes a methodology for defect review and process monitoring on wafer's upper bevel and apex. A case study gives an example of successful application.
author_names: Britta Becker

Ronnie Porat

Hanan Eschwege
title: Identification of yield loss sources in the outer dies using SEM based wafer bevel review
venue: 2010 IEEE/SEMI Advanced Semiconductor Manufacturing Conference (ASMC)
year: 2010

abstract: Defects on the backside of wafers can be either tool or process induced and can cause lithography related issues such as focus deviation or chuck contamination. Tool induced scratches, process induced contamination, or residues on the back of wafers often have unique signatures, such as a repeatable scratch caused by wafer handling equipment or a chuck imprint on the backside of a wafer. Certain backside defect signatures such as large scratches or divots can contribute to wafer breakage or reliability issues. Spatial Pattern Recognition (SPR) is a method of comparing defect patterns at the wafer level with known defect signatures stored in a library that is created from process data. These defect signatures can represent systemic issues with process tools, handling equipment, or the process itself. This paper describes a backside inspection method for identifying wafers with both known and new spatial pattern signatures. By reporting the frequency of each signature category, process partitioning can efficiently trace the source of these problems. In addition, new defect signatures can be automatically learned and added to the library. The paper also includes examples of how this method was used to identify backside defect patterns caused by process and tool excursions in a 300mm fabricator.
author_names: Alan Carlson

Prasad Bachiraju

Jennifer Clark

Dale Trost
title: Use of wafer backside inspection and SPR to address systemic tool and process issues
venue: Advanced Lithography
year: 2010

abstract: We regard the stringent adoption of factory automation as the right strategy to efficiently leverage a 200 mm fab's competitiveness. In this article we exemplarily show how the Dresden fab cut its own path in the face of the transition challenge from a high volume low mix fab to a high mix low volume fab. We discuss the advantages of our conveyor type transport system with respect to our automation strategy and its extendibility to direct tool loading. A comparison of our transport system with typical 300 mm performance data and current ITRS requirements [1] is presented. We describe the positive influence of the taken factory automation measures on typical key manufacturing indicators like cycle time, tool utilization, head count efficiency, variability improvement, cost efficiency and quality.
author_names: Harald Heinrich

Germar Schneider

Frank Heinlein

Sophia Keil

Arthur Deutschlander

Rainer Lasch
title: Pursuing the Increase of Factory Automation in 200mm Frontend Manufacturing to Manage the Changes Imposed by the Transitionfrom High Volume Low Mix to High Mix Low Volume Production
venue: 2008 IEEE/SEMI Advanced Semiconductor Manufacturing Conference
year: 2008