Search query: modern semiconductor devices for integrated circuits

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abstract: 3. Electrons and holes are the major characters in the play and carry opposite charge. Their mass however is altered from the mass of an electron in vacuum. The altered mass is called e ective mass, mn and mp 4. The band model is the tool required for quantitative analysis of semiconductors. From this model one can get the energy gap, E K diagrams allowing the determination of e ective masses, analysis of the energy levels with in the gap and the conduction/valence bands etc
author_names: Chenming Calvin Hu
title: Modern Semiconductor Devices for Integrated Circuits
year: 2009

abstract: In this article a universal system for photoelectric measurements (USPM) is described, with several subsystems allowing comprehensive characterization of various semiconductor devices, primarily MOS (metal oxide semiconductor) structures. MOS structures are fundamental components of all modern integrated circuits and the key parameters of these structures can be determined by several electrical and photoelectric techniques. In particular, photoelectric investigations are very important and useful in the characterization of micro and nanoelectronic semiconductor devices since they offer very accurate and reproducible measurements of important electric parameters, e.g. barrier heights on interfaces of multilayered structures. In the case of integrated circuits with structures of nm aerial dimensions, photoelectric measurements have to be made on test structures with larger aerial dimensions, accompanying the integrated circuits, since the minimum diameter of the light beam used is in the range of micrometers. The USPM system has been designed and built in our laboratory and allows very precise and sensitive measurements to be taken.
author_names: Krzysztof Piskorski

M Niemiec

L Borowicz

Henryk M Przewlocki
title: A measurement system for the photoelectric and electrical characterization of modern semiconductor devices
year: 2017

abstract: Radio frequency integrated circuits (RF ICs) built the core of modern information and communication systems. Graphene based devices like transistors, diodes or varactors have been recognized from the very beginning as promising candidates in future RF ICs, having the potential to significant outperform established devices based on Silicon or III/V semiconductor materials in terms of speed, functionality or flexibility. However, so far the potential of graphene in RF electronics has mainly been demonstrated on a single device level because the realization of more complex integrated RF circuits was limited by a non mature fabrication technology and large variations in the device performances. In this talk I will present the MMIC (monolithic microwave integrated circuit) process for graphene based RF circuits developed at AMO (figure 1) [1,2] and discuss especially the challenges and possible solutions related to device variability and yield. Different RF ICs have been realized so far, which are designed for future WiFi communication systems in 5G and for IoT applications [3] As one example, a double balanced mixer designed for operation from 6 12 GHz has been realized using a graphene based diode ring and metal based passive components (figure 2) This integrated circuit was fabricated on a glass substrate and provides a down conversion loss of only 10dB, which is identical to GaAs based mixers, but achieved with a much more flexible and cheaper production technology. References [1] A Askar et al. Microwave Conference (GeMiC) 2015 German 299 302 (2015) [2] M Shaygan et al, Nanoscale, 9 (2017) 11944. [3] MS Elsayed et al. Nanoscale, 10 (2018) 93.
author_names: Daniel Neumaier
title: Integrated Circuits for RF Communication with Graphene based Devices
year: 2018

abstract: Thermo mechanical stress accumulation in the power electronic integrated circuit (PIC) devices influences their lifetime and reliability. In order to determine both the temperature and the stress accumulation, numerical simulation is a very important tool in the design of PIC devices for quantifying and enhancing their lifetime and reliability. An open source solution integrated in Salome Meca and Code_Aster based on the finite element method (FEM) is used in this paper to analyze the thermo mechanical behavior on a simple metal semiconductor structure, which is typically found in a PIC. The computational time and accuracy of the simulations results is improved by finding the optimal mesh configuration. A convergence study is computed for five different cases by progressively reducing the size of the discretization elements (hence, increasing the number of mesh elements) in the area of interest. The results for an optimal relative error and computational time are compared with the results obtained using the commercial software Comsol. The simulated mechanical stress is compared with similar results reported in literature.
author_names: Adrian Bojita

Alexandru M Avram

Marius Purcar

Calin Munteanu

Vasile Topa
title: Thermo mechanical simulation of the metal semiconductor structures of power integrated circuits
venue: 2017 International Conference on Modern Power Systems (MPS)
year: 2017

abstract: Photonic integrated circuits that are manufactured with mature semiconductor technology hold great promise for realizing scalable quantum technology. Efficient interfaces between quantum emitters and nanophotonic devices are crucial building blocks for such implementations on silicon chips. These interfaces can be realized as nanobeam optical cavities with high quality factors and wavelength scale mode volumes, thus providing enhanced coupling between nanoscale quantum emitters and nanophotonic circuits. Realizing such resonant structures is particularly challenging for the visible wavelength range, where many of the currently considered quantum emitters operate, and if compatibility with modern semiconductor nanofabrication processes is desired. Here we show that photonic crystal nanobeam cavities for the visible spectrum can be designed and fabricated directly on substrate with high quality factors and small mode volumes. We compare designs based on deterministic and mode matching methods and find the latter advantageous for on substrate realizations. Our results pave the way for integrating quantum emitters with nanophotonic circuits for applications in quantum technology.
author_names: Jan Olthaus

Philip P J Schrinner

Doris E Reiter

Carsten Schuck
title: Optimal Photonic Crystal Cavities for Coupling Nanoemitters to Photonic Integrated Circuits
venue: Advanced Quantum Technologies
year: 2019

abstract: Abstract Metal oxide semiconductor field effect transistor (MOSFET) is the main building block in low power and high performance very large scale integration (VLSI) chips for the last few decades. Device scaling is the guiding force toward technological advancements, which allows more devices to be integrated on a single die thereby allowing greater functionality per chip. The ultimate goal of scaling is to build an individual transistor that is smaller, faster, cheaper, and consuming low power. We see an exponential growth in device complexity in today's nanoscaled chip. However, device scaling to deep nanometer regime leads to exponential increase in leakage current and excessive heat generation. Moreover, process variability has caused a serious limitation to further scaling. It is believed that with a mix of chemistry, physics, and engineering, nanoelectronics may provide a solution to increasing fabrication costs and may allow integrated circuits to be scaled beyond the limits of the modern transistor. Carbon nanotube (CNT) and nanowire (NW) based FETs (CNTFET and NWFET) have been analyzed and characterized in the laboratory and also been demonstrated as prototypes. This work first presents, a detailed explanation on chemical bonding and crystalline structures of these new devices and then an extensive simulation and analysis of CNTFET and NWFET devices and compared the results with conventional MOSFET and double gate MOSFET. From this study, it reveals that these new devices have got some excellent properties and favorable characteristics, which will definitely lead the future semiconductor devices in the post silicon era.
author_names: Saurabh Chaudhury

Sanjeet Kumar Sinha
title: Carbon Nanotube and Nanowires for Future Semiconductor Devices Applications
year: 2019

abstract: Introduction. The modern stage of development of electronics is characterized by the widespread use of integrated circuits (IC) Assessment of working conditions in a promising, developing production of electronic components with hygienic positions is an urgent task.The aim of the study is to conduct a hygienic assessment of working conditions of workers in the main professions in the production of IC.Materials and methods. Hygienic research conducted at three modern enterprises for the production of chips and semiconductor devices, included the study of the conditions and nature of work of workers in the main professions. 215 chemical analyses for the content of harmful substances were carried out in order to assess the air environment and 270 measurements of the levels of physical factors at 18 workplaces.Results. Findings of hygienic assessment of working conditions for employees engaged in manufacture of microcircuits: operators of chemical processing, precision photolithography (PPL) diffusion processes, vacuum deposition, and IMC assemblers are reported. Based on the analysis of the technological process and the list of materials used and time study data, the studies of workplace air pollution, sound levels, artificial lighting, microclimate parameters (temperature, humidity, air velocity) working process parameters were carried out. The jobs in which work is characterized by toxic chemicals exposure, precision visual operations using optical instruments during 55% of the shift were singled out. Priority occupational health risk factors for workers employed in modern IMC production and main areas of working environment optimization were revealed.Conclusions. Based on the conducted hygienic studies, musculoskeletal system load combined with visual strain were found to be the priority occupational health risk factors for microcircuit production workers. Manual operations taking up a significant part of the working process and introduction of automated IMC technological processes being insufficient, preventive measures should be aimed at organizing a rational working regime that provides reducing of visual strain and musculoskeletal system load.
author_names: M N Kir'yanova

O L Markova

Evgenia V Ivanova
title: Features of formation of working conditions of workers of the main professions in the production of integrated circuits
venue: Russian Journal of Occupational Health and Industrial Ecology
year: 2019

abstract: The silicon Integrated circuits (ICs) continues to have an unprecedented impact on improving almost every aspect of modern society including communications, military, security, healthcare, energy saving, industrial automation, transport, and entertainment. Over the last four decades, the relentless pursuit of IC device miniaturization for manufacturing high performance and high density IC chips and system on a chip (SoC) led to the creation of Internet and social media. The semiconductor components are used in smart cars, smart homes, smart cities, smart health, smart energy, smart security, smart appliances, and so on. The Internet enables connecting any and every smart devices or "things" creating "Internet of Things" (IoT) or Internet of everything (IoE) And, the IoT connected smart devices constitute a smart environment and integrated ecosystem that can be accessed via personal computers, tablets, and smartphones from anywhere without human interaction. However, the performance of nanoscale MOSFETs in the design and manufacturing of "smart" electronic products necessary to create smart networks or "smart things" to enable smart environments and integrated ecosystems is inadequate due to the fundamental physical limitations such as short channel effects (SCEs) Shrinking conventional bulk MOSFET device dimensions in the decananometer regime degrades device performance including degradation in the subthreshold swing and decrease in device turn on voltage. As a result, the scaled MOSFETs cannot be turned off easily by lowering the gate voltage leading to excessive leakage current. Due to SCEs, the device characteristics become increasingly sensitive to process variation that imposes a serious challenge for continued scaling of bulk MOSFETs for the nanometer technology nodes. In addition, at gate length below 20 nm, the sub surface leakage paths are weakly controlled by the gate irrespective of gate oxide thickness and their potential barriers can be easily lowered by drain bias through the enhanced electric field coupling to the drain. Thus, to surmount the continuous scaling challenges of conventional bulk MOSFET devices new device technologies such as FinFET has emerged as the real alternative to MOSFETs. This tutorial provides the basic features and operating principles of FinFETs required for the understanding of design and manufacturing of advanced ICs at the nanometer nodes for smart electronic products. In addition, this tutorial also discusses the emerging undoped or lightly doped channel MOSFETs with performance comparable to FinFETs for design and manufacturing of smart IC products.
author_names: Samar K Saha
title: TUTORIAL 01: Advanced Silicon Devices for VLSI Circuits and Systems at Nanometer Nodes
venue: 2018 IEEE International Conference on Semiconductor Electronics (ICSE)
year: 2018

abstract: Abstract There had been tremendous growth in the field of Integrated circuits (ICs) in the past fifty years. Scaling laws mandated both lateral and vertical dimensions to be reduced and a steady increase in doping densities. Most of the modern semiconductor devices have invariably heavily doped regions where Fermi Dirac Integrals are required. Several attempts have been devoted to developing analytical approximations for Fermi Dirac Integrals since numerical computations of Fermi Dirac Integrals are difficult to use in semiconductor devices, although there are several highly accurate tabulated functions available. Most of these analytical expressions are not sufficiently suitable to be employed in semiconductor device applications due to their poor accuracy, the requirement of complicated calculations, and difficulties in differentiating and integrating. A new approximation has been developed for the Fermi Dirac integrals of the order 1/2 by using Prony's method and discussed in this paper. The approximation is accurate enough (Mean Absolute Error (MAE) 0.38% and easy enough to be used in semiconductor device equations. The new approximation of Fermi Dirac Integrals is applied to a more generalized Einstein Relation which is an important relation in semiconductor devices.
author_names: Ahmed Alqurashi

Chettypalayam R Selvakumar
title: A new approximation of Fermi Dirac integrals of order 1/2 for degenerate semiconductor devices
year: 2018

abstract: In this paper a review of the design and properties of silicon light emitting devices fabricated in conventional CMOS/BiCMOS IC process technology is given. The performance of both two and three terminal Si LEDs for monolithic integration in optoelectronic systems is described, followed by a discussion of the differences observed between avalanche LED (i.e. two terminal device, diode) and field emission LED (i. e. three terminal device, gate controlled diode)
author_names: Kaikai Xu

Guannpyng Li
title: The Path Forward: Silicon Electro Optical Interface for Modern Complementary Metal Oxide Semiconductor Integrated Circuits (CMOS ICs)
year: 2013