Search query: Mitigation of Sense Amplifier Degradation Using Skewed Design

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abstract: Designers typically add design margins to semiconductor memories to compensate for aging. However, the aging impact increases with technology downscaling, leading to the need for higher margins. This results into a negative impact on area, yield, performance, and power consumption. As an alternative, mitigation schemes can be developed to reduce such impact. This paper proposes a mitigation scheme for the memory's sense amplifier (SA) the scheme is based on creating a skew in the relative strengths of the SA's cross coupled inverters during design. The skew is compensated by aging due to unbalanced workloads. As a result, the impact of aging on the SA is reduced. To validate the mitigation scheme, the degradation of the sense amplifier is analyzed for several workloads. The experimental results show that the proposed mitigation scheme reduces the degradation of the sense amplifier's critical figure of merit, the offset voltage, with up to 26%
author_names: Daniel Kraak

Mottaqiallah Taouil

Said Hamdioui

Pieter Weckx

Stefan Cosemans

Francky Catthoor
title: Mitigation of Sense Amplifier Degradation Using Skewed Design
venue: 2020 Design, Automation Test in Europe Conference Exhibition (DATE)
year: 2020

abstract: To compensate for time zero (due to process variation) and time dependent (due to e.g. Bias Temperature Instability (BTI) variability, designers usually add design margins. Due to technology scaling, these variabilities become worse, leading to the need for bigger design margins. Typically, only worst case scenarios are considered, which will not present the actual workload of the targeted application. Alternatively, mitigation schemes can be used to counteract the variability. This paper presents a run time design for reliability scheme for memory Sense Amplifiers (SAs) SAs are an integral part of any memory system and are very critical for high performance. The proposed scheme mitigates the impact of time dependent variability due to aging by using an on line control circuit to create a balanced workload. The simulation results show that the proposed scheme can reduce the most critical figures of merit, namely the offset voltage shift and the sensing delay of the SA with up to ~40% and ~10% respectively, depending on the stress conditions (temperature, voltage, workload)
author_names: Daniel Kraak

Innocent Okwudili Agbo

Mottaqiallah Taouil

Said Hamdioui

Pieter Weckx

Stefan Cosemans

Francky Catthoor

Wim Dehaene
title: Mitigation of sense amplifier degradation using input switching
venue: Design, Automation Test in Europe Conference Exhibition (DATE) 2017
year: 2017

abstract: Designers typically add design margins to compensate for time zero variability (due to process variation) and time dependent (due to, e.g. bias temperature instability) variability. These variabilities become worse with scaling, which leads to larger design margin requirements. As an alternative, mitigation schemes can be applied to counteract the variability. This paper investigates the impact of aging on the offset voltage of the memory's sense amplifier (SA) For the analysis, the degradation of the SAs in the L1 data and instruction caches of an ARM processor is quantified while using realistic workloads extracted from the SPEC CPU2006 Benchmark suite. Furthermore, the effect of our mitigation scheme, i.e. an online control circuit that balances the SA workload, is analyzed. The simulation results show that the mitigation scheme reduces the offset voltage degradation due to aging with up to 40% for the benchmarks, depending on the stress conditions (temperature, voltage, and workload)
author_names: Daniel Kraak

Mottaqiallah Taouil

Innocent Okwudili Agbo

Said Hamdioui

Pieter Weckx

Stefan Cosemans

Francky Catthoor
title: Impact and Mitigation of Sense Amplifier Aging Degradation Using Realistic Workloads
venue: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
year: 2017

abstract: 1T1R spin transfer torque (STT) MRAM is a promising candidate for next generation high density embedded non volatile memory [1 2] However, 1T1R STT MRAM suffers from limited sensing margin and high write power. As shown in Fig. 30.2.1(a) sense amplifier design is challenging due to the small difference (only 2x) between the high resistance state (RAP) and the low resistance state (RP) as well as RAP degradation with increasing temperature. Moreover, RP and RAP resistance distributions shift with process variation, requiring a read reference (Vref) that tracks process. To improve the sensing margin, several offset cancellation methods have been reported to reduce sense amplifier mismatch [3] However, these methods use multiple capacitors and hence incur significant area overheads. To address this issue, we propose an offset cancelled sense amplifier that uses only a single capacitor to significantly improve the sensing margin by more than 60% A second design challenge for STT MRAM stems from the high current needed to flip a cell during a write operation. For non volatile memory applications with a 10 year retention time requirement, the write current can be as high as several hundred mA. However, as shown in Fig. 30.2.1(b) the required write time varies with the state change required (0 1 or 1 0) process variation, and temperature. As a result, a fixed write time that ensures successful write for all conditions wastes a significant energy for typical or average conditions. We propose an in situ write self termination method to reduce write energy in most scenarios. The sense amplifier is reconfigured to continuously monitor the write operation and automatically shuts off the write drivers when the state transition is detected, without an area or timing penalty. In addition, dual dummy columns are added in each array to provide read Vref tracking of row wise PVT variation. A 1Mb STT MRAM was fabricated in 28nm technology, and achieves a 2.8ns read access time at 25degC and 3.6ns at 120degC, respectively. With in situ self write termination the write power is reduced by 47% with a 20ns write access time at 25degC and by 60% at 120degC.
author_names: Qing Dong

Zhehong Wang

Jongyup Lim

Yiqun Zhang

Yi-Chun Shih

Y D Chih

Tsung-Yung Jonathan Chang

David Blaauw

Dennis Sylvester
title: A 1Mb 28nm STT MRAM with 2.8ns read access time at 1.2V VDD using single cap offset cancelled sense amplifier and in situ self write termination
venue: 2018 IEEE International Solid State Circuits Conference (ISSCC)
year: 2018

abstract: This paper investigates the reliability tolerant design for ultra thin body (UTB) GeOI 6T SRAM cell and sense amplifiers. For UTB GeOI 6T SRAM cells, using high threshold voltage design significantly mitigates the read and hold static noise margin degradations due to NBTI and PBTI. Due to worse PBTI degradations, as stress (aging) time increases, GeOI current and voltage latch sense amplifiers show larger degradation in word line to sense amplifier enable (SAE) delay <inline formula> <tex math notation="LaTeX"\text{T}_{\mathrm{ WS} /tex math>/inline formula> and sense amplifier sensing delay <inline formula> <tex math notation="LaTeX"\text{T}_{\mathrm{ SA} /tex math>/inline formula> compared with the SOI counterparts. Using WL to SAE self timed sensing scheme mitigates the BTI induced delay degradation. A new reliability tolerant sense amplifier with speed up design is proposed for the first time to improve the PBTI dominated sensing delay for UTB GeOI sense amplifier.
author_names: Vita Pi-Ho Hu
title: Reliability Tolerant Design for Ultra Thin Body GeOI 6T SRAM Cell and Sense Amplifier
venue: IEEE Journal of the Electron Devices Society
year: 2017

abstract: Today to compete the race of improvements and advancements of technological mysteries are lasting upon innovative ideas and noble thoughts. The consequences of using normal Master Slave Flip flops in ultra high speed circuits are increase in cycle time, blurredness in clock edge skew, higher crosstalk substrate coupling/power consumption/ expensive packaging including cooling systems and limiting performance. An innovative idea of Sense amplifier based Flip flops (SAFF) has been implemented which can be speedup the processes up to optimum rate (i.e. Shannon Rate) with compensated SNR. To save the Time Element, designed prototype model to be operated, with ultra high speed for error detection and performance evaluation. Referred to authors previous paper, Modeling and design optimization of Latch Circuits using Parametric Timing Analysis, the latch circuits were thoroughly analyzed w.r.t. their operating speed and its effect over various parameters was discussed, in tighter timing constraints needs to concentrate on power dissipation and durability of device. Overlooking of setup and hold times spans, pays a heavy cost of compromise in the circuits with various latch ups inducted during design, testing and quality check phase. In sense amplifierflip flop (SAFF) based structures, delay can be fairly minimized between the latest point of data arrival and output transition using hybrid latch flip flop (HLFF) and semidynamic flip flop (SDFF) SAFF based latch models, consists of the sense amplifier in the first stage and the RS latch in the second stage which are being implemented and simulated by using the Cadence Spectre design tool using 45nm technology. It senses the true and complementary differential inputs and produces monotonous transitions from high to low logic or vice versa outputs for S R Latch following the leading clock edge. The S R latch captures each transition and holds the state until the next leading clock edge arrives, due to this feature; the whole structure becomes a self sustaining flip flop device.
author_names: Akhilesh Tiwari

Shyam Akashe
title: Modeling and designing of Sense Amplifier based Flip Flop using Cadence tool at 45 nm
year: 2017

abstract: This paper describes the design and implementation of an embedded ROM memory along with its sense amplifier. Several applications in machine learning have fixed data to be stored in a memory, which needs to be read out multiple times. Hence a fast, on chip solution is proposed in this technical paper wherein logic transistors are used to design a read only memory with completely zero added process complexity. Several design constraints of sensing the ROM cell have been elaborated to a great extent. Also, a key advantage in the sense amplifier used is the ability to use all transistors from the same process technology. Further, by always fixing a MOS device in saturation and the other MOS device in cut off region, fast sensing is achieved at the sense amplifier output. The layout designed for the sense amplifier is verified to produce a very minimal deviation from the actual schematic simulations, hence suggesting a considerably well designed layout. The operating frequency of the sense amplifier is determined as 12.5 GHz with full swing resolution.
author_names: V Balaji

Ch K S D Ranga

N Shylashree

Nuthakki Praveena
title: Design of a Delta Threshold Voltage Difference based fully Embedded Read Only Memory along with a Skew Sense Amplifier
venue: 2019 4th International Conference on Recent Trends on Electronics, Information, Communication Technology (RTEICT)
year: 2019

abstract: Nowadays, typical (memory) designers add design margins to compensate for uncertainties, however, this may be overestimated leading to yield loss, or underestimated leading to reduced reliability designs. Accurate quantification of all uncertainties is therefore critical to provide high quality and optimal designs. These uncertainties are caused by zero time variability (due to process variability) and by run time variability(due to environmental variabilities such as voltage and temperature, or due to temporal variability such as aging) This paper uses an accurate methodology to predict the impact of both zero and run time variability on the offset voltage of sense amplifiers while considering different workloads and PVT variations for a pre defined failure rate. The results show a marginal impact of environmental run time variability on the offset specification when considering zero time variability only, while this becomes significant (up to 2X) when incorporating aging run time variability. The results can be used to quantify whether the required offset voltage is met or not for the targeted lifetime, hence, enable the designer to take appropriate measures for an efficient and optimized design, depending on the targeted application lifetime.
author_names: Innocent Okwudili Agbo

Mottaqiallah Taouil

Said Hamdioui

Pieter Weckx

Stefan Cosemans

Praveen Raghavan

Francky Catthoor

Wim Dehaene
title: Quantification of Sense Amplifier Offset Voltage Degradation due to Zero and Run Time Variability
venue: 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
year: 2016

abstract: The continuous downscaling of CMOS technology causes increased impact of time zero (due to process variation) and time dependent variability (due to e.g. Bias Temperature Instability) This causes major challenges w.r.t. the device reliability, which is critical for industries, such as the automotive one. This paper uses an accurate method to quantify the impact of time zero and time dependent variability on the offset voltage specification of memory Sense Amplifiers. Furthermore, it presents a run time design for reliability scheme to mitigate the impact of time dependent variability on the offset voltage specification. The simulation results show that the mitigation scheme improves the offset voltage specification up to ~40% compared to the standard design after 10 years of aging.
author_names: Innocent Okwudili Agbo

Mottaqiallah Taouil

Said Hamdioui

Pieter Weckx

Stefan Cosemans

Francky Catthoor

Wim Dehaene
title: On Mitigating Sense Amplifier Offset Voltage Degradation
year: 2016

abstract: This paper presents a high speed and low energy match line (ML) sensing scheme for ternary content addressable memory (TCAM) The proposed sensing scheme employs selective precharge which performs partial comparison on the TCAM words to eliminate most of the mismatched words from further comparison. Use of positive feedback in the sense amplifiers engaged in this phase speeds up search operation and reduces energy consumption. In the next phase, remaining portions of those words which were matched in the first phase are scanned to find the fully matched words. Lower resistance in the charging path of the sense amplifier in the second phase causes fast match detection. The proposed technique is simulated using 130nm 1.2V CMOS logic. Compared to conventional current race (CR) sensing scheme the proposed scheme shows 26.5% speed enhancement and at least 31% energy reduction at the cost of insignificant area overhead and small voltage margin degradation. Unlike many CR type schemes, no analog control voltage has been used in the proposed scheme.
author_names: Syed Iftekhar Ali

M S Islam
title: An Energy Efficient Design of High Speed Ternary CAM Using Match Line Segmentation and Resistive Feedback in Sense Amplifier
venue: J. Comput.
year: 2012