Search query: {CMOS} and Memristor-Based Neural Network Design for Position Detection

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abstract: Most hardware neural networks have a basic competitive learning rule on top of a more involved processing algorithm. This work highlights two basic learning rules/behavior: winner take all (WTA) and spike timing dependent plasticity (STDP) It also gives a design example implementing WTA combined with STDP in a position detector. A complementary metal oxide semiconductor (CMOS) and a memristor MOS technology (MMOST) design simulation results are compared on the bases of power, area, and noise handling capabilities. Design and layout were done in 130 nm IBM process for CMOS, and the HSPICE model files for the process were used to simulate the CMOS part of the MMOST design. CMOS consumes area, 55 W max power, and requires a 3 dB SNR. On the other hand, the MMOST design consumes 15 W max power, and requires a 4.8 dB SNR. There is a potential to improve upon analog computing with the adoption of MMOST designs.
author_names: Idongesit E Ebong

Pinaki Mazumder
title: CMOS and Memristor Based Neural Network Design for Position Detection
venue: Proceedings of the IEEE
year: 2012

abstract: Most neural networks have a basic competitive learning rule on top of a more involved processing algorithm. This work highlights three basic learning rules winner take all (WTA) spike timing dependent plasticity (STDP) and inhibition of return (IOR) It also gives a design example implementing WTA combined with STDP in a position detector. A CMOS and an MMOST (Memristor MOS Technology) design simulation results are compared on the bases of power, area, and noise handling capabilities. Design and layout was done in 130 nm IBM process for CMOS, and the HSPICE model files for the process were used to simulate the CMOS part of the MMOST design. CMOS consumes 2.9x10 4cm2 area, 55 uW max power, and requires a 3 dB SNR. On the other hand, the MMOST design consumes 6x10 5cm2, 15 uW max power, and requires a 4.8 dB SNR.
author_names: Idongesit E Ebong

Pinaki Mazumder
title: Memristor based STDP learning network for position detection
venue: 2010 International Conference on Microelectronics
year: 2010

abstract: Memristor nanodevices have good properties for use as synapses to add dynamic learning to neuromorphic networks implemented in crossbar based CMOS/Nano hybrids. In this paper, we propose and analyze Spike Timing Dependent Plasticity (STDP) rule for memristor crossbar based spiking neuromorphic networks. The learning method is implemented by using CMOS based neurons which generate two part spikes similar to biological Action Potentials (APs) and send them to both forward and backward directions along their axon and dendrites, simultaneously. The local learning method can modify the state of nanodevices with regards to pre and postsynaptic spike timings.
author_names: A Afifi

Ahmad Ayatollahi

Farshid Raissi
title: Implementation of biologically plausible spiking neural network models on the memristor crossbar based CMOS/nano circuits
venue: 2009 European Conference on Circuit Theory and Design
year: 2009

abstract: This article proposes a general approach to the simulation and design of a multilayer perceptron (MLP) network on the basis of cross bar arrays of metal oxide memristive devices. The proposed approach uses the ANNM theory, tolerance theory, simulation methodology and experiment design. The tolerances analysis and synthesis process is performed for the ANNM hardware implementation on the basis of two arrays of memristive microdevices in the original 16x16 cross bar topology being a component of bidirectional adaptive neural interface for automatic registration and stimulation of bioelectrical activity of a living neuronal culture used in robotics control system. The ANNM is trained for solving a nonlinear classification problem of stable information characteristics registered in the culture grown on a multi electrode array. Memristive devices are fabricated on the basis of a newly engineered Au/Ta/ZrO2(Y)/Ta2O5/TiN/Ti multilayer structure, which contains self organized interface oxide layers, nanocrystals and is specially developed to obtain robust resistive switching with low variation of parameters. An array of memristive devices is mounted into a standard metal ceramic package and can be easily integrated into the neurointerface circuit. Memristive devices demonstrate bipolar switching of anionic type between the high resistance state and low resistance state and can be programmed to set the intermediate resistive states with a desired accuracy. The ANNM tuning, testing and control are implemented by the FPGA based control subsystem. All developed models and algorithms are implemented as Python based software.
author_names: Sergey Shchanikov

Anton Zuev

Ilya Bordanov

Sergey Danilin

Dmitry S Korolev

Alexey Belov

Yana Pigareva

Alexey S Pimashkin

Alexey N Mikhaylov

Victor B Kazantsev
title: Design and Simulation of Memristor Based Artificial Neural Network for Bidirectional Adaptive Neural Interface
venue: ArXiv
year: 2020

abstract: A radial basis function (RBF) neural network control algorithm can effectively improve the robotic manipulators' performance against a large amount of uncertainty. The adaptive law can be derived by using the Lyapunov method so that the stability of robotic manipulator control system and the weight self adaptive convergence of RBF neural networks will be guaranteed. Meanwhile, system fluctuations and even overshot phenomenon under every start up process, which are caused by the system's convergence from the given nonoptimal initial weight value to the optimal weight value, can be avoided by using memristors to remember the optimal weight after the system's first operation. According to the above analysis, this correspondence paper designs a kind of RBF neural network control algorithm based on spintronic memristors, and then analyzes its theoretical derivation process and core design idea. Finally, the system simulation model, which uses a two link robotic manipulator as control object, is built to prove the algorithm's validity and feasibility. Simulation results show that the proposed algorithm can satisfy the effect of presupposition.
author_names: Tianshu Li

Shukai Duan

Jun Liu

Lidan Wang

Tingwen Huang
title: A Spintronic Memristor Based Neural Network With Radial Basis Function for Robotic Manipulator Control Implementation
venue: IEEE Transactions on Systems, Man, and Cybernetics: Systems
year: 2016

abstract: This paper describes a simulated memristor based neuromorphic system that can be used for ex situ training of a multi layer perceptron algorithm. The presented programming technique can be used to map the weights required of a neural algorithm directly onto the grid of resistances in a memristor crossbar. Using this weight to crossbar mapping approach along with the dot product calculation circuit, neural algorithms can be easily implemented using this system. To show the effectiveness of this circuit, a Multilayer Perceptron is trained to perform Sobel edge detection. Following these simulations, an analysis was presented that shows how memristor programming accuracy and network size are related to output error; the results show that network size can be increased to reduce testing error. In some cases, the memristors in the circuit may be capable of operating with at lower precision if the network size is increased. This means that less precise (or lower resolution) memristor devices may be used to implement the proposed system. Furthermore, a power, timing, and energy analysis shows that this circuit has a computation throughput that allows it to process 4K UHD video in real time at approximately 337mW.
author_names: Chris Yakopcic

B Rasitha Fernando

Tarek M Taha
title: Design Space Evaluation of a Memristor Crossbar Based Multilayer Perceptron for Image Processing
venue: 2019 International Joint Conference on Neural Networks (IJCNN)
year: 2019

abstract: Back propagation (BP) based on stochastic gradient descent is the prevailing method to train multilayer neural networks (MNNs) with hidden layers. However, the existence of the physical separation between memory arrays and arithmetic module makes it inefficient and ineffective to implement BP in conventional digital hardware. Although CMOS may alleviate some problems of the hardware implementation of MNNs, synapses based on CMOS cost too much power and areas in very large scale integrated circuits. As a novel device, memristor shows promises to overcome this shortcoming due to its ability to closely integrate processing and memory. This paper proposes a novel circuit for implementing a synapse based on a memristor and two MOSFET tansistors (p type and n type) Compared with a CMOS only circuit, the proposed one reduced the area consumption by 92% 98% In addition, we develop a fuzzy method for the adjustment of the learning rates of MNNs, which increases the learning accuracy by 2% 3% compared with a constant learning rate. Meanwhile, the fuzzy adjustment method is robust and insensitive to parameter changes due to the approximate reasoning. Furthermore, the proposed methods can be extended to memristor based multilayer convolutional neural network for complex tasks. The novel architecture behaves in a human liking thinking process.
author_names: Shiping Wen

Shuixin Xiao

Yin Yang

Zheng Yan

Zhigang Zeng

Tingwen Huang
title: Adjusting Learning Rate of Memristor Based Multilayer Neural Networks via Fuzzy Method
venue: IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
year: 2019

abstract: In this paper, a general framework named Filippov framework and some new analytic techniques are presented for dealing with the exponential synchronization of memristor based neural network system with time varying delay. Several new sufficient conditions are established to guarantee two different types of exponential synchronization of the coupled networks based on master slave (drive response) concept and discontinuous state feedback controller. In addition, we also provide an estimation of the exponential synchronization rate which depends on the time delay and system parameters. These conditions are good improvement and extension of the existing works on synchronization control of memristive or switching networks. Finally, the validity of our method and theoretical results is demonstrated by concrete examples with numerical simulations. HighlightsWe analyze the exponential synchronization of the memristor based networks.We present the Filippov framework and some new analytic techniques.We provide an estimation of the exponential synchronization rate.
author_names: Zuowei Cai

Lihong Huang

Lingling Zhang
title: New conditions on synchronization of memristor based neural networks via differential inclusions
venue: Neurocomputing
year: 2016

abstract: Finite time stability of a class of fractional order complex valued memristor based neural networks with both leakage and time varying delays is investigated in this paper. By employing the set valued map and differential inclusions, the solutions of memristor based systems are intended in Filippovs sense. Via using Hlder inequality, GronwallBellman inequality and inequality scaling skills, sufficient conditions to guarantee the stability of the system are derived when 0<<12 and 121, respectively. Finally, two numerical examples are designed to illustrate the validity and feasibility of the obtained results.
author_names: Limin Wang

Qiankun Song

Yurong Liu

Zhenjiang Zhao

Fuad E Alsaadi
title: Finite time stability analysis of fractional order complex valued memristor based neural networks with both leakage and time varying delays
venue: Neurocomputing
year: 2017

abstract: Recently Resistive RAM (RRAM) crossbar has been used in the design of the accelerator of convolutional neural networks (CNNs) to solve the memory wall issue. However, the intensive multiply accumulate computations (MACs) executed at the crossbars during the inference phase are still the bottleneck for the further improvement of energy efficiency and throughput. In this work, we explore several methods to reduce the computations for the RRAM based CNN accelerators. First, the output sparsity resulting from the widely employed Rectified Linear Unit is exploited, and a significant portion of computations are bypassed through an early detection of the negative output activations. Second, an adaptive approximation is proposed to terminate the MAC early when the sum of the partial results of the remaining computations is considered to be within a certain range of the intermediate accumulated result and thus has an insignificant contribution to the inference. In order to determine these redundant computations, a novel runtime estimation on the maximum and minimum values of each output activation is developed and used during the MAC operation. Experimental results show that around 70% of the computations can be reduced during the inference with a negligible accuracy loss smaller than 0.2% As a result, the energy efficiency and the throughput are improved by over 2.9 and 2.8 times, respectively, compared with the state of the art RRAM based accelerators.
author_names: Xizi Chen

Jingyang Zhu

Jingbo Jiang

Chi-Ying Tsui
title: CompRRAE: RRAM based convolutional neural network accelerator with reduced computations through a runtime activation estimation
venue: ASP DAC
year: 2019