US9978652B2 - Method of semiconductor fabrication with height control through active region profile - Google Patents
Method of semiconductor fabrication with height control through active region profile Download PDF
US9978652B2
US9978652B2 US15/612,627 US201715612627A US9978652B2 US 9978652 B2 US9978652 B2 US 9978652B2 US 201715612627 A US201715612627 A US 201715612627A US 9978652 B2 US9978652 B2 US 9978652B2
US15/612,627
US20170309526A1 (en
Yi-Cheng Chao
Jung-Jui Li
2015-02-13 Priority to US201562116257P priority Critical
2015-12-18 Priority to US14/975,525 priority patent/US9673112B2/en
2017-06-02 Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
2017-06-02 Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. reassignment TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHANG, CHE-CHENG, CHAO, YI-CHENG, LI, JUNG-JUI, WU, PO-CHI
2017-06-02 Priority to US15/612,627 priority patent/US9978652B2/en
2017-10-26 Publication of US20170309526A1 publication Critical patent/US20170309526A1/en
2018-05-22 Publication of US9978652B2 publication Critical patent/US9978652B2/en
A method includes forming trenches on a semiconductor substrate, thereby defining regions for forming semiconductor devices; extracting a profile of the regions; determining an etch recipe based on at least the profile of the regions; filling in the trenches with a dielectric material; and performing an etching process to the dielectric material using the etch recipe.
This is a continuation of U.S. application Ser. No. 14/975,525, filed Dec. 18, 2015, now issued U.S. Pat. No. 9,673,112, which claims priority to U.S. Provisional Patent Application Ser. No. 62/116,257, filed Feb. 13, 2015, the entire disclosure of which is hereby incorporated herein by reference.
In advanced technology nodes of integrated circuit industry, the critical dimensions of semiconductor devices become smaller and smaller. Various new compositions and structures are adopted. For examples, a high k dielectric material and metal are used to form a gate stack of a field-effect transistor (FET) such as a metal-oxide-semiconductor field-effect transistor (MOSFET). Three dimensional (3D) fin field effect transistors (FINFETs) are also used. However, in the FINFETs, the fin active regions are extruded above the semiconductor substrate. It is challenging to control the height of the fin active regions uniformly from wafer to wafer, lot to lot, product to product. Accordingly, the circuit performance and quality are impacted. For example, in existing methods to form the metal gate stack, metal gates are formed in a gate-replacement process that removes dummy gates and fills in the gate trenches with gate materials. Due to high packing density and small feature sizes, it is challenging to achieve proper gap filling and profile control, especially for the FINFETs.
Therefore, a method and system to form integrated circuits of FINFETs are needed to address the issues identified above.
FIG. 1 is a flowchart of a method making a semiconductor structure, constructed in accordance with some embodiments.
FIGS. 2, 3, 4, 5, 6, 7, 8, and 15 are sectional views of a semiconductor structure at various fabrication stages, constructed in accordance with some embodiments.
FIGS. 9 and 10 are sectional views of a semiconductor structure, constructed in accordance with some embodiments.
FIGS. 11, 12, 13, and 14 are sectional views of a semiconductor structure at various fabrication stages, constructed in accordance with some other embodiments.
FIGS. 16, 17, 18, and 19 are sectional views of a semiconductor structure at various fabrication stages, constructed in accordance with some embodiments.
FIG. 20 is a sectional view of a gate stack of the semiconductor structure in FIG. 19, constructed in accordance with some embodiments.
FIG. 21 is a top view of the semiconductor structure in FIG. 19, constructed in accordance with some embodiments.
FIG. 22 is a sectional view of the semiconductor structure of FIG. 21, constructed in accordance with some embodiments.
FIG. 23 is a schematic view of an exemplary embodiment of a system in which the method of FIG. 1 is implemented.
FIG. 1 is a flowchart of a method 100 making a semiconductor structure having fin active regions constructed according to aspects of the present disclosure. FIGS. 2-8 and 15 are sectional views of a semiconductor structure 200 at various fabrication stages in accordance with some embodiments. FIGS. 9 and 10 are sectional views of a semiconductor structure constructed in accordance with various examples. The semiconductor structure 200 and the method 100 of making the same are collectively described.
Referring to FIGS. 1 and 2, the method 100 begins by providing a semiconductor substrate 210. The semiconductor substrate 210 includes silicon. Alternatively, the substrate 210 includes germanium or silicon germanium. In other embodiments, the substrate 210 may use another semiconductor material such as diamond, silicon carbide, gallium arsenic, GaAsP, AlInAs, AlGaAs, GaInP, or other proper combination thereof.
The method 100 proceeds to an operation 110 by forming one or more trenches in the semiconductor substrate 210. In some embodiments, the formation of trenches includes forming an etch mask 220 that defines areas for fin active regions, as illustrated as FIG. 3; and further includes performing an etching process to the semiconductor substrate 210 through the openings of the etch mask 220, thereby transferring a pattern from the etch mask 220 to the semiconductor substrate 210, as illustrated in FIG. 4. In some embodiments, the etch mask 220 is a hard mask effectively resists an etching process. The hard mask includes one or more dielectric material layer. In some examples, the hard mask includes silicon oxide, silicon nitride, silicon carbide or silicon oxynitride. In one example, the hard mask includes a silicon oxide layer and a silicon nitride layer formed on the silicon oxide layer. The formation of the hard mask includes deposition and patterning. For example, the deposition of the hard mask includes forming a silicon oxide layer by a thermal oxidation process and forming a silicon nitride layer by a chemical vapor deposition (CVD) process. The patterning of the hard mask includes forming a patterned photoresist layer on the hard mask, etching the hard mask through the openings of the patterned photoresist layer, and stripping the photoresist layer. The patterned photoresist is formed by a procedure that includes photoresist coating, soft baking, mask aligning, pattern exposing, post-exposure baking, photoresist developing, and hard baking, according to some embodiments. The patterned photoresist layer may also be formed or replaced by other suitable methods such as maskless photolithography, electron-beam writing, ion-beam writing, and molecular imprint. In other embodiments, the etch mask 220 is a soft mask, such as the patterned photoresist layer, that is able to effectively resist the etching process applied to the semiconductor substrate 210.
The operation 110 includes an etching process applied to the semiconductor substrate 210 through the openings of the etch mask 220, thereby forming one or trenches 225 and fin active regions 230, as illustrated in FIG. 4. The fin active regions 230 are protruded out and provide 3D active features. The etching process applied to the semiconductor substrate 210 may include dry etch, wet etch or a combination thereof. In some embodiments, a wet etching process is applied to the silicon substrate with an etchant that includes KOH solution. In some embodiments, a dry etching process is applied to the silicon substrate with an etchant that includes a fluorine-containing gas, a chlorine-containing gas, or a combination thereof, such as CF4, SF6, NF3, or C12. In some embodiments, the etch mask 220 is removed at this present fabrication stage after the formation of the trenches 225, such as by an etching process.
FIG. 5 is a sectional view of the semiconductor structure 200, in portion, constructed in accordance with some embodiments. Referring to FIGS. 1 and 5, the method 100 includes an operation 120 extracting the profile of the fin active regions 230, or particularly extracting profile parameters of the fin active regions 230. In some embodiments, the profile parameters of the fin active regions 230 include a sidewall angle (SWA) of the fin active regions 230. In some embodiments, the profile parameters of the fin active regions 230 include SWA and other parameters, such as the horizontal trench dimension spanning between the adjacent fin active regions 230. In some embodiments, the fin active regions may have more complicated profile and may need more profile parameters.
The operation 120 includes a measuring process to extract the profile of the fin active regions 230 using suitable metrology technology and metrology tool. In some embodiments, the profile of the fin active regions 230 is measured by an optical critical dimension (OCD) metrology tool. The OCD technology is a critical dimension measurement technology used to precisely determine the dimensions (such as width, height or sidewall angle) of a circuit feature on the semiconductor wafer. The OCD technology combines non-contact optical technology with powerful data analysis software to provide highly accurate measurement results for line width, height and sidewall angles. This technology is available in both standalone and integrated platforms. In furtherance of the embodiments, a scatterometry-based optical critical dimension metrology (OCD) is used to measure the profile of the fin active regions 230, with the benefit that it provides a nearly non-demolition measurement to the integrated circuit structure. Furthermore, OCD is impervious to the edge roughness of the fin active regions 230. In some other embodiments, other metrology tools, such as scanning electron microscope (SEM), may be additionally or alternatively used to extract the profile of the fin active regions 230.
Due to the sidewall angle, the horizontal dimension of the fin active regions 230 is different when measured from different level. As illustrated in FIG. 5, the width of the fin active region 230, measured at the height H1 from the top surface of the fin active region 230, is W1. The width of the fin active region 230, measured at the height H2 from the top surface of the fin active regions 230, is W2. When H2 is greater than H1, usually W2 is greater than W1. The parameter SWA is related to those dimensions by a formula, such as SWA=(H2−H1)/(W2−W1). When the profile of the fin active regions 230 is more complicated (such as curved sidewalls), the operation 120 may include extracting additional data or full profile if necessary. In some examples, the operation 120 includes measurement and data analysis such that proper parameter (such as SWA) is obtained. The profile of the fin active region 230 is used to determine the etch process at a later fabrication stage, the proper parameters of the profile of a fin active region are those relevant to the etch process.
In some embodiments, a plurality of fin active regions is measured for respective profiles. In this case, the profile is averaged over the plurality of fin active regions. For example, various fin active regions at different locations (such as wafer edges and wafer center) of the semiconductor substrate 210 are measured by OCD for respective SWAs. Then, an averaging process is applied to the SWAs to determine an average SWA of the semiconductor substrate 210. In some other embodiments, the average SWA may be an average SWA over a plurality of wafers in a batch, such as in a production lot.
Referring to FIG. 1, the method 100 also includes an operation 130 by determining an etch dosage for a subsequent etching process, which is implemented at a later stage and will be described later. The etch dosage is a parameter related to the etching process. For example, the etch dosage may be defined as the product of the etch strength and the etch duration. In some embodiments, when the etchant and etching condition (such as substrate temperature) are given, the etch dosage is determined by the etching duration. In this case, when the etch dosage is doubled, the etching duration is doubled.
In the operation 130, the etch dosage is determined according to the extracted profile of the fin active regions 230. In a particular example, the etch dosage is determined according to the SWA of the fin active regions 230. When SWA varies, the etch dosage is also adjusted accordingly such that the desired height of the fin active region 230 remains unchanged. Furthermore, the etch dosage is determined according to the extracted profile of the fin active regions 230 and the desired height of the fin active regions 230. The operation 130 provides a mechanism to tune/adjust the etch dosage as a function of the fin profile (e.g., SWA) such that the height of the fin active regions 230 remains substantially the same, from wafer to wafer and lot to lot. In some embodiments, the operation 130 includes determining the etch dosage by using a formula that associate the etch dosage to one or more parameter of the profile of the fin active regions. In some embodiments, the operation 130 includes determining the etch dosage by using a lookup table that associate the etch dosage to one or more parameter of the profile of the fin active regions. The lookup table may be created and updated according to the historic fabrication data. In some other embodiments, the operation 130 includes adjusting the etch dosage according to the variation of the profile of the fin active regions, either through a lookup table or a formula. The operation 130 will be further described with more details later after the etch process is introduced.
Referring back to FIG. 1, the method 100 proceeds to an operation 140 by filling in the trenches 225 with one or more dielectric material 240, such as silicon oxide, silicon nitride, silicon oxynitride, low k dielectric material, other suitable dielectric material or combinations thereof. The filled trench may have a multi-layer structure. In one example, the materials filling the trenches include a liner layer and another dielectric material that forms on the liner layer.
In some embodiments, the filling of the dielectric material 240 in the operation 140 includes deposition 150 (as illustrated in FIG. 6) and polishing 160 (as illustrated in FIG. 7). In some examples, the deposition 150 of the dielectric material 240 to the trenches 225 includes forming a thermal oxide liner layer and thereafter another dielectric material, such as silicon oxide by chemical vapor deposition (CVD), such as high density plasma CVD (HDPCVD) with both deposition and etching effects for better gap filling result. After the deposition 150, the dielectric material 240 is filled in the trenches 225 and may also be excessively formed on the fin active regions 230. Alternatively, the operation 150 may alternatively include other technique to form the dielectric material 240 in the trenches 225. For example, a silicon oxide may be formed in the trenches 225 by spin-on coating a chemical solution and curing the solution to form spin-on glass or polymer dielectric material.
In some examples, the polishing 160 includes a chemical mechanical polishing (CMP) process applied to the semiconductor substrate 210 to remove the excessive dielectric material 240 and to globally planarize the top surface of the semiconductor substrate 210, resulting in the isolation features formed between the fin active regions 230. In some examples, the operation 160 may alternatively include an etch-back process that removes both the dielectric material 240 and the fin active regions 230 at a substantially same rate.
Referring to FIGS. 1 and 8, the method 100 proceeds to an operation 170 by performing an etching process to the semiconductor structure 200 to selectively etch the dielectric material 240 and recess the dielectric material 240, thereby forming shallow trench isolation (STI) features 245 and defining the fin active regions 230 with a certain height H. The etching process is designed to have the etch dosage determined at the operation 130. Particularly, the etch dosage is determined or adjusted according to the profile of the fin active regions 230, in order to achieve a uniform height of the fin active regions 230 from wafer to wafer and from lot to lot. Particularly, the etch dosage is determined or adjusted according to one or more profile parameters extracted from the profile of the fin active regions 240. In some examples, the profile parameters include sidewall angle. In other examples, the profile parameters include sidewall angle and the dimension of the trenches 225. In various embodiments, the etch process includes wet etch, dry etch, or a combination designed to selectively etch the dielectric material 240. For example, when the dielectric material 240 includes silicon oxide, the etch process may include a wet etch with etchant having diluted hydrofluoric acid (DHF).
The height H of the fin active regions 230 is defined in the specification of the corresponding product. When the variation of the height H is beyond a tolerable range defined by the specification, the performance of the corresponding circuit in the semiconductor structure 200 is substantially degraded. In the advanced technology nodes with smaller feature sizes, the controlling of the height H of the fin active regions is more challenging. Since the uniform fin height directly impacts to the device performance and reliability, especially for 3D structure with FINFETs and advanced technologies with much smaller feature sizes. The disclosed method provides an approach to dynamically tune/adjust the etch dosage according to the profile of the active regions 230, which effectively reduces the variation of the height of the fin active regions. The etch dosage is defined in the recipe of the etch process. In some embodiments, the etch dosage is defined by the etching duration when other parameters (such as etching chemical and the temperature of the etchant) of the etching process are given. Its mechanism is further explained below.
Through our experiments, it is found that the etch thickness is impacted by an etch volume (the volume of the dielectric material to be removed), which is referred to as a etch volume effect. For example, the removed volume of the dielectric material 240 in a given area is proportional to the chemical supply of the etchant, and therefore is proportional to the etch dosage.
FIGS. 9 and 10 illustrate two semiconductor structures substantially similar but having fin active regions with different profiles, particularly with different SWAs. The fin active regions in FIG. 8 have a first SWA and the fin active regions in FIG. 9 have a second SWA different from the first SWA. By applying a same etching process with a same etch dosage, the thicknesses of the removed portions of the dielectric material are different, such as T1 and T2, respectively, as illustrated in FIGS. 9 and 10. As the first SWA is greater, the first etched dielectric thickness T1 is less. The etching process is impacted by the horizontal trench dimension (such as the dimension CD1 that spanning between two adjacent fin active regions, as illustrated in FIG. 9 or CD2 in FIG. 10) since it determines the chemical supply during the etching process. The etching process is also related to the SWA since it determines how much amount of the dielectric material to be removed in order to reach a certain recessing depth. By the same etching process with a same etch dosage, a first volume V1 of the dielectric material 240 is removed in the semiconductor structure of FIG. 8 and a second volume V2 of the dielectric material 240 is removed in the semiconductor structure of FIG. 9. When the CD1 and CD2 are same, the chemical supplies are same. In this case, V1 is substantially equal to V2. Accordingly, the second thickness T2 is different from the first thickness T1 since the second SWA is different from the first SWA. In this particular example, the second thickness T2 is greater than the first thickness T1 since the second SWA is less than the first sidewall angle.
With consideration of the etch volume effect, the operations 120 extracts the profile of the fin active regions 230 and the operation 130 determines the etch dosage according to the profile of the fin active regions 230 and further according to the desired fin height H such that the fin height is substantially same from wafer to wafer, and from a lot to a lot. Even the previous processes (such as operation 110) may introduce variations, causing the profile of the fin active regions 230 different, the variation of the fin height is eliminated or minimized by implementing the operations 120, 130 and 150.
In various embodiments, the operations 130 may be implemented differently. For example, a lookup table is built up based on historic data to pair etch dosage to SWA. When SWA is extracted by the operation 120, the etch dosage is determined according to the SWA using the saved lookup table. In another example, a baseline etch dosage is determined according to a baseline SWA. When the extracted SWA is changed, a relative change of the etch dosage is determined according to a formula (a linear formula or a non-linear formula, depending on the complexity of the profile and the characteristic of the etch process).
In another example, the variation of the etch dosage is proportional to the variation of SWA in a small range. Therefore, the ratio of the dosage variation to the SWA variation is a constant for the given etch apparatus and the given etch process. The historic manufacturing data associated with the etch apparatus and the etch process are used to determine the ratio. Thus, the operation 130 includes determining the dosage change according to the SWA change using the determined ratio. The ratio may be adjusted according to the new manufacturing data, thus catching the shifting of the etch process and other associated shifting.
The present method 100 may include other alternatives. For example, the etch mask 220 may be removed by an etching process prior to the CMP process, be removed by the CMP process, or remain during the CMP process as a polishing mask. In the last case, the etch mask 220 may be removed by an etching process after the CMP process. In some embodiments illustrated in FIGS. 3-7, the etch mask 220 is removed prior to the operation 140.
In other embodiments as illustrated in FIGS. 11-15, the etch mask 220 remains after the CMP process. Particularly, after the operation 110, the trenches 225 are formed, the etch mask 220 remains on the top of the fin active regions 230, as illustrated in FIG. 11. In the operation 150, the dielectric material 240 is deposited in the trenches 25 and may be deposited on the etch mask 220 as well, as illustrated in FIG. 12. In operation 160, a CMP process is applied to the dielectric material 240 to remove the excessive portion above the etch mask 220. The CMP process may stop on the etch mask 220 using the etch mask 220 as a polishing stop layer, as illustrated in FIG. 13. By the approach, the thickness of the dielectric material 240 is better controlled. In the operation 170, the etch process recesses the dielectric material 240, thereby forming the shallow trench isolation features 245, as illustrated in FIG. 14. During the etch process, the etch mask 220 remains on the fin active regions 230 and further function as a protection layer to protect the fin active regions 230 from the damage by the etch process. Thereafter, the etch mask 220 is removed by a suitable technique, such as a wet etch with an etchant that selectively removes the etch mask 220, resulting in the semiconductor structure 200 illustrated in FIG. 8. The etch process in the operation 170 uses the etch dosage determined by the operation 130. However, in the present embodiment, the etch dosage thus determined is different from the etch dosage of the etch process in FIGS. 7-8 since the thicknesses of the dielectric material 240 after the CMP in operation 160 and before the etch process are different due to the etch mask 220.
Referring to FIG. 1, the method 100 may further include other operations before, during and/or after the above operations. In some embodiments, the method 100 includes an operation 180 to form various devices, such as FETs, on the fin active regions 230. Accordingly, those FETs are referred to as fin field-effect transistor (FINFETs).
In some embodiments, the formation of the FINFETs includes forming gate stacks 260 of the FINFETs, as illustrated in FIG. 15. The gate stacks 260 include a gate dielectric layer and a gate conductive layer formed on the gate dielectric layer. The gate stack may be formed by a gate replacement process. In the gate replacement process, dummy gates are formed, source and drain features are formed thereafter, and then the dummy gates are replaced by metal gate with high k dielectric material and metal.
In some embodiments, the gate dielectric layer includes a high k dielectric material layer formed on the fin active regions 230. The gate dielectric layer may further include an interfacial layer (IL) interposed between the fin active regions 230 and the high k dielectric material layer.
In furtherance of the embodiments, the interfacial layer includes silicon oxide formed by a proper technique, such as an atomic layer deposition (ALD), thermal oxidation or UV-Ozone Oxidation. The high-k dielectric layer includes a dielectric material having the dielectric constant higher than that of thermal silicon oxide, about 3.9. The high k dielectric layer is formed by a suitable process, such as ALD. Other methods to form the high k dielectric material layer include metal organic chemical vapor deposition (MOCVD), physical vapor deposition (PVD), UV-Ozone Oxidation or molecular beam epitaxy (MBE). In one embodiment, the high k dielectric material includes HfO2. Alternatively, the high k dielectric material layer includes metal nitrides, metal silicates or other metal oxides.
The gate conductive layer includes one or more conductive material, such as doped polysilicon, silicide, metal or metal alloy. In some examples, the gate conductive layer includes aluminum, copper, tungsten, or other suitable conductive material. In various examples, the gate conductive layer may include more than conductive layers, such as capping layer, a work function layer with a proper work function tuned for each type (n-type or p-type) FETs and filling metal (such as aluminum).
The gate stack may be formed by a gate replacement process. In the gate replacement process, dummy gates are formed, source and drain features are formed thereafter, and then the dummy gates are replaced by metal gate with high k dielectric material and metal. The formation of the source and drain features may include forming light doped drain (LDD) features and then heavily doped source and drain (S/D). The formation of the source and drain features may involve one or more ion implantation process. In some embodiments, strained source and drain features are formed by etching the source and drain regions to form source and drain recesses, filling the recesses by epitaxailly growing one or more semiconductor material different from that of the semiconductor substrate for straining effect to enhance the carrier mobility in the channel regions. The source and drain features may be in situ doped during the epitaxy growth.
The semiconductor structure 200 having one or more FINFET devices and the operation 180 are further described below in accordance with some embodiments. The semiconductor structure 200 in the following figures may only include a portion (the portion 200A) of FIG. 15 for simplicity. Even though the semiconductor structure 200 in the following figures may illustrates one fin active region 230 and one gate stack, however, it is understood that the semiconductor structure 200 may include a plurality of fin active regions 230 and a plurality of gate stacks in various configurations, such as a plurality of gate stacks configured in parallel and each of the gate stack disposed over the plurality of the fin active regions 230.
After the operation 170, the fin active regions 230 may include semiconductor material same to that of the semiconductor substrate 210, such as silicon. Alternatively, the fin active regions 230 include semiconductor material different from that of the semiconductor substrate 210. The fin active regions 230 may include two or more semiconductor layers of different semiconductor materials configured according to individual applications, such as strained devices, high frequency devices or light-emitting diodes. For example, the fin active regions 230 include a first silicon layer, a silicon germanium layer on the first silicon layer and a second silicon layer on the silicon germanium layer. In another example, the fin active regions 230 include a first silicon germanium layer, a silicon layer on the first silicon germanium layer and a second silicon germanium layer on the silicon layer. In some embodiments, the various semiconductor layers in the fin active regions 230 are formed by selective epitaxy growth (SEG) performed before the operation 110. In other embodiments, the various semiconductor layers in the fin active regions 230 are formed by SEG performed after the operation 160. Particularly, after the operation 160, the fin active regions 230 are recessed and then semiconductor layers are formed by SEG in the recesses. A CMP process may be performed to planarize the top surface.
Referring to FIG. 16, a doped well 270 may be formed in the fin active region 230. In some embodiments, the fin active region 230 is designed to form a FET, such as a p-type FET (pFET) or an n-type FET (nFET). In some examples, a pFET is to be formed on the active region 214, and the doped well 270 includes an n-type dopant, such as phosphorous (P). In some other examples, an nFET is to be formed on the active region 230, and the doped well 270 includes a p-type dopant, such as boron (B), distributed in an active region. The dopant may be introduced the substrate 210 to form the doped well 270 by a suitable doping process, such as one or more ion implantation.
Still referring to FIG. 16, one or more dummy gate stacks 272 are formed on the semiconductor substrate 210. The dummy gate stacks 220 include a gate dielectric layer 274 (such as silicon oxide) and a gate conductive layer 276 (such as polysilicon). The formation of the gate stack 270 includes deposition and patterning. The patterning further includes lithography process and etching. A hard mask layer may be further used to pattern the gate stack 270.
Referring to FIG. 17, source and drain (S/D) features 280 are formed in the fin active region 230. In some embodiments, gate spacer 278 and light doped drain (LDD) features 282 are further formed in the fin active region 230.
The gate spacer 278 includes a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride. The gate spacer 278 is formed on the sidewall of the gate stack 272 by a procedure that includes deposition and etching. The S/D features 280 and LDD features are formed by respective ion implantation. One or more thermal annealing process is followed to activate the doped species. The S/D features 280 and LDD features 282 include a same type conductivity and but different doping concentration. In one procedure, LDD features 282 are formed on the fin active region 230 with a first type of conductivity and a lower doping concentration; the gate spacer 278 is formed on the sidewall of the gate stack 272; and then the S/D features 280 are formed on the fin active region 230 with the first type conductivity and a higher doping concentration.
In some embodiments, the S/D features 280 are formed by epitaxy growth to enhance device performance, such as for strain effect to enhance mobility. In furtherance of the embodiments, the formation of the source and drain 280 includes selectively etching the substrate 210 to form the recesses; and eptaxy growing a semiconductor material in the recesses to form the S/D 280. The recesses may be formed using wet and/or dry etch process to selectively etch the material of the substrate 210. In furtherance of the embodiments, the gate stack 272, the gate spacers 278, and the STI 245 collectively function as an etching hard mask, thereby forming the recesses in the source and drain regions. In some examples, an etchant such as carbon tetrafluoride (CF4), tetramethylammonium hydroxide (THMA), other suitable etchant, or a combination thereof is used to form the recesses.
Thereafter, the recesses are filled with a semiconductor material by epitaxially growing S/D features 280 in crystalline structure. The epitaxy growth may include in-situ doping to form S/D with proper dopant. In some embodiments, the epitaxy growth is a selective deposition process that involves etching during the epitaxy growth, such that the semiconductor material is substantially grown on the semiconductor surfaces in the recess. Particularly, the selective deposition process involves chlorine for etching effect and makes the deposition selective. The selective deposition process is designed and tuned to epitaxially grow such that the S/D 280 formed in the recesses include the semiconductor material in a crystalline structure. The semiconductor material is different from that of the substrate 210. For example, the semiconductor material includes silicon carbide or silicon germanium while the substrate 210 is a silicon substrate. In some embodiments, the semiconductor material is chosen for proper strained effect in the channel region such that the corresponding carrier mobility is increased. In one example, the fin active region 230 is for a pFET, the semiconductor material is silicon germanium doped with boron for S/D 280 while the substrate 210 is a silicon substrate. In another example, the fin active region 230 is for an nFET, the semiconductor material is silicon carbide doped with phosphorous for S/D 280 while the substrate 210 is a silicon substrate.
In yet another embodiment, silicide features may be further formed on the source and drain regions to reduce the contact resistance. The silicide features may be formed by a technique referred to as self-aligned silicide (salicide) including metal deposition (such as nickel deposition) onto a silicon substrate, a thermal anneal to react the metal with silicon to form silicide, and an etch to removed un-reacted metal.
Still referring to FIG. 17, an interlayer dielectric (ILD) 284 is formed on the substrate and the gate stack 272. The ILD 284 is deposited by a proper technique, such as CVD. The ILD 284 includes a dielectric material, such as silicon oxide, low k dielectric material or a combination. Then a chemical mechanical polishing (CMP) process may be applied thereafter to polarize the surface of the ILD 284. In one example, the gate stack is exposed by the CMP process for the subsequent processing steps. In another example that the hard mask to pattern the gate stack 272 is not removed at the previous operation, the CMP removes the hard mask as well. Alternatively the CMP stops on the hard mask and the hard mask is removed thereafter by an etch process.
Referring to FIG. 18, the dummy gate stack 272 is partially or completely removed, resulting in a gate trench 286. The removal of the dummy gate includes one or more etching steps to selectively remove the gate conductive layer 276 or alternatively the gate stack 272 by a suitable etching process, such as one or more wet etch, dry etch or a combination.
Referring to FIG. 19, the various gate material layers are filled in the gate trench 286, forming a metal gate 290 in the gate trench 286. In some embodiments such as in high-k last process, the gate material layers includes a gate dielectric layer 294 and a gate conductive layer (or gate electrode) 296. The gate dielectric layer 294 includes a high-k dielectric material. The gate conductive layer 296 includes metal. In some embodiments, the gate conductive layer 296 include multiple layers, such as a capping layer, a work function metal layer, a blocking layer and a filling metal layer (such as aluminum or tungsten). The gate material layers may further include an interfacial layer 292, such as silicon oxide, interposed between the substrate 210 and the high-k dielectric material. The interfacial layer 292 is a portion of the gate dielectric layer. The various gate material layers are filled in the gate trench 286 by deposition, such as CVD, PVD, plating, ALD or other suitable techniques.
The high-k dielectric layer 294 includes HfO2, or alternatively metal nitrides, metal silicates or other metal oxides. The high k dielectric layer 294 is formed by a suitable process such as ALD. Other methods to form the high k dielectric material layer include MOCVD, PVD, UV-Ozone Oxidation or MBE.
In one embodiment illustrated in FIG. 20 in a sectional view, the gate electrode 256 includes a capping layer 296A, a blocking layer 296B, a work function metal layer 296C, another blocking layer 296D and a filling metal layer 296E. In furtherance of the embodiments, the capping layer 296A includes titanium nitride, tantalum nitride, or other suitable material, formed by a proper deposition technique such as ALD. The blocking layer 296B includes titanium nitride, tantalum nitride, or other suitable material, formed by a proper deposition technique such as ALD.
The work functional metal layer 296C includes a conductive layer of metal or metal alloy with proper work function such that the corresponding FET is enhanced for its device performance. The work function (WF) metal layer 296C is different for a pFET and a nFET, respectively referred to as an n-type WF metal and a p-type WF metal. The choice of the WF metal depends on the FET to be formed on the active region 230. For example, the semiconductor structure 200 includes a first active region 230 for an nFET and another active region for a pFET, and accordingly, the n-type WF metal and the p-type WF metal are respectively formed in the corresponding gate stacks. Particularly, an n-type WF metal is a metal having a first work function such that the threshold voltage of the associated nFET is reduced. The n-type WK metal is close to the silicon conduction band energy (Ec) or lower work function, presenting easier electron escape. For example, the n-type WF metal has a work function of about 4.2 eV or less. A p-type WF metal is a metal having a second work function such that the threshold voltage of the associated pFET is reduced. The p-type WF metal is close to the silicon valence band energy (Ev) or higher work function, presenting strong electron bonding energy to the nuclei. For example, the p-type work function metal has a WF of about 5.2 eV or higher.
The blocking layer 296D includes titanium nitride, tantalum nitride, or other suitable material, formed by a proper deposition technique such as ALD. In various embodiments, the filling metal layer 296E includes aluminum, tungsten or other suitable metal. The filling metal layer 296E is deposited by a suitable technique, such as PVD or plating.
The semiconductor structure 200 in FIG. 19 is further illustrated in FIGS. 21 and 22 as well. FIG. 21 is a top view of the semiconductor structure 200. FIGS. 19 and 22 are sectional views of the semiconductor structure 200 along the dashed lines AA′ and BB′ of FIG. 21, respectively. FIG. 21 illustrates two fin active regions 230 but FIG. 22 only illustrates one fin active region 230 for simplicity. It is understood that semiconductor structure 200 may include two or more fin active regions 230 and two or more gate stacks 290. Various corresponding nFETs, pFETs and other circuit devices are formed on the substrate 210. Particularly, the gate 290 is disposed on the fin active region 230 and the isolation features 245. The first portion of the gate 290 on the fin active region 230 and the second portion of the gate 290 on the isolation features 245 have respective bottom surfaces at different levels (not coplanar in other words).
Referring back to FIG. 1, the method 100 may include other fabrication operations. In some embodiments, an interconnect structure is formed on the substrate and is designed to couple various transistors and other devices to form a functional circuit. The interconnect structure includes various conductive features, such as metal lines for horizontal connections and contacts/vias for vertical connections. The various interconnect features may implement various conductive materials including copper, tungsten and silicide. In one example, a damascene process is used to form copper-based multilayer interconnect structure. In another embodiment, tungsten is used to form tungsten plug in the contact holes.
FIG. 23 illustrates a schematic view of an exemplary embodiment of a manufacturing system 300 to implement the method 100, constructed in accordance with some embodiments. The apparatus 300 includes a manufacturing module 310 coupled with a metrology tool 320 and an etch apparatus 330. The metrology tool 320 may be an OCD tool in one example. The etch apparatus 330 is the tool to perform the etching process of the operation 170. The manufacturing module 310 may be embedded in the etch apparatus 330 or distributed in the semiconductor manufacturing system. The manufacturing module 310 includes software, hardware and database 340. The database 340 is designed to keep and maintain the etch recipes, device specifications (such as fin height), historic fabrication data and/or a lookup table that matches the SWAs and the etch dosages. The manufacturing module 310 further includes a fin profile extraction module (FPE module) 350 designed to extract the profile of the fin active regions 230 (such as SWA). The FPE module 350 is coupled with the metrology tool 320 and extracts the fin profile based on the measurement by the metrology tool (the operation 120). The manufacturing module 310 further includes an etch dosage (ED) module 360 designed to determine the etch dosage of the etching process based on the extracted fin profile. Accordingly, the operation 130 is implemented by the ED module 360. The ED module 360 is coupled with the FPE module 350 for the fin profile and is coupled with the database 340 for various data (such as desired fin height). The ED module 360 is further coupled with the etch apparatus 330 to provide the determined etch dosage to the etch apparatus such that the etching process in the operation 170 is implemented by the etch apparatus 330 with the determined etch dosage, thereby forming the fin active regions 230 with fin height having minimized variation from wafer to wafer and from lot to lot. The system 300 may further include other modules, manufacturing apparatus and metrology tools coupled or integrated together. In various examples, various entities of the system 300 are coupled together through Internet, intranet or other cable/wireless communication means.
The present disclosure provides a semiconductor structure and method making the same. The method includes extracting the profile of the fin active region, determining or adjusting the etch dosage according to the fin active region profile; and performing the etch process to recess the dielectric material using the etch dosage, thereby forming the fin active region and the shallow trench isolation features. The operation to determine the etch dosage may use a lookup table or a formula. Alternatively, a feed-forward loop is implemented such that the variation of the profile from a previous wafer is used to adjust the etch dosage of the subsequent wafer. Some embodiments of the present disclosure offer advantages over existing art, though it is understood that other embodiments may offer different advantages, not all advantages are necessarily discussed herein, and that no particular advantage is required for all embodiments. By using the disclosed method, the variation of the height of the fin active regions in the corresponding semiconductor structure is reduced and the device performance is enhanced. By using the disclosed method, fin height loading can be controlled too be less than 6 nm. The fin height loading is defined as fin height variation due to the fin height loading. For example, one structure has a dense fin pattern with 1000 fin features densely configured in parallel and another structure has an isolated fin pattern with 4 fin features isolated from other fin features. The fin height difference between the dense fin pattern in the first structure and the isolated fin pattern in the second structure is fin height loading. Our experiments consistently show that the fin height loading is: more than 6 nm if using the existing method; and less than 6 nm if using the disclosed method. Particularly, by using the disclosed method, the fin height loading is controlled to a range between 1 nm and 3 nm in some examples. Overall, with the disclosed method, the fin loading effect is substantially reduced in term of fin height variation, which provides significant improvement to the FinFET structure (or other 3D structure), especially for the advanced technology nodes with much smaller feature sizes. The etch process with optimized and dynamically adjusted etch dosage may be applied to other structure with similar profile-sensitive circuit features.
Thus, the present disclosure also provides a method for fabricating an integrated circuit in accordance with some embodiments. The method includes forming a trench on a semiconductor substrate, thereby defining fin active regions; extracting a profile of the fin active regions; determining an etch dosage according to the profile of the fin active regions; filling in the trench with a dielectric material; and performing an etching process to the dielectric material using the etch dosage, thereby recessing the dielectric material and defining a fin height of the fin active regions.
The present disclosure provides a method for fabricating an integrated circuit in accordance with some embodiments. The method includes forming first trenches on a substrate, thereby defining first ridge features on the substrate; measuring a sidewall angle (SWA) of the first ridge features; determining an etch dosage according to the SWA and a desired height; filling in the first trench with a material; and performing an etching process to the material with the etch dosage, thereby recessing the material and defining the first ridge features having the desired height.
The present disclosure provides a system for semiconductor fabrication in accordance with some embodiments. The system includes a metrology tool operable to measure profile of a fin active region formed on a semiconductor substrate; an etch apparatus operable to perform an etching process to the semiconductor substrate; and a manufacturing module coupled with the metrology tool and the etch apparatus, wherein the manufacturing module is designed to determine an etch dosage based on the profile of the fin active region.
Aspects of the present disclosure are best understood from the following above description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. It is also emphasized that the drawings appended illustrate only typical embodiments of this invention and are therefore not to be considered limiting in scope, for the invention may apply equally well to other embodiments.
forming trenches on a semiconductor substrate, thereby defining regions for forming semiconductor devices;
extracting a profile of the regions;
determining an etch recipe based on at least the profile of the regions;
filling in the trenches with a dielectric material; and
performing an etching process to the dielectric material using the etch recipe.
2. The method of claim 1, further comprising, before the forming of the trenches:
forming an etch mask over the semiconductor substrate, wherein the forming of the trenches includes etching the semiconductor substrate through openings of the etch mask.
removing the etch mask before the extracting of the profile.
removing the etch mask after the extracting of the profile.
5. The method of claim 1, wherein the extracting of the profile includes measuring a sidewall angle of the regions.
6. The method of claim 5, wherein the extracting of the profile further includes measuring a dimension of the trenches.
7. The method of claim 1, wherein the extracting of the profile includes:
measuring sidewall angles at different locations of the regions; and
determining an average of the measured sidewall angles.
8. The method of claim 1, wherein the etch recipe is determined based on the profile of the regions and a desired height of the regions after the performing of the etching process.
9. The method of claim 1, further comprising, before the performing of the etching process:
performing a chemical mechanical polishing process or an etch-back process to the dielectric material.
10. The method of claim 1, further comprising, after the performing of the etching process:
forming transistor source and drain features in the regions.
forming an etch mask on a substrate;
etching the substrate through openings of the etch mask, thereby forming trenches and ridges;
determining a profile of the ridges including the etch mask;
determining an etch recipe based on at least the profile;
filling the trenches with one or more dielectric materials; and
recessing the one or more dielectric materials using the etch recipe.
12. The method of claim 11, wherein the filling of the trenches includes depositing the one or more dielectric materials on the etch mask.
applying a chemical mechanical polishing (CMP) process to the one or more dielectric materials, wherein the etch mask serves as a polishing stop for the CMP process.
14. The method of claim 11, wherein the etch mask remains over the ridges during the recessing of the one or more dielectric materials.
15. The method of claim 11, further comprising removing the etch mask after the recessing of the one or more dielectric materials.
forming first ridge features on a substrate;
measuring a sidewall angle (SWA) of the first ridge features;
determining an etch dosage according to the SWA and a desired height of the first ridge features;
depositing a dielectric material over the substrate and covering the first ridge features; and
performing an etching process to the dielectric material with the etch dosage, thereby recessing the dielectric material and defining the first ridge features to have the desired height.
17. The method of claim 16, further comprising measuring a dimension between two first ridge features, wherein the determining of the etch dosage also takes into account the dimension.
18. The method of claim 16, wherein the determining of the etch dosage includes reading a lookup table that associates the etch dosage to the SWA.
19. The method of claim 16, wherein the forming of the first ridge features includes:
forming an etch mask over the substrate; and
etching the substrate through openings of the etch mask with remaining portions of the substrate becoming the first ridge features.
removing the etch mask before the measuring of the SWA.
US15/612,627 2015-02-13 2017-06-02 Method of semiconductor fabrication with height control through active region profile Active US9978652B2 (en)
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US10499876B2 (en) 2017-07-31 2019-12-10 Taiwan Semiconductor Manufacturing Company, Ltd. Test key design to enable X-ray scatterometry measurement
US10170577B1 (en) * 2017-12-04 2019-01-01 International Business Machines Corporation Vertical transport FETs having a gradient threshold voltage
JP2010034467A (en) 2008-07-31 2010-02-12 Renesas Technology Corp Method for manufacturing semiconductor device
TW201110352A (en) 2009-09-01 2011-03-16 Taiwan Semiconductor Mfg Accumulation type FinFET, circuits and fabrication method thereof
TW201427005A (en) 2012-12-28 2014-07-01 Taiwan Semiconductor Mfg Methods for forming FinFETs having multiple threshold voltages
TW201436052A (en) 2013-03-13 2014-09-16 Taiwan Semiconductor Mfg Semiconductor devices and method of manufacture thereof
US20160240444A1 (en) 2015-02-13 2016-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Method of Semiconductor Fabrication with Height Control Through Active Region Profile
KR100978886B1 (en) * 2007-02-13 2010-08-31 가부시키가이샤 히다치 하이테크놀로지즈 Plasma processing method and plasma processing apparatus
US20150014808A1 (en) 2013-07-11 2015-01-15 United Microelectronics Corp. Semiconductor structure and fabrication method thereof
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TW201401513A (en) 2012-05-21 2014-01-01 Globalfoundries Us Inc Methods of forming FinFET devices with alternative channel materials
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US20170309526A1 (en) 2017-10-26
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US8563410B2 (en) 2013-10-22 End-cut first approach for critical dimension control
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Be Prepared for Downed Power Lines, Gas Leaks, More - Government - Manhattan Beach, CA Patch
Be Prepared for Downed Power Lines, Gas Leaks, More
A free public meeting Wednesday night will present vital information on how to handle utilities safely when a disaster strikes.
Ever since two women trying to help a man who crashed his vehicle into a hydrant and knocked down a live electric wire in Valley Village in August were electrocuted and died, George Butts has wanted to deliver safety information to the public.
Thanks to his perseverance and determination, the City of Manhattan Beach and the Manhattan Beach Emergency Response Team Association (MBCERTA), of which Butts is president, are offering a free public meeting on "Utility Safety in the Event of an Emergency" on Wednesday at 7:00 p.m. at the Joslyn Community Center, 1601 Valley Drive, Manhattan Beach.
Representatives from Southern California Edison, the Gas Company and the city's Public Works Department will discuss what to do when coming across downed electrical wires, gas leaks and potential water hazards. These individuals will also be on hand to answer questions so that you can learn how to best protect yourself and others during an emergency or disaster.
Related: Expert Addresses Disaster Preparedness
Related: Will You Be Ready When Disaster Strikes?
Related: Resident Produces Disaster Preparedness Radio Shows
Related: Holiday Spotlight: George Butts
Related: Volunteer Spotlight: George Butts

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Lock NUT SET 1 2 034 Ford Thread Centerline MAG Wheels Washers AMP Dual Size KEY | eBay Skip to main contenteBayShop bycategoryEnter your search keywordAll Categories AdvancedeBay DealsG'day, (Sign in to bid or buy)My eBayExpand My eBaySellExpand SellCommunityExpand CommunityCustomer Support
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Psychobiological Approaches for Anxiety Disorders: Treatment Combination Strategies by Stefan G. Hofmann | NOOK Book (eBook) | Barnes & Noble®
Psychobiological Approaches for Anxiety Disorders presents a comprehensive overview of the latest empirical evidence and research results on combining pharmacological agents and CBT techniques for the treatment of anxiety disorders. The first book to focus on the issue of enhancing CBT with pharmacological agents Features chapters
Psychobiological Approaches for Anxiety Disorders: Treatment Combination Strategies available in
Paperback - $48.09
9781118342473

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In-order delivery of correlated messages in Logic Apps by using Service Bus sessions – Azure Logic Apps
Aprana Seth May 2, 2017 2
Nice post, but could you explain a little more why you are doing this?
It looks to me that we are reading Session based messages and then creating Topic based messages from them. Are the messages being read from and then posted to the same ServiceBus – or are two used?
What is the point, couldn’t the client simply create Topic based messages instead of Session base ones?
Presumably the rest of the solution has an App Logic listening to the topic queue?
Aprana Seth says:
Thanks Jason. The intent is to show how one can use service bus sessions in Logic Apps. We are reading messages from a queue and messages associated with a session are sent to a Topic in this example, although you can process these messages any way you want.

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United States›New York (NY)›Richfield Springs›Richfield Springs Restaurants› New York Pizzeria
40 Reviews #4 of 9 Restaurants in Richfield Springs $
Also show MapSatellite Map updates are paused. Zoom in to see updated info. Reset zoom Updating Map... Return to Map Get directions 37 Main St, Richfield Springs, NY 13439-2527 +1 315-858-0405
12 helpful votes “New York Trip”
I was a bit disappointed with this placed since I visited on the basis of previous Trip Adviser ratings. The Clerk at the counter had no personality at all. He was not helpful with his menu. He was matter of fact. Told us to get our drinks but I had to ask him for the cups to get a drink...
More Helpful? Thank RBailey59 Report mspe1960
This place serves about the best pizza and calzone I have had anywhere. The service is friendly and helpful. The prices are excellent. The tables and decore are very casual and it is a little tired and worn out - that is the only drawback. It is not dirty or run down looking. If you just want to go our...
More Helpful? Thank mspe1960 Report Mackenzie P
1 review “Well Done ”
Helpful? Thank Mackenzie P Report schustergin
2 reviews “Best thing in the area -- not that there is much to choose from”
Helpful? Thank schustergin Report Cathy D
Level Contributor 4 reviews “Don't ask for anything special”
I have a sister who is allergic to cheese, so I asked for an antipasto salad without cheese. They agreed but then had to remake salad because cheese was used. I got the impression that they thought I was lying to them. I will not go there again. They are not sensitive at all.
Helpful? Thank Cathy D Report Theresa M
Level Contributor 8 reviews 1 helpful vote “Miss you NY Pizzeria!”
(Rt 28 runs from NYS thruway exit in...
More Helpful? Thank Theresa M Report robert f
For the first time I can say that I wasn't impressed. My order was wrong both the pizza and the wings. They did take care of it and were apologetic in person but seemed very rude over the phone when I first called about the issue. It's usually a stop I make everytime I'm in town, but definitely won't be...
More Helpful? Thank robert f Report robert f has 2 more reviews of New York Pizzeria “Never disappoints!”
“Annual Stop!!!!”
I order pizza from here and they made it the way I wanted it. The owners here are great people and all the staff is great as well. Pizza here is the BEST around. I DO NOT eat at the chains anymore. Nice thing is that they are open year round including the cold and snowy days when nobody wants...
More Helpful? Thank Trey M Report robert f
69 helpful votes “Never disappoints!”
Helpful? Thank robert f Report robert f has 2 more reviews of New York Pizzeria “Average ”
24 helpful votes “Fresh tasting and ample”
Following a hot day at the beach in Cooperstown, I was hungry, but I knew I didn't want a big meal or anything expensive. I had stopped at NY Pizzeria for the first time in July and enjoyed a meatball tunnel. This time, I ordered a calzone with one free topping (sausagel). The clerk told me it would take 20...
More Helpful? Thank UpstateNYUtica_NY Report Previous
Posting guidelines Get notified about new answers to your questions. Ask Typical questions asked: Do you have gluten-free options? Is there a dress code? Do you allow dogs on the outdoor patio? Near New York Pizzeria Top-rated Attractions Nearby 14 Reviews Petrified Creatures
Browse all attractions Top-rated Restaurants Nearby 40 Reviews Tally-Ho Restaurant

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Stunning! - Review of Constance Aiyana, Pemba Island, Tanzania - TripAdvisor
Stunning! - Constance Aiyana
Booking.com$763
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Review of Constance Aiyana
We stayed at The Aiyana for 2 nights on a recent visit to Pemba. Aiyana is situated in the top North of Pemba on an idyllic white sand beach. After a 1 1/2 hour journey from the airport through the fascinating countryside and unspoiled forest we arrived in paradise! Wow!
The design of Aiyana is unique....very artistic, with rooms and communal areas beautifully and sensitively located to maximise the views of the beach and turquoise blue sea from every room.
Our suite was large and private, with private terraces, indoor and outdoor bathrooms and an comfortable living area.
We went for walks along the beach and swam in the ocean, almost alone but never lonely!
The highlight of our trip was the food....utterly delicious, imaginatively prepared and presented, majoring on seafood. We marvelled at the ability of the Mauritian chef to produce food of such an exceptional quality in such an 'away from it all' location.
Truly relaxing! We'll be backMore
Ask 111MichaelN about Constance Aiyana
Gecko Nature Lodge(Pemba Island)(Great Value!)
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Where to start with describing the Constance Aiyana on Pemba island? It’s a beautiful place, very tranquil as if part of time has stood still. I say part as the Aiyana offers every comfort you can think of when spending a few nights or even, like us lucky ones, 10 nights! The villas are connected to each other, but offer privacy in such a way that you don’t notice this, also because they are set among a very green garden with lots of palm trees. We stayed in an Ambassador Villa/suite which has a ground and 1st floor with two bedrooms and bathrooms. The upstairs bathroom is outside in open air. This particular villa comes with its own private pool. Basically everything is there in the room which you need to enjoy a beach holiday and relax as you hear the waves and see the tides coming in and out. Watching the local fishermen in their traditional boats fishing and as you are laying on your sunbed on the pristine beach or at your own villa you see them bringing in freshly caught fish such as tuna, grouper, dorade, octopus etc. The Constance Aiyana chef then puts this on the menu the same evening! How more fresh can you get it? And food is good, selection is limited, but this is not a negative at all as the Constance Aiyana is located in quite remote part of the island, so bringing in goods/foods is sometimes a challenge. However many of the ingredients grow in the area, so is sourced locally.
If you are looking for something to do next to relaxing and absorbing the terrific sea views there are plenty of activities on the island, such as diving (we haven’t done), snorkeling (directly in front of the resort, but bring some aqua shoes as with low tide its tricky to get into the water), cycling around a part of the island (the reception can lend you bikes), fishing, visiting a sandbank, a native forest etc. etc.
It took us flying from Dar es Salaam via Zanzibar to Pemba 1hour + the journey by car transfer from the local Pemba airport at Chaka Chaka another 1h15min, this drive is terrific, you immediately get a good impression of the island. Very lush green and as you get closer to the Constance Aiyana more and more quiet. The cars used for this trip are mostly Toyota Landcruisers with airconditioning.
There’s so much more to say in a positive way about the Constance Aiyana and the friendly staff, the people from the local village, but I guess you just have to find out yourself!
Ask James290774 about Constance Aiyana
Zico Marlon F
We had many options for our honeymoon but in the end we decided to go to Zanzibar and chose The Aiyana for our special getaway. And we have no regrets!
At first, we were a bit worried as the forecast for early November was showing rain and thunderstorms. In truth, Pemba island is flat and this property is located in the far north so the clouds just pass by real quick.
We were greeted by Syedi (always smiling) at the airport who drove us to and from the hotel. In my opinion the guy is going to be a future president of Zanzibar. He knows everybody!
Once we got to the hotel there was a welcome party on arrival. Katrina, Kosmos and a few staff members introduced themselves and made us feel at home with the sun setting over the horizon. (nice touch)
Our check-in was swift and we were shown to our villa personally by the GM (Katrina)
Where do I begin with this? Our villa was spectacular! The design, the detail, comfort and the privacy. Even 5 star hotels couldn't offer this not even those in the Maldives. The Villa had a huge lounge area, a massive bed, spacious bathroom (with a bath, a shower and an outdoor shower!!). All villas have access to the beach via their own backyards and all have sea views. Housekeeping visits the villa twice daily and they do everything even folded our clothes! The villas have decent WiFi but don't complain if your videos aren't loading, you are here to relax and disconnect.
The bigger suites have two bedrooms and private pool which is ideal for families.
On our first night we were invited for a cocktail party with the management and to get to now the other couples staying in the resort. Including us there were three other couples so it was a cosy evening. We were then escorted to our candle lit dinner tables on the beach.
Now I'm not big on seafood but this holiday was a perfect chance for me to change my diet (and shed some weight lol). The food here is HEAVENLY! Prepared by Chef Geerish and his band of merry men, all the dishes were prepared fresh. For breakfast everything was standard but still good, however lunch and dinner was a surprise. What they would serve you was what they caught from the sea simple as that. You sit down at your table and you open a rolled up script and you will be amazed by the creativity that comes out from that kitchen!
For me, it was seafood all the way! Calamari, Octopus, Cigale we tried everything! and not a single day was the food or dessert the same. So for me the food was on point!
There isn't much to do around the hotel but you come here really to relax. If you feel a bit adventurous then the hotel provides Bicycles. You can go to the other side of the island and to the lighthouse passing through a bit of forest on the way. Although Pemba is completely safe I'd advise taking a guide who can show you around quickly.
The hotel also provides snorkelling equipment and paddle boats if you want to venture around.
They also had a bunch of cool excursions where you go to the sandbank and snorkelling in deeper waters. You can check out a variety of fish amongst the coral and dolphins (not amongst the coral of course) and if you're real lucky you can see humpback whales!
The Hotel also has an amazing spa called Maji (water in Swahili). We were treated to the signature Maji treatment which is a must try! They also offer a spa treatment on one of their satellite islands which I presume would be even more relaxing.
Please be patient with the staff. They do their utmost to make your stay comfortable. Many of them are young but eager to learn so if they don't understand you the first time please explain to them and you won't have to teach them again. They are bunch of enthusiastic individuals and are always smiling.
The owner Mr. Ashok is such a down to earth person who is always around to make you feel comfortable. A truly great person who adds that extra touch to everything the Aiyana does.
Our only regret is not staying here for longer as we bonded with all the hotel staff and they made us feel like family! Cue emotions!
Will definitely be going back and most definitely recommend this non-touristy, charming property!
Special mention to Katrina, Kosmos, Jean-mari, Geerish and the kitchen staff, the bartenders (David, James and Simon), the restaurant staff (Suleiman, Eli, Bella, Naiomi and Joanna), the spa staff (Elisabeth and Happiness), Captain Makame and his crew, our guides Syedi and Abedi and finally the main man Ashok Sungkur. Without you guys this place would be just another hotel...
P.S you are in for a great treat on your last day, I'm not going to spoil it ;)
Ask Zico Marlon F about Constance Aiyana
5 Thank Zico Marlon F
We have been for 5 days in The Aiyana and have enjoyed every minute in this luxurious retreat at the north-western end of Pemba Island.
A multitude of sculptures fit harmoniously into the garden designed with great empathy.
Our bungalow was generously and tastefully designed.
There have been used local woods and materials to combine modern design with African flair and create maximum privacy with a combined living- and sleeping area, a spacious bathroom with bathtub, separate shower and outside shower.
We had the pleasure to meet Mr. Ashok Sungkur, the owner of the hotel and his brother, Mr. Shailesh Sungkur. Mr. Ashok told us that the "Aiyana" is his life's work and really has a lot of heart and soul in it. What we also found very great and convincing is that Mr. Ashok relies on regionalism. Thus, the villas were built with a lot of materials from Pemba and people from Pemba used for the construction.
The same goes on the menu, there is much from the sea and everything farmers grow in the area.
We have visited a lot of hotels all over the world, but The Aiyana is really something special.
In this hotel we felt we were living in an ever blooming garden away from the hustle and bustle of the world
Ask powersensi about Constance Aiyana
Thank powersensi
Paradise, Excellent luxury resort in Africa, made to feel like royalty.
The Aiyana is Paradise on Earth - Jewel of Pemba, in Tanzania. A sanctuary where you recharge the mind and body and you are one with nature.
We have just returned from a perfect 5 nights holiday from the Aiyana resort. From the moment we arrived, until the time we left, we were looked after with love, and care and made to feel like royalty, nothing was too much trouble. We booked a suite and to our delight we were upgraded to the Presidential suite with a good size pool with a spectacular view, of pure white sandy beach with a clear blue sea. As you enter the suite it has a good size hallway with high ceiling, the lounge area is absolutely massive with a comfortable sofa and TV and dining table facing a very secluded peaceful garden and view of the pool and the sea. The bedroom is also large with an amazingly comfortable four poster bed and pillows you sink into all white cotton sheets, very beautiful and stylish - your bed is facing the sea as well. It has a large bathroom with a sunken bath if you want to relax, an inside shower and an outside shower in a beautiful garden. The terrace has table and chairs and sun lounges, with a landscaped garden. I watched Kingfisher birds skimming in the water and catching fish. I was also very lucky to watch a sunbird everyday around the garden of the outside shower. It's pure heaven, full of wildlife. It's definitely the best hotel we have ever stayed at and can't wait to book our next holiday here. We are so happy we found this Gem of a place the Aiyana.
We would highly recommend the Aiyana resort to anyone who enjoy being pampered and enjoy peace and tranquility with a beautiful architecture, beautiful garden surrounded by wildlife, great service, delicious foods. Mr Ashok the owner and his team provide very attentive service and attention to detail. The care and love they show to all their guests is exceptional and it exceeded all our expectations.
We arrived at Pemba airport a short 35 minutes flight from Zanzibar and were picked up by Francis - who gave us a very warm welcome. We were given wet towels to freshen up, fresh fruit skewer and drinks which was exactly what we needed as we had a short delay in Zanzibar and we were a little hungry. The one hour drive through the unspoilt villages was very interesting and gave us a glimpse of how the locals live.
Walking around the hotel we were blown away by the beauty of Aiyana, the energy and love of the people, architecture, art, the rooms are stylishly decorated, beautifully designed landscape garden, delicious food and nature all around us and the pure luxury in Africa. It was a contrast from small villages we drove through to this wonderland resort the Aiyana - you enter into Paradise.
Katrina the operation manager was truly amazing she told us to call her, if we needed anything, they did everything to make our stay very special. We had our own butler who was also amazing - our every needs were met without any problem, nothing was too much trouble.
My husband went on an early morning fishing trip - and amazingly they did not only catch fish , which we had for lunch but they also saw a pod of whales with two babies jumping out of the water playfully and also dolphins following their boat. I was told it's the season for whales and some of the guests who were sunbathing on the beach saw whales in front of the Aiyana beach. Aiyana also is a great place to snorkel lots of beautiful tropical fish
The food at the Aiyana is absolute delicious, all fruit and veg are freshly sourced from the local market, also freshly caught local fish - loved the salad dressing, which had a touch of delicate lemongrass. As a full board resort you get a variety of beautifully presented, delicious meals for breakfast, lunch and dinner. We would like to thank Geerish the chef and his team for preparing all the great food during our stay and for the special Lunch. To top it all up, we had the most memorable meal on the beach, red flower petals strewn pathway, which was painstakingly done for us to walk on to your table, you are made to feel like a prince and princess's. It's perfection and poetry all in one and it's a unique touch of love for their guests. No where in the world to be experienced.
The spa is heavenly, it's set in a beautiful garden with ponds, amazing architecture and it's in harmony with nature, individual separate thatched rooms with white painted walls. They showed me round and it's a great place for weddings as they have a special rooms for the brides to bath. I had a massage on my first day and all the stresses and strain was taken away, thank you for a great experience.
The staffs are so respectful when you walk around they bow and all greet you with a Namaste or Jambo in Swahili.
If you are a wildlife fan and photography then the Aiyana resort is the place to be..I have taken thousands of photographs of the Architecture, amazing garden and the wildlife. I saw Toucans, Sunbirds, Eagles , parrots and many absolutely beautiful birds. I was told they also have velvet monkeys but I did not stay long enough to spot one. I managed to take a bird watching Trip and saw amazing flying foxes hanging upside down on very tall trees, which are covered by these amazing creatures. Their are also lots of other activities available at the resort. The Aiyana is a great place to stay if you want to include a safari holiday as part of your stay.
Finally, in our opinion, the Aiyana's secret ambassador is the never failing Mr Ashok Sungkur. His vision and ethos is always to focus on guests, the integrity of a bound workforce to always do what is right. These values are deep in the heart of Mr Ashok's ethos. We will come back again, until then we hold the memories of the Aiyana family close to our hearts, of happy times spent in a heavenly place. Our thanks goes to all the amazing staffs at the Aiyana.
Room Tip: Presidential suite no 1, secluded garden and terrace with table and chairs, loungers, a large private pool.
Ask Prim M about Constance Aiyana
2 Thank Prim M
Absolutely stunning and even more beautiful than the website!
This property is pure magic. While it is on the opposite end of the island from the airport, the hour-long drive gives you an amazing feel and perspective on just how unspoiled the island really is.
From the moment you arrive, a parade of staff are on hand with cool towels, tea and snacks ... and they are there at every single other day-part to help your stay be the very best it can be.
The property and rooms are stunning ... massive and every single detail has been thought of wherever you go.
The sand is like powdered icing sugar; so soft, you sink down a fair few inches as you walk along it.
All meals are super delicious with high standards in detail, cuisine and big flavour. Ekaterina is amazing and hooked me up with Luca and Mike from Swahili Divers. Did two dives - Coral Gardens is just that ... beats any of the diving I've done in the Caribbean combined.
They also suggested I take a bike ride over to Vumawimbi Beach - again, stunning, stunning, stunning. It was just me and felt super safe and worth the time for sure.
The last night at The Aiyana is super special - I won't give it away but I was so thrilled with the whole night.
I cannot say enough about The Aiyana; it's a must do if you are contemplating island time after a safari or quite frankly, an alternative to the Maldives with more culture given the local villages.
Room Tip: I've heard the Presidential Suite is spectacular!
Ask Charlene P about Constance Aiyana
4 Thank Charlene P


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Stamping With Gwen: Occasions Mini Catalog -- AVAILABLE TODAY
Occasions Mini Catalog -- AVAILABLE TODAY
The Occasions Mini Catalog is available TODAY! So it’s only fitting that today’s card features a couple products from the new Catalog. I used the Tulips Textured Impressions Embossing Folder to add detail to the Baja Breeze portion of my card. Then I used a couple different patterns from the Springtime Vintage Designer Series Paper. This paper is really beautiful. I’ll be using lots of it. CLICK HERE to view the Occasions Mini Catalog online.
QUICK TIP: I originally saw this idea for repeating the tulip border impression on Darlene McCallum's blog. My tip is to emboss the bottom row first. Then insert the cardstock back in the embossing folder so the edge of the folder is just above the first embossed impression. If the initial impression is in the folder, the next roll through the Big Shot will flatten out that impression.
Card Recipe: Stamps- Just Believe (sentiment); Paper- Springtime Vintage DSP, Crumb Cake, Baja Breeze, Very Vanilla, Not Quite Navy; Ink- Not Quite Navy; Accessories- Decorative Label Punch, Seam Binding, Large Oval Punch, Scallop Trim Border Punch, Tulip Impressions EF, Dimensionals
Posted by Gwen at 9:22 AM
Labels: Just Believe, Thank You

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Tina Says...: Waiting on Wednesday: If We Had Known
Waiting on Wednesday: If We Had Known
This week's pick: If We Had Known by Elise Juska
Due out: April 17, 2018
After a shooting in her local mall in rural Maine, English professor Maggie Daley is stunned to learn the gunman was her former student. She is further dismayed when she finds an old essay offering clues to his violent nature she might have missed.
Even as the tragedy begins to fade from the national consciousness, its ripple effect on Maggie intensifies, jeopardizing her relationships with those closest to her, including her anxiety-ridden daughter, Anna; her ex-husband; and her boss-not to mention her new, but secret, relationship with a colleague. Meanwhile, a viral social media post prompts further public scrutiny and an investigation into the shooter's troubled past. Feeling pressured from all sides, Maggie begins to fear that her culpability may extend past a simple sense of guilt and put the life she's built at risk.
IF WE HAD KNOWN explores the private implications of public tragedies, how we navigate fear in today's world, and whether it's possible to see anyone-children, parents, students--as they truly are.
This book does sound good. Sometimes I wonder about the other people in the lives of individuals that commit these horrible acts. I could definitely see this scenario.


FCC releases net neutrality regulations; opponents expected to sue - LA Times
BUSINESS FCC releases net neutrality regulations; opponents expected to sue
FCC commissioners Pablo Martinez Monsivais / Associated Press FCC Chairman Tom Wheeler, center, is flanked by Commissioners Ajit Pai, left, Mignon Clyburn, Jessica Rosenworcel and Michael O'Rielly during a hearing and vote on proposed net neutrality rules in Washington. FCC Chairman Tom Wheeler, center, is flanked by Commissioners Ajit Pai, left, Mignon Clyburn, Jessica Rosenworcel and Michael O'Rielly during a hearing and vote on proposed net neutrality rules in Washington. (Pablo Martinez Monsivais / Associated Press) Jim PuzzangheraContact Reporter
FCC releases wording of net neutrality rules in 400-page tome, with the regulations taking up only eight pages
Federal regulators released details of the new rules governing Internet traffic in a 400-page tome that also lays out the justification for tough measures and gives critics the fodder for their expected court appeals.The Federal Communications Commission released the wording of net neutrality rules it approved two weeks ago, but the regulations themselves didn't take up much room — only eight pages.
Most of the order contains explanations and rationale for the new regulations. The last 87 pages are statements from the commissioners, including a 64-page dissent from Republican Commissioner Ajit Pai.The release of the document was highly anticipated, though there was little that was new. The agency will take a more active role in ensuring that the flow of Internet traffic remains unhindered and will require broadband providers act in a "just and reasonable" manner.
In releasing the details Thursday, the FCC essentially started the clock on implementing the new rules of the road for the Internet and on efforts by opponents to stop them.Lawyers for industry trade groups and broadband service providers, such as AT&T Inc. and Verizon Communications Inc., began poring over the document posted on the FCC's website Thursday. Ultimately, though, we are confident the issue will be resolved by bipartisan action by Congress or a future FCC or by the courts. — Jim Cicconi, AT&T's senior executive vice president of external and legislative affairs "It will be challenged," predicted Michael Pryor, a special counsel in the regulatory communications practice at the Cooley law firm in Washington. "I think the question is how many people end up challenging it."Twice before, the industry has won court orders tossing out similar rules.
Lawmakers also are reviewing the details. Three key Republicans are pushing legislation that would take a more limited approach to ensuring the unfettered flow of content on the Internet. Some Democrats have expressed interest in working with them because legislation would provide more certainty than a regulatory decision. FCC's new net neutrality rules are sure to be challenged Jim Puzzanghera After two failed attempts to enact rules for Internet traffic, regulators adopted a heavily criticized — but legally stronger — strategy to try to make sure their net neutrality rules stand up in court. But an expected lawsuit is only one hurdle for the new policy. The plan that the Federal Communications... After two failed attempts to enact rules for Internet traffic, regulators adopted a heavily criticized — but legally stronger — strategy to try to make sure their net neutrality rules stand up in court. But an expected lawsuit is only one hurdle for the new policy. The plan that the Federal Communications... (Jim Puzzanghera) "Our six-page draft legislation could prevent abuses and promote robust Internet investment — all without the overreach included in the FCC's order," Sen. John Thune (R-S.D.), Rep. Fred Upton (R-Mich.) and Rep. Greg Walden (R-Ore.) said in a joint statement.All five FCC members are scheduled to testify Wednesday before the Senate Commerce Committee, which Thune chairs.The Democrat-controlled FCC approved the regulations Feb. 26 in a party-line 3-2 vote after President Obama publicly urged them to do so.The main provisions prohibit broadband providers from blocking or slowing delivery of any lawful content through their networks for any reason other than "reasonable network management" and ban so-called paid prioritization, the sale of faster delivery.The FCC would waive the ban on paid prioritization if a company could show that it "would provide some significant public interest benefit and would not harm the open nature of the Internet.""The order uses every tool in the commission's toolbox to make sure the Internet stays fair, fast and open for all Americans, while ensuring investment and innovation can flourish," the FCC said in releasing the full order.In the next few weeks, the order will be published in the Federal Register and nearly all the provisions will take effect 60 days after that unless a court steps in with a preliminary injunction.FCC officials said the length of the order, which included 1,950 footnotes, was partly in response to many of the arguments made in the nearly 4 million public comments the agency received on the issue last year.But another reason for the extensive detail was to offer the legal and factual basis for the regulations in anticipation of a legal challenge, FCC officials said."Clearly it is very much written with litigation in mind," Pryor said.What has made this set of net neutrality rules so much more controversial than past efforts was the FCC's major policy shift in treating broadband providers as more highly regulated telecommunications services. That decision was aimed at addressing a major flaw in the 2010 net neutrality rules that led federal judges to overturn them.Critics slammed the FCC for reclassifying broadband as a utility even though FCC Chairman Tom Wheeler has promised a light approach that avoids rate regulation and many other heavy-handed rules.The FCC also decided for the first time to apply net neutrality regulations to wireless broadband. The agency does that by expanding the definition of conventional phone service to include Internet addresses as well as phone numbers, according to the order.That decision could have major implications for telecommunications regulation as the types of Internet-connected devices expand, said Robert McDowell, a former Republican FCC commissioner who voted against the 2010 net neutrality regulations."As we see the Internet of everything starting to explode, it's more than just your computer, your tablet, your smartphone. It's going to be your car, your dishwasher and all sorts of things," said McDowell, a senior fellow at the Hudson Institute think tank. "This is going to have an unfathomable number of consequences."AT&T hinted at a likely legal challenge of the regulations as it warned that the release of the order "begins a period of uncertainty that will damage broadband investment in the United States.""Ultimately, though, we are confident the issue will be resolved by bipartisan action by Congress or a future FCC or by the courts," said Jim Cicconi, AT&T's senior executive vice president of external and legislative affairs.The National Cable and Telecommunications Assn. trade group also warned of "years of litigation" that would cause "serious collateral consequences for consumers, and ongoing market uncertainty that will slow America's quest to advance broadband deployment and adoption."
Matt Wood, policy director of Free Press, a digital rights group that strongly supported tough net neutrality rules, said he hoped that the public release of the details would end "fear-mongering" by opponents of the FCC's action."This is not a government takeover of the Internet or an onerous utility-style regulation," he said.
Opponents of Internet rules recklessly play the tax-grab card

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