Repository: UVVM/UVVM
Description: UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improvement.    Community forum: https://forum.uvvm.org/    UVVM.org: https://uvvm.org/
Languages: Stata,VHDL,Python,Shell,HTML
Stars: 385
License: Apache License 2.0