Repository: liuqdev/8-bits-RISC-CPU-Verilog
Description: Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（中央处理器）简单结构和Verilog实现。
Languages: Verilog,Stata
Stars: 140
License: MIT License