semvec/pypi-packages huggingface dataset:
sphinx-verilog-domain 0.2.post21
Verilog Domain for Sphinx
Requires Python: >=3.7

sphinx-verilog-domain
=====================

.. warning::

    This extension is in development stage.

Dependencies
------------

* ``lark-parser``

Enabling
--------

Add extension in ``conf.py``::

    extensions = [ 'sphinx_verilog_domain' ]

Usage
-----

Module headers (non-ANSI-style only for now)::

    .. verilog::module:: module Top(a, b);

Port declarations::

    .. verilog:port:: input wire [31:0] a, b;

Parameter declarations::

    .. verilog:parameter:: parameter logic param_name_05 = 1, param_name_05_b = 2;

Custom name for use in references::

    .. verilog:module:: module \35(4p3|) (z);
        :refname: module_escaped

References::

    Reference to :verilog:ref:`Top`
    Reference to :verilog:ref:`module_escaped` - links to ``\\35(4p3|)``

Nesting::

    .. verilog:module:: module Top1(a, b, c);

        .. verilog:port:: input a;

            Description of port ``a``

        .. verilog:port:: input b;

            Description of port ``b``

        .. verilog:module:: module Nested(a);

            .. verilog:port:: output a;

                Description of port ``a`` in ``Nested``

            Reference to module ``Top1``'s port ``a``: :verilog:ref:`Top1.a`.

Namespaces
^^^^^^^^^^

There are three directives for changing current Verilog scope:

* ``.. verilog:namespace:: A::B`` - sets current scope to ``A::B``. Using ``$root`` as an argument or using the directive without argument at all sets global namespace.

* ``.. verilog:namespace-push:: C::D`` - sets current scope to ``C::D`` relatively to current scope

* ``.. verilog:namespace-pop::`` - restores scope which was active before previous ``namespace-push`` was called. If there is no matching ``namespace-push``, scope is set to global scope.

.. note::
    ``verilog::namespace`` resets push/pop stack

Example::

    .. verilog:namespace:: A::B
    .. verilog:port:: input inside_a_b;
    .. verilog:namespace-push:: C::D
    .. verilog:port:: input inside_a_b_c_d;
    .. verilog:namespace-pop::
    .. verilog:port:: input inside_a_b_again;
    .. verilog:namespace::
    .. verilog:port:: input in_global_namespace;

Development
-----------

To create and open the development environment with all system
and python packages use::

   make env
   source env/conda/bin/activate sphinx-verilog-domain
pyfs-application 1.0.2
Feishu Application Module for Python.
Keywords: Feishu Application

================
pyfs-application
================

Feishu Application Module for Python.

Installation
============

::

    pip install pyfs-application


Usage
=====

::

    from pyfs_application import Application, is_user_admin


Method
======

::

    class MarketCode(BaseToken):
        def __init__(self, appid=None, secret=None, token=None, storage=None):
            super(MarketCode, self).__init__(appid=appid, secret=secret, token=token, storage=storage)

        def is_user_admin(self, open_id=None, employee_id=None, appid=None, secret=None, ticket=None, token=None, storage=None):
pyfs-pay 1.0.1
Feishu Pay Module for Python.
Keywords: Feishu Pay

========
pyfs-pay
========

Feishu Pay Module for Python.

Installation
============

::

    pip install pyfs-pay


Usage
=====

::

    from pyfs_pay import Pay, check_user_paid_scope


Method
======

::

    class Pay(TenantAccessToken):
        def __init__(self, appid=None, secret=None, ticket=None, tenant_key=None, token=None, storage=None):
            super(Pay, self).__init__(appid=appid, secret=secret, ticket=ticket, tenant_key=tenant_key, token=token, storage=storage)

        def check_user_paid_scope(self, open_id=None, user_id=None, appid=None, secret=None, ticket=None, tenant_key=None, token=None, storage=None):