pyVHDLModel 0.33.1
An abstract VHDL language model.
License: Apache-2.0
Requires Python: >=3.11
Keywords: Python3 VHDL Language Model Abstract

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An abstract VHDL language model written in Python.


# Main Goals

This package provides a unified abstract language model for VHDL.
Projects reading from source files can derive own classes and implement additional logic to create a concrete language
model for their tools.

Projects consuming pre-processed VHDL data (parsed, analyzed or elaborated) can build higher level features and services
on such a model, while supporting multiple frontends.


# Use Cases

## pyVHDLModel Generators

* High-level API for [GHDL's](https://GitHub.com/ghdl/ghdl) `libghdl` offered via `pyghdl`.
* Code Document-Object-Model (Code-DOM) in [pyVHDLParser](https://GitHub.com/Paebbels/pyVHDLParser).

## pyVHDLModel Consumers

* Create graphical views of VHDL files or designs.  
	Possible candidates: [Symbolator](https://GitHub.com/kevinpt/symbolator)
* Created a (re)formatted output of VHDL.


# Examples

## List all Entities with Generics and Ports

The following tiny example is based on GHDL's [`pyGHDL.dom`](https://GitHub.com/ghdl/ghdl/tree/master/pyGHDL/dom) package implementing
pyVHDLModel.

```python
from pathlib import Path
from pyGHDL.dom.NonStandard import Design, Document

sourceFile = Path("example.vhdl")

design = Design()
library = design.GetLibrary("lib")
document = Document(sourceFile)
design.AddDocument(document, library)

for entity in document.Entities.values():
  print(f"{entity.Identifier}")
  print("  generics:")
  for generic in entity.GenericItems:
    identifiers = ", ".join([str(i) for i in generic.Identifiers])
    print(f"  - {identifiers} : {generic.Mode!s} {generic.Subtype}")
  print("  ports:")
  for port in entity.PortItems:
    identifiers = ", ".join([str(i) for i in port.Identifiers])
    print(f"  - {identifiers} : {port.Mode!s} {port.Subtype}")
```


# Contributors

* [Patrick Lehmann](https://GitHub.com/Paebbels) (Maintainer)
* [Unai Martinez-Corral](https://GitHub.com/umarcor)
* [and more...](https://GitHub.com/VHDL/pyVHDLModel/graphs/contributors)


# License

This Python package (source code) licensed under [Apache License 2.0](LICENSE.md).  
The accompanying documentation is licensed under [Creative Commons - Attribution 4.0 (CC-BY 4.0)](doc/Doc-License.rst).

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SPDX-License-Identifier: Apache-2.0