DooPourd 0.7.1
A comprehensive Python framework for parsing Verilog code and generating circuit diagrams (Verilog Parser + Circuit Visualization)
License: MIT
Requires Python: >=3.8
Keywords: verilog, parser, circuit, diagram, hdl, hardware, visualization, ast, lexer

# DooPourd - Verilog Parser & Circuit Diagram Generator

A comprehensive Python framework for parsing Verilog code and generating circuit diagrams (SVG/PNG).

**GitHub:** https://github.com/Dev-vesper/DooPourd  
**PyPI:** https://pypi.org/project/DooPourd/  
**License:** MIT

## Quick Install

```bash
pip install DooPourd
```

**Works on Windows, macOS, Linux - no external tools needed!**

## Features

- ✅ **Verilog Parsing** - Parse Verilog into fully-featured Abstract Syntax Trees (AST)
- ✅ **Lexical Analysis** - Full tokenization with keywords, identifiers, operators, literals
- ✅ **Pure Python Circuit SVG** - Generate circuit diagrams WITHOUT external tools (NEW v0.7.1!)
- ✅ **Circuit Diagrams** - Generate SVG and PNG from Yosys output (optional)
- ✅ **AST Visualization** - Graphical code structure via Graphviz (optional)
- ✅ **Cross-Platform** - Windows, macOS, Linux - native support

## Examples

### 1. Parse Verilog (Works Everywhere!) ✅

```python
from verilog_framework.core import parse_verilog

code = """
module adder(input a, input b, output sum);
    assign sum = a + b;
endmodule
"""

ast = parse_verilog(code)
print(f"Module: {ast.name}")
print(f"Ports: {len(ast.port_list)}")
```

### 2. Generate Circuit Diagram - Pure Python! (NEW v0.7.1 ✨)

**No external tools needed!**

```python
from verilog_framework.core import parse_verilog
from verilog_framework.visualization import CircuitSVG

code = """
module full_adder(input a, input b, input cin, output sum, output cout);
    assign sum = a ^ b ^ cin;
    assign cout = (a & b) | (cin & (a ^ b));
endmodule
"""

ast = parse_verilog(code)
svg = CircuitSVG(ast)
svg.save("circuit.svg")
print("Circuit saved to circuit.svg!")
```

**Benefits:**
- ✅ No Yosys needed
- ✅ No system dependencies  
- ✅ Windows native support
- ✅ Works immediately after `pip install`

### 3. Analyze Ports (Works Everywhere!) ✅

```python
from verilog_framework.core import parse_verilog

code = """
module counter(input clk, input reset, output [7:0] count);
    reg [7:0] count;
endmodule
"""

ast = parse_verilog(code)

# Extract inputs/outputs
inputs = [p.name for p in ast.port_list if p.direction == 'input']
outputs = [p.name for p in ast.port_list if p.direction == 'output']

print(f"Inputs: {inputs}")    # ['clk', 'reset']
print(f"Outputs: {outputs}")  # ['count']
```

## Installation

### Minimal Installation (Recommended)

```bash
pip install DooPourd
```

Includes Pure Python CircuitSVG for circuit diagrams - **no external tools needed!**

### With Graphviz Support (Optional)

For AST structure visualization:

```bash
pip install DooPourd[graph]
```

Then install Graphviz on your system:
```bash
# macOS
brew install graphviz

# Ubuntu/WSL
sudo apt-get install graphviz

# Windows
choco install graphviz
```

### With Advanced Diagrams (Linux/WSL only)

For detailed schematics via Yosys:

```bash
pip install DooPourd[circuit]
sudo apt-get install yosys npm
npm install -g netlistsvg
```

### All Features
```bash
pip install DooPourd[all]
```

### From Source

```bash
git clone https://github.com/Dev-vesper/DooPourd.git
cd DooPourd
pip install -e .
```

## Platform Support

| Feature | Windows | macOS | Linux |
|---------|---------|-------|-------|
| Parse Verilog | ✅ | ✅ | ✅ |
| Pure Python SVG | ✅ | ✅ | ✅ |
| Graphviz visualization | ⚠️ optional | ⚠️ optional | ⚠️ optional |
| Yosys diagrams | ⚠️ optional | ✅ optional | ✅ optional |

## Supported Verilog Features

## Supported Verilog Features

| Feature | Status |
|---------|--------|
| Module declarations | ✅ Supported |
| Ports (input/output/inout) | ✅ Supported |
| Wire declarations | ✅ Supported |
| Reg declarations | ✅ Supported |
| Bit-width specifications | ✅ Supported |
| Continuous assignments | ✅ Supported |
| Always blocks | ✅ Supported |
| @(posedge/negedge) | ✅ Supported |
| Binary/unary expressions | ✅ Supported |
| Comments | ✅ Supported |
| Multi-line code | ✅ Supported |

**Note:** Advanced features (functions, tasks, generate blocks) not yet supported.

## Troubleshooting

### "Graphviz not installed"

Optional feature - install graphviz on your system or use Pure Python CircuitSVG!

```bash
brew install graphviz  # macOS
# or
sudo apt-get install graphviz  # Linux
```

### "Yosys not found"

Optional advanced feature for Linux/WSL. Pure Python CircuitSVG works on Windows without Yosys!

## License

MIT - See LICENSE for details