static void _decode_opc(DisasContext * ctx)

{

#if 0

    fprintf(stderr, "Translating opcode 0x%04x\n", ctx->opcode);

#endif

    switch (ctx->opcode) {

    case 0x0019:		/* div0u */

	tcg_gen_andi_i32(cpu_sr, cpu_sr, ~(SR_M | SR_Q | SR_T));

	return;

    case 0x000b:		/* rts */

	CHECK_NOT_DELAY_SLOT

	tcg_gen_mov_i32(cpu_delayed_pc, cpu_pr);

	ctx->flags |= DELAY_SLOT;

	ctx->delayed_pc = (uint32_t) - 1;

	return;

    case 0x0028:		/* clrmac */

	tcg_gen_movi_i32(cpu_mach, 0);

	tcg_gen_movi_i32(cpu_macl, 0);

	return;

    case 0x0048:		/* clrs */

	tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_S);

	return;

    case 0x0008:		/* clrt */

	gen_clr_t();

	return;

    case 0x0038:		/* ldtlb */

	CHECK_PRIVILEGED

	gen_helper_ldtlb();

	return;

    case 0x002b:		/* rte */

	CHECK_PRIVILEGED

	CHECK_NOT_DELAY_SLOT

	tcg_gen_mov_i32(cpu_sr, cpu_ssr);

	tcg_gen_mov_i32(cpu_delayed_pc, cpu_spc);

	ctx->flags |= DELAY_SLOT;

	ctx->delayed_pc = (uint32_t) - 1;

	return;

    case 0x0058:		/* sets */

	tcg_gen_ori_i32(cpu_sr, cpu_sr, SR_S);

	return;

    case 0x0018:		/* sett */

	gen_set_t();

	return;

    case 0xfbfd:		/* frchg */

	tcg_gen_xori_i32(cpu_fpscr, cpu_fpscr, FPSCR_FR);

	ctx->bstate = BS_STOP;

	return;

    case 0xf3fd:		/* fschg */

	tcg_gen_xori_i32(cpu_fpscr, cpu_fpscr, FPSCR_SZ);

	ctx->bstate = BS_STOP;

	return;

    case 0x0009:		/* nop */

	return;

    case 0x001b:		/* sleep */

	CHECK_PRIVILEGED

	gen_helper_sleep(tcg_const_i32(ctx->pc + 2));

	return;

    }

    switch (ctx->opcode & 0xf000) {

    case 0x1000:		/* mov.l Rm,@(disp,Rn) */

	{

	    TCGv addr = tcg_temp_new();

	    tcg_gen_addi_i32(addr, REG(B11_8), B3_0 * 4);

	    tcg_gen_qemu_st32(REG(B7_4), addr, ctx->memidx);

	    tcg_temp_free(addr);

	}

	return;

    case 0x5000:		/* mov.l @(disp,Rm),Rn */

	{

	    TCGv addr = tcg_temp_new();

	    tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 4);

	    tcg_gen_qemu_ld32s(REG(B11_8), addr, ctx->memidx);

	    tcg_temp_free(addr);

	}

	return;

    case 0xe000:		/* mov #imm,Rn */

	tcg_gen_movi_i32(REG(B11_8), B7_0s);

	return;

    case 0x9000:		/* mov.w @(disp,PC),Rn */

	{

	    TCGv addr = tcg_const_i32(ctx->pc + 4 + B7_0 * 2);

	    tcg_gen_qemu_ld16s(REG(B11_8), addr, ctx->memidx);

	    tcg_temp_free(addr);

	}

	return;

    case 0xd000:		/* mov.l @(disp,PC),Rn */

	{

	    TCGv addr = tcg_const_i32((ctx->pc + 4 + B7_0 * 4) & ~3);

	    tcg_gen_qemu_ld32s(REG(B11_8), addr, ctx->memidx);

	    tcg_temp_free(addr);

	}

	return;

    case 0x7000:		/* add #imm,Rn */

	tcg_gen_addi_i32(REG(B11_8), REG(B11_8), B7_0s);

	return;

    case 0xa000:		/* bra disp */

	CHECK_NOT_DELAY_SLOT

	ctx->delayed_pc = ctx->pc + 4 + B11_0s * 2;

	tcg_gen_movi_i32(cpu_delayed_pc, ctx->delayed_pc);

	ctx->flags |= DELAY_SLOT;

	return;

    case 0xb000:		/* bsr disp */

	CHECK_NOT_DELAY_SLOT

	tcg_gen_movi_i32(cpu_pr, ctx->pc + 4);

	ctx->delayed_pc = ctx->pc + 4 + B11_0s * 2;

	tcg_gen_movi_i32(cpu_delayed_pc, ctx->delayed_pc);

	ctx->flags |= DELAY_SLOT;

	return;

    }

    switch (ctx->opcode & 0xf00f) {

    case 0x6003:		/* mov Rm,Rn */

	tcg_gen_mov_i32(REG(B11_8), REG(B7_4));

	return;

    case 0x2000:		/* mov.b Rm,@Rn */

	tcg_gen_qemu_st8(REG(B7_4), REG(B11_8), ctx->memidx);

	return;

    case 0x2001:		/* mov.w Rm,@Rn */

	tcg_gen_qemu_st16(REG(B7_4), REG(B11_8), ctx->memidx);

	return;

    case 0x2002:		/* mov.l Rm,@Rn */

	tcg_gen_qemu_st32(REG(B7_4), REG(B11_8), ctx->memidx);

	return;

    case 0x6000:		/* mov.b @Rm,Rn */

	tcg_gen_qemu_ld8s(REG(B11_8), REG(B7_4), ctx->memidx);

	return;

    case 0x6001:		/* mov.w @Rm,Rn */

	tcg_gen_qemu_ld16s(REG(B11_8), REG(B7_4), ctx->memidx);

	return;

    case 0x6002:		/* mov.l @Rm,Rn */

	tcg_gen_qemu_ld32s(REG(B11_8), REG(B7_4), ctx->memidx);

	return;

    case 0x2004:		/* mov.b Rm,@-Rn */

	{

	    TCGv addr = tcg_temp_new();

	    tcg_gen_subi_i32(addr, REG(B11_8), 1);

	    tcg_gen_qemu_st8(REG(B7_4), addr, ctx->memidx);	/* might cause re-execution */

	    tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 1);	/* modify register status */

	    tcg_temp_free(addr);

	}

	return;

    case 0x2005:		/* mov.w Rm,@-Rn */

	{

	    TCGv addr = tcg_temp_new();

	    tcg_gen_subi_i32(addr, REG(B11_8), 2);

	    tcg_gen_qemu_st16(REG(B7_4), addr, ctx->memidx);

	    tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 2);

	    tcg_temp_free(addr);

	}

	return;

    case 0x2006:		/* mov.l Rm,@-Rn */

	{

	    TCGv addr = tcg_temp_new();

	    tcg_gen_subi_i32(addr, REG(B11_8), 4);

	    tcg_gen_qemu_st32(REG(B7_4), addr, ctx->memidx);

	    tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4);

	}

	return;

    case 0x6004:		/* mov.b @Rm+,Rn */

	tcg_gen_qemu_ld8s(REG(B11_8), REG(B7_4), ctx->memidx);

	if ( B11_8 != B7_4 )

		tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 1);

	return;

    case 0x6005:		/* mov.w @Rm+,Rn */

	tcg_gen_qemu_ld16s(REG(B11_8), REG(B7_4), ctx->memidx);

	if ( B11_8 != B7_4 )

		tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 2);

	return;

    case 0x6006:		/* mov.l @Rm+,Rn */

	tcg_gen_qemu_ld32s(REG(B11_8), REG(B7_4), ctx->memidx);

	if ( B11_8 != B7_4 )

		tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);

	return;

    case 0x0004:		/* mov.b Rm,@(R0,Rn) */

	{

	    TCGv addr = tcg_temp_new();

	    tcg_gen_add_i32(addr, REG(B11_8), REG(0));

	    tcg_gen_qemu_st8(REG(B7_4), addr, ctx->memidx);

	    tcg_temp_free(addr);

	}

	return;

    case 0x0005:		/* mov.w Rm,@(R0,Rn) */

	{

	    TCGv addr = tcg_temp_new();

	    tcg_gen_add_i32(addr, REG(B11_8), REG(0));

	    tcg_gen_qemu_st16(REG(B7_4), addr, ctx->memidx);

	    tcg_temp_free(addr);

	}

	return;

    case 0x0006:		/* mov.l Rm,@(R0,Rn) */

	{

	    TCGv addr = tcg_temp_new();

	    tcg_gen_add_i32(addr, REG(B11_8), REG(0));

	    tcg_gen_qemu_st32(REG(B7_4), addr, ctx->memidx);

	    tcg_temp_free(addr);

	}

	return;

    case 0x000c:		/* mov.b @(R0,Rm),Rn */

	{

	    TCGv addr = tcg_temp_new();

	    tcg_gen_add_i32(addr, REG(B7_4), REG(0));

	    tcg_gen_qemu_ld8s(REG(B11_8), addr, ctx->memidx);

	    tcg_temp_free(addr);

	}

	return;

    case 0x000d:		/* mov.w @(R0,Rm),Rn */

	{

	    TCGv addr = tcg_temp_new();

	    tcg_gen_add_i32(addr, REG(B7_4), REG(0));

	    tcg_gen_qemu_ld16s(REG(B11_8), addr, ctx->memidx);

	    tcg_temp_free(addr);

	}

	return;

    case 0x000e:		/* mov.l @(R0,Rm),Rn */

	{

	    TCGv addr = tcg_temp_new();

	    tcg_gen_add_i32(addr, REG(B7_4), REG(0));

	    tcg_gen_qemu_ld32s(REG(B11_8), addr, ctx->memidx);

	    tcg_temp_free(addr);

	}

	return;

    case 0x6008:		/* swap.b Rm,Rn */

	{

	    TCGv highw, high, low;

	    highw = tcg_temp_new();

	    tcg_gen_andi_i32(highw, REG(B7_4), 0xffff0000);

	    high = tcg_temp_new();

	    tcg_gen_ext8u_i32(high, REG(B7_4));

	    tcg_gen_shli_i32(high, high, 8);

	    low = tcg_temp_new();

	    tcg_gen_shri_i32(low, REG(B7_4), 8);

	    tcg_gen_ext8u_i32(low, low);

	    tcg_gen_or_i32(REG(B11_8), high, low);

	    tcg_gen_or_i32(REG(B11_8), REG(B11_8), highw);

	    tcg_temp_free(low);

	    tcg_temp_free(high);

	}

	return;

    case 0x6009:		/* swap.w Rm,Rn */

	{

	    TCGv high, low;

	    high = tcg_temp_new();

	    tcg_gen_ext16u_i32(high, REG(B7_4));

	    tcg_gen_shli_i32(high, high, 16);

	    low = tcg_temp_new();

	    tcg_gen_shri_i32(low, REG(B7_4), 16);

	    tcg_gen_ext16u_i32(low, low);

	    tcg_gen_or_i32(REG(B11_8), high, low);

	    tcg_temp_free(low);

	    tcg_temp_free(high);

	}

	return;

    case 0x200d:		/* xtrct Rm,Rn */

	{

	    TCGv high, low;

	    high = tcg_temp_new();

	    tcg_gen_ext16u_i32(high, REG(B7_4));

	    tcg_gen_shli_i32(high, high, 16);

	    low = tcg_temp_new();

	    tcg_gen_shri_i32(low, REG(B11_8), 16);

	    tcg_gen_ext16u_i32(low, low);

	    tcg_gen_or_i32(REG(B11_8), high, low);

	    tcg_temp_free(low);

	    tcg_temp_free(high);

	}

	return;

    case 0x300c:		/* add Rm,Rn */

	tcg_gen_add_i32(REG(B11_8), REG(B11_8), REG(B7_4));

	return;

    case 0x300e:		/* addc Rm,Rn */

	gen_helper_addc(REG(B11_8), REG(B7_4), REG(B11_8));

	return;

    case 0x300f:		/* addv Rm,Rn */

	gen_helper_addv(REG(B11_8), REG(B7_4), REG(B11_8));

	return;

    case 0x2009:		/* and Rm,Rn */

	tcg_gen_and_i32(REG(B11_8), REG(B11_8), REG(B7_4));

	return;

    case 0x3000:		/* cmp/eq Rm,Rn */

	gen_cmp(TCG_COND_EQ, REG(B7_4), REG(B11_8));

	return;

    case 0x3003:		/* cmp/ge Rm,Rn */

	gen_cmp(TCG_COND_GE, REG(B7_4), REG(B11_8));

	return;

    case 0x3007:		/* cmp/gt Rm,Rn */

	gen_cmp(TCG_COND_GT, REG(B7_4), REG(B11_8));

	return;

    case 0x3006:		/* cmp/hi Rm,Rn */

	gen_cmp(TCG_COND_GTU, REG(B7_4), REG(B11_8));

	return;

    case 0x3002:		/* cmp/hs Rm,Rn */

	gen_cmp(TCG_COND_GEU, REG(B7_4), REG(B11_8));

	return;

    case 0x200c:		/* cmp/str Rm,Rn */

	{

	    int label1 = gen_new_label();

	    int label2 = gen_new_label();

	    TCGv cmp1 = tcg_temp_local_new();

	    TCGv cmp2 = tcg_temp_local_new();

	    tcg_gen_xor_i32(cmp1, REG(B7_4), REG(B11_8));

	    tcg_gen_andi_i32(cmp2, cmp1, 0xff000000);

	    tcg_gen_brcondi_i32(TCG_COND_EQ, cmp2, 0, label1);

	    tcg_gen_andi_i32(cmp2, cmp1, 0x00ff0000);

	    tcg_gen_brcondi_i32(TCG_COND_EQ, cmp2, 0, label1);

	    tcg_gen_andi_i32(cmp2, cmp1, 0x0000ff00);

	    tcg_gen_brcondi_i32(TCG_COND_EQ, cmp2, 0, label1);

	    tcg_gen_andi_i32(cmp2, cmp1, 0x000000ff);

	    tcg_gen_brcondi_i32(TCG_COND_EQ, cmp2, 0, label1);

	    tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T);

	    tcg_gen_br(label2);

	    gen_set_label(label1);

	    tcg_gen_ori_i32(cpu_sr, cpu_sr, SR_T);

	    gen_set_label(label2);

	    tcg_temp_free(cmp2);

	    tcg_temp_free(cmp1);

	}

	return;

    case 0x2007:		/* div0s Rm,Rn */

	{

	    gen_copy_bit_i32(cpu_sr, 8, REG(B11_8), 31);	/* SR_Q */

	    gen_copy_bit_i32(cpu_sr, 9, REG(B7_4), 31);		/* SR_M */

	    TCGv val = tcg_temp_new();

	    tcg_gen_xor_i32(val, REG(B7_4), REG(B11_8));

	    gen_copy_bit_i32(cpu_sr, 0, val, 31);		/* SR_T */

	    tcg_temp_free(val);

	}

	return;

    case 0x3004:		/* div1 Rm,Rn */

	gen_helper_div1(REG(B11_8), REG(B7_4), REG(B11_8));

	return;

    case 0x300d:		/* dmuls.l Rm,Rn */

	{

	    TCGv_i64 tmp1 = tcg_temp_new_i64();

	    TCGv_i64 tmp2 = tcg_temp_new_i64();

	    tcg_gen_ext_i32_i64(tmp1, REG(B7_4));

	    tcg_gen_ext_i32_i64(tmp2, REG(B11_8));

	    tcg_gen_mul_i64(tmp1, tmp1, tmp2);

	    tcg_gen_trunc_i64_i32(cpu_macl, tmp1);

	    tcg_gen_shri_i64(tmp1, tmp1, 32);

	    tcg_gen_trunc_i64_i32(cpu_mach, tmp1);

	    tcg_temp_free_i64(tmp2);

	    tcg_temp_free_i64(tmp1);

	}

	return;

    case 0x3005:		/* dmulu.l Rm,Rn */

	{

	    TCGv_i64 tmp1 = tcg_temp_new_i64();

	    TCGv_i64 tmp2 = tcg_temp_new_i64();

	    tcg_gen_extu_i32_i64(tmp1, REG(B7_4));

	    tcg_gen_extu_i32_i64(tmp2, REG(B11_8));

	    tcg_gen_mul_i64(tmp1, tmp1, tmp2);

	    tcg_gen_trunc_i64_i32(cpu_macl, tmp1);

	    tcg_gen_shri_i64(tmp1, tmp1, 32);

	    tcg_gen_trunc_i64_i32(cpu_mach, tmp1);

	    tcg_temp_free_i64(tmp2);

	    tcg_temp_free_i64(tmp1);

	}

	return;

    case 0x600e:		/* exts.b Rm,Rn */

	tcg_gen_ext8s_i32(REG(B11_8), REG(B7_4));

	return;

    case 0x600f:		/* exts.w Rm,Rn */

	tcg_gen_ext16s_i32(REG(B11_8), REG(B7_4));

	return;

    case 0x600c:		/* extu.b Rm,Rn */

	tcg_gen_ext8u_i32(REG(B11_8), REG(B7_4));

	return;

    case 0x600d:		/* extu.w Rm,Rn */

	tcg_gen_ext16u_i32(REG(B11_8), REG(B7_4));

	return;

    case 0x000f:		/* mac.l @Rm+,@Rn+ */

	{

	    TCGv arg0, arg1;

	    arg0 = tcg_temp_new();

	    tcg_gen_qemu_ld32s(arg0, REG(B7_4), ctx->memidx);

	    arg1 = tcg_temp_new();

	    tcg_gen_qemu_ld32s(arg1, REG(B11_8), ctx->memidx);

	    gen_helper_macl(arg0, arg1);

	    tcg_temp_free(arg1);

	    tcg_temp_free(arg0);

	    tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);

	    tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);

	}

	return;

    case 0x400f:		/* mac.w @Rm+,@Rn+ */

	{

	    TCGv arg0, arg1;

	    arg0 = tcg_temp_new();

	    tcg_gen_qemu_ld32s(arg0, REG(B7_4), ctx->memidx);

	    arg1 = tcg_temp_new();

	    tcg_gen_qemu_ld32s(arg1, REG(B11_8), ctx->memidx);

	    gen_helper_macw(arg0, arg1);

	    tcg_temp_free(arg1);

	    tcg_temp_free(arg0);

	    tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 2);

	    tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 2);

	}

	return;

    case 0x0007:		/* mul.l Rm,Rn */

	tcg_gen_mul_i32(cpu_macl, REG(B7_4), REG(B11_8));

	return;

    case 0x200f:		/* muls.w Rm,Rn */

	{

	    TCGv arg0, arg1;

	    arg0 = tcg_temp_new();

	    tcg_gen_ext16s_i32(arg0, REG(B7_4));

	    arg1 = tcg_temp_new();

	    tcg_gen_ext16s_i32(arg1, REG(B11_8));

	    tcg_gen_mul_i32(cpu_macl, arg0, arg1);

	    tcg_temp_free(arg1);

	    tcg_temp_free(arg0);

	}

	return;

    case 0x200e:		/* mulu.w Rm,Rn */

	{

	    TCGv arg0, arg1;

	    arg0 = tcg_temp_new();

	    tcg_gen_ext16u_i32(arg0, REG(B7_4));

	    arg1 = tcg_temp_new();

	    tcg_gen_ext16u_i32(arg1, REG(B11_8));

	    tcg_gen_mul_i32(cpu_macl, arg0, arg1);

	    tcg_temp_free(arg1);

	    tcg_temp_free(arg0);

	}

	return;

    case 0x600b:		/* neg Rm,Rn */

	tcg_gen_neg_i32(REG(B11_8), REG(B7_4));

	return;

    case 0x600a:		/* negc Rm,Rn */

	gen_helper_negc(REG(B11_8), REG(B7_4));

	return;

    case 0x6007:		/* not Rm,Rn */

	tcg_gen_not_i32(REG(B11_8), REG(B7_4));

	return;

    case 0x200b:		/* or Rm,Rn */

	tcg_gen_or_i32(REG(B11_8), REG(B11_8), REG(B7_4));

	return;

    case 0x400c:		/* shad Rm,Rn */

	{

	    int label1 = gen_new_label();

	    int label2 = gen_new_label();

	    int label3 = gen_new_label();

	    int label4 = gen_new_label();

	    TCGv shift = tcg_temp_local_new();

	    tcg_gen_brcondi_i32(TCG_COND_LT, REG(B7_4), 0, label1);

	    /* Rm positive, shift to the left */

	    tcg_gen_andi_i32(shift, REG(B7_4), 0x1f);

	    tcg_gen_shl_i32(REG(B11_8), REG(B11_8), shift);

	    tcg_gen_br(label4);

	    /* Rm negative, shift to the right */

	    gen_set_label(label1);

	    tcg_gen_andi_i32(shift, REG(B7_4), 0x1f);

	    tcg_gen_brcondi_i32(TCG_COND_EQ, shift, 0, label2);

	    tcg_gen_not_i32(shift, REG(B7_4));

	    tcg_gen_andi_i32(shift, shift, 0x1f);

	    tcg_gen_addi_i32(shift, shift, 1);

	    tcg_gen_sar_i32(REG(B11_8), REG(B11_8), shift);

	    tcg_gen_br(label4);

	    /* Rm = -32 */

	    gen_set_label(label2);

	    tcg_gen_brcondi_i32(TCG_COND_LT, REG(B11_8), 0, label3);

	    tcg_gen_movi_i32(REG(B11_8), 0);

	    tcg_gen_br(label4);

	    gen_set_label(label3);

	    tcg_gen_movi_i32(REG(B11_8), 0xffffffff);

	    gen_set_label(label4);

	    tcg_temp_free(shift);

	}

	return;

    case 0x400d:		/* shld Rm,Rn */

	{

	    int label1 = gen_new_label();

	    int label2 = gen_new_label();

	    int label3 = gen_new_label();

	    TCGv shift = tcg_temp_local_new();

	    tcg_gen_brcondi_i32(TCG_COND_LT, REG(B7_4), 0, label1);

	    /* Rm positive, shift to the left */

	    tcg_gen_andi_i32(shift, REG(B7_4), 0x1f);

	    tcg_gen_shl_i32(REG(B11_8), REG(B11_8), shift);

	    tcg_gen_br(label3);

	    /* Rm negative, shift to the right */

	    gen_set_label(label1);

	    tcg_gen_andi_i32(shift, REG(B7_4), 0x1f);

	    tcg_gen_brcondi_i32(TCG_COND_EQ, shift, 0, label2);

	    tcg_gen_not_i32(shift, REG(B7_4));

	    tcg_gen_andi_i32(shift, shift, 0x1f);

	    tcg_gen_addi_i32(shift, shift, 1);

	    tcg_gen_shr_i32(REG(B11_8), REG(B11_8), shift);

	    tcg_gen_br(label3);

	    /* Rm = -32 */

	    gen_set_label(label2);

	    tcg_gen_movi_i32(REG(B11_8), 0);

	    gen_set_label(label3);

	    tcg_temp_free(shift);

	}

	return;

    case 0x3008:		/* sub Rm,Rn */

	tcg_gen_sub_i32(REG(B11_8), REG(B11_8), REG(B7_4));

	return;

    case 0x300a:		/* subc Rm,Rn */

	gen_helper_subc(REG(B11_8), REG(B7_4), REG(B11_8));

	return;

    case 0x300b:		/* subv Rm,Rn */

	gen_helper_subv(REG(B11_8), REG(B7_4), REG(B11_8));

	return;

    case 0x2008:		/* tst Rm,Rn */

	{

	    TCGv val = tcg_temp_new();

	    tcg_gen_and_i32(val, REG(B7_4), REG(B11_8));

	    gen_cmp_imm(TCG_COND_EQ, val, 0);

	    tcg_temp_free(val);

	}

	return;

    case 0x200a:		/* xor Rm,Rn */

	tcg_gen_xor_i32(REG(B11_8), REG(B11_8), REG(B7_4));

	return;

    case 0xf00c: /* fmov {F,D,X}Rm,{F,D,X}Rn - FPSCR: Nothing */

	CHECK_FPU_ENABLED

	if (ctx->fpscr & FPSCR_SZ) {

	    TCGv_i64 fp = tcg_temp_new_i64();

	    gen_load_fpr64(fp, XREG(B7_4));

	    gen_store_fpr64(fp, XREG(B11_8));

	    tcg_temp_free_i64(fp);

	} else {

	    tcg_gen_mov_i32(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);

	}

	return;

    case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */

	CHECK_FPU_ENABLED

	if (ctx->fpscr & FPSCR_SZ) {

	    TCGv addr_hi = tcg_temp_new();

	    int fr = XREG(B7_4);

	    tcg_gen_addi_i32(addr_hi, REG(B11_8), 4);

	    tcg_gen_qemu_st32(cpu_fregs[fr  ], REG(B11_8), ctx->memidx);

	    tcg_gen_qemu_st32(cpu_fregs[fr+1], addr_hi,	   ctx->memidx);

	    tcg_temp_free(addr_hi);

	} else {

	    tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], REG(B11_8), ctx->memidx);

	}

	return;

    case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */

	CHECK_FPU_ENABLED

	if (ctx->fpscr & FPSCR_SZ) {

	    TCGv addr_hi = tcg_temp_new();

	    int fr = XREG(B11_8);

	    tcg_gen_addi_i32(addr_hi, REG(B7_4), 4);

	    tcg_gen_qemu_ld32u(cpu_fregs[fr  ], REG(B7_4), ctx->memidx);

	    tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr_hi,   ctx->memidx);

	    tcg_temp_free(addr_hi);

	} else {

	    tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], REG(B7_4), ctx->memidx);

	}

	return;

    case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */

	CHECK_FPU_ENABLED

	if (ctx->fpscr & FPSCR_SZ) {

	    TCGv addr_hi = tcg_temp_new();

	    int fr = XREG(B11_8);

	    tcg_gen_addi_i32(addr_hi, REG(B7_4), 4);

	    tcg_gen_qemu_ld32u(cpu_fregs[fr  ], REG(B7_4), ctx->memidx);

	    tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr_hi,   ctx->memidx);

	    tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 8);

	    tcg_temp_free(addr_hi);

	} else {

	    tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], REG(B7_4), ctx->memidx);

	    tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);

	}

	return;

    case 0xf00b: /* fmov {F,D,X}Rm,@-Rn - FPSCR: Nothing */

	CHECK_FPU_ENABLED

	if (ctx->fpscr & FPSCR_SZ) {

	    TCGv addr = tcg_temp_new_i32();

	    int fr = XREG(B7_4);

	    tcg_gen_subi_i32(addr, REG(B11_8), 4);

	    tcg_gen_qemu_st32(cpu_fregs[fr+1], addr, ctx->memidx);

	    tcg_gen_subi_i32(addr, REG(B11_8), 8);

	    tcg_gen_qemu_st32(cpu_fregs[fr  ], addr, ctx->memidx);

	    tcg_gen_mov_i32(REG(B11_8), addr);

	    tcg_temp_free(addr);

	} else {

	    TCGv addr;

	    addr = tcg_temp_new_i32();

	    tcg_gen_subi_i32(addr, REG(B11_8), 4);

	    tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], addr, ctx->memidx);

	    tcg_temp_free(addr);

	    tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4);

	}

	return;

    case 0xf006: /* fmov @(R0,Rm),{F,D,X}Rm - FPSCR: Nothing */

	CHECK_FPU_ENABLED

	{

	    TCGv addr = tcg_temp_new_i32();

	    tcg_gen_add_i32(addr, REG(B7_4), REG(0));

	    if (ctx->fpscr & FPSCR_SZ) {

		int fr = XREG(B11_8);

		tcg_gen_qemu_ld32u(cpu_fregs[fr	 ], addr, ctx->memidx);

		tcg_gen_addi_i32(addr, addr, 4);

		tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr, ctx->memidx);

	    } else {

		tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], addr, ctx->memidx);

	    }

	    tcg_temp_free(addr);

	}

	return;

    case 0xf007: /* fmov {F,D,X}Rn,@(R0,Rn) - FPSCR: Nothing */

	CHECK_FPU_ENABLED

	{

	    TCGv addr = tcg_temp_new();

	    tcg_gen_add_i32(addr, REG(B11_8), REG(0));

	    if (ctx->fpscr & FPSCR_SZ) {

		int fr = XREG(B7_4);

		tcg_gen_qemu_ld32u(cpu_fregs[fr	 ], addr, ctx->memidx);

		tcg_gen_addi_i32(addr, addr, 4);

		tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr, ctx->memidx);

	    } else {

		tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], addr, ctx->memidx);

	    }

	    tcg_temp_free(addr);

	}

	return;

    case 0xf000: /* fadd Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */

    case 0xf001: /* fsub Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */

    case 0xf002: /* fmul Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */

    case 0xf003: /* fdiv Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */

    case 0xf004: /* fcmp/eq Rm,Rn - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */

    case 0xf005: /* fcmp/gt Rm,Rn - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */

	{

	    CHECK_FPU_ENABLED

	    if (ctx->fpscr & FPSCR_PR) {

                TCGv_i64 fp0, fp1;

		if (ctx->opcode & 0x0110)

		    break; /* illegal instruction */

		fp0 = tcg_temp_new_i64();

		fp1 = tcg_temp_new_i64();

		gen_load_fpr64(fp0, DREG(B11_8));

		gen_load_fpr64(fp1, DREG(B7_4));

                switch (ctx->opcode & 0xf00f) {

                case 0xf000:		/* fadd Rm,Rn */

                    gen_helper_fadd_DT(fp0, fp0, fp1);

                    break;

                case 0xf001:		/* fsub Rm,Rn */

                    gen_helper_fsub_DT(fp0, fp0, fp1);

                    break;

                case 0xf002:		/* fmul Rm,Rn */

                    gen_helper_fmul_DT(fp0, fp0, fp1);

                    break;

                case 0xf003:		/* fdiv Rm,Rn */

                    gen_helper_fdiv_DT(fp0, fp0, fp1);

                    break;

                case 0xf004:		/* fcmp/eq Rm,Rn */

                    gen_helper_fcmp_eq_DT(fp0, fp1);

                    return;

                case 0xf005:		/* fcmp/gt Rm,Rn */

                    gen_helper_fcmp_gt_DT(fp0, fp1);

                    return;

                }

		gen_store_fpr64(fp0, DREG(B11_8));

                tcg_temp_free_i64(fp0);

                tcg_temp_free_i64(fp1);

	    } else {

                switch (ctx->opcode & 0xf00f) {

                case 0xf000:		/* fadd Rm,Rn */

                    gen_helper_fadd_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);

                    break;

                case 0xf001:		/* fsub Rm,Rn */

                    gen_helper_fsub_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);

                    break;

                case 0xf002:		/* fmul Rm,Rn */

                    gen_helper_fmul_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);

                    break;

                case 0xf003:		/* fdiv Rm,Rn */

                    gen_helper_fdiv_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);

                    break;

                case 0xf004:		/* fcmp/eq Rm,Rn */

                    gen_helper_fcmp_eq_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);

                    return;

                case 0xf005:		/* fcmp/gt Rm,Rn */

                    gen_helper_fcmp_gt_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);

                    return;

                }

	    }

	}

	return;

    case 0xf00e: /* fmac FR0,RM,Rn */

        {

            CHECK_FPU_ENABLED

            if (ctx->fpscr & FPSCR_PR) {

                break; /* illegal instruction */

            } else {

                gen_helper_fmac_FT(cpu_fregs[FREG(B11_8)],

                                   cpu_fregs[FREG(0)], cpu_fregs[FREG(B7_4)], cpu_fregs[FREG(B11_8)]);

                return;

            }

        }

    }

    switch (ctx->opcode & 0xff00) {

    case 0xc900:		/* and #imm,R0 */

	tcg_gen_andi_i32(REG(0), REG(0), B7_0);

	return;

    case 0xcd00:		/* and.b #imm,@(R0,GBR) */

	{

	    TCGv addr, val;

	    addr = tcg_temp_new();

	    tcg_gen_add_i32(addr, REG(0), cpu_gbr);

	    val = tcg_temp_new();

	    tcg_gen_qemu_ld8u(val, addr, ctx->memidx);

	    tcg_gen_andi_i32(val, val, B7_0);

	    tcg_gen_qemu_st8(val, addr, ctx->memidx);

	    tcg_temp_free(val);

	    tcg_temp_free(addr);

	}

	return;

    case 0x8b00:		/* bf label */

	CHECK_NOT_DELAY_SLOT

	    gen_conditional_jump(ctx, ctx->pc + 2,

				 ctx->pc + 4 + B7_0s * 2);

	ctx->bstate = BS_BRANCH;

	return;

    case 0x8f00:		/* bf/s label */

	CHECK_NOT_DELAY_SLOT

	gen_branch_slot(ctx->delayed_pc = ctx->pc + 4 + B7_0s * 2, 0);

	ctx->flags |= DELAY_SLOT_CONDITIONAL;

	return;

    case 0x8900:		/* bt label */

	CHECK_NOT_DELAY_SLOT

	    gen_conditional_jump(ctx, ctx->pc + 4 + B7_0s * 2,

				 ctx->pc + 2);

	ctx->bstate = BS_BRANCH;

	return;

    case 0x8d00:		/* bt/s label */

	CHECK_NOT_DELAY_SLOT

	gen_branch_slot(ctx->delayed_pc = ctx->pc + 4 + B7_0s * 2, 1);

	ctx->flags |= DELAY_SLOT_CONDITIONAL;

	return;

    case 0x8800:		/* cmp/eq #imm,R0 */

	gen_cmp_imm(TCG_COND_EQ, REG(0), B7_0s);

	return;

    case 0xc400:		/* mov.b @(disp,GBR),R0 */

	{

	    TCGv addr = tcg_temp_new();

	    tcg_gen_addi_i32(addr, cpu_gbr, B7_0);

	    tcg_gen_qemu_ld8s(REG(0), addr, ctx->memidx);

	    tcg_temp_free(addr);

	}

	return;

    case 0xc500:		/* mov.w @(disp,GBR),R0 */

	{

	    TCGv addr = tcg_temp_new();

	    tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 2);

	    tcg_gen_qemu_ld16s(REG(0), addr, ctx->memidx);

	    tcg_temp_free(addr);

	}

	return;

    case 0xc600:		/* mov.l @(disp,GBR),R0 */

	{

	    TCGv addr = tcg_temp_new();

	    tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 4);

	    tcg_gen_qemu_ld32s(REG(0), addr, ctx->memidx);

	    tcg_temp_free(addr);

	}

	return;

    case 0xc000:		/* mov.b R0,@(disp,GBR) */

	{

	    TCGv addr = tcg_temp_new();

	    tcg_gen_addi_i32(addr, cpu_gbr, B7_0);

	    tcg_gen_qemu_st8(REG(0), addr, ctx->memidx);

	    tcg_temp_free(addr);

	}

	return;

    case 0xc100:		/* mov.w R0,@(disp,GBR) */

	{

	    TCGv addr = tcg_temp_new();

	    tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 2);

	    tcg_gen_qemu_st16(REG(0), addr, ctx->memidx);

	    tcg_temp_free(addr);

	}

	return;

    case 0xc200:		/* mov.l R0,@(disp,GBR) */

	{

	    TCGv addr = tcg_temp_new();

	    tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 4);

	    tcg_gen_qemu_st32(REG(0), addr, ctx->memidx);

	    tcg_temp_free(addr);

	}

	return;

    case 0x8000:		/* mov.b R0,@(disp,Rn) */

	{

	    TCGv addr = tcg_temp_new();

	    tcg_gen_addi_i32(addr, REG(B7_4), B3_0);

	    tcg_gen_qemu_st8(REG(0), addr, ctx->memidx);

	    tcg_temp_free(addr);

	}

	return;

    case 0x8100:		/* mov.w R0,@(disp,Rn) */

	{

	    TCGv addr = tcg_temp_new();

	    tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 2);

	    tcg_gen_qemu_st16(REG(0), addr, ctx->memidx);

	    tcg_temp_free(addr);

	}

	return;

    case 0x8400:		/* mov.b @(disp,Rn),R0 */

	{

	    TCGv addr = tcg_temp_new();

	    tcg_gen_addi_i32(addr, REG(B7_4), B3_0);

	    tcg_gen_qemu_ld8s(REG(0), addr, ctx->memidx);

	    tcg_temp_free(addr);

	}

	return;

    case 0x8500:		/* mov.w @(disp,Rn),R0 */

	{

	    TCGv addr = tcg_temp_new();

	    tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 2);

	    tcg_gen_qemu_ld16s(REG(0), addr, ctx->memidx);

	    tcg_temp_free(addr);

	}

	return;

    case 0xc700:		/* mova @(disp,PC),R0 */

	tcg_gen_movi_i32(REG(0), ((ctx->pc & 0xfffffffc) + 4 + B7_0 * 4) & ~3);

	return;

    case 0xcb00:		/* or #imm,R0 */

	tcg_gen_ori_i32(REG(0), REG(0), B7_0);

	return;

    case 0xcf00:		/* or.b #imm,@(R0,GBR) */

	{

	    TCGv addr, val;

	    addr = tcg_temp_new();

	    tcg_gen_add_i32(addr, REG(0), cpu_gbr);

	    val = tcg_temp_new();

	    tcg_gen_qemu_ld8u(val, addr, ctx->memidx);

	    tcg_gen_ori_i32(val, val, B7_0);

	    tcg_gen_qemu_st8(val, addr, ctx->memidx);

	    tcg_temp_free(val);

	    tcg_temp_free(addr);

	}

	return;

    case 0xc300:		/* trapa #imm */

	{

	    TCGv imm;

	    CHECK_NOT_DELAY_SLOT

	    tcg_gen_movi_i32(cpu_pc, ctx->pc);

	    imm = tcg_const_i32(B7_0);

	    gen_helper_trapa(imm);

	    tcg_temp_free(imm);

	    ctx->bstate = BS_BRANCH;

	}

	return;

    case 0xc800:		/* tst #imm,R0 */

	{

	    TCGv val = tcg_temp_new();

	    tcg_gen_andi_i32(val, REG(0), B7_0);

	    gen_cmp_imm(TCG_COND_EQ, val, 0);

	    tcg_temp_free(val);

	}

	return;

    case 0xcc00:		/* tst.b #imm,@(R0,GBR) */

	{

	    TCGv val = tcg_temp_new();

	    tcg_gen_add_i32(val, REG(0), cpu_gbr);

	    tcg_gen_qemu_ld8u(val, val, ctx->memidx);

	    tcg_gen_andi_i32(val, val, B7_0);

	    gen_cmp_imm(TCG_COND_EQ, val, 0);

	    tcg_temp_free(val);

	}

	return;

    case 0xca00:		/* xor #imm,R0 */

	tcg_gen_xori_i32(REG(0), REG(0), B7_0);

	return;

    case 0xce00:		/* xor.b #imm,@(R0,GBR) */

	{

	    TCGv addr, val;

	    addr = tcg_temp_new();

	    tcg_gen_add_i32(addr, REG(0), cpu_gbr);

	    val = tcg_temp_new();

	    tcg_gen_qemu_ld8u(val, addr, ctx->memidx);

	    tcg_gen_xori_i32(val, val, B7_0);

	    tcg_gen_qemu_st8(val, addr, ctx->memidx);

	    tcg_temp_free(val);

	    tcg_temp_free(addr);

	}

	return;

    }

    switch (ctx->opcode & 0xf08f) {

    case 0x408e:		/* ldc Rm,Rn_BANK */

	CHECK_PRIVILEGED

	tcg_gen_mov_i32(ALTREG(B6_4), REG(B11_8));

	return;

    case 0x4087:		/* ldc.l @Rm+,Rn_BANK */

	CHECK_PRIVILEGED

	tcg_gen_qemu_ld32s(ALTREG(B6_4), REG(B11_8), ctx->memidx);

	tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);

	return;

    case 0x0082:		/* stc Rm_BANK,Rn */

	CHECK_PRIVILEGED

	tcg_gen_mov_i32(REG(B11_8), ALTREG(B6_4));

	return;

    case 0x4083:		/* stc.l Rm_BANK,@-Rn */

	CHECK_PRIVILEGED

	{

	    TCGv addr = tcg_temp_new();

	    tcg_gen_subi_i32(addr, REG(B11_8), 4);

	    tcg_gen_qemu_st32(ALTREG(B6_4), addr, ctx->memidx);

	    tcg_temp_free(addr);

	    tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4);

	}

	return;

    }

    switch (ctx->opcode & 0xf0ff) {

    case 0x0023:		/* braf Rn */

	CHECK_NOT_DELAY_SLOT

	tcg_gen_addi_i32(cpu_delayed_pc, REG(B11_8), ctx->pc + 4);

	ctx->flags |= DELAY_SLOT;

	ctx->delayed_pc = (uint32_t) - 1;

	return;

    case 0x0003:		/* bsrf Rn */

	CHECK_NOT_DELAY_SLOT

	tcg_gen_movi_i32(cpu_pr, ctx->pc + 4);

	tcg_gen_add_i32(cpu_delayed_pc, REG(B11_8), cpu_pr);

	ctx->flags |= DELAY_SLOT;

	ctx->delayed_pc = (uint32_t) - 1;

	return;

    case 0x4015:		/* cmp/pl Rn */

	gen_cmp_imm(TCG_COND_GT, REG(B11_8), 0);

	return;

    case 0x4011:		/* cmp/pz Rn */

	gen_cmp_imm(TCG_COND_GE, REG(B11_8), 0);

	return;

    case 0x4010:		/* dt Rn */

	tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 1);

	gen_cmp_imm(TCG_COND_EQ, REG(B11_8), 0);

	return;

    case 0x402b:		/* jmp @Rn */

	CHECK_NOT_DELAY_SLOT

	tcg_gen_mov_i32(cpu_delayed_pc, REG(B11_8));

	ctx->flags |= DELAY_SLOT;

	ctx->delayed_pc = (uint32_t) - 1;

	return;

    case 0x400b:		/* jsr @Rn */

	CHECK_NOT_DELAY_SLOT

	tcg_gen_movi_i32(cpu_pr, ctx->pc + 4);

	tcg_gen_mov_i32(cpu_delayed_pc, REG(B11_8));

	ctx->flags |= DELAY_SLOT;

	ctx->delayed_pc = (uint32_t) - 1;

	return;

    case 0x400e:		/* ldc Rm,SR */

	CHECK_PRIVILEGED

	tcg_gen_andi_i32(cpu_sr, REG(B11_8), 0x700083f3);

	ctx->bstate = BS_STOP;

	return;

    case 0x4007:		/* ldc.l @Rm+,SR */

	CHECK_PRIVILEGED

	{

	    TCGv val = tcg_temp_new();

	    tcg_gen_qemu_ld32s(val, REG(B11_8), ctx->memidx);

	    tcg_gen_andi_i32(cpu_sr, val, 0x700083f3);

	    tcg_temp_free(val);

	    tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);

	    ctx->bstate = BS_STOP;

	}

	return;

    case 0x0002:		/* stc SR,Rn */

	CHECK_PRIVILEGED

	tcg_gen_mov_i32(REG(B11_8), cpu_sr);

	return;

    case 0x4003:		/* stc SR,@-Rn */

	CHECK_PRIVILEGED

	{

	    TCGv addr = tcg_temp_new();

	    tcg_gen_subi_i32(addr, REG(B11_8), 4);

	    tcg_gen_qemu_st32(cpu_sr, addr, ctx->memidx);

	    tcg_temp_free(addr);

	    tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4);

	}

	return;

#define LDST(reg,ldnum,ldpnum,stnum,stpnum,prechk)		\

  case ldnum:							\

    prechk    							\

    tcg_gen_mov_i32 (cpu_##reg, REG(B11_8));			\

    return;							\

  case ldpnum:							\

    prechk    							\

    tcg_gen_qemu_ld32s (cpu_##reg, REG(B11_8), ctx->memidx);	\

    tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);		\

    return;							\

  case stnum:							\

    prechk    							\

    tcg_gen_mov_i32 (REG(B11_8), cpu_##reg);			\

    return;							\

  case stpnum:							\

    prechk    							\

    {								\

	TCGv addr = tcg_temp_new();			\

	tcg_gen_subi_i32(addr, REG(B11_8), 4);			\

	tcg_gen_qemu_st32 (cpu_##reg, addr, ctx->memidx);	\

	tcg_temp_free(addr);					\

	tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4);		\

    }								\

    return;

	LDST(gbr,  0x401e, 0x4017, 0x0012, 0x4013, {})

	LDST(vbr,  0x402e, 0x4027, 0x0022, 0x4023, CHECK_PRIVILEGED)

	LDST(ssr,  0x403e, 0x4037, 0x0032, 0x4033, CHECK_PRIVILEGED)

	LDST(spc,  0x404e, 0x4047, 0x0042, 0x4043, CHECK_PRIVILEGED)

	LDST(dbr,  0x40fa, 0x40f6, 0x00fa, 0x40f2, CHECK_PRIVILEGED)

	LDST(mach, 0x400a, 0x4006, 0x000a, 0x4002, {})

	LDST(macl, 0x401a, 0x4016, 0x001a, 0x4012, {})

	LDST(pr,   0x402a, 0x4026, 0x002a, 0x4022, {})

	LDST(fpul, 0x405a, 0x4056, 0x005a, 0x4052, {CHECK_FPU_ENABLED})

    case 0x406a:		/* lds Rm,FPSCR */

	CHECK_FPU_ENABLED

	gen_helper_ld_fpscr(REG(B11_8));

	ctx->bstate = BS_STOP;

	return;

    case 0x4066:		/* lds.l @Rm+,FPSCR */

	CHECK_FPU_ENABLED

	{

	    TCGv addr = tcg_temp_new();

	    tcg_gen_qemu_ld32s(addr, REG(B11_8), ctx->memidx);

	    tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);

	    gen_helper_ld_fpscr(addr);

	    tcg_temp_free(addr);

	    ctx->bstate = BS_STOP;

	}

	return;

    case 0x006a:		/* sts FPSCR,Rn */

	CHECK_FPU_ENABLED

	tcg_gen_andi_i32(REG(B11_8), cpu_fpscr, 0x003fffff);

	return;

    case 0x4062:		/* sts FPSCR,@-Rn */

	CHECK_FPU_ENABLED

	{

	    TCGv addr, val;

	    val = tcg_temp_new();

	    tcg_gen_andi_i32(val, cpu_fpscr, 0x003fffff);

	    addr = tcg_temp_new();

	    tcg_gen_subi_i32(addr, REG(B11_8), 4);

	    tcg_gen_qemu_st32(val, addr, ctx->memidx);

	    tcg_temp_free(addr);

	    tcg_temp_free(val);

	    tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4);

	}

	return;

    case 0x00c3:		/* movca.l R0,@Rm */

	tcg_gen_qemu_st32(REG(0), REG(B11_8), ctx->memidx);

	return;

    case 0x40a9:

	/* MOVUA.L @Rm,R0 (Rm) -> R0

	   Load non-boundary-aligned data */

	tcg_gen_qemu_ld32u(REG(0), REG(B11_8), ctx->memidx);

	return;

    case 0x40e9:

	/* MOVUA.L @Rm+,R0   (Rm) -> R0, Rm + 4 -> Rm

	   Load non-boundary-aligned data */

	tcg_gen_qemu_ld32u(REG(0), REG(B11_8), ctx->memidx);

	tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);

	return;

    case 0x0029:		/* movt Rn */

	tcg_gen_andi_i32(REG(B11_8), cpu_sr, SR_T);

	return;

    case 0x0073:

        /* MOVCO.L

	       LDST -> T

               If (T == 1) R0 -> (Rn)

               0 -> LDST

        */

        if (ctx->features & SH_FEATURE_SH4A) {

	    int label = gen_new_label();

	    gen_clr_t();

	    tcg_gen_or_i32(cpu_sr, cpu_sr, cpu_ldst);

	    tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_ldst, 0, label);

	    tcg_gen_qemu_st32(REG(0), REG(B11_8), ctx->memidx);

	    gen_set_label(label);

	    tcg_gen_movi_i32(cpu_ldst, 0);

	    return;

	} else

	    break;

    case 0x0063:

        /* MOVLI.L @Rm,R0

               1 -> LDST

               (Rm) -> R0

               When interrupt/exception

               occurred 0 -> LDST

        */

	if (ctx->features & SH_FEATURE_SH4A) {

	    tcg_gen_movi_i32(cpu_ldst, 0);

	    tcg_gen_qemu_ld32s(REG(0), REG(B11_8), ctx->memidx);

	    tcg_gen_movi_i32(cpu_ldst, 1);

	    return;

	} else

	    break;

    case 0x0093:		/* ocbi @Rn */

	{

	    TCGv dummy = tcg_temp_new();

	    tcg_gen_qemu_ld32s(dummy, REG(B11_8), ctx->memidx);

	    tcg_temp_free(dummy);

	}

	return;

    case 0x00a3:		/* ocbp @Rn */

	{

	    TCGv dummy = tcg_temp_new();

	    tcg_gen_qemu_ld32s(dummy, REG(B11_8), ctx->memidx);

	    tcg_temp_free(dummy);

	}

	return;

    case 0x00b3:		/* ocbwb @Rn */

	{

	    TCGv dummy = tcg_temp_new();

	    tcg_gen_qemu_ld32s(dummy, REG(B11_8), ctx->memidx);

	    tcg_temp_free(dummy);

	}

	return;

    case 0x0083:		/* pref @Rn */

	return;

    case 0x00d3:		/* prefi @Rn */

	if (ctx->features & SH_FEATURE_SH4A)

	    return;

	else

	    break;

    case 0x00e3:		/* icbi @Rn */

	if (ctx->features & SH_FEATURE_SH4A)

	    return;

	else

	    break;

    case 0x00ab:		/* synco */

	if (ctx->features & SH_FEATURE_SH4A)

	    return;

	else

	    break;

    case 0x4024:		/* rotcl Rn */

	{

	    TCGv tmp = tcg_temp_new();

	    tcg_gen_mov_i32(tmp, cpu_sr);

	    gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 31);

	    tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 1);

	    gen_copy_bit_i32(REG(B11_8), 0, tmp, 0);

	    tcg_temp_free(tmp);

	}

	return;

    case 0x4025:		/* rotcr Rn */

	{

	    TCGv tmp = tcg_temp_new();

	    tcg_gen_mov_i32(tmp, cpu_sr);

	    gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0);

	    tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 1);

	    gen_copy_bit_i32(REG(B11_8), 31, tmp, 0);

	    tcg_temp_free(tmp);

	}

	return;

    case 0x4004:		/* rotl Rn */

	gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 31);

	tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 1);

	gen_copy_bit_i32(REG(B11_8), 0, cpu_sr, 0);

	return;

    case 0x4005:		/* rotr Rn */

	gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0);

	tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 1);

	gen_copy_bit_i32(REG(B11_8), 31, cpu_sr, 0);

	return;

    case 0x4000:		/* shll Rn */

    case 0x4020:		/* shal Rn */

	gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 31);

	tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 1);

	return;

    case 0x4021:		/* shar Rn */

	gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0);

	tcg_gen_sari_i32(REG(B11_8), REG(B11_8), 1);

	return;

    case 0x4001:		/* shlr Rn */

	gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0);

	tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 1);

	return;

    case 0x4008:		/* shll2 Rn */

	tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 2);

	return;

    case 0x4018:		/* shll8 Rn */

	tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 8);

	return;

    case 0x4028:		/* shll16 Rn */

	tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 16);

	return;

    case 0x4009:		/* shlr2 Rn */

	tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 2);

	return;

    case 0x4019:		/* shlr8 Rn */

	tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 8);

	return;

    case 0x4029:		/* shlr16 Rn */

	tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 16);

	return;

    case 0x401b:		/* tas.b @Rn */

	{

	    TCGv addr, val;

	    addr = tcg_temp_local_new();

	    tcg_gen_mov_i32(addr, REG(B11_8));

	    val = tcg_temp_local_new();

	    tcg_gen_qemu_ld8u(val, addr, ctx->memidx);

	    gen_cmp_imm(TCG_COND_EQ, val, 0);

	    tcg_gen_ori_i32(val, val, 0x80);

	    tcg_gen_qemu_st8(val, addr, ctx->memidx);

	    tcg_temp_free(val);

	    tcg_temp_free(addr);

	}

	return;

    case 0xf00d: /* fsts FPUL,FRn - FPSCR: Nothing */

	CHECK_FPU_ENABLED

	tcg_gen_mov_i32(cpu_fregs[FREG(B11_8)], cpu_fpul);

	return;

    case 0xf01d: /* flds FRm,FPUL - FPSCR: Nothing */

	CHECK_FPU_ENABLED

	tcg_gen_mov_i32(cpu_fpul, cpu_fregs[FREG(B11_8)]);

	return;

    case 0xf02d: /* float FPUL,FRn/DRn - FPSCR: R[PR,Enable.I]/W[Cause,Flag] */

	CHECK_FPU_ENABLED

	if (ctx->fpscr & FPSCR_PR) {

	    TCGv_i64 fp;

	    if (ctx->opcode & 0x0100)

		break; /* illegal instruction */

	    fp = tcg_temp_new_i64();

	    gen_helper_float_DT(fp, cpu_fpul);

	    gen_store_fpr64(fp, DREG(B11_8));

	    tcg_temp_free_i64(fp);

	}

	else {

	    gen_helper_float_FT(cpu_fregs[FREG(B11_8)], cpu_fpul);

	}

	return;

    case 0xf03d: /* ftrc FRm/DRm,FPUL - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */

	CHECK_FPU_ENABLED

	if (ctx->fpscr & FPSCR_PR) {

	    TCGv_i64 fp;

	    if (ctx->opcode & 0x0100)

		break; /* illegal instruction */

	    fp = tcg_temp_new_i64();

	    gen_load_fpr64(fp, DREG(B11_8));

	    gen_helper_ftrc_DT(cpu_fpul, fp);

	    tcg_temp_free_i64(fp);

	}

	else {

	    gen_helper_ftrc_FT(cpu_fpul, cpu_fregs[FREG(B11_8)]);

	}

	return;

    case 0xf04d: /* fneg FRn/DRn - FPSCR: Nothing */

	CHECK_FPU_ENABLED

	{

	    gen_helper_fneg_T(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)]);

	}

	return;

    case 0xf05d: /* fabs FRn/DRn */

	CHECK_FPU_ENABLED

	if (ctx->fpscr & FPSCR_PR) {

	    if (ctx->opcode & 0x0100)

		break; /* illegal instruction */

	    TCGv_i64 fp = tcg_temp_new_i64();

	    gen_load_fpr64(fp, DREG(B11_8));

	    gen_helper_fabs_DT(fp, fp);

	    gen_store_fpr64(fp, DREG(B11_8));

	    tcg_temp_free_i64(fp);

	} else {

	    gen_helper_fabs_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)]);

	}

	return;

    case 0xf06d: /* fsqrt FRn */

	CHECK_FPU_ENABLED

	if (ctx->fpscr & FPSCR_PR) {

	    if (ctx->opcode & 0x0100)

		break; /* illegal instruction */

	    TCGv_i64 fp = tcg_temp_new_i64();

	    gen_load_fpr64(fp, DREG(B11_8));

	    gen_helper_fsqrt_DT(fp, fp);

	    gen_store_fpr64(fp, DREG(B11_8));

	    tcg_temp_free_i64(fp);

	} else {

	    gen_helper_fsqrt_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)]);

	}

	return;

    case 0xf07d: /* fsrra FRn */

	CHECK_FPU_ENABLED

	break;

    case 0xf08d: /* fldi0 FRn - FPSCR: R[PR] */

	CHECK_FPU_ENABLED

	if (!(ctx->fpscr & FPSCR_PR)) {

	    tcg_gen_movi_i32(cpu_fregs[FREG(B11_8)], 0);

	}

	return;

    case 0xf09d: /* fldi1 FRn - FPSCR: R[PR] */

	CHECK_FPU_ENABLED

	if (!(ctx->fpscr & FPSCR_PR)) {

	    tcg_gen_movi_i32(cpu_fregs[FREG(B11_8)], 0x3f800000);

	}

	return;

    case 0xf0ad: /* fcnvsd FPUL,DRn */

	CHECK_FPU_ENABLED

	{

	    TCGv_i64 fp = tcg_temp_new_i64();

	    gen_helper_fcnvsd_FT_DT(fp, cpu_fpul);

	    gen_store_fpr64(fp, DREG(B11_8));

	    tcg_temp_free_i64(fp);

	}

	return;

    case 0xf0bd: /* fcnvds DRn,FPUL */

	CHECK_FPU_ENABLED

	{

	    TCGv_i64 fp = tcg_temp_new_i64();

	    gen_load_fpr64(fp, DREG(B11_8));

	    gen_helper_fcnvds_DT_FT(cpu_fpul, fp);

	    tcg_temp_free_i64(fp);

	}

	return;

    }

#if 0

    fprintf(stderr, "unknown instruction 0x%04x at pc 0x%08x\n",

	    ctx->opcode, ctx->pc);

    fflush(stderr);

#endif

    gen_helper_raise_illegal_instruction();

    ctx->bstate = BS_EXCP;

}


static void *spapr_create_fdt_skel(const char *cpu_model,

                                   target_phys_addr_t initrd_base,

                                   target_phys_addr_t initrd_size,

                                   const char *boot_device,

                                   const char *kernel_cmdline,

                                   long hash_shift)

{

    void *fdt;

    CPUState *env;

    uint64_t mem_reg_property[] = { 0, cpu_to_be64(ram_size) };

    uint32_t start_prop = cpu_to_be32(initrd_base);

    uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size);

    uint32_t pft_size_prop[] = {0, cpu_to_be32(hash_shift)};

    char hypertas_prop[] = "hcall-pft\0hcall-term\0hcall-dabr\0hcall-interrupt"

        "\0hcall-tce\0hcall-vio\0hcall-splpar";

    uint32_t interrupt_server_ranges_prop[] = {0, cpu_to_be32(smp_cpus)};

    int i;

    char *modelname;

#define _FDT(exp) \

    do { \

        int ret = (exp);                                           \

        if (ret < 0) {                                             \

            fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \

                    #exp, fdt_strerror(ret));                      \

            exit(1);                                               \

        }                                                          \

    } while (0)

    fdt = g_malloc0(FDT_MAX_SIZE);

    _FDT((fdt_create(fdt, FDT_MAX_SIZE)));

    _FDT((fdt_finish_reservemap(fdt)));

    /* Root node */

    _FDT((fdt_begin_node(fdt, "")));

    _FDT((fdt_property_string(fdt, "device_type", "chrp")));

    _FDT((fdt_property_string(fdt, "model", "IBM pSeries (emulated by qemu)")));

    _FDT((fdt_property_cell(fdt, "#address-cells", 0x2)));

    _FDT((fdt_property_cell(fdt, "#size-cells", 0x2)));

    /* /chosen */

    _FDT((fdt_begin_node(fdt, "chosen")));

    _FDT((fdt_property_string(fdt, "bootargs", kernel_cmdline)));

    _FDT((fdt_property(fdt, "linux,initrd-start",

                       &start_prop, sizeof(start_prop))));

    _FDT((fdt_property(fdt, "linux,initrd-end",

                       &end_prop, sizeof(end_prop))));

    _FDT((fdt_property_string(fdt, "qemu,boot-device", boot_device)));

    _FDT((fdt_end_node(fdt)));

    /* memory node */

    _FDT((fdt_begin_node(fdt, "memory@0")));

    _FDT((fdt_property_string(fdt, "device_type", "memory")));

    _FDT((fdt_property(fdt, "reg",

                       mem_reg_property, sizeof(mem_reg_property))));

    _FDT((fdt_end_node(fdt)));

    /* cpus */

    _FDT((fdt_begin_node(fdt, "cpus")));

    _FDT((fdt_property_cell(fdt, "#address-cells", 0x1)));

    _FDT((fdt_property_cell(fdt, "#size-cells", 0x0)));

    modelname = g_strdup(cpu_model);

    for (i = 0; i < strlen(modelname); i++) {

        modelname[i] = toupper(modelname[i]);

    }

    for (env = first_cpu; env != NULL; env = env->next_cpu) {

        int index = env->cpu_index;

        uint32_t gserver_prop[] = {cpu_to_be32(index), 0}; /* HACK! */

        char *nodename;

        uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),

                           0xffffffff, 0xffffffff};

        uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() : TIMEBASE_FREQ;

        uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;

        if (asprintf(&nodename, "%s@%x", modelname, index) < 0) {

            fprintf(stderr, "Allocation failure\n");

            exit(1);

        }

        _FDT((fdt_begin_node(fdt, nodename)));

        free(nodename);

        _FDT((fdt_property_cell(fdt, "reg", index)));

        _FDT((fdt_property_string(fdt, "device_type", "cpu")));

        _FDT((fdt_property_cell(fdt, "cpu-version", env->spr[SPR_PVR])));

        _FDT((fdt_property_cell(fdt, "dcache-block-size",

                                env->dcache_line_size)));

        _FDT((fdt_property_cell(fdt, "icache-block-size",

                                env->icache_line_size)));

        _FDT((fdt_property_cell(fdt, "timebase-frequency", tbfreq)));

        _FDT((fdt_property_cell(fdt, "clock-frequency", cpufreq)));

        _FDT((fdt_property_cell(fdt, "ibm,slb-size", env->slb_nr)));

        _FDT((fdt_property(fdt, "ibm,pft-size",

                           pft_size_prop, sizeof(pft_size_prop))));

        _FDT((fdt_property_string(fdt, "status", "okay")));

        _FDT((fdt_property(fdt, "64-bit", NULL, 0)));

        _FDT((fdt_property_cell(fdt, "ibm,ppc-interrupt-server#s", index)));

        _FDT((fdt_property(fdt, "ibm,ppc-interrupt-gserver#s",

                           gserver_prop, sizeof(gserver_prop))));

        if (env->mmu_model & POWERPC_MMU_1TSEG) {

            _FDT((fdt_property(fdt, "ibm,processor-segment-sizes",

                               segs, sizeof(segs))));

        }

        _FDT((fdt_end_node(fdt)));

    }

    g_free(modelname);

    _FDT((fdt_end_node(fdt)));

    /* RTAS */

    _FDT((fdt_begin_node(fdt, "rtas")));

    _FDT((fdt_property(fdt, "ibm,hypertas-functions", hypertas_prop,

                       sizeof(hypertas_prop))));

    _FDT((fdt_end_node(fdt)));

    /* interrupt controller */

    _FDT((fdt_begin_node(fdt, "interrupt-controller@0")));

    _FDT((fdt_property_string(fdt, "device_type",

                              "PowerPC-External-Interrupt-Presentation")));

    _FDT((fdt_property_string(fdt, "compatible", "IBM,ppc-xicp")));

    _FDT((fdt_property_cell(fdt, "reg", 0)));

    _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0)));

    _FDT((fdt_property(fdt, "ibm,interrupt-server-ranges",

                       interrupt_server_ranges_prop,

                       sizeof(interrupt_server_ranges_prop))));

    _FDT((fdt_property_cell(fdt, "#interrupt-cells", 2)));

    _FDT((fdt_property_cell(fdt, "linux,phandle", PHANDLE_XICP)));

    _FDT((fdt_property_cell(fdt, "phandle", PHANDLE_XICP)));

    _FDT((fdt_end_node(fdt)));

    /* vdevice */

    _FDT((fdt_begin_node(fdt, "vdevice")));

    _FDT((fdt_property_string(fdt, "device_type", "vdevice")));

    _FDT((fdt_property_string(fdt, "compatible", "IBM,vdevice")));

    _FDT((fdt_property_cell(fdt, "#address-cells", 0x1)));

    _FDT((fdt_property_cell(fdt, "#size-cells", 0x0)));

    _FDT((fdt_property_cell(fdt, "#interrupt-cells", 0x2)));

    _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0)));

    _FDT((fdt_end_node(fdt)));

    _FDT((fdt_end_node(fdt))); /* close root node */

    _FDT((fdt_finish(fdt)));

    return fdt;

}


static int decode_extradata_ps(const uint8_t *data, int size, H264ParamSets *ps,

                               int is_avc, void *logctx)

{

    H2645Packet pkt = { 0 };

    int i, ret = 0;

    ret = ff_h2645_packet_split(&pkt, data, size, logctx, is_avc, 2, AV_CODEC_ID_H264);

    if (ret < 0) {

        ret = 0;

        goto fail;

    }

    for (i = 0; i < pkt.nb_nals; i++) {

        H2645NAL *nal = &pkt.nals[i];

        switch (nal->type) {

        case H264_NAL_SPS:

            ret = ff_h264_decode_seq_parameter_set(&nal->gb, logctx, ps, 0);

            if (ret < 0)

                goto fail;

            break;

        case H264_NAL_PPS:

            ret = ff_h264_decode_picture_parameter_set(&nal->gb, logctx, ps,

                                                       nal->size_bits);

            if (ret < 0)

                goto fail;

            break;

        default:

            av_log(logctx, AV_LOG_VERBOSE, "Ignoring NAL type %d in extradata\n",

                   nal->type);

            break;

        }

    }

fail:

    ff_h2645_packet_uninit(&pkt);

    return ret;

}


int qcow2_get_cluster_offset(BlockDriverState *bs, uint64_t offset,

                             unsigned int *bytes, uint64_t *cluster_offset)

{

    BDRVQcow2State *s = bs->opaque;

    unsigned int l2_index;

    uint64_t l1_index, l2_offset, *l2_table;

    int l1_bits, c;

    unsigned int offset_in_cluster, nb_clusters;

    uint64_t bytes_available, bytes_needed;

    int ret;

    offset_in_cluster = offset_into_cluster(s, offset);

    bytes_needed = (uint64_t) *bytes + offset_in_cluster;

    l1_bits = s->l2_bits + s->cluster_bits;

    /* compute how many bytes there are between the start of the cluster

     * containing offset and the end of the l1 entry */

    bytes_available = (1ULL << l1_bits) - (offset & ((1ULL << l1_bits) - 1))

                    + offset_in_cluster;

    if (bytes_needed > bytes_available) {

        bytes_needed = bytes_available;

    }

    assert(bytes_needed <= INT_MAX);

    *cluster_offset = 0;

    /* seek to the l2 offset in the l1 table */

    l1_index = offset >> l1_bits;

    if (l1_index >= s->l1_size) {

        ret = QCOW2_CLUSTER_UNALLOCATED;

        goto out;

    }

    l2_offset = s->l1_table[l1_index] & L1E_OFFSET_MASK;

    if (!l2_offset) {

        ret = QCOW2_CLUSTER_UNALLOCATED;

        goto out;

    }

    if (offset_into_cluster(s, l2_offset)) {

        qcow2_signal_corruption(bs, true, -1, -1, "L2 table offset %#" PRIx64

                                " unaligned (L1 index: %#" PRIx64 ")",

                                l2_offset, l1_index);

        return -EIO;

    }

    /* load the l2 table in memory */

    ret = l2_load(bs, l2_offset, &l2_table);

    if (ret < 0) {

        return ret;

    }

    /* find the cluster offset for the given disk offset */

    l2_index = (offset >> s->cluster_bits) & (s->l2_size - 1);

    *cluster_offset = be64_to_cpu(l2_table[l2_index]);

    /* nb_needed <= INT_MAX, thus nb_clusters <= INT_MAX, too */

    nb_clusters = size_to_clusters(s, bytes_needed);

    ret = qcow2_get_cluster_type(*cluster_offset);

    switch (ret) {

    case QCOW2_CLUSTER_COMPRESSED:

        /* Compressed clusters can only be processed one by one */

        c = 1;

        *cluster_offset &= L2E_COMPRESSED_OFFSET_SIZE_MASK;

        break;

    case QCOW2_CLUSTER_ZERO:

        if (s->qcow_version < 3) {

            qcow2_signal_corruption(bs, true, -1, -1, "Zero cluster entry found"

                                    " in pre-v3 image (L2 offset: %#" PRIx64

                                    ", L2 index: %#x)", l2_offset, l2_index);

            ret = -EIO;

            goto fail;

        }

        c = count_contiguous_clusters_by_type(nb_clusters, &l2_table[l2_index],

                                              QCOW2_CLUSTER_ZERO);

        *cluster_offset = 0;

        break;

    case QCOW2_CLUSTER_UNALLOCATED:

        /* how many empty clusters ? */

        c = count_contiguous_clusters_by_type(nb_clusters, &l2_table[l2_index],

                                              QCOW2_CLUSTER_UNALLOCATED);

        *cluster_offset = 0;

        break;

    case QCOW2_CLUSTER_NORMAL:

        /* how many allocated clusters ? */

        c = count_contiguous_clusters(nb_clusters, s->cluster_size,

                &l2_table[l2_index], QCOW_OFLAG_ZERO);

        *cluster_offset &= L2E_OFFSET_MASK;

        if (offset_into_cluster(s, *cluster_offset)) {

            qcow2_signal_corruption(bs, true, -1, -1, "Data cluster offset %#"

                                    PRIx64 " unaligned (L2 offset: %#" PRIx64

                                    ", L2 index: %#x)", *cluster_offset,

                                    l2_offset, l2_index);

            ret = -EIO;

            goto fail;

        }

        break;

    default:

        abort();

    }

    qcow2_cache_put(bs, s->l2_table_cache, (void**) &l2_table);

    bytes_available = (c * s->cluster_size);

out:

    if (bytes_available > bytes_needed) {

        bytes_available = bytes_needed;

    }

    *bytes = bytes_available - offset_in_cluster;

    return ret;

fail:

    qcow2_cache_put(bs, s->l2_table_cache, (void **)&l2_table);

    return ret;

}


int ff_qsv_decode_init(AVCodecContext *avctx, QSVContext *q, mfxSession session)

{

    mfxVideoParam param = { { 0 } };

    int ret;

    q->async_fifo = av_fifo_alloc((1 + q->async_depth) *

                                  (sizeof(mfxSyncPoint) + sizeof(QSVFrame*)));

    if (!q->async_fifo)

        return AVERROR(ENOMEM);

    ret = qsv_init_session(avctx, q, session);

    if (ret < 0) {

        av_log(avctx, AV_LOG_ERROR, "Error initializing an MFX session\n");

        return ret;

    }

    ret = ff_qsv_codec_id_to_mfx(avctx->codec_id);

    if (ret < 0)

        return ret;

    param.mfx.CodecId      = ret;

    param.mfx.CodecProfile = avctx->profile;

    param.mfx.CodecLevel   = avctx->level;

    param.mfx.FrameInfo.BitDepthLuma   = 8;

    param.mfx.FrameInfo.BitDepthChroma = 8;

    param.mfx.FrameInfo.Shift          = 0;

    param.mfx.FrameInfo.FourCC         = MFX_FOURCC_NV12;

    param.mfx.FrameInfo.Width          = avctx->coded_width;

    param.mfx.FrameInfo.Height         = avctx->coded_height;

    param.mfx.FrameInfo.ChromaFormat   = MFX_CHROMAFORMAT_YUV420;

    param.IOPattern   = q->iopattern;

    param.AsyncDepth  = q->async_depth;

    param.ExtParam    = q->ext_buffers;

    param.NumExtParam = q->nb_ext_buffers;

    ret = MFXVideoDECODE_Init(q->session, &param);

    if (ret < 0) {

        av_log(avctx, AV_LOG_ERROR, "Error initializing the MFX video decoder\n");

        return ff_qsv_error(ret);

    }

    return 0;

}


static int kvm_init(MachineState *ms)

{

    MachineClass *mc = MACHINE_GET_CLASS(ms);

    static const char upgrade_note[] =

        "Please upgrade to at least kernel 2.6.29 or recent kvm-kmod\n"

        "(see http://sourceforge.net/projects/kvm).\n";

    struct {

        const char *name;

        int num;

    } num_cpus[] = {

        { "SMP",          smp_cpus },

        { "hotpluggable", max_cpus },

        { NULL, }

    }, *nc = num_cpus;

    int soft_vcpus_limit, hard_vcpus_limit;

    KVMState *s;

    const KVMCapabilityInfo *missing_cap;

    int ret;

    int i, type = 0;

    const char *kvm_type;

    s = KVM_STATE(ms->accelerator);

    /*

     * On systems where the kernel can support different base page

     * sizes, host page size may be different from TARGET_PAGE_SIZE,

     * even with KVM.  TARGET_PAGE_SIZE is assumed to be the minimum

     * page size for the system though.

     */

    assert(TARGET_PAGE_SIZE <= getpagesize());

    page_size_init();

    s->sigmask_len = 8;

#ifdef KVM_CAP_SET_GUEST_DEBUG

    QTAILQ_INIT(&s->kvm_sw_breakpoints);

#endif

    s->vmfd = -1;

    s->fd = qemu_open("/dev/kvm", O_RDWR);

    if (s->fd == -1) {

        fprintf(stderr, "Could not access KVM kernel module: %m\n");

        ret = -errno;

        goto err;

    }

    ret = kvm_ioctl(s, KVM_GET_API_VERSION, 0);

    if (ret < KVM_API_VERSION) {

        if (ret >= 0) {

            ret = -EINVAL;

        }

        fprintf(stderr, "kvm version too old\n");

        goto err;

    }

    if (ret > KVM_API_VERSION) {

        ret = -EINVAL;

        fprintf(stderr, "kvm version not supported\n");

        goto err;

    }

    s->nr_slots = kvm_check_extension(s, KVM_CAP_NR_MEMSLOTS);

    /* If unspecified, use the default value */

    if (!s->nr_slots) {

        s->nr_slots = 32;

    }

    s->slots = g_malloc0(s->nr_slots * sizeof(KVMSlot));

    for (i = 0; i < s->nr_slots; i++) {

        s->slots[i].slot = i;

    }

    /* check the vcpu limits */

    soft_vcpus_limit = kvm_recommended_vcpus(s);

    hard_vcpus_limit = kvm_max_vcpus(s);

    while (nc->name) {

        if (nc->num > soft_vcpus_limit) {

            fprintf(stderr,

                    "Warning: Number of %s cpus requested (%d) exceeds "

                    "the recommended cpus supported by KVM (%d)\n",

                    nc->name, nc->num, soft_vcpus_limit);

            if (nc->num > hard_vcpus_limit) {

                fprintf(stderr, "Number of %s cpus requested (%d) exceeds "

                        "the maximum cpus supported by KVM (%d)\n",

                        nc->name, nc->num, hard_vcpus_limit);

                exit(1);

            }

        }

        nc++;

    }

    kvm_type = qemu_opt_get(qemu_get_machine_opts(), "kvm-type");

    if (mc->kvm_type) {

        type = mc->kvm_type(kvm_type);

    } else if (kvm_type) {

        ret = -EINVAL;

        fprintf(stderr, "Invalid argument kvm-type=%s\n", kvm_type);

        goto err;

    }

    do {

        ret = kvm_ioctl(s, KVM_CREATE_VM, type);

    } while (ret == -EINTR);

    if (ret < 0) {

        fprintf(stderr, "ioctl(KVM_CREATE_VM) failed: %d %s\n", -ret,

                strerror(-ret));

#ifdef TARGET_S390X

        fprintf(stderr, "Please add the 'switch_amode' kernel parameter to "

                        "your host kernel command line\n");

#endif

        goto err;

    }

    s->vmfd = ret;

    missing_cap = kvm_check_extension_list(s, kvm_required_capabilites);

    if (!missing_cap) {

        missing_cap =

            kvm_check_extension_list(s, kvm_arch_required_capabilities);

    }

    if (missing_cap) {

        ret = -EINVAL;

        fprintf(stderr, "kvm does not support %s\n%s",

                missing_cap->name, upgrade_note);

        goto err;

    }

    s->coalesced_mmio = kvm_check_extension(s, KVM_CAP_COALESCED_MMIO);

    s->broken_set_mem_region = 1;

    ret = kvm_check_extension(s, KVM_CAP_JOIN_MEMORY_REGIONS_WORKS);

    if (ret > 0) {

        s->broken_set_mem_region = 0;

    }

#ifdef KVM_CAP_VCPU_EVENTS

    s->vcpu_events = kvm_check_extension(s, KVM_CAP_VCPU_EVENTS);

#endif

    s->robust_singlestep =

        kvm_check_extension(s, KVM_CAP_X86_ROBUST_SINGLESTEP);

#ifdef KVM_CAP_DEBUGREGS

    s->debugregs = kvm_check_extension(s, KVM_CAP_DEBUGREGS);

#endif

#ifdef KVM_CAP_XSAVE

    s->xsave = kvm_check_extension(s, KVM_CAP_XSAVE);

#endif

#ifdef KVM_CAP_XCRS

    s->xcrs = kvm_check_extension(s, KVM_CAP_XCRS);

#endif

#ifdef KVM_CAP_PIT_STATE2

    s->pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);

#endif

#ifdef KVM_CAP_IRQ_ROUTING

    s->direct_msi = (kvm_check_extension(s, KVM_CAP_SIGNAL_MSI) > 0);

#endif

    s->intx_set_mask = kvm_check_extension(s, KVM_CAP_PCI_2_3);

    s->irq_set_ioctl = KVM_IRQ_LINE;

    if (kvm_check_extension(s, KVM_CAP_IRQ_INJECT_STATUS)) {

        s->irq_set_ioctl = KVM_IRQ_LINE_STATUS;

    }

#ifdef KVM_CAP_READONLY_MEM

    kvm_readonly_mem_allowed =

        (kvm_check_extension(s, KVM_CAP_READONLY_MEM) > 0);

#endif

    kvm_eventfds_allowed =

        (kvm_check_extension(s, KVM_CAP_IOEVENTFD) > 0);

    kvm_irqfds_allowed =

        (kvm_check_extension(s, KVM_CAP_IRQFD) > 0);

    kvm_resamplefds_allowed =

        (kvm_check_extension(s, KVM_CAP_IRQFD_RESAMPLE) > 0);

    ret = kvm_arch_init(s);

    if (ret < 0) {

        goto err;

    }

    ret = kvm_irqchip_create(s);

    if (ret < 0) {

        goto err;

    }

    kvm_state = s;

    memory_listener_register(&kvm_memory_listener, &address_space_memory);

    memory_listener_register(&kvm_io_listener, &address_space_io);

    s->many_ioeventfds = kvm_check_many_ioeventfds();

    cpu_interrupt_handler = kvm_handle_interrupt;

    return 0;

err:

    assert(ret < 0);

    if (s->vmfd >= 0) {

        close(s->vmfd);

    }

    if (s->fd != -1) {

        close(s->fd);

    }

    g_free(s->slots);

    return ret;

}


int ff_msmpeg4_decode_init(MpegEncContext *s)

{

    static int done = 0;

    int i;

    MVTable *mv;

    common_init(s);

    if (!done) {

        done = 1;

        for(i=0;i<NB_RL_TABLES;i++) {

            init_rl(&rl_table[i]);

            init_vlc_rl(&rl_table[i]);

        }

        for(i=0;i<2;i++) {

            mv = &mv_tables[i];

            init_vlc(&mv->vlc, MV_VLC_BITS, mv->n + 1,

                     mv->table_mv_bits, 1, 1,

                     mv->table_mv_code, 2, 2);

        }

        init_vlc(&dc_lum_vlc[0], DC_VLC_BITS, 120,

                 &table0_dc_lum[0][1], 8, 4,

                 &table0_dc_lum[0][0], 8, 4);

        init_vlc(&dc_chroma_vlc[0], DC_VLC_BITS, 120,

                 &table0_dc_chroma[0][1], 8, 4,

                 &table0_dc_chroma[0][0], 8, 4);

        init_vlc(&dc_lum_vlc[1], DC_VLC_BITS, 120,

                 &table1_dc_lum[0][1], 8, 4,

                 &table1_dc_lum[0][0], 8, 4);

        init_vlc(&dc_chroma_vlc[1], DC_VLC_BITS, 120,

                 &table1_dc_chroma[0][1], 8, 4,

                 &table1_dc_chroma[0][0], 8, 4);

        init_vlc(&v2_dc_lum_vlc, DC_VLC_BITS, 512,

                 &v2_dc_lum_table[0][1], 8, 4,

                 &v2_dc_lum_table[0][0], 8, 4);

        init_vlc(&v2_dc_chroma_vlc, DC_VLC_BITS, 512,

                 &v2_dc_chroma_table[0][1], 8, 4,

                 &v2_dc_chroma_table[0][0], 8, 4);

        init_vlc(&cbpy_vlc, CBPY_VLC_BITS, 16,

                 &cbpy_tab[0][1], 2, 1,

                 &cbpy_tab[0][0], 2, 1);

        init_vlc(&v2_intra_cbpc_vlc, V2_INTRA_CBPC_VLC_BITS, 4,

                 &v2_intra_cbpc[0][1], 2, 1,

                 &v2_intra_cbpc[0][0], 2, 1);

        init_vlc(&v2_mb_type_vlc, V2_MB_TYPE_VLC_BITS, 8,

                 &v2_mb_type[0][1], 2, 1,

                 &v2_mb_type[0][0], 2, 1);

        init_vlc(&v2_mv_vlc, V2_MV_VLC_BITS, 33,

                 &mvtab[0][1], 2, 1,

                 &mvtab[0][0], 2, 1);

        for(i=0; i<4; i++){

            init_vlc(&mb_non_intra_vlc[i], MB_NON_INTRA_VLC_BITS, 128,

                     &wmv2_inter_table[i][0][1], 8, 4,

                     &wmv2_inter_table[i][0][0], 8, 4); //FIXME name?

        }

        init_vlc(&mb_intra_vlc, MB_INTRA_VLC_BITS, 64,

                 &table_mb_intra[0][1], 4, 2,

                 &table_mb_intra[0][0], 4, 2);

        init_vlc(&v1_intra_cbpc_vlc, V1_INTRA_CBPC_VLC_BITS, 8,

                 intra_MCBPC_bits, 1, 1,

                 intra_MCBPC_code, 1, 1);

        init_vlc(&v1_inter_cbpc_vlc, V1_INTER_CBPC_VLC_BITS, 25,

                 inter_MCBPC_bits, 1, 1,

                 inter_MCBPC_code, 1, 1);

        init_vlc(&inter_intra_vlc, INTER_INTRA_VLC_BITS, 4,

                 &table_inter_intra[0][1], 2, 1,

                 &table_inter_intra[0][0], 2, 1);

    }

    switch(s->msmpeg4_version){

    case 1:

    case 2:

        s->decode_mb= msmpeg4v12_decode_mb;

        break;

    case 3:

    case 4:

        s->decode_mb= msmpeg4v34_decode_mb;

        break;

    case 5:

        s->decode_mb= wmv2_decode_mb;

        break;

    }

    s->slice_height= s->mb_height; //to avoid 1/0 if the first frame isnt a keyframe

    return 0;

}


void block_job_sleep_ns(BlockJob *job, QEMUClockType type, int64_t ns)

{

    assert(job->busy);

    /* Check cancellation *before* setting busy = false, too!  */

    if (block_job_is_cancelled(job)) {

        return;

    }

    job->busy = false;

    if (!block_job_should_pause(job)) {

        co_aio_sleep_ns(blk_get_aio_context(job->blk), type, ns);

    }

    /* The job can be paused while sleeping, so check this again */

    if (block_job_should_pause(job)) {

        qemu_coroutine_yield();

    }

    job->busy = true;

}


static void adb_mouse_reset(DeviceState *dev)

{

    ADBDevice *d = ADB_DEVICE(dev);

    MouseState *s = ADB_MOUSE(dev);

    d->handler = 2;

    d->devaddr = ADB_DEVID_MOUSE;

    s->last_buttons_state = s->buttons_state = 0;

    s->dx = s->dy = s->dz = 0;

}


static void raw_close(BlockDriverState *bs)

{

    BDRVRawState *s = bs->opaque;

    if (s->fd >= 0) {

        close(s->fd);

        s->fd = -1;

        if (s->aligned_buf != NULL)

            qemu_free(s->aligned_buf);

    }

}


static void start_frame_overlay(AVFilterLink *inlink, AVFilterBufferRef *inpicref)

{

    AVFilterContext *ctx = inlink->dst;

    OverlayContext *over = ctx->priv;

    inpicref->pts = av_rescale_q(inpicref->pts, ctx->inputs[OVERLAY]->time_base,

                                 ctx->outputs[0]->time_base);

    if (!over->overpicref) over->overpicref      = inpicref;

    else                   over->overpicref_next = inpicref;

}


START_TEST(simple_dict)

{

    int i;

    struct {

        const char *encoded;

        LiteralQObject decoded;

    } test_cases[] = {

        {

            .encoded = "{\"foo\": 42, \"bar\": \"hello world\"}",

            .decoded = QLIT_QDICT(((LiteralQDictEntry[]){

                        { "foo", QLIT_QINT(42) },

                        { "bar", QLIT_QSTR("hello world") },

                        { }

                    })),

        }, {

            .encoded = "{}",

            .decoded = QLIT_QDICT(((LiteralQDictEntry[]){

                        { }

                    })),

        }, {

            .encoded = "{\"foo\": 43}",

            .decoded = QLIT_QDICT(((LiteralQDictEntry[]){

                        { "foo", QLIT_QINT(43) },

                        { }

                    })),

        },

        { }

    };

    for (i = 0; test_cases[i].encoded; i++) {

        QObject *obj;

        QString *str;

        obj = qobject_from_json(test_cases[i].encoded);

        fail_unless(obj != NULL);

        fail_unless(qobject_type(obj) == QTYPE_QDICT);

        fail_unless(compare_litqobj_to_qobj(&test_cases[i].decoded, obj) == 1);

        str = qobject_to_json(obj);

        qobject_decref(obj);

        obj = qobject_from_json(qstring_get_str(str));

        fail_unless(obj != NULL);

        fail_unless(qobject_type(obj) == QTYPE_QDICT);

        fail_unless(compare_litqobj_to_qobj(&test_cases[i].decoded, obj) == 1);

        qobject_decref(obj);

        QDECREF(str);

    }

}


static void i440fx_pcihost_get_pci_hole64_end(Object *obj, Visitor *v,

                                              const char *name, void *opaque,

                                              Error **errp)

{

    PCIHostState *h = PCI_HOST_BRIDGE(obj);

    Range w64;

    pci_bus_get_w64_range(h->bus, &w64);

    visit_type_uint64(v, name, &w64.end, errp);

}


void ioinst_handle_stsch(S390CPU *cpu, uint64_t reg1, uint32_t ipb)

{

    int cssid, ssid, schid, m;

    SubchDev *sch;

    uint64_t addr;

    int cc;

    SCHIB schib;

    CPUS390XState *env = &cpu->env;

    uint8_t ar;

    addr = decode_basedisp_s(env, ipb, &ar);

    if (addr & 3) {

        program_interrupt(env, PGM_SPECIFICATION, 2);

        return;

    }

    if (ioinst_disassemble_sch_ident(reg1, &m, &cssid, &ssid, &schid)) {

        /*

         * As operand exceptions have a lower priority than access exceptions,

         * we check whether the memory area is writeable (injecting the

         * access execption if it is not) first.

         */

        if (!s390_cpu_virt_mem_check_write(cpu, addr, ar, sizeof(schib))) {

            program_interrupt(env, PGM_OPERAND, 2);

        }

        return;

    }

    trace_ioinst_sch_id("stsch", cssid, ssid, schid);

    sch = css_find_subch(m, cssid, ssid, schid);

    if (sch) {

        if (css_subch_visible(sch)) {

            css_do_stsch(sch, &schib);

            cc = 0;

        } else {

            /* Indicate no more subchannels in this css/ss */

            cc = 3;

        }

    } else {

        if (css_schid_final(m, cssid, ssid, schid)) {

            cc = 3; /* No more subchannels in this css/ss */

        } else {

            /* Store an empty schib. */

            memset(&schib, 0, sizeof(schib));

            cc = 0;

        }

    }

    if (cc != 3) {

        if (s390_cpu_virt_mem_write(cpu, addr, ar, &schib,

                                    sizeof(schib)) != 0) {

            return;

        }

    } else {

        /* Access exceptions have a higher priority than cc3 */

        if (s390_cpu_virt_mem_check_write(cpu, addr, ar, sizeof(schib)) != 0) {

            return;

        }

    }

    setcc(cpu, cc);

}


static void cow_close(BlockDriverState *bs)

{

}


static int cllc_decode_frame(AVCodecContext *avctx, void *data,

                             int *got_picture_ptr, AVPacket *avpkt)

{

    CLLCContext *ctx = avctx->priv_data;

    AVFrame *pic = avctx->coded_frame;

    uint8_t *src = avpkt->data;

    uint8_t *swapped_buf_new;

    uint32_t info_tag, info_offset;

    GetBitContext gb;

    int coding_type, ret;

    if (pic->data[0])

        avctx->release_buffer(avctx, pic);

    pic->reference = 0;

    /* Make sure our bswap16'd buffer is big enough */

    swapped_buf_new = av_fast_realloc(ctx->swapped_buf,

                                      &ctx->swapped_buf_size, avpkt->size);

    if (!swapped_buf_new) {

        av_log(avctx, AV_LOG_ERROR, "Could not realloc swapped buffer.\n");

        return AVERROR(ENOMEM);

    }

    ctx->swapped_buf = swapped_buf_new;

    /* Skip the INFO header if present */

    info_offset = 0;

    info_tag    = AV_RL32(src);

    if (info_tag == MKTAG('I', 'N', 'F', 'O')) {

        info_offset = AV_RL32(src + 4);

        if (info_offset > UINT32_MAX - 8 || info_offset + 8 > avpkt->size) {

            av_log(avctx, AV_LOG_ERROR,

                   "Invalid INFO header offset: 0x%08X is too large.\n",

                   info_offset);

            return AVERROR_INVALIDDATA;

        }

        info_offset += 8;

        src         += info_offset;

        av_log(avctx, AV_LOG_DEBUG, "Skipping INFO chunk.\n");

    }

    /* bswap16 the buffer since CLLC's bitreader works in 16-bit words */

    ctx->dsp.bswap16_buf((uint16_t *) ctx->swapped_buf, (uint16_t *) src,

                         (avpkt->size - info_offset) / 2);

    init_get_bits(&gb, ctx->swapped_buf, (avpkt->size - info_offset) * 8);

    /*

     * Read in coding type. The types are as follows:

     *

     * 0 - YUY2

     * 1 - BGR24 (Triples)

     * 2 - BGR24 (Quads)

     * 3 - BGRA

     */

    coding_type = (AV_RL32(src) >> 8) & 0xFF;

    av_log(avctx, AV_LOG_DEBUG, "Frame coding type: %d\n", coding_type);

    switch (coding_type) {

    case 1:

    case 2:

        avctx->pix_fmt             = PIX_FMT_RGB24;

        avctx->bits_per_raw_sample = 8;

        ret = avctx->get_buffer(avctx, pic);

        if (ret < 0) {

            av_log(avctx, AV_LOG_ERROR, "Could not allocate buffer.\n");

            return ret;

        }

        ret = decode_rgb24_frame(ctx, &gb, pic);

        if (ret < 0)

            return ret;

        break;

    case 3:

        avctx->pix_fmt             = PIX_FMT_ARGB;

        avctx->bits_per_raw_sample = 8;

        ret = avctx->get_buffer(avctx, pic);

        if (ret < 0) {

            av_log(avctx, AV_LOG_ERROR, "Could not allocate buffer.\n");

            return ret;

        }

        ret = decode_argb_frame(ctx, &gb, pic);

        if (ret < 0)

            return ret;

        break;

    default:

        av_log(avctx, AV_LOG_ERROR, "Unknown coding type: %d.\n", coding_type);

        return AVERROR_INVALIDDATA;

    }

    pic->key_frame = 1;

    pic->pict_type = AV_PICTURE_TYPE_I;

    *got_picture_ptr = 1;

    *(AVFrame *)data = *pic;

    return avpkt->size;

}


void mips_malta_init (ram_addr_t ram_size, int vga_ram_size,

                      const char *boot_device,

                      const char *kernel_filename, const char *kernel_cmdline,

                      const char *initrd_filename, const char *cpu_model)

{

    char buf[1024];

    unsigned long bios_offset;

    target_long bios_size;

    int64_t kernel_entry;

    PCIBus *pci_bus;

    CPUState *env;

    RTCState *rtc_state;

    fdctrl_t *floppy_controller;

    MaltaFPGAState *malta_fpga;

    qemu_irq *i8259;

    int piix4_devfn;

    uint8_t *eeprom_buf;

    i2c_bus *smbus;

    int i;

    int index;

    BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];

    BlockDriverState *fd[MAX_FD];

    int fl_idx = 0;

    int fl_sectors = 0;

    /* init CPUs */

    if (cpu_model == NULL) {

#ifdef TARGET_MIPS64

        cpu_model = "20Kc";

#else

        cpu_model = "24Kf";

#endif

    env = cpu_init(cpu_model);

    if (!env) {

        fprintf(stderr, "Unable to find CPU definition\n");

    qemu_register_reset(main_cpu_reset, env);

    /* allocate RAM */

    cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);

    /* Map the bios at two physical locations, as on the real board. */

    bios_offset = ram_size + vga_ram_size;

    cpu_register_physical_memory(0x1e000000LL,

                                 BIOS_SIZE, bios_offset | IO_MEM_ROM);

    cpu_register_physical_memory(0x1fc00000LL,

                                 BIOS_SIZE, bios_offset | IO_MEM_ROM);

    /* FPGA */

    malta_fpga = malta_fpga_init(0x1f000000LL, env->irq[2], serial_hds[2]);

    /* Load firmware in flash / BIOS unless we boot directly into a kernel. */

    if (kernel_filename) {

        /* Write a small bootloader to the flash location. */

        loaderparams.ram_size = ram_size;

        loaderparams.kernel_filename = kernel_filename;

        loaderparams.kernel_cmdline = kernel_cmdline;

        loaderparams.initrd_filename = initrd_filename;

        kernel_entry = load_kernel(env);

        env->CP0_Status &= ~((1 << CP0St_BEV) | (1 << CP0St_ERL));

        write_bootloader(env, bios_offset, kernel_entry);

    } else {

        index = drive_get_index(IF_PFLASH, 0, fl_idx);

        if (index != -1) {

            /* Load firmware from flash. */

            bios_size = 0x400000;

            fl_sectors = bios_size >> 16;

#ifdef DEBUG_BOARD_INIT

            printf("Register parallel flash %d size " TARGET_FMT_lx " at "

                   "offset %08lx addr %08llx '%s' %x\n",

                   fl_idx, bios_size, bios_offset, 0x1e000000LL,

                   bdrv_get_device_name(drives_table[index].bdrv), fl_sectors);

#endif

            pflash_cfi01_register(0x1e000000LL, bios_offset,

                                  drives_table[index].bdrv, 65536, fl_sectors,

                                  4, 0x0000, 0x0000, 0x0000, 0x0000);

            fl_idx++;

        } else {

            /* Load a BIOS image. */

            if (bios_name == NULL)

                bios_name = BIOS_FILENAME;

            snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);

            bios_size = load_image(buf, phys_ram_base + bios_offset);

            if ((bios_size < 0 || bios_size > BIOS_SIZE) && !kernel_filename) {

                        "qemu: Could not load MIPS bios '%s', and no -kernel argument was specified\n",

                        buf);

        /* In little endian mode the 32bit words in the bios are swapped,

           a neat trick which allows bi-endian firmware. */

#ifndef TARGET_WORDS_BIGENDIAN

        {

            uint32_t *addr;

            for (addr = (uint32_t *)(phys_ram_base + bios_offset);

                 addr < (uint32_t *)(phys_ram_base + bios_offset + bios_size);

                 addr++) {

                *addr = bswap32(*addr);

#endif

    /* Board ID = 0x420 (Malta Board with CoreLV)

       XXX: theoretically 0x1e000010 should map to flash and 0x1fc00010 should

       map to the board ID. */

    stl_raw(phys_ram_base + bios_offset + 0x10, 0x00000420);

    /* Init internal devices */

    cpu_mips_irq_init_cpu(env);

    cpu_mips_clock_init(env);

    /* Interrupt controller */

    /* The 8259 is attached to the MIPS CPU INT0 pin, ie interrupt 2 */

    i8259 = i8259_init(env->irq[2]);

    /* Northbridge */

    pci_bus = pci_gt64120_init(i8259);

    /* Southbridge */

    if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {

        fprintf(stderr, "qemu: too many IDE bus\n");

    for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {

        index = drive_get_index(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);

        if (index != -1)

            hd[i] = drives_table[index].bdrv;

        else

            hd[i] = NULL;

    piix4_devfn = piix4_init(pci_bus, 80);

    pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1, i8259);

    usb_uhci_piix4_init(pci_bus, piix4_devfn + 2);

    smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100, i8259[9]);

    eeprom_buf = qemu_mallocz(8 * 256); /* XXX: make this persistent */

    for (i = 0; i < 8; i++) {

        /* TODO: Populate SPD eeprom data.  */

        smbus_eeprom_device_init(smbus, 0x50 + i, eeprom_buf + (i * 256));

    pit = pit_init(0x40, i8259[0]);

    DMA_init(0);

    /* Super I/O */

    i8042_init(i8259[1], i8259[12], 0x60);

    rtc_state = rtc_init(0x70, i8259[8]);

    serial_init(0x3f8, i8259[4], 115200, serial_hds[0]);

    serial_init(0x2f8, i8259[3], 115200, serial_hds[1]);

    if (parallel_hds[0])

        parallel_init(0x378, i8259[7], parallel_hds[0]);

    for(i = 0; i < MAX_FD; i++) {

        index = drive_get_index(IF_FLOPPY, 0, i);

       if (index != -1)

           fd[i] = drives_table[index].bdrv;

       else

           fd[i] = NULL;

    floppy_controller = fdctrl_init(i8259[6], 2, 0, 0x3f0, fd);

    /* Sound card */

#ifdef HAS_AUDIO

    audio_init(pci_bus);

#endif

    /* Network card */

    network_init(pci_bus);

    /* Optional PCI video card */

    pci_cirrus_vga_init(pci_bus, phys_ram_base + ram_size,

                        ram_size, vga_ram_size);


static int ohci_service_td(OHCIState *ohci, struct ohci_ed *ed)

{

    int dir;

    size_t len = 0;

#ifdef DEBUG_PACKET

    const char *str = NULL;

#endif

    int pid;

    int ret;

    int i;

    USBDevice *dev;

    struct ohci_td td;

    uint32_t addr;

    int flag_r;

    int completion;

    addr = ed->head & OHCI_DPTR_MASK;

    /* See if this TD has already been submitted to the device.  */

    completion = (addr == ohci->async_td);

    if (completion && !ohci->async_complete) {

#ifdef DEBUG_PACKET

        DPRINTF("Skipping async TD\n");

#endif

        return 1;

    }

    if (!ohci_read_td(ohci, addr, &td)) {

        fprintf(stderr, "usb-ohci: TD read error at %x\n", addr);

        return 0;

    }

    dir = OHCI_BM(ed->flags, ED_D);

    switch (dir) {

    case OHCI_TD_DIR_OUT:

    case OHCI_TD_DIR_IN:

        /* Same value.  */

        break;

    default:

        dir = OHCI_BM(td.flags, TD_DP);

        break;

    }

    switch (dir) {

    case OHCI_TD_DIR_IN:

#ifdef DEBUG_PACKET

        str = "in";

#endif

        pid = USB_TOKEN_IN;

        break;

    case OHCI_TD_DIR_OUT:

#ifdef DEBUG_PACKET

        str = "out";

#endif

        pid = USB_TOKEN_OUT;

        break;

    case OHCI_TD_DIR_SETUP:

#ifdef DEBUG_PACKET

        str = "setup";

#endif

        pid = USB_TOKEN_SETUP;

        break;

    default:

        fprintf(stderr, "usb-ohci: Bad direction\n");

        return 1;

    }

    if (td.cbp && td.be) {

        if ((td.cbp & 0xfffff000) != (td.be & 0xfffff000)) {

            len = (td.be & 0xfff) + 0x1001 - (td.cbp & 0xfff);

        } else {

            len = (td.be - td.cbp) + 1;

        }

        if (len && dir != OHCI_TD_DIR_IN && !completion) {

            ohci_copy_td(ohci, &td, ohci->usb_buf, len, 0);

        }

    }

    flag_r = (td.flags & OHCI_TD_R) != 0;

#ifdef DEBUG_PACKET

    DPRINTF(" TD @ 0x%.8x %" PRId64 " bytes %s r=%d cbp=0x%.8x be=0x%.8x\n",

            addr, (int64_t)len, str, flag_r, td.cbp, td.be);

    if (len > 0 && dir != OHCI_TD_DIR_IN) {

        DPRINTF("  data:");

        for (i = 0; i < len; i++)

            printf(" %.2x", ohci->usb_buf[i]);

        DPRINTF("\n");

    }

#endif

    if (completion) {

        ret = ohci->usb_packet.len;

        ohci->async_td = 0;

        ohci->async_complete = 0;

    } else {

        ret = USB_RET_NODEV;

        for (i = 0; i < ohci->num_ports; i++) {

            dev = ohci->rhport[i].port.dev;

            if ((ohci->rhport[i].ctrl & OHCI_PORT_PES) == 0)

                continue;

            if (ohci->async_td) {

                /* ??? The hardware should allow one active packet per

                   endpoint.  We only allow one active packet per controller.

                   This should be sufficient as long as devices respond in a

                   timely manner.

                 */

#ifdef DEBUG_PACKET

                DPRINTF("Too many pending packets\n");

#endif

                return 1;

            }

            ohci->usb_packet.pid = pid;

            ohci->usb_packet.devaddr = OHCI_BM(ed->flags, ED_FA);

            ohci->usb_packet.devep = OHCI_BM(ed->flags, ED_EN);

            ohci->usb_packet.data = ohci->usb_buf;

            ohci->usb_packet.len = len;

            ret = usb_handle_packet(dev, &ohci->usb_packet);

            if (ret != USB_RET_NODEV)

                break;

        }

#ifdef DEBUG_PACKET

        DPRINTF("ret=%d\n", ret);

#endif

        if (ret == USB_RET_ASYNC) {

            ohci->async_td = addr;

            return 1;

        }

    }

    if (ret >= 0) {

        if (dir == OHCI_TD_DIR_IN) {

            ohci_copy_td(ohci, &td, ohci->usb_buf, ret, 1);

#ifdef DEBUG_PACKET

            DPRINTF("  data:");

            for (i = 0; i < ret; i++)

                printf(" %.2x", ohci->usb_buf[i]);

            DPRINTF("\n");

#endif

        } else {

            ret = len;

        }

    }

    /* Writeback */

    if (ret == len || (dir == OHCI_TD_DIR_IN && ret >= 0 && flag_r)) {

        /* Transmission succeeded.  */

        if (ret == len) {

            td.cbp = 0;

        } else {

            td.cbp += ret;

            if ((td.cbp & 0xfff) + ret > 0xfff) {

                td.cbp &= 0xfff;

                td.cbp |= td.be & ~0xfff;

            }

        }

        td.flags |= OHCI_TD_T1;

        td.flags ^= OHCI_TD_T0;

        OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_NOERROR);

        OHCI_SET_BM(td.flags, TD_EC, 0);

        ed->head &= ~OHCI_ED_C;

        if (td.flags & OHCI_TD_T0)

            ed->head |= OHCI_ED_C;

    } else {

        if (ret >= 0) {

            DPRINTF("usb-ohci: Underrun\n");

            OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DATAUNDERRUN);

        } else {

            switch (ret) {

            case USB_RET_NODEV:

                OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DEVICENOTRESPONDING);

            case USB_RET_NAK:

                DPRINTF("usb-ohci: got NAK\n");

                return 1;

            case USB_RET_STALL:

                DPRINTF("usb-ohci: got STALL\n");

                OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_STALL);

                break;

            case USB_RET_BABBLE:

                DPRINTF("usb-ohci: got BABBLE\n");

                OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DATAOVERRUN);

                break;

            default:

                fprintf(stderr, "usb-ohci: Bad device response %d\n", ret);

                OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_UNDEXPETEDPID);

                OHCI_SET_BM(td.flags, TD_EC, 3);

                break;

            }

        }

        ed->head |= OHCI_ED_H;

    }

    /* Retire this TD */

    ed->head &= ~OHCI_DPTR_MASK;

    ed->head |= td.next & OHCI_DPTR_MASK;

    td.next = ohci->done;

    ohci->done = addr;

    i = OHCI_BM(td.flags, TD_DI);

    if (i < ohci->done_count)

        ohci->done_count = i;

    ohci_put_td(ohci, addr, &td);

    return OHCI_BM(td.flags, TD_CC) != OHCI_CC_NOERROR;

}


void qdev_prop_set_drive(DeviceState *dev, const char *name,

                         BlockBackend *value, Error **errp)

{

    object_property_set_str(OBJECT(dev), value ? blk_name(value) : "",

                            name, errp);

}


int net_slirp_redir(const char *redir_str)

{

    struct slirp_config_str *config;

    if (QTAILQ_EMPTY(&slirp_stacks)) {

        config = g_malloc(sizeof(*config));

        pstrcpy(config->str, sizeof(config->str), redir_str);

        config->flags = SLIRP_CFG_HOSTFWD | SLIRP_CFG_LEGACY;

        config->next = slirp_configs;

        slirp_configs = config;

        return 0;

    }

    return slirp_hostfwd(QTAILQ_FIRST(&slirp_stacks), redir_str, 1);

}


static int decode_frame(AVCodecContext *avctx, const uint8_t *databuf,

                        float **out_samples)

{

    ATRAC3Context *q = avctx->priv_data;

    int ret, i, ch;

    uint8_t *ptr1;

    if (q->coding_mode == JOINT_STEREO) {

        /* channel coupling mode */

        /* Decode sound unit pairs (channels are expected to be even).

         * Multichannel joint stereo interleaves pairs (6ch: 2ch + 2ch + 2ch) */

        const uint8_t *js_databuf;

        int js_pair, js_block_align;

        js_block_align = (avctx->block_align / avctx->channels) * 2; /* block pair */

        for (ch = 0; ch < avctx->channels; ch = ch + 2) {

            js_pair = ch/2;

            js_databuf = databuf + js_pair * js_block_align; /* align to current pair */

            /* Set the bitstream reader at the start of first channel sound unit. */

            init_get_bits(&q->gb,

                          js_databuf, js_block_align * 8);

            /* decode Sound Unit 1 */

            ret = decode_channel_sound_unit(q, &q->gb, &q->units[ch],

                                            out_samples[ch], ch, JOINT_STEREO);

            if (ret != 0)

                return ret;

            /* Framedata of the su2 in the joint-stereo mode is encoded in

             * reverse byte order so we need to swap it first. */

            if (js_databuf == q->decoded_bytes_buffer) {

                uint8_t *ptr2 = q->decoded_bytes_buffer + js_block_align - 1;

                ptr1          = q->decoded_bytes_buffer;

                for (i = 0; i < js_block_align / 2; i++, ptr1++, ptr2--)

                    FFSWAP(uint8_t, *ptr1, *ptr2);

            } else {

                const uint8_t *ptr2 = js_databuf + js_block_align - 1;

                for (i = 0; i < js_block_align; i++)

                    q->decoded_bytes_buffer[i] = *ptr2--;

            }

            /* Skip the sync codes (0xF8). */

            ptr1 = q->decoded_bytes_buffer;

            for (i = 4; *ptr1 == 0xF8; i++, ptr1++) {

                if (i >= js_block_align)

                    return AVERROR_INVALIDDATA;

            }

            /* set the bitstream reader at the start of the second Sound Unit */

            init_get_bits8(&q->gb,

                           ptr1, q->decoded_bytes_buffer + js_block_align - ptr1);

            /* Fill the Weighting coeffs delay buffer */

            memmove(q->weighting_delay[js_pair], &q->weighting_delay[js_pair][2],

                    4 * sizeof(*q->weighting_delay[js_pair]));

            q->weighting_delay[js_pair][4] = get_bits1(&q->gb);

            q->weighting_delay[js_pair][5] = get_bits(&q->gb, 3);

            for (i = 0; i < 4; i++) {

                q->matrix_coeff_index_prev[js_pair][i] = q->matrix_coeff_index_now[js_pair][i];

                q->matrix_coeff_index_now[js_pair][i]  = q->matrix_coeff_index_next[js_pair][i];

                q->matrix_coeff_index_next[js_pair][i] = get_bits(&q->gb, 2);

            }

            /* Decode Sound Unit 2. */

            ret = decode_channel_sound_unit(q, &q->gb, &q->units[ch+1],

                                            out_samples[ch+1], ch+1, JOINT_STEREO);

            if (ret != 0)

                return ret;

            /* Reconstruct the channel coefficients. */

            reverse_matrixing(out_samples[ch], out_samples[ch+1],

                              q->matrix_coeff_index_prev[js_pair],

                              q->matrix_coeff_index_now[js_pair]);

            channel_weighting(out_samples[ch], out_samples[ch+1], q->weighting_delay[js_pair]);

        }

    } else {

        /* single channels */

        /* Decode the channel sound units. */

        for (i = 0; i < avctx->channels; i++) {

            /* Set the bitstream reader at the start of a channel sound unit. */

            init_get_bits(&q->gb,

                          databuf + i * avctx->block_align / avctx->channels,

                          avctx->block_align * 8 / avctx->channels);

            ret = decode_channel_sound_unit(q, &q->gb, &q->units[i],

                                            out_samples[i], i, q->coding_mode);

            if (ret != 0)

                return ret;

        }

    }

    /* Apply the iQMF synthesis filter. */

    for (i = 0; i < avctx->channels; i++) {

        float *p1 = out_samples[i];

        float *p2 = p1 + 256;

        float *p3 = p2 + 256;

        float *p4 = p3 + 256;

        ff_atrac_iqmf(p1, p2, 256, p1, q->units[i].delay_buf1, q->temp_buf);

        ff_atrac_iqmf(p4, p3, 256, p3, q->units[i].delay_buf2, q->temp_buf);

        ff_atrac_iqmf(p1, p3, 512, p1, q->units[i].delay_buf3, q->temp_buf);

    }

    return 0;

}


static void decode_refpass(Jpeg2000T1Context *t1, int width, int height,

                           int bpno, int vert_causal_ctx_csty_symbol)

{

    int phalf, nhalf;

    int y0, x, y;

    phalf = 1 << (bpno - 1);

    nhalf = -phalf;

    for (y0 = 0; y0 < height; y0 += 4)

        for (x = 0; x < width; x++)

            for (y = y0; y < height && y < y0 + 4; y++)

                if ((t1->flags[y + 1][x + 1] & (JPEG2000_T1_SIG | JPEG2000_T1_VIS)) == JPEG2000_T1_SIG) {

                    int flags_mask = (vert_causal_ctx_csty_symbol && y == y0 + 3) ?

                        ~(JPEG2000_T1_SIG_S | JPEG2000_T1_SIG_SW | JPEG2000_T1_SIG_SE | JPEG2000_T1_SGN_S) : -1;

                    int ctxno = ff_jpeg2000_getrefctxno(t1->flags[y + 1][x + 1] & flags_mask);

                    int r     = ff_mqc_decode(&t1->mqc,

                                              t1->mqc.cx_states + ctxno)

                                ? phalf : nhalf;

                    t1->data[y][x]          += t1->data[y][x] < 0 ? -r : r;

                    t1->flags[y + 1][x + 1] |= JPEG2000_T1_REF;

                }

}


static void kvm_invoke_set_guest_debug(void *data)

{

    struct kvm_set_guest_debug_data *dbg_data = data;

    CPUState *env = dbg_data->env;

    if (env->kvm_vcpu_dirty) {

        kvm_arch_put_registers(env);

        env->kvm_vcpu_dirty = 0;

    }

    dbg_data->err = kvm_vcpu_ioctl(env, KVM_SET_GUEST_DEBUG, &dbg_data->dbg);

}


static uint32_t find_subframe_rice_params(FlacEncodeContext *s,

                                          FlacSubframe *sub, int pred_order)

{

    int pmin = get_max_p_order(s->options.min_partition_order,

                               s->frame.blocksize, pred_order);

    int pmax = get_max_p_order(s->options.max_partition_order,

                               s->frame.blocksize, pred_order);

    uint32_t bits = 8 + pred_order * sub->obits + 2 + 4;

    if (sub->type == FLAC_SUBFRAME_LPC)

        bits += 4 + 5 + pred_order * s->options.lpc_coeff_precision;

    bits += calc_rice_params(&sub->rc, pmin, pmax, sub->residual,

                             s->frame.blocksize, pred_order);

    return bits;

}


static int mmap_start(AVFormatContext *ctx)

{

    struct video_data *s = ctx->priv_data;

    enum v4l2_buf_type type;

    int i, res;

    for (i = 0; i < s->buffers; i++) {

        struct v4l2_buffer buf;

        memset(&buf, 0, sizeof(struct v4l2_buffer));

        buf.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;

        buf.memory = V4L2_MEMORY_MMAP;

        buf.index  = i;

        res = ioctl(s->fd, VIDIOC_QBUF, &buf);

        if (res < 0) {

            av_log(ctx, AV_LOG_ERROR, "ioctl(VIDIOC_QBUF): %s\n",

                   strerror(errno));

            return AVERROR(errno);

        }

    }

    type = V4L2_BUF_TYPE_VIDEO_CAPTURE;

    res = ioctl(s->fd, VIDIOC_STREAMON, &type);

    if (res < 0) {

        av_log(ctx, AV_LOG_ERROR, "ioctl(VIDIOC_STREAMON): %s\n",

               strerror(errno));

        return AVERROR(errno);

    }

    return 0;

}


static void bdrv_rw_em_cb(void *opaque, int ret)

{

    *(int *)opaque = ret;

}


void ppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr, Error **errp)

{

    int ret = 0;

    CPUPPCState *env = &cpu->env;

    PowerPCCPUClass *host_pcc;

    cpu->compat_pvr = compat_pvr;

    switch (compat_pvr) {

    case CPU_POWERPC_LOGICAL_2_05:

        env->spr[SPR_PCR] = PCR_TM_DIS | PCR_VSX_DIS | PCR_COMPAT_2_07 |

                            PCR_COMPAT_2_06 | PCR_COMPAT_2_05;

        break;

    case CPU_POWERPC_LOGICAL_2_06:

    case CPU_POWERPC_LOGICAL_2_06_PLUS:

        env->spr[SPR_PCR] = PCR_TM_DIS | PCR_COMPAT_2_07 | PCR_COMPAT_2_06;

        break;

    case CPU_POWERPC_LOGICAL_2_07:

        env->spr[SPR_PCR] = PCR_COMPAT_2_07;

        break;

    default:

        env->spr[SPR_PCR] = 0;

        break;

    }

    host_pcc = kvm_ppc_get_host_cpu_class();

    if (host_pcc) {

        env->spr[SPR_PCR] &= host_pcc->pcr_mask;

    }

    if (kvm_enabled()) {

        ret = kvmppc_set_compat(cpu, cpu->compat_pvr);

        if (ret < 0) {

            error_setg_errno(errp, -ret,

                             "Unable to set CPU compatibility mode in KVM");

        }

    }

}


static coroutine_fn int sd_co_pdiscard(BlockDriverState *bs, int64_t offset,

                                      int count)

{

    SheepdogAIOCB acb;

    BDRVSheepdogState *s = bs->opaque;

    QEMUIOVector discard_iov;

    struct iovec iov;

    uint32_t zero = 0;

    if (!s->discard_supported) {

        return 0;

    }

    memset(&discard_iov, 0, sizeof(discard_iov));

    memset(&iov, 0, sizeof(iov));

    iov.iov_base = &zero;

    iov.iov_len = sizeof(zero);

    discard_iov.iov = &iov;

    discard_iov.niov = 1;

    if (!QEMU_IS_ALIGNED(offset | count, BDRV_SECTOR_SIZE)) {

        return -ENOTSUP;

    }

    sd_aio_setup(&acb, s, &discard_iov, offset >> BDRV_SECTOR_BITS,

                 count >> BDRV_SECTOR_BITS, AIOCB_DISCARD_OBJ);

retry:

    if (check_overlapping_aiocb(s, &acb)) {

        qemu_co_queue_wait(&s->overlapping_queue);

        goto retry;

    }

    sd_co_rw_vector(&acb);

    QLIST_REMOVE(&acb, aiocb_siblings);

    qemu_co_queue_restart_all(&s->overlapping_queue);

    return acb.ret;

}


static void gdb_vm_stopped(void *opaque, int reason)

{

    GDBState *s = opaque;

    char buf[256];

    const char *type;

    int ret;

    if (s->state == RS_SYSCALL)

        return;

    /* disable single step if it was enable */

    cpu_single_step(s->env, 0);

    if (reason == EXCP_DEBUG) {

        if (s->env->watchpoint_hit) {

            switch (s->env->watchpoint_hit->flags & BP_MEM_ACCESS) {

            case BP_MEM_READ:

                type = "r";

                break;

            case BP_MEM_ACCESS:

                type = "a";

                break;

            default:

                type = "";

                break;

            }

            snprintf(buf, sizeof(buf), "T%02x%swatch:" TARGET_FMT_lx ";",

                     SIGTRAP, type, s->env->watchpoint_hit->vaddr);

            put_packet(s, buf);

            s->env->watchpoint_hit = NULL;

            return;

        }

	tb_flush(s->env);

        ret = SIGTRAP;

    } else if (reason == EXCP_INTERRUPT) {

        ret = SIGINT;

    } else {

        ret = 0;

    }

    snprintf(buf, sizeof(buf), "S%02x", ret);

    put_packet(s, buf);

}


void qemu_peer_set_offload(NetClientState *nc, int csum, int tso4, int tso6,

                          int ecn, int ufo)

{

    if (!nc->peer || !nc->peer->info->set_offload) {

        return;

    }

    nc->peer->info->set_offload(nc->peer, csum, tso4, tso6, ecn, ufo);

}


uint32_t helper_bcdsetsgn(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps)

{

    int i;

    int invalid = 0;

    int sgnb = bcd_get_sgn(b);

    *r = *b;

    bcd_put_digit(r, bcd_preferred_sgn(sgnb, ps), 0);

    for (i = 1; i < 32; i++) {

        bcd_get_digit(b, i, &invalid);

        if (unlikely(invalid)) {

            return CRF_SO;

        }

    }

    return bcd_cmp_zero(r);

}


uint32_t msix_bar_size(PCIDevice *dev)

{

    return (dev->cap_present & QEMU_PCI_CAP_MSIX) ?

        dev->msix_bar_size : 0;

}