{"task_id": "mux2to1v", "task_number": 1, "description": "Create a 2-1 multiplexer. When sel=0, choose a. When sel=1, choose b.", "header": "module top_module (\n\tinput [99:0] a,\n\tinput [99:0] b,\n\tinput sel,\n\toutput [99:0] out\n);\n", "module_code": "module top_module (\n\tinput [99:0] a,\n\tinput [99:0] b,\n\tinput sel,\n\toutput [99:0] out\n);\n\n\tassign out = sel ? b : a;\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [99:0] a,\n\tinput [99:0] b,\n\tinput sel,\n\toutput [99:0] out\n);\n\n\tassign out = sel ? b : a;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic [99:0] a,b,\n\toutput logic sel,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\tinitial begin\n\t\ta <= 'hdeadbeef;\n\t\tb <= 'h5eaf00d;\n\t\tsel <= 0;\n\t\t@(negedge clk);\n\t\twavedrom_start(\"Beef or seafood?\");\n\t\t\trepeat(6) @(posedge clk) sel <= ~sel;\n\t\t@(negedge clk);\n\t\twavedrom_stop();\n\t\trepeat(100) @(posedge clk, negedge clk)\n\t\t\t{a,b,sel} <= {$random, $random, $random, $random, $random, $random, $random};\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [99:0] a;\n\tlogic [99:0] b;\n\tlogic sel;\n\tlogic [99:0] out_ref;\n\tlogic [99:0] out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,a,b,sel,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.a,\n\t\t.b,\n\t\t.sel );\n\treference_module good1 (\n\t\t.a,\n\t\t.b,\n\t\t.sel,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.a,\n\t\t.b,\n\t\t.sel,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "m2014_q6b", "task_number": 2, "description": "Consider the state machine shown below:\n\n// A (0) --0--> B\n// A (0) --1--> A\n// B (0) --0--> C\n// B (0) --1--> D\n// C (0) --0--> E\n// C (0) --1--> D\n// D (0) --0--> F\n// D (0) --1--> A\n// E (1) --0--> E\n// E (1) --1--> D\n// F (1) --0--> C\n// F (1) --1--> D\n\n// Assume that you want to Implement the FSM using three flip-flops and state codes y[3:1] = 000, 001, ..., 101 for states A, B, ..., F, respectively. Implement just the next-state logic for y[2] in Verilog. The output Y2 is y[2].", "header": "module top_module(\n\tinput [3:1] y,\n\tinput w,\n\toutput reg Y2);\n", "module_code": "module top_module(\n\tinput [3:1] y,\n\tinput w,\n\toutput reg Y2);\n\t\n\talways_comb begin\n\t\tcase ({y, w})\n\t\t\t4'h0: Y2 = 1'b0;\n\t\t\t4'h1: Y2 = 1'b0;\n\t\t\t4'h2: Y2 = 1'b1;\n\t\t\t4'h3: Y2 = 1'b1;\n\t\t\t4'h4: Y2 = 1'b0;\n\t\t\t4'h5: Y2 = 1'b1;\n\t\t\t4'h6: Y2 = 1'b0;\n\t\t\t4'h7: Y2 = 1'b0;\n\t\t\t4'h8: Y2 = 1'b0;\n\t\t\t4'h9: Y2 = 1'b1;\n\t\t\t4'ha: Y2 = 1'b1;\n\t\t\t4'hb: Y2 = 1'b1;\n\t\t\tdefault: Y2 = 1'bx;\n\t\tendcase\n\tend\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput [3:1] y,\n\tinput w,\n\toutput reg Y2);\n\t\n\talways_comb begin\n\t\tcase ({y, w})\n\t\t\t4'h0: Y2 = 1'b0;\n\t\t\t4'h1: Y2 = 1'b0;\n\t\t\t4'h2: Y2 = 1'b1;\n\t\t\t4'h3: Y2 = 1'b1;\n\t\t\t4'h4: Y2 = 1'b0;\n\t\t\t4'h5: Y2 = 1'b1;\n\t\t\t4'h6: Y2 = 1'b0;\n\t\t\t4'h7: Y2 = 1'b0;\n\t\t\t4'h8: Y2 = 1'b0;\n\t\t\t4'h9: Y2 = 1'b1;\n\t\t\t4'ha: Y2 = 1'b1;\n\t\t\t4'hb: Y2 = 1'b1;\n\t\t\tdefault: Y2 = 1'bx;\n\t\tendcase\n\tend\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg [3:1] y,\n\toutput reg w\n);\n\n\tinitial begin\n\t\trepeat(100) @(posedge clk, negedge clk) begin\n\t\t\t{y,w} <= $random;\n\t\tend\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_Y2;\n\t\tint errortime_Y2;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [3:1] y;\n\tlogic w;\n\tlogic Y2_ref;\n\tlogic Y2_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,y,w,Y2_ref,Y2_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.y,\n\t\t.w );\n\treference_module good1 (\n\t\t.y,\n\t\t.w,\n\t\t.Y2(Y2_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.y,\n\t\t.w,\n\t\t.Y2(Y2_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_Y2) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"Y2\", stats1.errors_Y2, stats1.errortime_Y2);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"Y2\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { Y2_ref } === ( { Y2_ref } ^ { Y2_dut } ^ { Y2_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (Y2_ref !== ( Y2_ref ^ Y2_dut ^ Y2_ref ))\n\t\tbegin if (stats1.errors_Y2 == 0) stats1.errortime_Y2 = $time;\n\t\t\tstats1.errors_Y2 = stats1.errors_Y2+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "ringer", "task_number": 3, "description": "Suppose you are designing a circuit to control a cellphone's ringer and vibration motor. Whenever the phone needs to ring from an incoming call (input ring), your circuit must either turn on the ringer (output ringer = 1) or the motor (output motor = 1), but not both. If the phone is in vibrate mode (input vibrate_mode = 1), turn on the motor. Otherwise, turn on the ringer.", "header": "module top_module(\n\tinput ring, \n\tinput vibrate_mode,\n\toutput ringer,\n\toutput motor\n);\n", "module_code": "module top_module(\n\tinput ring, \n\tinput vibrate_mode,\n\toutput ringer,\n\toutput motor\n);\n\t\n\tassign ringer = ring & ~vibrate_mode;\n\tassign motor = ring & vibrate_mode;\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput ring, \n\tinput vibrate_mode,\n\toutput ringer,\n\toutput motor\n);\n\t\n\tassign ringer = ring & ~vibrate_mode;\n\tassign motor = ring & vibrate_mode;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg ring, vibrate_mode,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\tint count; count = 0;\n\t\t{vibrate_mode,ring} <= 1'b0;\n\t\twavedrom_start();\n\t\trepeat(10) @(posedge clk)\n\t\t\t{vibrate_mode,ring} <= count++;\t\t\n\t\twavedrom_stop();\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_ringer;\n\t\tint errortime_ringer;\n\t\tint errors_motor;\n\t\tint errortime_motor;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic ring;\n\tlogic vibrate_mode;\n\tlogic ringer_ref;\n\tlogic ringer_dut;\n\tlogic motor_ref;\n\tlogic motor_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,ring,vibrate_mode,ringer_ref,ringer_dut,motor_ref,motor_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.ring,\n\t\t.vibrate_mode );\n\treference_module good1 (\n\t\t.ring,\n\t\t.vibrate_mode,\n\t\t.ringer(ringer_ref),\n\t\t.motor(motor_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.ring,\n\t\t.vibrate_mode,\n\t\t.ringer(ringer_dut),\n\t\t.motor(motor_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_ringer) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"ringer\", stats1.errors_ringer, stats1.errortime_ringer);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"ringer\");\n\t\tif (stats1.errors_motor) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"motor\", stats1.errors_motor, stats1.errortime_motor);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"motor\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { ringer_ref, motor_ref } === ( { ringer_ref, motor_ref } ^ { ringer_dut, motor_dut } ^ { ringer_ref, motor_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (ringer_ref !== ( ringer_ref ^ ringer_dut ^ ringer_ref ))\n\t\tbegin if (stats1.errors_ringer == 0) stats1.errortime_ringer = $time;\n\t\t\tstats1.errors_ringer = stats1.errors_ringer+1'b1; end\n\t\tif (motor_ref !== ( motor_ref ^ motor_dut ^ motor_ref ))\n\t\tbegin if (stats1.errors_motor == 0) stats1.errortime_motor = $time;\n\t\t\tstats1.errors_motor = stats1.errors_motor+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "alwaysblock1", "task_number": 4, "description": "Build an AND gate using both an assign statement and a combinational always block. ", "header": "module top_module(\n\tinput a, \n\tinput b,\n\toutput out_assign,\n\toutput reg out_alwaysblock\n);\n", "module_code": "module top_module(\n\tinput a, \n\tinput b,\n\toutput out_assign,\n\toutput reg out_alwaysblock\n);\n\t\n\tassign out_assign = a & b;\n\talways @(*) out_alwaysblock = a & b;\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput a, \n\tinput b,\n\toutput out_assign,\n\toutput reg out_alwaysblock\n);\n\t\n\tassign out_assign = a & b;\n\talways @(*) out_alwaysblock = a & b;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg a, b,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\tint count; count = 0;\n\t\t{a,b} <= 1'b0;\n\t\twavedrom_start(\"AND gate\");\n\t\trepeat(10) @(posedge clk)\n\t\t\t{a,b} <= count++;\t\t\n\t\twavedrom_stop();\n\t\t\n\t\trepeat(200) @(posedge clk, negedge clk)\n\t\t\t{b,a} <= $random;\n\t\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out_assign;\n\t\tint errortime_out_assign;\n\t\tint errors_out_alwaysblock;\n\t\tint errortime_out_alwaysblock;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic a;\n\tlogic b;\n\tlogic out_assign_ref;\n\tlogic out_assign_dut;\n\tlogic out_alwaysblock_ref;\n\tlogic out_alwaysblock_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,a,b,out_assign_ref,out_assign_dut,out_alwaysblock_ref,out_alwaysblock_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.a,\n\t\t.b );\n\treference_module good1 (\n\t\t.a,\n\t\t.b,\n\t\t.out_assign(out_assign_ref),\n\t\t.out_alwaysblock(out_alwaysblock_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.a,\n\t\t.b,\n\t\t.out_assign(out_assign_dut),\n\t\t.out_alwaysblock(out_alwaysblock_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out_assign) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_assign\", stats1.errors_out_assign, stats1.errortime_out_assign);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_assign\");\n\t\tif (stats1.errors_out_alwaysblock) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_alwaysblock\", stats1.errors_out_alwaysblock, stats1.errortime_out_alwaysblock);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_alwaysblock\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_assign_ref, out_alwaysblock_ref } === ( { out_assign_ref, out_alwaysblock_ref } ^ { out_assign_dut, out_alwaysblock_dut } ^ { out_assign_ref, out_alwaysblock_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_assign_ref !== ( out_assign_ref ^ out_assign_dut ^ out_assign_ref ))\n\t\tbegin if (stats1.errors_out_assign == 0) stats1.errortime_out_assign = $time;\n\t\t\tstats1.errors_out_assign = stats1.errors_out_assign+1'b1; end\n\t\tif (out_alwaysblock_ref !== ( out_alwaysblock_ref ^ out_alwaysblock_dut ^ out_alwaysblock_ref ))\n\t\tbegin if (stats1.errors_out_alwaysblock == 0) stats1.errortime_out_alwaysblock = $time;\n\t\t\tstats1.errors_out_alwaysblock = stats1.errors_out_alwaysblock+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "zero", "task_number": 5, "description": "Build a circuit that always outputs a LOW.", "header": "module top_module(\n\toutput zero);\n", "module_code": "module top_module(\n\toutput zero);\n\t\n\tassign zero = 1'b0;\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\toutput zero);\n\t\n\tassign zero = 1'b0;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\twavedrom_start(\"Output should 0\");\n\t\trepeat(20) @(posedge clk, negedge clk);\n\t\twavedrom_stop();\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_zero;\n\t\tint errortime_zero;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic zero_ref;\n\tlogic zero_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,zero_ref,zero_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.*  );\n\treference_module good1 (\n\t\t.zero(zero_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.zero(zero_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_zero) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"zero\", stats1.errors_zero, stats1.errortime_zero);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"zero\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { zero_ref } === ( { zero_ref } ^ { zero_dut } ^ { zero_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (zero_ref !== ( zero_ref ^ zero_dut ^ zero_ref ))\n\t\tbegin if (stats1.errors_zero == 0) stats1.errortime_zero = $time;\n\t\t\tstats1.errors_zero = stats1.errors_zero+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "circuit7", "task_number": 6, "description": "This is a sequential circuit. Read the simulation waveforms to determine what the circuit does, then implement it.\n\n// time            clk             a               q               \n// 0ns             0               x               x               \n// 5ns             1               0               x               \n// 10ns            0               0               x               \n// 15ns            1               0               1               \n// 20ns            0               0               1               \n// 25ns            1               0               1               \n// 30ns            0               0               1               \n// 35ns            1               1               1               \n// 40ns            0               1               1               \n// 45ns            1               1               0               \n// 50ns            0               1               0               \n// 55ns            1               1               0               \n// 60ns            0               1               0               \n// 65ns            1               1               0               \n// 70ns            0               1               0               \n// 75ns            1               1               0               \n// 80ns            0               1               0               \n// 85ns            1               1               0               \n// 90ns            0               1               0         ", "header": "module top_module (\n\tinput clk,\n\tinput a, \n\toutput reg q\n);\n", "module_code": "module top_module (\n\tinput clk,\n\tinput a, \n\toutput reg q\n);\n\n\talways @(posedge clk)\n\t\tq <= ~a;\n\t\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput a, \n\toutput reg q\n);\n\n\talways @(posedge clk)\n\t\tq <= ~a;\n\t\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic a,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\t@(posedge clk) {a} <= 0;\n\t\t@(negedge clk) wavedrom_start(\"Unknown circuit\");\n\t\t\t@(posedge clk) {a} <= 0;\n\t\t\trepeat(10) @(posedge clk) a <= $urandom;\n\t\twavedrom_stop();\n\n\t\trepeat(100) @(posedge clk, negedge clk)\n\t\t\ta <= $urandom;\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_q;\n\t\tint errortime_q;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic a;\n\tlogic q_ref;\n\tlogic q_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,a,q_ref,q_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.a );\n\treference_module good1 (\n\t\t.clk,\n\t\t.a,\n\t\t.q(q_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.a,\n\t\t.q(q_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"q\", stats1.errors_q, stats1.errortime_q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"q\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (q_ref !== ( q_ref ^ q_dut ^ q_ref ))\n\t\tbegin if (stats1.errors_q == 0) stats1.errortime_q = $time;\n\t\t\tstats1.errors_q = stats1.errors_q+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "ece241_2014_q5a", "task_number": 7, "description": "You are to design a one-input one-output serial 2's complementer Moore state machine. The input (x) is a series of bits (one per clock cycle) beginning with the least-significant bit of the number, and the output (Z) is the 2's complement of the input. The machine will accept input numbers of arbitrary length. The circuit requires a positive edge triggered asynchronous reset. The conversion begins when Reset is released and stops when Reset is asserted.", "header": "module top_module (\n\tinput clk,\n\tinput areset,\n\tinput x,\n\toutput z\n);\n", "module_code": "module top_module (\n\tinput clk,\n\tinput areset,\n\tinput x,\n\toutput z\n);\n\n\tparameter A=0,B=1,C=2;\n\treg [1:0] state;\n\talways @(posedge clk, posedge areset) begin\n\t\tif (areset)\n\t\t\tstate <= A;\n\t\telse begin\n\t\t\tcase (state)\n\t\t\t\tA: state <= x ? C : A;\n\t\t\t\tB: state <= x ? B : C;\n\t\t\t\tC: state <= x ? B : C;\n\t\t\tendcase\n\t\tend\n\tend\n\t\n\tassign z = (state == C);\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput areset,\n\tinput x,\n\toutput z\n);\n\n\tparameter A=0,B=1,C=2;\n\treg [1:0] state;\n\talways @(posedge clk, posedge areset) begin\n\t\tif (areset)\n\t\t\tstate <= A;\n\t\telse begin\n\t\t\tcase (state)\n\t\t\t\tA: state <= x ? C : A;\n\t\t\t\tB: state <= x ? B : C;\n\t\t\t\tC: state <= x ? B : C;\n\t\t\tendcase\n\t\tend\n\tend\n\t\n\tassign z = (state == C);\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic x,\n\toutput logic areset,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\tinput tb_match\n);\n\treg reset;\n\tassign areset = reset;\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\n\tinitial begin\n\t\tx <= 0;\n\t\treset <= 1;\n\t\t@(posedge clk) reset <= 0; x <= 1;\n\t\t@(posedge clk) x <= 0;\n\t\treset_test(1);\n\t\t\n\t\t@(negedge clk) wavedrom_start();\n\t\t\t@(posedge clk) {reset,x} <= 2'h2;\n\t\t\t@(posedge clk) {reset,x} <= 2'h0;\n\t\t\t@(posedge clk) {reset,x} <= 2'h0;\n\t\t\t@(posedge clk) {reset,x} <= 2'h1;\n\t\t\t@(posedge clk) {reset,x} <= 2'h0;\n\t\t\t@(posedge clk) {reset,x} <= 2'h1;\n\t\t\t@(posedge clk) {reset,x} <= 2'h1;\n\t\t\t@(posedge clk) {reset,x} <= 2'h0;\n\t\t\t@(posedge clk) {reset,x} <= 2'h0;\n\t\t@(negedge clk) wavedrom_stop();\n\t\trepeat(400) @(posedge clk, negedge clk)\n\t\t\t{reset,x} <= {($random&31) == 0, ($random&1)==0 };\n\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_z;\n\t\tint errortime_z;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic areset;\n\tlogic x;\n\tlogic z_ref;\n\tlogic z_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,areset,x,z_ref,z_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.areset,\n\t\t.x );\n\treference_module good1 (\n\t\t.clk,\n\t\t.areset,\n\t\t.x,\n\t\t.z(z_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.areset,\n\t\t.x,\n\t\t.z(z_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_z) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"z\", stats1.errors_z, stats1.errortime_z);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"z\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { z_ref } === ( { z_ref } ^ { z_dut } ^ { z_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (z_ref !== ( z_ref ^ z_dut ^ z_ref ))\n\t\tbegin if (stats1.errors_z == 0) stats1.errortime_z = $time;\n\t\t\tstats1.errors_z = stats1.errors_z+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "fsm3", "task_number": 8, "description": "The following is the state transition table for a Moore state machine with one input, one output, and four states. Implement this state machine. Include a positive edge triggered asynchronous reset that resets the FSM to state A.\n \n// state | next state in=0, next state in=1 | output\n// A | A, B | 0\n// B | C, B | 0\n// C | A, D | 0\n// D | C, B | 1", "header": "module top_module (\n\tinput clk,\n\tinput in,\n\tinput areset,\n\toutput out\n);\n", "module_code": "module top_module (\n\tinput clk,\n\tinput in,\n\tinput areset,\n\toutput out\n);\n\tparameter A=0, B=1, C=2, D=3;\n\treg [1:0] state;\n\treg [1:0] next;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tA: next = in ? B : A;\n\t\t\tB: next = in ? B : C;\n\t\t\tC: next = in ? D : A;\n\t\t\tD: next = in ? B : C;\n\t\tendcase\n    end\n    \n    always @(posedge clk, posedge areset) begin\n\t\tif (areset) state <= A;\n        else state <= next;\n\tend\n\t\t\n\tassign out = (state==D);\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput in,\n\tinput areset,\n\toutput out\n);\n\tparameter A=0, B=1, C=2, D=3;\n\treg [1:0] state;\n\treg [1:0] next;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tA: next = in ? B : A;\n\t\t\tB: next = in ? B : C;\n\t\t\tC: next = in ? D : A;\n\t\t\tD: next = in ? B : C;\n\t\tendcase\n    end\n    \n    always @(posedge clk, posedge areset) begin\n\t\tif (areset) state <= A;\n        else state <= next;\n\tend\n\t\t\n\tassign out = (state==D);\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic in,\n\toutput logic areset,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\tinput tb_match\n);\n\treg reset;\n\tassign areset = reset;\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\tinitial begin\n\t\treset <= 1;\n\t\tin <= 0;\n\t\t@(posedge clk) reset <= 0; in <= 1;\n\t\t@(posedge clk) in <= 0;\n\t\t@(posedge clk) in <= 1;\n\t\twavedrom_start();\n\t\t\t@(posedge clk) in <= 0;\n\t\t\t@(posedge clk) in <= 1;\n\t\t\t@(posedge clk);\n\t\t\t@(negedge clk) reset <= 1;\n\t\t\t@(posedge clk) reset <= 0;\n\t\t\t@(posedge clk) in <= 1;\n\t\t\t@(posedge clk) in <= 1;\n\t\t\t@(posedge clk) in <= 0;\n\t\t\t@(posedge clk) in <= 1;\n\t\t\t@(posedge clk) in <= 0;\n\t\t\t@(posedge clk) in <= 1;\n\t\t\t@(posedge clk) in <= 1;\n\t\t\t@(posedge clk) in <= 1;\n\t\t@(negedge clk);\n\t\twavedrom_stop();\n\t\trepeat(200) @(posedge clk, negedge clk) begin\n\t\t\tin <= $random;\n\t\t\treset <= !($random & 31);\n\t\tend\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic in;\n\tlogic areset;\n\tlogic out_ref;\n\tlogic out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,in,areset,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in,\n\t\t.areset );\n\treference_module good1 (\n\t\t.clk,\n\t\t.in,\n\t\t.areset,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.in,\n\t\t.areset,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "vector2", "task_number": 9, "description": "Build a circuit that reverses the byte order of a 32-bit vector.", "header": "module top_module (\n\tinput [31:0] in,\n\toutput [31:0] out\n);\n", "module_code": "module top_module (\n\tinput [31:0] in,\n\toutput [31:0] out\n);\n\n\tassign out = {in[7:0], in[15:8], in[23:16], in[31:24]};\t\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [31:0] in,\n\toutput [31:0] out\n);\n\n\tassign out = {in[7:0], in[15:8], in[23:16], in[31:24]};\t\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic [31:0] in,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\twavedrom_start(\"Random inputs\");\n\t\trepeat(10) @(posedge clk, negedge clk) \n\t\t\tin <= $random;\n\t\twavedrom_stop();\n\t\trepeat(100) @(posedge clk, negedge clk)\n\t\t\tin <= $random;\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [31:0] in;\n\tlogic [31:0] out_ref;\n\tlogic [31:0] out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,in,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in );\n\treference_module good1 (\n\t\t.in,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.in,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "m2014_q4c", "task_number": 10, "description": "Implement a simple D flip flop with active high synchronous reset (reset output to 0).", "header": "module top_module (\n\tinput clk,\n\tinput d,\n\tinput r,\n\toutput logic q\n);\n", "module_code": "module top_module (\n\tinput clk,\n\tinput d,\n\tinput r,\n\toutput logic q\n);\n\n\talways@(posedge clk) begin\n\t\tif (r)\n\t\t\tq <= 0;\n\t\telse\n\t\t\tq <= d;\n\tend\n\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput d,\n\tinput r,\n\toutput logic q\n);\n\n\talways@(posedge clk) begin\n\t\tif (r)\n\t\t\tq <= 0;\n\t\telse\n\t\t\tq <= d;\n\tend\n\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic d, r\n);\n\n\tinitial begin\n\t\trepeat(100) @(posedge clk, negedge clk) begin\n\t\t\t{d,r} <= $random;\n\t\tend\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_q;\n\t\tint errortime_q;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic d;\n\tlogic r;\n\tlogic q_ref;\n\tlogic q_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,d,r,q_ref,q_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.d,\n\t\t.r );\n\treference_module good1 (\n\t\t.clk,\n\t\t.d,\n\t\t.r,\n\t\t.q(q_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.d,\n\t\t.r,\n\t\t.q(q_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"q\", stats1.errors_q, stats1.errortime_q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"q\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (q_ref !== ( q_ref ^ q_dut ^ q_ref ))\n\t\tbegin if (stats1.errors_q == 0) stats1.errortime_q = $time;\n\t\t\tstats1.errors_q = stats1.errors_q+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "mt2015_q4a", "task_number": 11, "description": "Implement the boolean function z = (x^y) & x.", "header": "module top_module(\n\tinput x,\n\tinput y,\n\toutput z);\n", "module_code": "module top_module(\n\tinput x,\n\tinput y,\n\toutput z);\n\n\tassign z = (x^y) & x;\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput x,\n\tinput y,\n\toutput z);\n\n\tassign z = (x^y) & x;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic x,\n\toutput logic y\n);\n\n\talways @(posedge clk, negedge clk)\n\t\t{x, y} <= $random % 4;\n\t\n\tinitial begin\n\t\trepeat(101) @(negedge clk);\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_z;\n\t\tint errortime_z;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic x;\n\tlogic y;\n\tlogic z_ref;\n\tlogic z_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,x,y,z_ref,z_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.x,\n\t\t.y );\n\treference_module good1 (\n\t\t.x,\n\t\t.y,\n\t\t.z(z_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.x,\n\t\t.y,\n\t\t.z(z_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_z) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"z\", stats1.errors_z, stats1.errortime_z);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"z\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { z_ref } === ( { z_ref } ^ { z_dut } ^ { z_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (z_ref !== ( z_ref ^ z_dut ^ z_ref ))\n\t\tbegin if (stats1.errors_z == 0) stats1.errortime_z = $time;\n\t\t\tstats1.errors_z = stats1.errors_z+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "shift18", "task_number": 12, "description": "Build a 64-bit arithmetic shift register, with synchronous load. The shifter can shift both left and right, and by 1 or 8 bit positions, selected by \"amount.\" Assume the right shit is an arithmetic right shift. \n\n// Signals are defined as below:\n// (1) load: Loads shift register with data[63:0] instead of shifting. Active high.\n// (2) ena: Chooses whether to shift. Active high. \n// (3) amount: Chooses which direction and how much to shift. \n//     (a) 2'b00: shift left by 1 bit. \n//     (b) 2'b01: shift left by 8 bits. \n//     (c) 2'b10: shift right by 1 bit. \n//     (d) 2'b11: shift right by 8 bits. \n// (4) q: The contents of the shifter.", "header": "module top_module(\n\tinput clk,\n\tinput load,\n\tinput ena,\n\tinput [1:0] amount,\n\tinput [63:0] data,\n\toutput reg [63:0] q);\n", "module_code": "module top_module(\n\tinput clk,\n\tinput load,\n\tinput ena,\n\tinput [1:0] amount,\n\tinput [63:0] data,\n\toutput reg [63:0] q);\n\t\n\t\n\talways @(posedge clk) begin\n\t\tif (load)\n\t\t\tq <= data;\n\t\telse if (ena) case (amount)\n\t\t\t2'b00: q <= {q[62:0], 1'b0};\n\t\t\t2'b01: q <= {q[55:0], 8'b0};\n\t\t\t2'b10: q <= {q[63], q[63:1]};\n\t\t\t2'b11: q <= {{8{q[63]}}, q[63:8]};\n\t\t\tdefault: q <= 64'hx;\n\t\tendcase\n\tend\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput clk,\n\tinput load,\n\tinput ena,\n\tinput [1:0] amount,\n\tinput [63:0] data,\n\toutput reg [63:0] q);\n\t\n\t\n\talways @(posedge clk) begin\n\t\tif (load)\n\t\t\tq <= data;\n\t\telse if (ena) case (amount)\n\t\t\t2'b00: q <= {q[62:0], 1'b0};\n\t\t\t2'b01: q <= {q[55:0], 8'b0};\n\t\t\t2'b10: q <= {q[63], q[63:1]};\n\t\t\t2'b11: q <= {{8{q[63]}}, q[63:8]};\n\t\t\tdefault: q <= 64'hx;\n\t\tendcase\n\tend\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg load,\n\toutput reg ena,\n\toutput reg[1:0] amount,\n\toutput reg[63:0] data,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\tload <= 1;\n\t\tena <= 0;\n\t\tdata <= 'x;\n\t\tamount <= 0;\n\t\t@(posedge clk) data <= 64'h000100;\n\t\twavedrom_start(\"Shifting\");\n\t\t\t@(posedge clk) load <= 0; ena <= 1;\n\t\t\t\t\t\t\tamount <= 2;\n\t\t\t@(posedge clk) amount <= 2;\n\t\t\t@(posedge clk) amount <= 2;\n\t\t\t@(posedge clk) amount <= 1;\n\t\t\t@(posedge clk) amount <= 1;\n\t\t\t@(posedge clk) amount <= 0;\n\t\t\t@(posedge clk) amount <= 0;\n\t\t\t@(posedge clk) amount <= 3;\n\t\t\t@(posedge clk) amount <= 3;\n\t\t\t@(posedge clk) amount <= 2;\n\t\t\t@(posedge clk) amount <= 2;\n\t\t\t@(negedge clk);\n\t\twavedrom_stop();\n\t\t\n\t\t@(posedge clk); load <= 1; data <= 64'hx;\n\t\t@(posedge clk); load <= 1; data <= 64'h80000000_00000000;\n\t\twavedrom_start(\"Arithmetic right shift\");\n\t\t\t@(posedge clk) load <= 0; ena <= 1;\n\t\t\t\t\t\t\tamount <= 2;\n\t\t\t@(posedge clk) amount <= 2;\n\t\t\t@(posedge clk) amount <= 2;\n\t\t\t@(posedge clk) amount <= 2;\n\t\t\t@(posedge clk) amount <= 2;\n\t\t\t@(negedge clk);\n\t\twavedrom_stop();\n\n\t\t@(posedge clk);\n\t\t@(posedge clk);\n\t\t\n\t\t\n\t\t\n\t\trepeat(4000) @(posedge clk, negedge clk) begin\n\t\t\tload <= !($random & 31);\n\t\t\tena <= |($random & 15);\n\t\t\tamount <= $random;\n\t\t\tdata <= {$random,$random};\n\t\tend\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_q;\n\t\tint errortime_q;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic load;\n\tlogic ena;\n\tlogic [1:0] amount;\n\tlogic [63:0] data;\n\tlogic [63:0] q_ref;\n\tlogic [63:0] q_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,load,ena,amount,data,q_ref,q_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.load,\n\t\t.ena,\n\t\t.amount,\n\t\t.data );\n\treference_module good1 (\n\t\t.clk,\n\t\t.load,\n\t\t.ena,\n\t\t.amount,\n\t\t.data,\n\t\t.q(q_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.load,\n\t\t.ena,\n\t\t.amount,\n\t\t.data,\n\t\t.q(q_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"q\", stats1.errors_q, stats1.errortime_q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"q\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (q_ref !== ( q_ref ^ q_dut ^ q_ref ))\n\t\tbegin if (stats1.errors_q == 0) stats1.errortime_q = $time;\n\t\t\tstats1.errors_q = stats1.errors_q+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "ece241_2013_q8", "task_number": 13, "description": "Implement a Mealy-type finite state machine that recognizes the sequence \"101\" on an input signal named x. Your FSM should have an output signal, z, that is asserted to logic-1 when the \"101\" sequence is detected. Your FSM should also have a negative edge triggered asynchronous reset. You may only have 3 states in your state machine. Your FSM should recognize overlapping sequences.", "header": "module top_module (\n\tinput clk,\n\tinput aresetn,\n\tinput x,\n\toutput reg z\n);\n", "module_code": "module top_module (\n\tinput clk,\n\tinput aresetn,\n\tinput x,\n\toutput reg z\n);\n\tparameter S=0, S1=1, S10=2;\n\treg[1:0] state, next;\n\t\n\talways@(posedge clk, negedge aresetn)\n\t\tif (!aresetn)\n\t\t\tstate <= S;\n\t\telse\n\t\t\tstate <= next;\n\t\t\t\n\talways_comb begin\n\t\tcase (state)\n\t\t\tS: next = x ? S1 : S;\n\t\t\tS1: next = x ? S1 : S10;\n\t\t\tS10: next = x ? S1 : S;\n\t\t\tdefault: next = 'x;\n\t\tendcase\n\tend\n\t\n\talways_comb begin\n\t\tcase (state)\n\t\t\tS: z = 0;\n\t\t\tS1: z = 0;\n\t\t\tS10: z = x;\n\t\t\tdefault: z = 'x;\n\t\tendcase\n\tend\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput aresetn,\n\tinput x,\n\toutput reg z\n);\n\tparameter S=0, S1=1, S10=2;\n\treg[1:0] state, next;\n\t\n\talways@(posedge clk, negedge aresetn)\n\t\tif (!aresetn)\n\t\t\tstate <= S;\n\t\telse\n\t\t\tstate <= next;\n\t\t\t\n\talways_comb begin\n\t\tcase (state)\n\t\t\tS: next = x ? S1 : S;\n\t\t\tS1: next = x ? S1 : S10;\n\t\t\tS10: next = x ? S1 : S;\n\t\t\tdefault: next = 'x;\n\t\tendcase\n\tend\n\t\n\talways_comb begin\n\t\tcase (state)\n\t\t\tS: z = 0;\n\t\t\tS1: z = 0;\n\t\t\tS10: z = x;\n\t\t\tdefault: z = 'x;\n\t\tendcase\n\tend\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic aresetn,\n\toutput logic x,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\tinput tb_match\n);\n\treg reset;\n\tassign aresetn = ~reset;\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\n\tinitial begin\n\t\tx <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\t@(posedge clk) x <= 1;\n\t\t@(posedge clk) x <= 0;\n\t\t@(posedge clk) x <= 1;\n\tend\n\t\n\tinitial begin\n\t\treset <= 1;\n\t\t@(posedge clk) reset <= 0;\n\t\treset_test(1);\n\t\t\n\t\t@(negedge clk) wavedrom_start();\n\t\t\t@(posedge clk) x <= 0;\n\t\t\t@(posedge clk) x <= 0;\n\t\t\t@(posedge clk) x <= 0;\n\t\t\t@(posedge clk) x <= 1;\n\t\t\t@(posedge clk) x <= 0;\n\t\t\t@(posedge clk) x <= 1;\n\t\t\t@(posedge clk) x <= 0;\n\t\t\t@(posedge clk) x <= 1;\n\t\t\t@(posedge clk) x <= 1;\n\t\t\t@(posedge clk) x <= 0;\n\t\t\t@(posedge clk) x <= 1;\n\t\t\t@(posedge clk) x <= 0;\n\t\t@(negedge clk) wavedrom_stop();\n\n\t\trepeat(400) @(posedge clk, negedge clk) begin\n\t\t\tx <= $random;\n\t\t\treset <= ($random&31) == 0;\n\t\tend\n\t\t\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_z;\n\t\tint errortime_z;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic aresetn;\n\tlogic x;\n\tlogic z_ref;\n\tlogic z_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,aresetn,x,z_ref,z_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.aresetn,\n\t\t.x );\n\treference_module good1 (\n\t\t.clk,\n\t\t.aresetn,\n\t\t.x,\n\t\t.z(z_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.aresetn,\n\t\t.x,\n\t\t.z(z_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_z) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"z\", stats1.errors_z, stats1.errortime_z);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"z\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { z_ref } === ( { z_ref } ^ { z_dut } ^ { z_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (z_ref !== ( z_ref ^ z_dut ^ z_ref ))\n\t\tbegin if (stats1.errors_z == 0) stats1.errortime_z = $time;\n\t\t\tstats1.errors_z = stats1.errors_z+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "m2014_q6", "task_number": 14, "description": "Consider the state machine shown below:\n\n// A (0) --0--> B\n// A (0) --1--> A\n// B (0) --0--> C\n// B (0) --1--> D\n// C (0) --0--> E\n// C (0) --1--> D\n// D (0) --0--> F\n// D (0) --1--> A\n// E (1) --0--> E\n// E (1) --1--> D\n// F (1) --0--> C\n// F (1) --1--> D\n\n// Implement this state machine in Verilog.", "header": "module top_module (\n\tinput clk,\n\tinput reset,\n\tinput w,\n\toutput z\n);\n", "module_code": "module top_module (\n\tinput clk,\n\tinput reset,\n\tinput w,\n\toutput z\n);\n\tparameter A=0, B=1, C=2, D=3, E=4, F=5;\n\treg [2:0] state, next;\n\t\n\talways @(posedge clk)\n\t\tif (reset)\n\t\t\tstate <= A;\n\t\telse \n\t\t\tstate <= next;\n\t\t\t\n\t\t\t\n\talways_comb begin\n\t\tcase(state)\n\t\t\tA: next = w ? A : B;\n\t\t\tB: next = w ? D : C;\n\t\t\tC: next = w ? D : E;\n\t\t\tD: next = w ? A : F;\n\t\t\tE: next = w ? D : E;\n\t\t\tF: next = w ? D : C;\n\t\t\tdefault: next = 'x;\n\t\tendcase\n\tend\n\t\n\tassign z = (state == E || state == F);\n\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput reset,\n\tinput w,\n\toutput z\n);\n\tparameter A=0, B=1, C=2, D=3, E=4, F=5;\n\treg [2:0] state, next;\n\t\n\talways @(posedge clk)\n\t\tif (reset)\n\t\t\tstate <= A;\n\t\telse \n\t\t\tstate <= next;\n\t\t\t\n\t\t\t\n\talways_comb begin\n\t\tcase(state)\n\t\t\tA: next = w ? A : B;\n\t\t\tB: next = w ? D : C;\n\t\t\tC: next = w ? D : E;\n\t\t\tD: next = w ? A : F;\n\t\t\tE: next = w ? D : E;\n\t\t\tF: next = w ? D : C;\n\t\t\tdefault: next = 'x;\n\t\tendcase\n\tend\n\t\n\tassign z = (state == E || state == F);\n\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic reset,\n\toutput logic w\n);\n\n\tinitial begin\n\t\trepeat(200) @(posedge clk, negedge clk) begin\n\t\t\tw <= $random;\n\t\t\treset <= ($random & 15) == 0;\n\t\tend\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_z;\n\t\tint errortime_z;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic reset;\n\tlogic w;\n\tlogic z_ref;\n\tlogic z_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,w,z_ref,z_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.reset,\n\t\t.w );\n\treference_module good1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.w,\n\t\t.z(z_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.w,\n\t\t.z(z_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_z) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"z\", stats1.errors_z, stats1.errortime_z);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"z\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { z_ref } === ( { z_ref } ^ { z_dut } ^ { z_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (z_ref !== ( z_ref ^ z_dut ^ z_ref ))\n\t\tbegin if (stats1.errors_z == 0) stats1.errortime_z = $time;\n\t\t\tstats1.errors_z = stats1.errors_z+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "fsm_ps2data", "task_number": 15, "description": "We want a finite state machine that will search for message boundaries when given an input byte stream. The algorithm we'll use is to discard bytes until we see one with in[3]=1. We then assume that this is byte 1 of a message, and signal the receipt of a message once all 3 bytes have been received (done). The FSM should signal done in the cycle immediately after the third byte of each message was successfully received.\n\n// Implement the datapath module that will output the 24-bit (3 byte) message whenever a packet is received (out_bytes[23:16] is the first byte, out_bytes[15:8] is the second byte, etc.). The reset signal is active high synchronous. out_bytes needs to be valid whenever the done signal is asserted. You may output anything at other times (i.e., don't-care). \n\n// Waveform example:\n// time            clk             reset           in[7:0]         done            out_bytes       \n// 0ns             0               1                0              x                    x          \n// 5ns             1               1                0              0                    x          \n// 10ns            0               1                0              0                    x          \n// 15ns            1               0               2c              0                    x          \n// 20ns            0               0               2c              0                    x          \n// 25ns            1               0               81              0                    x          \n// 30ns            0               0               81              0                    x          \n// 35ns            1               0                9              0                    x          \n// 40ns            0               0                9              0                    x          \n// 45ns            1               0               6b              1               2c8109          \n// 50ns            0               0               6b              1               2c8109          \n// 55ns            1               0                d              0                    x          \n// 60ns            0               0                d              0                    x          \n// 65ns            1               0               8d              0                    x          \n// 70ns            0               0               8d              0                    x          \n// 75ns            1               0               6d              1               6b0d8d          \n// 80ns            0               0               6d              1               6b0d8d          \n// 85ns            1               0               12              0                    x          \n// 90ns            0               0               12              0                    x          \n// 95ns            1               0                1              0                    x          \n// 100ns           0               0                1              0                    x          \n// 105ns           1               0                d              1               6d1201          \n// 110ns           0               0                d              1               6d1201          \n// 115ns           1               0               76              0                    x          \n// 120ns           0               0               76              0                    x          \n// 125ns           1               0               3d              0                    x          \n// 130ns           0               0               3d              0                    x          \n// 135ns           1               0               ed              1                d763d          \n// 140ns           0               0               ed              1                d763d          \n// 145ns           1               0               8c              0                    x          \n// 150ns           0               0               8c              0                    x          \n// 155ns           1               0               f9              0                    x          \n// 160ns           0               0               f9              0                    x          \n// 165ns           1               0               ce              1               ed8cf9          \n// 170ns           0               0               ce              1               ed8cf9          \n// 175ns           1               0               c5              0                    x          \n// 180ns           0               0               c5              0                    x          \n// 185ns           1               0               aa              0                    x          \n// 190ns           0               0               aa              0                    x          ", "header": "module top_module (\n\tinput clk,\n\tinput [7:0] in,\n\tinput reset,\n\toutput [23:0] out_bytes,\n\toutput done\n);\n", "module_code": "module top_module (\n\tinput clk,\n\tinput [7:0] in,\n\tinput reset,\n\toutput [23:0] out_bytes,\n\toutput done\n);\n\tparameter BYTE1=0, BYTE2=1, BYTE3=2, DONE=3;\n\treg [1:0] state;\n\treg [1:0] next;\n    \n    wire in3 = in[3];\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tBYTE1: next = in3 ? BYTE2 : BYTE1;\n\t\t\tBYTE2: next = BYTE3;\n\t\t\tBYTE3: next = DONE;\n\t\t\tDONE: next = in3 ? BYTE2 : BYTE1;\n\t\tendcase\n    end\n    \n    always @(posedge clk) begin\n\t\tif (reset) state <= BYTE1;\n        else state <= next;\n\tend\n\t\t\n\tassign done = (state==DONE);\n\t\n\treg [23:0] out_bytes_r;\n\talways @(posedge clk)\n\t\tout_bytes_r <= {out_bytes_r[15:0], in};\n\t\n\t// Implementations may vary: Allow user to do anything while the output doesn't have to be valid.\t\n\tassign out_bytes = done ? out_bytes_r : 'x;\t\t\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput [7:0] in,\n\tinput reset,\n\toutput [23:0] out_bytes,\n\toutput done\n);\n\tparameter BYTE1=0, BYTE2=1, BYTE3=2, DONE=3;\n\treg [1:0] state;\n\treg [1:0] next;\n    \n    wire in3 = in[3];\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tBYTE1: next = in3 ? BYTE2 : BYTE1;\n\t\t\tBYTE2: next = BYTE3;\n\t\t\tBYTE3: next = DONE;\n\t\t\tDONE: next = in3 ? BYTE2 : BYTE1;\n\t\tendcase\n    end\n    \n    always @(posedge clk) begin\n\t\tif (reset) state <= BYTE1;\n        else state <= next;\n\tend\n\t\t\n\tassign done = (state==DONE);\n\t\n\treg [23:0] out_bytes_r;\n\talways @(posedge clk)\n\t\tout_bytes_r <= {out_bytes_r[15:0], in};\n\t\n\t// Implementations may vary: Allow user to do anything while the output doesn't have to be valid.\t\n\tassign out_bytes = done ? out_bytes_r : 'x;\t\t\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic [7:0] in,\n\toutput logic reset\n);\n\n\tinitial begin\n\t\trepeat(200) @(negedge clk) begin\n\t\t\tin <= $random;\n\t\t\treset <= !($random & 31);\n\t\tend\n\t\treset <= 1'b0;\n\t\tin <= '0;\n\t\trepeat(10) @(posedge clk);\n\t\t\n\t\trepeat(200) begin\n\t\t\tin <= $random;\n\t\t\tin[3] <= 1'b1;\n\t\t\t@(posedge clk);\n\t\t\tin <= $random;\n\t\t\t@(posedge clk);\n\t\t\tin <= $random;\n\t\t\t@(posedge clk);\n\t\tend\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out_bytes;\n\t\tint errortime_out_bytes;\n\t\tint errors_done;\n\t\tint errortime_done;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [7:0] in;\n\tlogic reset;\n\tlogic [23:0] out_bytes_ref;\n\tlogic [23:0] out_bytes_dut;\n\tlogic done_ref;\n\tlogic done_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,in,reset,out_bytes_ref,out_bytes_dut,done_ref,done_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in,\n\t\t.reset );\n\treference_module good1 (\n\t\t.clk,\n\t\t.in,\n\t\t.reset,\n\t\t.out_bytes(out_bytes_ref),\n\t\t.done(done_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.in,\n\t\t.reset,\n\t\t.out_bytes(out_bytes_dut),\n\t\t.done(done_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out_bytes) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_bytes\", stats1.errors_out_bytes, stats1.errortime_out_bytes);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_bytes\");\n\t\tif (stats1.errors_done) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"done\", stats1.errors_done, stats1.errortime_done);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"done\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_bytes_ref, done_ref } === ( { out_bytes_ref, done_ref } ^ { out_bytes_dut, done_dut } ^ { out_bytes_ref, done_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_bytes_ref !== ( out_bytes_ref ^ out_bytes_dut ^ out_bytes_ref ))\n\t\tbegin if (stats1.errors_out_bytes == 0) stats1.errortime_out_bytes = $time;\n\t\t\tstats1.errors_out_bytes = stats1.errors_out_bytes+1'b1; end\n\t\tif (done_ref !== ( done_ref ^ done_dut ^ done_ref ))\n\t\tbegin if (stats1.errors_done == 0) stats1.errortime_done = $time;\n\t\t\tstats1.errors_done = stats1.errors_done+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "2012_q2b", "task_number": 16, "description": "\n// Consider the state machine shown below:\n\n// A (0) --1--> B\n// A (0) --0--> A\n// B (0) --1--> C\n// B (0) --0--> D\n// C (0) --1--> E\n// C (0) --0--> D\n// D (0) --1--> F\n// D (0) --0--> A\n// E (1) --1--> E\n// E (1) --0--> D\n// F (1) --1--> C\n// F (1) --0--> D\n\n// Assume that a one-hot code is used with the state assignment y[5:0] = 000001(A), 000010(B), 000100(C), 001000(D), 010000(E), 100000(F)\n\n// Write a Verilog for the signal Y1, which is the input of state flip-flop y[1], for the signal Y3, which is the input of state flip-flop y[3]. Derive the Verilog by inspection assuming a one-hot encoding.\n", "header": "module top_module (\n\tinput [5:0] y,\n\tinput w,\n\toutput Y1,\n\toutput Y3\n);\n", "module_code": "module top_module (\n\tinput [5:0] y,\n\tinput w,\n\toutput Y1,\n\toutput Y3\n);\n\tassign Y1 = y[0]&w;\n\tassign Y3 = (y[1]|y[2]|y[4]|y[5]) & ~w;\n\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [5:0] y,\n\tinput w,\n\toutput Y1,\n\toutput Y3\n);\n\tassign Y1 = y[0]&w;\n\tassign Y3 = (y[1]|y[2]|y[4]|y[5]) & ~w;\n\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic[5:0] y,\n\toutput logic w,\n\tinput tb_match\n);\n\n\tint errored1 = 0;\n\tint onehot_error = 0;\n\tint temp;\n\t\n\tinitial begin\n\t\t// Test the one-hot cases first.\n\t\trepeat(200) @(posedge clk, negedge clk) begin\n\t\t\ty <= 1<< ($unsigned($random) % 6);\n\t\t\tw <= $random;\n\t\t\tif (!tb_match) onehot_error++;\n\t\tend\n\t\t\t\n\t\t\t\n\t\t// Random.\n\t\terrored1 = 0;\n\t\trepeat(400) @(posedge clk, negedge clk) begin\n\t\t\tdo \n\t\t\t\ttemp = $random;\n\t\t\twhile ( !{temp[5:4],temp[2:1]} == !{temp[3],temp[0]} );\t\n\t\t\t// Make y[3,0] and y[5,4,2,1] mutually exclusive, so we can accept Y3=(~y[3] & ~y[0]) &~w as a valid answer too.\n\n\t\t\ty <= temp;\n\t\t\tw <= $random;\n\t\t\tif (!tb_match)\n\t\t\t\terrored1++;\n\t\tend\n\t\tif (!onehot_error && errored1) \n\t\t\t$display (\"Hint: Your circuit passed when given only one-hot inputs, but not with semi-random inputs.\");\n\n\t\tif (!onehot_error && errored1)\n\t\t\t$display(\"Hint: Are you doing something more complicated than deriving state transition equations by inspection?\\n\");\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_Y1;\n\t\tint errortime_Y1;\n\t\tint errors_Y3;\n\t\tint errortime_Y3;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [5:0] y;\n\tlogic w;\n\tlogic Y1_ref;\n\tlogic Y1_dut;\n\tlogic Y3_ref;\n\tlogic Y3_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,y,w,Y1_ref,Y1_dut,Y3_ref,Y3_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.y,\n\t\t.w );\n\treference_module good1 (\n\t\t.y,\n\t\t.w,\n\t\t.Y1(Y1_ref),\n\t\t.Y3(Y3_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.y,\n\t\t.w,\n\t\t.Y1(Y1_dut),\n\t\t.Y3(Y3_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_Y1) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"Y1\", stats1.errors_Y1, stats1.errortime_Y1);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"Y1\");\n\t\tif (stats1.errors_Y3) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"Y3\", stats1.errors_Y3, stats1.errortime_Y3);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"Y3\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { Y1_ref, Y3_ref } === ( { Y1_ref, Y3_ref } ^ { Y1_dut, Y3_dut } ^ { Y1_ref, Y3_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (Y1_ref !== ( Y1_ref ^ Y1_dut ^ Y1_ref ))\n\t\tbegin if (stats1.errors_Y1 == 0) stats1.errortime_Y1 = $time;\n\t\t\tstats1.errors_Y1 = stats1.errors_Y1+1'b1; end\n\t\tif (Y3_ref !== ( Y3_ref ^ Y3_dut ^ Y3_ref ))\n\t\tbegin if (stats1.errors_Y3 == 0) stats1.errortime_Y3 = $time;\n\t\t\tstats1.errors_Y3 = stats1.errors_Y3+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "vector0", "task_number": 17, "description": "Build a circuit that has one 3-bit input, then outputs the same vector, and also splits it into three separate 1-bit outputs. Connect output o0 to the input vector's position 0, o1 to position 1, etc.", "header": "module top_module(\n\tinput [2:0] vec, \n\toutput [2:0] outv,\n\toutput o2,\n\toutput o1,\n\toutput o0\n);\n", "module_code": "module top_module(\n\tinput [2:0] vec, \n\toutput [2:0] outv,\n\toutput o2,\n\toutput o1,\n\toutput o0\n);\n\t\n\tassign outv = vec;\n\tassign {o2, o1, o0} = vec;\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput [2:0] vec, \n\toutput [2:0] outv,\n\toutput o2,\n\toutput o1,\n\toutput o0\n);\n\t\n\tassign outv = vec;\n\tassign {o2, o1, o0} = vec;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg [2:0] vec,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\tint count; count = 0;\n\t\tvec <= 3'b0;\n\t\t@(negedge clk);\n\t\twavedrom_start();\n\t\trepeat(10) @(posedge clk)\n\t\t\tvec <= count++;\t\t\n\t\twavedrom_stop();\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_outv;\n\t\tint errortime_outv;\n\t\tint errors_o2;\n\t\tint errortime_o2;\n\t\tint errors_o1;\n\t\tint errortime_o1;\n\t\tint errors_o0;\n\t\tint errortime_o0;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [2:0] vec;\n\tlogic [2:0] outv_ref;\n\tlogic [2:0] outv_dut;\n\tlogic o2_ref;\n\tlogic o2_dut;\n\tlogic o1_ref;\n\tlogic o1_dut;\n\tlogic o0_ref;\n\tlogic o0_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,vec,outv_ref,outv_dut,o2_ref,o2_dut,o1_ref,o1_dut,o0_ref,o0_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.vec );\n\treference_module good1 (\n\t\t.vec,\n\t\t.outv(outv_ref),\n\t\t.o2(o2_ref),\n\t\t.o1(o1_ref),\n\t\t.o0(o0_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.vec,\n\t\t.outv(outv_dut),\n\t\t.o2(o2_dut),\n\t\t.o1(o1_dut),\n\t\t.o0(o0_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_outv) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"outv\", stats1.errors_outv, stats1.errortime_outv);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"outv\");\n\t\tif (stats1.errors_o2) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"o2\", stats1.errors_o2, stats1.errortime_o2);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"o2\");\n\t\tif (stats1.errors_o1) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"o1\", stats1.errors_o1, stats1.errortime_o1);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"o1\");\n\t\tif (stats1.errors_o0) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"o0\", stats1.errors_o0, stats1.errortime_o0);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"o0\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { outv_ref, o2_ref, o1_ref, o0_ref } === ( { outv_ref, o2_ref, o1_ref, o0_ref } ^ { outv_dut, o2_dut, o1_dut, o0_dut } ^ { outv_ref, o2_ref, o1_ref, o0_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (outv_ref !== ( outv_ref ^ outv_dut ^ outv_ref ))\n\t\tbegin if (stats1.errors_outv == 0) stats1.errortime_outv = $time;\n\t\t\tstats1.errors_outv = stats1.errors_outv+1'b1; end\n\t\tif (o2_ref !== ( o2_ref ^ o2_dut ^ o2_ref ))\n\t\tbegin if (stats1.errors_o2 == 0) stats1.errortime_o2 = $time;\n\t\t\tstats1.errors_o2 = stats1.errors_o2+1'b1; end\n\t\tif (o1_ref !== ( o1_ref ^ o1_dut ^ o1_ref ))\n\t\tbegin if (stats1.errors_o1 == 0) stats1.errortime_o1 = $time;\n\t\t\tstats1.errors_o1 = stats1.errors_o1+1'b1; end\n\t\tif (o0_ref !== ( o0_ref ^ o0_dut ^ o0_ref ))\n\t\tbegin if (stats1.errors_o0 == 0) stats1.errortime_o0 = $time;\n\t\t\tstats1.errors_o0 = stats1.errors_o0+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "kmap4", "task_number": 18, "description": "Implement the circuit described by the Karnaugh map below.\n\n//        ab\n// cd   00 01 11 10\n//  00 | 0 | 1 | 0 | 1 |\n//  01 | 1 | 0 | 1 | 0 |\n//  11 | 0 | 1 | 0 | 1 |\n//  10 | 1 | 0 | 1 | 0 |", "header": "module top_module (\n\tinput a, \n\tinput b,\n\tinput c,\n\tinput d,\n\toutput reg out\n);\n", "module_code": "module top_module (\n\tinput a, \n\tinput b,\n\tinput c,\n\tinput d,\n\toutput reg out\n);\n\t\n    always @(*) begin\n        case({a,b,c,d})\n            4'h0: out = 0;\n            4'h1: out = 1;\n            4'h3: out = 0;\n            4'h2: out = 1;\n            4'h4: out = 1;\n            4'h5: out = 0;\n            4'h7: out = 1;\n            4'h6: out = 0;\n            4'hc: out = 0;\n            4'hd: out = 1;\n            4'hf: out = 0;\n            4'he: out = 1;\n            4'h8: out = 1;\n            4'h9: out = 0;\n            4'hb: out = 1;\n            4'ha: out = 0;\n        endcase\n    end\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput a, \n\tinput b,\n\tinput c,\n\tinput d,\n\toutput reg out\n);\n\t\n    always @(*) begin\n        case({a,b,c,d})\n            4'h0: out = 0;\n            4'h1: out = 1;\n            4'h3: out = 0;\n            4'h2: out = 1;\n            4'h4: out = 1;\n            4'h5: out = 0;\n            4'h7: out = 1;\n            4'h6: out = 0;\n            4'hc: out = 0;\n            4'hd: out = 1;\n            4'hf: out = 0;\n            4'he: out = 1;\n            4'h8: out = 1;\n            4'h9: out = 0;\n            4'hb: out = 1;\n            4'ha: out = 0;\n        endcase\n    end\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg a, b, c, d,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\tint count; count = 0;\n\t\t{a,b,c,d} <= 4'b0;\n\t\twavedrom_start();\n\t\trepeat(16) @(posedge clk)\n\t\t\t{a,b,c,d} <= count++;\t\t\n\t\t@(negedge clk) wavedrom_stop();\n\t\t\n\t\trepeat(200) @(posedge clk, negedge clk)\n\t\t\t{d,c,b,a} <= $urandom;\n\t\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic a;\n\tlogic b;\n\tlogic c;\n\tlogic d;\n\tlogic out_ref;\n\tlogic out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,a,b,c,d,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d );\n\treference_module good1 (\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "vector1", "task_number": 19, "description": "Build a combinational circuit that splits an input half-word (16 bits, [15:0] ) into lower [7:0] and upper [15:8] bytes.", "header": "module top_module (\n\tinput [15:0] in,\n\toutput [7:0] out_hi,\n\toutput [7:0] out_lo\n);\n", "module_code": "module top_module (\n\tinput [15:0] in,\n\toutput [7:0] out_hi,\n\toutput [7:0] out_lo\n);\n\t\n\tassign {out_hi, out_lo} = in;\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [15:0] in,\n\toutput [7:0] out_hi,\n\toutput [7:0] out_lo\n);\n\t\n\tassign {out_hi, out_lo} = in;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic [15:0] in,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\talways @(posedge clk, negedge clk)\n\t\tin <= $random;\n\t\n\tinitial begin\n\t\twavedrom_start(\"Random inputs\");\n\t\trepeat(10) @(posedge clk);\n\t\twavedrom_stop();\n\t\trepeat(100) @(negedge clk);\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out_hi;\n\t\tint errortime_out_hi;\n\t\tint errors_out_lo;\n\t\tint errortime_out_lo;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [15:0] in;\n\tlogic [7:0] out_hi_ref;\n\tlogic [7:0] out_hi_dut;\n\tlogic [7:0] out_lo_ref;\n\tlogic [7:0] out_lo_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,in,out_hi_ref,out_hi_dut,out_lo_ref,out_lo_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in );\n\treference_module good1 (\n\t\t.in,\n\t\t.out_hi(out_hi_ref),\n\t\t.out_lo(out_lo_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.in,\n\t\t.out_hi(out_hi_dut),\n\t\t.out_lo(out_lo_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out_hi) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_hi\", stats1.errors_out_hi, stats1.errortime_out_hi);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_hi\");\n\t\tif (stats1.errors_out_lo) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_lo\", stats1.errors_out_lo, stats1.errortime_out_lo);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_lo\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_hi_ref, out_lo_ref } === ( { out_hi_ref, out_lo_ref } ^ { out_hi_dut, out_lo_dut } ^ { out_hi_ref, out_lo_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_hi_ref !== ( out_hi_ref ^ out_hi_dut ^ out_hi_ref ))\n\t\tbegin if (stats1.errors_out_hi == 0) stats1.errortime_out_hi = $time;\n\t\t\tstats1.errors_out_hi = stats1.errors_out_hi+1'b1; end\n\t\tif (out_lo_ref !== ( out_lo_ref ^ out_lo_dut ^ out_lo_ref ))\n\t\tbegin if (stats1.errors_out_lo == 0) stats1.errortime_out_lo = $time;\n\t\t\tstats1.errors_out_lo = stats1.errors_out_lo+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "norgate", "task_number": 20, "description": "Create a module that implements a NOR gate.", "header": "module top_module(\n\tinput a, \n\tinput b,\n\toutput out\n);\n", "module_code": "module top_module(\n\tinput a, \n\tinput b,\n\toutput out\n);\n\t\n\tassign out = ~(a | b);\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput a, \n\tinput b,\n\toutput out\n);\n\t\n\tassign out = ~(a | b);\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg a, b,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\tint count; count = 0;\n\t\t{a,b} <= 1'b0;\n\t\twavedrom_start(\"NOR gate\");\n\t\trepeat(10) @(posedge clk)\n\t\t\t{a,b} <= count++;\t\t\n\t\twavedrom_stop();\n\t\t\n\t\trepeat(200) @(posedge clk, negedge clk)\n\t\t\t{b,a} <= $random;\n\t\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic a;\n\tlogic b;\n\tlogic out_ref;\n\tlogic out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,a,b,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.a,\n\t\t.b );\n\treference_module good1 (\n\t\t.a,\n\t\t.b,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.a,\n\t\t.b,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "alwaysblock2", "task_number": 21, "description": "Build an XOR gate three ways, using an assign statement (output out_assign), a combinational always block (output out_always_comb), and a clocked always block (output out_always_ff). Note that the clocked always block produces a different circuit from the other two: There is a flip-flop so the output is delayed.", "header": "module top_module(\n\tinput clk,\n\tinput a, \n\tinput b,\n\toutput out_assign,\n\toutput reg out_always_comb,\n\toutput reg out_always_ff\n);\n", "module_code": "module top_module(\n\tinput clk,\n\tinput a, \n\tinput b,\n\toutput out_assign,\n\toutput reg out_always_comb,\n\toutput reg out_always_ff\n);\n\t\n\tassign out_assign = a ^ b;\n\talways @(*) out_always_comb = a ^ b;\n\talways @(posedge clk) out_always_ff <= a ^ b;\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput clk,\n\tinput a, \n\tinput b,\n\toutput out_assign,\n\toutput reg out_always_comb,\n\toutput reg out_always_ff\n);\n\t\n\tassign out_assign = a ^ b;\n\talways @(*) out_always_comb = a ^ b;\n\talways @(posedge clk) out_always_ff <= a ^ b;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg a, b,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\tint count; count = 0;\n\t\t{a,b} <= 1'b0;\n\t\twavedrom_start(\"XOR gate\");\n\t\trepeat(10) @(posedge clk)\n\t\t\t{a,b} <= count++;\t\t\n\t\twavedrom_stop();\n\t\t\n\t\trepeat(200) @(posedge clk, negedge clk)\n\t\t\t{b,a} <= $urandom;\n\t\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out_assign;\n\t\tint errortime_out_assign;\n\t\tint errors_out_always_comb;\n\t\tint errortime_out_always_comb;\n\t\tint errors_out_always_ff;\n\t\tint errortime_out_always_ff;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic a;\n\tlogic b;\n\tlogic out_assign_ref;\n\tlogic out_assign_dut;\n\tlogic out_always_comb_ref;\n\tlogic out_always_comb_dut;\n\tlogic out_always_ff_ref;\n\tlogic out_always_ff_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,a,b,out_assign_ref,out_assign_dut,out_always_comb_ref,out_always_comb_dut,out_always_ff_ref,out_always_ff_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.a,\n\t\t.b );\n\treference_module good1 (\n\t\t.clk,\n\t\t.a,\n\t\t.b,\n\t\t.out_assign(out_assign_ref),\n\t\t.out_always_comb(out_always_comb_ref),\n\t\t.out_always_ff(out_always_ff_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.a,\n\t\t.b,\n\t\t.out_assign(out_assign_dut),\n\t\t.out_always_comb(out_always_comb_dut),\n\t\t.out_always_ff(out_always_ff_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out_assign) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_assign\", stats1.errors_out_assign, stats1.errortime_out_assign);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_assign\");\n\t\tif (stats1.errors_out_always_comb) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_always_comb\", stats1.errors_out_always_comb, stats1.errortime_out_always_comb);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_always_comb\");\n\t\tif (stats1.errors_out_always_ff) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_always_ff\", stats1.errors_out_always_ff, stats1.errortime_out_always_ff);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_always_ff\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_assign_ref, out_always_comb_ref, out_always_ff_ref } === ( { out_assign_ref, out_always_comb_ref, out_always_ff_ref } ^ { out_assign_dut, out_always_comb_dut, out_always_ff_dut } ^ { out_assign_ref, out_always_comb_ref, out_always_ff_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_assign_ref !== ( out_assign_ref ^ out_assign_dut ^ out_assign_ref ))\n\t\tbegin if (stats1.errors_out_assign == 0) stats1.errortime_out_assign = $time;\n\t\t\tstats1.errors_out_assign = stats1.errors_out_assign+1'b1; end\n\t\tif (out_always_comb_ref !== ( out_always_comb_ref ^ out_always_comb_dut ^ out_always_comb_ref ))\n\t\tbegin if (stats1.errors_out_always_comb == 0) stats1.errortime_out_always_comb = $time;\n\t\t\tstats1.errors_out_always_comb = stats1.errors_out_always_comb+1'b1; end\n\t\tif (out_always_ff_ref !== ( out_always_ff_ref ^ out_always_ff_dut ^ out_always_ff_ref ))\n\t\tbegin if (stats1.errors_out_always_ff == 0) stats1.errortime_out_always_ff = $time;\n\t\t\tstats1.errors_out_always_ff = stats1.errors_out_always_ff+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "m2014_q6c", "task_number": 22, "description": "Consider the state machine shown below:\n\n// A (0) --0--> B\n// A (0) --1--> A\n// B (0) --0--> C\n// B (0) --1--> D\n// C (0) --0--> E\n// C (0) --1--> D\n// D (0) --0--> F\n// D (0) --1--> A\n// E (1) --0--> E\n// E (1) --1--> D\n// F (1) --0--> C\n// F (1) --1--> D\n\n// Resets into state A. For this part, assume that a one-hot code is used with the state assignment y[6:1] = 000001, 000010, 000100, 001000, 010000, 100000 for states A, B,..., F, respectively.\n\n// Write Verilog for the next-state signals Y2 and Y4 corresponding to signal y[2] and y[4]. Derive the logic equations by inspection assuming a one-hot encoding. ", "header": "module top_module (\n\tinput [6:1] y,\n\tinput w,\n\toutput Y2,\n\toutput Y4\n);\n", "module_code": "module top_module (\n\tinput [6:1] y,\n\tinput w,\n\toutput Y2,\n\toutput Y4\n);\n\tassign Y2 = y[1]&~w;\n\tassign Y4 = (y[2]|y[3]|y[5]|y[6]) & w;\n\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [6:1] y,\n\tinput w,\n\toutput Y2,\n\toutput Y4\n);\n\tassign Y2 = y[1]&~w;\n\tassign Y4 = (y[2]|y[3]|y[5]|y[6]) & w;\n\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic[6:1] y,\n\toutput logic w,\n\tinput tb_match\n);\n\n\tint errored1 = 0;\n\tint onehot_error = 0;\n\tint temp;\n\t\n\tinitial begin\n\t\t// Test the one-hot cases first.\n\t\trepeat(200) @(posedge clk, negedge clk) begin\n\t\t\ty <= 1<< ($unsigned($random) % 6);\n\t\t\tw <= $random;\n\t\t\tif (!tb_match) onehot_error++;\n\t\tend\n\t\t\t\n\t\t\t\n\t\t// Random.\n\t\terrored1 = 0;\n\t\trepeat(400) @(posedge clk, negedge clk) begin\n\t\t\tdo \n\t\t\t\ttemp = $random;\n\t\t\twhile ( !{temp[6:5],temp[3:2]} == !{temp[4],temp[1]} );\t\n\t\t\t// Make y[4,1] and y[6,5,3,2] mutually exclusive, so we can accept Y4=(~y[1] & ~y[4]) &w as a valid answer too.\n\n\t\t\ty[6:1] <= temp[6:1];\n\t\t\tw <= $random;\n\t\t\tif (!tb_match)\n\t\t\t\terrored1++;\n\t\tend\n\t\tif (!onehot_error && errored1) \n\t\t\t$display (\"Hint: Your circuit passed when given only one-hot inputs, but not with semi-random inputs.\");\n\n\t\tif (!onehot_error && errored1)\n\t\t\t$display(\"Hint: Are you doing something more complicated than deriving state transition equations by inspection?\\n\");\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_Y2;\n\t\tint errortime_Y2;\n\t\tint errors_Y4;\n\t\tint errortime_Y4;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [6:1] y;\n\tlogic w;\n\tlogic Y2_ref;\n\tlogic Y2_dut;\n\tlogic Y4_ref;\n\tlogic Y4_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,y,w,Y2_ref,Y2_dut,Y4_ref,Y4_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.y,\n\t\t.w );\n\treference_module good1 (\n\t\t.y,\n\t\t.w,\n\t\t.Y2(Y2_ref),\n\t\t.Y4(Y4_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.y,\n\t\t.w,\n\t\t.Y2(Y2_dut),\n\t\t.Y4(Y4_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_Y2) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"Y2\", stats1.errors_Y2, stats1.errortime_Y2);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"Y2\");\n\t\tif (stats1.errors_Y4) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"Y4\", stats1.errors_Y4, stats1.errortime_Y4);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"Y4\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { Y2_ref, Y4_ref } === ( { Y2_ref, Y4_ref } ^ { Y2_dut, Y4_dut } ^ { Y2_ref, Y4_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (Y2_ref !== ( Y2_ref ^ Y2_dut ^ Y2_ref ))\n\t\tbegin if (stats1.errors_Y2 == 0) stats1.errortime_Y2 = $time;\n\t\t\tstats1.errors_Y2 = stats1.errors_Y2+1'b1; end\n\t\tif (Y4_ref !== ( Y4_ref ^ Y4_dut ^ Y4_ref ))\n\t\tbegin if (stats1.errors_Y4 == 0) stats1.errortime_Y4 = $time;\n\t\t\tstats1.errors_Y4 = stats1.errors_Y4+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "mux256to1", "task_number": 23, "description": "Create a 1-bit wide, 256-to-1 multiplexer. The 256 inputs are all packed into a single 256-bit input vector. sel=0 should select in[0], sel=1 selects bits in[1], sel=2 selects bits in[2], etc.", "header": "module top_module (\n\tinput [255:0] in,\n\tinput [7:0] sel,\n\toutput  out\n);\n", "module_code": "module top_module (\n\tinput [255:0] in,\n\tinput [7:0] sel,\n\toutput  out\n);\n\n\tassign out = in[sel];\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [255:0] in,\n\tinput [7:0] sel,\n\toutput  out\n);\n\n\tassign out = in[sel];\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic [255:0] in,\n\toutput logic [7:0] sel\n);\n\n\talways @(posedge clk, negedge clk) begin\n\t\tfor (int i=0;i<8; i++)\n\t\t\tin[i*32+:32] <= $random;\n\t\tsel <= $random;\n\tend\n\t\n\tinitial begin\n\t\trepeat(1000) @(negedge clk);\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [255:0] in;\n\tlogic [7:0] sel;\n\tlogic out_ref;\n\tlogic out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,in,sel,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in,\n\t\t.sel );\n\treference_module good1 (\n\t\t.in,\n\t\t.sel,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.in,\n\t\t.sel,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "2014_q4a", "task_number": 24, "description": "Consider an n-bit shift register circuit. Inputs E are for enabling shift, R for value to load, L is asserted when it should load, and w is the input to the first stage of the shift register. Write a Verilog module named top_module for one stage of this circuit, including both the flip-flop and multiplexers.", "header": "module top_module (\n\tinput clk,\n\tinput w,\n\tinput R,\n\tinput E,\n\tinput L,\n\toutput reg Q\n);\n", "module_code": "module top_module (\n\tinput clk,\n\tinput w,\n\tinput R,\n\tinput E,\n\tinput L,\n\toutput reg Q\n);\n\n\talways @(posedge clk)\n\t\tif (L)\n\t\t\tQ <= R;\n\t\telse if (E)\n\t\t\tQ <= w;\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput w,\n\tinput R,\n\tinput E,\n\tinput L,\n\toutput reg Q\n);\n\n\talways @(posedge clk)\n\t\tif (L)\n\t\t\tQ <= R;\n\t\telse if (E)\n\t\t\tQ <= w;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic w, R, E, L\n);\n\n\tinitial begin\n\t\trepeat(200) @(posedge clk, negedge clk) begin\n\t\t\t{w,R,E,L} <= $random;\n\t\tend\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_Q;\n\t\tint errortime_Q;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic w;\n\tlogic R;\n\tlogic E;\n\tlogic L;\n\tlogic Q_ref;\n\tlogic Q_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,w,R,E,L,Q_ref,Q_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.w,\n\t\t.R,\n\t\t.E,\n\t\t.L );\n\treference_module good1 (\n\t\t.clk,\n\t\t.w,\n\t\t.R,\n\t\t.E,\n\t\t.L,\n\t\t.Q(Q_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.w,\n\t\t.R,\n\t\t.E,\n\t\t.L,\n\t\t.Q(Q_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_Q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"Q\", stats1.errors_Q, stats1.errortime_Q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"Q\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { Q_ref } === ( { Q_ref } ^ { Q_dut } ^ { Q_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (Q_ref !== ( Q_ref ^ Q_dut ^ Q_ref ))\n\t\tbegin if (stats1.errors_Q == 0) stats1.errortime_Q = $time;\n\t\t\tstats1.errors_Q = stats1.errors_Q+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "ece241_2014_q4", "task_number": 25, "description": "Given the finite state machine circuit described below, assume that the D flip-flops are initially reset to zero before the machine begins.\n\n// Build this circuit in Verilog.\n\n// Input x goes to three different two-input gates: a XOR, an AND, and a OR gate. Each of the three gates is connected to the input of a D flip-flop and then the flip-flop outputs all go to a three-input XNOR, whose output is Z. The second input of the XOR is its corresponding flip-flop's output, the second input of the AND is its corresponding flip-flop's complemented output, and finally the second input of the OR is its corresponding flip-flop's complementary output.", "header": "module top_module (\n\tinput clk,\n\tinput x,\n\toutput z\n);\n", "module_code": "module top_module (\n\tinput clk,\n\tinput x,\n\toutput z\n);\n\t\n\treg [2:0] s = 0;\n\t\n\talways @(posedge clk) begin\n\t\ts <= { s[2] ^ x, ~s[1] & x, ~s[0] | x };\t\t\n\tend\n\t\n\tassign z = ~|s;\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput x,\n\toutput z\n);\n\t\n\treg [2:0] s = 0;\n\t\n\talways @(posedge clk) begin\n\t\ts <= { s[2] ^ x, ~s[1] & x, ~s[0] | x };\t\t\n\tend\n\t\n\tassign z = ~|s;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic x,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\tx <= 0;\n\t\t@(negedge clk) wavedrom_start();\n\t\t\t@(posedge clk) x <= 2'h0;\n\t\t\t@(posedge clk) x <= 2'h0;\n\t\t\t@(posedge clk) x <= 2'h0;\n\t\t\t@(posedge clk) x <= 2'h0;\n\t\t\t@(posedge clk) x <= 2'h1;\n\t\t\t@(posedge clk) x <= 2'h1;\n\t\t\t@(posedge clk) x <= 2'h1;\n\t\t\t@(posedge clk) x <= 2'h1;\n\t\t@(negedge clk) wavedrom_stop();\n\t\trepeat(100) @(posedge clk, negedge clk)\n\t\t\tx <= $random;\n\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_z;\n\t\tint errortime_z;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic x;\n\tlogic z_ref;\n\tlogic z_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,x,z_ref,z_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.x );\n\treference_module good1 (\n\t\t.clk,\n\t\t.x,\n\t\t.z(z_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.x,\n\t\t.z(z_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_z) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"z\", stats1.errors_z, stats1.errortime_z);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"z\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { z_ref } === ( { z_ref } ^ { z_dut } ^ { z_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (z_ref !== ( z_ref ^ z_dut ^ z_ref ))\n\t\tbegin if (stats1.errors_z == 0) stats1.errortime_z = $time;\n\t\t\tstats1.errors_z = stats1.errors_z+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "circuit4", "task_number": 26, "description": "This is a combinational circuit. Read the simulation waveforms to determine what the circuit does, then implement it.\n\n// time            a               b               c               d               q               \n// 0ns             0               0               0               0               0               \n// 5ns             0               0               0               0               0               \n// 10ns            0               0               0               0               0               \n// 15ns            0               0               0               0               0               \n// 20ns            0               0               0               1               0               \n// 25ns            0               0               1               0               1               \n// 30ns            0               0               1               1               1               \n// 35ns            0               1               0               0               1               \n// 40ns            0               1               0               1               1               \n// 45ns            0               1               1               0               1               \n// 50ns            0               1               1               1               1               \n// 55ns            1               0               0               0               0               \n// 60ns            1               0               0               1               0               \n// 65ns            1               0               1               0               1               \n// 70ns            1               0               1               1               1               \n// 75ns            1               1               0               0               1               \n// 80ns            1               1               0               1               1               \n// 85ns            1               1               1               0               1               \n// 90ns            1               1               1               1               1               ", "header": "module top_module (\n\tinput a, \n\tinput b, \n\tinput c, \n\tinput d,\n\toutput q\n);\n", "module_code": "module top_module (\n\tinput a, \n\tinput b, \n\tinput c, \n\tinput d,\n\toutput q\n);\n\n\tassign q = c | b;\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput a, \n\tinput b, \n\tinput c, \n\tinput d,\n\toutput q\n);\n\n\tassign q = c | b;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic a,b,c,d,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\t{a,b,c,d} <= 0;\n\t\t@(negedge clk) wavedrom_start(\"Unknown circuit\");\n\t\t\t@(posedge clk) {a,b,c,d} <= 0;\n\t\t\trepeat(18) @(posedge clk, negedge clk) {a,b,c,d} <= {a,b,c,d} + 1;\n\t\twavedrom_stop();\n\t\t\n\t\trepeat(100) @(posedge clk, negedge clk)\n\t\t\t{a,b,c,d} <= $urandom;\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_q;\n\t\tint errortime_q;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic a;\n\tlogic b;\n\tlogic c;\n\tlogic d;\n\tlogic q_ref;\n\tlogic q_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,a,b,c,d,q_ref,q_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d );\n\treference_module good1 (\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d,\n\t\t.q(q_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d,\n\t\t.q(q_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"q\", stats1.errors_q, stats1.errortime_q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"q\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (q_ref !== ( q_ref ^ q_dut ^ q_ref ))\n\t\tbegin if (stats1.errors_q == 0) stats1.errortime_q = $time;\n\t\t\tstats1.errors_q = stats1.errors_q+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "rule110", "task_number": 27, "description": "Rule 110 is a one-dimensional cellular automaton with interesting properties (such as being Turing-complete). There is a one-dimensional array of cells (on or off). At each time step, the state of each cell changes. In Rule 110, the next state of each cell depends only on itself and its two neighbours, according to the following table:\n// Left | Center | Right | Center's next state\n// 1 | 1 | 1 | 0\n// 1 | 1 | 0 | 1\n// 1 | 0 | 1 | 1\n// 1 | 0 | 0 | 0\n// 0 | 1 | 1 | 1\n// 0 | 1 | 0 | 1\n// 0 | 0 | 1 | 1\n// 0 | 0 | 0 | 0 \n// In this circuit, create a 512-cell system (q[511:0]), and advance by one time step each clock cycle. The synchronous active high load input indicates the state of the system should be loaded with data[511:0]. Assume the boundaries (q[-1] and q[512]) are both zero (off).", "header": "module top_module(\n\tinput clk,\n\tinput load,\n\tinput [511:0] data,\n\toutput reg [511:0] q);\n", "module_code": "module top_module(\n\tinput clk,\n\tinput load,\n\tinput [511:0] data,\n\toutput reg [511:0] q);\n\t\n\talways @(posedge clk) begin\n\t\tif (load)\n\t\t\tq <= data;\n\t\telse begin\n\t\t\tq <= \n\t\t\t~((q[$bits(q)-1:1] & q[$bits(q)-1:0] & {q[$bits(q)-2:0], 1'b0}) |\n\t\t\t(~q[$bits(q)-1:1] & ~q[$bits(q)-1:0] & ~{q[$bits(q)-2:0], 1'b0}) |  \n\t\t\t(q[$bits(q)-1:1] & ~q[$bits(q)-1:0] & ~{q[$bits(q)-2:0], 1'b0}) )\n\t\t\t;\n\t\tend\n\tend\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput clk,\n\tinput load,\n\tinput [511:0] data,\n\toutput reg [511:0] q);\n\t\n\talways @(posedge clk) begin\n\t\tif (load)\n\t\t\tq <= data;\n\t\telse begin\n\t\t\tq <= \n\t\t\t~((q[$bits(q)-1:1] & q[$bits(q)-1:0] & {q[$bits(q)-2:0], 1'b0}) |\n\t\t\t(~q[$bits(q)-1:1] & ~q[$bits(q)-1:0] & ~{q[$bits(q)-2:0], 1'b0}) |  \n\t\t\t(q[$bits(q)-1:1] & ~q[$bits(q)-1:0] & ~{q[$bits(q)-2:0], 1'b0}) )\n\t\t\t;\n\t\tend\n\tend\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg load,\n\toutput reg[511:0] data,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\tdata <= 0;\n\t\tdata[0] <= 1'b1;\n\t\tload <= 1;\n\t\t@(posedge clk); wavedrom_start(\"Load q[511:0] = 1: See Hint.\");\n\t\t@(posedge clk);\n\t\t@(posedge clk);\n\t\tload <= 0;\n\t\trepeat(10) @(posedge clk);\t\t\n\t\twavedrom_stop();\n\t\t\n\t\tdata <= 0;\n\t\tdata[256] <= 1'b1;\n\t\tload <= 1;\n\t\t@(posedge clk);\n\t\t@(posedge clk);\n\t\t@(posedge clk);\n\t\tload <= 0;\n\t\trepeat(1000) @(posedge clk) begin\n\t\tend\n\t\tdata <= 512'h4df;\n\t\tload <= 1;\n\t\t@(posedge clk);\n\t\tload <= 0;\n\t\trepeat(1000) @(posedge clk) begin\n\t\tend\n\t\tdata <= $random;\n\t\tload <= 1;\n\t\t@(posedge clk);\n\t\tload <= 0;\n\t\trepeat(1000) @(posedge clk) begin\n\t\tend\n\n\t\tdata <= 0;\n\t\tload <= 1;\n\t\trepeat (20) @(posedge clk);\n\t\t@(posedge clk) data <= 2;\n\t\t@(posedge clk) data <= 4;\n\t\t@(posedge clk) begin\n\t\t\tdata <= 9;\n\t\t\tload <= 0;\n\t\tend\n\t\t@(posedge clk) data <= 12;\n\t\trepeat(100) @(posedge clk);\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_q;\n\t\tint errortime_q;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic load;\n\tlogic [511:0] data;\n\tlogic [511:0] q_ref;\n\tlogic [511:0] q_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,load,data,q_ref,q_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.load,\n\t\t.data );\n\treference_module good1 (\n\t\t.clk,\n\t\t.load,\n\t\t.data,\n\t\t.q(q_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.load,\n\t\t.data,\n\t\t.q(q_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"q\", stats1.errors_q, stats1.errortime_q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"q\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (q_ref !== ( q_ref ^ q_dut ^ q_ref ))\n\t\tbegin if (stats1.errors_q == 0) stats1.errortime_q = $time;\n\t\t\tstats1.errors_q = stats1.errors_q+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "fsm3s", "task_number": 28, "description": "The following is the state transition table for a Moore state machine with one input, one output, and four states. Implement this state machine. Include a synchronous active high reset that resets the FSM to state A. \n// State | Next state in=0, Next state in=1 | Output\n// A | A, B | 0\n// B | C, B | 0\n// C | A, D | 0\n// D | C, B | 1", "header": "module top_module (\n\tinput clk,\n\tinput in,\n\tinput reset,\n\toutput out\n);\n", "module_code": "module top_module (\n\tinput clk,\n\tinput in,\n\tinput reset,\n\toutput out\n);\n\tparameter A=0, B=1, C=2, D=3;\n\treg [1:0] state;\n\treg [1:0] next;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tA: next = in ? B : A;\n\t\t\tB: next = in ? B : C;\n\t\t\tC: next = in ? D : A;\n\t\t\tD: next = in ? B : C;\n\t\tendcase\n    end\n    \n    always @(posedge clk) begin\n\t\tif (reset) state <= A;\n        else state <= next;\n\tend\n\t\t\n\tassign out = (state==D);\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput in,\n\tinput reset,\n\toutput out\n);\n\tparameter A=0, B=1, C=2, D=3;\n\treg [1:0] state;\n\treg [1:0] next;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tA: next = in ? B : A;\n\t\t\tB: next = in ? B : C;\n\t\t\tC: next = in ? D : A;\n\t\t\tD: next = in ? B : C;\n\t\tendcase\n    end\n    \n    always @(posedge clk) begin\n\t\tif (reset) state <= A;\n        else state <= next;\n\tend\n\t\t\n\tassign out = (state==D);\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic in,\n\toutput logic reset,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\tinput tb_match\n);\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\tinitial begin\n\t\treset <= 1;\n\t\tin <= 0;\n\t\t@(posedge clk) reset <= 0; in <= 1;\n\t\t@(posedge clk) in <= 0;\n\t\t@(posedge clk) in <= 1;\n\t\twavedrom_start();\n\t\t\t@(posedge clk) in <= 0;\n\t\t\t@(posedge clk) in <= 1;\n\t\t\t@(posedge clk);\n\t\t\t@(negedge clk) reset <= 1;\n\t\t\t@(posedge clk) reset <= 0;\n\t\t\t@(posedge clk) in <= 1;\n\t\t\t@(posedge clk) in <= 1;\n\t\t\t@(posedge clk) in <= 0;\n\t\t\t@(posedge clk) in <= 1;\n\t\t\t@(posedge clk) in <= 0;\n\t\t\t@(posedge clk) in <= 1;\n\t\t\t@(posedge clk) in <= 1;\n\t\t\t@(posedge clk) in <= 1;\n\t\t@(negedge clk);\n\t\twavedrom_stop();\n\t\trepeat(200) @(posedge clk, negedge clk) begin\n\t\t\tin <= $random;\n\t\t\treset <= !($random & 31);\n\t\tend\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic in;\n\tlogic reset;\n\tlogic out_ref;\n\tlogic out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,in,reset,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in,\n\t\t.reset );\n\treference_module good1 (\n\t\t.clk,\n\t\t.in,\n\t\t.reset,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.in,\n\t\t.reset,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "circuit5", "task_number": 29, "description": "This is a combinational circuit. Read the simulation waveforms to determine what the circuit does, then implement it.\n\n// time            a               b               c               d               e               q               \n// 0ns             x               x               x               x               x               x               \n// 5ns             x               x               x               x               x               x               \n// 10ns            x               x               x               x               x               x               \n// 15ns            a               b               0               d               e               b               \n// 20ns            a               b               1               d               e               e               \n// 25ns            a               b               2               d               e               a               \n// 30ns            a               b               3               d               e               d               \n// 35ns            a               b               4               d               e               f               \n// 40ns            a               b               5               d               e               f               \n// 45ns            a               b               6               d               e               f               \n// 50ns            a               b               7               d               e               f               \n// 55ns            a               b               8               d               e               f               \n// 60ns            a               b               9               d               e               f               \n// 65ns            a               b               a               d               e               f               \n// 70ns            a               b               b               d               e               f               \n// 75ns            a               b               c               d               e               f               \n// 80ns            a               b               d               d               e               f               \n// 85ns            a               b               e               d               e               f               \n// 90ns            a               b               f               d               e               f               ", "header": "module top_module (\n\tinput [3:0] a, \n\tinput [3:0] b, \n\tinput [3:0] c, \n\tinput [3:0] d,\n\tinput [3:0] e,\n\toutput reg [3:0] q\n);\n", "module_code": "module top_module (\n\tinput [3:0] a, \n\tinput [3:0] b, \n\tinput [3:0] c, \n\tinput [3:0] d,\n\tinput [3:0] e,\n\toutput reg [3:0] q\n);\n\n\talways @(*) \n\t\tcase (c)\n\t\t\t0: q = b;\n\t\t\t1: q = e;\n\t\t\t2: q = a;\n\t\t\t3: q = d;\n\t\t\tdefault: q = 4'hf;\n\t\tendcase\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [3:0] a, \n\tinput [3:0] b, \n\tinput [3:0] c, \n\tinput [3:0] d,\n\tinput [3:0] e,\n\toutput reg [3:0] q\n);\n\n\talways @(*) \n\t\tcase (c)\n\t\t\t0: q = b;\n\t\t\t1: q = e;\n\t\t\t2: q = a;\n\t\t\t3: q = d;\n\t\t\tdefault: q = 4'hf;\n\t\tendcase\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic [3:0] a,b,c,d,e,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\t@(negedge clk) wavedrom_start(\"Unknown circuit\");\n\t\t\t@(posedge clk) {a,b,c,d,e} <= {20'hab0de};\n\t\t\trepeat(18) @(posedge clk, negedge clk) c <= c + 1;\n\t\twavedrom_stop();\n\n\t\t@(negedge clk) wavedrom_start(\"Unknown circuit\");\n\t\t\t@(posedge clk) {a,b,c,d,e} <= {20'h12034};\n\t\t\trepeat(8) @(posedge clk, negedge clk) c <= c + 1;\n\t\t\t@(posedge clk) {a,b,c,d,e} <= {20'h56078};\n\t\t\trepeat(8) @(posedge clk, negedge clk) c <= c + 1;\n\t\twavedrom_stop();\n\t\t\n\t\trepeat(100) @(posedge clk, negedge clk)\n\t\t\t{a,b,c,d,e} <= $urandom;\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_q;\n\t\tint errortime_q;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [3:0] a;\n\tlogic [3:0] b;\n\tlogic [3:0] c;\n\tlogic [3:0] d;\n\tlogic [3:0] e;\n\tlogic [3:0] q_ref;\n\tlogic [3:0] q_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,a,b,c,d,e,q_ref,q_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d,\n\t\t.e );\n\treference_module good1 (\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d,\n\t\t.e,\n\t\t.q(q_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d,\n\t\t.e,\n\t\t.q(q_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"q\", stats1.errors_q, stats1.errortime_q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"q\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (q_ref !== ( q_ref ^ q_dut ^ q_ref ))\n\t\tbegin if (stats1.errors_q == 0) stats1.errortime_q = $time;\n\t\t\tstats1.errors_q = stats1.errors_q+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "bugs_mux2", "task_number": 30, "description": "Find the bug and fix this 8-bit wide 2-to-1 mux.\n\n// module top_module (\n//     input sel,\n//     input [7:0] a,\n//     input [7:0] b,\n//     output out  );\n\n//     assign out = (~sel & a) | (sel & b);\n\n// endmodule", "header": "module top_module (\n\tinput sel,\n\tinput [7:0] a,\n\tinput [7:0] b,\n\toutput reg [7:0] out\n);\n", "module_code": "module top_module (\n\tinput sel,\n\tinput [7:0] a,\n\tinput [7:0] b,\n\toutput reg [7:0] out\n);\n\n\t// assign out = (~sel & a) | (sel & b);\n    assign out = sel ? a : b;\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput sel,\n\tinput [7:0] a,\n\tinput [7:0] b,\n\toutput reg [7:0] out\n);\n\n\t// assign out = (~sel & a) | (sel & b);\n    assign out = sel ? a : b;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic sel,\n\toutput logic [7:0] a, b,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\t{a, b, sel} <= '0;\n\t\t@(negedge clk) wavedrom_start(\"\");\n\t\t\t@(posedge clk, negedge clk) {a,b,sel} <= {8'haa, 8'hbb, 1'b0};\n\t\t\t@(posedge clk, negedge clk) {a,b,sel} <= {8'haa, 8'hbb, 1'b0};\n\t\t\t@(posedge clk, negedge clk) {a,b,sel} <= {8'haa, 8'hbb, 1'b1};\n\t\t\t@(posedge clk, negedge clk) {a,b,sel} <= {8'haa, 8'hbb, 1'b0};\n\t\t\t@(posedge clk, negedge clk) {a,b,sel} <= {8'haa, 8'hbb, 1'b1};\n\t\t\t@(posedge clk, negedge clk) {a,b,sel} <= {8'haa, 8'hbb, 1'b1};\n\t\t\t\n\t\t\t@(posedge clk, negedge clk) {a, b} <= {8'hff, 8'h00}; sel <= 1'b0;\n\t\t\t@(posedge clk, negedge clk) sel <= 1'b0;\n\t\t\t@(posedge clk, negedge clk) sel <= 1'b1;\n\t\t\t@(posedge clk, negedge clk) sel <= 1'b0;\n\t\t\t@(posedge clk, negedge clk) sel <= 1'b1;\n\t\t\t@(posedge clk, negedge clk) sel <= 1'b1;\n\t\twavedrom_stop();\n\t\t\n\t\trepeat(100) @(posedge clk, negedge clk)\n\t\t\t{a,b,sel} <= $urandom;\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic sel;\n\tlogic [7:0] a;\n\tlogic [7:0] b;\n\tlogic [7:0] out_ref;\n\tlogic [7:0] out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,sel,a,b,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.sel,\n\t\t.a,\n\t\t.b );\n\treference_module good1 (\n\t\t.sel,\n\t\t.a,\n\t\t.b,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.sel,\n\t\t.a,\n\t\t.b,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "mt2015_muxdff", "task_number": 31, "description": "Consider this Verilog module \"full_module\":\n\n// module full_module (\n//     input [2:0] r,\n//     input L,\n//     input clk,\n//     output reg [2:0] q\n);\n\n// always @(posedge clk) begin\n//     if (L) begin\n//         q <= r;\n//     end else begin\n//         q <= {q[1] ^ q[2], q[0], q[2]};\n//     end\n// end\n\n// endmodule\n\n// You want to create a hierarchical Verilog design where a flipflop and 2-1 multiplexer are in a submodule, and that submodule is instantiated three times in this code. Create the submodule called \"top_module\".\n", "header": "module top_module(\n\tinput clk,\n\tinput L,\n\tinput q_in,\n\tinput r_in,\n\toutput reg Q);\n", "module_code": "module top_module(\n\tinput clk,\n\tinput L,\n\tinput q_in,\n\tinput r_in,\n\toutput reg Q);\n\n\tinitial Q=0;\n\talways @(posedge clk)\n\t\tQ <= L ? r_in : q_in;\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\n/*\n\tMidterm 2015 Question 5a. Build a flip-flop with a 2-to-1 mux before it.\n*/\nmodule reference_module(\n\tinput clk,\n\tinput L,\n\tinput q_in,\n\tinput r_in,\n\toutput reg Q);\n\n\tinitial Q=0;\n\talways @(posedge clk)\n\t\tQ <= L ? r_in : q_in;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic L,\n\toutput logic r_in,\n\toutput logic q_in\n);\n\n\talways @(posedge clk, negedge clk)\n\t\t{L, r_in, q_in} <= $random % 8;\n\t\n\tinitial begin\n\t\trepeat(100) @(posedge clk);\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_Q;\n\t\tint errortime_Q;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic L;\n\tlogic q_in;\n\tlogic r_in;\n\tlogic Q_ref;\n\tlogic Q_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,L,q_in,r_in,Q_ref,Q_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.L,\n\t\t.q_in,\n\t\t.r_in );\n\treference_module good1 (\n\t\t.clk,\n\t\t.L,\n\t\t.q_in,\n\t\t.r_in,\n\t\t.Q(Q_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.L,\n\t\t.q_in,\n\t\t.r_in,\n\t\t.Q(Q_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_Q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"Q\", stats1.errors_Q, stats1.errortime_Q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"Q\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { Q_ref } === ( { Q_ref } ^ { Q_dut } ^ { Q_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (Q_ref !== ( Q_ref ^ Q_dut ^ Q_ref ))\n\t\tbegin if (stats1.errors_Q == 0) stats1.errortime_Q = $time;\n\t\t\tstats1.errors_Q = stats1.errors_Q+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "edgecapture", "task_number": 32, "description": "For each bit in a 32-bit vector, capture when the input signal changes from 1 in one clock cycle to 0 the next. \"Capture\" means that the output will remain 1 until the register is reset (active high synchronous reset).", "header": "module top_module(\n\tinput clk,\n\tinput reset,\n\tinput [31:0] in,\n\toutput reg [31:0] out);\n", "module_code": "module top_module(\n\tinput clk,\n\tinput reset,\n\tinput [31:0] in,\n\toutput reg [31:0] out);\n\t\n\treg [31:0] d_last;\t\n\t\t\t\n\talways @(posedge clk) begin\n\t\td_last <= in;\n\t\tif (reset)\n\t\t\tout <= '0;\n\t\telse\n\t\t\tout <= out | (~in & d_last);\n\tend\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput clk,\n\tinput reset,\n\tinput [31:0] in,\n\toutput reg [31:0] out);\n\t\n\treg [31:0] d_last;\t\n\t\t\t\n\talways @(posedge clk) begin\n\t\td_last <= in;\n\t\tif (reset)\n\t\t\tout <= '0;\n\t\telse\n\t\t\tout <= out | (~in & d_last);\n\tend\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\tinput tb_match,\n\toutput reg [31:0] in,\n\toutput reg reset,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\tinitial begin\n\t\tin <= 0;\n\t\treset <= 1;\n\t\t@(posedge clk);\n\t\treset <= 1;\n\t\tin = 0;\n\t\t@(negedge clk) wavedrom_start(\"Example\");\n\t\trepeat(1) @(posedge clk);\n\t\treset = 0;\n\t\t@(posedge clk) in = 32'h2;\n\t\trepeat(4) @(posedge clk);\n\t\tin = 32'he;\n\t\trepeat(2) @(posedge clk);\n\t\tin = 0;\n\t\t@(posedge clk) in = 32'h2;\n\t\trepeat(2) @(posedge clk);\n\t\treset = 1;\n\t\t@(posedge clk);\n\t\treset = 0; in = 0;\n\t\trepeat(3) @(posedge clk);\n\n\t\t@(negedge clk) wavedrom_stop();\n\n\n\t\t@(negedge clk) wavedrom_start(\"\");\n\t\trepeat(2) @(posedge clk);\n\t\tin <= 1;\n\t\trepeat(2) @(posedge clk);\n\t\tin <= 0;\n\t\trepeat(2) @(negedge clk);\n\t\tin <= 6;\n\t\trepeat(1) @(negedge clk);\n\t\tin <= 0;\t\t\n\t\trepeat(2) @(posedge clk);\n\t\tin <= 32'h10;\t\t\n\t\trepeat(2) @(posedge clk);\n\t\treset <= 1;\n\t\trepeat(1) @(posedge clk);\n\t\tin <= 32'h0;\n\t\trepeat(1) @(posedge clk);\n\t\treset <= 0;\n\t\trepeat(1) @(posedge clk);\n\t\treset <= 1;\n\t\tin <= 32'h20;\n\t\trepeat(1) @(posedge clk);\n\t\treset <= 0;\n\t\tin <= 32'h00;\n\t\n\t\trepeat(2) @(posedge clk);\n\n\t\t@(negedge clk) wavedrom_stop();\n\t\n\t\trepeat(200)\n\t\t\t@(posedge clk, negedge clk) begin\n\t\t\t\tin <= $random;\n\t\t\t\treset <= !($random & 15);\n\t\t\tend\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic reset;\n\tlogic [31:0] in;\n\tlogic [31:0] out_ref;\n\tlogic [31:0] out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,in,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.reset,\n\t\t.in );\n\treference_module good1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.in,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.in,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "dff8", "task_number": 33, "description": "Create 8 D flip-flops. All DFFs should be triggered by the positive edge of clk.", "header": "module top_module(\n\tinput clk,\n\tinput [7:0] d,\n\toutput reg [7:0] q);\n", "module_code": "module top_module(\n\tinput clk,\n\tinput [7:0] d,\n\toutput reg [7:0] q);\n\t\n\tinitial\n\t\tq = 8'h0;\n\t\t\n\talways @(posedge clk)\n\t\tq <= d;\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput clk,\n\tinput [7:0] d,\n\toutput reg [7:0] q);\n\t\n\tinitial\n\t\tq = 8'h0;\n\t\t\n\talways @(posedge clk)\n\t\tq <= d;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg [7:0] d,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\talways @(posedge clk, negedge clk)\n\t\td <= $random % 256;\n\t\n\tinitial begin\n\t\t@(posedge clk);\n\t\twavedrom_start(\"Positive-edge triggered DFF\");\n\t\trepeat(10) @(posedge clk);\n\t\twavedrom_stop();\n\t\t#100;\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_q;\n\t\tint errortime_q;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [7:0] d;\n\tlogic [7:0] q_ref;\n\tlogic [7:0] q_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,d,q_ref,q_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.d );\n\treference_module good1 (\n\t\t.clk,\n\t\t.d,\n\t\t.q(q_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.d,\n\t\t.q(q_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"q\", stats1.errors_q, stats1.errortime_q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"q\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (q_ref !== ( q_ref ^ q_dut ^ q_ref ))\n\t\tbegin if (stats1.errors_q == 0) stats1.errortime_q = $time;\n\t\t\tstats1.errors_q = stats1.errors_q+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "ece241_2014_q1c", "task_number": 34, "description": "Assume that you have two 8-bit 2's complement numbers, a[7:0] and b[7:0]. These numbers are added to produce s[7:0]. Also compute whether a (signed) overflow has occurred.", "header": "module top_module (\n\tinput [7:0] a,\n\tinput [7:0] b,\n\toutput [7:0] s,\n\toutput overflow\n);\n", "module_code": "module top_module (\n\tinput [7:0] a,\n\tinput [7:0] b,\n\toutput [7:0] s,\n\toutput overflow\n);\n\t\n\twire [8:0] sum = a+b;\n\tassign s = sum[7:0];\n\tassign overflow = !(a[7]^b[7]) && (a[7] != s[7]);\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [7:0] a,\n\tinput [7:0] b,\n\toutput [7:0] s,\n\toutput overflow\n);\n\t\n\twire [8:0] sum = a+b;\n\tassign s = sum[7:0];\n\tassign overflow = !(a[7]^b[7]) && (a[7] != s[7]);\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic [7:0] a, b,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\t{a, b} <= 0;\n\t\t@(negedge clk) wavedrom_start();\n\t\t\t@(posedge clk) {a, b} <= 16'h0;\n\t\t\t@(posedge clk) {a, b} <= 16'h0070;\n\t\t\t@(posedge clk) {a, b} <= 16'h7070;\n\t\t\t@(posedge clk) {a, b} <= 16'h7090;\n\t\t\t@(posedge clk) {a, b} <= 16'h9070;\n\t\t\t@(posedge clk) {a, b} <= 16'h9090;\n\t\t\t@(posedge clk) {a, b} <= 16'h90ff;\n\t\t@(negedge clk) wavedrom_stop();\n\t\trepeat(100) @(posedge clk, negedge clk)\n\t\t\t{a,b} <= $random;\n\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_s;\n\t\tint errortime_s;\n\t\tint errors_overflow;\n\t\tint errortime_overflow;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [7:0] a;\n\tlogic [7:0] b;\n\tlogic [7:0] s_ref;\n\tlogic [7:0] s_dut;\n\tlogic overflow_ref;\n\tlogic overflow_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,a,b,s_ref,s_dut,overflow_ref,overflow_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.a,\n\t\t.b );\n\treference_module good1 (\n\t\t.a,\n\t\t.b,\n\t\t.s(s_ref),\n\t\t.overflow(overflow_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.a,\n\t\t.b,\n\t\t.s(s_dut),\n\t\t.overflow(overflow_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_s) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"s\", stats1.errors_s, stats1.errortime_s);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"s\");\n\t\tif (stats1.errors_overflow) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"overflow\", stats1.errors_overflow, stats1.errortime_overflow);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"overflow\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { s_ref, overflow_ref } === ( { s_ref, overflow_ref } ^ { s_dut, overflow_dut } ^ { s_ref, overflow_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (s_ref !== ( s_ref ^ s_dut ^ s_ref ))\n\t\tbegin if (stats1.errors_s == 0) stats1.errortime_s = $time;\n\t\t\tstats1.errors_s = stats1.errors_s+1'b1; end\n\t\tif (overflow_ref !== ( overflow_ref ^ overflow_dut ^ overflow_ref ))\n\t\tbegin if (stats1.errors_overflow == 0) stats1.errortime_overflow = $time;\n\t\t\tstats1.errors_overflow = stats1.errors_overflow+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "review2015_fsmonehot", "task_number": 35, "description": "Given the following Moore state machine with 3 input (d, done_counting, ack) and 3 outputs (shift_ena, counting, done). Unless otherwise stated in the diagram below, assume outputs are 0 and inputs are don't cares.\n\n// S () --d=0--> S\n// S () --d=1--> S1\n// S1 () --d=0--> S\n// S1 () --d=1--> S11\n// S11 () --d=0--> S110\n// S11 () --d=1--> S11\n// S110 () --d=0--> S\n// S110 () --d=1--> B0\n// B0 (shift_ena=1) -- (always go to next cycle) --> B1\n// B1 (shift_ena=1) -- (always go to next cycle) --> B2\n// B2 (shift_ena=1) -- (always go to next cycle) --> B3\n// B3 (shift_ena=1) -- (always go to next cycle) --> Count\n// Count (counting=1) --!(done_counting)--> Count\n// Count (counting=1) --(done_counting)--> Wait\n// Wait (done=1) --ack=0--> Wait\n// Wait (done=1) --ack=1--> S\n\n// At reset, the state machine starts in state \"S\". Derive next-state logic equations and output logic equations by inspection assuming the following one-hot encoding is used: (S, S1, S11, S110, B0, B1, B2, B3, Count, Wait) = (10'b0000000001, 10'b0000000010, 10'b0000000100, ... , 10'b1000000000)\n\n// Derive state transition and output logic equations by inspection assuming a one-hot encoding. Implement only the state transition logic and output logic (the combinational logic portion) for this state machine.\n\n// Write code that generates the following equations:\n\n// - B3_next -- next-state logic for state B3\n// - S_next\n// - S1_next\n// - Count_next\n// - Wait_next\n// - done -- output logic\n// - counting\n// - shift_ena\n", "header": "module top_module(\n    input d,\n    input done_counting,\n    input ack,\n    input [9:0] state,    // 10-bit one-hot current state\n    output B3_next,\n    output S_next,\n    output S1_next,\n    output Count_next,\n    output Wait_next,\n    output done,\n    output counting,\n    output shift_ena\n );\n", "module_code": "module top_module(\n    input d,\n    input done_counting,\n    input ack,\n    input [9:0] state,    // 10-bit one-hot current state\n    output B3_next,\n    output S_next,\n    output S1_next,\n    output Count_next,\n    output Wait_next,\n    output done,\n    output counting,\n    output shift_ena\n );\n \n\tparameter S=0, S1=1, S11=2, S110=3, B0=4, B1=5, B2=6, B3=7, Count=8, Wait=9;\n\n\tassign B3_next = state[B2];\n\tassign S_next = state[S]&~d | state[S1]&~d | state[S110]&~d | state[Wait]&ack;\n\tassign S1_next = state[S]&d;\n\tassign Count_next = state[B3] | state[Count]&~done_counting;\n\tassign Wait_next = state[Count]&done_counting | state[Wait]&~ack;\n\n\tassign done = state[Wait];\n\tassign counting = state[Count];\n\tassign shift_ena = |state[B3:B0];\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n    input d,\n    input done_counting,\n    input ack,\n    input [9:0] state,    // 10-bit one-hot current state\n    output B3_next,\n    output S_next,\n    output S1_next,\n    output Count_next,\n    output Wait_next,\n    output done,\n    output counting,\n    output shift_ena\n );\n \n\t parameter S=0, S1=1, S11=2, S110=3, B0=4, B1=5, B2=6, B3=7, Count=8, Wait=9;\n\n\tassign B3_next = state[B2];\n\tassign S_next = state[S]&~d | state[S1]&~d | state[S110]&~d | state[Wait]&ack;\n\tassign S1_next = state[S]&d;\n\tassign Count_next = state[B3] | state[Count]&~done_counting;\n\tassign Wait_next = state[Count]&done_counting | state[Wait]&~ack;\n\n\tassign done = state[Wait];\n\tassign counting = state[Count];\n\tassign shift_ena = |state[B3:B0];\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg d, done_counting, ack,\n\toutput reg [9:0] state,\n\tinput tb_match\n);\n\tbit failed = 0;\n\tbit fail_onehot = 0;\n\t\n\talways @(posedge clk, negedge clk)\n\t\tif (!tb_match) \n\t\t\tfailed <= 1;\n\t\n\tinitial begin\n\t\t{d, done_counting, ack} <= 3'h0;\n\t\tstate <= 10'h0;\n\t\t\n\t\trepeat(300) @(posedge clk, negedge clk) begin\n\t\t\t{d, done_counting, ack} = $random;\n\t\t\tstate <= 1<< ($unsigned($random) % 10);\n\t\tend\n\n\t\t@(posedge clk) fail_onehot <= failed;\n\n\t\trepeat(3000) @(posedge clk, negedge clk) begin\n\t\t\t{d, done_counting, ack} = $random;\n\t\t\tstate <= $random;\n\t\tend\n\n\t\t\n\t\t@(posedge clk);\n\t\tif (!fail_onehot && failed) begin\n\t\t\t$display (\"Hint: Your circuit passed when given only one-hot inputs, but not with random inputs.\");\n\t\t\t$display (\"Hint: Are you doing something more complicated than deriving state transition equations by inspection?\\n\");\n\t\tend\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_B3_next;\n\t\tint errortime_B3_next;\n\t\tint errors_S_next;\n\t\tint errortime_S_next;\n\t\tint errors_S1_next;\n\t\tint errortime_S1_next;\n\t\tint errors_Count_next;\n\t\tint errortime_Count_next;\n\t\tint errors_Wait_next;\n\t\tint errortime_Wait_next;\n\t\tint errors_done;\n\t\tint errortime_done;\n\t\tint errors_counting;\n\t\tint errortime_counting;\n\t\tint errors_shift_ena;\n\t\tint errortime_shift_ena;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic d;\n\tlogic done_counting;\n\tlogic ack;\n\tlogic [9:0] state;\n\tlogic B3_next_ref;\n\tlogic B3_next_dut;\n\tlogic S_next_ref;\n\tlogic S_next_dut;\n\tlogic S1_next_ref;\n\tlogic S1_next_dut;\n\tlogic Count_next_ref;\n\tlogic Count_next_dut;\n\tlogic Wait_next_ref;\n\tlogic Wait_next_dut;\n\tlogic done_ref;\n\tlogic done_dut;\n\tlogic counting_ref;\n\tlogic counting_dut;\n\tlogic shift_ena_ref;\n\tlogic shift_ena_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,d,done_counting,ack,state,B3_next_ref,B3_next_dut,S_next_ref,S_next_dut,S1_next_ref,S1_next_dut,Count_next_ref,Count_next_dut,Wait_next_ref,Wait_next_dut,done_ref,done_dut,counting_ref,counting_dut,shift_ena_ref,shift_ena_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.d,\n\t\t.done_counting,\n\t\t.ack,\n\t\t.state );\n\treference_module good1 (\n\t\t.d,\n\t\t.done_counting,\n\t\t.ack,\n\t\t.state,\n\t\t.B3_next(B3_next_ref),\n\t\t.S_next(S_next_ref),\n\t\t.S1_next(S1_next_ref),\n\t\t.Count_next(Count_next_ref),\n\t\t.Wait_next(Wait_next_ref),\n\t\t.done(done_ref),\n\t\t.counting(counting_ref),\n\t\t.shift_ena(shift_ena_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.d,\n\t\t.done_counting,\n\t\t.ack,\n\t\t.state,\n\t\t.B3_next(B3_next_dut),\n\t\t.S_next(S_next_dut),\n\t\t.S1_next(S1_next_dut),\n\t\t.Count_next(Count_next_dut),\n\t\t.Wait_next(Wait_next_dut),\n\t\t.done(done_dut),\n\t\t.counting(counting_dut),\n\t\t.shift_ena(shift_ena_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_B3_next) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"B3_next\", stats1.errors_B3_next, stats1.errortime_B3_next);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"B3_next\");\n\t\tif (stats1.errors_S_next) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"S_next\", stats1.errors_S_next, stats1.errortime_S_next);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"S_next\");\n\t\tif (stats1.errors_S1_next) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"S1_next\", stats1.errors_S1_next, stats1.errortime_S1_next);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"S1_next\");\n\t\tif (stats1.errors_Count_next) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"Count_next\", stats1.errors_Count_next, stats1.errortime_Count_next);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"Count_next\");\n\t\tif (stats1.errors_Wait_next) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"Wait_next\", stats1.errors_Wait_next, stats1.errortime_Wait_next);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"Wait_next\");\n\t\tif (stats1.errors_done) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"done\", stats1.errors_done, stats1.errortime_done);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"done\");\n\t\tif (stats1.errors_counting) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"counting\", stats1.errors_counting, stats1.errortime_counting);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"counting\");\n\t\tif (stats1.errors_shift_ena) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"shift_ena\", stats1.errors_shift_ena, stats1.errortime_shift_ena);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"shift_ena\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { B3_next_ref, S_next_ref, S1_next_ref, Count_next_ref, Wait_next_ref, done_ref, counting_ref, shift_ena_ref } === ( { B3_next_ref, S_next_ref, S1_next_ref, Count_next_ref, Wait_next_ref, done_ref, counting_ref, shift_ena_ref } ^ { B3_next_dut, S_next_dut, S1_next_dut, Count_next_dut, Wait_next_dut, done_dut, counting_dut, shift_ena_dut } ^ { B3_next_ref, S_next_ref, S1_next_ref, Count_next_ref, Wait_next_ref, done_ref, counting_ref, shift_ena_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (B3_next_ref !== ( B3_next_ref ^ B3_next_dut ^ B3_next_ref ))\n\t\tbegin if (stats1.errors_B3_next == 0) stats1.errortime_B3_next = $time;\n\t\t\tstats1.errors_B3_next = stats1.errors_B3_next+1'b1; end\n\t\tif (S_next_ref !== ( S_next_ref ^ S_next_dut ^ S_next_ref ))\n\t\tbegin if (stats1.errors_S_next == 0) stats1.errortime_S_next = $time;\n\t\t\tstats1.errors_S_next = stats1.errors_S_next+1'b1; end\n\t\tif (S1_next_ref !== ( S1_next_ref ^ S1_next_dut ^ S1_next_ref ))\n\t\tbegin if (stats1.errors_S1_next == 0) stats1.errortime_S1_next = $time;\n\t\t\tstats1.errors_S1_next = stats1.errors_S1_next+1'b1; end\n\t\tif (Count_next_ref !== ( Count_next_ref ^ Count_next_dut ^ Count_next_ref ))\n\t\tbegin if (stats1.errors_Count_next == 0) stats1.errortime_Count_next = $time;\n\t\t\tstats1.errors_Count_next = stats1.errors_Count_next+1'b1; end\n\t\tif (Wait_next_ref !== ( Wait_next_ref ^ Wait_next_dut ^ Wait_next_ref ))\n\t\tbegin if (stats1.errors_Wait_next == 0) stats1.errortime_Wait_next = $time;\n\t\t\tstats1.errors_Wait_next = stats1.errors_Wait_next+1'b1; end\n\t\tif (done_ref !== ( done_ref ^ done_dut ^ done_ref ))\n\t\tbegin if (stats1.errors_done == 0) stats1.errortime_done = $time;\n\t\t\tstats1.errors_done = stats1.errors_done+1'b1; end\n\t\tif (counting_ref !== ( counting_ref ^ counting_dut ^ counting_ref ))\n\t\tbegin if (stats1.errors_counting == 0) stats1.errortime_counting = $time;\n\t\t\tstats1.errors_counting = stats1.errors_counting+1'b1; end\n\t\tif (shift_ena_ref !== ( shift_ena_ref ^ shift_ena_dut ^ shift_ena_ref ))\n\t\tbegin if (stats1.errors_shift_ena == 0) stats1.errortime_shift_ena = $time;\n\t\t\tstats1.errors_shift_ena = stats1.errors_shift_ena+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "counter_2bc", "task_number": 36, "description": "Build a two-bit saturating counter. The counter increments (up to a maximum of 3) when train_valid = 1 and train_taken = 1. It decrements (down to a minimum of 0) when train_valid = 1 and train_taken = 0. When not training (train_valid = 0), the counter keeps its value unchanged. areset is a positive edge triggered asynchronous reset that resets the counter to weakly not-taken (2'b01). Output state[1:0] is the two-bit counter value.", "header": "module top_module(\n    input clk,\n    input areset,\n    input train_valid,\n    input train_taken,\n    output logic [1:0] state\n);\n", "module_code": "module top_module(\n    input clk,\n    input areset,\n    input train_valid,\n    input train_taken,\n    output logic [1:0] state\n);\n    always @(posedge clk, posedge areset) begin\n        if (areset)\n            state <= 1;\n        else if (train_valid) begin\n            if(state < 3 && train_taken)\n                state <= state + 1;\n            else if(state > 0 && !train_taken)\n                state <= state - 1;\n        end\n    end\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n    input clk,\n    input areset,\n    input train_valid,\n    input train_taken,\n    output logic [1:0] state\n);\n    always @(posedge clk, posedge areset) begin\n        if (areset)\n            state <= 1;\n        else if (train_valid) begin\n            if(state < 3 && train_taken)\n                state <= state + 1;\n            else if(state > 0 && !train_taken)\n                state <= state - 1;\n        end\n    end\nendmodule\n\n\nmodule stimulus_gen(\n\tinput clk,\n\toutput logic areset,\n\toutput logic train_valid,\n\toutput train_taken,\n\n\tinput tb_match,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\toutput int wavedrom_hide_after_time\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\treg reset;\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\t\n\tassign areset = reset;\n\tlogic train_taken_r;\n\tassign train_taken = train_valid ? train_taken_r : 1'bx;\n\t\n\tinitial begin\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 1;\n\t\t@(posedge clk) reset <= 0;\n\t\ttrain_taken_r <= 1;\n\t\ttrain_valid <= 1;\n\t\n\t\twavedrom_start(\"Asynchronous reset\");\n\t\t\treset_test(1); // Test for asynchronous reset\n\t\twavedrom_stop();\n\t\t@(posedge clk) reset <= 1;\n\t\ttrain_taken_r <= 1;\n\t\ttrain_valid <= 0;\n\t\t@(posedge clk) reset <= 0;\n\n\t\twavedrom_start(\"Count up, then down\");\n\t\ttrain_taken_r <= 1;\n\t\t\t@(posedge clk) train_valid <= 1;\n\t\t\t@(posedge clk) train_valid <= 0;\n\t\t\t@(posedge clk) train_valid <= 1;\n\t\t\t@(posedge clk) train_valid <= 1;\n\t\t\t@(posedge clk) train_valid <= 1;\n\t\t\t@(posedge clk) train_valid <= 0;\n\t\t\t@(posedge clk) train_valid <= 1;\n\t\ttrain_taken_r <= 0;\n\t\t\t@(posedge clk) train_valid <= 1;\n\t\t\t@(posedge clk) train_valid <= 0;\n\t\t\t@(posedge clk) train_valid <= 1;\n\t\t\t@(posedge clk) train_valid <= 1;\n\t\t\t@(posedge clk) train_valid <= 1;\n\t\t\t@(posedge clk) train_valid <= 0;\n\t\t\t@(posedge clk) train_valid <= 1;\t\t\n\t\twavedrom_stop();\n\n\t\trepeat(1000) @(posedge clk,negedge clk) \n\t\t\t{train_valid, train_taken_r} <= {$urandom} ;\n\n\t\t#1 $finish;\n\tend\n\t\n\t\nendmodule\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_state;\n\t\tint errortime_state;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic areset;\n\tlogic train_valid;\n\tlogic train_taken;\n\tlogic [1:0] state_ref;\n\tlogic [1:0] state_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,areset,train_valid,train_taken,state_ref,state_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.areset,\n\t\t.train_valid,\n\t\t.train_taken );\n\treference_module good1 (\n\t\t.clk,\n\t\t.areset,\n\t\t.train_valid,\n\t\t.train_taken,\n\t\t.state(state_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.areset,\n\t\t.train_valid,\n\t\t.train_taken,\n\t\t.state(state_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_state) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"state\", stats1.errors_state, stats1.errortime_state);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"state\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { state_ref } === ( { state_ref } ^ { state_dut } ^ { state_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (state_ref !== ( state_ref ^ state_dut ^ state_ref ))\n\t\tbegin if (stats1.errors_state == 0) stats1.errortime_state = $time;\n\t\t\tstats1.errors_state = stats1.errors_state+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "always_casez", "task_number": 37, "description": "Build a priority encoder for 8-bit inputs. Given an 8-bit vector, the output should report the first (least significant) bit in the vector that is 1. Report zero if the input vector has no bits that are high. For example, the input 8'b10010000 should output 3'd4, because bit[4] is first bit that is high.", "header": "module top_module (\n\tinput [7:0] in,\n\toutput reg [2:0] pos\n);\n", "module_code": "module top_module (\n\tinput [7:0] in,\n\toutput reg [2:0] pos\n);\n\n\talways @(*) begin\n\t\tcasez (in)\n\t\t\tdefault : pos = 2'h0;\n\t\t\t8'bzzzzzzz1: pos = 3'h0;\n\t\t\t8'bzzzzzz1z: pos = 3'h1;\n\t\t\t8'bzzzzz1zz: pos = 3'h2;\n\t\t\t8'bzzzz1zzz: pos = 3'h3;\n\t\t\t8'bzzz1zzzz: pos = 3'h4;\n\t\t\t8'bzz1zzzzz: pos = 3'h5;\n\t\t\t8'bz1zzzzzz: pos = 3'h6;\n\t\t\t8'b1zzzzzzz: pos = 3'h7;\n\t\tendcase\n\tend\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [7:0] in,\n\toutput reg [2:0] pos\n);\n\n\talways @(*) begin\n\t\tcasez (in)\n\t\t\tdefault : pos = 2'h0;\n\t\t\t8'bzzzzzzz1: pos = 3'h0;\n\t\t\t8'bzzzzzz1z: pos = 3'h1;\n\t\t\t8'bzzzzz1zz: pos = 3'h2;\n\t\t\t8'bzzzz1zzz: pos = 3'h3;\n\t\t\t8'bzzz1zzzz: pos = 3'h4;\n\t\t\t8'bzz1zzzzz: pos = 3'h5;\n\t\t\t8'bz1zzzzzz: pos = 3'h6;\n\t\t\t8'b1zzzzzzz: pos = 3'h7;\n\t\tendcase\n\tend\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic [7:0] in, \n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\t@(negedge clk) wavedrom_start(\"Priority encoder\");\n\t\t\t@(posedge clk) in <= 8'h1;\n\t\t\trepeat(8) @(posedge clk) in <= in << 1;\n\t\t\tin <= 8'h10;\n\t\t\trepeat(8) @(posedge clk) in <= in + 1;\n\t\t@(negedge clk) wavedrom_stop();\n\n\t\trepeat(50) @(posedge clk, negedge clk) begin\n\t\t\tin <= $urandom;\n\t\tend\n\t\trepeat(260) @(posedge clk, negedge clk) begin\n\t\t\tin <= in + 1;\n\t\tend\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_pos;\n\t\tint errortime_pos;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [7:0] in;\n\tlogic [2:0] pos_ref;\n\tlogic [2:0] pos_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,in,pos_ref,pos_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in );\n\treference_module good1 (\n\t\t.in,\n\t\t.pos(pos_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.in,\n\t\t.pos(pos_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_pos) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"pos\", stats1.errors_pos, stats1.errortime_pos);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"pos\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { pos_ref } === ( { pos_ref } ^ { pos_dut } ^ { pos_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (pos_ref !== ( pos_ref ^ pos_dut ^ pos_ref ))\n\t\tbegin if (stats1.errors_pos == 0) stats1.errortime_pos = $time;\n\t\t\tstats1.errors_pos = stats1.errors_pos+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "always_nolatches", "task_number": 38, "description": "Suppose you're building a circuit to process scancodes from a PS/2 keyboard for a game. Given the last two bytes of scancodes received, you need to indicate whether one of the arrow keys on the keyboard have been pressed. This involves a fairly simple mapping, which can be implemented as a case statement (or if-elseif) with four cases.\n// Scancode[15:0] | Arrow key\n// 16'he06b | left arrow\n// 16'he072 | down arrow\n// 16'he074 | right arrow\n// 16'he075 | up arrow\n// Anything else | none\n// Your circuit has one 16-bit input, and four outputs. Build this circuit that recognizes these four scancodes and asserts the correct output.\n\n", "header": "module top_module (\n\tinput [15:0] scancode,\n\toutput reg left,\n\toutput reg down,\n\toutput reg right,\n\toutput reg up\n);\n", "module_code": "module top_module (\n\tinput [15:0] scancode,\n\toutput reg left,\n\toutput reg down,\n\toutput reg right,\n\toutput reg up\n);\n\n\talways @(*) begin\n\t\t{up, left, down, right} = 0;\n\t\tcase (scancode)\n\t\t\t16'he06b: left = 1;\n\t\t\t16'he072: down = 1;\n\t\t\t16'he074: right = 1;\n\t\t\t16'he075: up = 1;\n\t\tendcase\n\tend\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [15:0] scancode,\n\toutput reg left,\n\toutput reg down,\n\toutput reg right,\n\toutput reg up\n);\n\n\talways @(*) begin\n\t\t{up, left, down, right} = 0;\n\t\tcase (scancode)\n\t\t\t16'he06b: left = 1;\n\t\t\t16'he072: down = 1;\n\t\t\t16'he074: right = 1;\n\t\t\t16'he075: up = 1;\n\t\tendcase\n\tend\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic [15:0] scancode, \n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\t@(negedge clk) wavedrom_start(\"Recognize arrow keys\");\n\t\t\t@(posedge clk) scancode <= 16'h0;\n\t\t\t@(posedge clk) scancode <= 16'h1;\n\t\t\t@(posedge clk) scancode <= 16'he075;\n\t\t\t@(posedge clk) scancode <= 16'he06b;\n\t\t\t@(posedge clk) scancode <= 16'he06c;\n\t\t\t@(posedge clk) scancode <= 16'he072;\n\t\t\t@(posedge clk) scancode <= 16'he074;\n\t\t\t@(posedge clk) scancode <= 16'he076;\n\t\t\t@(posedge clk) scancode <= 16'hffff;\n\t\t@(negedge clk) wavedrom_stop();\n\n\t\trepeat(30000) @(posedge clk, negedge clk) begin\n\t\t\tscancode <= $urandom;\n\t\tend\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_left;\n\t\tint errortime_left;\n\t\tint errors_down;\n\t\tint errortime_down;\n\t\tint errors_right;\n\t\tint errortime_right;\n\t\tint errors_up;\n\t\tint errortime_up;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [15:0] scancode;\n\tlogic left_ref;\n\tlogic left_dut;\n\tlogic down_ref;\n\tlogic down_dut;\n\tlogic right_ref;\n\tlogic right_dut;\n\tlogic up_ref;\n\tlogic up_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,scancode,left_ref,left_dut,down_ref,down_dut,right_ref,right_dut,up_ref,up_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.scancode );\n\treference_module good1 (\n\t\t.scancode,\n\t\t.left(left_ref),\n\t\t.down(down_ref),\n\t\t.right(right_ref),\n\t\t.up(up_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.scancode,\n\t\t.left(left_dut),\n\t\t.down(down_dut),\n\t\t.right(right_dut),\n\t\t.up(up_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_left) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"left\", stats1.errors_left, stats1.errortime_left);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"left\");\n\t\tif (stats1.errors_down) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"down\", stats1.errors_down, stats1.errortime_down);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"down\");\n\t\tif (stats1.errors_right) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"right\", stats1.errors_right, stats1.errortime_right);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"right\");\n\t\tif (stats1.errors_up) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"up\", stats1.errors_up, stats1.errortime_up);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"up\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { left_ref, down_ref, right_ref, up_ref } === ( { left_ref, down_ref, right_ref, up_ref } ^ { left_dut, down_dut, right_dut, up_dut } ^ { left_ref, down_ref, right_ref, up_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (left_ref !== ( left_ref ^ left_dut ^ left_ref ))\n\t\tbegin if (stats1.errors_left == 0) stats1.errortime_left = $time;\n\t\t\tstats1.errors_left = stats1.errors_left+1'b1; end\n\t\tif (down_ref !== ( down_ref ^ down_dut ^ down_ref ))\n\t\tbegin if (stats1.errors_down == 0) stats1.errortime_down = $time;\n\t\t\tstats1.errors_down = stats1.errors_down+1'b1; end\n\t\tif (right_ref !== ( right_ref ^ right_dut ^ right_ref ))\n\t\tbegin if (stats1.errors_right == 0) stats1.errortime_right = $time;\n\t\t\tstats1.errors_right = stats1.errors_right+1'b1; end\n\t\tif (up_ref !== ( up_ref ^ up_dut ^ up_ref ))\n\t\tbegin if (stats1.errors_up == 0) stats1.errortime_up = $time;\n\t\t\tstats1.errors_up = stats1.errors_up+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "m2014_q4j", "task_number": 39, "description": "Implement a 4-bit adder with full adders. The output sum should include the overflow bit.", "header": "module top_module (\n\tinput [3:0] x,\n\tinput [3:0] y,\n\toutput [4:0] sum\n);\n", "module_code": "module top_module (\n\tinput [3:0] x,\n\tinput [3:0] y,\n\toutput [4:0] sum\n);\n\n\tassign sum = x+y;\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [3:0] x,\n\tinput [3:0] y,\n\toutput [4:0] sum\n);\n\n\tassign sum = x+y;\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic [3:0] x,y\n);\n\n\tinitial begin\n\t\trepeat(100) @(posedge clk, negedge clk) begin\n\t\t\t{x,y} <= $random;\n\t\tend\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_sum;\n\t\tint errortime_sum;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [3:0] x;\n\tlogic [3:0] y;\n\tlogic [4:0] sum_ref;\n\tlogic [4:0] sum_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,x,y,sum_ref,sum_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.x,\n\t\t.y );\n\treference_module good1 (\n\t\t.x,\n\t\t.y,\n\t\t.sum(sum_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.x,\n\t\t.y,\n\t\t.sum(sum_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_sum) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"sum\", stats1.errors_sum, stats1.errortime_sum);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"sum\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { sum_ref } === ( { sum_ref } ^ { sum_dut } ^ { sum_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (sum_ref !== ( sum_ref ^ sum_dut ^ sum_ref ))\n\t\tbegin if (stats1.errors_sum == 0) stats1.errortime_sum = $time;\n\t\t\tstats1.errors_sum = stats1.errors_sum+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "history_shift", "task_number": 40, "description": "Build a 32-bit global history shift register, including support for rolling back state in response to a pipeline flush caused by a branch misprediction. When a branch prediction is made (predict_valid = 1), shift in predict_taken from the LSB side to update the branch history for the predicted branch. (predict_history[0] is the direction of the youngest branch.) When a branch misprediction occurs (train_mispredicted = 1), load the branch history register with the history after the completion of the mispredicted branch. This is the history before the mispredicted branch (train_history) concatenated with the actual result of the branch (train_taken). If both a prediction and misprediction occur at the same time, the misprediction takes precedence, because the pipeline flush will also flush out the branch that is currently making a prediction. predict_history is the value of the branch history register. areset is a positive edge triggered asynchronous reset that resets the history counter to zero.\n\n", "header": "module top_module\n(\n    input clk,\n    input areset,\n    input predict_valid,\n    input predict_taken,\n    output logic [31:0] predict_history,\n    \n    input train_mispredicted,\n    input train_taken,\n    input [31:0] train_history\n);\n", "module_code": "module top_module\n(\n    input clk,\n    input areset,\n    input predict_valid,\n    input predict_taken,\n    output logic [31:0] predict_history,\n    \n    input train_mispredicted,\n    input train_taken,\n    input [31:0] train_history\n);\n    always@(posedge clk, posedge areset)\n\t\tif (areset) begin\n\t\t\tpredict_history = 0;\n        end\telse begin\n\t\t\tif (train_mispredicted)\n\t\t\t\tpredict_history <= {train_history, train_taken};\n\t\t\telse if (predict_valid)\n\t\t\t\tpredict_history <= {predict_history, predict_taken};\n\t\tend\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module\n(\n    input clk,\n    input areset,\n    input predict_valid,\n    input predict_taken,\n    output logic [31:0] predict_history,\n    \n    input train_mispredicted,\n    input train_taken,\n    input [31:0] train_history\n);\n    always@(posedge clk, posedge areset)\n\t\tif (areset) begin\n\t\t\tpredict_history = 0;\n        end\telse begin\n\t\t\tif (train_mispredicted)\n\t\t\t\tpredict_history <= {train_history, train_taken};\n\t\t\telse if (predict_valid)\n\t\t\t\tpredict_history <= {predict_history, predict_taken};\n\t\tend\nendmodule\n\n\n\nmodule stimulus_gen\n(\n\tinput clk,\n\toutput logic areset,\n\t\n\toutput logic predict_valid,\n\toutput predict_taken,\n\t\n\toutput logic train_mispredicted,\n\toutput train_taken,\n\toutput [31:0] train_history,\n\n\tinput tb_match,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\toutput int wavedrom_hide_after_time\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\treg reset;\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\t\n\tassign areset = reset;\n\tlogic predict_taken_r;\n\tassign predict_taken = predict_valid ? predict_taken_r : 1'bx;\n\t\n\tlogic train_taken_r;\n\tlogic [31:0] train_history_r;\n\tassign train_taken = train_mispredicted ? train_taken_r : 1'bx;\n\tassign train_history = train_mispredicted ? train_history_r : 32'hx;\n\t\n\t\n\tinitial begin\n\t\t@(posedge clk) reset <= 1;\n\t\t@(posedge clk) reset <= 0;\n\t\tpredict_taken_r <= 1;\n\t\tpredict_valid <= 1;\n\t\ttrain_mispredicted <= 0;\n\t\ttrain_history_r <= 32'h5;\n\t\ttrain_taken_r <= 1;\n\t\n\t\twavedrom_start(\"Asynchronous reset\");\n\t\t\treset_test(1); // Test for asynchronous reset\n\t\twavedrom_stop();\n\t\t@(posedge clk) reset <= 1;\n\t\tpredict_valid <= 0;\n\n\t\twavedrom_start(\"Predictions: Shift in\");\n\t\trepeat(2) @(posedge clk) {predict_valid, predict_taken_r} <= {$urandom};\n\t\treset <= 0;\n\t\tpredict_valid <= 1;\n\t\trepeat(6) @(posedge clk) {predict_taken_r} <= {$urandom};\n\t\tpredict_valid <= 0;\n\t\trepeat(3) @(posedge clk) {predict_taken_r} <= {$urandom};\n\t\tpredict_valid <= 1;\n\t\ttrain_mispredicted <= 1;\n\t\t@(posedge clk) train_mispredicted <= 0;\n\t\trepeat(6) @(posedge clk) {predict_taken_r} <= {$urandom};\n\t\twavedrom_stop();\n\n\t\trepeat(2000) @(posedge clk,negedge clk) begin\n\t\t\t{predict_valid, predict_taken_r, train_taken_r} <= {$urandom};\n\t\t\ttrain_history_r <= $urandom;\n\t\t\ttrain_mispredicted <= !($urandom_range(0,31));\n\t\tend\n\n\t\t#1 $finish;\n\tend\n\t\n\t\nendmodule\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_predict_history;\n\t\tint errortime_predict_history;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic areset;\n\tlogic predict_valid;\n\tlogic predict_taken;\n\tlogic train_mispredicted;\n\tlogic train_taken;\n\tlogic [31:0] train_history;\n\tlogic [31:0] predict_history_ref;\n\tlogic [31:0] predict_history_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,areset,predict_valid,predict_taken,train_mispredicted,train_taken,train_history,predict_history_ref,predict_history_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.areset,\n\t\t.predict_valid,\n\t\t.predict_taken,\n\t\t.train_mispredicted,\n\t\t.train_taken,\n\t\t.train_history );\n\treference_module good1 (\n\t\t.clk,\n\t\t.areset,\n\t\t.predict_valid,\n\t\t.predict_taken,\n\t\t.train_mispredicted,\n\t\t.train_taken,\n\t\t.train_history,\n\t\t.predict_history(predict_history_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.areset,\n\t\t.predict_valid,\n\t\t.predict_taken,\n\t\t.train_mispredicted,\n\t\t.train_taken,\n\t\t.train_history,\n\t\t.predict_history(predict_history_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_predict_history) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"predict_history\", stats1.errors_predict_history, stats1.errortime_predict_history);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"predict_history\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { predict_history_ref } === ( { predict_history_ref } ^ { predict_history_dut } ^ { predict_history_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (predict_history_ref !== ( predict_history_ref ^ predict_history_dut ^ predict_history_ref ))\n\t\tbegin if (stats1.errors_predict_history == 0) stats1.errortime_predict_history = $time;\n\t\t\tstats1.errors_predict_history = stats1.errors_predict_history+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "wire_decl", "task_number": 41, "description": "Implement the following circuit. Create two intermediate wires (named anything you want) to connect the AND and OR gates together. Note that the wire that feeds the NOT gate is really wire `out`, so you do not necessarily need to declare a third wire here. Notice how wires are driven by exactly one source (output of a gate), but can feed multiple inputs.\n\n// The circuit is composed of two layers. The first layer, counting from the input, is two AND gates: one whose input is connected to a and b, and the second is connected to c and d. The second layer there is an OR gate to OR the two AND outputs, connected the output 'out'. Additionally, there is an inverted output 'out_n'.", "header": "module top_module (\n\tinput a,\n\tinput b,\n\tinput c,\n\tinput d,\n\toutput out,\n\toutput out_n );\n", "module_code": "module top_module (\n\tinput a,\n\tinput b,\n\tinput c,\n\tinput d,\n\toutput out,\n\toutput out_n );\n\t\n\twire w1, w2;\n\tassign w1 = a&b;\n\tassign w2 = c&d;\n\tassign out = w1|w2;\n\tassign out_n = ~out;\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\n// hdlbits_prop {len: 5}\nmodule reference_module (\n\tinput a,\n\tinput b,\n\tinput c,\n\tinput d,\n\toutput out,\n\toutput out_n );\n\t\n\twire w1, w2;\n\tassign w1 = a&b;\n\tassign w2 = c&d;\n\tassign out = w1|w2;\n\tassign out_n = ~out;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg a,b,c,d,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\t{a,b,c,d} = 4'h0;\n\t\t@(negedge clk);\n\t\twavedrom_start(\"Exhaustive test\");\n\t\trepeat(20) @(posedge clk, negedge clk)\n\t\t\t{d,c,b,a} <= {d,c,b,a} + 1'b1;\n\t\twavedrom_stop();\n\t\trepeat(100) @(posedge clk, negedge clk) begin\n\t\t\t{a,b,c,d} <= $random;\n\t\tend\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\t\tint errors_out_n;\n\t\tint errortime_out_n;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic a;\n\tlogic b;\n\tlogic c;\n\tlogic d;\n\tlogic out_ref;\n\tlogic out_dut;\n\tlogic out_n_ref;\n\tlogic out_n_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,a,b,c,d,out_ref,out_dut,out_n_ref,out_n_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d );\n\treference_module good1 (\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d,\n\t\t.out(out_ref),\n\t\t.out_n(out_n_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d,\n\t\t.out(out_dut),\n\t\t.out_n(out_n_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\t\tif (stats1.errors_out_n) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_n\", stats1.errors_out_n, stats1.errortime_out_n);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_n\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref, out_n_ref } === ( { out_ref, out_n_ref } ^ { out_dut, out_n_dut } ^ { out_ref, out_n_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\t\tif (out_n_ref !== ( out_n_ref ^ out_n_dut ^ out_n_ref ))\n\t\tbegin if (stats1.errors_out_n == 0) stats1.errortime_out_n = $time;\n\t\t\tstats1.errors_out_n = stats1.errors_out_n+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "dff", "task_number": 42, "description": "Create a single D flip-flop.", "header": "module top_module(\n\tinput clk,\n\tinput d,\n\toutput reg q);\n", "module_code": "module top_module(\n\tinput clk,\n\tinput d,\n\toutput reg q);\n\t\n\tinitial\n\t\tq = 1'hx;\n\t\t\n\talways @(posedge clk)\n\t\tq <= d;\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput clk,\n\tinput d,\n\toutput reg q);\n\t\n\tinitial\n\t\tq = 1'hx;\n\t\t\n\talways @(posedge clk)\n\t\tq <= d;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg d,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\talways @(posedge clk, negedge clk)\n\t\td <= $urandom;\n\t\n\tinitial begin\n\t\t@(posedge clk);\n\t\twavedrom_start(\"Positive-edge triggered DFF\");\n\t\trepeat(10) @(posedge clk);\n\t\twavedrom_stop();\n\t\t\n\t\trepeat(100) @(posedge clk, negedge clk);\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_q;\n\t\tint errortime_q;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic d;\n\tlogic q_ref;\n\tlogic q_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,d,q_ref,q_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.d );\n\treference_module good1 (\n\t\t.clk,\n\t\t.d,\n\t\t.q(q_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.d,\n\t\t.q(q_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"q\", stats1.errors_q, stats1.errortime_q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"q\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (q_ref !== ( q_ref ^ q_dut ^ q_ref ))\n\t\tbegin if (stats1.errors_q == 0) stats1.errortime_q = $time;\n\t\t\tstats1.errors_q = stats1.errors_q+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "ece241_2013_q12", "task_number": 43, "description": "In this question, you will design a circuit for an 8x1 memory, where writing to the memory is accomplished by shifting-in bits, and reading is \"random access\", as in a typical RAM. You will then use the circuit to realize a 3-input logic function. First, create an 8-bit shift register with 8 D-type flip-flops. Label the flip-flop outputs from Q[0]...Q[7]. The shift register input should be called S, which feeds the input of Q[0] (MSB is shifted in first). The enable input is synchronous active high and controls whether to shift. Extend the circuit to have 3 additional inputs A,B,C and an output Z. The circuit's behaviour should be as follows: when ABC is 000, Z=Q[0], when ABC is 001, Z=Q[1], and so on. Your circuit should contain ONLY the 8-bit shift register, and multiplexers. ", "header": "module top_module (\n\tinput clk,\n\tinput enable,\n\tinput S,\n\tinput A,\n\tinput B,\n\tinput C,\n\toutput reg Z\n);\n", "module_code": "module top_module (\n\tinput clk,\n\tinput enable,\n\tinput S,\n\tinput A,\n\tinput B,\n\tinput C,\n\toutput reg Z\n);\n\n\treg [7:0] q;\n\talways @(posedge clk) begin\n\t\tif (enable)\n\t\t\tq <= {q[6:0], S};\n\tend\n\t\n\tassign Z = q[ {A, B, C} ];\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput enable,\n\tinput S,\n\tinput A,\n\tinput B,\n\tinput C,\n\toutput reg Z\n);\n\n\treg [7:0] q;\n\talways @(posedge clk) begin\n\t\tif (enable)\n\t\t\tq <= {q[6:0], S};\n\tend\n\t\n\tassign Z = q[ {A, B, C} ];\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic S, enable,\n\toutput logic A, B, C,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\tenable <= 0;\n\t\t{A,B,C} <= 0;\n\t\tS <= 1'bx;\n\t\t@(negedge clk) wavedrom_start(\"A 3-input AND gate\");\n\t\t\t@(posedge clk);\n\t\t\t@(posedge clk) enable <= 1; S <= 1;\n\t\t\t@(posedge clk) S <= 0;\n\t\t\t@(posedge clk) S <= 0;\n\t\t\t@(posedge clk) S <= 0;\n\t\t\t@(posedge clk) S <= 0;\n\t\t\t@(posedge clk) S <= 0;\n\t\t\t@(posedge clk) S <= 0;\n\t\t\t@(posedge clk) S <= 0;\n\t\t\t@(posedge clk) enable <= 0; S <= 1'bx;\n\t\t\t{A,B,C} <= 5;\n\t\t\t@(posedge clk) {A,B,C} <= 6;\n\t\t\t@(posedge clk) {A,B,C} <= 7;\n\t\t\t@(posedge clk) {A,B,C} <= 0;\n\t\t\t@(posedge clk) {A,B,C} <= 1;\n\t\t@(negedge clk) wavedrom_stop();\n\n\t\trepeat(500) @(posedge clk, negedge clk) begin\n\t\t\t{A,B,C,S} <= $random;\n\t\t\tenable <= ($random&3) == 0;\n\t\tend\n\t\t\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_Z;\n\t\tint errortime_Z;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic enable;\n\tlogic S;\n\tlogic A;\n\tlogic B;\n\tlogic C;\n\tlogic Z_ref;\n\tlogic Z_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,enable,S,A,B,C,Z_ref,Z_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.enable,\n\t\t.S,\n\t\t.A,\n\t\t.B,\n\t\t.C );\n\treference_module good1 (\n\t\t.clk,\n\t\t.enable,\n\t\t.S,\n\t\t.A,\n\t\t.B,\n\t\t.C,\n\t\t.Z(Z_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.enable,\n\t\t.S,\n\t\t.A,\n\t\t.B,\n\t\t.C,\n\t\t.Z(Z_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_Z) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"Z\", stats1.errors_Z, stats1.errortime_Z);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"Z\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { Z_ref } === ( { Z_ref } ^ { Z_dut } ^ { Z_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (Z_ref !== ( Z_ref ^ Z_dut ^ Z_ref ))\n\t\tbegin if (stats1.errors_Z == 0) stats1.errortime_Z = $time;\n\t\t\tstats1.errors_Z = stats1.errors_Z+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "thermostat", "task_number": 44, "description": "A heating/cooling thermostat controls both a heater (during winter) and an air conditioner (during summer). Implement a circuit that will turn on and off the heater, air conditioning, and blower fan as appropriate. The thermostat can be in one of two modes: heating (mode = 1) and cooling (mode = 0). In heating mode, turn the heater on when it is too cold (too_cold = 1) but do not use the air conditioner. In cooling mode, turn the air conditioner on when it is too hot (too_hot = 1), but do not turn on the heater. When the heater or air conditioner are on, also turn on the fan to circulate the air. In addition, the user can also request the fan to turn on (fan_on = 1), even if the heater and air conditioner are off.", "header": "module top_module(\n\tinput mode,\n\tinput too_cold, \n\tinput too_hot,\n\tinput fan_on,\n\toutput heater,\n\toutput aircon,\n\toutput fan\n);\n", "module_code": "module top_module(\n\tinput mode,\n\tinput too_cold, \n\tinput too_hot,\n\tinput fan_on,\n\toutput heater,\n\toutput aircon,\n\toutput fan\n);\n\t\n\tassign fan = (mode ? too_cold : too_hot) | fan_on;\n\tassign heater = (mode & too_cold);\n\tassign aircon = (~mode & too_hot);\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput mode,\n\tinput too_cold, \n\tinput too_hot,\n\tinput fan_on,\n\toutput heater,\n\toutput aircon,\n\toutput fan\n);\n\t\n\tassign fan = (mode ? too_cold : too_hot) | fan_on;\n\tassign heater = (mode & too_cold);\n\tassign aircon = (~mode & too_hot);\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg too_cold, too_hot, mode, fan_on,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\t{too_cold, too_hot, mode, fan_on} <= 4'b0010;\n\t\t@(negedge clk);\n\t\twavedrom_start(\"Winter\");\n\t\t\t@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b0010;\n\t\t\t@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b0010;\n\t\t\t@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b1010;\n\t\t\t@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b1011;\n\t\t\t@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b0010;\n\t\t\t@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b0011;\n\t\t\t@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b0010;\n\t\t\t@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b0110;\n\t\t\t@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b1110;\n\t\t\t@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b0111;\n\t\t\t@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b1111;\n\t\t@(negedge clk) wavedrom_stop();\n\n\t\t{too_cold, too_hot, mode, fan_on} <= 4'b0000;\n\t\t@(negedge clk);\n\t\twavedrom_start(\"Summer\");\n\t\t\t@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b0000;\n\t\t\t@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b0000;\n\t\t\t@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b0100;\n\t\t\t@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b0101;\n\t\t\t@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b0000;\n\t\t\t@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b0001;\n\t\t\t@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b0000;\n\t\t\t@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b1000;\n\t\t\t@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b1100;\n\t\t\t@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b1001;\n\t\t\t@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b1101;\n\t\t@(negedge clk) wavedrom_stop();\n\t\t\n\t\trepeat(200)\n\t\t\t@(posedge clk, negedge clk) {too_cold, too_hot, mode, fan_on} <= $random;\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_heater;\n\t\tint errortime_heater;\n\t\tint errors_aircon;\n\t\tint errortime_aircon;\n\t\tint errors_fan;\n\t\tint errortime_fan;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic mode;\n\tlogic too_cold;\n\tlogic too_hot;\n\tlogic fan_on;\n\tlogic heater_ref;\n\tlogic heater_dut;\n\tlogic aircon_ref;\n\tlogic aircon_dut;\n\tlogic fan_ref;\n\tlogic fan_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,mode,too_cold,too_hot,fan_on,heater_ref,heater_dut,aircon_ref,aircon_dut,fan_ref,fan_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.mode,\n\t\t.too_cold,\n\t\t.too_hot,\n\t\t.fan_on );\n\treference_module good1 (\n\t\t.mode,\n\t\t.too_cold,\n\t\t.too_hot,\n\t\t.fan_on,\n\t\t.heater(heater_ref),\n\t\t.aircon(aircon_ref),\n\t\t.fan(fan_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.mode,\n\t\t.too_cold,\n\t\t.too_hot,\n\t\t.fan_on,\n\t\t.heater(heater_dut),\n\t\t.aircon(aircon_dut),\n\t\t.fan(fan_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_heater) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"heater\", stats1.errors_heater, stats1.errortime_heater);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"heater\");\n\t\tif (stats1.errors_aircon) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"aircon\", stats1.errors_aircon, stats1.errortime_aircon);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"aircon\");\n\t\tif (stats1.errors_fan) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"fan\", stats1.errors_fan, stats1.errortime_fan);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"fan\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { heater_ref, aircon_ref, fan_ref } === ( { heater_ref, aircon_ref, fan_ref } ^ { heater_dut, aircon_dut, fan_dut } ^ { heater_ref, aircon_ref, fan_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (heater_ref !== ( heater_ref ^ heater_dut ^ heater_ref ))\n\t\tbegin if (stats1.errors_heater == 0) stats1.errortime_heater = $time;\n\t\t\tstats1.errors_heater = stats1.errors_heater+1'b1; end\n\t\tif (aircon_ref !== ( aircon_ref ^ aircon_dut ^ aircon_ref ))\n\t\tbegin if (stats1.errors_aircon == 0) stats1.errortime_aircon = $time;\n\t\t\tstats1.errors_aircon = stats1.errors_aircon+1'b1; end\n\t\tif (fan_ref !== ( fan_ref ^ fan_dut ^ fan_ref ))\n\t\tbegin if (stats1.errors_fan == 0) stats1.errortime_fan = $time;\n\t\t\tstats1.errors_fan = stats1.errors_fan+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "ece241_2013_q2", "task_number": 45, "description": "A single-output digital system with four inputs (a,b,c,d) generates a logic-1 when 2, 7, or 15 appears on the inputs, and a logic-0 when 0, 1, 4, 5, 6, 9, 10, 13, or 14 appears. The input conditions for the numbers 3, 8, 11, and 12 never occur in this system. For example, 7 corresponds to a,b,c,d being set to 0,1,1,1, respectively. Determine the output out_sop in minimum sum-of-products form, and the output out_pos in minimum product-of-sums form.\n\n", "header": "module top_module (\n\tinput a,\n\tinput b,\n\tinput c,\n\tinput d,\n\toutput out_sop,\n\toutput out_pos\n);\n", "module_code": "module top_module (\n\tinput a,\n\tinput b,\n\tinput c,\n\tinput d,\n\toutput out_sop,\n\toutput out_pos\n);\n\t\n\twire pos0, pos1;\n\tassign out_sop = c&d | ~a&~b&c;\n\tassign pos0 = c & (~b|d)&(~a|b);\n\tassign pos1 = c & (~b|d)&(~a|d);\n\t\n\tassign out_pos = (pos0 == pos1) ? pos0 : 1'bx;\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput a,\n\tinput b,\n\tinput c,\n\tinput d,\n\toutput out_sop,\n\toutput out_pos\n);\n\t\n\twire pos0, pos1;\n\tassign out_sop = c&d | ~a&~b&c;\n\tassign pos0 = c & (~b|d)&(~a|b);\n\tassign pos1 = c & (~b|d)&(~a|d);\n\t\n\tassign out_pos = (pos0 == pos1) ? pos0 : 1'bx;\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic a, b, c, d,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\tinput tb_match\n);\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tbit fail = 0;\n\tbit fail1 = 0;\n\talways @(posedge clk, negedge clk)\n\t\tif (!tb_match)\n\t\t\tfail = 1;\n\n\tinitial begin\n\t\t@(posedge clk) {a,b,c,d} <= 0;\n\t\t@(posedge clk) {a,b,c,d} <= 1;\n\t\t@(posedge clk) {a,b,c,d} <= 2;\n\t\t@(posedge clk) {a,b,c,d} <= 4;\n\t\t@(posedge clk) {a,b,c,d} <= 5;\n\t\t@(posedge clk) {a,b,c,d} <= 6;\n\t\t@(posedge clk) {a,b,c,d} <= 7;\n\t\t@(posedge clk) {a,b,c,d} <= 9;\n\t\t@(posedge clk) {a,b,c,d} <= 10;\n\t\t@(posedge clk) {a,b,c,d} <= 13;\n\t\t@(posedge clk) {a,b,c,d} <= 14;\n\t\t@(posedge clk) {a,b,c,d} <= 15;\n\t\t@(posedge clk) fail1 = fail;\n\t\t\n\t\t\n\t\t\t\t\n\t\t\n\t\t//@(negedge clk) wavedrom_start();\n\t\t\tfor (int i=0;i<16;i++)\n\t\t\t\t@(posedge clk)\n\t\t\t\t\t{a,b,c,d} <= i;\n\t\t//@(negedge clk) wavedrom_stop();\n\t\t\n\t\trepeat(50) @(posedge clk, negedge clk)\n\t\t\t{a,b,c,d} <= $random;\n\t\t\t\n\t\tif (fail && ~fail1)\n\t\t\t$display(\"Hint: Your circuit passes on the 12 required input combinations, but doesn't match the don't-care cases. Are you using minimal SOP and POS?\");\n\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out_sop;\n\t\tint errortime_out_sop;\n\t\tint errors_out_pos;\n\t\tint errortime_out_pos;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic a;\n\tlogic b;\n\tlogic c;\n\tlogic d;\n\tlogic out_sop_ref;\n\tlogic out_sop_dut;\n\tlogic out_pos_ref;\n\tlogic out_pos_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,a,b,c,d,out_sop_ref,out_sop_dut,out_pos_ref,out_pos_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d );\n\treference_module good1 (\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d,\n\t\t.out_sop(out_sop_ref),\n\t\t.out_pos(out_pos_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d,\n\t\t.out_sop(out_sop_dut),\n\t\t.out_pos(out_pos_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out_sop) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_sop\", stats1.errors_out_sop, stats1.errortime_out_sop);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_sop\");\n\t\tif (stats1.errors_out_pos) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_pos\", stats1.errors_out_pos, stats1.errortime_out_pos);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_pos\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_sop_ref, out_pos_ref } === ( { out_sop_ref, out_pos_ref } ^ { out_sop_dut, out_pos_dut } ^ { out_sop_ref, out_pos_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_sop_ref !== ( out_sop_ref ^ out_sop_dut ^ out_sop_ref ))\n\t\tbegin if (stats1.errors_out_sop == 0) stats1.errortime_out_sop = $time;\n\t\t\tstats1.errors_out_sop = stats1.errors_out_sop+1'b1; end\n\t\tif (out_pos_ref !== ( out_pos_ref ^ out_pos_dut ^ out_pos_ref ))\n\t\tbegin if (stats1.errors_out_pos == 0) stats1.errortime_out_pos = $time;\n\t\t\tstats1.errors_out_pos = stats1.errors_out_pos+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "lfsr32", "task_number": 46, "description": "A linear feedback shift register is a shift register usually with a few XOR gates to produce the next state of the shift register. A Galois LFSR is one particular arrangement where bit positions with a \"tap\" are XORed with the output bit to produce each bit's next value, while bit positions without a tap shift. Build a 32-bit Galois LFSR with taps at bit positions 32, 22, 2, and 1. Reset should be active high synchronous, and should reset the output q to 32'h1.", "header": "module top_module(\n\tinput clk,\n\tinput reset,\n\toutput reg [31:0] q);\n", "module_code": "module top_module(\n\tinput clk,\n\tinput reset,\n\toutput reg [31:0] q);\n\t\n\tlogic [31:0] q_next;\n\talways@(q) begin\n\t\tq_next = q[31:1];\n\t\tq_next[31] = q[0];\n\t\tq_next[21] ^= q[0];\n\t\tq_next[1] ^= q[0];\n\t\tq_next[0] ^= q[0];\n\tend\n\t\n\talways @(posedge clk) begin\n\t\tif (reset)\n\t\t\tq <= 32'h1;\n\t\telse\n\t\t\tq <= q_next;\n\tend\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput clk,\n\tinput reset,\n\toutput reg [31:0] q);\n\t\n\tlogic [31:0] q_next;\n\talways@(q) begin\n\t\tq_next = q[31:1];\n\t\tq_next[31] = q[0];\n\t\tq_next[21] ^= q[0];\n\t\tq_next[1] ^= q[0];\n\t\tq_next[0] ^= q[0];\n\tend\n\t\n\talways @(posedge clk) begin\n\t\tif (reset)\n\t\t\tq <= 32'h1;\n\t\telse\n\t\t\tq <= q_next;\n\tend\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg reset\n);\n\n\t\n\tinitial begin\n\t\trepeat(400) @(posedge clk, negedge clk) begin\n\t\t\treset <= !($random & 31);\n\t\tend\n\t\t@(posedge clk) reset <= 1'b0;\n\t\trepeat(200000) @(posedge clk);\n\t\treset <= 1'b1;\n\t\trepeat(5) @(posedge clk);\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_q;\n\t\tint errortime_q;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic reset;\n\tlogic [31:0] q_ref;\n\tlogic [31:0] q_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,q_ref,q_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.reset );\n\treference_module good1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.q(q_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.q(q_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"q\", stats1.errors_q, stats1.errortime_q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"q\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (q_ref !== ( q_ref ^ q_dut ^ q_ref ))\n\t\tbegin if (stats1.errors_q == 0) stats1.errortime_q = $time;\n\t\t\tstats1.errors_q = stats1.errors_q+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "circuit3", "task_number": 47, "description": "This is a combinational circuit. Read the simulation waveforms to determine what the circuit does, then implement it.\n\n// time            a               b               c               d               q               \n// 0ns             0               0               0               0               0               \n// 5ns             0               0               0               0               0               \n// 10ns            0               0               0               0               0               \n// 15ns            0               0               0               0               0               \n// 20ns            0               0               0               1               0               \n// 25ns            0               0               1               0               0               \n// 30ns            0               0               1               1               0               \n// 35ns            0               1               0               0               0               \n// 40ns            0               1               0               1               1               \n// 45ns            0               1               1               0               1               \n// 50ns            0               1               1               1               1               \n// 55ns            1               0               0               0               0               \n// 60ns            1               0               0               1               1               \n// 65ns            1               0               1               0               1               \n// 70ns            1               0               1               1               1               \n// 75ns            1               1               0               0               0               \n// 80ns            1               1               0               1               1               \n// 85ns            1               1               1               0               1               \n// 90ns            1               1               1               1               1               ", "header": "module top_module (\n\tinput a, \n\tinput b, \n\tinput c, \n\tinput d,\n\toutput q\n);\n", "module_code": "module top_module (\n\tinput a, \n\tinput b, \n\tinput c, \n\tinput d,\n\toutput q\n);\n\n\tassign q = (a|b) & (c|d);\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput a, \n\tinput b, \n\tinput c, \n\tinput d,\n\toutput q\n);\n\n\tassign q = (a|b) & (c|d);\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic a,b,c,d,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\t{a,b,c,d} <= 0;\n\t\t@(negedge clk) wavedrom_start(\"Unknown circuit\");\n\t\t\t@(posedge clk) {a,b,c,d} <= 0;\n\t\t\trepeat(18) @(posedge clk, negedge clk) {a,b,c,d} <= {a,b,c,d} + 1;\n\t\twavedrom_stop();\n\t\t\n\t\trepeat(100) @(posedge clk, negedge clk)\n\t\t\t{a,b,c,d} <= $urandom;\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_q;\n\t\tint errortime_q;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic a;\n\tlogic b;\n\tlogic c;\n\tlogic d;\n\tlogic q_ref;\n\tlogic q_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,a,b,c,d,q_ref,q_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d );\n\treference_module good1 (\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d,\n\t\t.q(q_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d,\n\t\t.q(q_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"q\", stats1.errors_q, stats1.errortime_q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"q\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (q_ref !== ( q_ref ^ q_dut ^ q_ref ))\n\t\tbegin if (stats1.errors_q == 0) stats1.errortime_q = $time;\n\t\t\tstats1.errors_q = stats1.errors_q+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "7420", "task_number": 48, "description": "The 7400-series integrated circuits are a series of digital chips with a few gates each. The 7420 is a chip with two 4-input NAND gates.\n\n// Create a module with the same functionality as the 7420 chip. It has 8 inputs and 2 outputs.", "header": "module top_module(\n\tinput p1a, \n\tinput p1b, \n\tinput p1c, \n\tinput p1d, \n\toutput p1y, \n\tinput p2a, \n\tinput p2b, \n\tinput p2c, \n\tinput p2d, \n\toutput p2y\n);\n", "module_code": "module top_module(\n\tinput p1a, \n\tinput p1b, \n\tinput p1c, \n\tinput p1d, \n\toutput p1y, \n\tinput p2a, \n\tinput p2b, \n\tinput p2c, \n\tinput p2d, \n\toutput p2y\n);\n\t\n\tassign p1y = ~&( {p1a, p1b, p1c, p1d} );\n\tassign p2y = ~&( {p2a, p2b, p2c, p2d} );\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput p1a, \n\tinput p1b, \n\tinput p1c, \n\tinput p1d, \n\toutput p1y, \n\tinput p2a, \n\tinput p2b, \n\tinput p2c, \n\tinput p2d, \n\toutput p2y\n);\n\t\n\tassign p1y = ~&( {p1a, p1b, p1c, p1d} );\n\tassign p2y = ~&( {p2a, p2b, p2c, p2d} );\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg p1a, p1b, p1c, p1d,\n\toutput reg p2a, p2b, p2c, p2d,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\tint count; count = 0;\n\t\t{p1a,p1b,p1c,p1d} <= 4'h0;\t\t\n\t\t{p2a,p2b,p2c,p2d} <= 4'h0;\t\t\n\t\twavedrom_start(\"Two NAND gates\");\n\t\trepeat(20) @(posedge clk) begin\n\t\t\t{p1a,p1b,p1c,p1d} <= count;\t\t\n\t\t\t{p2a,p2b,p2c,p2d} <= count+1;\t\t\n\t\t\tcount = count + 1;\n\t\tend\n\t\twavedrom_stop();\n\n\t\trepeat(200) @(posedge clk,negedge clk) begin\n\t\t\t{p1a,p1b,p1c,p1d,p2a,p2b,p2c,p2d} <= $random;\t\t\n\t\tend\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_p1y;\n\t\tint errortime_p1y;\n\t\tint errors_p2y;\n\t\tint errortime_p2y;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic p1a;\n\tlogic p1b;\n\tlogic p1c;\n\tlogic p1d;\n\tlogic p2a;\n\tlogic p2b;\n\tlogic p2c;\n\tlogic p2d;\n\tlogic p1y_ref;\n\tlogic p1y_dut;\n\tlogic p2y_ref;\n\tlogic p2y_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,p1a,p1b,p1c,p1d,p2a,p2b,p2c,p2d,p1y_ref,p1y_dut,p2y_ref,p2y_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.p1a,\n\t\t.p1b,\n\t\t.p1c,\n\t\t.p1d,\n\t\t.p2a,\n\t\t.p2b,\n\t\t.p2c,\n\t\t.p2d );\n\treference_module good1 (\n\t\t.p1a,\n\t\t.p1b,\n\t\t.p1c,\n\t\t.p1d,\n\t\t.p2a,\n\t\t.p2b,\n\t\t.p2c,\n\t\t.p2d,\n\t\t.p1y(p1y_ref),\n\t\t.p2y(p2y_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.p1a,\n\t\t.p1b,\n\t\t.p1c,\n\t\t.p1d,\n\t\t.p2a,\n\t\t.p2b,\n\t\t.p2c,\n\t\t.p2d,\n\t\t.p1y(p1y_dut),\n\t\t.p2y(p2y_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_p1y) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"p1y\", stats1.errors_p1y, stats1.errortime_p1y);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"p1y\");\n\t\tif (stats1.errors_p2y) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"p2y\", stats1.errors_p2y, stats1.errortime_p2y);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"p2y\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { p1y_ref, p2y_ref } === ( { p1y_ref, p2y_ref } ^ { p1y_dut, p2y_dut } ^ { p1y_ref, p2y_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (p1y_ref !== ( p1y_ref ^ p1y_dut ^ p1y_ref ))\n\t\tbegin if (stats1.errors_p1y == 0) stats1.errortime_p1y = $time;\n\t\t\tstats1.errors_p1y = stats1.errors_p1y+1'b1; end\n\t\tif (p2y_ref !== ( p2y_ref ^ p2y_dut ^ p2y_ref ))\n\t\tbegin if (stats1.errors_p2y == 0) stats1.errortime_p2y = $time;\n\t\t\tstats1.errors_p2y = stats1.errors_p2y+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "popcount255", "task_number": 49, "description": "A \"population count\" circuit counts the number of '1's in an input vector. Build a population count circuit for a 255-bit input vector.", "header": "module top_module (\n\tinput [254:0] in,\n\toutput reg [7:0] out\n);\n", "module_code": "module top_module (\n\tinput [254:0] in,\n\toutput reg [7:0] out\n);\n\n\talways_comb  begin\n\t\tout = 0;\n\t\tfor (int i=0;i<255;i++)\n\t\t\tout = out + in[i];\n\tend\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [254:0] in,\n\toutput reg [7:0] out\n);\n\n\talways_comb  begin\n\t\tout = 0;\n\t\tfor (int i=0;i<255;i++)\n\t\t\tout = out + in[i];\n\tend\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic [254:0] in,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\tinitial begin\n\t\tin <= 255'h0;\n\t\twavedrom_start(\"\");\n\t\t@(posedge clk, negedge clk) in <= 255'h0;\n\t\t@(posedge clk, negedge clk) in <= 255'h0;\n\t\t@(posedge clk, negedge clk) in <= 255'h1;\n\t\t@(posedge clk, negedge clk) in <= 255'h1;\n\t\t@(posedge clk, negedge clk) in <= 255'h3;\n\t\t@(posedge clk, negedge clk) in <= 255'h3;\n\t\t@(posedge clk, negedge clk) in <= 255'h7;\n\t\t@(posedge clk, negedge clk) in <= 255'haaaa;\n\t\t@(posedge clk, negedge clk) in <= 255'hf00000;\n\t\t@(posedge clk, negedge clk) in <= 255'h0;\n\t\twavedrom_stop();\n\t\trepeat (200) @(posedge clk, negedge clk) begin\n\t\t\tin <= {$random, $random, $random, $random, $random, $random, $random, $random};\n\t\tend\n\t\t@(posedge clk);\n\t\tin <= '0;\n\t\t@(posedge clk)\n\t\tin <= '1;\n\t\t@(posedge clk)\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [254:0] in;\n\tlogic [7:0] out_ref;\n\tlogic [7:0] out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,in,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in );\n\treference_module good1 (\n\t\t.in,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.in,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "gatesv", "task_number": 50, "description": "You are given a four-bit input vector in[3:0]. We want to know some relationships between each bit and its neighbour: \n// (1) out_both: Each bit of this output vector should indicate whether both the corresponding input bit and its neighbour to the left (higher index) are '1'. For example, out_both[2] should indicate if in[2] and in[3] are both 1. Since in[3] has no neighbour to the left, the answer is obvious so we don't need to know out_both[3]. \n// (2) out_any: Each bit of this output vector should indicate whether any of the corresponding input bit and its neighbour to the right are '1'. For example, out_any[2] should indicate if either in[2] or in[1] are 1. Since in[0] has no neighbour to the right, the answer is obvious so we don't need to know out_any[0]. \n// (3) out_different: Each bit of this output vector should indicate whether the corresponding input bit is different from its neighbour to the left. For example, out_different[2] should indicate if in[2] is different from in[3]. For this part, treat the vector as wrapping around, so in[3]'s neighbour to the left is in[0].", "header": "module top_module (\n\tinput [3:0] in,\n\toutput [2:0] out_both,\n\toutput [3:1] out_any,\n\toutput [3:0] out_different\n);\n", "module_code": "module top_module (\n\tinput [3:0] in,\n\toutput [2:0] out_both,\n\toutput [3:1] out_any,\n\toutput [3:0] out_different\n);\n\n\tassign out_both = in[2:0] & in[3:1];\n\tassign out_any = in[2:0] | in[3:1];\n\tassign out_different = in^{in[0], in[3:1]};\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [3:0] in,\n\toutput [2:0] out_both,\n\toutput [3:1] out_any,\n\toutput [3:0] out_different\n);\n\n\tassign out_both = in[2:0] & in[3:1];\n\tassign out_any = in[2:0] | in[3:1];\n\tassign out_different = in^{in[0], in[3:1]};\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\tinput tb_match,\n\toutput logic [3:0] in,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\tin <= 4'h3;\n\t\t@(negedge clk);\n\t\twavedrom_start();\n\t\t\t@(posedge clk) in <= 3;\n\t\t\t@(posedge clk) in <= 6;\n\t\t\t@(posedge clk) in <= 12;\n\t\t\t@(posedge clk) in <= 9;\n\t\t\t@(posedge clk) in <= 5;\n\t\t@(negedge clk);\n\t\twavedrom_stop();\n\t\tin <= $random;\n\t\trepeat(100) begin\n\t\t\t@(negedge clk) in <= $random;\n\t\t\t@(posedge clk) in <= $random;\n\t\tend\n\t\t#1 $finish;\n\tend\n\t\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out_both;\n\t\tint errortime_out_both;\n\t\tint errors_out_any;\n\t\tint errortime_out_any;\n\t\tint errors_out_different;\n\t\tint errortime_out_different;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [3:0] in;\n\tlogic [2:0] out_both_ref;\n\tlogic [2:0] out_both_dut;\n\tlogic [3:1] out_any_ref;\n\tlogic [3:1] out_any_dut;\n\tlogic [3:0] out_different_ref;\n\tlogic [3:0] out_different_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,in,out_both_ref,out_both_dut,out_any_ref,out_any_dut,out_different_ref,out_different_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in );\n\treference_module good1 (\n\t\t.in,\n\t\t.out_both(out_both_ref),\n\t\t.out_any(out_any_ref),\n\t\t.out_different(out_different_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.in,\n\t\t.out_both(out_both_dut),\n\t\t.out_any(out_any_dut),\n\t\t.out_different(out_different_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out_both) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_both\", stats1.errors_out_both, stats1.errortime_out_both);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_both\");\n\t\tif (stats1.errors_out_any) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_any\", stats1.errors_out_any, stats1.errortime_out_any);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_any\");\n\t\tif (stats1.errors_out_different) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_different\", stats1.errors_out_different, stats1.errortime_out_different);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_different\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_both_ref, out_any_ref, out_different_ref } === ( { out_both_ref, out_any_ref, out_different_ref } ^ { out_both_dut, out_any_dut, out_different_dut } ^ { out_both_ref, out_any_ref, out_different_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_both_ref !== ( out_both_ref ^ out_both_dut ^ out_both_ref ))\n\t\tbegin if (stats1.errors_out_both == 0) stats1.errortime_out_both = $time;\n\t\t\tstats1.errors_out_both = stats1.errors_out_both+1'b1; end\n\t\tif (out_any_ref !== ( out_any_ref ^ out_any_dut ^ out_any_ref ))\n\t\tbegin if (stats1.errors_out_any == 0) stats1.errortime_out_any = $time;\n\t\t\tstats1.errors_out_any = stats1.errors_out_any+1'b1; end\n\t\tif (out_different_ref !== ( out_different_ref ^ out_different_dut ^ out_different_ref ))\n\t\tbegin if (stats1.errors_out_different == 0) stats1.errortime_out_different = $time;\n\t\t\tstats1.errors_out_different = stats1.errors_out_different+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "circuit6", "task_number": 51, "description": "This is a combinational circuit. Read the simulation waveforms to determine what the circuit does, then implement it.\n\n// time            a                  q            \n// 0ns             x                  x            \n// 5ns             x                  x            \n// 10ns            x                  x            \n// 15ns            0               1232            \n// 20ns            1               aee0            \n// 25ns            2               27d4            \n// 30ns            3               5a0e            \n// 35ns            4               2066            \n// 40ns            5               64ce            \n// 45ns            6               c526            \n// 50ns            7               2f19            \n// 55ns            0               1232            \n// 60ns            1               aee0            \n// 65ns            2               27d4            \n// 70ns            4               2066            \n// 75ns            1               aee0            \n// 80ns            1               aee0            \n// 85ns            3               5a0e            \n// 90ns            5               64ce            ", "header": "module top_module (\n\tinput [2:0] a, \n\toutput reg [15:0] q\n);\n", "module_code": "module top_module (\n\tinput [2:0] a, \n\toutput reg [15:0] q\n);\n\n\talways @(*) \n\t\tcase (a)\n\t\t\t0: q = 4658;\n\t\t\t1: q = 44768;\n\t\t\t2: q = 10196;\n\t\t\t3: q = 23054;\n\t\t\t4: q = 8294;\n\t\t\t5: q = 25806;\n\t\t\t6: q = 50470;\n\t\t\t7: q = 12057;\n\t\tendcase\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [2:0] a, \n\toutput reg [15:0] q\n);\n\n\talways @(*) \n\t\tcase (a)\n\t\t\t0: q = 4658;\n\t\t\t1: q = 44768;\n\t\t\t2: q = 10196;\n\t\t\t3: q = 23054;\n\t\t\t4: q = 8294;\n\t\t\t5: q = 25806;\n\t\t\t6: q = 50470;\n\t\t\t7: q = 12057;\n\t\tendcase\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic [2:0] a,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\t@(negedge clk) wavedrom_start(\"Unknown circuit\");\n\t\t\t@(posedge clk) {a} <= 0;\n\t\t\trepeat(10) @(posedge clk,negedge clk) a <= a + 1;\n\t\twavedrom_stop();\n\n\t\trepeat(100) @(posedge clk, negedge clk)\n\t\t\ta <= $urandom;\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_q;\n\t\tint errortime_q;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [2:0] a;\n\tlogic [15:0] q_ref;\n\tlogic [15:0] q_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,a,q_ref,q_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.a );\n\treference_module good1 (\n\t\t.a,\n\t\t.q(q_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.a,\n\t\t.q(q_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"q\", stats1.errors_q, stats1.errortime_q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"q\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (q_ref !== ( q_ref ^ q_dut ^ q_ref ))\n\t\tbegin if (stats1.errors_q == 0) stats1.errortime_q = $time;\n\t\t\tstats1.errors_q = stats1.errors_q+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "countslow", "task_number": 52, "description": "Build a decade counter that counts from 0 through 9, inclusive, with a period of 10. The reset input is active high synchronous, and should reset the counter to 0. We want to be able to pause the counter rather than always incrementing every clock cycle, so the \"slowena\" input if high indicates when the counter should increment. ", "header": "module top_module(\n\tinput clk,\n\tinput slowena,\n\tinput reset,\n\toutput reg [3:0] q);\n", "module_code": "module top_module(\n\tinput clk,\n\tinput slowena,\n\tinput reset,\n\toutput reg [3:0] q);\n\t\n\talways @(posedge clk)\n\t\tif (reset)\n\t\t\tq <= 0;\n\t\telse if (slowena) begin\n\t\t\tif (q == 9)\n\t\t\t\tq <= 0;\n\t\t\telse\n\t\t\t\tq <= q+1;\n\t\tend\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput clk,\n\tinput slowena,\n\tinput reset,\n\toutput reg [3:0] q);\n\t\n\talways @(posedge clk)\n\t\tif (reset)\n\t\t\tq <= 0;\n\t\telse if (slowena) begin\n\t\t\tif (q == 9)\n\t\t\t\tq <= 0;\n\t\t\telse\n\t\t\t\tq <= q+1;\n\t\tend\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg slowena,\n\toutput reg reset,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\tinput tb_match\t\n);\n\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\t\n\treg hint1;\n\tinitial begin\n\t\treset <= 1;\n\t\tslowena <= 1;\n\t\twavedrom_start(\"Synchronous reset and counting.\");\n\t\treset_test();\n\t\trepeat(12) @(posedge clk);\n\t\twavedrom_stop();\n\t\t@(posedge clk);\n\n\t\t//wavedrom_start(\"Testing.\");\n\t\treset <= 1;\n\t\t@(posedge clk);\n\t\treset <= 0;\n\t\trepeat(9) @(posedge clk);\n\t\tslowena <= 0;\n\t\t@(negedge clk) hint1 = tb_match;\n\t\trepeat(3) @(posedge clk);\n\t\tif (hint1 && !tb_match) begin\n\t\t\t$display (\"Hint: What is supposed to happen when the counter is 9 and not enabled?\");\n\t\tend\n\t\t//wavedrom_stop();\n\t\tslowena <= 1;\n\t\treset <= 1;\n\t\t@(posedge clk);\n\t\treset <= 0;\n\n\n\t\twavedrom_start(\"Enable/disable\");\n\t\trepeat(15) @(posedge clk) slowena <= !($random & 1);\n\t\twavedrom_stop();\n\t\t@(posedge clk);\n\n\t\trepeat(400) @(posedge clk, negedge clk) begin\n\t\t\tslowena <= !($random&3);\n\t\t\treset <= !($random & 31);\n\t\tend\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_q;\n\t\tint errortime_q;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic slowena;\n\tlogic reset;\n\tlogic [3:0] q_ref;\n\tlogic [3:0] q_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,slowena,reset,q_ref,q_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.slowena,\n\t\t.reset );\n\treference_module good1 (\n\t\t.clk,\n\t\t.slowena,\n\t\t.reset,\n\t\t.q(q_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.slowena,\n\t\t.reset,\n\t\t.q(q_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"q\", stats1.errors_q, stats1.errortime_q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"q\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (q_ref !== ( q_ref ^ q_dut ^ q_ref ))\n\t\tbegin if (stats1.errors_q == 0) stats1.errortime_q = $time;\n\t\t\tstats1.errors_q = stats1.errors_q+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "m2014_q4f", "task_number": 53, "description": "Implement the following circuit in Verilog. Two inputs (in1 and in2) go to an AND gate, but the in2 input to the AND gate has a bubble. The output of the AND gate is connected to 'out'.", "header": "module top_module (\n\tinput in1,\n\tinput in2,\n\toutput logic out\n);\n", "module_code": "module top_module (\n\tinput in1,\n\tinput in2,\n\toutput logic out\n);\n\n\tassign out = in1 & ~in2;\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput in1,\n\tinput in2,\n\toutput logic out\n);\n\n\tassign out = in1 & ~in2;\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic in1, in2\n);\n\n\tinitial begin\n\t\trepeat(100) @(posedge clk, negedge clk) begin\n\t\t\t{in1, in2} <= $random;\n\t\tend\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic in1;\n\tlogic in2;\n\tlogic out_ref;\n\tlogic out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,in1,in2,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in1,\n\t\t.in2 );\n\treference_module good1 (\n\t\t.in1,\n\t\t.in2,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.in1,\n\t\t.in2,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "m2014_q4h", "task_number": 54, "description": "The module assigns the output port to the same value as the input port combinationally.", "header": "module top_module(\n\tinput in,\n\toutput out);\n", "module_code": "module top_module(\n\tinput in,\n\toutput out);\n\t\n\tassign out = in;\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput in,\n\toutput out);\n\t\n\tassign out = in;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg in = 0\n);\n\n\tinitial begin\n\t\trepeat(100) @(posedge clk, negedge clk) begin\n\t\t\tin <= $random;\n\t\tend\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic in;\n\tlogic out_ref;\n\tlogic out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,in,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in );\n\treference_module good1 (\n\t\t.in,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.in,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "fsm1", "task_number": 55, "description": "Consider the follow Moore machine with the diagram described below:\n\n// B (1) --0--> A\n// B (1) --1--> B\n// A (0) --0--> B\n// A (0) --1--> A\n\n// Write Verilog implementing this state machine. It should asynchronously reset into state B if reset if high.", "header": "module top_module (\n\tinput clk,\n\tinput in,\n\tinput areset,\n\toutput out\n);\n", "module_code": "module top_module (\n\tinput clk,\n\tinput in,\n\tinput areset,\n\toutput out\n);\n\tparameter A=0, B=1;\n\treg state;\n\treg next;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tA: next = in ? A : B;\n\t\t\tB: next = in ? B : A;\n\t\tendcase\n    end\n    \n    always @(posedge clk, posedge areset) begin\n\t\tif (areset) state <= B;\n        else state <= next;\n\tend\n\t\t\n\tassign out = (state==B);\n\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput in,\n\tinput areset,\n\toutput out\n);\n\tparameter A=0, B=1;\n\treg state;\n\treg next;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tA: next = in ? A : B;\n\t\t\tB: next = in ? B : A;\n\t\tendcase\n    end\n    \n    always @(posedge clk, posedge areset) begin\n\t\tif (areset) state <= B;\n        else state <= next;\n\tend\n\t\t\n\tassign out = (state==B);\n\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic in,\n\toutput logic areset,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\tinput tb_match\n);\n\treg reset;\n\tassign areset = reset;\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\tinitial begin\n\t\treset <= 1;\n\t\tin <= 0;\n\t\t@(posedge clk) reset <= 0; in <= 0;\n\t\t@(posedge clk) in <= 1;\n\t\twavedrom_start();\n\t\t\treset_test(1);\n\t\t\t@(posedge clk) in <= 0;\n\t\t\t@(posedge clk) in <= 0;\n\t\t\t@(posedge clk) in <= 0;\n\t\t\t@(posedge clk) in <= 1;\n\t\t\t@(posedge clk) in <= 1;\n\t\t@(negedge clk);\n\t\twavedrom_stop();\n\t\trepeat(200) @(posedge clk, negedge clk) begin\n\t\t\tin <= $random;\n\t\t\treset <= !($random & 7);\n\t\tend\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic in;\n\tlogic areset;\n\tlogic out_ref;\n\tlogic out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,in,areset,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in,\n\t\t.areset );\n\treference_module good1 (\n\t\t.clk,\n\t\t.in,\n\t\t.areset,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.in,\n\t\t.areset,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "dualedge", "task_number": 56, "description": "A dual-edge triggered flip-flop is triggered on both edges of the clock. However, FPGAs don't have dual-edge triggered flip-flops, and always @(posedge clk or negedge clk) is not accepted as a legal sensitivity list. Build a circuit that functionally behaves like a dual-edge triggered flip-flop.", "header": "module top_module(\n\tinput clk,\n\tinput d,\n\toutput reg q);\n", "module_code": "module top_module(\n\tinput clk,\n\tinput d,\n\toutput reg q);\n\t\n\t/*always @(posedge clk, negedge clk) begin\n\t\tq <= d;\n\tend*/\n\n\treg qp, qn;\n    always @(posedge clk)\n        qp <= d;\n    always @(negedge clk)\n        qn <= d;\n    // assign q = clk ? qp : qn;  // This causes q to change too early when clk changes. Need delay by delta cycle\n    always @(*)\n        q <= clk ? qp : qn;\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput clk,\n\tinput d,\n\toutput reg q);\n\t\n\t/*always @(posedge clk, negedge clk) begin\n\t\tq <= d;\n\tend*/\n\n\treg qp, qn;\n    always @(posedge clk)\n        qp <= d;\n    always @(negedge clk)\n        qn <= d;\n    // assign q = clk ? qp : qn;  // This causes q to change too early when clk changes. Need delay by delta cycle\n    always @(*)\n        q <= clk ? qp : qn;\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg d,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\t\n\t\n\tinitial begin\n\t\td <= 1'b0;\n\t\t@(negedge clk) wavedrom_start();\n\t\t\trepeat(20) @(posedge clk, negedge clk)\n\t\t\t\td <= $random>>2;\n\t\t@(negedge clk) wavedrom_stop();\n\t\trepeat(200) @(posedge clk, negedge clk) begin\n\t\t\td <= $random;\n\t\tend\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_q;\n\t\tint errortime_q;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic d;\n\tlogic q_ref;\n\tlogic q_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,d,q_ref,q_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.d );\n\treference_module good1 (\n\t\t.clk,\n\t\t.d,\n\t\t.q(q_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.d,\n\t\t.q(q_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"q\", stats1.errors_q, stats1.errortime_q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"q\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (q_ref !== ( q_ref ^ q_dut ^ q_ref ))\n\t\tbegin if (stats1.errors_q == 0) stats1.errortime_q = $time;\n\t\t\tstats1.errors_q = stats1.errors_q+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "xnorgate", "task_number": 57, "description": "Create a module that implements an XNOR gate.", "header": "module top_module(\n\tinput a, \n\tinput b,\n\toutput out\n);\n", "module_code": "module top_module(\n\tinput a, \n\tinput b,\n\toutput out\n);\n\t\n\tassign out = ~(a^b);\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput a, \n\tinput b,\n\toutput out\n);\n\t\n\tassign out = ~(a^b);\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg a, b,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\tint count; count = 0;\n\t\t{a,b} <= 1'b0;\n\t\twavedrom_start(\"XNOR gate\");\n\t\trepeat(10) @(posedge clk)\n\t\t\t{a,b} <= count++;\t\t\n\t\twavedrom_stop();\n\t\t\n\t\trepeat(200) @(posedge clk, negedge clk)\n\t\t\t{b,a} <= $random;\n\t\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic a;\n\tlogic b;\n\tlogic out_ref;\n\tlogic out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,a,b,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.a,\n\t\t.b );\n\treference_module good1 (\n\t\t.a,\n\t\t.b,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.a,\n\t\t.b,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "mt2015_q4", "task_number": 58, "description": "Module A implements the boolean function z = (x^y) & x.\n\n// Module B can be described by the following simulation waveform: \n\n// time            x               y               z               \n// 0ns             0               0               1               \n// 5ns             0               0               1               \n// 10ns            0               0               1               \n// 15ns            0               0               1               \n// 20ns            0               0               1               \n// 25ns            1               0               0               \n// 30ns            1               0               0               \n// 35ns            0               1               0               \n// 40ns            0               1               0               \n// 45ns            1               1               1               \n// 50ns            1               1               1               \n// 55ns            0               0               1               \n// 60ns            0               1               0               \n// 65ns            0               1               0               \n// 70ns            1               1               1               \n// 75ns            0               1               0               \n// 80ns            0               1               0               \n// 85ns            0               1               0               \n// 90ns            1               0               0               \n\n\n// Now consider a top-level that uses two A submodules and two B submodules. The first input of all four submodules is connect to input 'x', and the second input of all four submodules is connected to 'y'. The output of the first A submodule is connected to a two-input OR, along with the output of the first B submodule. The second pair of A and B submodules is similarly connected to an AND gate. The output of the OR and the AND is connected to an XOR, whose output is 'z'.\n\n// Implement this circuit in Verilog.", "header": "module top_module(\n\tinput x,\n\tinput y,\n\toutput z);\n", "module_code": "module top_module(\n\tinput x,\n\tinput y,\n\toutput z);\n\n\tassign z = x|~y;\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput x,\n\tinput y,\n\toutput z);\n\n\tassign z = x|~y;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic x,\n\toutput logic y\n);\n\n\talways @(posedge clk, negedge clk)\n\t\t{x, y} <= $random % 4;\n\t\n\tinitial begin\n\t\trepeat(100) @(negedge clk);\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_z;\n\t\tint errortime_z;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic x;\n\tlogic y;\n\tlogic z_ref;\n\tlogic z_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,x,y,z_ref,z_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.x,\n\t\t.y );\n\treference_module good1 (\n\t\t.x,\n\t\t.y,\n\t\t.z(z_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.x,\n\t\t.y,\n\t\t.z(z_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_z) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"z\", stats1.errors_z, stats1.errortime_z);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"z\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { z_ref } === ( { z_ref } ^ { z_dut } ^ { z_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (z_ref !== ( z_ref ^ z_dut ^ z_ref ))\n\t\tbegin if (stats1.errors_z == 0) stats1.errortime_z = $time;\n\t\t\tstats1.errors_z = stats1.errors_z+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "rotate100", "task_number": 59, "description": "Build a 100-bit left/right rotator, with synchronous load and left/right enable. A rotator shifts-in the shifted-out bit from the other end of the register, unlike a shifter that discards the shifted-out bit and shifts in a zero. If enabled, a rotator rotates the bits around and does not modify/discard them. \n// (1) load: Loads shift register with data[99:0] instead of rotating. Synchronous active high.\n// (2) ena[1:0]: Synchronous. Chooses whether and which direction to rotate: \n//     (a) 2'b01 rotates right by one bit, \n//     (b) 2'b10 rotates left by one bit, \n//     (c) 2'b00 and 2'b11 do not rotate. \n// (3) q: The contents of the rotator.", "header": "module top_module(\n\tinput clk,\n\tinput load,\n\tinput [1:0] ena,\n\tinput [99:0] data,\n\toutput reg [99:0] q);\n", "module_code": "module top_module(\n\tinput clk,\n\tinput load,\n\tinput [1:0] ena,\n\tinput [99:0] data,\n\toutput reg [99:0] q);\n\t\n\t\n\talways @(posedge clk) begin\n\t\tif (load)\n\t\t\tq <= data;\n\t\telse if (ena == 2'h1)\n\t\t\tq <= {q[0], q[99:1]};\n\t\telse if (ena == 2'h2)\n\t\t\tq <= {q[98:0], q[99]};\n\tend\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput clk,\n\tinput load,\n\tinput [1:0] ena,\n\tinput [99:0] data,\n\toutput reg [99:0] q);\n\t\n\t\n\talways @(posedge clk) begin\n\t\tif (load)\n\t\t\tq <= data;\n\t\telse if (ena == 2'h1)\n\t\t\tq <= {q[0], q[99:1]};\n\t\telse if (ena == 2'h2)\n\t\t\tq <= {q[98:0], q[99]};\n\tend\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg load,\n\toutput reg[1:0] ena,\n\toutput reg[99:0] data\n);\n\n\talways @(posedge clk)\n\t\tdata <= {$random,$random,$random,$random};\n\t\n\tinitial begin\n\t\tload <= 1;\n\t\t@(posedge clk);\n\t\t@(posedge clk);\n\t\t@(posedge clk);\n\t\trepeat(4000) @(posedge clk, negedge clk) begin\n\t\t\tload <= !($random & 31);\n\t\t\tena <= $random;\n\t\tend\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_q;\n\t\tint errortime_q;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic load;\n\tlogic [1:0] ena;\n\tlogic [99:0] data;\n\tlogic [99:0] q_ref;\n\tlogic [99:0] q_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,load,ena,data,q_ref,q_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.load,\n\t\t.ena,\n\t\t.data );\n\treference_module good1 (\n\t\t.clk,\n\t\t.load,\n\t\t.ena,\n\t\t.data,\n\t\t.q(q_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.load,\n\t\t.ena,\n\t\t.data,\n\t\t.q(q_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"q\", stats1.errors_q, stats1.errortime_q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"q\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (q_ref !== ( q_ref ^ q_dut ^ q_ref ))\n\t\tbegin if (stats1.errors_q == 0) stats1.errortime_q = $time;\n\t\t\tstats1.errors_q = stats1.errors_q+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "review2015_count1k", "task_number": 60, "description": "Build a counter that counts from 0 to 999, inclusive, with a period of 1000 cycles. The reset input is active high synchronous, and should reset the counter to 0.", "header": "module top_module(\n\tinput clk,\n\tinput reset,\n\toutput reg [9:0] q);\n", "module_code": "module top_module(\n\tinput clk,\n\tinput reset,\n\toutput reg [9:0] q);\n\t\n\talways @(posedge clk)\n\t\tif (reset || q == 999)\n\t\t\tq <= 0;\n\t\telse\n\t\t\tq <= q+1;\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput clk,\n\tinput reset,\n\toutput reg [9:0] q);\n\t\n\talways @(posedge clk)\n\t\tif (reset || q == 999)\n\t\t\tq <= 0;\n\t\telse\n\t\t\tq <= q+1;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg reset,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\tinput tb_match\n);\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\tinitial begin\n\t\treset <= 1;\n\t\twavedrom_start(\"Synchronous reset\");\n\t\treset_test();\n\t\trepeat(5) @(posedge clk);\n\t\twavedrom_stop();\n\n\t\treset <= 0;\n\t\t\n\t\trepeat(989) @(negedge clk);\n\t\twavedrom_start(\"Wrap around behaviour\");\n\t\trepeat(14)@(posedge clk);\n\t\twavedrom_stop();\n\t\t\n\t\n\t\t\n\t\trepeat(2000) @(posedge clk, negedge clk) begin\n\t\t\treset <= !($random & 127);\n\t\tend\n\t\treset <= 0;\n\t\trepeat(2000) @(posedge clk);\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_q;\n\t\tint errortime_q;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic reset;\n\tlogic [9:0] q_ref;\n\tlogic [9:0] q_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,q_ref,q_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.reset );\n\treference_module good1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.q(q_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.q(q_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"q\", stats1.errors_q, stats1.errortime_q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"q\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (q_ref !== ( q_ref ^ q_dut ^ q_ref ))\n\t\tbegin if (stats1.errors_q == 0) stats1.errortime_q = $time;\n\t\t\tstats1.errors_q = stats1.errors_q+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "notgate", "task_number": 61, "description": "Create a module that implements a NOT gate.", "header": "module top_module(\n\tinput in,\n\toutput out\n);\n", "module_code": "module top_module(\n\tinput in,\n\toutput out\n);\n\t\n\tassign out = ~in;\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput in,\n\toutput out\n);\n\t\n\tassign out = ~in;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg in,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\tin <= 1'b0;\n\t\twavedrom_start(\"Inversion\");\n\t\trepeat(20) @(posedge clk)\n\t\t\tin <= $random;\t\t\n\t\twavedrom_stop();\n\t\t\n\t\trepeat(200) @(posedge clk, negedge clk)\n\t\t\tin <= $random;\n\t\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic in;\n\tlogic out_ref;\n\tlogic out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,in,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in );\n\treference_module good1 (\n\t\t.in,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.in,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "fsm_onehot", "task_number": 62, "description": "Given the follow state machine with 1 input and 2 outputs (the outputs are given as \"(out1, out2)\"):\n\n// S0 (0, 0) --0--> S0\n// S0 (0, 0) --1--> S1\n// S1 (0, 0) --0--> S0\n// S1 (0, 0) --1--> S2\n// S2 (0, 0) --0--> S0\n// S2 (0, 0) --1--> S3\n// S3 (0, 0) --0--> S0\n// S3 (0, 0) --1--> S4\n// S4 (0, 0) --0--> S0\n// S4 (0, 0) --1--> S5\n// S5 (0, 0) --0--> S8\n// S5 (0, 0) --1--> S6\n// S6 (0, 0) --0--> S9\n// S6 (0, 0) --1--> S7\n// S7 (0, 1) --0--> S0\n// S7 (0, 1) --1--> S7\n// S8 (1, 0) --0--> S0\n// S8 (1, 0) --1--> S1\n// S9 (1, 1) --0--> S0\n// S9 (1, 1) --1--> S1\n\n// Suppose this state machine uses one-hot encoding, where state[0] through state[9] correspond to the states S0 though S9, respectively. The outputs are zero unless otherwise specified.\n\n// Write Verilog implementing the state transition logic and output logic portions of the state machine (but not the state flip-flops). You are given the current state in state[9:0] and must produce next_state[9:0] and the two outputs. Derive the logic equations by inspection assuming a one-hot encoding.", "header": "module top_module (\n\tinput in,\n\tinput [9:0] state,\n\toutput [9:0] next_state,\n\toutput out1,\n\toutput out2);\n", "module_code": "module top_module (\n\tinput in,\n\tinput [9:0] state,\n\toutput [9:0] next_state,\n\toutput out1,\n\toutput out2);\n\t\n\tassign out1 = state[8] | state[9];\n\tassign out2 = state[7] | state[9];\n\n\tassign next_state[0] = !in && (|state[4:0] | state[7] | state[8] | state[9]);\n\tassign next_state[1] = in && (state[0] | state[8] | state[9]);\n\tassign next_state[2] = in && state[1];\n\tassign next_state[3] = in && state[2];\n\tassign next_state[4] = in && state[3];\n\tassign next_state[5] = in && state[4];\n\tassign next_state[6] = in && state[5];\n\tassign next_state[7] = in && (state[6] | state[7]);\n\tassign next_state[8] = !in && state[5];\n\tassign next_state[9] = !in && state[6];\n\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput in,\n\tinput [9:0] state,\n\toutput [9:0] next_state,\n\toutput out1,\n\toutput out2);\n\t\n\tassign out1 = state[8] | state[9];\n\tassign out2 = state[7] | state[9];\n\n\tassign next_state[0] = !in && (|state[4:0] | state[7] | state[8] | state[9]);\n\tassign next_state[1] = in && (state[0] | state[8] | state[9]);\n\tassign next_state[2] = in && state[1];\n\tassign next_state[3] = in && state[2];\n\tassign next_state[4] = in && state[3];\n\tassign next_state[5] = in && state[4];\n\tassign next_state[6] = in && state[5];\n\tassign next_state[7] = in && (state[6] | state[7]);\n\tassign next_state[8] = !in && state[5];\n\tassign next_state[9] = !in && state[6];\n\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic in,\n\toutput logic [9:0] state,\n\tinput tb_match,\n\tinput [9:0] next_state_ref,\n\tinput [9:0] next_state_dut,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tint errored1 = 0;\n\tint errored2 = 0;\n\tint onehot_error = 0;\n\treg [9:0] state_error = 10'h0;\n\t\n\tinitial begin\n\t\trepeat(2) @(posedge clk);\n\t\tforever @(posedge clk, negedge clk)\n\t\t\tstate_error <= state_error | (next_state_ref^next_state_dut);\n\tend\n\t\t\n\tinitial begin\n\t\tstate <= 0;\n\t\t\n\t\t@(negedge clk) wavedrom_start();\n\t\tfor (int i=0;i<10;i++) begin\n\t\t\t@(negedge clk, posedge clk);\n\t\t\tstate <= 1<< i;\n\t\t\tin <= 0;\n\t\tend\n\t\tfor (int i=0;i<10;i++) begin\n\t\t\t@(negedge clk, posedge clk);\n\t\t\tstate <= 1<< i;\n\t\t\tin <= 1;\n\t\tend\t\t\t\n\t\t@(negedge clk) wavedrom_stop();\n\t\t\n\t\t// Test the one-hot cases first.\n\t\trepeat(200) @(posedge clk, negedge clk) begin\n\t\t\tstate <= 1<< ($unsigned($random) % 10);\n\t\t\tin <= $random;\n\t\t\tif (!tb_match) onehot_error++;\n\t\tend\n\t\t\n\t\t// Two-hot.\n\t\terrored1 = 0;\n\t\trepeat(400) @(posedge clk, negedge clk) begin\n\t\t\tstate <= (1<< ($unsigned($random) % 10)) | (1<< ($unsigned($random) % 10));\n\t\t\tin <= $random;\n\t\t\tif (!tb_match)\n\t\t\t\terrored1++;\n\t\tend\n\t\t\n\t\tif (!onehot_error && errored1) \n\t\t\t$display (\"Hint: Your circuit passed when given only one-hot inputs, but not with two-hot inputs.\");\n\t\t\n\t\t// Random.\n\t\terrored2 = 0;\n\t\trepeat(800) @(posedge clk, negedge clk) begin\n\t\t\tstate <= $random;\n\t\t\tin <= $random;\n\t\t\tif (!tb_match)\n\t\t\t\terrored2++;\n\t\tend\n\t\tif (!onehot_error && errored2) \n\t\t\t$display (\"Hint: Your circuit passed when given only one-hot inputs, but not with random inputs.\");\n\n\t\tif (!onehot_error && (errored1 || errored2))\n\t\t\t$display(\"Hint: Are you doing something more complicated than deriving state transition equations by inspection?\\n\");\n\t\t\n\t\tfor (int i=0;i<$bits(state_error);i++)\n\t\t\t$display(\"Hint: next_state[%0d] is %s.\", i, (state_error[i] === 1'b0) ? \"correct\": \"incorrect\");\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_next_state;\n\t\tint errortime_next_state;\n\t\tint errors_out1;\n\t\tint errortime_out1;\n\t\tint errors_out2;\n\t\tint errortime_out2;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic in;\n\tlogic [9:0] state;\n\tlogic [9:0] next_state_ref;\n\tlogic [9:0] next_state_dut;\n\tlogic out1_ref;\n\tlogic out1_dut;\n\tlogic out2_ref;\n\tlogic out2_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,in,state,next_state_ref,next_state_dut,out1_ref,out1_dut,out2_ref,out2_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in,\n\t\t.state );\n\treference_module good1 (\n\t\t.in,\n\t\t.state,\n\t\t.next_state(next_state_ref),\n\t\t.out1(out1_ref),\n\t\t.out2(out2_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.in,\n\t\t.state,\n\t\t.next_state(next_state_dut),\n\t\t.out1(out1_dut),\n\t\t.out2(out2_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_next_state) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"next_state\", stats1.errors_next_state, stats1.errortime_next_state);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"next_state\");\n\t\tif (stats1.errors_out1) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out1\", stats1.errors_out1, stats1.errortime_out1);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out1\");\n\t\tif (stats1.errors_out2) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out2\", stats1.errors_out2, stats1.errortime_out2);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out2\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { next_state_ref, out1_ref, out2_ref } === ( { next_state_ref, out1_ref, out2_ref } ^ { next_state_dut, out1_dut, out2_dut } ^ { next_state_ref, out1_ref, out2_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (next_state_ref !== ( next_state_ref ^ next_state_dut ^ next_state_ref ))\n\t\tbegin if (stats1.errors_next_state == 0) stats1.errortime_next_state = $time;\n\t\t\tstats1.errors_next_state = stats1.errors_next_state+1'b1; end\n\t\tif (out1_ref !== ( out1_ref ^ out1_dut ^ out1_ref ))\n\t\tbegin if (stats1.errors_out1 == 0) stats1.errortime_out1 = $time;\n\t\t\tstats1.errors_out1 = stats1.errors_out1+1'b1; end\n\t\tif (out2_ref !== ( out2_ref ^ out2_dut ^ out2_ref ))\n\t\tbegin if (stats1.errors_out2 == 0) stats1.errortime_out2 = $time;\n\t\t\tstats1.errors_out2 = stats1.errors_out2+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "ece241_2013_q7", "task_number": 63, "description": "A JK flip-flop has the below truth table. Note: Qold is the output of the flip-flop before the positive clock edge.\n// J | K | Q\n// 0 | 0 | Qold\n// 0 | 1 | 0\n// 1 | 0 | 1\n// 1 | 1 | ~Qold", "header": "module top_module (\n\tinput clk,\n\tinput j,\n\tinput k,\n\toutput reg Q\n);\n", "module_code": "module top_module (\n\tinput clk,\n\tinput j,\n\tinput k,\n\toutput reg Q\n);\n\n\talways @(posedge clk)\n\t\tQ <= j&~Q | ~k&Q;\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput j,\n\tinput k,\n\toutput reg Q\n);\n\n\talways @(posedge clk)\n\t\tQ <= j&~Q | ~k&Q;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic j, k,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\n);\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\t{j,k} <= 1;\n\t\t\n\t\t@(negedge clk) wavedrom_start();\n\t\t\t@(posedge clk) {j,k} <= 2'h1;\n\t\t\t@(posedge clk) {j,k} <= 2'h2;\n\t\t\t@(posedge clk) {j,k} <= 2'h3;\n\t\t\t@(posedge clk) {j,k} <= 2'h3;\n\t\t\t@(posedge clk) {j,k} <= 2'h3;\n\t\t\t@(posedge clk) {j,k} <= 2'h0;\n\t\t\t@(posedge clk) {j,k} <= 2'h0;\n\t\t\t@(posedge clk) {j,k} <= 2'h0;\n\t\t\t@(posedge clk) {j,k} <= 2'h2;\n\t\t\t@(posedge clk) {j,k} <= 2'h2;\n\t\t@(negedge clk) wavedrom_stop();\n\t\trepeat(400) @(posedge clk, negedge clk)\n\t\t\t{j,k} <= $random;\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_Q;\n\t\tint errortime_Q;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic j;\n\tlogic k;\n\tlogic Q_ref;\n\tlogic Q_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,j,k,Q_ref,Q_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.j,\n\t\t.k );\n\treference_module good1 (\n\t\t.clk,\n\t\t.j,\n\t\t.k,\n\t\t.Q(Q_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.j,\n\t\t.k,\n\t\t.Q(Q_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_Q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"Q\", stats1.errors_Q, stats1.errortime_Q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"Q\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { Q_ref } === ( { Q_ref } ^ { Q_dut } ^ { Q_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (Q_ref !== ( Q_ref ^ Q_dut ^ Q_ref ))\n\t\tbegin if (stats1.errors_Q == 0) stats1.errortime_Q = $time;\n\t\t\tstats1.errors_Q = stats1.errors_Q+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "popcount3", "task_number": 64, "description": "A \"population count\" circuit counts the number of '1's in an input vector. Build a population count circuit for a 3-bit input vector.", "header": "module top_module (\n\tinput [2:0] in,\n\toutput [1:0] out\n);\n", "module_code": "module top_module (\n\tinput [2:0] in,\n\toutput [1:0] out\n);\n\n\tassign out = in[0]+in[1]+in[2];\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [2:0] in,\n\toutput [1:0] out\n);\n\n\tassign out = in[0]+in[1]+in[2];\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic [2:0] in,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\t\n\tinitial begin\n\t\tin <= 7;\n\t\t@(negedge clk);\n\t\twavedrom_start();\n\t\t\trepeat(9) @(posedge clk) in <= in + 1'b1;\n\t\t@(negedge clk);\n\t\twavedrom_stop();\n\t\trepeat(200) @(posedge clk, negedge clk)\n\t\t\tin <= $random;\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [2:0] in;\n\tlogic [1:0] out_ref;\n\tlogic [1:0] out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,in,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in );\n\treference_module good1 (\n\t\t.in,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.in,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "vector5", "task_number": 65, "description": "Given five 1-bit signals (a, b, c, d, and e), compute all 25 pairwise one-bit comparisons in the 25-bit output vector. The output should be 1 if the two bits being compared are equal. Example: out[24] = ~a ^ a; out[23] = ~a ^ b; out[22] = ~a ^ c; ... out[ 1] = ~e ^ d; out[ 0] = ~e ^ e.", "header": "module top_module (\n\tinput a,\n\tinput b,\n\tinput c,\n\tinput d,\n\tinput e,\n\toutput [24:0] out\n);\n", "module_code": "module top_module (\n\tinput a,\n\tinput b,\n\tinput c,\n\tinput d,\n\tinput e,\n\toutput [24:0] out\n);\n\n\tassign out = ~{ {5{a}}, {5{b}}, {5{c}}, {5{d}}, {5{e}} } ^ {5{a,b,c,d,e}};\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput a,\n\tinput b,\n\tinput c,\n\tinput d,\n\tinput e,\n\toutput [24:0] out\n);\n\n\tassign out = ~{ {5{a}}, {5{b}}, {5{c}}, {5{d}}, {5{e}} } ^ {5{a,b,c,d,e}};\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic a, b, c, d, e\n);\n\n\tinitial begin\n\t\trepeat(100) @(posedge clk, negedge clk)\n\t\t\t{a,b,c,d,e} <= $random;\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic a;\n\tlogic b;\n\tlogic c;\n\tlogic d;\n\tlogic e;\n\tlogic [24:0] out_ref;\n\tlogic [24:0] out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,a,b,c,d,e,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d,\n\t\t.e );\n\treference_module good1 (\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d,\n\t\t.e,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d,\n\t\t.e,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "lemmings1", "task_number": 66, "description": "The game Lemmings involves critters with fairly simple brains. So simple that we are going to model it using a finite state machine. In the Lemmings' 2D world, Lemmings can be in one of two states: walking left (walk_left is 1) or walking right (walk_right is 1). It will switch directions if it hits an obstacle. In particular, if a Lemming is bumped on the left (by receiving a 1 on bump_left), it will walk right. If it's bumped on the right (by receiving a 1 on bump_right), it will walk left. If it's bumped on both sides at the same time, it will still switch directions. Implement a Moore state machine with two states, two inputs, and one output (internal to the module) that models this behaviour. areset is positive edge triggered asynchronous reseting the Lemming machine to walk left.", "header": "module top_module (\n\tinput clk,\n\tinput areset,\n\tinput bump_left,\n\tinput bump_right,\n\toutput walk_left,\n\toutput walk_right\n);\n", "module_code": "module top_module (\n\tinput clk,\n\tinput areset,\n\tinput bump_left,\n\tinput bump_right,\n\toutput walk_left,\n\toutput walk_right\n);\n\tparameter WL=0, WR=1;\n\treg state;\n\treg next;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tWL: next = bump_left ? WR : WL;\n\t\t\tWR: next = bump_right ? WL: WR;\n\t\tendcase\n    end\n    \n    always @(posedge clk, posedge areset) begin\n\t\tif (areset) state <= WL;\n        else state <= next;\n\tend\n\t\t\n\tassign walk_left = (state==WL);\n\tassign walk_right = (state==WR);\n\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput areset,\n\tinput bump_left,\n\tinput bump_right,\n\toutput walk_left,\n\toutput walk_right\n);\n\tparameter WL=0, WR=1;\n\treg state;\n\treg next;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tWL: next = bump_left ? WR : WL;\n\t\t\tWR: next = bump_right ? WL: WR;\n\t\tendcase\n    end\n    \n    always @(posedge clk, posedge areset) begin\n\t\tif (areset) state <= WL;\n        else state <= next;\n\tend\n\t\t\n\tassign walk_left = (state==WL);\n\tassign walk_right = (state==WR);\n\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic areset,\n\toutput logic bump_left,\n\toutput logic bump_right,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\tinput tb_match\n);\n\treg reset;\n\tassign areset = reset;\n\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\t\n\tinitial begin\n\t\treset <= 1'b1;\n\t\t{bump_right, bump_left} <= 3'h3;\n\t\twavedrom_start(\"Asynchronous reset\");\n\t\treset_test(1);\n\t\trepeat(3) @(posedge clk);\n\t\t{bump_right, bump_left} <= 2;\n\t\trepeat(2) @(posedge clk);\n\t\t{bump_right, bump_left} <= 1;\n\t\trepeat(2) @(posedge clk);\n\t\twavedrom_stop();\n\t\t\n\t\t@(posedge clk);\n\t\trepeat(200) @(posedge clk, negedge clk) begin\n\t\t\t{bump_right, bump_left} <= $random & $random;\n\t\t\treset <= !($random & 31);\n\t\tend\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_walk_left;\n\t\tint errortime_walk_left;\n\t\tint errors_walk_right;\n\t\tint errortime_walk_right;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic areset;\n\tlogic bump_left;\n\tlogic bump_right;\n\tlogic walk_left_ref;\n\tlogic walk_left_dut;\n\tlogic walk_right_ref;\n\tlogic walk_right_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,areset,bump_left,bump_right,walk_left_ref,walk_left_dut,walk_right_ref,walk_right_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.areset,\n\t\t.bump_left,\n\t\t.bump_right );\n\treference_module good1 (\n\t\t.clk,\n\t\t.areset,\n\t\t.bump_left,\n\t\t.bump_right,\n\t\t.walk_left(walk_left_ref),\n\t\t.walk_right(walk_right_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.areset,\n\t\t.bump_left,\n\t\t.bump_right,\n\t\t.walk_left(walk_left_dut),\n\t\t.walk_right(walk_right_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_walk_left) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"walk_left\", stats1.errors_walk_left, stats1.errortime_walk_left);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"walk_left\");\n\t\tif (stats1.errors_walk_right) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"walk_right\", stats1.errors_walk_right, stats1.errortime_walk_right);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"walk_right\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { walk_left_ref, walk_right_ref } === ( { walk_left_ref, walk_right_ref } ^ { walk_left_dut, walk_right_dut } ^ { walk_left_ref, walk_right_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (walk_left_ref !== ( walk_left_ref ^ walk_left_dut ^ walk_left_ref ))\n\t\tbegin if (stats1.errors_walk_left == 0) stats1.errortime_walk_left = $time;\n\t\t\tstats1.errors_walk_left = stats1.errors_walk_left+1'b1; end\n\t\tif (walk_right_ref !== ( walk_right_ref ^ walk_right_dut ^ walk_right_ref ))\n\t\tbegin if (stats1.errors_walk_right == 0) stats1.errortime_walk_right = $time;\n\t\t\tstats1.errors_walk_right = stats1.errors_walk_right+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "circuit1", "task_number": 67, "description": "This is a combinational circuit. Read the simulation waveforms to determine what the circuit does, then implement it.\n\n// time            a               b               q               \n// 0ns             0               0               0               \n// 5ns             0               0               0               \n// 10ns            0               0               0               \n// 15ns            0               0               0               \n// 20ns            0               0               0               \n// 25ns            0               1               0               \n// 30ns            0               1               0               \n// 35ns            1               0               0               \n// 40ns            1               0               0               \n// 45ns            1               1               1               \n// 50ns            1               1               1               \n// 55ns            0               0               0               \n// 60ns            0               0               0               \n// 65ns            0               1               0               \n// 70ns            0               1               0               \n// 75ns            1               0               0               \n// 80ns            1               0               0               \n// 85ns            1               1               1               \n// 90ns            1               1               1               \n", "header": "module top_module (\n\tinput a, \n\tinput b, \n\toutput q\n);\n", "module_code": "module top_module (\n\tinput a, \n\tinput b, \n\toutput q\n);\n\n\tassign q = a&b;\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput a, \n\tinput b, \n\toutput q\n);\n\n\tassign q = a&b;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic a,b,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\t{a,b} <= 0;\n\t\t@(negedge clk) wavedrom_start(\"Unknown circuit\");\n\t\t\t@(posedge clk) {a,b} <= 0;\n\t\t\trepeat(8) @(posedge clk) {a,b} <= {a,b} + 1;\n\t\t@(negedge clk) wavedrom_stop();\n\t\t\n\t\trepeat(100) @(posedge clk, negedge clk)\n\t\t\t{a,b} <= $urandom;\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_q;\n\t\tint errortime_q;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic a;\n\tlogic b;\n\tlogic q_ref;\n\tlogic q_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,a,b,q_ref,q_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.a,\n\t\t.b );\n\treference_module good1 (\n\t\t.a,\n\t\t.b,\n\t\t.q(q_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.a,\n\t\t.b,\n\t\t.q(q_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"q\", stats1.errors_q, stats1.errortime_q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"q\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (q_ref !== ( q_ref ^ q_dut ^ q_ref ))\n\t\tbegin if (stats1.errors_q == 0) stats1.errortime_q = $time;\n\t\t\tstats1.errors_q = stats1.errors_q+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "7458", "task_number": 68, "description": "The 7458 is a chip with four AND gates and two OR gates. Create a module in Verilog with the same functionality as the 7458 chip. It has 10 inputs and 2 outputs. You may choose to use an `assign` statement to drive each of the output wires, or you may choose to declare (four) wires for use as intermediate signals, where each internal wire is driven by the output of one of the AND gates.\n\n// In this circuit, p1y should be the OR of two 3-input AND gates: one that ANDs p1a, p1b, and p1c, and the second that ANDs p1d, p1e, and p1f. The output p2y is the OR of two 2-input AND gates: one that ANDs p2a and p2b, and the second that ANDs p2c and p2d.", "header": "module top_module(\n\tinput p1a, \n\tinput p1b, \n\tinput p1c, \n\tinput p1d,\n\tinput p1e,\n\tinput p1f,\n\toutput p1y, \n\tinput p2a, \n\tinput p2b, \n\tinput p2c, \n\tinput p2d, \n\toutput p2y\n);\n", "module_code": "module top_module(\n\tinput p1a, \n\tinput p1b, \n\tinput p1c, \n\tinput p1d,\n\tinput p1e,\n\tinput p1f,\n\toutput p1y, \n\tinput p2a, \n\tinput p2b, \n\tinput p2c, \n\tinput p2d, \n\toutput p2y\n);\n\t\n\tassign p1y = &{p1a, p1b, p1c} | &{p1d, p1e, p1f};\n\tassign p2y = &{p2a, p2b} | &{p2c, p2d};\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput p1a, \n\tinput p1b, \n\tinput p1c, \n\tinput p1d,\n\tinput p1e,\n\tinput p1f,\n\toutput p1y, \n\tinput p2a, \n\tinput p2b, \n\tinput p2c, \n\tinput p2d, \n\toutput p2y\n);\n\t\n\tassign p1y = &{p1a, p1b, p1c} | &{p1d, p1e, p1f};\n\tassign p2y = &{p2a, p2b} | &{p2c, p2d};\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg p1a, p1b, p1c, p1d, p1e, p1f,\n\toutput reg p2a, p2b, p2c, p2d,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\tint count; count = 0;\n\t\t{p1a,p1b,p1c,p1d,p1e,p1f} <= 4'h0;\t\t\n\t\t{p2a,p2b,p2c,p2d} <= 4'h0;\t\t\n\t\twavedrom_start();\n\t\trepeat(20) @(posedge clk) begin\n\t\t\t{p1a,p1b,p1c,p1d,p1e,p1f} <= {count[2:0], count[3:1]};\t\t\n\t\t\t{p2a,p2b,p2c,p2d} <= count;\t\t\n\t\t\tcount = count + 1;\n\t\tend\n\t\twavedrom_stop();\n\n\t\trepeat(400) @(posedge clk,negedge clk) begin\n\t\t\t{p1a,p1b,p1c,p1d,p2a,p2b,p2c,p2d} <= $random;\t\t\n\t\tend\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_p1y;\n\t\tint errortime_p1y;\n\t\tint errors_p2y;\n\t\tint errortime_p2y;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic p1a;\n\tlogic p1b;\n\tlogic p1c;\n\tlogic p1d;\n\tlogic p1e;\n\tlogic p1f;\n\tlogic p2a;\n\tlogic p2b;\n\tlogic p2c;\n\tlogic p2d;\n\tlogic p1y_ref;\n\tlogic p1y_dut;\n\tlogic p2y_ref;\n\tlogic p2y_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,p1a,p1b,p1c,p1d,p1e,p1f,p2a,p2b,p2c,p2d,p1y_ref,p1y_dut,p2y_ref,p2y_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.p1a,\n\t\t.p1b,\n\t\t.p1c,\n\t\t.p1d,\n\t\t.p1e,\n\t\t.p1f,\n\t\t.p2a,\n\t\t.p2b,\n\t\t.p2c,\n\t\t.p2d );\n\treference_module good1 (\n\t\t.p1a,\n\t\t.p1b,\n\t\t.p1c,\n\t\t.p1d,\n\t\t.p1e,\n\t\t.p1f,\n\t\t.p2a,\n\t\t.p2b,\n\t\t.p2c,\n\t\t.p2d,\n\t\t.p1y(p1y_ref),\n\t\t.p2y(p2y_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.p1a,\n\t\t.p1b,\n\t\t.p1c,\n\t\t.p1d,\n\t\t.p1e,\n\t\t.p1f,\n\t\t.p2a,\n\t\t.p2b,\n\t\t.p2c,\n\t\t.p2d,\n\t\t.p1y(p1y_dut),\n\t\t.p2y(p2y_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_p1y) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"p1y\", stats1.errors_p1y, stats1.errortime_p1y);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"p1y\");\n\t\tif (stats1.errors_p2y) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"p2y\", stats1.errors_p2y, stats1.errortime_p2y);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"p2y\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { p1y_ref, p2y_ref } === ( { p1y_ref, p2y_ref } ^ { p1y_dut, p2y_dut } ^ { p1y_ref, p2y_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (p1y_ref !== ( p1y_ref ^ p1y_dut ^ p1y_ref ))\n\t\tbegin if (stats1.errors_p1y == 0) stats1.errortime_p1y = $time;\n\t\t\tstats1.errors_p1y = stats1.errors_p1y+1'b1; end\n\t\tif (p2y_ref !== ( p2y_ref ^ p2y_dut ^ p2y_ref ))\n\t\tbegin if (stats1.errors_p2y == 0) stats1.errortime_p2y = $time;\n\t\t\tstats1.errors_p2y = stats1.errors_p2y+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "2014_q3c", "task_number": 69, "description": "Given the state-assigned table shown below, implement the logic functions Y[0] and z.\n// Present state y[2:0] | Next state Y[2:0] x=0, Next state Y[2:0] x=1 | Output z\n// 000 | 000, 001 | 0\n// 001 | 001, 100 | 0\n// 010 | 010, 001 | 0\n// 011 | 001, 010 | 1\n// 100 | 011, 100 | 1\n", "header": "module top_module (\n\tinput clk,\n\tinput x,\n\tinput [2:0] y,\n\toutput reg Y0,\n\toutput reg z\n);\n", "module_code": "module top_module (\n\tinput clk,\n\tinput x,\n\tinput [2:0] y,\n\toutput reg Y0,\n\toutput reg z\n);\n\n\talways @(*) begin\n\t\tcase ({y[2:0], x})\n\t\t\t4'h0: Y0 = 0;\n\t\t\t4'h1: Y0 = 1;\n\t\t\t4'h2: Y0 = 1;\n\t\t\t4'h3: Y0 = 0;\n\t\t\t4'h4: Y0 = 0;\n\t\t\t4'h5: Y0 = 1;\n\t\t\t4'h6: Y0 = 1;\n\t\t\t4'h7: Y0 = 0;\n\t\t\t4'h8: Y0 = 1;\n\t\t\t4'h9: Y0 = 0;\n\t\t\tdefault: Y0 = 1'bx;\n\t\tendcase\n\t\t\n\t\tcase (y[2:0])\n\t\t\t3'h0: z = 0;\n\t\t\t3'h1: z = 0;\n\t\t\t3'h2: z = 0;\n\t\t\t3'h3: z = 1;\n\t\t\t3'h4: z = 1;\n\t\t\tdefault: z = 1'bx;\n\t\tendcase\n\tend\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput x,\n\tinput [2:0] y,\n\toutput reg Y0,\n\toutput reg z\n);\n\n\talways_comb begin\n\t\tcase ({y[2:0], x})\n\t\t\t4'h0: Y0 = 0;\n\t\t\t4'h1: Y0 = 1;\n\t\t\t4'h2: Y0 = 1;\n\t\t\t4'h3: Y0 = 0;\n\t\t\t4'h4: Y0 = 0;\n\t\t\t4'h5: Y0 = 1;\n\t\t\t4'h6: Y0 = 1;\n\t\t\t4'h7: Y0 = 0;\n\t\t\t4'h8: Y0 = 1;\n\t\t\t4'h9: Y0 = 0;\n\t\t\tdefault: Y0 = 1'bx;\n\t\tendcase\n\t\t\n\t\tcase (y[2:0])\n\t\t\t3'h0: z = 0;\n\t\t\t3'h1: z = 0;\n\t\t\t3'h2: z = 0;\n\t\t\t3'h3: z = 1;\n\t\t\t3'h4: z = 1;\n\t\t\tdefault: z = 1'bx;\n\t\tendcase\n\tend\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic x,\n\toutput logic [2:0] y\n);\n\n\tinitial begin\n\t\trepeat(200) @(posedge clk, negedge clk) begin\n\t\t\ty <= $random;\n\t\t\tx <= $random;\n\t\tend\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_Y0;\n\t\tint errortime_Y0;\n\t\tint errors_z;\n\t\tint errortime_z;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic x;\n\tlogic [2:0] y;\n\tlogic Y0_ref;\n\tlogic Y0_dut;\n\tlogic z_ref;\n\tlogic z_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,x,y,Y0_ref,Y0_dut,z_ref,z_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.x,\n\t\t.y );\n\treference_module good1 (\n\t\t.clk,\n\t\t.x,\n\t\t.y,\n\t\t.Y0(Y0_ref),\n\t\t.z(z_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.x,\n\t\t.y,\n\t\t.Y0(Y0_dut),\n\t\t.z(z_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_Y0) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"Y0\", stats1.errors_Y0, stats1.errortime_Y0);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"Y0\");\n\t\tif (stats1.errors_z) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"z\", stats1.errors_z, stats1.errortime_z);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"z\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { Y0_ref, z_ref } === ( { Y0_ref, z_ref } ^ { Y0_dut, z_dut } ^ { Y0_ref, z_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (Y0_ref !== ( Y0_ref ^ Y0_dut ^ Y0_ref ))\n\t\tbegin if (stats1.errors_Y0 == 0) stats1.errortime_Y0 = $time;\n\t\t\tstats1.errors_Y0 = stats1.errors_Y0+1'b1; end\n\t\tif (z_ref !== ( z_ref ^ z_dut ^ z_ref ))\n\t\tbegin if (stats1.errors_z == 0) stats1.errortime_z = $time;\n\t\t\tstats1.errors_z = stats1.errors_z+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "m2014_q4e", "task_number": 70, "description": "Implement a 2-input NOR gate.", "header": "module top_module (\n\tinput in1,\n\tinput in2,\n\toutput logic out\n);\n", "module_code": "module top_module (\n\tinput in1,\n\tinput in2,\n\toutput logic out\n);\n\n\tassign out = ~(in1 | in2);\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput in1,\n\tinput in2,\n\toutput logic out\n);\n\n\tassign out = ~(in1 | in2);\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic in1, in2\n);\n\n\tinitial begin\n\t\trepeat(100) @(posedge clk, negedge clk) begin\n\t\t\t{in1, in2} <= $random;\n\t\tend\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic in1;\n\tlogic in2;\n\tlogic out_ref;\n\tlogic out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,in1,in2,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in1,\n\t\t.in2 );\n\treference_module good1 (\n\t\t.in1,\n\t\t.in2,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.in1,\n\t\t.in2,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "wire4", "task_number": 71, "description": "Create a module with 3 inputs and 4 outputs that behaves like wires that makes these connections: a -> w\n// ; b -> x; b -> y; c -> z.", "header": "module top_module (\n\tinput a,\n\tinput b,\n\tinput c,\n\toutput w,\n\toutput x,\n\toutput y,\n\toutput z  );\n", "module_code": "module top_module (\n\tinput a,\n\tinput b,\n\tinput c,\n\toutput w,\n\toutput x,\n\toutput y,\n\toutput z  );\n\t\n\tassign {w,x,y,z} = {a,b,b,c};\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput a,\n\tinput b,\n\tinput c,\n\toutput w,\n\toutput x,\n\toutput y,\n\toutput z  );\n\t\n\tassign {w,x,y,z} = {a,b,b,c};\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic a, b, c,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\talways @(posedge clk, negedge clk)\n\t\t{a,b,c} <= $random;\n\t\n\tinitial begin\n\t\t@(negedge clk) wavedrom_start();\n\t\t\trepeat(8) @(posedge clk);\n\t\t@(negedge clk) wavedrom_stop();\n\t\trepeat(100) @(negedge clk);\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_w;\n\t\tint errortime_w;\n\t\tint errors_x;\n\t\tint errortime_x;\n\t\tint errors_y;\n\t\tint errortime_y;\n\t\tint errors_z;\n\t\tint errortime_z;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic a;\n\tlogic b;\n\tlogic c;\n\tlogic w_ref;\n\tlogic w_dut;\n\tlogic x_ref;\n\tlogic x_dut;\n\tlogic y_ref;\n\tlogic y_dut;\n\tlogic z_ref;\n\tlogic z_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,a,b,c,w_ref,w_dut,x_ref,x_dut,y_ref,y_dut,z_ref,z_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.a,\n\t\t.b,\n\t\t.c );\n\treference_module good1 (\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.w(w_ref),\n\t\t.x(x_ref),\n\t\t.y(y_ref),\n\t\t.z(z_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.w(w_dut),\n\t\t.x(x_dut),\n\t\t.y(y_dut),\n\t\t.z(z_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_w) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"w\", stats1.errors_w, stats1.errortime_w);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"w\");\n\t\tif (stats1.errors_x) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"x\", stats1.errors_x, stats1.errortime_x);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"x\");\n\t\tif (stats1.errors_y) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"y\", stats1.errors_y, stats1.errortime_y);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"y\");\n\t\tif (stats1.errors_z) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"z\", stats1.errors_z, stats1.errortime_z);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"z\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { w_ref, x_ref, y_ref, z_ref } === ( { w_ref, x_ref, y_ref, z_ref } ^ { w_dut, x_dut, y_dut, z_dut } ^ { w_ref, x_ref, y_ref, z_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (w_ref !== ( w_ref ^ w_dut ^ w_ref ))\n\t\tbegin if (stats1.errors_w == 0) stats1.errortime_w = $time;\n\t\t\tstats1.errors_w = stats1.errors_w+1'b1; end\n\t\tif (x_ref !== ( x_ref ^ x_dut ^ x_ref ))\n\t\tbegin if (stats1.errors_x == 0) stats1.errortime_x = $time;\n\t\t\tstats1.errors_x = stats1.errors_x+1'b1; end\n\t\tif (y_ref !== ( y_ref ^ y_dut ^ y_ref ))\n\t\tbegin if (stats1.errors_y == 0) stats1.errortime_y = $time;\n\t\t\tstats1.errors_y = stats1.errors_y+1'b1; end\n\t\tif (z_ref !== ( z_ref ^ z_dut ^ z_ref ))\n\t\tbegin if (stats1.errors_z == 0) stats1.errortime_z = $time;\n\t\t\tstats1.errors_z = stats1.errors_z+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "m2014_q4b", "task_number": 72, "description": "Implement a D flip flop, positive edge triggered, with an asynchronous reset \"ar\".", "header": "module top_module (\n\tinput clk,\n\tinput d,\n\tinput ar,\n\toutput logic q\n);\n", "module_code": "module top_module (\n\tinput clk,\n\tinput d,\n\tinput ar,\n\toutput logic q\n);\n\n\talways@(posedge clk or posedge ar) begin\n\t\tif (ar)\n\t\t\tq <= 0;\n\t\telse\n\t\t\tq <= d;\n\tend\n\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput d,\n\tinput ar,\n\toutput logic q\n);\n\n\talways@(posedge clk or posedge ar) begin\n\t\tif (ar)\n\t\t\tq <= 0;\n\t\telse\n\t\t\tq <= d;\n\tend\n\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic d, ar\n);\n\n\tinitial begin\n\t\trepeat(100) @(posedge clk, negedge clk) begin\n\t\t\t{d,ar} <= $random;\n\t\tend\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_q;\n\t\tint errortime_q;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic d;\n\tlogic ar;\n\tlogic q_ref;\n\tlogic q_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,d,ar,q_ref,q_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.d,\n\t\t.ar );\n\treference_module good1 (\n\t\t.clk,\n\t\t.d,\n\t\t.ar,\n\t\t.q(q_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.d,\n\t\t.ar,\n\t\t.q(q_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"q\", stats1.errors_q, stats1.errortime_q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"q\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (q_ref !== ( q_ref ^ q_dut ^ q_ref ))\n\t\tbegin if (stats1.errors_q == 0) stats1.errortime_q = $time;\n\t\t\tstats1.errors_q = stats1.errors_q+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "always_case", "task_number": 73, "description": "Create a 6-to-1 multiplexer. When sel is between 0 and 5, choose the corresponding data input. Otherwise, output 0. The data inputs and outputs are all 4 bits wide.", "header": "module top_module (\n\tinput [2:0] sel,\n\tinput [3:0] data0,\n\tinput [3:0] data1,\n\tinput [3:0] data2,\n\tinput [3:0] data3,\n\tinput [3:0] data4,\n\tinput [3:0] data5,\n\toutput reg [3:0] out\n);\n", "module_code": "module top_module (\n\tinput [2:0] sel,\n\tinput [3:0] data0,\n\tinput [3:0] data1,\n\tinput [3:0] data2,\n\tinput [3:0] data3,\n\tinput [3:0] data4,\n\tinput [3:0] data5,\n\toutput reg [3:0] out\n);\n\n\talways @(*) begin\n\t\tcase (sel)\n\t\t\t3'h0: out = data0;\n\t\t\t3'h1: out = data1;\n\t\t\t3'h2: out = data2;\n\t\t\t3'h3: out = data3;\n\t\t\t3'h4: out = data4;\n\t\t\t3'h5: out = data5;\n\t\t\tdefault: out = 4'b0;\n\t\tendcase\n\tend\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [2:0] sel,\n\tinput [3:0] data0,\n\tinput [3:0] data1,\n\tinput [3:0] data2,\n\tinput [3:0] data3,\n\tinput [3:0] data4,\n\tinput [3:0] data5,\n\toutput reg [3:0] out\n);\n\n\talways @(*) begin\n\t\tcase (sel)\n\t\t\t3'h0: out = data0;\n\t\t\t3'h1: out = data1;\n\t\t\t3'h2: out = data2;\n\t\t\t3'h3: out = data3;\n\t\t\t3'h4: out = data4;\n\t\t\t3'h5: out = data5;\n\t\t\tdefault: out = 4'b0;\n\t\tendcase\n\tend\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic [2:0] sel, \n\toutput logic [3:0] data0,\n\toutput logic [3:0] data1,\n\toutput logic [3:0] data2,\n\toutput logic [3:0] data3,\n\toutput logic [3:0] data4,\n\toutput logic [3:0] data5,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\tdata0 <= 4'ha;\n\t\tdata1 <= 4'hb;\n\t\tdata2 <= 4'hc;\n\t\tdata3 <= 4'hd;\n\t\tdata4 <= 4'he;\n\t\tdata5 <= 4'hf;\n\t\t{sel} <= 3'b111;\n\t\t@(negedge clk) wavedrom_start(\"<b>Sel</b> chooses one of the data inputs\");\n\t\t\trepeat(8) @(posedge clk) sel <= sel + 1;\n\t\t@(negedge clk) wavedrom_stop();\n\n\t\trepeat(100) @(posedge clk, negedge clk) begin\n\t\t\t{data0, data1, data2, data3} <= $urandom;\n\t\t\t{data4, data5, sel} <= $urandom;\n\t\tend\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [2:0] sel;\n\tlogic [3:0] data0;\n\tlogic [3:0] data1;\n\tlogic [3:0] data2;\n\tlogic [3:0] data3;\n\tlogic [3:0] data4;\n\tlogic [3:0] data5;\n\tlogic [3:0] out_ref;\n\tlogic [3:0] out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,sel,data0,data1,data2,data3,data4,data5,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.sel,\n\t\t.data0,\n\t\t.data1,\n\t\t.data2,\n\t\t.data3,\n\t\t.data4,\n\t\t.data5 );\n\treference_module good1 (\n\t\t.sel,\n\t\t.data0,\n\t\t.data1,\n\t\t.data2,\n\t\t.data3,\n\t\t.data4,\n\t\t.data5,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.sel,\n\t\t.data0,\n\t\t.data1,\n\t\t.data2,\n\t\t.data3,\n\t\t.data4,\n\t\t.data5,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "timer", "task_number": 74, "description": "Implement a timer that counts down for a given number of clock cycles, then asserts a signal to indicate that the given duration has elapsed. A good way to implement this is with a down-counter that asserts an output signal when the count becomes 0. At each clock cycle: \n// (1) If load = 1, load the internal counter with the 10-bit data, the number of clock cycles the timer should count before timing out. The counter can be loaded at any time, including when it is still counting and has not yet reached 0. \n// (2) If load = 0, the internal counter should decrement by 1. The output signal tc (\"terminal count\") indicates whether the internal counter has reached 0. Once the internal counter has reached 0, it should stay 0 (stop counting) until the counter is loaded again.\n\n", "header": "module top_module(\n\tinput clk, \n\tinput load, \n\tinput [9:0] data, \n\toutput tc\n);\n", "module_code": "module top_module(\n\tinput clk, \n\tinput load, \n\tinput [9:0] data, \n\toutput tc\n);\n\tlogic [9:0] count_value;\n\n\talways @(posedge clk)\n\t\tif(load) count_value <= data;\n\t\telse if(count_value != 0) count_value <= count_value - 1;\n\n\tassign tc = count_value == 0;\n\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput clk, \n\tinput load, \n\tinput [9:0] data, \n\toutput tc\n);\n\tlogic [9:0] count_value;\n\n\talways @(posedge clk)\n\t\tif(load) count_value <= data;\n\t\telse if(count_value != 0) count_value <= count_value - 1;\n\n\tassign tc = count_value == 0;\n\nendmodule\n\nmodule stimulus_gen(\n\tinput clk, \n\toutput logic load, \n\toutput logic [9:0] data, \n\tinput tb_match,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\toutput int wavedrom_hide_after_time\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\tinitial begin\n\t\tload <= 1'b0;\n\t\twavedrom_start(\"Count 3, then 10 cycles\");\n\t\t\t@(posedge clk) {data, load} <= {10'd3, 1'b1};\n\t\t\t@(posedge clk) {data, load} <= {10'hx, 1'b0};\n\t\t\t@(posedge clk) load <= 0;\n\t\t\t@(posedge clk) load <= 0;\n\t\t\t@(posedge clk) load <= 0;\n\t\t\t@(posedge clk) {data, load} <= {10'd10, 1'b1};\n\t\t\t@(posedge clk) {data, load} <= {10'hx, 1'b0};\n\t\t\trepeat(12) @(posedge clk);\n\t\twavedrom_stop();\n\n\t\t@(posedge clk) {load, data} <= {1'b1, 10'h10};\n\t\t@(posedge clk) {load, data} <= {1'b0, 10'h10};\n\t\t@(posedge clk) {load, data} <= {1'b1, 10'h0};   // Load 0\n\t\t@(posedge clk) {load, data} <= {1'b1, 10'h3ff}; // Load 1023\n\t\t@(posedge clk) {load, data} <= {1'b0, 10'h0};\n\t\trepeat(1040) @(posedge clk);\n\n\t\trepeat(2500) @(posedge clk) begin\n\t\t\tload <= !($urandom & 10'hf);\n\t\t\tdata <= $urandom_range(0,32);\n\t\tend\n\n\t\t\n\t\t#1 $finish;\n\tend\n\nendmodule\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_tc;\n\t\tint errortime_tc;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic load;\n\tlogic [9:0] data;\n\tlogic tc_ref;\n\tlogic tc_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,load,data,tc_ref,tc_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.load,\n\t\t.data );\n\treference_module good1 (\n\t\t.clk,\n\t\t.load,\n\t\t.data,\n\t\t.tc(tc_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.load,\n\t\t.data,\n\t\t.tc(tc_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_tc) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"tc\", stats1.errors_tc, stats1.errortime_tc);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"tc\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { tc_ref } === ( { tc_ref } ^ { tc_dut } ^ { tc_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (tc_ref !== ( tc_ref ^ tc_dut ^ tc_ref ))\n\t\tbegin if (stats1.errors_tc == 0) stats1.errortime_tc = $time;\n\t\t\tstats1.errors_tc = stats1.errors_tc+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "review2015_fsmseq", "task_number": 75, "description": "Build a finite-state machine that searches for the sequence 1101 in an input bit stream. When the sequence is found, it should set start_shifting to 1, forever, until reset. Reset is active high synchronous.", "header": "module top_module(\n\tinput clk,\n\tinput reset,\n\tinput data,\n\toutput start_shifting);\n", "module_code": "module top_module(\n\tinput clk,\n\tinput reset,\n\tinput data,\n\toutput start_shifting);\n\n\tparameter S=0, S1=1, S11=2, S110=3, Done=4;\n\t\n\treg [2:0] state, next;\n\t\n\talways_comb begin\n\t\tcase (state)\n\t\t\tS: next = data ? S1: S;\n\t\t\tS1: next = data ? S11: S;\n\t\t\tS11: next = data ? S11 : S110;\n\t\t\tS110: next = data ? Done : S;\n\t\t\tDone: next = Done;\n\t\tendcase\n\tend\n\t\n\talways @(posedge clk)\n\t\tif (reset) state <= S;\n\t\telse state <= next;\n\t\t\n\tassign start_shifting = state == Done;\n\t\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput clk,\n\tinput reset,\n\tinput data,\n\toutput start_shifting);\n\n\tparameter S=0, S1=1, S11=2, S110=3, Done=4;\n\t\n\treg [2:0] state, next;\n\t\n\talways_comb begin\n\t\tcase (state)\n\t\t\tS: next = data ? S1: S;\n\t\t\tS1: next = data ? S11: S;\n\t\t\tS11: next = data ? S11 : S110;\n\t\t\tS110: next = data ? Done : S;\n\t\t\tDone: next = Done;\n\t\tendcase\n\tend\n\t\n\talways @(posedge clk)\n\t\tif (reset) state <= S;\n\t\telse state <= next;\n\t\t\n\tassign start_shifting = state == Done;\n\t\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg reset, data,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\tinput tb_match\n);\n\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\twire [0:9] d = 10'b1110110011;\n\t\n\t\n\tinitial begin\n\t\treset <= 1;\n\t\t@(posedge clk) reset <= 0;\n\t\tdata <= 1;\n\t\trepeat(2) @(posedge clk) ;\n\t\tdata <= 0;\n\t\t@(posedge clk);\n\t\tdata <= 1;\n\t\t@(posedge clk);\n\t\tdata <= 0;\n\t\n\t\twavedrom_start(\"Reset and sequence detect\");\n\t\treset_test();\n\t\tfor (int i=0;i<10;i++) begin\n\t\t\t@(posedge clk) data <= d[i];\n\t\tend\n\t\twavedrom_stop();\n\t\trepeat(600) @(posedge clk, negedge clk) begin\n\t\t\treset <= !($random & 31);\n\t\t\tdata <= $random;\n\t\tend\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_start_shifting;\n\t\tint errortime_start_shifting;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic reset;\n\tlogic data;\n\tlogic start_shifting_ref;\n\tlogic start_shifting_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,data,start_shifting_ref,start_shifting_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.reset,\n\t\t.data );\n\treference_module good1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.data,\n\t\t.start_shifting(start_shifting_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.data,\n\t\t.start_shifting(start_shifting_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_start_shifting) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"start_shifting\", stats1.errors_start_shifting, stats1.errortime_start_shifting);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"start_shifting\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { start_shifting_ref } === ( { start_shifting_ref } ^ { start_shifting_dut } ^ { start_shifting_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (start_shifting_ref !== ( start_shifting_ref ^ start_shifting_dut ^ start_shifting_ref ))\n\t\tbegin if (stats1.errors_start_shifting == 0) stats1.errortime_start_shifting = $time;\n\t\t\tstats1.errors_start_shifting = stats1.errors_start_shifting+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "dff8r", "task_number": 76, "description": "Create 8 D flip-flops with active high synchronous reset setting the output to zero. All DFFs should be triggered by the positive edge of clk.", "header": "module top_module(\n\tinput clk,\n\tinput [7:0] d,\n\tinput reset,\n\toutput reg [7:0] q);\n", "module_code": "module top_module(\n\tinput clk,\n\tinput [7:0] d,\n\tinput reset,\n\toutput reg [7:0] q);\n\t\n\talways @(posedge clk)\n\t\tif (reset)\n\t\t\tq <= 0;\n\t\telse\n\t\t\tq <= d;\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput clk,\n\tinput [7:0] d,\n\tinput reset,\n\toutput reg [7:0] q);\n\t\n\talways @(posedge clk)\n\t\tif (reset)\n\t\t\tq <= 0;\n\t\telse\n\t\t\tq <= d;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg [7:0] d, output reg reset,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\tinput tb_match\t\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\t\n\t\n\tinitial begin\n\t\treset <= 1;\n\t\td <= $random;\n\t\twavedrom_start(\"Synchronous active-high reset\");\n\t\treset_test();\n\t\trepeat(10) @(negedge clk)\n\t\t\td <= $random;\n\t\twavedrom_stop();\n\t\n\t\trepeat(400) @(posedge clk, negedge clk) begin\n\t\t\treset <= !($random & 15);\n\t\t\td <= $random;\n\t\tend\n\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_q;\n\t\tint errortime_q;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [7:0] d;\n\tlogic reset;\n\tlogic [7:0] q_ref;\n\tlogic [7:0] q_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,d,reset,q_ref,q_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.d,\n\t\t.reset );\n\treference_module good1 (\n\t\t.clk,\n\t\t.d,\n\t\t.reset,\n\t\t.q(q_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.d,\n\t\t.reset,\n\t\t.q(q_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"q\", stats1.errors_q, stats1.errortime_q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"q\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (q_ref !== ( q_ref ^ q_dut ^ q_ref ))\n\t\tbegin if (stats1.errors_q == 0) stats1.errortime_q = $time;\n\t\t\tstats1.errors_q = stats1.errors_q+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "edgedetect2", "task_number": 77, "description": "For each bit in an 8-bit vector, detect when the input signal changes from one clock cycle to the next (detect any edge). The output bit should be set the cycle after a 0 to 1 transition occurs.", "header": "module top_module(\n\tinput clk,\n\tinput [7:0] in,\n\toutput reg [7:0] anyedge);\n", "module_code": "module top_module(\n\tinput clk,\n\tinput [7:0] in,\n\toutput reg [7:0] anyedge);\n\t\n\treg [7:0] d_last;\t\n\t\t\t\n\talways @(posedge clk) begin\n\t\td_last <= in;\n\t\tanyedge <= in ^ d_last;\n\tend\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput clk,\n\tinput [7:0] in,\n\toutput reg [7:0] anyedge);\n\t\n\treg [7:0] d_last;\t\n\t\t\t\n\talways @(posedge clk) begin\n\t\td_last <= in;\n\t\tanyedge <= in ^ d_last;\n\tend\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\tinput tb_match,\n\toutput reg [7:0] in,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\tinitial begin\n\t\tin <= 0;\n\t\t@(posedge clk);\n\t\t@(negedge clk) wavedrom_start(\"\");\n\t\trepeat(2) @(posedge clk);\n\t\tin <= 1;\n\t\trepeat(4) @(posedge clk);\n\t\tin <= 0;\n\t\trepeat(4) @(negedge clk);\n\t\tin <= 6;\n\t\trepeat(2) @(negedge clk);\n\t\tin <= 0;\t\t\n\t\trepeat(2) @(posedge clk);\n\t\t@(negedge clk) wavedrom_stop();\n\t\t\t\n\t\trepeat(200)\n\t\t\t@(posedge clk, negedge clk) in <= $random;\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_anyedge;\n\t\tint errortime_anyedge;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [7:0] in;\n\tlogic [7:0] anyedge_ref;\n\tlogic [7:0] anyedge_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,in,anyedge_ref,anyedge_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in );\n\treference_module good1 (\n\t\t.clk,\n\t\t.in,\n\t\t.anyedge(anyedge_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.in,\n\t\t.anyedge(anyedge_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_anyedge) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"anyedge\", stats1.errors_anyedge, stats1.errortime_anyedge);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"anyedge\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { anyedge_ref } === ( { anyedge_ref } ^ { anyedge_dut } ^ { anyedge_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (anyedge_ref !== ( anyedge_ref ^ anyedge_dut ^ anyedge_ref ))\n\t\tbegin if (stats1.errors_anyedge == 0) stats1.errortime_anyedge = $time;\n\t\t\tstats1.errors_anyedge = stats1.errors_anyedge+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "count1to10", "task_number": 78, "description": "Make a decade counter that counts 1 through 10, inclusive. The reset input is active high synchronous, and should reset the counter to 1.", "header": "module top_module(\n\tinput clk,\n\tinput reset,\n\toutput reg [3:0] q);\n", "module_code": "module top_module(\n\tinput clk,\n\tinput reset,\n\toutput reg [3:0] q);\n\t\n\talways @(posedge clk)\n\t\tif (reset || q == 10)\n\t\t\tq <= 1;\n\t\telse\n\t\t\tq <= q+1;\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput clk,\n\tinput reset,\n\toutput reg [3:0] q);\n\t\n\talways @(posedge clk)\n\t\tif (reset || q == 10)\n\t\t\tq <= 1;\n\t\telse\n\t\t\tq <= q+1;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg reset,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\tinput tb_match\t\n);\n\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\t\n\tinitial begin\n\t\treset <= 1;\n\t\twavedrom_start(\"Synchronous reset and counting.\");\n\t\treset_test();\n\t\trepeat(12) @(posedge clk);\n\t\twavedrom_stop();\n\t\t@(posedge clk);\n\t\t\n\t\trepeat(400) @(posedge clk, negedge clk) begin\n\t\t\treset <= !($random & 31);\n\t\tend\n\t\t#1 $finish;\n\tend\n\t\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_q;\n\t\tint errortime_q;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic reset;\n\tlogic [3:0] q_ref;\n\tlogic [3:0] q_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,q_ref,q_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.reset );\n\treference_module good1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.q(q_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.q(q_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"q\", stats1.errors_q, stats1.errortime_q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"q\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (q_ref !== ( q_ref ^ q_dut ^ q_ref ))\n\t\tbegin if (stats1.errors_q == 0) stats1.errortime_q = $time;\n\t\t\tstats1.errors_q = stats1.errors_q+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "circuit9", "task_number": 79, "description": "This is a sequential circuit. Read the simulation waveforms to determine what the circuit does, then implement it.\n\n// time            clk             a               q               \n// 0ns             0               1               x               \n// 5ns             1               1               4               \n// 10ns            0               1               4               \n// 15ns            1               1               4               \n// 20ns            0               1               4               \n// 25ns            1               1               4               \n// 30ns            0               1               4               \n// 35ns            1               1               4               \n// 40ns            0               1               4               \n// 45ns            1               0               4               \n// 50ns            0               0               4               \n// 55ns            1               0               5               \n// 60ns            0               0               5               \n// 65ns            1               0               6               \n// 70ns            0               0               6               \n// 75ns            1               0               0               \n// 80ns            0               0               0               \n// 85ns            1               0               1               \n// 90ns            0               0               1               ", "header": "module top_module (\n\tinput clk,\n\tinput a, \n\toutput reg [2:0] q\n);\n", "module_code": "module top_module (\n\tinput clk,\n\tinput a, \n\toutput reg [2:0] q\n);\n\n\talways @(posedge clk)\n\t\tif (a)\n\t\t\tq <= 4;\n\t\telse if (q == 6)\n\t\t\tq <= 0;\n\t\telse\n\t\t\tq <= q + 1'b1;\n\t\t\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput a, \n\toutput reg [2:0] q\n);\n\n\talways @(posedge clk)\n\t\tif (a)\n\t\t\tq <= 4;\n\t\telse if (q == 6)\n\t\t\tq <= 0;\n\t\telse\n\t\t\tq <= q + 1'b1;\n\t\t\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic a,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\ta <= 1;\n\t\t@(negedge clk) {a} <= 1;\n\t\t@(negedge clk) wavedrom_start(\"Unknown circuit\");\n\t\t\trepeat(2) @(posedge clk);\n\t\t\t@(posedge clk) {a} <= 0;\n\t\t\trepeat(11) @(posedge clk);\n\t\t\t@(negedge clk) a <= 1;\n\t\t\trepeat(5) @(posedge clk, negedge clk);\n\t\t\ta <= 0;\n\t\t\trepeat(4) @(posedge clk);\n\t\twavedrom_stop();\n\n\t\trepeat(200) @(posedge clk, negedge clk)\n\t\t\ta <= &((5)'($urandom));\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_q;\n\t\tint errortime_q;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic a;\n\tlogic [2:0] q_ref;\n\tlogic [2:0] q_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,a,q_ref,q_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.a );\n\treference_module good1 (\n\t\t.clk,\n\t\t.a,\n\t\t.q(q_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.a,\n\t\t.q(q_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"q\", stats1.errors_q, stats1.errortime_q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"q\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (q_ref !== ( q_ref ^ q_dut ^ q_ref ))\n\t\tbegin if (stats1.errors_q == 0) stats1.errortime_q = $time;\n\t\t\tstats1.errors_q = stats1.errors_q+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "lfsr5", "task_number": 80, "description": "A linear feedback shift register is a shift register usually with a few XOR gates to produce the next state of the shift register. A Galois LFSR is one particular arrangement where bit positions with a \"tap\" are XORed with the output bit to produce its next value, while bit positions without a tap shift. If the taps positions are carefully chosen, the LFSR can be made to be \"maximum-length\". A maximum-length LFSR of n bits cycles through 2**n-1 states before repeating (the all-zero state is never reached). Build a 5-bit maximal-length Galois LFSR with taps at bit positions 5 and 3. The active-high synchronous reset should reset the LFSR output to 1.", "header": "module top_module(\n\tinput clk,\n\tinput reset,\n\toutput reg [4:0] q);\n", "module_code": "module top_module(\n\tinput clk,\n\tinput reset,\n\toutput reg [4:0] q);\n\t\n\tlogic [4:0] q_next;\n\talways @(q) begin\n\t\tq_next = q[4:1];\n\t\tq_next[4] = q[0];\n\t\tq_next[2] ^= q[0];\n\tend\n\t\n\talways @(posedge clk) begin\n\t\tif (reset)\n\t\t\tq <= 5'h1;\n\t\telse\n\t\t\tq <= q_next;\n\tend\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput clk,\n\tinput reset,\n\toutput reg [4:0] q);\n\t\n\tlogic [4:0] q_next;\n\talways @(q) begin\n\t\tq_next = q[4:1];\n\t\tq_next[4] = q[0];\n\t\tq_next[2] ^= q[0];\n\tend\n\t\n\talways @(posedge clk) begin\n\t\tif (reset)\n\t\t\tq <= 5'h1;\n\t\telse\n\t\t\tq <= q_next;\n\tend\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg reset,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\tinput tb_match\t\n);\n\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\tinitial begin\n\t\treset <= 1;\n\t\t@(negedge clk);\n\t\twavedrom_start();\n\t\t\treset_test();\n\t\t\trepeat(8) @(posedge clk);\n\t\t@(negedge clk);\n\t\twavedrom_stop();\n\t\trepeat(400) @(posedge clk, negedge clk) begin\n\t\t\treset <= !($random & 31);\n\t\tend\n\t\t@(posedge clk) reset <= 1'b0;\n\t\trepeat(2000) @(posedge clk);\n\t\treset <= 1'b1;\n\t\trepeat(5) @(posedge clk);\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_q;\n\t\tint errortime_q;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic reset;\n\tlogic [4:0] q_ref;\n\tlogic [4:0] q_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,q_ref,q_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.reset );\n\treference_module good1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.q(q_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.q(q_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"q\", stats1.errors_q, stats1.errortime_q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"q\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (q_ref !== ( q_ref ^ q_dut ^ q_ref ))\n\t\tbegin if (stats1.errors_q == 0) stats1.errortime_q = $time;\n\t\t\tstats1.errors_q = stats1.errors_q+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "bugs_addsubz", "task_number": 81, "description": "The following adder-subtractor with zero flag doesn't work. Fix the bug(s).\n\n// synthesis verilog_input_version verilog_2001\n// module top_module ( \n//     input do_sub,\n//     input [7:0] a,\n//     input [7:0] b,\n//     output reg [7:0] out,\n//     output reg result_is_zero\n// );//\n\n//     always @(*) begin\n//         case (do_sub)\n//           0: out = a+b;\n//           1: out = a-b;\n//         endcase\n\n//         if (~out)\n//             result_is_zero = 1;\n//     end\n\n// endmodule", "header": "module top_module (\n\tinput do_sub,\n\tinput [7:0] a,\n\tinput [7:0] b,\n\toutput reg [7:0] out,\n\toutput reg result_is_zero\n);\n", "module_code": "module top_module (\n\tinput do_sub,\n\tinput [7:0] a,\n\tinput [7:0] b,\n\toutput reg [7:0] out,\n\toutput reg result_is_zero\n);\n\n\talways @(*) begin\n\t\tcase (do_sub)\n\t\t\t0: out = a + b;\n\t\t\t1: out = a - b;\n\t\tendcase\n\t\tresult_is_zero = (out == 0);\n\tend\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput do_sub,\n\tinput [7:0] a,\n\tinput [7:0] b,\n\toutput reg [7:0] out,\n\toutput reg result_is_zero\n);\n\n\talways @(*) begin\n\t\tcase (do_sub)\n\t\t\t0: out = a + b;\n\t\t\t1: out = a - b;\n\t\tendcase\n\t\tresult_is_zero = (out == 0);\n\tend\n\t\nendmodule\n\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic do_sub,\n\toutput logic [7:0] a, b,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\tinput tb_match\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\tinitial begin\n\t\t{a, b} <= 16'haabb;\n\t\tdo_sub <= 0;\n\t\t@(negedge clk) wavedrom_start(\"\");\n\t\t\t@(posedge clk, negedge clk) do_sub <= 0;\n\t\t\t@(posedge clk, negedge clk) do_sub <= 0;\n\t\t\t@(posedge clk, negedge clk) do_sub <= 1;\n\t\t\t@(posedge clk, negedge clk) do_sub <= 1;\n\t\t\t\n\t\t\t@(posedge clk, negedge clk) {a, b} <= 16'h0303; do_sub <= 1'b0;\n\t\t\t@(posedge clk, negedge clk) do_sub <= 0;\n\t\t\t@(posedge clk, negedge clk) do_sub <= 1;\n\t\t\t@(posedge clk, negedge clk) {a, b} <= 16'h0304; do_sub <= 1'b0;\n\t\t\t@(posedge clk, negedge clk) do_sub <= 0;\n\t\t\t@(posedge clk, negedge clk) do_sub <= 1;\n\t\t\t@(posedge clk, negedge clk) {a, b} <= 16'hfd03; do_sub <= 1'b0;\n\t\t\t@(posedge clk, negedge clk) do_sub <= 0;\n\t\t\t@(posedge clk, negedge clk) do_sub <= 1;\n\t\t\t@(posedge clk, negedge clk) {a, b} <= 16'hfd04; do_sub <= 1'b0;\n\t\t\t@(posedge clk, negedge clk) do_sub <= 0;\n\t\t\t@(posedge clk, negedge clk) do_sub <= 1;\n\t\twavedrom_stop();\n\t\t\n\t\trepeat(100) @(posedge clk, negedge clk) begin\n\t\t\t{a,b, do_sub} <= $urandom;\n\t\tend\n\t\t\t\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\t\tint errors_result_is_zero;\n\t\tint errortime_result_is_zero;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic do_sub;\n\tlogic [7:0] a;\n\tlogic [7:0] b;\n\tlogic [7:0] out_ref;\n\tlogic [7:0] out_dut;\n\tlogic result_is_zero_ref;\n\tlogic result_is_zero_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,do_sub,a,b,out_ref,out_dut,result_is_zero_ref,result_is_zero_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.do_sub,\n\t\t.a,\n\t\t.b );\n\treference_module good1 (\n\t\t.do_sub,\n\t\t.a,\n\t\t.b,\n\t\t.out(out_ref),\n\t\t.result_is_zero(result_is_zero_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.do_sub,\n\t\t.a,\n\t\t.b,\n\t\t.out(out_dut),\n\t\t.result_is_zero(result_is_zero_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\t\tif (stats1.errors_result_is_zero) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"result_is_zero\", stats1.errors_result_is_zero, stats1.errortime_result_is_zero);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"result_is_zero\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref, result_is_zero_ref } === ( { out_ref, result_is_zero_ref } ^ { out_dut, result_is_zero_dut } ^ { out_ref, result_is_zero_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\t\tif (result_is_zero_ref !== ( result_is_zero_ref ^ result_is_zero_dut ^ result_is_zero_ref ))\n\t\tbegin if (stats1.errors_result_is_zero == 0) stats1.errortime_result_is_zero = $time;\n\t\t\tstats1.errors_result_is_zero = stats1.errors_result_is_zero+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "m2014_q3", "task_number": 82, "description": "Consider the function f shown in the Karnaugh map below. d is don't-care, which means you may choose to output whatever value is convenient. Implement this function. \n//        x[1]x[2]\n// x[3]x[4]   00 01 11 10\n//  00 | d | 0 | d | d |\n//  01 | 0 | d | 1 | 0 |\n//  11 | 1 | 1 | d | d |\n//  10 | 1 | 1 | 0 | d |", "header": "module top_module (\n\tinput [4:1] x,\n\toutput logic f\n);\n", "module_code": "module top_module (\n\tinput [4:1] x,\n\toutput logic f\n);\n\n\talways_comb begin\n\t\tcase (x) \n\t\t\t4'h0: f = 1'bx;\n\t\t\t4'h1: f = 1'bx;\n\t\t\t4'h2: f = 0;\n\t\t\t4'h3: f = 1'bx;\n\t\t\t4'h4: f = 1;\n\t\t\t4'h5: f = 1'bx;\n\t\t\t4'h6: f = 1;\n\t\t\t4'h7: f = 0;\n\t\t\t4'h8: f = 0;\n\t\t\t4'h9: f = 0;\n\t\t\t4'ha: f = 1'bx;\n\t\t\t4'hb: f = 1;\n\t\t\t4'hc: f = 1;\n\t\t\t4'hd: f = 1'bx;\n\t\t\t4'he: f = 1;\n\t\t\t4'hf: f = 1'bx;\n\t\tendcase\n\tend\n\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [4:1] x,\n\toutput logic f\n);\n\n\talways_comb begin\n\t\tcase (x) \n\t\t\t4'h0: f = 1'bx;\n\t\t\t4'h1: f = 1'bx;\n\t\t\t4'h2: f = 0;\n\t\t\t4'h3: f = 1'bx;\n\t\t\t4'h4: f = 1;\n\t\t\t4'h5: f = 1'bx;\n\t\t\t4'h6: f = 1;\n\t\t\t4'h7: f = 0;\n\t\t\t4'h8: f = 0;\n\t\t\t4'h9: f = 0;\n\t\t\t4'ha: f = 1'bx;\n\t\t\t4'hb: f = 1;\n\t\t\t4'hc: f = 1;\n\t\t\t4'hd: f = 1'bx;\n\t\t\t4'he: f = 1;\n\t\t\t4'hf: f = 1'bx;\n\t\tendcase\n\tend\n\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic [4:1] x\n);\n\n\tinitial begin\n\t\trepeat(100) @(posedge clk, negedge clk) begin\n\t\t\tx <= $random;\n\t\tend\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_f;\n\t\tint errortime_f;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [4:1] x;\n\tlogic f_ref;\n\tlogic f_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,x,f_ref,f_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.x );\n\treference_module good1 (\n\t\t.x,\n\t\t.f(f_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.x,\n\t\t.f(f_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_f) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"f\", stats1.errors_f, stats1.errortime_f);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"f\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { f_ref } === ( { f_ref } ^ { f_dut } ^ { f_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (f_ref !== ( f_ref ^ f_dut ^ f_ref ))\n\t\tbegin if (stats1.errors_f == 0) stats1.errortime_f = $time;\n\t\t\tstats1.errors_f = stats1.errors_f+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "bugs_case", "task_number": 83, "description": "This combinational circuit is supposed to recognize 8-bit keyboard scancodes for keys 0 through 9. It should indicate whether one of the 10 cases were recognized (valid), and if so, which key was detected. If the 8-bit input is 8'h45, 8'h16, 8'h1e, 8'h26, 8'h25, 8'h2e, 8'h36, 8'h3d, 8'h3e, or 8'h46, the 4-bit output will be set to 0, 1, 2, 3, 4, 5, 6, 7, 8, or 9 respectively, the 1-bit valid would be set to 1. If the input does not match any of the cases, both output signals would be set to 0.", "header": "module top_module (\n\tinput [7:0] code,\n\toutput reg [3:0] out,\n\toutput reg valid\n);\n", "module_code": "module top_module (\n\tinput [7:0] code,\n\toutput reg [3:0] out,\n\toutput reg valid\n);\n//\tuhh.. make a case statement: maps scancode to 0-9, but accidentally infer a latch?\n//  and have one of the entries be wrong? (duplicate case, using different base!) \n\talways @(*) begin\n\t\tout = 0;\n\t\tvalid = 1;\n\t\tcase (code)\n\t\t\t8'h45: out = 0;\n\t\t\t8'h16: out = 1;\n\t\t\t8'h1e: out = 2;\n\t\t\t8'h26: out = 3;\n\t\t\t8'h25: out = 4;\n\t\t\t8'h2e: out = 5;\n\t\t\t8'h36: out = 6;\n\t\t\t8'h3d: out = 7;\n\t\t\t8'h3e: out = 8;\n\t\t\t8'h46: out = 9;\n\t\t\tdefault: valid = 0;\n\t\tendcase\n\tend\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [7:0] code,\n\toutput reg [3:0] out,\n\toutput reg valid\n);\n//\tuhh.. make a case statement: maps scancode to 0-9, but accidentally infer a latch?\n//  and have one of the entries be wrong? (duplicate case, using different base!) \n\talways @(*) begin\n\t\tout = 0;\n\t\tvalid = 1;\n\t\tcase (code)\n\t\t\t8'h45: out = 0;\n\t\t\t8'h16: out = 1;\n\t\t\t8'h1e: out = 2;\n\t\t\t8'h26: out = 3;\n\t\t\t8'h25: out = 4;\n\t\t\t8'h2e: out = 5;\n\t\t\t8'h36: out = 6;\n\t\t\t8'h3d: out = 7;\n\t\t\t8'h3e: out = 8;\n\t\t\t8'h46: out = 9;\n\t\t\tdefault: valid = 0;\n\t\tendcase\n\tend\n\t\nendmodule\n\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic [7:0] code,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\tinput tb_match\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\tinitial begin\n\t\tcode <= 8'h45;\n\t\t@(negedge clk) wavedrom_start(\"Decode scancodes\");\n\t\t\t@(posedge clk) code <= 8'h45;\n\t\t\t@(posedge clk) code <= 8'h03;\n\t\t\t@(posedge clk) code <= 8'h46;\n\t\t\t@(posedge clk) code <= 8'h16;\n\t\t\t@(posedge clk) code <= 8'd26;\n\t\t\t@(posedge clk) code <= 8'h1e;\n\t\t\t@(posedge clk) code <= 8'h25;\n\t\t\t@(posedge clk) code <= 8'h26;\n\t\t\t@(posedge clk) code <= 8'h2e;\n\t\t\t@(posedge clk) code <= $random;\n\t\t\t@(posedge clk) code <= 8'h36;\n\t\t\t@(posedge clk) code <= $random;\n\t\t\t@(posedge clk) code <= 8'h3d;\n\t\t\t@(posedge clk) code <= 8'h3e;\n\t\t\t@(posedge clk) code <= 8'h45;\n\t\t\t@(posedge clk) code <= 8'h46;\n\t\t\t@(posedge clk) code <= $random;\n\t\t\t@(posedge clk) code <= $random;\n\t\t\t@(posedge clk) code <= $random;\n\t\t\t@(posedge clk) code <= $random;\n\t\twavedrom_stop();\n\t\t\n\t\trepeat(1000) @(posedge clk, negedge clk) begin\n\t\t\tcode <= $urandom;\n\t\tend\n\t\t\t\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\t\tint errors_valid;\n\t\tint errortime_valid;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [7:0] code;\n\tlogic [3:0] out_ref;\n\tlogic [3:0] out_dut;\n\tlogic valid_ref;\n\tlogic valid_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,code,out_ref,out_dut,valid_ref,valid_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.code );\n\treference_module good1 (\n\t\t.code,\n\t\t.out(out_ref),\n\t\t.valid(valid_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.code,\n\t\t.out(out_dut),\n\t\t.valid(valid_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\t\tif (stats1.errors_valid) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"valid\", stats1.errors_valid, stats1.errortime_valid);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"valid\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref, valid_ref } === ( { out_ref, valid_ref } ^ { out_dut, valid_dut } ^ { out_ref, valid_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\t\tif (valid_ref !== ( valid_ref ^ valid_dut ^ valid_ref ))\n\t\tbegin if (stats1.errors_valid == 0) stats1.errortime_valid = $time;\n\t\t\tstats1.errors_valid = stats1.errors_valid+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "vectorr", "task_number": 84, "description": "Given an 8-bit input vector [7:0], reverse its bit ordering.", "header": "module top_module (\n\tinput [7:0] in,\n\toutput [7:0] out\n);\n", "module_code": "module top_module (\n\tinput [7:0] in,\n\toutput [7:0] out\n);\n\t\n\tassign {out[0],out[1],out[2],out[3],out[4],out[5],out[6],out[7]} = in;\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [7:0] in,\n\toutput [7:0] out\n);\n\t\n\tassign {out[0],out[1],out[2],out[3],out[4],out[5],out[6],out[7]} = in;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic [7:0] in,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\t\n\n\t\n\tinitial begin\n\t\tin <= 0;\n\t\t@(negedge clk) wavedrom_start();\n\t\t\t@(posedge clk) in <= 8'h1;\n\t\t\t@(posedge clk) in <= 8'h2;\n\t\t\t@(posedge clk) in <= 8'h4;\n\t\t\t@(posedge clk) in <= 8'h8;\n\t\t\t@(posedge clk) in <= 8'h80;\n\t\t\t@(posedge clk) in <= 8'hc0;\n\t\t\t@(posedge clk) in <= 8'he0;\n\t\t\t@(posedge clk) in <= 8'hf0;\n\t\t@(negedge clk) wavedrom_stop();\n\t\n\t\trepeat(200) @(posedge clk, negedge clk)\n\t\t\tin <= $random;\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [7:0] in;\n\tlogic [7:0] out_ref;\n\tlogic [7:0] out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,in,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in );\n\treference_module good1 (\n\t\t.in,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.in,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "kmap3", "task_number": 85, "description": "Implement the circuit described by the Karnaugh map below. d is don't-care, which means you may choose to output whatever value is convenient.\n\n//        ab\n// cd   01 00 10 11\n//  00 | d | 0 | 1 | 1 |\n//  01 | 0 | 0 | d | d |\n//  11 | 0 | 1 | 1 | 1 |\n//  10 | 0 | 1 | 1 | 1 |", "header": "module top_module (\n\tinput a, \n\tinput b,\n\tinput c,\n\tinput d,\n\toutput reg out\n);\n", "module_code": "module top_module (\n\tinput a, \n\tinput b,\n\tinput c,\n\tinput d,\n\toutput reg out\n);\n\t\n    always @(*) begin\n        case({a,b,c,d})\n            4'h0: out = 0;\n            4'h1: out = 0;\n            4'h3: out = 1;\n            4'h2: out = 1;\n            4'h4: out = 1'bx;\n            4'h5: out = 0;\n            4'h7: out = 0;\n            4'h6: out = 0;\n            4'hc: out = 1;\n            4'hd: out = 1'bx;\n            4'hf: out = 1;\n            4'he: out = 1;\n            4'h8: out = 1;\n            4'h9: out = 1'bx;\n            4'hb: out = 1;\n            4'ha: out = 1;\n        endcase\n    end\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput a, \n\tinput b,\n\tinput c,\n\tinput d,\n\toutput reg out\n);\n\t\n    always @(*) begin\n        case({a,b,c,d})\n            4'h0: out = 0;\n            4'h1: out = 0;\n            4'h3: out = 1;\n            4'h2: out = 1;\n            4'h4: out = 1'bx;\n            4'h5: out = 0;\n            4'h7: out = 0;\n            4'h6: out = 0;\n            4'hc: out = 1;\n            4'hd: out = 1'bx;\n            4'hf: out = 1;\n            4'he: out = 1;\n            4'h8: out = 1;\n            4'h9: out = 1'bx;\n            4'hb: out = 1;\n            4'ha: out = 1;\n        endcase\n    end\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg a, b, c, d,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\tint count; count = 0;\n\t\t{a,b,c,d} <= 4'b0;\n\t\twavedrom_start();\n\t\trepeat(16) @(posedge clk)\n\t\t\t{a,b,c,d} <= count++;\t\t\n\t\t@(negedge clk) wavedrom_stop();\n\t\t\n\t\trepeat(200) @(posedge clk, negedge clk)\n\t\t\t{d,c,b,a} <= $urandom;\n\t\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic a;\n\tlogic b;\n\tlogic c;\n\tlogic d;\n\tlogic out_ref;\n\tlogic out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,a,b,c,d,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d );\n\treference_module good1 (\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "review2015_shiftcount", "task_number": 86, "description": "Build a four-bit shift register that also acts as a down counter. Data is shifted in most-significant-bit first when shift_ena is 1. The number currently in the shift register is decremented when count_ena is 1. Since the full system doesn't ever use shift_ena and count_ena together, it does not matter what your circuit does if both control inputs are 1 (This mainly means that it doesn't matter which case gets higher priority).", "header": "module top_module(\n\tinput clk,\n\tinput shift_ena,\n\tinput count_ena,\n\tinput data,\n\toutput reg [3:0] q);\n", "module_code": "module top_module(\n\tinput clk,\n\tinput shift_ena,\n\tinput count_ena,\n\tinput data,\n\toutput reg [3:0] q);\n\t\n\talways @(posedge clk) begin\n\t\tif (shift_ena)\n\t\t\tq <= { q[2:0], data };\n\t\telse if (count_ena)\n\t\t\tq <= q - 1'b1;\n\tend \n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput clk,\n\tinput shift_ena,\n\tinput count_ena,\n\tinput data,\n\toutput reg [3:0] q);\n\t\n\talways @(posedge clk) begin\n\t\tif (shift_ena)\n\t\t\tq <= { q[2:0], data };\n\t\telse if (count_ena)\n\t\t\tq <= q - 1'b1;\n\tend \n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg shift_ena, count_ena, data,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\tinitial begin\n\t\tdata <= 0;\n\t\tshift_ena <= 1;\n\t\tcount_ena <= 0;\n\t\trepeat(5) @(posedge clk);\n\t\n\t\tdata <= 1;\n\t\tshift_ena <= 0;\n\t\tcount_ena <= 0;\n\t\t@(posedge clk);\n\t\twavedrom_start(\"Shift mode\");\n\t\t@(posedge clk) shift_ena <= 1;\n\t\trepeat(2) @(posedge clk) shift_ena <= 0;\n\t\t@(posedge clk) shift_ena <= 1;\n\t\trepeat(4) @(posedge clk);\n\t\t@(posedge clk) data <= 0;\n\t\trepeat(4) @(posedge clk);\n\t\twavedrom_stop();\n\t\n\t\tdata <= 1;\n\t\tshift_ena <= 1;\t\t\n\t\trepeat(4) @(posedge clk);\n\t\tshift_ena <= 0;\n\t\twavedrom_start(\"Count mode\");\n\t\t@(posedge clk) count_ena <= 1;\n\t\trepeat(2) @(posedge clk) count_ena <= 0;\n\t\t@(posedge clk) count_ena <= 1;\n\t\trepeat(4) @(posedge clk);\n\t\t@(posedge clk) data <= 0;\n\t\trepeat(4) @(posedge clk);\n\t\twavedrom_stop();\n\t\n\t\trepeat(2000) @(posedge clk, negedge clk) begin\n\t\t\t{shift_ena, count_ena} <= $unsigned($random) % 3;\n\t\t\tdata <= $random;\n\t\tend\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_q;\n\t\tint errortime_q;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic shift_ena;\n\tlogic count_ena;\n\tlogic data;\n\tlogic [3:0] q_ref;\n\tlogic [3:0] q_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,shift_ena,count_ena,data,q_ref,q_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.shift_ena,\n\t\t.count_ena,\n\t\t.data );\n\treference_module good1 (\n\t\t.clk,\n\t\t.shift_ena,\n\t\t.count_ena,\n\t\t.data,\n\t\t.q(q_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.shift_ena,\n\t\t.count_ena,\n\t\t.data,\n\t\t.q(q_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"q\", stats1.errors_q, stats1.errortime_q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"q\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (q_ref !== ( q_ref ^ q_dut ^ q_ref ))\n\t\tbegin if (stats1.errors_q == 0) stats1.errortime_q = $time;\n\t\t\tstats1.errors_q = stats1.errors_q+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "wire", "task_number": 87, "description": "Create a module with one input and one output that behaves like a wire.", "header": "module top_module(\n\tinput in,\n\toutput out);\n", "module_code": "module top_module(\n\tinput in,\n\toutput out);\n\t\n\tassign out = in;\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput in,\n\toutput out);\n\t\n\tassign out = in;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg in,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\twavedrom_start(\"Output should follow input\");\n\t\trepeat(20) @(posedge clk, negedge clk)\n\t\t\tin <= $random;\n\t\twavedrom_stop();\n\t\trepeat(100) @(posedge clk, negedge clk) begin\n\t\t\tin <= $random;\n\t\tend\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic in;\n\tlogic out_ref;\n\tlogic out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,in,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in );\n\treference_module good1 (\n\t\t.in,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.in,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "review2015_fsmshift", "task_number": 88, "description": "This module is a part of the FSM for controlling the shift register, we want the ability to enable the shift register for exactly 4 clock cycles whenever the proper bit pattern is detected. Whenever the FSM is reset, assert shift_ena for 4 cycles, then 0 forever (until reset). Reset should be active high synchronous.", "header": "module top_module(\n\tinput clk,\n\tinput reset,\n\toutput shift_ena);\n", "module_code": "module top_module(\n\tinput clk,\n\tinput reset,\n\toutput shift_ena);\n\n\tparameter B0=0, B1=1, B2=2, B3=3, Done=4;\n\t\n\treg [2:0] state, next;\n\t\n\talways_comb begin\n\t\tcase (state)\n\t\t\tB0: next = B1;\n\t\t\tB1: next = B2;\n\t\t\tB2: next = B3;\n\t\t\tB3: next = Done;\n\t\t\tDone: next = Done;\n\t\tendcase\n\tend\n\t\n\talways @(posedge clk)\n\t\tif (reset) state <= B0;\n\t\telse state <= next;\n\t\t\n\tassign shift_ena = (state == B0 || state == B1 || state == B2 || state == B3);\n\t\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput clk,\n\tinput reset,\n\toutput shift_ena);\n\n\tparameter B0=0, B1=1, B2=2, B3=3, Done=4;\n\t\n\treg [2:0] state, next;\n\t\n\talways_comb begin\n\t\tcase (state)\n\t\t\tB0: next = B1;\n\t\t\tB1: next = B2;\n\t\t\tB2: next = B3;\n\t\t\tB3: next = Done;\n\t\t\tDone: next = Done;\n\t\tendcase\n\tend\n\t\n\talways @(posedge clk)\n\t\tif (reset) state <= B0;\n\t\telse state <= next;\n\t\t\n\tassign shift_ena = (state == B0 || state == B1 || state == B2 || state == B3);\n\t\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg reset\n);\n\n\t\n\tinitial begin\n\t\trepeat(100) @(negedge clk) begin\n\t\t\treset <= !($random & 31);\n\t\tend\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_shift_ena;\n\t\tint errortime_shift_ena;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic reset;\n\tlogic shift_ena_ref;\n\tlogic shift_ena_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,shift_ena_ref,shift_ena_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.reset );\n\treference_module good1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.shift_ena(shift_ena_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.shift_ena(shift_ena_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_shift_ena) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"shift_ena\", stats1.errors_shift_ena, stats1.errortime_shift_ena);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"shift_ena\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { shift_ena_ref } === ( { shift_ena_ref } ^ { shift_ena_dut } ^ { shift_ena_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (shift_ena_ref !== ( shift_ena_ref ^ shift_ena_dut ^ shift_ena_ref ))\n\t\tbegin if (stats1.errors_shift_ena == 0) stats1.errortime_shift_ena = $time;\n\t\t\tstats1.errors_shift_ena = stats1.errors_shift_ena+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "count15", "task_number": 89, "description": "Build a 4-bit binary counter that counts from 0 through 15, inclusive, with a period of 16. The reset input is active high synchronous, and should reset the counter to 0.", "header": "module top_module(\n\tinput clk,\n\tinput reset,\n\toutput reg [3:0] q);\n", "module_code": "module top_module(\n\tinput clk,\n\tinput reset,\n\toutput reg [3:0] q);\n\t\n\talways @(posedge clk)\n\t\tif (reset)\n\t\t\tq <= 0;\n\t\telse\n\t\t\tq <= q+1;\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput clk,\n\tinput reset,\n\toutput reg [3:0] q);\n\t\n\talways @(posedge clk)\n\t\tif (reset)\n\t\t\tq <= 0;\n\t\telse\n\t\t\tq <= q+1;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg reset,\n\tinput tb_match,\n\toutput reg wavedrom_enable,\n\toutput reg[511:0] wavedrom_title\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\n\tinitial begin\n\t\treset <= 1;\n\t\t@(negedge clk);\n\t\t\n\t\twavedrom_start(\"Reset and counting\");\n\t\treset_test();\n\t\t\n\t\trepeat(3) @(posedge clk);\n\t\twavedrom_stop();\n\n\t\trepeat(400) @(posedge clk, negedge clk) begin\n\t\t\treset <= !($random & 31);\n\t\tend\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_q;\n\t\tint errortime_q;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic reset;\n\tlogic [3:0] q_ref;\n\tlogic [3:0] q_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,q_ref,q_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.reset );\n\treference_module good1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.q(q_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.q(q_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"q\", stats1.errors_q, stats1.errortime_q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"q\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (q_ref !== ( q_ref ^ q_dut ^ q_ref ))\n\t\tbegin if (stats1.errors_q == 0) stats1.errortime_q = $time;\n\t\t\tstats1.errors_q = stats1.errors_q+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "always_if", "task_number": 90, "description": "Build a 2-to-1 mux that chooses between a and b. Choose b if both sel_b1 and sel_b2 are true. Otherwise, choose a. Do the same twice, once using assign statements and once using a procedural if statement.", "header": "module top_module (\n\tinput a,\n\tinput b,\n\tinput sel_b1,\n\tinput sel_b2,\n\toutput out_assign,\n\toutput reg out_always\n);\n", "module_code": "module top_module (\n\tinput a,\n\tinput b,\n\tinput sel_b1,\n\tinput sel_b2,\n\toutput out_assign,\n\toutput reg out_always\n);\n\n\tassign out_assign = (sel_b1 & sel_b2) ? b : a;\n\talways @(*) out_always = (sel_b1 & sel_b2) ? b : a;\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput a,\n\tinput b,\n\tinput sel_b1,\n\tinput sel_b2,\n\toutput out_assign,\n\toutput reg out_always\n);\n\n\tassign out_assign = (sel_b1 & sel_b2) ? b : a;\n\talways @(*) out_always = (sel_b1 & sel_b2) ? b : a;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic a,b,sel_b1, sel_b2,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\t{a, b, sel_b1, sel_b2} <= 4'b000;\n\t\t@(negedge clk) wavedrom_start(\"\");\n\t\t\t@(posedge clk, negedge clk) {a,b,sel_b1,sel_b2} <= 4'b0100;\n\t\t\t@(posedge clk, negedge clk) {a,b,sel_b1,sel_b2} <= 4'b1000;\n\t\t\t@(posedge clk, negedge clk) {a,b,sel_b1,sel_b2} <= 4'b1101;\n\t\t\t@(posedge clk, negedge clk) {a,b,sel_b1,sel_b2} <= 4'b0001;\n\t\t\t@(posedge clk, negedge clk) {a,b,sel_b1,sel_b2} <= 4'b0110;\n\t\t\t@(posedge clk, negedge clk) {a,b,sel_b1,sel_b2} <= 4'b1010;\n\t\t\t@(posedge clk, negedge clk) {a,b,sel_b1,sel_b2} <= 4'b1111;\n\t\t\t@(posedge clk, negedge clk) {a,b,sel_b1,sel_b2} <= 4'b0011;\n\t\t\t@(posedge clk, negedge clk) {a,b,sel_b1,sel_b2} <= 4'b0111;\n\t\t\t@(posedge clk, negedge clk) {a,b,sel_b1,sel_b2} <= 4'b1011;\n\t\t\t@(posedge clk, negedge clk) {a,b,sel_b1,sel_b2} <= 4'b1111;\n\t\t\t@(posedge clk, negedge clk) {a,b,sel_b1,sel_b2} <= 4'b0011;\n\t\twavedrom_stop();\n\t\trepeat(100) @(posedge clk, negedge clk)\n\t\t\t{a,b,sel_b1,sel_b2} <= $urandom;\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out_assign;\n\t\tint errortime_out_assign;\n\t\tint errors_out_always;\n\t\tint errortime_out_always;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic a;\n\tlogic b;\n\tlogic sel_b1;\n\tlogic sel_b2;\n\tlogic out_assign_ref;\n\tlogic out_assign_dut;\n\tlogic out_always_ref;\n\tlogic out_always_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,a,b,sel_b1,sel_b2,out_assign_ref,out_assign_dut,out_always_ref,out_always_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.a,\n\t\t.b,\n\t\t.sel_b1,\n\t\t.sel_b2 );\n\treference_module good1 (\n\t\t.a,\n\t\t.b,\n\t\t.sel_b1,\n\t\t.sel_b2,\n\t\t.out_assign(out_assign_ref),\n\t\t.out_always(out_always_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.a,\n\t\t.b,\n\t\t.sel_b1,\n\t\t.sel_b2,\n\t\t.out_assign(out_assign_dut),\n\t\t.out_always(out_always_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out_assign) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_assign\", stats1.errors_out_assign, stats1.errortime_out_assign);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_assign\");\n\t\tif (stats1.errors_out_always) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_always\", stats1.errors_out_always, stats1.errortime_out_always);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_always\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_assign_ref, out_always_ref } === ( { out_assign_ref, out_always_ref } ^ { out_assign_dut, out_always_dut } ^ { out_assign_ref, out_always_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_assign_ref !== ( out_assign_ref ^ out_assign_dut ^ out_assign_ref ))\n\t\tbegin if (stats1.errors_out_assign == 0) stats1.errortime_out_assign = $time;\n\t\t\tstats1.errors_out_assign = stats1.errors_out_assign+1'b1; end\n\t\tif (out_always_ref !== ( out_always_ref ^ out_always_dut ^ out_always_ref ))\n\t\tbegin if (stats1.errors_out_always == 0) stats1.errortime_out_always = $time;\n\t\t\tstats1.errors_out_always = stats1.errors_out_always+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "kmap1", "task_number": 91, "description": "Implement the circuit described by the Karnaugh map below.\n//        a\n// bc   0 1 \n//  00 | 0 | 1 |\n//  01 | 1 | 1 | \n//  11 | 1 | 1 | \n//  10 | 1 | 1 | \n", "header": "module top_module(\n\tinput a, \n\tinput b,\n\tinput c,\n\toutput out\n);\n", "module_code": "module top_module(\n\tinput a, \n\tinput b,\n\tinput c,\n\toutput out\n);\n\t\n\tassign out = (a | b | c);\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput a, \n\tinput b,\n\tinput c,\n\toutput out\n);\n\t\n\tassign out = (a | b | c);\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg a, b, c,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\tint count; count = 0;\n\t\t{a,b,c} <= 1'b0;\n\t\twavedrom_start();\n\t\trepeat(10) @(posedge clk)\n\t\t\t{a,b,c} <= count++;\t\t\n\t\twavedrom_stop();\n\t\t\n\t\trepeat(200) @(posedge clk, negedge clk)\n\t\t\t{c,b,a} <= $urandom;\n\t\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic a;\n\tlogic b;\n\tlogic c;\n\tlogic out_ref;\n\tlogic out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,a,b,c,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.a,\n\t\t.b,\n\t\t.c );\n\treference_module good1 (\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "2013_q2afsm", "task_number": 92, "description": "Consider the FSM described by the state diagram shown below:\n\n// A --r1=0,r2=0,r3=0--> A\n// A --r1=1--> B\n// A --r1=0,r2=1--> C\n// A --r1=0,r2=0,r3=0--> D\n// B (g1=1) --r1=1--> B\n// B (g1=1) --r1=0--> A\n// C (g2=1) --r2=1--> C\n// C (g2=1) --r2=0--> A\n\n// Resetn is an active-low synchronous reset that resets into state A. This FSM acts as an arbiter circuit, which controls access to some type of resource by three requesting devices. Each device makes its request for the resource by setting a signal _r[i]_ = 1, where _r[i]_ is either _r[1]_, _r[2]_, or _r[3]_. Each r[i] is an input signal to the FSM, and represents one of the three devices. The FSM stays in state _A_ as long as there are no requests. When one or more request occurs, then the FSM decides which device receives a grant to use the resource and changes to a state that sets that device's _g[i]_ signal to 1. Each _g[i]_ is an output from the FSM. There is a priority system, in that device 1 has a higher priority than device 2, and device 3 has the lowest priority. Hence, for example, device 3 will only receive a grant if it is the only device making a request when the FSM is in state _A_. Once a device, _i_, is given a grant by the FSM, that device continues to receive the grant as long as its request, _r[i]_ = 1.\n\n// Write complete Verilog code that represents this FSM. Use separate always blocks for the state table and the state flip-flops, as done in lectures. Describe the FSM outputs, _g[i]_, using either continuous assignment statement(s) or an always block (at your discretion). Assign any state codes that you wish to use.", "header": "module top_module (\n\tinput clk,\n\tinput resetn,\n\tinput [3:1] r,\n\toutput [3:1] g\n);\n", "module_code": "module top_module (\n\tinput clk,\n\tinput resetn,\n\tinput [3:1] r,\n\toutput [3:1] g\n);\n\tparameter A=0, B=1, C=2, D=3;\n\treg [1:0] state, next;\n\n\talways @(posedge clk) begin\n\t\tif (~resetn) state <= A;\n\t\telse state <= next;\n\tend\n\t\n\talways@(state,r) begin\n\t\tcase (state)\n\t\t\tA: if (r[1]) next = B;\n\t\t\t   else if (r[2]) next = C;\n\t\t\t   else if (r[3]) next = D;\n\t\t\t   else next = A;\n\t\t\tB: next = r[1] ? B : A;\n\t\t\tC: next = r[2] ? C : A;\n\t\t\tD: next = r[3] ? D : A;\n\t\t\tdefault: next = 'x;\n\t\tendcase\n\tend\n\t    \n\tassign g[1] = (state == B);\t\n\tassign g[2] = (state == C);\t\n\tassign g[3] = (state == D);\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput resetn,\n\tinput [3:1] r,\n\toutput [3:1] g\n);\n\tparameter A=0, B=1, C=2, D=3;\n\treg [1:0] state, next;\n\n\talways @(posedge clk) begin\n\t\tif (~resetn) state <= A;\n\t\telse state <= next;\n\tend\n\t\n\talways@(state,r) begin\n\t\tcase (state)\n\t\t\tA: if (r[1]) next = B;\n\t\t\t   else if (r[2]) next = C;\n\t\t\t   else if (r[3]) next = D;\n\t\t\t   else next = A;\n\t\t\tB: next = r[1] ? B : A;\n\t\t\tC: next = r[2] ? C : A;\n\t\t\tD: next = r[3] ? D : A;\n\t\t\tdefault: next = 'x;\n\t\tendcase\n\tend\n\t    \n\tassign g[1] = (state == B);\t\n\tassign g[2] = (state == C);\t\n\tassign g[3] = (state == D);\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic resetn,\n\toutput logic [3:1] r,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\tinput tb_match\n);\n\treg reset;\n\tassign resetn = ~reset;\n\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\tinitial begin\n\t\treset <= 1;\n\t\tr <= 0;\n\t\t@(posedge clk);\n\t\t\n\t\tr <= 1;\n\t\treset_test();\n\t\t\n\t\tr <= 0;\n\t\twavedrom_start(\"\");\n\t\t@(posedge clk) r <= 0;\n\t\t@(posedge clk) r <= 7;\n\t\t@(posedge clk) r <= 7;\n\t\t@(posedge clk) r <= 7;\n\t\t@(posedge clk) r <= 6;\n\t\t@(posedge clk) r <= 6;\n\t\t@(posedge clk) r <= 6;\n\t\t@(posedge clk) r <= 4;\n\t\t@(posedge clk) r <= 4;\n\t\t@(posedge clk) r <= 4;\n\t\t@(posedge clk) r <= 0;\n\t\t@(posedge clk) r <= 0;\n\t\t@(posedge clk) r <= 4;\n\t\t@(posedge clk) r <= 6;\n\t\t@(posedge clk) r <= 7;\n\t\t@(posedge clk) r <= 7;\n\t\t@(posedge clk) r <= 7;\n\t\t@(negedge clk);\n\t\twavedrom_stop();\n\t\t\n\t\t@(posedge clk);\n\t\treset <= 0;\n\t\t@(posedge clk);\n\t\t@(posedge clk);\n\t\t\n\t\trepeat(500) @(negedge clk) begin\n\t\t\treset <= ($random & 63) == 0;\n\t\t\tr <= $random;\n\t\tend\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_g;\n\t\tint errortime_g;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic resetn;\n\tlogic [3:1] r;\n\tlogic [3:1] g_ref;\n\tlogic [3:1] g_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,resetn,r,g_ref,g_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.resetn,\n\t\t.r );\n\treference_module good1 (\n\t\t.clk,\n\t\t.resetn,\n\t\t.r,\n\t\t.g(g_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.resetn,\n\t\t.r,\n\t\t.g(g_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_g) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"g\", stats1.errors_g, stats1.errortime_g);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"g\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { g_ref } === ( { g_ref } ^ { g_dut } ^ { g_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (g_ref !== ( g_ref ^ g_dut ^ g_ref ))\n\t\tbegin if (stats1.errors_g == 0) stats1.errortime_g = $time;\n\t\t\tstats1.errors_g = stats1.errors_g+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "count10", "task_number": 93, "description": "Build a decade counter that counts from 0 through 9, inclusive, with a period of 10. The reset input is active high synchronous, and should reset the counter to 0.", "header": "module top_module(\n\tinput clk,\n\tinput reset,\n\toutput reg [3:0] q);\n", "module_code": "module top_module(\n\tinput clk,\n\tinput reset,\n\toutput reg [3:0] q);\n\t\n\talways @(posedge clk)\n\t\tif (reset || q == 9)\n\t\t\tq <= 0;\n\t\telse\n\t\t\tq <= q+1;\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput clk,\n\tinput reset,\n\toutput reg [3:0] q);\n\t\n\talways @(posedge clk)\n\t\tif (reset || q == 9)\n\t\t\tq <= 0;\n\t\telse\n\t\t\tq <= q+1;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg reset,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\tinput tb_match\t\n);\n\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\t\n\tinitial begin\n\t\treset <= 1;\n\t\twavedrom_start(\"Synchronous reset and counting\");\n\t\treset_test();\n\t\trepeat(12) @(posedge clk);\n\t\twavedrom_stop();\n\t\t@(posedge clk);\n\t\t\n\t\trepeat(400) @(posedge clk, negedge clk) begin\n\t\t\treset <= !($random & 31);\n\t\tend\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_q;\n\t\tint errortime_q;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic reset;\n\tlogic [3:0] q_ref;\n\tlogic [3:0] q_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,q_ref,q_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.reset );\n\treference_module good1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.q(q_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.q(q_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"q\", stats1.errors_q, stats1.errortime_q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"q\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (q_ref !== ( q_ref ^ q_dut ^ q_ref ))\n\t\tbegin if (stats1.errors_q == 0) stats1.errortime_q = $time;\n\t\t\tstats1.errors_q = stats1.errors_q+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "fsm_ps2", "task_number": 94, "description": "The PS/2 mouse protocol sends messages that are three bytes long. However, within a continuous byte stream, it's not obvious where messages start and end. The only indication is that the first byte of each three byte message always has in[3]=1 (but in[3] of the other two bytes may be 1 or 0 depending on data). We want a finite state machine that will search for message boundaries when given an input byte stream. The algorithm we'll use is to discard bytes until we see one with in[3]=1. We then assume that this is byte 1 of a message, and signal the receipt of a message once all 3 bytes have been received (done). The FSM should signal done in the cycle immediately after the third byte of each message was successfully received. Reset should be active high synchronous.", "header": "module top_module (\n\tinput clk,\n\tinput [7:0] in,\n\tinput reset,\n\toutput done\n);\n", "module_code": "module top_module (\n\tinput clk,\n\tinput [7:0] in,\n\tinput reset,\n\toutput done\n);\n\tparameter BYTE1=0, BYTE2=1, BYTE3=2, DONE=3;\n\treg [1:0] state;\n\treg [1:0] next;\n    \n    wire in3 = in[3];\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tBYTE1: next = in3 ? BYTE2 : BYTE1;\n\t\t\tBYTE2: next = BYTE3;\n\t\t\tBYTE3: next = DONE;\n\t\t\tDONE: next = in3 ? BYTE2 : BYTE1;\n\t\tendcase\n    end\n    \n    always @(posedge clk) begin\n\t\tif (reset) state <= BYTE1;\n        else state <= next;\n\tend\n\t\t\n\tassign done = (state==DONE);\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput [7:0] in,\n\tinput reset,\n\toutput done\n);\n\tparameter BYTE1=0, BYTE2=1, BYTE3=2, DONE=3;\n\treg [1:0] state;\n\treg [1:0] next;\n    \n    wire in3 = in[3];\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tBYTE1: next = in3 ? BYTE2 : BYTE1;\n\t\t\tBYTE2: next = BYTE3;\n\t\t\tBYTE3: next = DONE;\n\t\t\tDONE: next = in3 ? BYTE2 : BYTE1;\n\t\tendcase\n    end\n    \n    always @(posedge clk) begin\n\t\tif (reset) state <= BYTE1;\n        else state <= next;\n\tend\n\t\t\n\tassign done = (state==DONE);\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic [7:0] in,\n\toutput logic reset\n);\n\n\tinitial begin\n\t\trepeat(200) @(negedge clk) begin\n\t\t\tin <= $random;\n\t\t\treset <= !($random & 31);\n\t\tend\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_done;\n\t\tint errortime_done;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [7:0] in;\n\tlogic reset;\n\tlogic done_ref;\n\tlogic done_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,in,reset,done_ref,done_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in,\n\t\t.reset );\n\treference_module good1 (\n\t\t.clk,\n\t\t.in,\n\t\t.reset,\n\t\t.done(done_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.in,\n\t\t.reset,\n\t\t.done(done_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_done) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"done\", stats1.errors_done, stats1.errortime_done);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"done\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { done_ref } === ( { done_ref } ^ { done_dut } ^ { done_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (done_ref !== ( done_ref ^ done_dut ^ done_ref ))\n\t\tbegin if (stats1.errors_done == 0) stats1.errortime_done = $time;\n\t\t\tstats1.errors_done = stats1.errors_done+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "mux2to1", "task_number": 95, "description": "Create a one-bit wide, 2-to-1 multiplexer. When sel=0, choose a. When sel=1, choose b.", "header": "module top_module (\n\tinput a,\n\tinput b,\n\tinput sel,\n\toutput out\n);\n", "module_code": "module top_module (\n\tinput a,\n\tinput b,\n\tinput sel,\n\toutput out\n);\n\n\tassign out = sel ? b : a;\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput a,\n\tinput b,\n\tinput sel,\n\toutput out\n);\n\n\tassign out = sel ? b : a;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic a,b,sel,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\t{a, b, sel} <= 3'b000;\n\t\t@(negedge clk) wavedrom_start(\"<b>Sel</b> chooses between <b>a</b> and <b>b</b>\");\n\t\t\t@(posedge clk) {a, b, sel} <= 3'b000;\n\t\t\t@(posedge clk) {a, b, sel} <= 3'b100;\n\t\t\t@(posedge clk) {a, b, sel} <= 3'b110;\n\t\t\t@(posedge clk) {a, b, sel} <= 3'b111;\n\t\t\t@(posedge clk) {a, b, sel} <= 3'b011;\n\t\t\t@(posedge clk) {a, b, sel} <= 3'b001;\n\t\t\t@(posedge clk) {a, b, sel} <= 3'b100;\n\t\t\t@(posedge clk) {a, b, sel} <= 3'b101;\n\t\t\t@(posedge clk) {a, b, sel} <= 3'b110;\n\t\t\t@(posedge clk) {a, b, sel} <= 3'b111;\n\t\t@(negedge clk) wavedrom_stop();\n\t\trepeat(100) @(posedge clk, negedge clk)\n\t\t\t{a,b,sel} <= $random;\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic a;\n\tlogic b;\n\tlogic sel;\n\tlogic out_ref;\n\tlogic out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,a,b,sel,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.a,\n\t\t.b,\n\t\t.sel );\n\treference_module good1 (\n\t\t.a,\n\t\t.b,\n\t\t.sel,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.a,\n\t\t.b,\n\t\t.sel,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "gates4", "task_number": 96, "description": "Build a combinational circuit with four inputs, in[3:0]. There are 3 outputs: \n// (1) out_and: output of a 4-input AND gate. \n// (2) out_or: output of a 4-input OR gate. \n// (3) out_xor: output of a 4-input XOR gate.\n", "header": "module top_module (\n\tinput [3:0] in,\n\toutput out_and,\n\toutput out_or,\n\toutput out_xor\n);\n", "module_code": "module top_module (\n\tinput [3:0] in,\n\toutput out_and,\n\toutput out_or,\n\toutput out_xor\n);\n\n\tassign out_and = &in;\n\tassign out_or = |in;\n\tassign out_xor = ^in;\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [3:0] in,\n\toutput out_and,\n\toutput out_or,\n\toutput out_xor\n);\n\n\tassign out_and = &in;\n\tassign out_or = |in;\n\tassign out_xor = ^in;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic [3:0] in,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\tinitial begin\n\t\tin <= 0;\n\t\t@(negedge clk) wavedrom_start(\"All combinations\");\n\t\t\t@(posedge clk);\n\t\t\trepeat(15) @(posedge clk) in <= in + 1;\n\t\t@(negedge clk) wavedrom_stop();\t\t\n\t\trepeat(200) @(posedge clk, negedge clk)\n\t\t\tin <= $random;\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out_and;\n\t\tint errortime_out_and;\n\t\tint errors_out_or;\n\t\tint errortime_out_or;\n\t\tint errors_out_xor;\n\t\tint errortime_out_xor;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [3:0] in;\n\tlogic out_and_ref;\n\tlogic out_and_dut;\n\tlogic out_or_ref;\n\tlogic out_or_dut;\n\tlogic out_xor_ref;\n\tlogic out_xor_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,in,out_and_ref,out_and_dut,out_or_ref,out_or_dut,out_xor_ref,out_xor_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in );\n\treference_module good1 (\n\t\t.in,\n\t\t.out_and(out_and_ref),\n\t\t.out_or(out_or_ref),\n\t\t.out_xor(out_xor_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.in,\n\t\t.out_and(out_and_dut),\n\t\t.out_or(out_or_dut),\n\t\t.out_xor(out_xor_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out_and) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_and\", stats1.errors_out_and, stats1.errortime_out_and);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_and\");\n\t\tif (stats1.errors_out_or) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_or\", stats1.errors_out_or, stats1.errortime_out_or);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_or\");\n\t\tif (stats1.errors_out_xor) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_xor\", stats1.errors_out_xor, stats1.errortime_out_xor);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_xor\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_and_ref, out_or_ref, out_xor_ref } === ( { out_and_ref, out_or_ref, out_xor_ref } ^ { out_and_dut, out_or_dut, out_xor_dut } ^ { out_and_ref, out_or_ref, out_xor_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_and_ref !== ( out_and_ref ^ out_and_dut ^ out_and_ref ))\n\t\tbegin if (stats1.errors_out_and == 0) stats1.errortime_out_and = $time;\n\t\t\tstats1.errors_out_and = stats1.errors_out_and+1'b1; end\n\t\tif (out_or_ref !== ( out_or_ref ^ out_or_dut ^ out_or_ref ))\n\t\tbegin if (stats1.errors_out_or == 0) stats1.errortime_out_or = $time;\n\t\t\tstats1.errors_out_or = stats1.errors_out_or+1'b1; end\n\t\tif (out_xor_ref !== ( out_xor_ref ^ out_xor_dut ^ out_xor_ref ))\n\t\tbegin if (stats1.errors_out_xor == 0) stats1.errortime_out_xor = $time;\n\t\t\tstats1.errors_out_xor = stats1.errors_out_xor+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "2014_q3bfsm", "task_number": 97, "description": "Given the state-assigned table shown below, implement the finite-state machine. Reset should synchronous active high reset the FSM to state 000.\n\n// Present state y[2:0] | Next state y[2:0] x=0, Next state y[2:0] x=1, Output z\n// 000 | 000, 001 | 0\n// 001 | 001, 100 | 0\n// 010 | 010, 001 | 0\n// 011 | 001, 010 | 1\n// 100 | 011, 100 | 1\n", "header": "module top_module (\n\tinput clk,\n\tinput reset,\n\tinput x,\n\toutput reg z\n);\n", "module_code": "module top_module (\n\tinput clk,\n\tinput reset,\n\tinput x,\n\toutput reg z\n);\n\tparameter A=0, B=1, C=2, D=3, E=4;\n\treg [2:0] state, next;\n\n\talways @(posedge clk) begin\n\t\tif (reset) state <= A;\n\t\telse state <= next;\n\tend\n\t\n\talways_comb begin\n\t\tcase (state)\n\t\t\tA: next = x ? B : A;\n\t\t\tB: next = x ? E : B;\n\t\t\tC: next = x ? B : C;\n\t\t\tD: next = x ? C : B;\n\t\t\tE: next = x ? E : D;\t\t\n\t\t\tdefault: next = 'x;\n\t\tendcase\n\tend\n\t    \n\tassign z = (state == D) || (state == E);\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput reset,\n\tinput x,\n\toutput reg z\n);\n\tparameter A=0, B=1, C=2, D=3, E=4;\n\treg [2:0] state, next;\n\n\talways @(posedge clk) begin\n\t\tif (reset) state <= A;\n\t\telse state <= next;\n\tend\n\t\n\talways_comb begin\n\t\tcase (state)\n\t\t\tA: next = x ? B : A;\n\t\t\tB: next = x ? E : B;\n\t\t\tC: next = x ? B : C;\n\t\t\tD: next = x ? C : B;\n\t\t\tE: next = x ? E : D;\t\t\n\t\t\tdefault: next = 'x;\n\t\tendcase\n\tend\n\t    \n\tassign z = (state == D) || (state == E);\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic reset,\n\toutput logic x\n);\n\n\tinitial begin\n\t\treset = 1;\n\t\tx = 0;\n\t\t@(posedge clk);\n\t\t@(posedge clk);\n\t\treset = 0;\n\t\t@(posedge clk);\n\t\t@(posedge clk);\n\t\t\n\t\trepeat(500) @(negedge clk) begin\n\t\t\treset <= !($random & 63);\n\t\t\tx <= $random;\n\t\tend\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_z;\n\t\tint errortime_z;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic reset;\n\tlogic x;\n\tlogic z_ref;\n\tlogic z_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,x,z_ref,z_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.reset,\n\t\t.x );\n\treference_module good1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.x,\n\t\t.z(z_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.x,\n\t\t.z(z_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_z) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"z\", stats1.errors_z, stats1.errortime_z);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"z\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { z_ref } === ( { z_ref } ^ { z_dut } ^ { z_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (z_ref !== ( z_ref ^ z_dut ^ z_ref ))\n\t\tbegin if (stats1.errors_z == 0) stats1.errortime_z = $time;\n\t\t\tstats1.errors_z = stats1.errors_z+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "2013_q2bfsm", "task_number": 98, "description": "Consider a finite state machine that is used to control some type of motor. The FSM has inputs x and y, which come from the motor, and produces outputs f and g, which control the motor. There is also a clock input called clk and a reset input (synchronous, active low) called resetn. The FSM has to work as follows. As long as the reset input is asserted, the FSM stays in a beginning state, called state A. When the reset signal is de-asserted, then after the next clock edge the FSM has to set the output f to 1 for one clock cycle. Then, the FSM has to monitor the x input. When x has produced the values 1, 0, 1 in three successive clock cycles, then g should be set to 1 on the following clock cycle. While maintaining g = 1 the FSM has to monitor the y input. If y has the value 1 within at most two clock cycles, then the FSM should maintain g = 1 permanently (that is, until reset). But if y does not become 1 within two clock cycles, then the FSM should set g = 0 permanently (until reset).", "header": "module top_module (\n\tinput clk,\n\tinput resetn,\n\tinput x,\n\tinput y,\n\toutput f,\n\toutput g\n);\n", "module_code": "module top_module (\n\tinput clk,\n\tinput resetn,\n\tinput x,\n\tinput y,\n\toutput f,\n\toutput g\n);\n\tparameter A=0, B=1, S0=2, S1=3, S10=4, G1=5, G2=6, P0=7, P1=8;\n\treg [3:0] state, next;\n\n\talways @(posedge clk) begin\n\t\tif (~resetn) state <= A;\n\t\telse state <= next;\n\tend\n\t\n\talways_comb begin\n\t\tcase (state)\n\t\t\tA: next = B;\n\t\t\tB: next = S0;\n\t\t\tS0: next = x ? S1 : S0;\n\t\t\tS1: next = x ? S1 : S10;\n\t\t\tS10: next = x? G1 : S0;\n\t\t\tG1: next = y ? P1 : G2;\n\t\t\tG2: next = y ? P1 : P0;\n\t\t\tP0: next = P0;\n\t\t\tP1: next = P1;\n\t\t\tdefault: next = 'x;\n\t\tendcase\n\tend\n\t    \n\tassign f = (state == B);\n\tassign g = (state == G1) || (state == G2) || (state == P1);\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput resetn,\n\tinput x,\n\tinput y,\n\toutput f,\n\toutput g\n);\n\tparameter A=0, B=1, S0=2, S1=3, S10=4, G1=5, G2=6, P0=7, P1=8;\n\treg [3:0] state, next;\n\n\talways @(posedge clk) begin\n\t\tif (~resetn) state <= A;\n\t\telse state <= next;\n\tend\n\t\n\talways_comb begin\n\t\tcase (state)\n\t\t\tA: next = B;\n\t\t\tB: next = S0;\n\t\t\tS0: next = x ? S1 : S0;\n\t\t\tS1: next = x ? S1 : S10;\n\t\t\tS10: next = x? G1 : S0;\n\t\t\tG1: next = y ? P1 : G2;\n\t\t\tG2: next = y ? P1 : P0;\n\t\t\tP0: next = P0;\n\t\t\tP1: next = P1;\n\t\t\tdefault: next = 'x;\n\t\tendcase\n\tend\n\t    \n\tassign f = (state == B);\n\tassign g = (state == G1) || (state == G2) || (state == P1);\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic resetn,\n\toutput logic x, y\n);\n\n\tinitial begin\n\t\tresetn = 0;\n\t\tx = 0;\n\t\ty = 0;\n\t\t@(posedge clk);\n\t\t@(posedge clk);\n\t\tresetn = 1;\n\t\trepeat(500) @(negedge clk) begin\n\t\t\tresetn <= ($random & 31) != 0;\n\t\t\t{x,y} <= $random;\n\t\tend\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_f;\n\t\tint errortime_f;\n\t\tint errors_g;\n\t\tint errortime_g;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic resetn;\n\tlogic x;\n\tlogic y;\n\tlogic f_ref;\n\tlogic f_dut;\n\tlogic g_ref;\n\tlogic g_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,resetn,x,y,f_ref,f_dut,g_ref,g_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.resetn,\n\t\t.x,\n\t\t.y );\n\treference_module good1 (\n\t\t.clk,\n\t\t.resetn,\n\t\t.x,\n\t\t.y,\n\t\t.f(f_ref),\n\t\t.g(g_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.resetn,\n\t\t.x,\n\t\t.y,\n\t\t.f(f_dut),\n\t\t.g(g_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_f) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"f\", stats1.errors_f, stats1.errortime_f);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"f\");\n\t\tif (stats1.errors_g) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"g\", stats1.errors_g, stats1.errortime_g);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"g\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { f_ref, g_ref } === ( { f_ref, g_ref } ^ { f_dut, g_dut } ^ { f_ref, g_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (f_ref !== ( f_ref ^ f_dut ^ f_ref ))\n\t\tbegin if (stats1.errors_f == 0) stats1.errortime_f = $time;\n\t\t\tstats1.errors_f = stats1.errors_f+1'b1; end\n\t\tif (g_ref !== ( g_ref ^ g_dut ^ g_ref ))\n\t\tbegin if (stats1.errors_g == 0) stats1.errortime_g = $time;\n\t\t\tstats1.errors_g = stats1.errors_g+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "dff8p", "task_number": 99, "description": "Create 8 D flip-flops with active high synchronous reset. The flip-flops must be reset to 0x34 rather than zero. All DFFs should be triggered by the negative edge of clk.", "header": "module top_module(\n\tinput clk,\n\tinput [7:0] d,\n\tinput reset,\n\toutput reg [7:0] q);\n", "module_code": "module top_module(\n\tinput clk,\n\tinput [7:0] d,\n\tinput reset,\n\toutput reg [7:0] q);\n\t\n\talways @(negedge clk)\n\t\tif (reset)\n\t\t\tq <= 8'h34;\n\t\telse\n\t\t\tq <= d;\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput clk,\n\tinput [7:0] d,\n\tinput reset,\n\toutput reg [7:0] q);\n\t\n\talways @(negedge clk)\n\t\tif (reset)\n\t\t\tq <= 8'h34;\n\t\telse\n\t\t\tq <= d;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg [7:0] d, output reg reset,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\tinput tb_match\t\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\t\n\t\n\tinitial begin\n\t\treset <= 1;\n\t\td <= $random;\n\t\t@(negedge clk);\n\t\t@(negedge clk);\n\t\twavedrom_start(\"Synchronous active-high reset\");\n\t\treset_test();\n\t\trepeat(10) @(negedge clk)\n\t\t\td <= $random;\n\t\twavedrom_stop();\n\n\n\t\trepeat(400) @(posedge clk, negedge clk) begin\n\t\t\treset <= !($random & 15);\n\t\t\td <= $random;\n\t\tend\n\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_q;\n\t\tint errortime_q;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [7:0] d;\n\tlogic reset;\n\tlogic [7:0] q_ref;\n\tlogic [7:0] q_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,d,reset,q_ref,q_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.d,\n\t\t.reset );\n\treference_module good1 (\n\t\t.clk,\n\t\t.d,\n\t\t.reset,\n\t\t.q(q_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.d,\n\t\t.reset,\n\t\t.q(q_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"q\", stats1.errors_q, stats1.errortime_q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"q\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (q_ref !== ( q_ref ^ q_dut ^ q_ref ))\n\t\tbegin if (stats1.errors_q == 0) stats1.errortime_q = $time;\n\t\t\tstats1.errors_q = stats1.errors_q+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "reduction", "task_number": 100, "description": "Parity checking is often used as a simple method of detecting errors when transmitting data through an imperfect channel. Create a circuit that will compute a parity bit for a 8-bit byte (which will add a 9th bit to the byte). We will use \"even\" parity, where the parity bit is just the XOR of all 8 data bits.", "header": "module top_module (\n\tinput [7:0] in,\n\toutput parity\n);\n", "module_code": "module top_module (\n\tinput [7:0] in,\n\toutput parity\n);\n\n\tassign parity = ^in;\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [7:0] in,\n\toutput parity\n);\n\n\tassign parity = ^in;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic [7:0] in\n);\n\n\tinitial begin\n\t\trepeat(100) @(posedge clk, negedge clk)\n\t\t\tin <= $random;\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_parity;\n\t\tint errortime_parity;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [7:0] in;\n\tlogic parity_ref;\n\tlogic parity_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,in,parity_ref,parity_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in );\n\treference_module good1 (\n\t\t.in,\n\t\t.parity(parity_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.in,\n\t\t.parity(parity_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_parity) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"parity\", stats1.errors_parity, stats1.errortime_parity);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"parity\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { parity_ref } === ( { parity_ref } ^ { parity_dut } ^ { parity_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (parity_ref !== ( parity_ref ^ parity_dut ^ parity_ref ))\n\t\tbegin if (stats1.errors_parity == 0) stats1.errortime_parity = $time;\n\t\t\tstats1.errors_parity = stats1.errors_parity+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "fsm3comb", "task_number": 101, "description": "The following is the state transition table for a Moore state machine with one input, one output, and four states. Use the following state encoding: A=2'b00, B=2'b01, C=2'b10, D=2'b11.Implement only the state transition logic and output logic (the combinational logic portion) for this state machine. Given the current state (state), compute the next_state and output (out) based on the state transition table.\n// State | Next state in=0, Next state in=1 | Output\n// A | A, B | 0\n// B | C, B | 0\n// C | A, D | 0\n// D | C, B | 1", "header": "module top_module (\n\tinput in,\n\tinput [1:0] state,\n\toutput reg [1:0] next_state,\n\toutput out\n);\n", "module_code": "module top_module (\n\tinput in,\n\tinput [1:0] state,\n\toutput reg [1:0] next_state,\n\toutput out\n);\n\tparameter A=0, B=1, C=2, D=3;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tA: next_state = in ? B : A;\n\t\t\tB: next_state = in ? B : C;\n\t\t\tC: next_state = in ? D : A;\n\t\t\tD: next_state = in ? B : C;\n\t\tendcase\n    end\n    \n\tassign out = (state==D);\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput in,\n\tinput [1:0] state,\n\toutput reg [1:0] next_state,\n\toutput out\n);\n\tparameter A=0, B=1, C=2, D=3;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tA: next_state = in ? B : A;\n\t\t\tB: next_state = in ? B : C;\n\t\t\tC: next_state = in ? D : A;\n\t\t\tD: next_state = in ? B : C;\n\t\tendcase\n    end\n    \n\tassign out = (state==D);\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic in,\n\toutput logic [1:0] state\n);\n\n\tinitial begin\n\t\trepeat(100) @(posedge clk, negedge clk) begin\n\t\t\tin <= $random;\n\t\t\tstate <= $random;\n\t\tend\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_next_state;\n\t\tint errortime_next_state;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic in;\n\tlogic [1:0] state;\n\tlogic [1:0] next_state_ref;\n\tlogic [1:0] next_state_dut;\n\tlogic out_ref;\n\tlogic out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,in,state,next_state_ref,next_state_dut,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in,\n\t\t.state );\n\treference_module good1 (\n\t\t.in,\n\t\t.state,\n\t\t.next_state(next_state_ref),\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.in,\n\t\t.state,\n\t\t.next_state(next_state_dut),\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_next_state) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"next_state\", stats1.errors_next_state, stats1.errortime_next_state);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"next_state\");\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { next_state_ref, out_ref } === ( { next_state_ref, out_ref } ^ { next_state_dut, out_dut } ^ { next_state_ref, out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (next_state_ref !== ( next_state_ref ^ next_state_dut ^ next_state_ref ))\n\t\tbegin if (stats1.errors_next_state == 0) stats1.errortime_next_state = $time;\n\t\t\tstats1.errors_next_state = stats1.errors_next_state+1'b1; end\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "mt2015_q4b", "task_number": 102, "description": "The module can be described by the following simulation waveform: \n\n// time            x               y               z               \n// 0ns             0               0               1               \n// 5ns             0               0               1               \n// 10ns            0               0               1               \n// 15ns            0               0               1               \n// 20ns            0               0               1               \n// 25ns            1               0               0               \n// 30ns            1               0               0               \n// 35ns            0               1               0               \n// 40ns            0               1               0               \n// 45ns            1               1               1               \n// 50ns            1               1               1               \n// 55ns            0               0               1               \n// 60ns            0               1               0               \n// 65ns            0               1               0               \n// 70ns            1               1               1               \n// 75ns            0               1               0               \n// 80ns            0               1               0               \n// 85ns            0               1               0               \n// 90ns            1               0               0               ", "header": "module top_module(\n\tinput x,\n\tinput y,\n\toutput z);\n", "module_code": "module top_module(\n\tinput x,\n\tinput y,\n\toutput z);\n\n\tassign z = ~(x^y);\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput x,\n\tinput y,\n\toutput z);\n\n\tassign z = ~(x^y);\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic x,\n\toutput logic y,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\tinitial begin\n\t\t{x,y} <= 0;\n\t\t@(negedge clk) wavedrom_start();\n\t\t\t@(posedge clk) {y,x} <= 0;\n\t\t\t@(posedge clk) {y,x} <= 1;\n\t\t\t@(posedge clk) {y,x} <= 2;\n\t\t\t@(posedge clk) {y,x} <= 3;\n\t\t@(negedge clk) wavedrom_stop();\n\t\trepeat(100) @(posedge clk, negedge clk)\n\t\t\t{x, y} <= $random % 4;\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_z;\n\t\tint errortime_z;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic x;\n\tlogic y;\n\tlogic z_ref;\n\tlogic z_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,x,y,z_ref,z_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.x,\n\t\t.y );\n\treference_module good1 (\n\t\t.x,\n\t\t.y,\n\t\t.z(z_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.x,\n\t\t.y,\n\t\t.z(z_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_z) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"z\", stats1.errors_z, stats1.errortime_z);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"z\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { z_ref } === ( { z_ref } ^ { z_dut } ^ { z_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (z_ref !== ( z_ref ^ z_dut ^ z_ref ))\n\t\tbegin if (stats1.errors_z == 0) stats1.errortime_z = $time;\n\t\t\tstats1.errors_z = stats1.errors_z+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "2012_q2fsm", "task_number": 103, "description": "Consider the state machine shown below:\n\n// A (0) --1--> B\n// A (0) --0--> A\n// B (0) --1--> C\n// B (0) --0--> D\n// C (0) --1--> E\n// C (0) --0--> D\n// D (0) --1--> F\n// D (0) --0--> A\n// E (1) --1--> E\n// E (1) --0--> D\n// F (1) --1--> C\n// F (1) --0--> D\n\n// Reset resets into state A and is synchronous active-high. \n\n// Write complete Verilog code that represents this FSM. Use separate **always** blocks for the state table and the state flip-flops. Describe the FSM output, which is called _z_, using either continuous assignment statement(s) or an **always** block (at your discretion). Assign any state codes that you wish to use.", "header": "module top_module (\n\tinput clk,\n\tinput reset,\n\tinput w,\n\toutput z\n);\n", "module_code": "module top_module (\n\tinput clk,\n\tinput reset,\n\tinput w,\n\toutput z\n);\n\tparameter A=0,B=1,C=2,D=3,E=4,F=5;\n\treg[2:0] state, next;\n\t\n\talways @(posedge clk)\n\t\tif (reset) state <= A;\n\t\telse state <= next;\n\t\t\n\t\t\n\talways_comb begin\n\t\tcase (state)\n\t\t\tA: next = w ? B : A;\n\t\t\tB: next = w ? C : D;\n\t\t\tC: next = w ? E : D;\n\t\t\tD: next = w ? F : A;\n\t\t\tE: next = w ? E : D;\n\t\t\tF: next = w ? C : D;\n\t\t\tdefault: next = 'x;\n\t\tendcase\n\tend\n\t\n\tassign z = (state == E) || (state == F);\n\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput reset,\n\tinput w,\n\toutput z\n);\n\tparameter A=0,B=1,C=2,D=3,E=4,F=5;\n\treg[2:0] state, next;\n\t\n\talways @(posedge clk)\n\t\tif (reset) state <= A;\n\t\telse state <= next;\n\t\t\n\t\t\n\talways_comb begin\n\t\tcase (state)\n\t\t\tA: next = w ? B : A;\n\t\t\tB: next = w ? C : D;\n\t\t\tC: next = w ? E : D;\n\t\t\tD: next = w ? F : A;\n\t\t\tE: next = w ? E : D;\n\t\t\tF: next = w ? C : D;\n\t\t\tdefault: next = 'x;\n\t\tendcase\n\tend\n\t\n\tassign z = (state == E) || (state == F);\n\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic reset,\n\toutput logic w\n);\n\n\tinitial begin\n\t\trepeat(200) @(negedge clk) begin\n\t\t\treset <= ($random & 'h1f) == 0;\n\t\t\tw <= $random;\n\t\tend\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_z;\n\t\tint errortime_z;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic reset;\n\tlogic w;\n\tlogic z_ref;\n\tlogic z_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,w,z_ref,z_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.reset,\n\t\t.w );\n\treference_module good1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.w,\n\t\t.z(z_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.w,\n\t\t.z(z_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_z) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"z\", stats1.errors_z, stats1.errortime_z);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"z\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { z_ref } === ( { z_ref } ^ { z_dut } ^ { z_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (z_ref !== ( z_ref ^ z_dut ^ z_ref ))\n\t\tbegin if (stats1.errors_z == 0) stats1.errortime_z = $time;\n\t\t\tstats1.errors_z = stats1.errors_z+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "dff16e", "task_number": 104, "description": "Create 16 D flip-flops. It's sometimes useful to only modify parts of a group of flip-flops. The byte-enable inputs control whether each byte of the 16 registers should be written to on that cycle. byteena[1] controls the upper byte d[15:8], while byteena[0] controls the lower byte d[7:0]. resetn is a synchronous, active-low reset. All DFFs should be triggered by the positive edge of clk.", "header": "module top_module(\n\tinput clk,\n\tinput resetn,\n\tinput [1:0] byteena,\n\tinput [15:0] d,\n\toutput reg [15:0] q);\n", "module_code": "module top_module(\n\tinput clk,\n\tinput resetn,\n\tinput [1:0] byteena,\n\tinput [15:0] d,\n\toutput reg [15:0] q);\n\t\n\talways @(posedge clk) begin\n\t\tif (!resetn)\n\t\t\tq <= 0;\n\t\telse begin\n\t\t\tif (byteena[0])\n\t\t\t\tq[7:0] <= d[7:0];\n\t\t\tif (byteena[1])\n\t\t\t\tq[15:8] <= d[15:8];\n\t\tend\n\tend\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput clk,\n\tinput resetn,\n\tinput [1:0] byteena,\n\tinput [15:0] d,\n\toutput reg [15:0] q);\n\t\n\talways @(posedge clk) begin\n\t\tif (!resetn)\n\t\t\tq <= 0;\n\t\telse begin\n\t\t\tif (byteena[0])\n\t\t\t\tq[7:0] <= d[7:0];\n\t\t\tif (byteena[1])\n\t\t\t\tq[15:8] <= d[15:8];\n\t\tend\n\tend\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg [15:0] d, output reg [1:0] byteena,\n\toutput reg resetn,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\tinput tb_match\n);\n\treg reset;\n\tassign resetn = ~reset;\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\t\n\tinitial begin\n\t\treset <= 1;\n\t\tbyteena <= 2'b11;\n\t\td <= 16'habcd;\n\t\t@(posedge clk);\n\t\twavedrom_start(\"Synchronous active-low reset\");\n\t\treset_test(0);\n\t\trepeat(2) @(posedge clk);\n\t\twavedrom_stop();\n\t\t@(posedge clk);\n\t\t\n\t\t\n\t\tbyteena <= 2'b11;\n\t\td <= $random;\n\t\t@(posedge clk);\n\t\t@(negedge clk);\n\t\twavedrom_start(\"DFF with byte enables\");\n\t\trepeat(10) @(posedge clk) begin\n\t\t\td <= $random;\n\t\t\tbyteena <= byteena + 1;\n\t\tend\n\t\twavedrom_stop();\n\t\t\n\t\trepeat(400) @(posedge clk, negedge clk) begin\n\t\t\tbyteena[0] <= ($random & 3) != 0;\n\t\t\tbyteena[1] <= ($random & 3) != 0;\n\t\t\td <= $random;\n\t\tend\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_q;\n\t\tint errortime_q;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic resetn;\n\tlogic [1:0] byteena;\n\tlogic [15:0] d;\n\tlogic [15:0] q_ref;\n\tlogic [15:0] q_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,resetn,byteena,d,q_ref,q_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.resetn,\n\t\t.byteena,\n\t\t.d );\n\treference_module good1 (\n\t\t.clk,\n\t\t.resetn,\n\t\t.byteena,\n\t\t.d,\n\t\t.q(q_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.resetn,\n\t\t.byteena,\n\t\t.d,\n\t\t.q(q_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"q\", stats1.errors_q, stats1.errortime_q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"q\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (q_ref !== ( q_ref ^ q_dut ^ q_ref ))\n\t\tbegin if (stats1.errors_q == 0) stats1.errortime_q = $time;\n\t\t\tstats1.errors_q = stats1.errors_q+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "edgedetect", "task_number": 105, "description": "For each bit in an 8-bit vector, detect when the input signal changes from 0 in one clock cycle to 1 the next (similar to positive edge detection). The output bit should be set the cycle after a 0 to 1 transition occurs.", "header": "module top_module(\n\tinput clk,\n\tinput [7:0] in,\n\toutput reg [7:0] pedge);\n", "module_code": "module top_module(\n\tinput clk,\n\tinput [7:0] in,\n\toutput reg [7:0] pedge);\n\t\n\treg [7:0] d_last;\t\n\t\t\t\n\talways @(posedge clk) begin\n\t\td_last <= in;\n\t\tpedge <= in & ~d_last;\n\tend\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput clk,\n\tinput [7:0] in,\n\toutput reg [7:0] pedge);\n\t\n\treg [7:0] d_last;\t\n\t\t\t\n\talways @(posedge clk) begin\n\t\td_last <= in;\n\t\tpedge <= in & ~d_last;\n\tend\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\tinput tb_match,\n\toutput reg [7:0] in,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\tinitial begin\n\t\tin <= 0;\n\t\t@(posedge clk);\n\t\twavedrom_start(\"\");\n\t\trepeat(2) @(posedge clk);\n\t\tin <= 1;\n\t\trepeat(4) @(posedge clk);\n\t\tin <= 0;\n\t\trepeat(4) @(negedge clk);\n\t\tin <= 6;\n\t\trepeat(2) @(negedge clk);\n\t\tin <= 0;\t\t\n\t\trepeat(2) @(posedge clk);\n\t\twavedrom_stop();\n\n\t\trepeat(200)\n\t\t\t@(posedge clk, negedge clk) in <= $random;\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_pedge;\n\t\tint errortime_pedge;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [7:0] in;\n\tlogic [7:0] pedge_ref;\n\tlogic [7:0] pedge_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,in,pedge_ref,pedge_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in );\n\treference_module good1 (\n\t\t.clk,\n\t\t.in,\n\t\t.pedge(pedge_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.in,\n\t\t.pedge(pedge_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_pedge) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"pedge\", stats1.errors_pedge, stats1.errortime_pedge);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"pedge\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { pedge_ref } === ( { pedge_ref } ^ { pedge_dut } ^ { pedge_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (pedge_ref !== ( pedge_ref ^ pedge_dut ^ pedge_ref ))\n\t\tbegin if (stats1.errors_pedge == 0) stats1.errortime_pedge = $time;\n\t\t\tstats1.errors_pedge = stats1.errors_pedge+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "circuit8", "task_number": 106, "description": "This is a sequential circuit. Read the simulation waveforms to determine what the circuit does, then implement it.\n\n// time            clock           a               p               q               \n// 0ns             0               0               x               x               \n// 5ns             0               0               x               x               \n// 10ns            0               0               x               x               \n// 15ns            0               0               x               x               \n// 20ns            0               0               x               x               \n// 25ns            1               0               0               x               \n// 30ns            1               0               0               x               \n// 35ns            1               0               0               x               \n// 40ns            1               0               0               x               \n// 45ns            1               0               0               x               \n// 50ns            1               0               0               x               \n// 55ns            0               0               0               0               \n// 60ns            0               0               0               0               \n// 65ns            0               0               0               0               \n// 70ns            0               1               0               0               \n// 75ns            0               0               0               0               \n// 80ns            0               1               0               0               \n// 85ns            1               0               0               0               \n// 90ns            1               1               1               0               \n// 95ns            1               0               0               0               \n// 100ns           1               1               1               0               \n// 105ns           1               0               0               0               \n// 110ns           1               1               1               0               \n// 115ns           0               0               1               1               \n// 120ns           0               1               1               1               \n// 125ns           0               0               1               1               \n// 130ns           0               1               1               1               \n// 135ns           0               0               1               1               \n// 140ns           0               0               1               1               \n// 145ns           1               0               0               1               \n// 150ns           1               0               0               1               \n// 155ns           1               0               0               1               \n// 160ns           1               0               0               1               \n// 165ns           1               1               1               1               \n// 170ns           1               0               0               1               \n// 175ns           0               1               0               0               \n// 180ns           0               0               0               0               \n// 185ns           0               1               0               0               \n// 190ns           0               0               0               0       ", "header": "module top_module (\n\tinput clock,\n\tinput a, \n\toutput reg p,\n\toutput reg q\n);\n", "module_code": "module top_module (\n\tinput clock,\n\tinput a, \n\toutput reg p,\n\toutput reg q\n);\n\n\talways @(negedge clock)\n\t\tq <= a;\n\t\t\n\talways @(*)\n\t\tif (clock)\n\t\t\tp = a;\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clock,\n\tinput a, \n\toutput reg p,\n\toutput reg q\n);\n\n\talways @(negedge clock)\n\t\tq <= a;\n\t\t\n\talways @(*)\n\t\tif (clock)\n\t\t\tp = a;\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic clock=0,\n\toutput logic a,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n\talways begin\n\t\trepeat(3) @(posedge clk);\n\t\tclock = ~clock;\n\tend\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\ta <= 0;\n\t\t@(negedge clock) {a} <= 0;\n\t\t@(negedge clk) wavedrom_start(\"Unknown circuit\");\n\t\t\t@(posedge clk) {a} <= 0;\n\t\t\trepeat(14) @(posedge clk,negedge clk) a <= ~a;\n\t\t\trepeat(5) @(posedge clk, negedge clk);\n\t\t\trepeat(8) @(posedge clk,negedge clk) a <= ~a;\n\t\twavedrom_stop();\n\n\t\trepeat(200) @(posedge clk, negedge clk)\n\t\t\ta <= $urandom;\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_p;\n\t\tint errortime_p;\n\t\tint errors_q;\n\t\tint errortime_q;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic clock;\n\tlogic a;\n\tlogic p_ref;\n\tlogic p_dut;\n\tlogic q_ref;\n\tlogic q_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clock,a,p_ref,p_dut,q_ref,q_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.clock,\n\t\t.a );\n\treference_module good1 (\n\t\t.clock,\n\t\t.a,\n\t\t.p(p_ref),\n\t\t.q(q_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clock,\n\t\t.a,\n\t\t.p(p_dut),\n\t\t.q(q_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_p) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"p\", stats1.errors_p, stats1.errortime_p);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"p\");\n\t\tif (stats1.errors_q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"q\", stats1.errors_q, stats1.errortime_q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"q\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { p_ref, q_ref } === ( { p_ref, q_ref } ^ { p_dut, q_dut } ^ { p_ref, q_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (p_ref !== ( p_ref ^ p_dut ^ p_ref ))\n\t\tbegin if (stats1.errors_p == 0) stats1.errortime_p = $time;\n\t\t\tstats1.errors_p = stats1.errors_p+1'b1; end\n\t\tif (q_ref !== ( q_ref ^ q_dut ^ q_ref ))\n\t\tbegin if (stats1.errors_q == 0) stats1.errortime_q = $time;\n\t\t\tstats1.errors_q = stats1.errors_q+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "rule90", "task_number": 107, "description": "Rule 90 is a one-dimensional cellular automaton with interesting properties. The rules are simple. There is a one-dimensional array of cells (on or off). At each time step, the next state of each cell is the XOR of the cell's two current neighbours:\n// Left | Center | Right | Center's next state\n// 1 | 1 | 1 | 0\n// 1 | 1 | 0 | 1\n// 1 | 0 | 1 | 0\n// 1 | 0 | 0 | 1\n// 0 | 1 | 1 | 1\n// 0 | 1 | 0 | 0 \n// 0 | 0 | 1 | 1\n// 0 | 0 | 0 | 0\n// In this circuit, create a 512-cell system (q[511:0]), and advance by one time step each clock cycle. The load input indicates the state of the system should be loaded with data[511:0]. Assume the boundaries (q[-1] and q[512]) are both zero (off).", "header": "module top_module(\n\tinput clk,\n\tinput load,\n\tinput [511:0] data,\n\toutput reg [511:0] q);\n", "module_code": "module top_module(\n\tinput clk,\n\tinput load,\n\tinput [511:0] data,\n\toutput reg [511:0] q);\n\t\n\talways @(posedge clk) begin\n\t\tif (load)\n\t\t\tq <= data;\n\t\telse begin\n\t\t\tq <= q[$bits(q)-1:1] ^ {q[$bits(q)-2:0], 1'b0} ;\n\t\tend\n\tend\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput clk,\n\tinput load,\n\tinput [511:0] data,\n\toutput reg [511:0] q);\n\t\n\talways @(posedge clk) begin\n\t\tif (load)\n\t\t\tq <= data;\n\t\telse begin\n\t\t\tq <= q[$bits(q)-1:1] ^ {q[$bits(q)-2:0], 1'b0} ;\n\t\tend\n\tend\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg load,\n\toutput reg[511:0] data,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\tdata <= 0;\n\t\tdata[0] <= 1'b1;\n\t\tload <= 1;\n\t\t@(posedge clk); wavedrom_start(\"Sierpi&#324;ski triangle: See Hint.\");\n\t\t@(posedge clk);\n\t\t@(posedge clk);\n\t\tload <= 0;\n\t\trepeat(10) @(posedge clk);\t\t\n\t\twavedrom_stop();\n\n\n\t\tdata <= 0;\n\t\tdata[256] <= 1'b1;\n\t\tload <= 1;\n\t\t@(posedge clk);\n\t\t@(posedge clk);\n\t\t@(posedge clk);\n\t\tload <= 0;\n\t\trepeat(1000) @(posedge clk) begin\n\t\tend\n\t\tdata <= 512'h1000000000000001;\n\t\tload <= 1;\n\t\t@(posedge clk);\n\t\tload <= 0;\n\t\trepeat(1000) @(posedge clk) begin\n\t\tend\n\n\t\tdata <= $random;\n\t\tload <= 1;\n\t\t@(posedge clk);\n\t\tload <= 0;\n\t\trepeat(1000) @(posedge clk) begin\n\t\tend\n\n\t\tdata <= 0;\n\t\tload <= 1;\n\t\trepeat(20) @(posedge clk);\n\t\trepeat(2) @(posedge clk) data <= data + 2;\n\t\t@(posedge clk) begin \n\t\t\tload <= 0;\n\t\t\tdata <= data + 1;\n\t\tend\n\t\trepeat(20) @(posedge clk) data <= data + 1;\n\t\trepeat(500) @(posedge clk) begin\n\t\tend\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_q;\n\t\tint errortime_q;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic load;\n\tlogic [511:0] data;\n\tlogic [511:0] q_ref;\n\tlogic [511:0] q_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,load,data,q_ref,q_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.load,\n\t\t.data );\n\treference_module good1 (\n\t\t.clk,\n\t\t.load,\n\t\t.data,\n\t\t.q(q_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.load,\n\t\t.data,\n\t\t.q(q_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"q\", stats1.errors_q, stats1.errortime_q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"q\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (q_ref !== ( q_ref ^ q_dut ^ q_ref ))\n\t\tbegin if (stats1.errors_q == 0) stats1.errortime_q = $time;\n\t\t\tstats1.errors_q = stats1.errors_q+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "mt2015_eq2", "task_number": 108, "description": "Create a circuit that has two 2-bit inputs A[1:0] and B[1:0], and produces an output z. The value of z should be 1 if A = B, otherwise z should be 0.", "header": "module top_module(\n\tinput [1:0] A,\n\tinput [1:0] B,\n\toutput z);\n", "module_code": "module top_module(\n\tinput [1:0] A,\n\tinput [1:0] B,\n\toutput z);\n\n\tassign z = A[1:0]==B[1:0];\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\n/*\n\tMidterm 2015 Question 1k. 2-bit equality comparator.\n*/\nmodule reference_module(\n\tinput [1:0] A,\n\tinput [1:0] B,\n\toutput z);\n\n\tassign z = A[1:0]==B[1:0];\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic [1:0] A,\n\toutput logic [1:0] B\n);\n\n\talways @(posedge clk, negedge clk)\n\t\t{A, B} <= $random % 16;\n\t\n\tinitial begin\n\t\trepeat(1000) @(negedge clk);\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_z;\n\t\tint errortime_z;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [1:0] A;\n\tlogic [1:0] B;\n\tlogic z_ref;\n\tlogic z_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,A,B,z_ref,z_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.A,\n\t\t.B );\n\treference_module good1 (\n\t\t.A,\n\t\t.B,\n\t\t.z(z_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.A,\n\t\t.B,\n\t\t.z(z_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_z) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"z\", stats1.errors_z, stats1.errortime_z);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"z\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { z_ref } === ( { z_ref } ^ { z_dut } ^ { z_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (z_ref !== ( z_ref ^ z_dut ^ z_ref ))\n\t\tbegin if (stats1.errors_z == 0) stats1.errortime_z = $time;\n\t\t\tstats1.errors_z = stats1.errors_z+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "gatesv100", "task_number": 109, "description": "You are given a 100-bit input vector in[99:0]. We want to know some relationships between each bit and its neighbour: \n// (1) out_both: Each bit of this output vector should indicate whether both the corresponding input bit and its neighbour to the left are '1'. For example, out_both[98] should indicate if in[98] and in[99] are both 1. Since in[99] has no neighbour to the left, the answer is obvious so we don't need to know out_both[99]. \n// (2) out_any: Each bit of this output vector should indicate whether any of the corresponding input bit and its neighbour to the right are '1'. For example, out_any[2] should indicate if either in[2] or in[1] are 1. Since in[0] has no neighbour to the right, the answer is obvious so we don't need to know out_any[0]. \n// (3) out_different: Each bit of this output vector should indicate whether the corresponding input bit is different from its neighbour to the left. For example, out_different[98] should indicate if in[98] is different from in[99]. For this part, treat the vector as wrapping around, so in[99]'s neighbour to the left is in[0].\n", "header": "module top_module (\n\tinput [99:0] in,\n\toutput [98:0] out_both,\n\toutput [99:1] out_any,\n\toutput [99:0] out_different\n);\n", "module_code": "module top_module (\n\tinput [99:0] in,\n\toutput [98:0] out_both,\n\toutput [99:1] out_any,\n\toutput [99:0] out_different\n);\n\n\tassign out_both = in & in[99:1];\n\tassign out_any = in | in[99:1];\n\tassign out_different = in^{in[0], in[99:1]};\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [99:0] in,\n\toutput [98:0] out_both,\n\toutput [99:1] out_any,\n\toutput [99:0] out_different\n);\n\n\tassign out_both = in & in[99:1];\n\tassign out_any = in | in[99:1];\n\tassign out_different = in^{in[0], in[99:1]};\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\tinput tb_match,\n\toutput logic [99:0] in\n);\n\n\tinitial begin\n\t\tin <= $random;\n\t\trepeat(100) begin\n\t\t\t@(negedge clk) in <= $random;\n\t\t\t@(posedge clk) in <= $random;\n\t\tend\n\t\t#1 $finish;\n\tend\n\t\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out_both;\n\t\tint errortime_out_both;\n\t\tint errors_out_any;\n\t\tint errortime_out_any;\n\t\tint errors_out_different;\n\t\tint errortime_out_different;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [99:0] in;\n\tlogic [98:0] out_both_ref;\n\tlogic [98:0] out_both_dut;\n\tlogic [99:1] out_any_ref;\n\tlogic [99:1] out_any_dut;\n\tlogic [99:0] out_different_ref;\n\tlogic [99:0] out_different_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,in,out_both_ref,out_both_dut,out_any_ref,out_any_dut,out_different_ref,out_different_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in );\n\treference_module good1 (\n\t\t.in,\n\t\t.out_both(out_both_ref),\n\t\t.out_any(out_any_ref),\n\t\t.out_different(out_different_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.in,\n\t\t.out_both(out_both_dut),\n\t\t.out_any(out_any_dut),\n\t\t.out_different(out_different_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out_both) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_both\", stats1.errors_out_both, stats1.errortime_out_both);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_both\");\n\t\tif (stats1.errors_out_any) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_any\", stats1.errors_out_any, stats1.errortime_out_any);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_any\");\n\t\tif (stats1.errors_out_different) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_different\", stats1.errors_out_different, stats1.errortime_out_different);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_different\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_both_ref, out_any_ref, out_different_ref } === ( { out_both_ref, out_any_ref, out_different_ref } ^ { out_both_dut, out_any_dut, out_different_dut } ^ { out_both_ref, out_any_ref, out_different_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_both_ref !== ( out_both_ref ^ out_both_dut ^ out_both_ref ))\n\t\tbegin if (stats1.errors_out_both == 0) stats1.errortime_out_both = $time;\n\t\t\tstats1.errors_out_both = stats1.errors_out_both+1'b1; end\n\t\tif (out_any_ref !== ( out_any_ref ^ out_any_dut ^ out_any_ref ))\n\t\tbegin if (stats1.errors_out_any == 0) stats1.errortime_out_any = $time;\n\t\t\tstats1.errors_out_any = stats1.errors_out_any+1'b1; end\n\t\tif (out_different_ref !== ( out_different_ref ^ out_different_dut ^ out_different_ref ))\n\t\tbegin if (stats1.errors_out_different == 0) stats1.errortime_out_different = $time;\n\t\t\tstats1.errors_out_different = stats1.errors_out_different+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "m2014_q4a", "task_number": 110, "description": "Implement a D latch using an always block.\n", "header": "module top_module (\n\tinput d,\n\tinput ena,\n\toutput logic q\n);\n", "module_code": "module top_module (\n\tinput d,\n\tinput ena,\n\toutput logic q\n);\n\n\talways@(*) begin\n\t\tif (ena)\n\t\t\tq = d;\n\tend\n\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput d,\n\tinput ena,\n\toutput logic q\n);\n\n\talways@(*) begin\n\t\tif (ena)\n\t\t\tq = d;\n\tend\n\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic d, ena\n);\n\n\tinitial begin\n\t\trepeat(100) @(posedge clk, negedge clk) begin\n\t\t\t{d,ena} <= $random;\n\t\tend\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_q;\n\t\tint errortime_q;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic d;\n\tlogic ena;\n\tlogic q_ref;\n\tlogic q_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,d,ena,q_ref,q_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.d,\n\t\t.ena );\n\treference_module good1 (\n\t\t.d,\n\t\t.ena,\n\t\t.q(q_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.d,\n\t\t.ena,\n\t\t.q(q_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"q\", stats1.errors_q, stats1.errortime_q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"q\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (q_ref !== ( q_ref ^ q_dut ^ q_ref ))\n\t\tbegin if (stats1.errors_q == 0) stats1.errortime_q = $time;\n\t\t\tstats1.errors_q = stats1.errors_q+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "mux256to1v", "task_number": 111, "description": "Create a 4-bit wide, 256-to-1 multiplexer. The 256 4-bit inputs are all packed into a single 1024-bit input vector. sel=0 should select bits in[3:0], sel=1 selects bits in[7:4], sel=2 selects bits in[11:8], etc.", "header": "module top_module (\n\tinput [1023:0] in,\n\tinput [7:0] sel,\n\toutput [3:0] out\n);\n", "module_code": "module top_module (\n\tinput [1023:0] in,\n\tinput [7:0] sel,\n\toutput [3:0] out\n);\n\n\tassign out = {in[sel*4+3], in[sel*4+2], in[sel*4+1], in[sel*4+0]};\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [1023:0] in,\n\tinput [7:0] sel,\n\toutput [3:0] out\n);\n\n\tassign out = {in[sel*4+3], in[sel*4+2], in[sel*4+1], in[sel*4+0]};\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic [1023:0] in,\n\toutput logic [7:0] sel\n);\n\n\talways @(posedge clk, negedge clk) begin\n\t\tfor (int i=0;i<32; i++)\n\t\t\tin[i*32+:32] <= $random;\n\t\tsel <= $random;\n\tend\n\t\n\tinitial begin\n\t\trepeat(1000) @(negedge clk);\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [1023:0] in;\n\tlogic [7:0] sel;\n\tlogic [3:0] out_ref;\n\tlogic [3:0] out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,in,sel,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in,\n\t\t.sel );\n\treference_module good1 (\n\t\t.in,\n\t\t.sel,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.in,\n\t\t.sel,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "mux9to1v", "task_number": 112, "description": "Create a 16-bit wide, 9-to-1 multiplexer. sel=0 chooses a, sel=1 chooses b, etc. For the unused cases (sel=9 to 15), set all output bits to '1'.", "header": "module top_module (\n\tinput [15:0] a,\n\tinput [15:0] b,\n\tinput [15:0] c,\n\tinput [15:0] d,\n\tinput [15:0] e,\n\tinput [15:0] f,\n\tinput [15:0] g,\n\tinput [15:0] h,\n\tinput [15:0] i,\n\tinput [3:0] sel,\n\toutput logic [15:0] out\n);\n", "module_code": "module top_module (\n\tinput [15:0] a,\n\tinput [15:0] b,\n\tinput [15:0] c,\n\tinput [15:0] d,\n\tinput [15:0] e,\n\tinput [15:0] f,\n\tinput [15:0] g,\n\tinput [15:0] h,\n\tinput [15:0] i,\n\tinput [3:0] sel,\n\toutput logic [15:0] out\n);\n\n\talways @(*) begin\n\t\tout = '1;\n\t\tcase (sel)\n\t\t\t4'h0: out = a;\n\t\t\t4'h1: out = b;\n\t\t\t4'h2: out = c;\n\t\t\t4'h3: out = d;\n\t\t\t4'h4: out = e;\n\t\t\t4'h5: out = f;\n\t\t\t4'h6: out = g;\n\t\t\t4'h7: out = h;\n\t\t\t4'h8: out = i;\n\t\tendcase\n\tend\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [15:0] a,\n\tinput [15:0] b,\n\tinput [15:0] c,\n\tinput [15:0] d,\n\tinput [15:0] e,\n\tinput [15:0] f,\n\tinput [15:0] g,\n\tinput [15:0] h,\n\tinput [15:0] i,\n\tinput [3:0] sel,\n\toutput logic [15:0] out\n);\n\n\talways @(*) begin\n\t\tout = '1;\n\t\tcase (sel)\n\t\t\t4'h0: out = a;\n\t\t\t4'h1: out = b;\n\t\t\t4'h2: out = c;\n\t\t\t4'h3: out = d;\n\t\t\t4'h4: out = e;\n\t\t\t4'h5: out = f;\n\t\t\t4'h6: out = g;\n\t\t\t4'h7: out = h;\n\t\t\t4'h8: out = i;\n\t\tendcase\n\tend\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic [15:0] a,b,c,d,e,f,g,h,i,\n\toutput logic [3:0] sel,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\t\n\t\n\tinitial begin\n\t\t{a,b,c,d,e,f,g,h,i,sel} <= { 16'ha, 16'hb, 16'hc, 16'hd, 16'he, 16'hf, 16'h11, 16'h12, 16'h13, 4'h0 };\n\t\t@(negedge clk) wavedrom_start();\n\t\t\t@(posedge clk) sel <= 4'h1;\n\t\t\t@(posedge clk) sel <= 4'h2;\n\t\t\t@(posedge clk) sel <= 4'h3;\n\t\t\t@(posedge clk) sel <= 4'h4;\n\t\t\t@(posedge clk) sel <= 4'h7;\n\t\t\t@(posedge clk) sel <= 4'h8;\n\t\t\t@(posedge clk) sel <= 4'h9;\n\t\t\t@(posedge clk) sel <= 4'ha;\n\t\t\t@(posedge clk) sel <= 4'hb;\n\t\t@(negedge clk) wavedrom_stop();\n\t\t\t\n\t\trepeat(200) @(negedge clk, posedge clk) begin\n\t\t\t{a,b,c,d,e,f,g,h,i,sel} <= {$random, $random, $random, $random, $random};\n\t\tend\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [15:0] a;\n\tlogic [15:0] b;\n\tlogic [15:0] c;\n\tlogic [15:0] d;\n\tlogic [15:0] e;\n\tlogic [15:0] f;\n\tlogic [15:0] g;\n\tlogic [15:0] h;\n\tlogic [15:0] i;\n\tlogic [3:0] sel;\n\tlogic [15:0] out_ref;\n\tlogic [15:0] out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,a,b,c,d,e,f,g,h,i,sel,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d,\n\t\t.e,\n\t\t.f,\n\t\t.g,\n\t\t.h,\n\t\t.i,\n\t\t.sel );\n\treference_module good1 (\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d,\n\t\t.e,\n\t\t.f,\n\t\t.g,\n\t\t.h,\n\t\t.i,\n\t\t.sel,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d,\n\t\t.e,\n\t\t.f,\n\t\t.g,\n\t\t.h,\n\t\t.i,\n\t\t.sel,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "vectorgates", "task_number": 113, "description": "Build a circuit that has two 3-bit inputs that computes the bitwise-OR of the two vectors, the logical-OR of the two vectors, and the inverse (NOT) of both vectors. Place the inverse of b in the upper half of out_not (i.e., bits [5:3]), and the inverse of a in the lower half.", "header": "module top_module(\n\tinput [2:0] a, \n\tinput [2:0] b, \n\toutput [2:0] out_or_bitwise,\n\toutput out_or_logical,\n\toutput [5:0] out_not\n);\n", "module_code": "module top_module(\n\tinput [2:0] a, \n\tinput [2:0] b, \n\toutput [2:0] out_or_bitwise,\n\toutput out_or_logical,\n\toutput [5:0] out_not\n);\n\t\n\tassign out_or_bitwise = a | b;\n\tassign out_or_logical = a || b;\n\tassign out_not = {~b,~a};\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput [2:0] a, \n\tinput [2:0] b, \n\toutput [2:0] out_or_bitwise,\n\toutput out_or_logical,\n\toutput [5:0] out_not\n);\n\t\n\tassign out_or_bitwise = a | b;\n\tassign out_or_logical = a || b;\n\tassign out_not = {~b,~a};\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg [2:0] a, b,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\tint count; count = 6'h38;\n\t\t{b, a} <= 6'b0;\n\t\t@(negedge clk);\n\t\twavedrom_start();\n\t\trepeat(30) @(posedge clk)\n\t\t\t{b, a} <= count++;\t\t\n\t\twavedrom_stop();\n\t\t\n\t\trepeat(200) @(posedge clk, negedge clk)\n\t\t\t{b,a} <= $random;\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out_or_bitwise;\n\t\tint errortime_out_or_bitwise;\n\t\tint errors_out_or_logical;\n\t\tint errortime_out_or_logical;\n\t\tint errors_out_not;\n\t\tint errortime_out_not;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [2:0] a;\n\tlogic [2:0] b;\n\tlogic [2:0] out_or_bitwise_ref;\n\tlogic [2:0] out_or_bitwise_dut;\n\tlogic out_or_logical_ref;\n\tlogic out_or_logical_dut;\n\tlogic [5:0] out_not_ref;\n\tlogic [5:0] out_not_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,a,b,out_or_bitwise_ref,out_or_bitwise_dut,out_or_logical_ref,out_or_logical_dut,out_not_ref,out_not_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.a,\n\t\t.b );\n\treference_module good1 (\n\t\t.a,\n\t\t.b,\n\t\t.out_or_bitwise(out_or_bitwise_ref),\n\t\t.out_or_logical(out_or_logical_ref),\n\t\t.out_not(out_not_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.a,\n\t\t.b,\n\t\t.out_or_bitwise(out_or_bitwise_dut),\n\t\t.out_or_logical(out_or_logical_dut),\n\t\t.out_not(out_not_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out_or_bitwise) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_or_bitwise\", stats1.errors_out_or_bitwise, stats1.errortime_out_or_bitwise);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_or_bitwise\");\n\t\tif (stats1.errors_out_or_logical) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_or_logical\", stats1.errors_out_or_logical, stats1.errortime_out_or_logical);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_or_logical\");\n\t\tif (stats1.errors_out_not) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_not\", stats1.errors_out_not, stats1.errortime_out_not);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_not\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_or_bitwise_ref, out_or_logical_ref, out_not_ref } === ( { out_or_bitwise_ref, out_or_logical_ref, out_not_ref } ^ { out_or_bitwise_dut, out_or_logical_dut, out_not_dut } ^ { out_or_bitwise_ref, out_or_logical_ref, out_not_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_or_bitwise_ref !== ( out_or_bitwise_ref ^ out_or_bitwise_dut ^ out_or_bitwise_ref ))\n\t\tbegin if (stats1.errors_out_or_bitwise == 0) stats1.errortime_out_or_bitwise = $time;\n\t\t\tstats1.errors_out_or_bitwise = stats1.errors_out_or_bitwise+1'b1; end\n\t\tif (out_or_logical_ref !== ( out_or_logical_ref ^ out_or_logical_dut ^ out_or_logical_ref ))\n\t\tbegin if (stats1.errors_out_or_logical == 0) stats1.errortime_out_or_logical = $time;\n\t\t\tstats1.errors_out_or_logical = stats1.errors_out_or_logical+1'b1; end\n\t\tif (out_not_ref !== ( out_not_ref ^ out_not_dut ^ out_not_ref ))\n\t\tbegin if (stats1.errors_out_not == 0) stats1.errortime_out_not = $time;\n\t\t\tstats1.errors_out_not = stats1.errors_out_not+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "fsm3onehot", "task_number": 114, "description": "The following is the state transition table for a Moore state machine with one input, one output, and four states. Use the following one-hot state encoding: A=4'b0001, B=4'b0010, C=4'b0100, D=4'b1000. Derive state transition and output logic equations by inspection assuming a one-hot encoding. Implement only the state transition logic and output logic (the combinational logic portion) for this state machine. \n// State | Next state in=0, Next state in=1 | Output\n// A | A, B | 0\n// B | C, B | 0\n// C | A, D | 0\n// D | C, B | 1", "header": "module top_module (\n\tinput in,\n\tinput [3:0] state,\n\toutput reg [3:0] next_state,\n\toutput out\n);\n", "module_code": "module top_module (\n\tinput in,\n\tinput [3:0] state,\n\toutput reg [3:0] next_state,\n\toutput out\n);\n\tparameter A=0, B=1, C=2, D=3;\n    \n    assign next_state[A] = (state[A] | state[C]) & ~in;\n    assign next_state[B] = (state[A] | state[B] | state[D]) & in;\n    assign next_state[C] = (state[B] | state[D]) & ~in;\n    assign next_state[D] = state[C] & in;\n    \n\tassign out = (state[D]);\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput in,\n\tinput [3:0] state,\n\toutput reg [3:0] next_state,\n\toutput out\n);\n\tparameter A=0, B=1, C=2, D=3;\n    \n    assign next_state[A] = (state[A] | state[C]) & ~in;\n    assign next_state[B] = (state[A] | state[B] | state[D]) & in;\n    assign next_state[C] = (state[B] | state[D]) & ~in;\n    assign next_state[D] = state[C] & in;\n    \n\tassign out = (state[D]);\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic in,\n\toutput logic [3:0] state,\n\tinput tb_match\n);\n\n\tint errored1 = 0;\n\tint onehot_error = 0;\n\t\n\tinitial begin\n\t\t// Test the one-hot cases first.\n\t\trepeat(200) @(posedge clk, negedge clk) begin\n\t\t\tstate <= 1<< ($unsigned($random) % 4);\n\t\t\tin <= $random;\n\t\t\tif (!tb_match) onehot_error++;\n\t\tend\n\t\t\t\n\t\t\t\n\t\t// Random.\n\t\terrored1 = 0;\n\t\trepeat(400) @(posedge clk, negedge clk) begin\n\t\t\tstate <= $random;\n\t\t\tin <= $random;\n\t\t\tif (!tb_match)\n\t\t\t\terrored1++;\n\t\tend\n\t\tif (!onehot_error && errored1) \n\t\t\t$display (\"Hint: Your circuit passed when given only one-hot inputs, but not with random inputs.\");\n\n\t\tif (!onehot_error && errored1)\n\t\t\t$display(\"Hint: Are you doing something more complicated than deriving state transition equations by inspection?\\n\");\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_next_state;\n\t\tint errortime_next_state;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic in;\n\tlogic [3:0] state;\n\tlogic [3:0] next_state_ref;\n\tlogic [3:0] next_state_dut;\n\tlogic out_ref;\n\tlogic out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,in,state,next_state_ref,next_state_dut,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in,\n\t\t.state );\n\treference_module good1 (\n\t\t.in,\n\t\t.state,\n\t\t.next_state(next_state_ref),\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.in,\n\t\t.state,\n\t\t.next_state(next_state_dut),\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_next_state) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"next_state\", stats1.errors_next_state, stats1.errortime_next_state);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"next_state\");\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { next_state_ref, out_ref } === ( { next_state_ref, out_ref } ^ { next_state_dut, out_dut } ^ { next_state_ref, out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (next_state_ref !== ( next_state_ref ^ next_state_dut ^ next_state_ref ))\n\t\tbegin if (stats1.errors_next_state == 0) stats1.errortime_next_state = $time;\n\t\t\tstats1.errors_next_state = stats1.errors_next_state+1'b1; end\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "conditional", "task_number": 115, "description": "Given four unsigned numbers, find the minimum. Unsigned numbers can be compared with standard comparison operators (a < b). ", "header": "module top_module (\n\tinput [7:0] a,\n\tinput [7:0] b,\n\tinput [7:0] c,\n\tinput [7:0] d,\n\toutput reg [7:0] min\n);\n", "module_code": "module top_module (\n\tinput [7:0] a,\n\tinput [7:0] b,\n\tinput [7:0] c,\n\tinput [7:0] d,\n\toutput reg [7:0] min\n);\n\n\talways_comb begin\n\t\tmin = a;\n\t\tif (min > b) min = b;\n\t\tif (min > c) min = c;\n\t\tif (min > d) min = d;\n\tend\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [7:0] a,\n\tinput [7:0] b,\n\tinput [7:0] c,\n\tinput [7:0] d,\n\toutput reg [7:0] min\n);\n\n\talways_comb begin\n\t\tmin = a;\n\t\tif (min > b) min = b;\n\t\tif (min > c) min = c;\n\t\tif (min > d) min = d;\n\tend\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic [7:0] a, b, c, d,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\n);\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n \tinitial begin\n \t\t{a,b,c,d} <= {8'h1, 8'h2, 8'h3, 8'h4};\n \t\t@(negedge clk);\n \t\twavedrom_start();\n\t \t\t@(posedge clk) {a,b,c,d} <= {8'h1, 8'h2, 8'h3, 8'h4};\n\t \t\t@(posedge clk) {a,b,c,d} <= {8'h11, 8'h2, 8'h3, 8'h4};\n\t \t\t@(posedge clk) {a,b,c,d} <= {8'h11, 8'h12, 8'h3, 8'h4};\n\t \t\t@(posedge clk) {a,b,c,d} <= {8'h11, 8'h12, 8'h13, 8'h4};\n\t \t\t@(posedge clk) {a,b,c,d} <= {8'h11, 8'h12, 8'h13, 8'h14};\n \t\t@(negedge clk);\n \t\twavedrom_stop();\n\t\trepeat(100) @(posedge clk, negedge clk)\n\t\t\t{a,b,c,d} <= $random;\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_min;\n\t\tint errortime_min;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [7:0] a;\n\tlogic [7:0] b;\n\tlogic [7:0] c;\n\tlogic [7:0] d;\n\tlogic [7:0] min_ref;\n\tlogic [7:0] min_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,a,b,c,d,min_ref,min_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d );\n\treference_module good1 (\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d,\n\t\t.min(min_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d,\n\t\t.min(min_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_min) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"min\", stats1.errors_min, stats1.errortime_min);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"min\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { min_ref } === ( { min_ref } ^ { min_dut } ^ { min_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (min_ref !== ( min_ref ^ min_dut ^ min_ref ))\n\t\tbegin if (stats1.errors_min == 0) stats1.errortime_min = $time;\n\t\t\tstats1.errors_min = stats1.errors_min+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "gates", "task_number": 116, "description": "Build a combinational circuit with two inputs, a and b. There are 7 outputs, each with a logic gate driving it: \n// (1) out_and: a and b \n// (2) out_or: a or b \n// (3) out_xor: a xor b \n// (4) out_nand: a nand b \n// (5) out_nor: a nor b \n// (6) out_xnor: a xnor b \n// (7) out_anotb: a and-not b", "header": "module top_module (\n\tinput a,\n\tinput b,\n\toutput out_and,\n\toutput out_or,\n\toutput out_xor,\n\toutput out_nand,\n\toutput out_nor,\n\toutput out_xnor,\n\toutput out_anotb\n);\n", "module_code": "module top_module (\n\tinput a,\n\tinput b,\n\toutput out_and,\n\toutput out_or,\n\toutput out_xor,\n\toutput out_nand,\n\toutput out_nor,\n\toutput out_xnor,\n\toutput out_anotb\n);\n\n\tassign out_and = a&b;\n\tassign out_or = a|b;\n\tassign out_xor = a^b;\n\tassign out_nand = ~(a&b);\n\tassign out_nor = ~(a|b);\n\tassign out_xnor = a^~b;\n\tassign out_anotb = a & ~b;\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput a,\n\tinput b,\n\toutput out_and,\n\toutput out_or,\n\toutput out_xor,\n\toutput out_nand,\n\toutput out_nor,\n\toutput out_xnor,\n\toutput out_anotb\n);\n\n\tassign out_and = a&b;\n\tassign out_or = a|b;\n\tassign out_xor = a^b;\n\tassign out_nand = ~(a&b);\n\tassign out_nor = ~(a|b);\n\tassign out_xnor = a^~b;\n\tassign out_anotb = a & ~b;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic a,b,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\n);\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\t\n\tinitial begin\n\t\t@(negedge clk) {a,b} <= 0;\n\t\twavedrom_start();\n\t\t\t@(posedge clk) {a,b} <= 0;\n\t\t\t@(posedge clk) {a,b} <= 1;\n\t\t\t@(posedge clk) {a,b} <= 2;\n\t\t\t@(posedge clk) {a,b} <= 3;\n\t\t\t@(negedge clk);\n\t\twavedrom_stop();\n\t\trepeat(200) @(posedge clk, negedge clk)\n\t\t{a,b} <= $random;\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out_and;\n\t\tint errortime_out_and;\n\t\tint errors_out_or;\n\t\tint errortime_out_or;\n\t\tint errors_out_xor;\n\t\tint errortime_out_xor;\n\t\tint errors_out_nand;\n\t\tint errortime_out_nand;\n\t\tint errors_out_nor;\n\t\tint errortime_out_nor;\n\t\tint errors_out_xnor;\n\t\tint errortime_out_xnor;\n\t\tint errors_out_anotb;\n\t\tint errortime_out_anotb;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic a;\n\tlogic b;\n\tlogic out_and_ref;\n\tlogic out_and_dut;\n\tlogic out_or_ref;\n\tlogic out_or_dut;\n\tlogic out_xor_ref;\n\tlogic out_xor_dut;\n\tlogic out_nand_ref;\n\tlogic out_nand_dut;\n\tlogic out_nor_ref;\n\tlogic out_nor_dut;\n\tlogic out_xnor_ref;\n\tlogic out_xnor_dut;\n\tlogic out_anotb_ref;\n\tlogic out_anotb_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,a,b,out_and_ref,out_and_dut,out_or_ref,out_or_dut,out_xor_ref,out_xor_dut,out_nand_ref,out_nand_dut,out_nor_ref,out_nor_dut,out_xnor_ref,out_xnor_dut,out_anotb_ref,out_anotb_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.a,\n\t\t.b );\n\treference_module good1 (\n\t\t.a,\n\t\t.b,\n\t\t.out_and(out_and_ref),\n\t\t.out_or(out_or_ref),\n\t\t.out_xor(out_xor_ref),\n\t\t.out_nand(out_nand_ref),\n\t\t.out_nor(out_nor_ref),\n\t\t.out_xnor(out_xnor_ref),\n\t\t.out_anotb(out_anotb_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.a,\n\t\t.b,\n\t\t.out_and(out_and_dut),\n\t\t.out_or(out_or_dut),\n\t\t.out_xor(out_xor_dut),\n\t\t.out_nand(out_nand_dut),\n\t\t.out_nor(out_nor_dut),\n\t\t.out_xnor(out_xnor_dut),\n\t\t.out_anotb(out_anotb_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out_and) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_and\", stats1.errors_out_and, stats1.errortime_out_and);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_and\");\n\t\tif (stats1.errors_out_or) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_or\", stats1.errors_out_or, stats1.errortime_out_or);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_or\");\n\t\tif (stats1.errors_out_xor) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_xor\", stats1.errors_out_xor, stats1.errortime_out_xor);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_xor\");\n\t\tif (stats1.errors_out_nand) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_nand\", stats1.errors_out_nand, stats1.errortime_out_nand);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_nand\");\n\t\tif (stats1.errors_out_nor) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_nor\", stats1.errors_out_nor, stats1.errortime_out_nor);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_nor\");\n\t\tif (stats1.errors_out_xnor) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_xnor\", stats1.errors_out_xnor, stats1.errortime_out_xnor);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_xnor\");\n\t\tif (stats1.errors_out_anotb) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_anotb\", stats1.errors_out_anotb, stats1.errortime_out_anotb);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_anotb\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_and_ref, out_or_ref, out_xor_ref, out_nand_ref, out_nor_ref, out_xnor_ref, out_anotb_ref } === ( { out_and_ref, out_or_ref, out_xor_ref, out_nand_ref, out_nor_ref, out_xnor_ref, out_anotb_ref } ^ { out_and_dut, out_or_dut, out_xor_dut, out_nand_dut, out_nor_dut, out_xnor_dut, out_anotb_dut } ^ { out_and_ref, out_or_ref, out_xor_ref, out_nand_ref, out_nor_ref, out_xnor_ref, out_anotb_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_and_ref !== ( out_and_ref ^ out_and_dut ^ out_and_ref ))\n\t\tbegin if (stats1.errors_out_and == 0) stats1.errortime_out_and = $time;\n\t\t\tstats1.errors_out_and = stats1.errors_out_and+1'b1; end\n\t\tif (out_or_ref !== ( out_or_ref ^ out_or_dut ^ out_or_ref ))\n\t\tbegin if (stats1.errors_out_or == 0) stats1.errortime_out_or = $time;\n\t\t\tstats1.errors_out_or = stats1.errors_out_or+1'b1; end\n\t\tif (out_xor_ref !== ( out_xor_ref ^ out_xor_dut ^ out_xor_ref ))\n\t\tbegin if (stats1.errors_out_xor == 0) stats1.errortime_out_xor = $time;\n\t\t\tstats1.errors_out_xor = stats1.errors_out_xor+1'b1; end\n\t\tif (out_nand_ref !== ( out_nand_ref ^ out_nand_dut ^ out_nand_ref ))\n\t\tbegin if (stats1.errors_out_nand == 0) stats1.errortime_out_nand = $time;\n\t\t\tstats1.errors_out_nand = stats1.errors_out_nand+1'b1; end\n\t\tif (out_nor_ref !== ( out_nor_ref ^ out_nor_dut ^ out_nor_ref ))\n\t\tbegin if (stats1.errors_out_nor == 0) stats1.errortime_out_nor = $time;\n\t\t\tstats1.errors_out_nor = stats1.errors_out_nor+1'b1; end\n\t\tif (out_xnor_ref !== ( out_xnor_ref ^ out_xnor_dut ^ out_xnor_ref ))\n\t\tbegin if (stats1.errors_out_xnor == 0) stats1.errortime_out_xnor = $time;\n\t\t\tstats1.errors_out_xnor = stats1.errors_out_xnor+1'b1; end\n\t\tif (out_anotb_ref !== ( out_anotb_ref ^ out_anotb_dut ^ out_anotb_ref ))\n\t\tbegin if (stats1.errors_out_anotb == 0) stats1.errortime_out_anotb = $time;\n\t\t\tstats1.errors_out_anotb = stats1.errors_out_anotb+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "kmap2", "task_number": 117, "description": "Implement the circuit described by the Karnaugh map below.\n\n//        ab\n// cd   00 01 11 10\n//  00 | 1 | 1 | 0 | 1 |\n//  01 | 1 | 0 | 0 | 1 |\n//  11 | 0 | 1 | 1 | 1 |\n//  10 | 1 | 1 | 0 | 0 |", "header": "module top_module (\n\tinput a, \n\tinput b,\n\tinput c,\n\tinput d,\n\toutput out\n);\n", "module_code": "module top_module (\n\tinput a, \n\tinput b,\n\tinput c,\n\tinput d,\n\toutput out\n);\n\t\n\tassign out = (~c & ~b) | (~d&~a) | (a&c&d) | (b&c&d);\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput a, \n\tinput b,\n\tinput c,\n\tinput d,\n\toutput out\n);\n\t\n\tassign out = (~c & ~b) | (~d&~a) | (a&c&d) | (b&c&d);\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg a, b, c, d,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\tint count; count = 0;\n\t\t{a,b,c,d} <= 4'b0;\n\t\twavedrom_start();\n\t\trepeat(16) @(posedge clk)\n\t\t\t{a,b,c,d} <= count++;\t\t\n\t\t@(negedge clk) wavedrom_stop();\n\t\t\n\t\trepeat(200) @(posedge clk, negedge clk)\n\t\t\t{d,c,b,a} <= $urandom;\n\t\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic a;\n\tlogic b;\n\tlogic c;\n\tlogic d;\n\tlogic out_ref;\n\tlogic out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,a,b,c,d,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d );\n\treference_module good1 (\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "2014_q3fsm", "task_number": 118, "description": "Consider a finite state machine with inputs s and w. Assume that the FSM begins in a reset state called A, as depicted below. The FSM remains in state A as long as s = 0, and it moves to state B when s = 1. Once in state B the FSM examines the value of the input w in the next three clock cycles. If w = 1 in exactly two of these clock cycles, then the FSM has to set an output z to 1 in the following clock cycle. Otherwise z has to be 0. The FSM continues checking w for the next three clock cycles, and so on. Use as few states as possible. Note that the s input is used only in state A, so you need to consider just the w input. Assume reset is active high synchronous.", "header": "module top_module (\n\tinput clk,\n\tinput reset,\n\tinput s,\n\tinput w,\n\toutput reg z\n);\n", "module_code": "module top_module (\n\tinput clk,\n\tinput reset,\n\tinput s,\n\tinput w,\n\toutput reg z\n);\n\tparameter A=0, B=1, C=2, S10=3, S11=4, S20=5, S21=6, S22=7;\n\treg [2:0] state, next;\n\n\talways @(posedge clk) begin\n\t\tif (reset) state <= A;\n\t\telse state <= next;\n\tend\n\t\n\talways_comb begin\n\t\tcase (state)\n\t\t\tA: next = s ? B : A;\n\t\t\tB: next = w ? S11 : S10;\n\t\t\tC: next = w ? S11 : S10;\n\t\t\tS10: next = w ? S21 : S20;\n\t\t\tS11: next = w ? S22 : S21;\n\t\t\tS20: next = B;\n\t\t\tS21: next = w ? C : B;\n\t\t\tS22: next = w ? B : C;\n\t\t\tdefault: next = 'x;\n\t\tendcase\n\tend\n\t    \n\tassign z = (state == C);\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput reset,\n\tinput s,\n\tinput w,\n\toutput reg z\n);\n\tparameter A=0, B=1, C=2, S10=3, S11=4, S20=5, S21=6, S22=7;\n\treg [2:0] state, next;\n\n\talways @(posedge clk) begin\n\t\tif (reset) state <= A;\n\t\telse state <= next;\n\tend\n\t\n\talways_comb begin\n\t\tcase (state)\n\t\t\tA: next = s ? B : A;\n\t\t\tB: next = w ? S11 : S10;\n\t\t\tC: next = w ? S11 : S10;\n\t\t\tS10: next = w ? S21 : S20;\n\t\t\tS11: next = w ? S22 : S21;\n\t\t\tS20: next = B;\n\t\t\tS21: next = w ? C : B;\n\t\t\tS22: next = w ? B : C;\n\t\t\tdefault: next = 'x;\n\t\tendcase\n\tend\n\t    \n\tassign z = (state == C);\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic reset,\n\toutput logic s, w,\n\tinput tb_match\n);\n\n\tbit spulse_fail = 0;\n\tbit failed = 0;\n\t\n\talways @(posedge clk, negedge clk)\n\t\tif (!tb_match) failed = 1;\n\t\t\n\t\t\n\tinitial begin\n\t\treset <= 1;\n\t\ts <= 0;\n\t\tw <= 0;\n\t\t@(posedge clk);\n\t\t@(posedge clk);\n\t\treset <= 0;\n\t\t@(posedge clk);\n\t\t@(posedge clk);\n\t\t\n\t\ts <= 1;\n\n\t\trepeat(200) @(posedge clk, negedge clk) begin\n\t\t\tw <= $random;\n\t\tend\n\n\t\treset <= 1;\n\t\t@(posedge clk);\n\t\treset <= 0;\n\t\t@(posedge clk);\n\t\t@(posedge clk);\n\n\t\trepeat(200) @(posedge clk, negedge clk) begin\n\t\t\tw <= $random;\n\t\tend\n\t\t\n\t\t@(posedge clk)\t\t\n\t\t\tspulse_fail <= failed;\n\t\t\n\t\trepeat(500) @(negedge clk) begin\n\t\t\treset <= !($random & 63);\n\t\t\ts <= !($random & 7);\n\t\t\tw <= $random;\n\t\tend\n\n\t\tif (failed && !spulse_fail) begin\n\t\t\t$display (\"Hint: Your state machine should ignore input 's' after the state A to B transition.\");\n\t\tend\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_z;\n\t\tint errortime_z;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic reset;\n\tlogic s;\n\tlogic w;\n\tlogic z_ref;\n\tlogic z_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,s,w,z_ref,z_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.reset,\n\t\t.s,\n\t\t.w );\n\treference_module good1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.s,\n\t\t.w,\n\t\t.z(z_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.s,\n\t\t.w,\n\t\t.z(z_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_z) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"z\", stats1.errors_z, stats1.errortime_z);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"z\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { z_ref } === ( { z_ref } ^ { z_dut } ^ { z_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (z_ref !== ( z_ref ^ z_dut ^ z_ref ))\n\t\tbegin if (stats1.errors_z == 0) stats1.errortime_z = $time;\n\t\t\tstats1.errors_z = stats1.errors_z+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "vector4", "task_number": 119, "description": "One common place to see a replication operator is when sign-extending a smaller number to a larger one, while preserving its signed value. This is done by replicating the sign bit (the most significant bit) of the smaller number to the left. For example, sign-extending 4'b0101 (5) to 8 bits results in 8'b00000101 (5), while sign-extending 4'b1101 (-3) to 8 bits results in 8'b11111101 (-3). Build a circuit that sign-extends an 8-bit number to 32 bits. This requires a concatenation of 24 copies of the sign bit (i.e., replicate bit[7] 24 times) followed by the 8-bit number itself.", "header": "module top_module (\n\tinput [7:0] in,\n\toutput [31:0] out\n);\n", "module_code": "module top_module (\n\tinput [7:0] in,\n\toutput [31:0] out\n);\n\n\tassign out = { {24{in[7]}}, in };\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [7:0] in,\n\toutput [31:0] out\n);\n\n\tassign out = { {24{in[7]}}, in };\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic [7:0] in\n);\n\n\tinitial begin\n\t\trepeat(100) @(posedge clk, negedge clk)\n\t\t\tin <= $random;\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [7:0] in;\n\tlogic [31:0] out_ref;\n\tlogic [31:0] out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,in,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in );\n\treference_module good1 (\n\t\t.in,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.in,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "m2014_q4k", "task_number": 120, "description": "Implement a shift register with four D flops. Reset is active-low synchronous resettable.", "header": "module top_module (\n\tinput clk,\n\tinput resetn,\n\tinput in,\n\toutput out\n);\n", "module_code": "module top_module (\n\tinput clk,\n\tinput resetn,\n\tinput in,\n\toutput out\n);\n\n\treg [3:0] sr;\n\talways @(posedge clk) begin\n\t\tif (~resetn)\n\t\t\tsr <= '0;\n\t\telse \n\t\t\tsr <= {sr[2:0], in};\n\tend\n\t\n\tassign out = sr[3];\n\t\n\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput resetn,\n\tinput in,\n\toutput out\n);\n\n\treg [3:0] sr;\n\talways @(posedge clk) begin\n\t\tif (~resetn)\n\t\t\tsr <= '0;\n\t\telse \n\t\t\tsr <= {sr[2:0], in};\n\tend\n\t\n\tassign out = sr[3];\n\t\n\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic in, resetn\n);\n\n\tinitial begin\n\t\trepeat(100) @(posedge clk) begin\n\t\t\tin <= $random;\n\t\t\tresetn <= ($random & 7) != 0;\n\t\tend\n\t\trepeat(100) @(posedge clk, negedge clk) begin\n\t\t\tin <= $random;\n\t\t\tresetn <= ($random & 7) != 0;\n\t\tend\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic resetn;\n\tlogic in;\n\tlogic out_ref;\n\tlogic out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,resetn,in,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.resetn,\n\t\t.in );\n\treference_module good1 (\n\t\t.clk,\n\t\t.resetn,\n\t\t.in,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.resetn,\n\t\t.in,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "always_case2", "task_number": 121, "description": "A priority encoder is a combinational circuit that, when given an input bit vector, outputs the position of the first 1 bit in the vector. For example, a 8-bit priority encoder given the input 8'b10010000 would output 3'd4, because bit[4] is first bit that is high. Build a 4-bit priority encoder. For this problem, if none of the input bits are high (i.e., input is zero), output zero. Note that a 4-bit number has 16 possible combinations.", "header": "module top_module (\n\tinput [3:0] in,\n\toutput reg [1:0] pos\n);\n", "module_code": "module top_module (\n\tinput [3:0] in,\n\toutput reg [1:0] pos\n);\n\n\talways @(*) begin\n\t\tcase (in)\n\t\t\t4'h0: pos = 2'h0;\n\t\t\t4'h1: pos = 2'h0;\n\t\t\t4'h2: pos = 2'h1;\n\t\t\t4'h3: pos = 2'h0;\n\t\t\t4'h4: pos = 2'h2;\n\t\t\t4'h5: pos = 2'h0;\n\t\t\t4'h6: pos = 2'h1;\n\t\t\t4'h7: pos = 2'h0;\n\t\t\t4'h8: pos = 2'h3;\n\t\t\t4'h9: pos = 2'h0;\n\t\t\t4'ha: pos = 2'h1;\n\t\t\t4'hb: pos = 2'h0;\n\t\t\t4'hc: pos = 2'h2;\n\t\t\t4'hd: pos = 2'h0;\n\t\t\t4'he: pos = 2'h1;\n\t\t\t4'hf: pos = 2'h0;\n\t\t\tdefault: pos = 2'b0;\n\t\tendcase\n\tend\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [3:0] in,\n\toutput reg [1:0] pos\n);\n\n\talways @(*) begin\n\t\tcase (in)\n\t\t\t4'h0: pos = 2'h0;\n\t\t\t4'h1: pos = 2'h0;\n\t\t\t4'h2: pos = 2'h1;\n\t\t\t4'h3: pos = 2'h0;\n\t\t\t4'h4: pos = 2'h2;\n\t\t\t4'h5: pos = 2'h0;\n\t\t\t4'h6: pos = 2'h1;\n\t\t\t4'h7: pos = 2'h0;\n\t\t\t4'h8: pos = 2'h3;\n\t\t\t4'h9: pos = 2'h0;\n\t\t\t4'ha: pos = 2'h1;\n\t\t\t4'hb: pos = 2'h0;\n\t\t\t4'hc: pos = 2'h2;\n\t\t\t4'hd: pos = 2'h0;\n\t\t\t4'he: pos = 2'h1;\n\t\t\t4'hf: pos = 2'h0;\n\t\t\tdefault: pos = 2'b0;\n\t\tendcase\n\tend\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic [3:0] in, \n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\t@(negedge clk) wavedrom_start(\"Priority encoder\");\n\t\t\t@(posedge clk) in <= 4'h1;\n\t\t\trepeat(4) @(posedge clk) in <= in << 1;\n\t\t\tin <= 0;\n\t\t\trepeat(16) @(posedge clk) in <= in + 1;\n\t\t@(negedge clk) wavedrom_stop();\n\n\t\trepeat(50) @(posedge clk, negedge clk) begin\n\t\t\tin <= $urandom;\n\t\tend\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_pos;\n\t\tint errortime_pos;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [3:0] in;\n\tlogic [1:0] pos_ref;\n\tlogic [1:0] pos_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,in,pos_ref,pos_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in );\n\treference_module good1 (\n\t\t.in,\n\t\t.pos(pos_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.in,\n\t\t.pos(pos_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_pos) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"pos\", stats1.errors_pos, stats1.errortime_pos);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"pos\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { pos_ref } === ( { pos_ref } ^ { pos_dut } ^ { pos_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (pos_ref !== ( pos_ref ^ pos_dut ^ pos_ref ))\n\t\tbegin if (stats1.errors_pos == 0) stats1.errortime_pos = $time;\n\t\t\tstats1.errors_pos = stats1.errors_pos+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "fsm2", "task_number": 122, "description": "This is a Moore state machine with two states, two inputs, and one output. Implement this state machine in Verilog. Reset is an active-high asynchronous reset to state OFF.\n\n// OFF (out=0) --j=0--> OFF\n// OFF (out=0) --j=1--> ON\n// ON (out=1) --k=0--> ON\n// ON (out=1) --k=1--> OFF", "header": "module top_module (\n\tinput clk,\n\tinput j,\n\tinput k,\n\tinput areset,\n\toutput out\n);\n", "module_code": "module top_module (\n\tinput clk,\n\tinput j,\n\tinput k,\n\tinput areset,\n\toutput out\n);\n\tparameter A=0, B=1;\n\treg state;\n\treg next;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tA: next = j ? B : A;\n\t\t\tB: next = k ? A : B;\n\t\tendcase\n    end\n    \n    always @(posedge clk, posedge areset) begin\n\t\tif (areset) state <= A;\n        else state <= next;\n\tend\n\t\t\n\tassign out = (state==B);\n\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput j,\n\tinput k,\n\tinput areset,\n\toutput out\n);\n\tparameter A=0, B=1;\n\treg state;\n\treg next;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tA: next = j ? B : A;\n\t\t\tB: next = k ? A : B;\n\t\tendcase\n    end\n    \n    always @(posedge clk, posedge areset) begin\n\t\tif (areset) state <= A;\n        else state <= next;\n\tend\n\t\t\n\tassign out = (state==B);\n\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic j, k,\n\toutput logic areset,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\tinput tb_match\n);\n\n\treg reset;\n\tassign areset = reset;\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\treg [0:11][1:0] d = 24'b000101010010101111111111;\n\t\n\tinitial begin\n\t\treset <= 1;\n\t\tj <= 0;\n\t\tk <= 0;\n\t\t@(posedge clk);\n\t\treset <= 0;\n\t\tj <= 1;\n\t\t@(posedge clk);\n\t\tj <= 0;\n\t\twavedrom_start(\"Reset and transitions\");\n\t\treset_test(1);\n\t\tfor (int i=0;i<12;i++)\n\t\t\t@(posedge clk) {k, j} <= d[i];\n\t\twavedrom_stop();\n\t\trepeat(200) @(posedge clk, negedge clk) begin\n\t\t\t{j,k} <= $random;\n\t\t\treset <= !($random & 7);\n\t\tend\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic j;\n\tlogic k;\n\tlogic areset;\n\tlogic out_ref;\n\tlogic out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,j,k,areset,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.j,\n\t\t.k,\n\t\t.areset );\n\treference_module good1 (\n\t\t.clk,\n\t\t.j,\n\t\t.k,\n\t\t.areset,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.j,\n\t\t.k,\n\t\t.areset,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "m2014_q4i", "task_number": 123, "description": "Build a circuit with no inputs and one output. That output should always drive 0 (or logic low).", "header": "module top_module(\n\toutput out);\n", "module_code": "module top_module(\n\toutput out);\n\t\n\tassign out = 1'b0;\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\toutput out);\n\t\n\tassign out = 1'b0;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk\n);\n\n\tinitial begin\n\t\trepeat(100) @(posedge clk, negedge clk) begin\n\t\t\t\n\t\tend\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic out_ref;\n\tlogic out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.*  );\n\treference_module good1 (\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "step_one", "task_number": 124, "description": "Build a circuit with no inputs and one output. That output should always drive 1 (or logic high).", "header": "module top_module(\n\toutput one);\n", "module_code": "module top_module(\n\toutput one);\n\t\n\tassign one = 1'b1;\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\toutput one);\n\t\n\tassign one = 1'b1;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\twavedrom_start(\"Output should be 1\");\n\t\trepeat(20) @(posedge clk, negedge clk);\n\t\twavedrom_stop();\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_one;\n\t\tint errortime_one;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic one_ref;\n\tlogic one_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,one_ref,one_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.*  );\n\treference_module good1 (\n\t\t.one(one_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.one(one_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_one) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"one\", stats1.errors_one, stats1.errortime_one);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"one\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { one_ref } === ( { one_ref } ^ { one_dut } ^ { one_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (one_ref !== ( one_ref ^ one_dut ^ one_ref ))\n\t\tbegin if (stats1.errors_one == 0) stats1.errortime_one = $time;\n\t\t\tstats1.errors_one = stats1.errors_one+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "vector100r", "task_number": 125, "description": "Given a 100-bit input vector [99:0], reverse its bit ordering.", "header": "module top_module (\n\tinput [99:0] in,\n\toutput reg [99:0] out\n);\n", "module_code": "module top_module (\n\tinput [99:0] in,\n\toutput reg [99:0] out\n);\n\t\n\talways_comb \n\t\tfor (int i=0;i<$bits(out);i++)\n\t\t\tout[i] = in[$bits(out)-i-1];\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [99:0] in,\n\toutput reg [99:0] out\n);\n\t\n\talways_comb \n\t\tfor (int i=0;i<$bits(out);i++)\n\t\t\tout[i] = in[$bits(out)-i-1];\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic [99:0] in\n);\n\n\talways @(posedge clk, negedge clk)\n\t\tin <= {$random, $random, $random, $random};\n\t\n\tinitial begin\n\t\trepeat(100) @(negedge clk);\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [99:0] in;\n\tlogic [99:0] out_ref;\n\tlogic [99:0] out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,in,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in );\n\treference_module good1 (\n\t\t.in,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.in,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "m2014_q4d", "task_number": 126, "description": "Implement in Verilog the following circuit: A D flip-flop takes as input the output of a two-input XOR. The flip-flop is positive edge triggered by clk, but there is no reset. The XOR takes as input 'in' along with the output 'out' of the flip-flop.", "header": "module top_module (\n\tinput clk,\n\tinput in,\n\toutput logic out\n);\n", "module_code": "module top_module (\n\tinput clk,\n\tinput in,\n\toutput logic out\n);\n\n\tinitial\n\t\tout = 0;\n\t\t\n\talways@(posedge clk) begin\n\t\tout <= in ^ out;\n\tend\n\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput in,\n\toutput logic out\n);\n\n\tinitial\n\t\tout = 0;\n\t\t\n\talways@(posedge clk) begin\n\t\tout <= in ^ out;\n\tend\n\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic in\n);\n\n\tinitial begin\n\t\trepeat(100) @(posedge clk, negedge clk) begin\n\t\t\tin <= $random;\n\t\tend\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic in;\n\tlogic out_ref;\n\tlogic out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,in,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in );\n\treference_module good1 (\n\t\t.clk,\n\t\t.in,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.in,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "shift4", "task_number": 127, "description": "Build a 4-bit shift register (right shift), with asynchronous positive edge triggered areset, synchronous active high signals load, and enable. \n// (1) areset: Resets shift register to zero. \n// (2) load: Loads shift register with data[3:0] instead of shifting. \n// (3) ena: Shift right (q[3] becomes zero, q[0] is shifted out and disappears). \n// (4) q: The contents of the shift register. If both the load and ena inputs are asserted (1), the load input has higher priority. \n", "header": "module top_module(\n\tinput clk,\n\tinput areset,\n\tinput load,\n\tinput ena,\n\tinput [3:0] data,\n\toutput reg [3:0] q);\n", "module_code": "module top_module(\n\tinput clk,\n\tinput areset,\n\tinput load,\n\tinput ena,\n\tinput [3:0] data,\n\toutput reg [3:0] q);\n\t\n\t\n\talways @(posedge clk, posedge areset) begin\n\t\tif (areset)\n\t\t\tq <= 0;\n\t\telse if (load)\n\t\t\tq <= data;\n\t\telse if (ena)\n\t\t\tq <= q[3:1];\n\tend\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput clk,\n\tinput areset,\n\tinput load,\n\tinput ena,\n\tinput [3:0] data,\n\toutput reg [3:0] q);\n\t\n\t\n\talways @(posedge clk, posedge areset) begin\n\t\tif (areset)\n\t\t\tq <= 0;\n\t\telse if (load)\n\t\t\tq <= data;\n\t\telse if (ena)\n\t\t\tq <= q[3:1];\n\tend\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput areset,\n\toutput reg load,\n\toutput reg ena,\n\toutput reg[3:0] data,\n\t\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\tinput tb_match\n);\n\treg reset;\n\tassign areset = reset;\n\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\n\tinitial begin\n\t\t{load, ena, reset, data} <= 7'h40;\n\t\t@(posedge clk) {load, ena, reset, data} <= 7'h4f;\n\t\twavedrom_start(\"Load and reset\");\n\t\t@(posedge clk) {load, ena, reset, data} <= 7'h0x;\n\t\t@(posedge clk) {load, ena, reset, data} <= 7'h2x;\n\t\t@(posedge clk) {load, ena, reset, data} <= 7'h2x;\n\t\t@(posedge clk) {load, ena, reset, data} <= 7'h0x;\n\t\treset_test(1);\n\t\t@(posedge clk);\n\t\t@(posedge clk);\n\t\twavedrom_stop();\n\t\t\n\t\trepeat(400) @(posedge clk, negedge clk) begin\n\t\t\treset <= !($random & 31);\n\t\t\tload <= !($random & 15);\n\t\t\tena <= |($random & 31);\n\t\t\tdata <= $random;\n\t\tend\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_q;\n\t\tint errortime_q;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic areset;\n\tlogic load;\n\tlogic ena;\n\tlogic [3:0] data;\n\tlogic [3:0] q_ref;\n\tlogic [3:0] q_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,areset,load,ena,data,q_ref,q_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.areset,\n\t\t.load,\n\t\t.ena,\n\t\t.data );\n\treference_module good1 (\n\t\t.clk,\n\t\t.areset,\n\t\t.load,\n\t\t.ena,\n\t\t.data,\n\t\t.q(q_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.areset,\n\t\t.load,\n\t\t.ena,\n\t\t.data,\n\t\t.q(q_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"q\", stats1.errors_q, stats1.errortime_q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"q\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (q_ref !== ( q_ref ^ q_dut ^ q_ref ))\n\t\tbegin if (stats1.errors_q == 0) stats1.errortime_q = $time;\n\t\t\tstats1.errors_q = stats1.errors_q+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "truthtable1", "task_number": 128, "description": "Create a combinational circuit that implements the truth table.\n\n// x3 | x2 | x1 | f\n// 0 | 0 | 0 | 0\n// 0 | 0 | 1 | 0\n// 0 | 1 | 0 | 1\n// 0 | 1 | 1 | 1\n// 1 | 0 | 0 | 0\n// 1 | 0 | 1 | 1\n// 1 | 1 | 0 | 0\n// 1 | 1 | 1 | 1", "header": "module top_module (\n\tinput x3,\n\tinput x2,\n\tinput x1,\n\toutput f\n);\n", "module_code": "module top_module (\n\tinput x3,\n\tinput x2,\n\tinput x1,\n\toutput f\n);\n\t\n\tassign f = ( ~x3 & x2 & ~x1 ) | \n\t\t\t\t( ~x3 & x2 & x1 ) |\n\t\t\t\t( x3 & ~x2 & x1 ) |\n\t\t\t\t( x3 & x2 & x1 ) ;\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput x3,\n\tinput x2,\n\tinput x1,\n\toutput f\n);\n\t\n\tassign f = ( ~x3 & x2 & ~x1 ) | \n\t\t\t\t( ~x3 & x2 & x1 ) |\n\t\t\t\t( x3 & ~x2 & x1 ) |\n\t\t\t\t( x3 & x2 & x1 ) ;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg x3, x2, x1,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\tinitial begin\n\t\t{x3, x2, x1} <= 3'h7;\n\t\t@(negedge clk) wavedrom_start(\"All 8 input combinations\");\n\t\trepeat(8) @(posedge clk) {x3, x2, x1} <= {x3, x2, x1} + 1'b1;\n\t\t@(negedge clk) wavedrom_stop();\n\t\trepeat(40) @(posedge clk, negedge clk);\n\t\t{x3, x2, x1} <= $random;\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_f;\n\t\tint errortime_f;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic x3;\n\tlogic x2;\n\tlogic x1;\n\tlogic f_ref;\n\tlogic f_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,x3,x2,x1,f_ref,f_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.x3,\n\t\t.x2,\n\t\t.x1 );\n\treference_module good1 (\n\t\t.x3,\n\t\t.x2,\n\t\t.x1,\n\t\t.f(f_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.x3,\n\t\t.x2,\n\t\t.x1,\n\t\t.f(f_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_f) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"f\", stats1.errors_f, stats1.errortime_f);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"f\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { f_ref } === ( { f_ref } ^ { f_dut } ^ { f_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (f_ref !== ( f_ref ^ f_dut ^ f_ref ))\n\t\tbegin if (stats1.errors_f == 0) stats1.errortime_f = $time;\n\t\t\tstats1.errors_f = stats1.errors_f+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "dff8ar", "task_number": 129, "description": "Create 8 D flip-flops with active high asynchronous reset. The output should be reset to 0. All DFFs should be triggered by the positive edge of clk.", "header": "module top_module(\n\tinput clk,\n\tinput [7:0] d,\n\tinput areset,\n\toutput reg [7:0] q);\n", "module_code": "module top_module(\n\tinput clk,\n\tinput [7:0] d,\n\tinput areset,\n\toutput reg [7:0] q);\n\t\n\talways @(posedge clk, posedge areset)\n\t\tif (areset)\n\t\t\tq <= 0;\n\t\telse\n\t\t\tq <= d;\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput clk,\n\tinput [7:0] d,\n\tinput areset,\n\toutput reg [7:0] q);\n\t\n\talways @(posedge clk, posedge areset)\n\t\tif (areset)\n\t\t\tq <= 0;\n\t\telse\n\t\t\tq <= d;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg [7:0] d, output areset,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\tinput tb_match\t\t\n);\n\n\treg reset;\n\tassign areset = reset;\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\t\n\t\n\tinitial begin\n\t\treset <= 1;\n\t\td <= $random;\n\t\t@(negedge clk);\n\t\t@(negedge clk);\n\t\twavedrom_start(\"Asynchronous active-high reset\");\n\t\treset_test(1);\n\t\trepeat(7) @(negedge clk) d <= $random;\n\t\t@(posedge clk) reset <= 1;\n\t\t@(negedge clk) reset <= 0; d <= $random;\n\t\trepeat(2) @(negedge clk) d <= $random;\n\t\twavedrom_stop();\n\n\n\t\trepeat(400) @(posedge clk, negedge clk) begin\n\t\t\treset <= !($random & 15);\n\t\t\td <= $random;\n\t\tend\n\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_q;\n\t\tint errortime_q;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [7:0] d;\n\tlogic areset;\n\tlogic [7:0] q_ref;\n\tlogic [7:0] q_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,d,areset,q_ref,q_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.d,\n\t\t.areset );\n\treference_module good1 (\n\t\t.clk,\n\t\t.d,\n\t\t.areset,\n\t\t.q(q_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.d,\n\t\t.areset,\n\t\t.q(q_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"q\", stats1.errors_q, stats1.errortime_q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"q\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (q_ref !== ( q_ref ^ q_dut ^ q_ref ))\n\t\tbegin if (stats1.errors_q == 0) stats1.errortime_q = $time;\n\t\t\tstats1.errors_q = stats1.errors_q+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "gates100", "task_number": 130, "description": "Build a combinational circuit with 100 inputs, in[99:0]. There are 3 outputs: \n// (1) out_and: output of a 100-input AND gate. \n// (2) out_or: output of a 100-input OR gate. \n// (3) out_xor: output of a 100-input XOR gate.\n\n", "header": "module top_module (\n\tinput [99:0] in,\n\toutput out_and,\n\toutput out_or,\n\toutput out_xor\n);\n", "module_code": "module top_module (\n\tinput [99:0] in,\n\toutput out_and,\n\toutput out_or,\n\toutput out_xor\n);\n\n\tassign out_and = &in;\n\tassign out_or = |in;\n\tassign out_xor = ^in;\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [99:0] in,\n\toutput out_and,\n\toutput out_or,\n\toutput out_xor\n);\n\n\tassign out_and = &in;\n\tassign out_or = |in;\n\tassign out_xor = ^in;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\tinput tb_match,\n\toutput logic [99:0] in,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\tinitial begin\n\t\treg [3:0] count; count = 0;\n\t\tin <= 100'h0;\n\t\t// AND gate uses huge numbers and creates a sparse waveform.\n\t\t@(negedge clk) wavedrom_start(\"Test AND gate\");\n\t\t\t@(posedge clk,negedge clk) in <= 100'h0;\t\t// Test OR gate\n\t\t\t@(posedge clk,negedge clk); in <= ~100'h0;\t\t// Test AND gate\n\t\t\t@(posedge clk,negedge clk); in <= 100'h3ffff;\t\n\t\t\t@(posedge clk,negedge clk); in <= ~100'h3ffff;\t\n\t\t\t@(posedge clk,negedge clk); in <= 100'h80;\t\t\n\t\t\t@(posedge clk,negedge clk); in <= ~100'h80;\t\t\n\t\twavedrom_stop();\n\n\t\t@(negedge clk) wavedrom_start(\"Test OR and XOR gates\");\n\t\t\t@(posedge clk) in <= 100'h0;\t\t// Test OR gate\n\t\t\t@(posedge clk); in <= 100'h7;\t\t// Test AND gate\n\t\t\trepeat(10) @(posedge clk, negedge clk) begin\n\t\t\t\tin <= count;\t\t\n\t\t\t\tcount <= count + 1;\n\t\t\tend\n\t\t\t@(posedge clk) in <= 100'h0;\n\t\t@(negedge clk) wavedrom_stop();\n\t\t\n\t\tin <= $random;\n\t\trepeat(100) begin\n\t\t\t@(negedge clk) in <= $random;\n\t\t\t@(posedge clk) in <= $random;\n\t\tend\n\t\tfor (int i=0;i<100;i++) begin\n\t\t\t@(negedge clk) in <= 100'h1<<i;\n\t\t\t@(posedge clk) in <= ~(100'h1<<i);\n\t\tend\n\t\t@(posedge clk) in <= 100'h0;\t\t// Test OR gate\n\t\t@(posedge clk); in <= ~100'h0;\t\t// Test AND gate\n\t\t@(posedge clk);\n\t\t#1 $finish;\n\tend\n\t\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out_and;\n\t\tint errortime_out_and;\n\t\tint errors_out_or;\n\t\tint errortime_out_or;\n\t\tint errors_out_xor;\n\t\tint errortime_out_xor;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [99:0] in;\n\tlogic out_and_ref;\n\tlogic out_and_dut;\n\tlogic out_or_ref;\n\tlogic out_or_dut;\n\tlogic out_xor_ref;\n\tlogic out_xor_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,in,out_and_ref,out_and_dut,out_or_ref,out_or_dut,out_xor_ref,out_xor_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in );\n\treference_module good1 (\n\t\t.in,\n\t\t.out_and(out_and_ref),\n\t\t.out_or(out_or_ref),\n\t\t.out_xor(out_xor_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.in,\n\t\t.out_and(out_and_dut),\n\t\t.out_or(out_or_dut),\n\t\t.out_xor(out_xor_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out_and) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_and\", stats1.errors_out_and, stats1.errortime_out_and);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_and\");\n\t\tif (stats1.errors_out_or) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_or\", stats1.errors_out_or, stats1.errortime_out_or);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_or\");\n\t\tif (stats1.errors_out_xor) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_xor\", stats1.errors_out_xor, stats1.errortime_out_xor);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_xor\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_and_ref, out_or_ref, out_xor_ref } === ( { out_and_ref, out_or_ref, out_xor_ref } ^ { out_and_dut, out_or_dut, out_xor_dut } ^ { out_and_ref, out_or_ref, out_xor_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_and_ref !== ( out_and_ref ^ out_and_dut ^ out_and_ref ))\n\t\tbegin if (stats1.errors_out_and == 0) stats1.errortime_out_and = $time;\n\t\t\tstats1.errors_out_and = stats1.errors_out_and+1'b1; end\n\t\tif (out_or_ref !== ( out_or_ref ^ out_or_dut ^ out_or_ref ))\n\t\tbegin if (stats1.errors_out_or == 0) stats1.errortime_out_or = $time;\n\t\t\tstats1.errors_out_or = stats1.errors_out_or+1'b1; end\n\t\tif (out_xor_ref !== ( out_xor_ref ^ out_xor_dut ^ out_xor_ref ))\n\t\tbegin if (stats1.errors_out_xor == 0) stats1.errortime_out_xor = $time;\n\t\t\tstats1.errors_out_xor = stats1.errors_out_xor+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "hadd", "task_number": 131, "description": "Create a half adder. A half adder adds two bits (with no carry-in) and produces a sum and carry-out.", "header": "module top_module (\n\tinput a,\n\tinput b,\n\toutput sum,\n\toutput cout\n);\n", "module_code": "module top_module (\n\tinput a,\n\tinput b,\n\toutput sum,\n\toutput cout\n);\n\n\tassign {cout, sum} = a+b;\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput a,\n\tinput b,\n\toutput sum,\n\toutput cout\n);\n\n\tassign {cout, sum} = a+b;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic a,b\n);\n\n\talways @(posedge clk, negedge clk)\n\t\t{a,b} <= $random;\n\t\n\tinitial begin\n\t\trepeat(100) @(negedge clk);\n\t\t$finish;\n\tend\n\t\nendmodule\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_sum;\n\t\tint errortime_sum;\n\t\tint errors_cout;\n\t\tint errortime_cout;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic a;\n\tlogic b;\n\tlogic sum_ref;\n\tlogic sum_dut;\n\tlogic cout_ref;\n\tlogic cout_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,a,b,sum_ref,sum_dut,cout_ref,cout_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.a,\n\t\t.b );\n\treference_module good1 (\n\t\t.a,\n\t\t.b,\n\t\t.sum(sum_ref),\n\t\t.cout(cout_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.a,\n\t\t.b,\n\t\t.sum(sum_dut),\n\t\t.cout(cout_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_sum) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"sum\", stats1.errors_sum, stats1.errortime_sum);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"sum\");\n\t\tif (stats1.errors_cout) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"cout\", stats1.errors_cout, stats1.errortime_cout);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"cout\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { sum_ref, cout_ref } === ( { sum_ref, cout_ref } ^ { sum_dut, cout_dut } ^ { sum_ref, cout_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (sum_ref !== ( sum_ref ^ sum_dut ^ sum_ref ))\n\t\tbegin if (stats1.errors_sum == 0) stats1.errortime_sum = $time;\n\t\t\tstats1.errors_sum = stats1.errors_sum+1'b1; end\n\t\tif (cout_ref !== ( cout_ref ^ cout_dut ^ cout_ref ))\n\t\tbegin if (stats1.errors_cout == 0) stats1.errortime_cout = $time;\n\t\t\tstats1.errors_cout = stats1.errors_cout+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "always_if2", "task_number": 132, "description": "Fix any and all bugs in this code:\n\n// module top_module (\n//     input      cpu_overheated,\n//     output reg shut_off_computer,\n//     input      arrived,\n//     input      gas_tank_empty,\n//     output reg keep_driving  ); //\n\n//     always @(*) begin\n//         if (cpu_overheated)\n//            shut_off_computer = 1;\n//     end\n\n//     always @(*) begin\n//         if (~arrived)\n//            keep_driving = ~gas_tank_empty;\n//     end\n\n// endmodule\n", "header": "module top_module (\n\tinput cpu_overheated,\n\toutput reg shut_off_computer,\n\tinput arrived,\n\tinput gas_tank_empty,\n\toutput reg keep_driving\n);\n", "module_code": "module top_module (\n\tinput cpu_overheated,\n\toutput reg shut_off_computer,\n\tinput arrived,\n\tinput gas_tank_empty,\n\toutput reg keep_driving\n);\n\n\talways @(*) begin\n\t\tif (cpu_overheated)\n\t\t\tshut_off_computer = 1;\n\t\telse\n\t\t\tshut_off_computer = 0;\n\tend\n\t\n\talways @(*) begin\n\t\tif (~arrived)\n\t\t\tkeep_driving = !gas_tank_empty;\n\t\telse\n\t\t\tkeep_driving = 1'b0;\n\tend\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput cpu_overheated,\n\toutput reg shut_off_computer,\n\tinput arrived,\n\tinput gas_tank_empty,\n\toutput reg keep_driving\n);\n\n\talways @(*) begin\n\t\tif (cpu_overheated)\n\t\t\tshut_off_computer = 1;\n\t\telse\n\t\t\tshut_off_computer = 0;\n\tend\n\t\n\talways @(*) begin\n\t\tif (~arrived)\n\t\t\tkeep_driving = !gas_tank_empty;\n\t\telse\n\t\t\tkeep_driving = 1'b0;\n\tend\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic cpu_overheated, arrived, gas_tank_empty,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tlogic [2:0] s = 3'b010;\n\tassign {cpu_overheated, arrived, gas_tank_empty} = s;\n\n\tinitial begin\n\t\t@(negedge clk) wavedrom_start(\"\");\n\t\t@(posedge clk) s <= 3'b010;\n\t\t@(posedge clk) s <= 3'b100;\n\t\t@(posedge clk) s <= 3'b100;\n\t\t@(posedge clk) s <= 3'b001;\n\t\t@(posedge clk) s <= 3'b000;\n\t\t@(posedge clk) s <= 3'b100;\n\t\t@(posedge clk) s <= 3'b110;\n\t\t@(posedge clk) s <= 3'b111;\n\t\t@(posedge clk) s <= 3'b111;\n\t\t@(posedge clk) s <= 3'b111;\n\t\twavedrom_stop();\n\t\trepeat(100) @(posedge clk, negedge clk)\n\t\t\ts <= $urandom;\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_shut_off_computer;\n\t\tint errortime_shut_off_computer;\n\t\tint errors_keep_driving;\n\t\tint errortime_keep_driving;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic cpu_overheated;\n\tlogic arrived;\n\tlogic gas_tank_empty;\n\tlogic shut_off_computer_ref;\n\tlogic shut_off_computer_dut;\n\tlogic keep_driving_ref;\n\tlogic keep_driving_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,cpu_overheated,arrived,gas_tank_empty,shut_off_computer_ref,shut_off_computer_dut,keep_driving_ref,keep_driving_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.cpu_overheated,\n\t\t.arrived,\n\t\t.gas_tank_empty );\n\treference_module good1 (\n\t\t.cpu_overheated,\n\t\t.arrived,\n\t\t.gas_tank_empty,\n\t\t.shut_off_computer(shut_off_computer_ref),\n\t\t.keep_driving(keep_driving_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.cpu_overheated,\n\t\t.arrived,\n\t\t.gas_tank_empty,\n\t\t.shut_off_computer(shut_off_computer_dut),\n\t\t.keep_driving(keep_driving_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_shut_off_computer) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"shut_off_computer\", stats1.errors_shut_off_computer, stats1.errortime_shut_off_computer);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"shut_off_computer\");\n\t\tif (stats1.errors_keep_driving) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"keep_driving\", stats1.errors_keep_driving, stats1.errortime_keep_driving);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"keep_driving\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { shut_off_computer_ref, keep_driving_ref } === ( { shut_off_computer_ref, keep_driving_ref } ^ { shut_off_computer_dut, keep_driving_dut } ^ { shut_off_computer_ref, keep_driving_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (shut_off_computer_ref !== ( shut_off_computer_ref ^ shut_off_computer_dut ^ shut_off_computer_ref ))\n\t\tbegin if (stats1.errors_shut_off_computer == 0) stats1.errortime_shut_off_computer = $time;\n\t\t\tstats1.errors_shut_off_computer = stats1.errors_shut_off_computer+1'b1; end\n\t\tif (keep_driving_ref !== ( keep_driving_ref ^ keep_driving_dut ^ keep_driving_ref ))\n\t\tbegin if (stats1.errors_keep_driving == 0) stats1.errortime_keep_driving = $time;\n\t\t\tstats1.errors_keep_driving = stats1.errors_keep_driving+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "fsm2s", "task_number": 133, "description": "This is a Moore state machine with two states, two inputs, and one output. Implement this state machine in Verilog. Reset is an active-high synchronous reset to state OFF.\n\n// OFF (out=0) --j=0--> OFF\n// OFF (out=0) --j=1--> ON\n// ON (out=1) --k=0--> ON\n// ON (out=1) --k=1--> OFF", "header": "module top_module (\n\tinput clk,\n\tinput j,\n\tinput k,\n\tinput reset,\n\toutput out\n);\n", "module_code": "module top_module (\n\tinput clk,\n\tinput j,\n\tinput k,\n\tinput reset,\n\toutput out\n);\n\tparameter A=0, B=1;\n\treg state;\n\treg next;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tA: next = j ? B : A;\n\t\t\tB: next = k ? A : B;\n\t\tendcase\n    end\n    \n    always @(posedge clk) begin\n\t\tif (reset) state <= A;\n        else state <= next;\n\tend\n\t\t\n\tassign out = (state==B);\n\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput j,\n\tinput k,\n\tinput reset,\n\toutput out\n);\n\tparameter A=0, B=1;\n\treg state;\n\treg next;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tA: next = j ? B : A;\n\t\t\tB: next = k ? A : B;\n\t\tendcase\n    end\n    \n    always @(posedge clk) begin\n\t\tif (reset) state <= A;\n        else state <= next;\n\tend\n\t\t\n\tassign out = (state==B);\n\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic j, k,\n\toutput logic reset,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\tinput tb_match\n);\n\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\treg [0:11][1:0] d = 24'b000101010010101111111111;\n\t\n\tinitial begin\n\t\treset <= 1;\n\t\tj <= 0;\n\t\tk <= 0;\n\t\t@(posedge clk);\n\t\treset <= 0;\n\t\tj <= 1;\n\t\t@(posedge clk);\n\t\tj <= 0;\n\t\twavedrom_start(\"Reset and transitions\");\n\t\treset_test();\n\t\tfor (int i=0;i<12;i++)\n\t\t\t@(posedge clk) {k, j} <= d[i];\n\t\twavedrom_stop();\n\t\trepeat(200) @(posedge clk, negedge clk) begin\n\t\t\t{j,k} <= $random;\n\t\t\treset <= !($random & 7);\n\t\tend\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic j;\n\tlogic k;\n\tlogic reset;\n\tlogic out_ref;\n\tlogic out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,j,k,reset,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.j,\n\t\t.k,\n\t\t.reset );\n\treference_module good1 (\n\t\t.clk,\n\t\t.j,\n\t\t.k,\n\t\t.reset,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.j,\n\t\t.k,\n\t\t.reset,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "vector3", "task_number": 134, "description": "Given several input vectors, concatenate them together then split them up into several output vectors. There are six 5-bit input vectors: a, b, c, d, e, and f, for a total of 30 bits of input. There are four 8-bit output vectors: w, x, y, and z, for 32 bits of output. The output should be a concatenation of the input vectors followed by two 1 bits (the two 1 bits should be in the LSB positions).", "header": "module top_module (\n\tinput [4:0] a,\n\tinput [4:0] b,\n\tinput [4:0] c,\n\tinput [4:0] d,\n\tinput [4:0] e,\n\tinput [4:0] f,\n\toutput [7:0] w,\n\toutput [7:0] x,\n\toutput [7:0] y,\n\toutput [7:0] z\n);\n", "module_code": "module top_module (\n\tinput [4:0] a,\n\tinput [4:0] b,\n\tinput [4:0] c,\n\tinput [4:0] d,\n\tinput [4:0] e,\n\tinput [4:0] f,\n\toutput [7:0] w,\n\toutput [7:0] x,\n\toutput [7:0] y,\n\toutput [7:0] z\n);\n\n\tassign { w,x,y,z} = {a,b,c,d,e,f,2'b11};\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [4:0] a,\n\tinput [4:0] b,\n\tinput [4:0] c,\n\tinput [4:0] d,\n\tinput [4:0] e,\n\tinput [4:0] f,\n\toutput [7:0] w,\n\toutput [7:0] x,\n\toutput [7:0] y,\n\toutput [7:0] z\n);\n\n\tassign { w,x,y,z} = {a,b,c,d,e,f,2'b11};\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic [4:0] a,b,c,d,e,f,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\tinitial begin\n\t\twavedrom_start(\"\");\n\t\t@(posedge clk) {a,b,c,d,e,f} <= '0;\n\t\t@(posedge clk) {a,b,c,d,e,f} <= 1;\n\t\t@(posedge clk) {a,b,c,d,e,f} <= 2;\n\t\t@(posedge clk) {a,b,c,d,e,f} <= 4;\n\t\t@(posedge clk) {a,b,c,d,e,f} <= 8;\n\t\t@(posedge clk) {a,b,c,d,e,f} <= 'h10;\n\t\t@(posedge clk) {a,b,c,d,e,f} <= 'h20;\n\t\t@(posedge clk) {a,b,c,d,e,f} <= 'h40;\n\t\t@(posedge clk) {a,b,c,d,e,f} <= 'h80;\n\t\t@(posedge clk) {a,b,c,d,e,f} <= 'h100;\n\t\t@(posedge clk) {a,b,c,d,e,f} <= 'h200;\n\t\t@(posedge clk) {a,b,c,d,e,f} <= 'h400;\n\t\t@(posedge clk) {a,b,c,d,e,f} <= {5'h1f, 5'h0, 5'h1f, 5'h0, 5'h1f, 5'h0};\n\t\t@(negedge clk);\n\t\twavedrom_stop();\n\t\trepeat(100) @(posedge clk, negedge clk)\n\t\t\t{a,b,c,d,e,f} <= $random;\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_w;\n\t\tint errortime_w;\n\t\tint errors_x;\n\t\tint errortime_x;\n\t\tint errors_y;\n\t\tint errortime_y;\n\t\tint errors_z;\n\t\tint errortime_z;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [4:0] a;\n\tlogic [4:0] b;\n\tlogic [4:0] c;\n\tlogic [4:0] d;\n\tlogic [4:0] e;\n\tlogic [4:0] f;\n\tlogic [7:0] w_ref;\n\tlogic [7:0] w_dut;\n\tlogic [7:0] x_ref;\n\tlogic [7:0] x_dut;\n\tlogic [7:0] y_ref;\n\tlogic [7:0] y_dut;\n\tlogic [7:0] z_ref;\n\tlogic [7:0] z_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,a,b,c,d,e,f,w_ref,w_dut,x_ref,x_dut,y_ref,y_dut,z_ref,z_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d,\n\t\t.e,\n\t\t.f );\n\treference_module good1 (\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d,\n\t\t.e,\n\t\t.f,\n\t\t.w(w_ref),\n\t\t.x(x_ref),\n\t\t.y(y_ref),\n\t\t.z(z_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d,\n\t\t.e,\n\t\t.f,\n\t\t.w(w_dut),\n\t\t.x(x_dut),\n\t\t.y(y_dut),\n\t\t.z(z_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_w) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"w\", stats1.errors_w, stats1.errortime_w);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"w\");\n\t\tif (stats1.errors_x) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"x\", stats1.errors_x, stats1.errortime_x);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"x\");\n\t\tif (stats1.errors_y) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"y\", stats1.errors_y, stats1.errortime_y);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"y\");\n\t\tif (stats1.errors_z) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"z\", stats1.errors_z, stats1.errortime_z);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"z\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { w_ref, x_ref, y_ref, z_ref } === ( { w_ref, x_ref, y_ref, z_ref } ^ { w_dut, x_dut, y_dut, z_dut } ^ { w_ref, x_ref, y_ref, z_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (w_ref !== ( w_ref ^ w_dut ^ w_ref ))\n\t\tbegin if (stats1.errors_w == 0) stats1.errortime_w = $time;\n\t\t\tstats1.errors_w = stats1.errors_w+1'b1; end\n\t\tif (x_ref !== ( x_ref ^ x_dut ^ x_ref ))\n\t\tbegin if (stats1.errors_x == 0) stats1.errortime_x = $time;\n\t\t\tstats1.errors_x = stats1.errors_x+1'b1; end\n\t\tif (y_ref !== ( y_ref ^ y_dut ^ y_ref ))\n\t\tbegin if (stats1.errors_y == 0) stats1.errortime_y = $time;\n\t\t\tstats1.errors_y = stats1.errors_y+1'b1; end\n\t\tif (z_ref !== ( z_ref ^ z_dut ^ z_ref ))\n\t\tbegin if (stats1.errors_z == 0) stats1.errortime_z = $time;\n\t\t\tstats1.errors_z = stats1.errors_z+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "circuit2", "task_number": 135, "description": "This is a combinational circuit. Read the simulation waveforms to determine what the circuit does, then implement it.\n\n// time            a               b               c               d               q               \n// 0ns             0               0               0               0               1               \n// 5ns             0               0               0               0               1               \n// 10ns            0               0               0               0               1               \n// 15ns            0               0               0               0               1               \n// 20ns            0               0               0               1               0               \n// 25ns            0               0               1               0               0               \n// 30ns            0               0               1               1               1               \n// 35ns            0               1               0               0               0               \n// 40ns            0               1               0               1               1               \n// 45ns            0               1               1               0               1               \n// 50ns            0               1               1               1               0               \n// 55ns            1               0               0               0               0               \n// 60ns            1               0               0               1               1               \n// 65ns            1               0               1               0               1               \n// 70ns            1               0               1               1               0               \n// 75ns            1               1               0               0               1               \n// 80ns            1               1               0               1               0               \n// 85ns            1               1               1               0               0               \n// 90ns            1               1               1               1               1       ", "header": "module top_module (\n\tinput a, \n\tinput b, \n\tinput c, \n\tinput d,\n\toutput q\n);\n", "module_code": "module top_module (\n\tinput a, \n\tinput b, \n\tinput c, \n\tinput d,\n\toutput q\n);\n\n\tassign q = ~a^b^c^d;\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput a, \n\tinput b, \n\tinput c, \n\tinput d,\n\toutput q\n);\n\n\tassign q = ~a^b^c^d;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic a,b,c,d,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\t{a,b,c,d} <= 0;\n\t\t@(negedge clk) wavedrom_start(\"Unknown circuit\");\n\t\t\t@(posedge clk) {a,b,c,d} <= 0;\n\t\t\trepeat(18) @(posedge clk, negedge clk) {a,b,c,d} <= {a,b,c,d} + 1;\n\t\twavedrom_stop();\n\t\t\n\t\trepeat(100) @(posedge clk, negedge clk)\n\t\t\t{a,b,c,d} <= $urandom;\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_q;\n\t\tint errortime_q;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic a;\n\tlogic b;\n\tlogic c;\n\tlogic d;\n\tlogic q_ref;\n\tlogic q_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,a,b,c,d,q_ref,q_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d );\n\treference_module good1 (\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d,\n\t\t.q(q_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d,\n\t\t.q(q_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"q\", stats1.errors_q, stats1.errortime_q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"q\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (q_ref !== ( q_ref ^ q_dut ^ q_ref ))\n\t\tbegin if (stats1.errors_q == 0) stats1.errortime_q = $time;\n\t\t\tstats1.errors_q = stats1.errors_q+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "andgate", "task_number": 136, "description": "Create a module that implements an AND gate.", "header": "module top_module(\n\tinput a, \n\tinput b,\n\toutput out\n);\n", "module_code": "module top_module(\n\tinput a, \n\tinput b,\n\toutput out\n);\n\t\n\tassign out = a & b;\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput a, \n\tinput b,\n\toutput out\n);\n\t\n\tassign out = a & b;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg a, b,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\tint count; count = 0;\n\t\t{a,b} <= 1'b0;\n\t\twavedrom_start(\"AND gate\");\n\t\trepeat(10) @(posedge clk)\n\t\t\t{a,b} <= count++;\t\t\n\t\twavedrom_stop();\n\t\t\n\t\trepeat(200) @(posedge clk, negedge clk)\n\t\t\t{b,a} <= $random;\n\t\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic a;\n\tlogic b;\n\tlogic out_ref;\n\tlogic out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,a,b,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.a,\n\t\t.b );\n\treference_module good1 (\n\t\t.a,\n\t\t.b,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.a,\n\t\t.b,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "fsm1s", "task_number": 137, "description": "This is a Moore state machine with two states, one input, and one output. Implement this state machine in Verilog. The reset state is B and reset is active-high synchronous.\n\n// B (out=1) --in=0--> A\n// B (out=1) --in=1--> B\n// A (out=0) --in=0--> B\n// A (out=0) --in=1--> A", "header": "module top_module (\n\tinput clk,\n\tinput in,\n\tinput reset,\n\toutput out\n);\n", "module_code": "module top_module (\n\tinput clk,\n\tinput in,\n\tinput reset,\n\toutput out\n);\n\tparameter A=0, B=1;\n\treg state;\n\treg next;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tA: next = in ? A : B;\n\t\t\tB: next = in ? B : A;\n\t\tendcase\n    end\n    \n    always @(posedge clk) begin\n\t\tif (reset) state <= B;\n        else state <= next;\n\tend\n\t\t\n\tassign out = (state==B);\n\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput in,\n\tinput reset,\n\toutput out\n);\n\tparameter A=0, B=1;\n\treg state;\n\treg next;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tA: next = in ? A : B;\n\t\t\tB: next = in ? B : A;\n\t\tendcase\n    end\n    \n    always @(posedge clk) begin\n\t\tif (reset) state <= B;\n        else state <= next;\n\tend\n\t\t\n\tassign out = (state==B);\n\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic in,\n\toutput logic reset,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\tinput tb_match\n);\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\tinitial begin\n\t\treset <= 1;\n\t\tin <= 0;\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0; in <= 0;\n\t\t@(posedge clk) in <= 1;\n\t\twavedrom_start();\n\t\t\treset_test(0);\n\t\t\t@(posedge clk) in <= 0;\n\t\t\t@(posedge clk) in <= 0;\n\t\t\t@(posedge clk) in <= 0;\n\t\t\t@(posedge clk) in <= 1;\n\t\t\t@(posedge clk) in <= 1;\n\t\t@(negedge clk);\n\t\twavedrom_stop();\n\t\trepeat(200) @(posedge clk, negedge clk) begin\n\t\t\tin <= $random;\n\t\t\treset <= !($random & 7);\n\t\tend\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic in;\n\tlogic reset;\n\tlogic out_ref;\n\tlogic out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,in,reset,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in,\n\t\t.reset );\n\treference_module good1 (\n\t\t.clk,\n\t\t.in,\n\t\t.reset,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.in,\n\t\t.reset,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "fadd", "task_number": 138, "description": "Create a full adder. A full adder adds three bits (including carry-in) and produces a sum and carry-out.", "header": "module top_module (\n\tinput a,\n\tinput b,\n\tinput cin,\n\toutput cout,\n\toutput sum\n);\n", "module_code": "module top_module (\n\tinput a,\n\tinput b,\n\tinput cin,\n\toutput cout,\n\toutput sum\n);\n\n\tassign {cout, sum} = a+b+cin;\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput a,\n\tinput b,\n\tinput cin,\n\toutput cout,\n\toutput sum\n);\n\n\tassign {cout, sum} = a+b+cin;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic a,b,cin,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\twavedrom_start();\n\t\t\t@(posedge clk) {a,b,cin} <= 3'b000;\n\t\t\t@(posedge clk) {a,b,cin} <= 3'b010;\n\t\t\t@(posedge clk) {a,b,cin} <= 3'b100;\n\t\t\t@(posedge clk) {a,b,cin} <= 3'b110;\n\t\t\t@(posedge clk) {a,b,cin} <= 3'b000;\n\t\t\t@(posedge clk) {a,b,cin} <= 3'b001;\n\t\t\t@(posedge clk) {a,b,cin} <= 3'b011;\t\t\t\n\t\t@(negedge clk) wavedrom_stop();\n\t\n\t\trepeat(200) @(posedge clk, negedge clk)\n\t\t\t{a,b,cin} <= $random;\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_cout;\n\t\tint errortime_cout;\n\t\tint errors_sum;\n\t\tint errortime_sum;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic a;\n\tlogic b;\n\tlogic cin;\n\tlogic cout_ref;\n\tlogic cout_dut;\n\tlogic sum_ref;\n\tlogic sum_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,a,b,cin,cout_ref,cout_dut,sum_ref,sum_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.a,\n\t\t.b,\n\t\t.cin );\n\treference_module good1 (\n\t\t.a,\n\t\t.b,\n\t\t.cin,\n\t\t.cout(cout_ref),\n\t\t.sum(sum_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.a,\n\t\t.b,\n\t\t.cin,\n\t\t.cout(cout_dut),\n\t\t.sum(sum_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_cout) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"cout\", stats1.errors_cout, stats1.errortime_cout);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"cout\");\n\t\tif (stats1.errors_sum) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"sum\", stats1.errors_sum, stats1.errortime_sum);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"sum\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { cout_ref, sum_ref } === ( { cout_ref, sum_ref } ^ { cout_dut, sum_dut } ^ { cout_ref, sum_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (cout_ref !== ( cout_ref ^ cout_dut ^ cout_ref ))\n\t\tbegin if (stats1.errors_cout == 0) stats1.errortime_cout = $time;\n\t\t\tstats1.errors_cout = stats1.errors_cout+1'b1; end\n\t\tif (sum_ref !== ( sum_ref ^ sum_dut ^ sum_ref ))\n\t\tbegin if (stats1.errors_sum == 0) stats1.errortime_sum = $time;\n\t\t\tstats1.errors_sum = stats1.errors_sum+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "m2014_q4g", "task_number": 139, "description": "Implement in Verilog the following circuit: A two-input XNOR (connected to 'in1' and 'in2) has an output connected to the input of a two-input XOR. The second input of the XOR is 'in3.' The output of the XOR is 'out'.", "header": "module top_module (\n\tinput in1,\n\tinput in2,\n\tinput in3,\n\toutput logic out\n);\n", "module_code": "module top_module (\n\tinput in1,\n\tinput in2,\n\tinput in3,\n\toutput logic out\n);\n\n\tassign out = (~(in1 ^ in2)) ^ in3;\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput in1,\n\tinput in2,\n\tinput in3,\n\toutput logic out\n);\n\n\tassign out = (~(in1 ^ in2)) ^ in3;\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic in1, in2, in3\n);\n\n\tinitial begin\n\t\trepeat(100) @(posedge clk, negedge clk) begin\n\t\t\t{in1, in2, in3} <= $random;\n\t\tend\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic in1;\n\tlogic in2;\n\tlogic in3;\n\tlogic out_ref;\n\tlogic out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,in1,in2,in3,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in1,\n\t\t.in2,\n\t\t.in3 );\n\treference_module good1 (\n\t\t.in1,\n\t\t.in2,\n\t\t.in3,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.in1,\n\t\t.in2,\n\t\t.in3,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "ece241_2014_q3", "task_number": 140, "description": "For the following Karnaugh map, give the circuit implementation using one 4-to-1 multiplexer and as many 2-to-1 multiplexers as required, but using as few as possible. You are not allowed to use any other logic gate and you must use _a_ and _b_ as the multiplexer selector inputs, as shown on the 4-to-1 multiplexer below.\n\n//       ab\n// cd   00 01 11 10\n//  00 | 0 | 0 | 0 | 1 |\n//  01 | 1 | 0 | 0 | 0 |\n//  11 | 1 | 0 | 1 | 1 |\n//  10 | 1 | 0 | 0 | 1 |\n\n// Consider a block diagram with inputs 'c' and 'd' going into a module called \"top_module\". This \"top_module\" has four outputs, mux_in[3:0], that connect to a four input mux. The mux takes as input {a,b} and ab = 00 is connected to mux_in[0], ab=01 is connected to mux_in[1], and so in. You are implementing in Verilog just the portion labelled \"top_module\", such that the entire circuit (including the 4-to-1 mux) implements the K-map.\n", "header": "module top_module (\n\tinput c,\n\tinput d,\n\toutput [3:0] mux_in\n);\n", "module_code": "module top_module (\n\tinput c,\n\tinput d,\n\toutput [3:0] mux_in\n);\n\t\n\tassign mux_in[0] = c | d;\n\tassign mux_in[1] = 0;\n\tassign mux_in[2] = ~d;\t\n\tassign mux_in[3] = c&d;\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput c,\n\tinput d,\n\toutput [3:0] mux_in\n);\n\t\n\tassign mux_in[0] = c | d;\n\tassign mux_in[1] = 0;\n\tassign mux_in[2] = ~d;\t\n\tassign mux_in[3] = c&d;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic c, d,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\t{c, d} <= 0;\n\t\t@(negedge clk) wavedrom_start();\n\t\t\t@(posedge clk) {c, d} <= 2'h0;\n\t\t\t@(posedge clk) {c, d} <= 2'h1;\n\t\t\t@(posedge clk) {c, d} <= 2'h2;\n\t\t\t@(posedge clk) {c, d} <= 2'h3;\n\t\t@(negedge clk) wavedrom_stop();\n\t\trepeat(50) @(posedge clk, negedge clk)\n\t\t\t{c,d} <= $random;\n\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_mux_in;\n\t\tint errortime_mux_in;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic c;\n\tlogic d;\n\tlogic [3:0] mux_in_ref;\n\tlogic [3:0] mux_in_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,c,d,mux_in_ref,mux_in_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.c,\n\t\t.d );\n\treference_module good1 (\n\t\t.c,\n\t\t.d,\n\t\t.mux_in(mux_in_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.c,\n\t\t.d,\n\t\t.mux_in(mux_in_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_mux_in) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"mux_in\", stats1.errors_mux_in, stats1.errortime_mux_in);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"mux_in\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { mux_in_ref } === ( { mux_in_ref } ^ { mux_in_dut } ^ { mux_in_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (mux_in_ref !== ( mux_in_ref ^ mux_in_dut ^ mux_in_ref ))\n\t\tbegin if (stats1.errors_mux_in == 0) stats1.errortime_mux_in = $time;\n\t\t\tstats1.errors_mux_in = stats1.errors_mux_in+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "ece241_2014_q5b", "task_number": 141, "description": "The following diagram is a Mealy machine implementation of the 2's complementer. Implement in Verilog using one-hot encoding. Resets into state A and reset is asynchronous active-high.\n\n// A --x=0 (z=0)--> A\n// A --x=1 (z=1)--> B\n// B --x=0 (z=1)--> B\n// B --x=1 (z=0)--> B", "header": "module top_module (\n\tinput clk,\n\tinput areset,\n\tinput x,\n\toutput z\n);\n", "module_code": "module top_module (\n\tinput clk,\n\tinput areset,\n\tinput x,\n\toutput z\n);\n\n\tparameter A=0,B=1;\n\treg state;\n\talways @(posedge clk, posedge areset) begin\n\t\tif (areset)\n\t\t\tstate <= A;\n\t\telse begin\n\t\t\tcase (state)\n\t\t\t\tA: state <= x ? B : A;\n\t\t\t\tB: state <= B;\n\t\t\tendcase\n\t\tend\n\tend\n\t\n\tassign z = (state == A && x==1) | (state == B && x==0);\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput areset,\n\tinput x,\n\toutput z\n);\n\n\tparameter A=0,B=1;\n\treg state;\n\talways @(posedge clk, posedge areset) begin\n\t\tif (areset)\n\t\t\tstate <= A;\n\t\telse begin\n\t\t\tcase (state)\n\t\t\t\tA: state <= x ? B : A;\n\t\t\t\tB: state <= B;\n\t\t\tendcase\n\t\tend\n\tend\n\t\n\tassign z = (state == A && x==1) | (state == B && x==0);\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic x,\n\toutput logic areset,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\tinput tb_match\n);\n\treg reset;\n\tassign areset = reset;\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\n\tinitial begin\n\t\tx <= 0;\n\t\treset <= 1;\n\t\t@(posedge clk) reset <= 0; x <= 1;\n\t\t@(posedge clk) x <= 0;\n\t\treset_test(1);\n\t\t\n\t\t@(negedge clk) wavedrom_start();\n\t\t\t@(posedge clk) {reset,x} <= 2'h2;\n\t\t\t@(posedge clk) {reset,x} <= 2'h0;\n\t\t\t@(posedge clk) {reset,x} <= 2'h0;\n\t\t\t@(posedge clk) {reset,x} <= 2'h1;\n\t\t\t@(posedge clk) {reset,x} <= 2'h0;\n\t\t\t@(posedge clk) {reset,x} <= 2'h1;\n\t\t\t@(posedge clk) {reset,x} <= 2'h1;\n\t\t\t@(posedge clk) {reset,x} <= 2'h0;\n\t\t\t@(posedge clk) {reset,x} <= 2'h0;\n\t\t@(negedge clk) wavedrom_stop();\n\t\trepeat(400) @(posedge clk, negedge clk)\n\t\t\t{reset,x} <= {($random&31) == 0, ($random&1)==0 };\n\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_z;\n\t\tint errortime_z;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic areset;\n\tlogic x;\n\tlogic z_ref;\n\tlogic z_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,areset,x,z_ref,z_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.areset,\n\t\t.x );\n\treference_module good1 (\n\t\t.clk,\n\t\t.areset,\n\t\t.x,\n\t\t.z(z_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.areset,\n\t\t.x,\n\t\t.z(z_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_z) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"z\", stats1.errors_z, stats1.errortime_z);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"z\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { z_ref } === ( { z_ref } ^ { z_dut } ^ { z_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (z_ref !== ( z_ref ^ z_dut ^ z_ref ))\n\t\tbegin if (stats1.errors_z == 0) stats1.errortime_z = $time;\n\t\t\tstats1.errors_z = stats1.errors_z+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "circuit10", "task_number": 142, "description": "This is a sequential circuit. The circuit consists of combinational logic and one bit of memory (i.e., one flip-flop). The output of the flip-flop has been made observable through the output state.\n\n// Read the simulation waveforms to determine what the circuit does, then implement it.\n\n// time            clk             a               b               state           q               \n// 0ns             0               1               x               x               x               \n// 5ns             1               1               x               x               x               \n// 10ns            0               0               0               x               x               \n// 15ns            1               0               0               0               0               \n// 20ns            0               0               0               0               0               \n// 25ns            1               0               0               0               0               \n// 30ns            0               0               0               0               0               \n// 35ns            1               0               0               0               0               \n// 40ns            0               0               0               0               0               \n// 45ns            1               0               1               0               1               \n// 50ns            0               0               1               0               1               \n// 55ns            1               1               0               0               1               \n// 60ns            0               1               0               0               1               \n// 65ns            1               1               1               0               0               \n// 70ns            0               1               1               0               0               \n// 75ns            1               0               0               1               1               \n// 80ns            0               0               0               1               1               \n// 85ns            1               1               1               0               0               \n// 90ns            0               1               1               0               0               \n// 95ns            1               1               1               1               1               \n// 100ns           0               1               1               1               1               \n// 105ns           1               1               1               1               1               \n// 110ns           0               1               1               1               1               \n// 115ns           1               1               0               1               0               \n// 120ns           0               1               0               1               0               \n// 125ns           1               0               1               1               0               \n// 130ns           0               0               1               1               0               \n// 135ns           1               0               0               1               1               \n// 140ns           0               0               0               1               1               \n// 145ns           1               0               0               0               0               \n// 150ns           0               0               0               0               0               \n// 155ns           1               0               0               0               0               \n// 160ns           0               0               0               0               0               \n// 165ns           1               0               0               0               0               \n// 170ns           0               0               0               0               0               \n// 175ns           1               0               0               0               0               \n// 180ns           0               0               0               0               0               \n// 185ns           1               0               0               0               0               \n// 190ns           0               0               0               0               0        ", "header": "module top_module (\n\tinput clk,\n\tinput a,\n\tinput b,\n\toutput q,\n\toutput state\n);\n", "module_code": "module top_module (\n\tinput clk,\n\tinput a,\n\tinput b,\n\toutput q,\n\toutput state\n);\n\n\treg c;\n\talways @(posedge clk)\n\t\tc <= a&b | a&c | b&c;\n\t\n\tassign q = a^b^c;\n\tassign state = c;\n\t\t\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput a,\n\tinput b,\n\toutput q,\n\toutput state\n);\n\n\treg c;\n\talways @(posedge clk)\n\t\tc <= a&b | a&c | b&c;\n\t\n\tassign q = a^b^c;\n\tassign state = c;\n\t\t\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic a,\n\toutput logic b,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\ta <= 1;\n\t\t@(negedge clk) {a,b} <= 0;\n\t\t@(negedge clk) wavedrom_start(\"Unknown circuit\");\n\t\t\trepeat(3) @(posedge clk);\n\t\t\t{a,b} <= 1;\n\t\t\t@(posedge clk) {a,b} <= 2;\n\t\t\t@(posedge clk) {a,b} <= 3;\n\t\t\t@(posedge clk) {a,b} <= 0;\n\t\t\t@(posedge clk) {a,b} <= 3;\n\t\t\t@(posedge clk) {a,b} <= 3;\n\t\t\t@(posedge clk) {a,b} <= 3;\n\t\t\t@(posedge clk) {a,b} <= 2;\n\t\t\t@(posedge clk) {a,b} <= 1;\n\t\t\t@(posedge clk) {a,b} <= 0;\n\t\t\t@(posedge clk) {a,b} <= 0;\n\t\t\t@(posedge clk) {a,b} <= 0;\n\t\t\t@(negedge clk);\n\t\twavedrom_stop();\n\n\t\trepeat(200) @(posedge clk, negedge clk)\n\t\t\ta <= &((5)'($urandom));\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_q;\n\t\tint errortime_q;\n\t\tint errors_state;\n\t\tint errortime_state;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic a;\n\tlogic b;\n\tlogic q_ref;\n\tlogic q_dut;\n\tlogic state_ref;\n\tlogic state_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,a,b,q_ref,q_dut,state_ref,state_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.a,\n\t\t.b );\n\treference_module good1 (\n\t\t.clk,\n\t\t.a,\n\t\t.b,\n\t\t.q(q_ref),\n\t\t.state(state_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.a,\n\t\t.b,\n\t\t.q(q_dut),\n\t\t.state(state_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"q\", stats1.errors_q, stats1.errortime_q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"q\");\n\t\tif (stats1.errors_state) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"state\", stats1.errors_state, stats1.errortime_state);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"state\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { q_ref, state_ref } === ( { q_ref, state_ref } ^ { q_dut, state_dut } ^ { q_ref, state_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (q_ref !== ( q_ref ^ q_dut ^ q_ref ))\n\t\tbegin if (stats1.errors_q == 0) stats1.errortime_q = $time;\n\t\t\tstats1.errors_q = stats1.errors_q+1'b1; end\n\t\tif (state_ref !== ( state_ref ^ state_dut ^ state_ref ))\n\t\tbegin if (stats1.errors_state == 0) stats1.errortime_state = $time;\n\t\t\tstats1.errors_state = stats1.errors_state+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "2012_q1g", "task_number": 143, "description": "Consider the function f shown in the Karnaugh map below. Implement this function.\n//        x[1]x[2]\n// x[3]x[4]   00 01 11 10\n//  00 | 1 | 0 | 0 | 1 |\n//  01 | 0 | 0 | 0 | 0 |\n//  11 | 1 | 1 | 1 | 0 |\n//  10 | 1 | 1 | 0 | 1 |", "header": "module top_module (\n\tinput [4:1] x,\n\toutput logic f\n);\n", "module_code": "module top_module (\n\tinput [4:1] x,\n\toutput logic f\n);\n\n\talways_comb begin\n\t\tcase (x) \n\t\t\t4'h0: f = 1;\n\t\t\t4'h1: f = 1;\n\t\t\t4'h2: f = 0;\n\t\t\t4'h3: f = 0;\n\t\t\t4'h4: f = 1;\n\t\t\t4'h5: f = 1;\n\t\t\t4'h6: f = 1;\n\t\t\t4'h7: f = 0;\n\t\t\t4'h8: f = 0;\n\t\t\t4'h9: f = 0;\n\t\t\t4'ha: f = 0;\n\t\t\t4'hb: f = 0;\n\t\t\t4'hc: f = 1;\n\t\t\t4'hd: f = 0;\n\t\t\t4'he: f = 1;\n\t\t\t4'hf: f = 1;\n\t\tendcase\n\tend\n\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [4:1] x,\n\toutput logic f\n);\n\n\talways_comb begin\n\t\tcase (x) \n\t\t\t4'h0: f = 1;\n\t\t\t4'h1: f = 1;\n\t\t\t4'h2: f = 0;\n\t\t\t4'h3: f = 0;\n\t\t\t4'h4: f = 1;\n\t\t\t4'h5: f = 1;\n\t\t\t4'h6: f = 1;\n\t\t\t4'h7: f = 0;\n\t\t\t4'h8: f = 0;\n\t\t\t4'h9: f = 0;\n\t\t\t4'ha: f = 0;\n\t\t\t4'hb: f = 0;\n\t\t\t4'hc: f = 1;\n\t\t\t4'hd: f = 0;\n\t\t\t4'he: f = 1;\n\t\t\t4'hf: f = 1;\n\t\tendcase\n\tend\n\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic [4:1] x\n);\n\n\tinitial begin\n\t\trepeat(100) @(posedge clk, negedge clk) begin\n\t\t\tx <= $random;\n\t\tend\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_f;\n\t\tint errortime_f;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [4:1] x;\n\tlogic f_ref;\n\tlogic f_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,x,f_ref,f_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.x );\n\treference_module good1 (\n\t\t.x,\n\t\t.f(f_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.x,\n\t\t.f(f_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_f) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"f\", stats1.errors_f, stats1.errortime_f);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"f\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { f_ref } === ( { f_ref } ^ { f_dut } ^ { f_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (f_ref !== ( f_ref ^ f_dut ^ f_ref ))\n\t\tbegin if (stats1.errors_f == 0) stats1.errortime_f = $time;\n\t\t\tstats1.errors_f = stats1.errors_f+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "fsm_hdlc", "task_number": 144, "description": "Synchronous HDLC framing involves decoding a continuous bit stream of data to look for bit patterns that indicate the beginning and end of frames (packets). Seeing exactly 6 consecutive 1s (i.e., 01111110) is a \"flag\" that indicate frame boundaries. To avoid the data stream from accidentally containing \"flags\", the sender inserts a zero after every 5 consecutive 1s which the receiver must detect and discard. We also need to signal an error if there are 7 or more consecutive 1s. Create a Moore-type finite state machine to recognize these three sequences:\n\n// (1) 0111110: Signal a bit needs to be discarded (disc).\n// (2) 01111110: Flag the beginning/end of a frame (flag).\n// (3) 01111111...: Error (7 or more 1s) (err).\n\n// When the FSM is reset, it should be in a state that behaves as though the previous input were 0. The reset signal is active high synchronous. The output signals should be asserted for a complete cycle beginning on the clock cycle after the condition occurs.", "header": "module top_module (\n\tinput clk,\n\tinput reset,\n\tinput in,\n\toutput disc,\n\toutput flag,\n\toutput err);\n", "module_code": "module top_module (\n\tinput clk,\n\tinput reset,\n\tinput in,\n\toutput disc,\n\toutput flag,\n\toutput err);\n\t\n\tparameter [3:0] S0=0, S1=1, S2=2, S3=3, S4=4, S5=5, S6=6, SERR=7, SDISC=8, SFLAG=9;\n\treg [3:0] state, next;\n\n\tassign disc = state == SDISC;\n\tassign flag = state == SFLAG;\n\tassign err = state == SERR;\n\t\n\talways @(posedge clk) begin\n\t\tcase (state)\n\t\t\tS0: state <= in ? S1 : S0;\n\t\t\tS1: state <= in ? S2 : S0;\n\t\t\tS2: state <= in ? S3 : S0;\n\t\t\tS3: state <= in ? S4 : S0;\n\t\t\tS4: state <= in ? S5 : S0;\n\t\t\tS5: state <= in ? S6 : SDISC;\n\t\t\tS6: state <= in ? SERR : SFLAG;\n\t\t\tSERR: state <= in ? SERR : S0;\n\t\t\tSFLAG: state <= in ? S1 : S0;\n\t\t\tSDISC: state <= in ? S1 : S0;\n\t\t\tdefault: state <= 'x;\n\t\tendcase\n\t\t\n\t\tif (reset) state <= S0;\n\tend\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput reset,\n\tinput in,\n\toutput disc,\n\toutput flag,\n\toutput err);\n\t\n\tparameter [3:0] S0=0, S1=1, S2=2, S3=3, S4=4, S5=5, S6=6, SERR=7, SDISC=8, SFLAG=9;\n\treg [3:0] state, next;\n\n\tassign disc = state == SDISC;\n\tassign flag = state == SFLAG;\n\tassign err = state == SERR;\n\t\n\talways @(posedge clk) begin\n\t\tcase (state)\n\t\t\tS0: state <= in ? S1 : S0;\n\t\t\tS1: state <= in ? S2 : S0;\n\t\t\tS2: state <= in ? S3 : S0;\n\t\t\tS3: state <= in ? S4 : S0;\n\t\t\tS4: state <= in ? S5 : S0;\n\t\t\tS5: state <= in ? S6 : SDISC;\n\t\t\tS6: state <= in ? SERR : SFLAG;\n\t\t\tSERR: state <= in ? SERR : S0;\n\t\t\tSFLAG: state <= in ? S1 : S0;\n\t\t\tSDISC: state <= in ? S1 : S0;\n\t\t\tdefault: state <= 'x;\n\t\tendcase\n\t\t\n\t\tif (reset) state <= S0;\n\tend\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic reset, in\n);\n\n\t\n\tinitial begin\n\t\treset <= 1;\n\t\tin <= 0;\n\t\t@(posedge clk);\n\t\trepeat(800) @(posedge clk, negedge clk) begin\n\t\t\treset <= !($random & 31);\n\t\t\tin <= |($random&7);\n\t\tend\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_disc;\n\t\tint errortime_disc;\n\t\tint errors_flag;\n\t\tint errortime_flag;\n\t\tint errors_err;\n\t\tint errortime_err;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic reset;\n\tlogic in;\n\tlogic disc_ref;\n\tlogic disc_dut;\n\tlogic flag_ref;\n\tlogic flag_dut;\n\tlogic err_ref;\n\tlogic err_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,in,disc_ref,disc_dut,flag_ref,flag_dut,err_ref,err_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.reset,\n\t\t.in );\n\treference_module good1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.in,\n\t\t.disc(disc_ref),\n\t\t.flag(flag_ref),\n\t\t.err(err_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.in,\n\t\t.disc(disc_dut),\n\t\t.flag(flag_dut),\n\t\t.err(err_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_disc) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"disc\", stats1.errors_disc, stats1.errortime_disc);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"disc\");\n\t\tif (stats1.errors_flag) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"flag\", stats1.errors_flag, stats1.errortime_flag);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"flag\");\n\t\tif (stats1.errors_err) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"err\", stats1.errors_err, stats1.errortime_err);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"err\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { disc_ref, flag_ref, err_ref } === ( { disc_ref, flag_ref, err_ref } ^ { disc_dut, flag_dut, err_dut } ^ { disc_ref, flag_ref, err_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (disc_ref !== ( disc_ref ^ disc_dut ^ disc_ref ))\n\t\tbegin if (stats1.errors_disc == 0) stats1.errortime_disc = $time;\n\t\t\tstats1.errors_disc = stats1.errors_disc+1'b1; end\n\t\tif (flag_ref !== ( flag_ref ^ flag_dut ^ flag_ref ))\n\t\tbegin if (stats1.errors_flag == 0) stats1.errortime_flag = $time;\n\t\t\tstats1.errors_flag = stats1.errors_flag+1'b1; end\n\t\tif (err_ref !== ( err_ref ^ err_dut ^ err_ref ))\n\t\tbegin if (stats1.errors_err == 0) stats1.errortime_err = $time;\n\t\t\tstats1.errors_err = stats1.errors_err+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "review2015_fancytimer", "task_number": 145, "description": "We want to create a timer with one input that:\n\n// (1) is started when a particular input pattern (1101) is detected,\n// (2) shifts in 4 more bits to determine the duration to delay,\n// (3) waits for the counters to finish counting, and\n// (4) notifies the user and waits for the user to acknowledge the timer.\n\n// The serial data is available on the data input pin. When the pattern 1101 is received, the circuit must then shift in the next 4 bits, most-significant-bit first. These 4 bits determine the duration of the timer delay, referred to as delay[3:0]. After that, the state machine asserts its counting output to indicate it is counting. Once the 1101 and delay[3:0] have been read, the circuit no longer looks at the data input until it resumes searching after everything else is done.\n\n// The state machine must count for exactly (delay[3:0] + 1) * 1000 clock cycles. e.g., delay=0 means count 1000 cycles, and delay=5 means count 6000 cycles. Also output the current remaining time. This should be equal to delay for 1000 cycles, then delay-1 for 1000 cycles, and so on until it is 0 for 1000 cycles. \n\n// When the circuit isn't counting, the count[3:0] output is don't-care (whatever value is convenient for you to implement). At that point, the circuit must assert done to notify the user the timer has timed out, and waits until input ack is 1 before being reset to look for the next occurrence of the start sequence (1101).\n\n// The circuit should reset into a state where it begins searching for the input sequence 1101. The reset signal is active high synchronous. \n", "header": "module top_module(\n\tinput wire clk,\n\tinput wire reset,\n\tinput wire data,\n    output wire [3:0] count,\n    output reg counting,\n    output reg done,\n    input wire ack );\n", "module_code": "module top_module(\n\tinput wire clk,\n\tinput wire reset,\n\tinput wire data,\n    output wire [3:0] count,\n    output reg counting,\n    output reg done,\n    input wire ack );\n\n\ttypedef enum logic[3:0] {\n\t\tS, S1, S11, S110, B0, B1, B2, B3, Count, Wait\n\t} States;\n\t\n\tStates state, next;\n\t\n\treg shift_ena;\n\treg [9:0] fcount;\n\treg [3:0] scount;\n\twire done_counting = (scount == 0) && (fcount == 999);\n\t\n\talways_comb begin\n\t\tcase (state)\n\t\t\tS: next = States'(data ? S1: S);\n\t\t\tS1: next = States'(data ? S11: S);\n\t\t\tS11: next = States'(data ? S11 : S110);\n\t\t\tS110: next = States'(data ? B0 : S);\n\t\t\tB0: next = B1;\n\t\t\tB1: next = B2;\n\t\t\tB2: next = B3;\n\t\t\tB3: next = Count;\n\t\t\tCount: next = States'(done_counting ? Wait : Count);\n\t\t\tWait: next = States'(ack ? S : Wait);\n\t\t\tdefault: next = States'(4'bx);\n\t\tendcase\n\tend\n\t\n\talways @(posedge clk) begin\n\t\tif (reset) state <= S;\n\t\telse state <= next;\n\tend\n\t\t\n\talways_comb begin\n\t\tshift_ena = 0; counting = 0; done = 0;\n\t\tif (state == B0 || state == B1 || state == B2 || state == B3)\n\t\t\tshift_ena = 1;\n\t\tif (state == Count)\n\t\t\tcounting = 1;\n\t\tif (state == Wait)\n\t\t\tdone = 1;\n\n\t\tif (|state === 1'bx) begin\n\t\t\t{shift_ena, counting, done} = 'x;\n\t\tend\t\t\n\tend\n\t\n\t\n\t// Shift register\n\talways @(posedge clk) begin\n\t\tif (shift_ena)\n\t\t\tscount <= {scount[2:0], data};\n\t\telse if (counting && fcount == 999)\n\t\t\tscount <= scount - 1'b1;\n\tend\n\t\n\t// Fast counter\n\talways @(posedge clk)\n\t\tif (!counting)\n\t\t\tfcount <= 10'h0;\n\t\telse if (fcount == 999)\n\t\t\tfcount <= 10'h0;\n\t\telse\n\t\t\tfcount <= fcount + 1'b1;\n\t\n\tassign count = counting ? scount : 'x;\n\t\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\n`default_nettype none\nmodule reference_module(\n\tinput wire clk,\n\tinput wire reset,\n\tinput wire data,\n    output wire [3:0] count,\n    output reg counting,\n    output reg done,\n    input wire ack );\n\n\ttypedef enum logic[3:0] {\n\t\tS, S1, S11, S110, B0, B1, B2, B3, Count, Wait\n\t} States;\n\t\n\tStates state, next;\n\t\n\treg shift_ena;\n\treg [9:0] fcount;\n\treg [3:0] scount;\n\twire done_counting = (scount == 0) && (fcount == 999);\n\t\n\talways_comb begin\n\t\tcase (state)\n\t\t\tS: next = States'(data ? S1: S);\n\t\t\tS1: next = States'(data ? S11: S);\n\t\t\tS11: next = States'(data ? S11 : S110);\n\t\t\tS110: next = States'(data ? B0 : S);\n\t\t\tB0: next = B1;\n\t\t\tB1: next = B2;\n\t\t\tB2: next = B3;\n\t\t\tB3: next = Count;\n\t\t\tCount: next = States'(done_counting ? Wait : Count);\n\t\t\tWait: next = States'(ack ? S : Wait);\n\t\t\tdefault: next = States'(4'bx);\n\t\tendcase\n\tend\n\t\n\talways @(posedge clk) begin\n\t\tif (reset) state <= S;\n\t\telse state <= next;\n\tend\n\t\t\n\talways_comb begin\n\t\tshift_ena = 0; counting = 0; done = 0;\n\t\tif (state == B0 || state == B1 || state == B2 || state == B3)\n\t\t\tshift_ena = 1;\n\t\tif (state == Count)\n\t\t\tcounting = 1;\n\t\tif (state == Wait)\n\t\t\tdone = 1;\n\n\t\tif (|state === 1'bx) begin\n\t\t\t{shift_ena, counting, done} = 'x;\n\t\tend\t\t\n\tend\n\t\n\t\n\t// Shift register\n\talways @(posedge clk) begin\n\t\tif (shift_ena)\n\t\t\tscount <= {scount[2:0], data};\n\t\telse if (counting && fcount == 999)\n\t\t\tscount <= scount - 1'b1;\n\tend\n\t\n\t// Fast counter\n\talways @(posedge clk)\n\t\tif (!counting)\n\t\t\tfcount <= 10'h0;\n\t\telse if (fcount == 999)\n\t\t\tfcount <= 10'h0;\n\t\telse\n\t\t\tfcount <= fcount + 1'b1;\n\t\n\tassign count = counting ? scount : 'x;\n\t\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput wire clk,\n\toutput reg reset,\n\toutput reg data, \n\toutput reg ack,\n\tinput wire tb_match,\n\tinput wire counting_dut\n);\n\tbit failed = 0;\n\tint counting_cycles = 0;\n\t\n\talways @(posedge clk, negedge clk)\n\t\tif (!tb_match) \n\t\t\tfailed <= 1;\n\t\t\t\n\talways @(posedge clk)\n\t\tif (counting_dut)\n\t\t\tcounting_cycles++;\n\t\n\tinitial begin\n\n\t\t@(posedge clk);\n\t\tfailed <= 0;\n\t\treset <= 1;\n\t\tdata <= 0;\n\t\tack <= 1'bx;\n\t\t@(posedge clk) \n\t\t\tdata <= 1;\n\t\t\treset <= 0;\n\t\t@(posedge clk) data <= 0;\n\t\t@(posedge clk) data <= 0;\n\t\t@(posedge clk) data <= 1;\n\t\t@(posedge clk) data <= 1;\n\t\t@(posedge clk) data <= 0;\n\t\t@(posedge clk) data <= 1;\n\t\t@(posedge clk) data <= 0;\n\t\t@(posedge clk) data <= 0;\n\t\t@(posedge clk) data <= 0;\n\t\t@(posedge clk) data <= 1;\n\t\t@(posedge clk);\n\t\t\tdata <= 1'bx;\n\t\trepeat(2000) @(posedge clk);\n\t\t\tack <= 1'b0;\n\t\trepeat(3) @(posedge clk);\n\t\t\tack <= 1'b1;\n\t\t@(posedge clk);\n\t\t\tack <= 1'b0;\n\t\t\tdata <= 1'b1;\n\t\tif (counting_cycles != 2000)\n\t\t\t$display(\"Hint: The first test case should count for 2000 cycles. Your circuit counted %0d\", counting_cycles);\n\t\tcounting_cycles <= 0;\n\t\t@(posedge clk);\n\t\t\tack <= 1'bx;\n\t\t\tdata <= 1'b1;\n\t\t@(posedge clk);\n\t\t\tdata <= 1'b0;\n\t\t@(posedge clk);\n\t\t\tdata <= 1'b1;\n\t\t@(posedge clk);\tdata <= 1'b1;\n\t\t@(posedge clk);\tdata <= 1'b1;\n\t\t@(posedge clk);\tdata <= 1'b1;\n\t\t@(posedge clk);\tdata <= 1'b0;\n\t\trepeat(14800) @(posedge clk);\n\t\tack <= 1'b0;\n\t\trepeat(400) @(posedge clk);\n\n\t\tif (counting_cycles != 15000)\n\t\t\t$display(\"Hint: The second test case should count for 15000 cycles. Your circuit counted %0d\", counting_cycles);\n\t\tcounting_cycles <= 0;\n\n\t\tif (failed)\n\t\t\t$display(\"Hint: Your FSM didn't pass the sample timing diagram posted with the problem statement. Perhaps try debugging that?\");\n\t\t\n\t\t\n\t\n\t\trepeat(1000) @(posedge clk, negedge clk) begin\n\t\t\treset <= !($random & 8191);\n\t\t\tdata <= $random;\n\t\t\tack <= !($random & 31);\n\t\tend\n\t\trepeat(100000) @(posedge clk) begin\n\t\t\treset <= !($random & 8191);\n\t\t\tdata <= $random;\n\t\t\tack <= !($random & 31);\n\t\tend\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_count;\n\t\tint errortime_count;\n\t\tint errors_counting;\n\t\tint errortime_counting;\n\t\tint errors_done;\n\t\tint errortime_done;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic reset;\n\tlogic data;\n\tlogic ack;\n\tlogic [3:0] count_ref;\n\tlogic [3:0] count_dut;\n\tlogic counting_ref;\n\tlogic counting_dut;\n\tlogic done_ref;\n\tlogic done_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,data,ack,count_ref,count_dut,counting_ref,counting_dut,done_ref,done_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.reset,\n\t\t.data,\n\t\t.ack );\n\treference_module good1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.data,\n\t\t.ack,\n\t\t.count(count_ref),\n\t\t.counting(counting_ref),\n\t\t.done(done_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.data,\n\t\t.ack,\n\t\t.count(count_dut),\n\t\t.counting(counting_dut),\n\t\t.done(done_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_count) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"count\", stats1.errors_count, stats1.errortime_count);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"count\");\n\t\tif (stats1.errors_counting) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"counting\", stats1.errors_counting, stats1.errortime_counting);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"counting\");\n\t\tif (stats1.errors_done) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"done\", stats1.errors_done, stats1.errortime_done);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"done\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { count_ref, counting_ref, done_ref } === ( { count_ref, counting_ref, done_ref } ^ { count_dut, counting_dut, done_dut } ^ { count_ref, counting_ref, done_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (count_ref !== ( count_ref ^ count_dut ^ count_ref ))\n\t\tbegin if (stats1.errors_count == 0) stats1.errortime_count = $time;\n\t\t\tstats1.errors_count = stats1.errors_count+1'b1; end\n\t\tif (counting_ref !== ( counting_ref ^ counting_dut ^ counting_ref ))\n\t\tbegin if (stats1.errors_counting == 0) stats1.errortime_counting = $time;\n\t\t\tstats1.errors_counting = stats1.errors_counting+1'b1; end\n\t\tif (done_ref !== ( done_ref ^ done_dut ^ done_ref ))\n\t\tbegin if (stats1.errors_done == 0) stats1.errortime_done = $time;\n\t\t\tstats1.errors_done = stats1.errors_done+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "ece241_2013_q4", "task_number": 146, "description": "A large reservior of water serves several users. In order to keep the level of water succificently high, three sensors are placed vertically at 5-inch intervals. When the water level is above the highest sensor s[3], the input flow rate should be zero. When the level is below the lowest sensor s[1], the flow rate should be at maximum (both Nominal flow valve and Supplemental flow valve opened). The flow rate when the level is between the upper and lower sensors is determined by two factors: the water level and the level previous to the last sensor change. Each water level has a nominal flow rate associated with it as show in the table below. If the sensor change indicates that the previous level was lower than the current level, the flow rate should be increased by opening the Supplemental flow valve (controlled by dfr). \n// Water Level | Sensors Asserted | Nominal Flow Rate Inputs to be Asserted\n// Above s[3] | s[1], s[2], s[3] | None\n// Between s[3] and s[2] | s[1], s[2] | fr1\n// Between s[2] and s[1]  | s[1] | fr1, fr2\n// Below s[1] | None | fr1, fr2, fr3\n// Also include an active-high synchronous reset that resets the state machine to a state equivalent to if the water level had been low for a long time (no sensors asserted, and all four outputs asserted).", "header": "module top_module (\n\tinput clk,\n\tinput reset,\n\tinput [3:1] s,\n\toutput reg fr3,\n\toutput reg fr2,\n\toutput reg fr1,\n\toutput reg dfr\n);\n", "module_code": "module top_module (\n\tinput clk,\n\tinput reset,\n\tinput [3:1] s,\n\toutput reg fr3,\n\toutput reg fr2,\n\toutput reg fr1,\n\toutput reg dfr\n);\n\tparameter A2=0, B1=1, B2=2, C1=3, C2=4, D1=5;\n\treg [2:0] state, next;\n\t\n\talways @(posedge clk) begin\n\t\tif (reset) state <= A2;\n\t\telse state <= next;\n\tend\n\t\n\talways@(*) begin\n\t\tcase (state)\n\t\t\tA2: next = s[1] ? B1 : A2;\n\t\t\tB1: next = s[2] ? C1 : (s[1] ? B1 : A2);\n\t\t\tB2: next = s[2] ? C1 : (s[1] ? B2 : A2);\n\t\t\tC1: next = s[3] ? D1 : (s[2] ? C1 : B2);\n\t\t\tC2: next = s[3] ? D1 : (s[2] ? C2 : B2);\n\t\t\tD1: next = s[3] ? D1 : C2;\n\t\t\tdefault: next = 'x;\n\t\tendcase\n\tend\n\treg [3:0] fr;\n\tassign {fr3, fr2, fr1, dfr} = fr;\n\talways_comb begin\n\t\tcase (state)\n\t\t\tA2: fr = 4'b1111;\n\t\t\tB1: fr = 4'b0110;\n\t\t\tB2: fr = 4'b0111;\n\t\t\tC1: fr = 4'b0010;\n\t\t\tC2: fr = 4'b0011;\n\t\t\tD1: fr = 4'b0000;\n\t\t\tdefault: fr = 'x;\n\t\tendcase\n\tend\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput reset,\n\tinput [3:1] s,\n\toutput reg fr3,\n\toutput reg fr2,\n\toutput reg fr1,\n\toutput reg dfr\n);\n\tparameter A2=0, B1=1, B2=2, C1=3, C2=4, D1=5;\n\treg [2:0] state, next;\n\t\n\talways @(posedge clk) begin\n\t\tif (reset) state <= A2;\n\t\telse state <= next;\n\tend\n\t\n\talways@(*) begin\n\t\tcase (state)\n\t\t\tA2: next = s[1] ? B1 : A2;\n\t\t\tB1: next = s[2] ? C1 : (s[1] ? B1 : A2);\n\t\t\tB2: next = s[2] ? C1 : (s[1] ? B2 : A2);\n\t\t\tC1: next = s[3] ? D1 : (s[2] ? C1 : B2);\n\t\t\tC2: next = s[3] ? D1 : (s[2] ? C2 : B2);\n\t\t\tD1: next = s[3] ? D1 : C2;\n\t\t\tdefault: next = 'x;\n\t\tendcase\n\tend\n\treg [3:0] fr;\n\tassign {fr3, fr2, fr1, dfr} = fr;\n\talways_comb begin\n\t\tcase (state)\n\t\t\tA2: fr = 4'b1111;\n\t\t\tB1: fr = 4'b0110;\n\t\t\tB2: fr = 4'b0111;\n\t\t\tC1: fr = 4'b0010;\n\t\t\tC2: fr = 4'b0011;\n\t\t\tD1: fr = 4'b0000;\n\t\t\tdefault: fr = 'x;\n\t\tendcase\n\tend\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic reset,\n\toutput logic [3:1] s,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\tinput tb_match\n);\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\n\twire [3:0][2:0] val = { 3'h7, 3'h3, 3'h1, 3'h0 };\n\tinteger sval;\n\tinitial begin\n\t\treset <= 1;\n\t\ts <= 1;\n\t\treset_test();\n\t\t\n\t\t\n\t\t@(posedge clk) s <= 0;\n\t\t@(posedge clk) s <= 0;\n\t\t@(negedge clk) wavedrom_start(\"Water rises to highest level, then down to lowest level.\");\n\t\t\t@(posedge clk) s <= 0;\n\t\t\t@(posedge clk) s <= 1;\n\t\t\t@(posedge clk) s <= 3;\n\t\t\t@(posedge clk) s <= 7;\n\t\t\t@(posedge clk) s <= 7;\n\t\t\t@(posedge clk) s <= 3;\n\t\t\t@(posedge clk) s <= 3;\n\t\t\t@(posedge clk) s <= 1;\n\t\t\t@(posedge clk) s <= 1;\n\t\t\t@(posedge clk) s <= 0;\n\t\t\t@(posedge clk) s <= 0;\n\t\t@(negedge clk) wavedrom_stop();\n\t\t\n\t\tsval = 0;\n\t\trepeat(1000) begin\n\t\t\t@(posedge clk);\n\t\t\t\tsval = sval + (sval == 3 ? 0 : $random&1);\n\t\t\t\ts <= val[sval];\n\t\t\t@(negedge clk);\n\t\t\t\tsval = sval - (sval == 0 ? 0 : $random&1);\n\t\t\t\ts <= val[sval];\n\t\tend\n\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_fr3;\n\t\tint errortime_fr3;\n\t\tint errors_fr2;\n\t\tint errortime_fr2;\n\t\tint errors_fr1;\n\t\tint errortime_fr1;\n\t\tint errors_dfr;\n\t\tint errortime_dfr;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic reset;\n\tlogic [3:1] s;\n\tlogic fr3_ref;\n\tlogic fr3_dut;\n\tlogic fr2_ref;\n\tlogic fr2_dut;\n\tlogic fr1_ref;\n\tlogic fr1_dut;\n\tlogic dfr_ref;\n\tlogic dfr_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,s,fr3_ref,fr3_dut,fr2_ref,fr2_dut,fr1_ref,fr1_dut,dfr_ref,dfr_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.reset,\n\t\t.s );\n\treference_module good1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.s,\n\t\t.fr3(fr3_ref),\n\t\t.fr2(fr2_ref),\n\t\t.fr1(fr1_ref),\n\t\t.dfr(dfr_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.s,\n\t\t.fr3(fr3_dut),\n\t\t.fr2(fr2_dut),\n\t\t.fr1(fr1_dut),\n\t\t.dfr(dfr_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_fr3) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"fr3\", stats1.errors_fr3, stats1.errortime_fr3);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"fr3\");\n\t\tif (stats1.errors_fr2) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"fr2\", stats1.errors_fr2, stats1.errortime_fr2);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"fr2\");\n\t\tif (stats1.errors_fr1) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"fr1\", stats1.errors_fr1, stats1.errortime_fr1);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"fr1\");\n\t\tif (stats1.errors_dfr) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"dfr\", stats1.errors_dfr, stats1.errortime_dfr);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"dfr\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { fr3_ref, fr2_ref, fr1_ref, dfr_ref } === ( { fr3_ref, fr2_ref, fr1_ref, dfr_ref } ^ { fr3_dut, fr2_dut, fr1_dut, dfr_dut } ^ { fr3_ref, fr2_ref, fr1_ref, dfr_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (fr3_ref !== ( fr3_ref ^ fr3_dut ^ fr3_ref ))\n\t\tbegin if (stats1.errors_fr3 == 0) stats1.errortime_fr3 = $time;\n\t\t\tstats1.errors_fr3 = stats1.errors_fr3+1'b1; end\n\t\tif (fr2_ref !== ( fr2_ref ^ fr2_dut ^ fr2_ref ))\n\t\tbegin if (stats1.errors_fr2 == 0) stats1.errortime_fr2 = $time;\n\t\t\tstats1.errors_fr2 = stats1.errors_fr2+1'b1; end\n\t\tif (fr1_ref !== ( fr1_ref ^ fr1_dut ^ fr1_ref ))\n\t\tbegin if (stats1.errors_fr1 == 0) stats1.errortime_fr1 = $time;\n\t\t\tstats1.errors_fr1 = stats1.errors_fr1+1'b1; end\n\t\tif (dfr_ref !== ( dfr_ref ^ dfr_dut ^ dfr_ref ))\n\t\tbegin if (stats1.errors_dfr == 0) stats1.errortime_dfr = $time;\n\t\t\tstats1.errors_dfr = stats1.errors_dfr+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "fsm_serial", "task_number": 147, "description": "In many (older) serial communications protocols, each data byte is sent along with a start bit and a stop bit, to help the receiver delimit bytes from the stream of bits. One common scheme is to use one start bit (0), 8 data bits, and 1 stop bit (1). The line is also at logic 1 when nothing is being transmitted (idle). Design a finite state machine that will identify when bytes have been correctly received when given a stream of bits. It needs to identify the start bit, wait for all 8 data bits, then verify that the stop bit was correct. If the stop bit does not appear when expected, the FSM must wait until it finds a stop bit before attempting to receive the next byte. Include a active-high synchronous reset. Note that the serial protocol sends the least significant bit first.", "header": "module top_module (\n\tinput clk,\n\tinput in,\n\tinput reset,\n\toutput done\n);\n", "module_code": "module top_module (\n\tinput clk,\n\tinput in,\n\tinput reset,\n\toutput done\n);\n\tparameter B0=0, B1=1, B2=2, B3=3, B4=4, B5=5, B6=6, B7=7, START=8, STOP=9, DONE=10, ERR=11;\n\treg [3:0] state;\n\treg [3:0] next;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tSTART: next = in ? START : B0;\t// start bit is 0\n\t\t\tB0: next = B1;\n\t\t\tB1: next = B2;\n\t\t\tB2: next = B3;\n\t\t\tB3: next = B4;\n\t\t\tB4: next = B5;\n\t\t\tB5: next = B6;\n\t\t\tB6: next = B7;\n\t\t\tB7: next = STOP;\n\t\t\tSTOP: next = in ? DONE : ERR;  // stop bit is 1. Idle state is 1.\n\t\t\tDONE: next = in ? START : B0;\n\t\t\tERR: next = in ? START : ERR;\n\t\tendcase\n    end\n    \n    always @(posedge clk) begin\n\t\tif (reset) state <= START;\n        else state <= next;\n\tend\n\t\t\n\tassign done = (state==DONE);\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput in,\n\tinput reset,\n\toutput done\n);\n\tparameter B0=0, B1=1, B2=2, B3=3, B4=4, B5=5, B6=6, B7=7, START=8, STOP=9, DONE=10, ERR=11;\n\treg [3:0] state;\n\treg [3:0] next;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tSTART: next = in ? START : B0;\t// start bit is 0\n\t\t\tB0: next = B1;\n\t\t\tB1: next = B2;\n\t\t\tB2: next = B3;\n\t\t\tB3: next = B4;\n\t\t\tB4: next = B5;\n\t\t\tB5: next = B6;\n\t\t\tB6: next = B7;\n\t\t\tB7: next = STOP;\n\t\t\tSTOP: next = in ? DONE : ERR;  // stop bit is 1. Idle state is 1.\n\t\t\tDONE: next = in ? START : B0;\n\t\t\tERR: next = in ? START : ERR;\n\t\tendcase\n    end\n    \n    always @(posedge clk) begin\n\t\tif (reset) state <= START;\n        else state <= next;\n\tend\n\t\t\n\tassign done = (state==DONE);\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic in,\n\toutput logic reset\n);\n\n\tinitial begin\n\t\treset <= 1;\n\t\tin <= 1;\n\t\t@(posedge clk);\n\t\treset <= 0;\n\t\tin <= 0;\n\t\trepeat(9) @(posedge clk);\n\t\tin <= 1;\n\t\t@(posedge clk);\n\t\tin <= 0;\n\t\trepeat(9) @(posedge clk);\n\t\tin <= 1;\n\t\t@(posedge clk);\n\t\tin <= 0;\n\t\trepeat(10) @(posedge clk);\n\t\tin <= 1;\n\t\t@(posedge clk);\n\t\tin <= 0;\n\t\trepeat(10) @(posedge clk);\n\t\tin <= 1;\n\t\t@(posedge clk);\n\t\tin <= 0;\n\t\trepeat(9) @(posedge clk);\n\t\tin <= 1;\n\t\t@(posedge clk);\n\t\t\n\t\t\n\t\t\n\t\trepeat(800) @(posedge clk, negedge clk) begin\n\t\t\tin <= $random;\n\t\t\treset <= !($random & 31);\n\t\tend\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_done;\n\t\tint errortime_done;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic in;\n\tlogic reset;\n\tlogic done_ref;\n\tlogic done_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,in,reset,done_ref,done_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in,\n\t\t.reset );\n\treference_module good1 (\n\t\t.clk,\n\t\t.in,\n\t\t.reset,\n\t\t.done(done_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.in,\n\t\t.reset,\n\t\t.done(done_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_done) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"done\", stats1.errors_done, stats1.errortime_done);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"done\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { done_ref } === ( { done_ref } ^ { done_dut } ^ { done_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (done_ref !== ( done_ref ^ done_dut ^ done_ref ))\n\t\tbegin if (stats1.errors_done == 0) stats1.errortime_done = $time;\n\t\t\tstats1.errors_done = stats1.errors_done+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "fsm_serialdata", "task_number": 148, "description": "In many (older) serial communications protocols, each data byte is sent along with a start bit and a stop bit, to help the receiver delimit bytes from the stream of bits. One common scheme is to use one start bit (0), 8 data bits, and 1 stop bit (1). The line is also at logic 1 when nothing is being transmitted (idle). Design a finite state machine that will identify when bytes have been correctly received when given a stream of bits. It needs to identify the start bit, wait for all 8 data bits, then verify that the stop bit was correct. The module will also output the correctly-received data byte. out_byte needs to be valid when done is 1, and is don't-care otherwise.If the stop bit does not appear when expected, the FSM must wait until it finds a stop bit before attempting to receive the next byte. Include a active-high synchronous reset. Note that the serial protocol sends the least significant bit first. It should assert done each time it finds a stop bit.", "header": "module top_module (\n\tinput clk,\n\tinput in,\n\tinput reset,\n\toutput [7:0] out_byte,\n\toutput done\n);\n", "module_code": "module top_module (\n\tinput clk,\n\tinput in,\n\tinput reset,\n\toutput [7:0] out_byte,\n\toutput done\n);\n\tparameter B0=0, B1=1, B2=2, B3=3, B4=4, B5=5, B6=6, B7=7, START=8, STOP=9, DONE=10, ERR=11;\n\treg [3:0] state;\n\treg [3:0] next;\n    \n    reg [9:0] byte_r;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tSTART: next = in ? START : B0;\t// start bit is 0\n\t\t\tB0: next = B1;\n\t\t\tB1: next = B2;\n\t\t\tB2: next = B3;\n\t\t\tB3: next = B4;\n\t\t\tB4: next = B5;\n\t\t\tB5: next = B6;\n\t\t\tB6: next = B7;\n\t\t\tB7: next = STOP;\n\t\t\tSTOP: next = in ? DONE : ERR;  // stop bit is 1. Idle state is 1.\n\t\t\tDONE: next = in ? START : B0;\n\t\t\tERR: next = in ? START : ERR;\n\t\tendcase\n    end\n    \n    always @(posedge clk) begin\n\t\tif (reset) state <= START;\n        else state <= next;\n\tend\n\t\n\talways @(posedge clk) begin\n\t\tbyte_r <= {in, byte_r[9:1]};\n\tend\n\t\t\n\tassign done = (state==DONE);\n\tassign out_byte = done ? byte_r[8:1] : 8'hx;\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput in,\n\tinput reset,\n\toutput [7:0] out_byte,\n\toutput done\n);\n\tparameter B0=0, B1=1, B2=2, B3=3, B4=4, B5=5, B6=6, B7=7, START=8, STOP=9, DONE=10, ERR=11;\n\treg [3:0] state;\n\treg [3:0] next;\n    \n    reg [9:0] byte_r;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tSTART: next = in ? START : B0;\t// start bit is 0\n\t\t\tB0: next = B1;\n\t\t\tB1: next = B2;\n\t\t\tB2: next = B3;\n\t\t\tB3: next = B4;\n\t\t\tB4: next = B5;\n\t\t\tB5: next = B6;\n\t\t\tB6: next = B7;\n\t\t\tB7: next = STOP;\n\t\t\tSTOP: next = in ? DONE : ERR;  // stop bit is 1. Idle state is 1.\n\t\t\tDONE: next = in ? START : B0;\n\t\t\tERR: next = in ? START : ERR;\n\t\tendcase\n    end\n    \n    always @(posedge clk) begin\n\t\tif (reset) state <= START;\n        else state <= next;\n\tend\n\t\n\talways @(posedge clk) begin\n\t\tbyte_r <= {in, byte_r[9:1]};\n\tend\n\t\t\n\tassign done = (state==DONE);\n\tassign out_byte = done ? byte_r[8:1] : 8'hx;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic in,\n\toutput logic reset\n);\n\n\tinitial begin\n\t\treset <= 1;\n\t\tin <= 1;\n\t\t@(posedge clk);\n\t\treset <= 0;\n\t\tin <= 0;\n\t\trepeat(9) @(posedge clk);\n\t\tin <= 1;\n\t\t@(posedge clk);\n\t\tin <= 0;\n\t\trepeat(9) @(posedge clk);\n\t\tin <= 1;\n\t\t@(posedge clk);\n\t\tin <= 0;\n\t\trepeat(10) @(posedge clk);\n\t\tin <= 1;\n\t\t@(posedge clk);\n\t\tin <= 0;\n\t\trepeat(10) @(posedge clk);\n\t\tin <= 1;\n\t\t@(posedge clk);\n\t\tin <= 0;\n\t\trepeat(9) @(posedge clk);\n\t\tin <= 1;\n\t\t@(posedge clk);\n\t\t\n\t\t\n\t\t\n\t\trepeat(800) @(posedge clk, negedge clk) begin\n\t\t\tin <= $random;\n\t\t\treset <= !($random & 31);\n\t\tend\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out_byte;\n\t\tint errortime_out_byte;\n\t\tint errors_done;\n\t\tint errortime_done;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic in;\n\tlogic reset;\n\tlogic [7:0] out_byte_ref;\n\tlogic [7:0] out_byte_dut;\n\tlogic done_ref;\n\tlogic done_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,in,reset,out_byte_ref,out_byte_dut,done_ref,done_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in,\n\t\t.reset );\n\treference_module good1 (\n\t\t.clk,\n\t\t.in,\n\t\t.reset,\n\t\t.out_byte(out_byte_ref),\n\t\t.done(done_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.in,\n\t\t.reset,\n\t\t.out_byte(out_byte_dut),\n\t\t.done(done_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out_byte) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_byte\", stats1.errors_out_byte, stats1.errortime_out_byte);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_byte\");\n\t\tif (stats1.errors_done) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"done\", stats1.errors_done, stats1.errortime_done);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"done\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_byte_ref, done_ref } === ( { out_byte_ref, done_ref } ^ { out_byte_dut, done_dut } ^ { out_byte_ref, done_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_byte_ref !== ( out_byte_ref ^ out_byte_dut ^ out_byte_ref ))\n\t\tbegin if (stats1.errors_out_byte == 0) stats1.errortime_out_byte = $time;\n\t\t\tstats1.errors_out_byte = stats1.errors_out_byte+1'b1; end\n\t\tif (done_ref !== ( done_ref ^ done_dut ^ done_ref ))\n\t\tbegin if (stats1.errors_done == 0) stats1.errortime_done = $time;\n\t\t\tstats1.errors_done = stats1.errors_done+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "gshare", "task_number": 149, "description": "Build a gshare branch predictor with 7-bit pc and 7-bit global history, hashed (using xor) into a 7-bit index. This index accesses a 128-entry table of two-bit saturating counters. The branch predictor should contain a 7-bit global branch history register. The branch predictor has two sets of interfaces: One for doing predictions and one for doing training. The prediction interface is used in the processor's Fetch stage to ask the branch predictor for branch direction predictions for the instructions being fetched. Once these branches proceed down the pipeline and are executed, the true outcomes of the branches become known. The branch predictor is then trained using the actual branch direction outcomes. \n// When a branch prediction is requested (predict_valid = 1) for a given pc, the branch predictor produces the predicted branch direction and state of the branch history register used to make the prediction. The branch history register is then updated (at the next positive clock edge) for the predicted branch. \n// When training for a branch is requested (train_valid = 1), the branch predictor is told the pc and branch history register value for the branch that is being trained, as well as the actual branch outcome and whether the branch was a misprediction (needing a pipeline flush). Update the pattern history table (PHT) to train the branch predictor to predict this branch more accurately next time. In addition, if the branch being trained is mispredicted, also recover the branch history register to the state immediately after the mispredicting branch completes execution.\n// If training for a misprediction and a prediction (for a different, younger instruction) occurs in the same cycle, both operations will want to modify the branch history register. When this happens, training takes precedence, because the branch being predicted will be discarded anyway. If training and prediction of the same PHT entry happen at the same time, the prediction sees the PHT state before training because training only modifies the PHT at the next positive clock edge. The following timing diagram shows the timing when training and predicting PHT entry 0 at the same time. The training request at cycle 4 changes the PHT entry state in cycle 5, but the prediction request in cycle 4 outputs the PHT state at cycle 4, without considering the effect of the training request in cycle 4. Reset is asynchronous active-high.", "header": "module top_module(\n\tinput clk,\n\tinput areset, \n\n\tinput predict_valid,\n\tinput [6:0] predict_pc,\n\toutput predict_taken, \n\toutput [6:0] predict_history,\n\n\tinput train_valid,\n\tinput train_taken,\n\tinput train_mispredicted,\n\tinput [6:0] train_history, \n\tinput [6:0] train_pc\n);\n", "module_code": "module top_module(\n\tinput clk,\n\tinput areset, \n\n\tinput predict_valid,\n\tinput [6:0] predict_pc,\n\toutput predict_taken, \n\toutput [6:0] predict_history,\n\n\tinput train_valid,\n\tinput train_taken,\n\tinput train_mispredicted,\n\tinput [6:0] train_history, \n\tinput [6:0] train_pc\n);\n\tparameter n = 7;\n\tlogic [1:0] pht [2**n-1:0];\n\n\tparameter [1:0] SNT = 0, LNT = 1, LT = 2, ST = 3;\n\n\tlogic [n-1:0] predict_history_r;\n\twire [n-1:0] predict_index = predict_history_r ^ predict_pc;\n\twire [n-1:0] train_index = train_history ^ train_pc;\n\t\n\talways@(posedge clk, posedge areset)\n\t\tif (areset) begin\n\t\t\tfor (integer i=0; i<2**n; i=i+1)\n\t\t\t\tpht[i] = LNT;\n\t\t\tpredict_history_r = 0;\n        end\telse begin\n\t\t\tif (predict_valid)\n\t\t\t\tpredict_history_r <= {predict_history_r, predict_taken};\n\t\t\tif(train_valid) begin\n\t\t\t\tif(pht[train_index] < 3 && train_taken)\n\t\t\t\t\tpht[train_index] <= pht[train_index] + 1;\n\t\t\t\telse if(pht[train_index] > 0 && !train_taken)\n\t\t\t\t\tpht[train_index] <= pht[train_index] - 1;\n\t\t\t\tif (train_mispredicted)\n\t\t\t\t\tpredict_history_r <= {train_history, train_taken};\n\t\t\tend\n\t\tend\n\n\tassign predict_taken = predict_valid ? pht[predict_index][1] : 1'bx;\n\tassign predict_history = predict_valid ? predict_history_r : {n{1'bx}};\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput clk,\n\tinput areset, \n\n\tinput predict_valid,\n\tinput [6:0] predict_pc,\n\toutput predict_taken, \n\toutput [6:0] predict_history,\n\n\tinput train_valid,\n\tinput train_taken,\n\tinput train_mispredicted,\n\tinput [6:0] train_history, \n\tinput [6:0] train_pc\n);\n\tparameter n = 7;\n\tlogic [1:0] pht [2**n-1:0];\n\n\tparameter [1:0] SNT = 0, LNT = 1, LT = 2, ST = 3;\n\n\tlogic [n-1:0] predict_history_r;\n\twire [n-1:0] predict_index = predict_history_r ^ predict_pc;\n\twire [n-1:0] train_index = train_history ^ train_pc;\n\t\n\talways@(posedge clk, posedge areset)\n\t\tif (areset) begin\n\t\t\tfor (integer i=0; i<2**n; i=i+1)\n\t\t\t\tpht[i] = LNT;\n\t\t\tpredict_history_r = 0;\n        end\telse begin\n\t\t\tif (predict_valid)\n\t\t\t\tpredict_history_r <= {predict_history_r, predict_taken};\n\t\t\tif(train_valid) begin\n\t\t\t\tif(pht[train_index] < 3 && train_taken)\n\t\t\t\t\tpht[train_index] <= pht[train_index] + 1;\n\t\t\t\telse if(pht[train_index] > 0 && !train_taken)\n\t\t\t\t\tpht[train_index] <= pht[train_index] - 1;\n\t\t\t\tif (train_mispredicted)\n\t\t\t\t\tpredict_history_r <= {train_history, train_taken};\n\t\t\tend\n\t\tend\n\n\tassign predict_taken = predict_valid ? pht[predict_index][1] : 1'bx;\n\tassign predict_history = predict_valid ? predict_history_r : {n{1'bx}};\nendmodule\n\n\nmodule stimulus_gen\n#(parameter N=7)\n(\n\tinput clk,\n\toutput logic areset,\n\t\n\toutput logic predict_valid,\n\toutput [N-1:0] predict_pc,\n\t\n\toutput logic train_valid,\n\toutput train_taken,\n\toutput train_mispredicted,\n\toutput [N-1:0] train_history,\n\toutput [N-1:0] train_pc,\n\n\tinput tb_match,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\toutput int wavedrom_hide_after_time\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\treg reset;\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\t\n\tassign areset = reset;\n\t\n\tlogic [N-1:0] predict_pc_r;\n\tlogic train_taken_r;\n\tlogic train_mispredicted_r;\n\tlogic [N-1:0] train_history_r;\n\tlogic [N-1:0] train_pc_r;\n\t\n\tassign predict_pc = predict_valid ? predict_pc_r : {N{1'bx}};\n\tassign train_taken = train_valid ? train_taken_r : 1'bx;\n\tassign train_mispredicted = train_valid ? train_mispredicted_r : 1'bx;\n\tassign train_history = train_valid ? train_history_r : {N{1'bx}};\n\tassign train_pc = train_valid ? train_pc_r : {N{1'bx}};\n\t\n\t\n\tinitial begin\n\t\t@(posedge clk) reset <= 1;\n\t\t@(posedge clk) reset <= 0;\n\t\tpredict_valid <= 1;\n\t\ttrain_mispredicted_r <= 1;\n\t\ttrain_history_r <= 7'h7f;\n\t\ttrain_pc_r <= 7'h4;\n\t\ttrain_taken_r <= 1;\n\t\ttrain_valid <= 1;\n\t\tpredict_valid <= 1;\n\t\tpredict_pc_r <= 4;\n\t\n\t\twavedrom_start(\"Asynchronous reset\");\n\t\t\treset_test(1); // Test for asynchronous reset\n\t\twavedrom_stop();\n\t\t@(posedge clk) reset <= 1;\n\t\tpredict_valid <= 0;\n\n\t\twavedrom_start(\"Training entries (pc = 0xa, history = 0 and 2)\");\n\t\tpredict_pc_r <= 7'ha;\n\t\tpredict_valid <= 1;\n\n\t\ttrain_history_r <= 7'h0;\n\t\ttrain_pc_r <= 7'ha;\n\t\ttrain_taken_r <= 1;\n\t\ttrain_valid <= 0;\n\t\ttrain_mispredicted_r <= 0;\n\t\t\n\t\t@(negedge clk) reset <= 0;\n\t\t@(posedge clk) train_valid <= 1;\n\t\t@(posedge clk) train_history_r <= 7'h2;\n\t\t@(posedge clk) train_valid <= 0;\n\n\t\trepeat(4) @(posedge clk);\n\t\ttrain_history_r <= 7'h0;\n\t\ttrain_taken_r <= 0;\n\t\ttrain_valid <= 1;\n\t\t@(posedge clk) train_valid <= 0;\n\t\t\n\t\trepeat(8) @(posedge clk);\n\t\twavedrom_stop();\n\n\t\t@(posedge clk);\n\n\t\twavedrom_start(\"History register recovery on misprediction\");\n\t\treset <= 1;\n\t\tpredict_pc_r <= 7'ha;\n\t\tpredict_valid <= 1;\n\n\t\ttrain_history_r <= 7'h0;\n\t\ttrain_pc_r <= 7'ha;\n\t\ttrain_taken_r <= 1;\n\t\ttrain_valid <= 0;\n\t\ttrain_mispredicted_r <= 1;\n\t\t\n\t\t@(negedge clk) reset <= 0;\n\t\t@(posedge clk);\n\t\t@(posedge clk) train_valid <= 1;\n\t\t@(posedge clk) train_valid <= 0;\n\t\t@(posedge clk) train_valid <= 1;\n\t\ttrain_history_r <= 7'h10;\n\t\ttrain_taken_r <= 0;\n\t\t@(posedge clk) train_valid <= 0;\n\n\t\trepeat(4) @(posedge clk);\n\t\ttrain_history_r <= 7'h0;\n\t\ttrain_taken_r <= 0;\n\t\ttrain_valid <= 1;\n\t\t@(posedge clk) train_valid <= 0;\n\t\t@(posedge clk) train_valid <= 1;\n\t\ttrain_history_r <= 7'h20;\n\t\t@(posedge clk) train_valid <= 0;\n\t\t\n\t\trepeat(3) @(posedge clk);\n\t\twavedrom_stop();\n\n\t\trepeat(1000) @(posedge clk,negedge clk) begin\n\t\t\t{predict_valid, predict_pc_r, train_pc_r, train_taken_r, train_valid} <= {$urandom};\n\t\t\ttrain_history_r <= $urandom;\n\t\t\ttrain_mispredicted_r <= !($urandom_range(0,31));\n\t\tend\n\n\t\t#1 $finish;\n\tend\n\t\n\t\nendmodule\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_predict_taken;\n\t\tint errortime_predict_taken;\n\t\tint errors_predict_history;\n\t\tint errortime_predict_history;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic areset;\n\tlogic predict_valid;\n\tlogic [6:0] predict_pc;\n\tlogic train_valid;\n\tlogic train_taken;\n\tlogic train_mispredicted;\n\tlogic [6:0] train_history;\n\tlogic [6:0] train_pc;\n\tlogic predict_taken_ref;\n\tlogic predict_taken_dut;\n\tlogic [6:0] predict_history_ref;\n\tlogic [6:0] predict_history_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,areset,predict_valid,predict_pc,train_valid,train_taken,train_mispredicted,train_history,train_pc,predict_taken_ref,predict_taken_dut,predict_history_ref,predict_history_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.areset,\n\t\t.predict_valid,\n\t\t.predict_pc,\n\t\t.train_valid,\n\t\t.train_taken,\n\t\t.train_mispredicted,\n\t\t.train_history,\n\t\t.train_pc );\n\treference_module good1 (\n\t\t.clk,\n\t\t.areset,\n\t\t.predict_valid,\n\t\t.predict_pc,\n\t\t.train_valid,\n\t\t.train_taken,\n\t\t.train_mispredicted,\n\t\t.train_history,\n\t\t.train_pc,\n\t\t.predict_taken(predict_taken_ref),\n\t\t.predict_history(predict_history_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.areset,\n\t\t.predict_valid,\n\t\t.predict_pc,\n\t\t.train_valid,\n\t\t.train_taken,\n\t\t.train_mispredicted,\n\t\t.train_history,\n\t\t.train_pc,\n\t\t.predict_taken(predict_taken_dut),\n\t\t.predict_history(predict_history_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_predict_taken) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"predict_taken\", stats1.errors_predict_taken, stats1.errortime_predict_taken);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"predict_taken\");\n\t\tif (stats1.errors_predict_history) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"predict_history\", stats1.errors_predict_history, stats1.errortime_predict_history);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"predict_history\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { predict_taken_ref, predict_history_ref } === ( { predict_taken_ref, predict_history_ref } ^ { predict_taken_dut, predict_history_dut } ^ { predict_taken_ref, predict_history_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (predict_taken_ref !== ( predict_taken_ref ^ predict_taken_dut ^ predict_taken_ref ))\n\t\tbegin if (stats1.errors_predict_taken == 0) stats1.errortime_predict_taken = $time;\n\t\t\tstats1.errors_predict_taken = stats1.errors_predict_taken+1'b1; end\n\t\tif (predict_history_ref !== ( predict_history_ref ^ predict_history_dut ^ predict_history_ref ))\n\t\tbegin if (stats1.errors_predict_history == 0) stats1.errortime_predict_history = $time;\n\t\t\tstats1.errors_predict_history = stats1.errors_predict_history+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "lemmings4", "task_number": 150, "description": "The game Lemmings involves critters with fairly simple brains. So simple that we are going to model it using a finite state machine. In the Lemmings' 2D world, Lemmings can be in one of two states: walking left (walk_left is 1) or walking right (walk_right is 1). It will switch directions if it hits an obstacle. In particular, if a Lemming is bumped on the left (by receiving a 1 on bump_left), it will walk right. If it's bumped on the right (by receiving a 1 on bump_right), it will walk left. If it's bumped on both sides at the same time, it will still switch directions. \n// In addition to walking left and right and changing direction when bumped, when ground=0, the Lemming will fall and say \"\"aaah!\"\". When the ground reappears (ground=1), the Lemming will resume walking in the same direction as before the fall. Being bumped while falling does not affect the walking direction, and being bumped in the same cycle as ground disappears (but not yet falling), or when the ground reappears while still falling, also does not affect the walking direction.\n// In addition to walking and falling, Lemmings can sometimes be told to do useful things, like dig (it starts digging when dig=1). A Lemming can dig if it is currently walking on ground (ground=1 and not falling), and will continue digging until it reaches the other side (ground=0). At that point, since there is no ground, it will fall (aaah!), then continue walking in its original direction once it hits ground again. As with falling, being bumped while digging has no effect, and being told to dig when falling or when there is no ground is ignored. (In other words, a walking Lemming can fall, dig, or switch directions. If more than one of these conditions are satisfied, fall has higher precedence than dig, which has higher precedence than switching directions.)\n// Although Lemmings can walk, fall, and dig, Lemmings aren't invulnerable. If a Lemming falls for too long then hits the ground, it can splatter. In particular, if a Lemming falls for more than 20 clock cycles then hits the ground, it will splatter and cease walking, falling, or digging (all 4 outputs become 0), forever (Or until the FSM gets reset). There is no upper limit on how far a Lemming can fall before hitting the ground. Lemmings only splatter when hitting the ground; they do not splatter in mid-air.\n// Implement a Moore state machine that models this behaviour. areset is positive edge triggered asynchronous reseting the Lemming machine to walk left.", "header": "module top_module (\n\tinput clk,\n\tinput areset,\n\tinput bump_left,\n\tinput bump_right,\n\tinput ground,\n\tinput dig,\n\toutput walk_left,\n\toutput walk_right,\n\toutput aaah,\n\toutput digging\n);\n", "module_code": "module top_module (\n\tinput clk,\n\tinput areset,\n\tinput bump_left,\n\tinput bump_right,\n\tinput ground,\n\tinput dig,\n\toutput walk_left,\n\toutput walk_right,\n\toutput aaah,\n\toutput digging\n);\n\tparameter WL=0, WR=1, FALLL=2, FALLR=3, DIGL=4, DIGR=5, DEAD=6;\n\treg [2:0] state;\n\treg [2:0] next;\n    \n    reg [4:0] fall_counter;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tWL: if (!ground) next = FALLL;\n\t\t\t\telse if (dig) next = DIGL;\n\t\t\t\telse if (bump_left) next = WR;\n\t\t\t\telse next = WL;\n\t\t\tWR: \n\t\t\t\tif (!ground) next = FALLR;\n\t\t\t\telse if (dig) next = DIGR;\n\t\t\t\telse if (bump_right) next = WL;\n\t\t\t\telse next = WR;\n\t\t\tFALLL: next = ground ? (fall_counter >= 20 ? DEAD : WL) : FALLL;\n\t\t\tFALLR: next = ground ? (fall_counter >= 20 ? DEAD : WR) : FALLR;\n\t\t\tDIGL: next = ground ? DIGL : FALLL;\n\t\t\tDIGR: next = ground ? DIGR : FALLR;\n\t\t\tDEAD: next = DEAD;\n\t\tendcase\n    end\n    \n    always @(posedge clk, posedge areset) begin\n\t\tif (areset) state <= WL;\n        else state <= next;\n\tend\n\t\n\talways @(posedge clk) begin\n\t\tif (state == FALLL || state == FALLR) begin\n\t\t\tif (fall_counter < 20)\n\t\t\t\tfall_counter <= fall_counter + 1'b1;\n\t\tend\n\t\telse\n\t\t\tfall_counter <= 0;\n\tend\n\t\t\n\tassign walk_left = (state==WL);\n\tassign walk_right = (state==WR);\n\tassign aaah = (state == FALLL) || (state == FALLR);\n\tassign digging = (state == DIGL) || (state == DIGR);\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput areset,\n\tinput bump_left,\n\tinput bump_right,\n\tinput ground,\n\tinput dig,\n\toutput walk_left,\n\toutput walk_right,\n\toutput aaah,\n\toutput digging\n);\n\tparameter WL=0, WR=1, FALLL=2, FALLR=3, DIGL=4, DIGR=5, DEAD=6;\n\treg [2:0] state;\n\treg [2:0] next;\n    \n    reg [4:0] fall_counter;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tWL: if (!ground) next = FALLL;\n\t\t\t\telse if (dig) next = DIGL;\n\t\t\t\telse if (bump_left) next = WR;\n\t\t\t\telse next = WL;\n\t\t\tWR: \n\t\t\t\tif (!ground) next = FALLR;\n\t\t\t\telse if (dig) next = DIGR;\n\t\t\t\telse if (bump_right) next = WL;\n\t\t\t\telse next = WR;\n\t\t\tFALLL: next = ground ? (fall_counter >= 20 ? DEAD : WL) : FALLL;\n\t\t\tFALLR: next = ground ? (fall_counter >= 20 ? DEAD : WR) : FALLR;\n\t\t\tDIGL: next = ground ? DIGL : FALLL;\n\t\t\tDIGR: next = ground ? DIGR : FALLR;\n\t\t\tDEAD: next = DEAD;\n\t\tendcase\n    end\n    \n    always @(posedge clk, posedge areset) begin\n\t\tif (areset) state <= WL;\n        else state <= next;\n\tend\n\t\n\talways @(posedge clk) begin\n\t\tif (state == FALLL || state == FALLR) begin\n\t\t\tif (fall_counter < 20)\n\t\t\t\tfall_counter <= fall_counter + 1'b1;\n\t\tend\n\t\telse\n\t\t\tfall_counter <= 0;\n\tend\n\t\t\n\tassign walk_left = (state==WL);\n\tassign walk_right = (state==WR);\n\tassign aaah = (state == FALLL) || (state == FALLR);\n\tassign digging = (state == DIGL) || (state == DIGR);\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic areset,\n\toutput logic bump_left,\n\toutput logic bump_right,\n\toutput logic dig,\n\toutput logic ground,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\tinput tb_match\n);\n\n\treg reset;\n\tassign areset = reset;\n\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\treset <= 1'b1;\n\t\t@(posedge clk);\n\t\treset <= 0;\n\t\t{bump_left, bump_right, ground, dig} <= 2;\n\t\trepeat(2) @(posedge clk);\n\t\t{bump_left, bump_right, ground, dig} <= 3;\n\t\t@(posedge clk);\n\t\t{bump_left, bump_right, ground, dig} <= 2;\n\t\t@(posedge clk);\n\t\t{bump_left, bump_right, ground, dig} <= 10;\n\t\t@(posedge clk);\n\t\t{bump_left, bump_right, ground, dig} <= 2;\n\t\t@(posedge clk);\n\t\t{bump_left, bump_right, ground, dig} <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\t{bump_left, bump_right, ground, dig} <= 3;\n\t\t@(posedge clk);\n\t\t{bump_left, bump_right, ground, dig} <= 2;\n\t\trepeat(4) @(posedge clk);\n\t\t\n\t\t{bump_left, bump_right, ground, dig} <= 0;\t\t// Fall\n\t\trepeat(20) @(posedge clk);\n\t\t{bump_left, bump_right, ground, dig} <= 2;\t\t// Survive\n\t\trepeat(1) @(posedge clk);\n\n\t\t{bump_left, bump_right, ground, dig} <= 0;\t\t// Fall\n\t\trepeat(21) @(posedge clk);\n\t\t{bump_left, bump_right, ground, dig} <= 2;\t\t// Splat after falling left\n\t\trepeat(20) @(posedge clk) begin\n\t\t\t{dig, bump_right, bump_left} <= $random & $random;\t// See if it's handled correctly.\n\t\t\tground <= |($random & 7);\n\t\tend\n\t\t\t\n\n\t\treset <= 1;\n\t\t{bump_left, bump_right, ground, dig} <= 2;\t\t// Normal\n\t\t@(posedge clk)\n\t\treset <= 0;\t\t// Resurrect.\n\t\tbump_left <= 1;\n\t\trepeat(5) @(posedge clk);\n\t\t{bump_left, bump_right, ground, dig} <= 0;\t\t// Fall\n\t\trepeat(21) @(posedge clk);\n\t\t{bump_left, bump_right, ground, dig} <= 2;\t\t// Splat after falling right\n\t\trepeat(20) @(posedge clk) begin\n\t\t\t{dig, bump_right, bump_left} <= $random & $random;\t// See if it's handled correctly.\n\t\t\tground <= |($random & 7);\n\t\tend\n\n\t\treset <= 1;\n\t\t@(posedge clk)\n\t\treset <= 0;\t\t// Resurrect.\n\t\t{bump_left, bump_right, ground, dig} <= 2;\t\t// Normal\n\t\twavedrom_start(\"Splat?\");\n\t\t@(posedge clk);\n\t\t{bump_left, bump_right, ground, dig} <= 0;\t\t// Fall\n\t\trepeat(24) @(posedge clk);\n\t\t{bump_left, bump_right, ground, dig} <= 2;\t\t// Splat? (24-cycles)\n\t\trepeat(2) @(posedge clk);\n\t\twavedrom_stop();\n\t\t\n\t\treset <= 1;\n\t\t@(posedge clk)\n\t\treset <= 0;\t\t// Resurrect.\n\t\t{bump_left, bump_right, ground, dig} <= 2;\t\t// Normal\n\t\t@(posedge clk);\n\t\t@(posedge clk);\n\t\t{bump_left, bump_right, ground, dig} <= 0;\t\t// Fall\n\t\trepeat(35) @(posedge clk);\n\t\t{bump_left, bump_right, ground, dig} <= 2;\t\t// Splat? (Test for 5-bit non-saturating counter)\n\t\trepeat(2) @(posedge clk);\n\t\trepeat(20) @(posedge clk) begin\n\t\t\t{dig, bump_right, bump_left} <= $random & $random;\t// See if it's handled correctly.\n\t\t\tground <= |($random & 7);\n\t\tend\t\t\n\n\t\treset <= 1;\n\t\t{bump_left, bump_right, ground, dig} <= 2;\t\t// Normal\n\t\t@(posedge clk);\n\t\treset <= 0;\t\t// Resurrect.\n\t\t@(posedge clk);\n\t\t{bump_left, bump_right, ground, dig} <= 0;\t\t// Fall\n\t\trepeat(67) @(posedge clk);\n\t\t{bump_left, bump_right, ground, dig} <= 2;\t\t// Splat? (Test for 6-bit non-saturating counter)\n\t\trepeat(20) @(posedge clk) begin\n\t\t\t{dig, bump_right, bump_left} <= $random & $random;\t// See if it's handled correctly.\n\t\t\tground <= |($random & 7);\n\t\tend\n\t\t\n\t\treset <= 1;\n\t\t{bump_left, bump_right, ground, dig} <= 2;\t\t// Normal\n\t\t@(posedge clk)\n\t\treset <= 0;\t\t// Resurrect.\n\t\t\n\t\t\n\t\trepeat(400) @(posedge clk, negedge clk) begin\n\t\t\t{dig, bump_right, bump_left} <= $random & $random;\n\t\t\tground <= |($random & 7);\n\t\t\treset <= !($random & 31);\n\t\tend\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_walk_left;\n\t\tint errortime_walk_left;\n\t\tint errors_walk_right;\n\t\tint errortime_walk_right;\n\t\tint errors_aaah;\n\t\tint errortime_aaah;\n\t\tint errors_digging;\n\t\tint errortime_digging;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic areset;\n\tlogic bump_left;\n\tlogic bump_right;\n\tlogic ground;\n\tlogic dig;\n\tlogic walk_left_ref;\n\tlogic walk_left_dut;\n\tlogic walk_right_ref;\n\tlogic walk_right_dut;\n\tlogic aaah_ref;\n\tlogic aaah_dut;\n\tlogic digging_ref;\n\tlogic digging_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,areset,bump_left,bump_right,ground,dig,walk_left_ref,walk_left_dut,walk_right_ref,walk_right_dut,aaah_ref,aaah_dut,digging_ref,digging_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.areset,\n\t\t.bump_left,\n\t\t.bump_right,\n\t\t.ground,\n\t\t.dig );\n\treference_module good1 (\n\t\t.clk,\n\t\t.areset,\n\t\t.bump_left,\n\t\t.bump_right,\n\t\t.ground,\n\t\t.dig,\n\t\t.walk_left(walk_left_ref),\n\t\t.walk_right(walk_right_ref),\n\t\t.aaah(aaah_ref),\n\t\t.digging(digging_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.areset,\n\t\t.bump_left,\n\t\t.bump_right,\n\t\t.ground,\n\t\t.dig,\n\t\t.walk_left(walk_left_dut),\n\t\t.walk_right(walk_right_dut),\n\t\t.aaah(aaah_dut),\n\t\t.digging(digging_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_walk_left) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"walk_left\", stats1.errors_walk_left, stats1.errortime_walk_left);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"walk_left\");\n\t\tif (stats1.errors_walk_right) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"walk_right\", stats1.errors_walk_right, stats1.errortime_walk_right);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"walk_right\");\n\t\tif (stats1.errors_aaah) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"aaah\", stats1.errors_aaah, stats1.errortime_aaah);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"aaah\");\n\t\tif (stats1.errors_digging) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"digging\", stats1.errors_digging, stats1.errortime_digging);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"digging\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { walk_left_ref, walk_right_ref, aaah_ref, digging_ref } === ( { walk_left_ref, walk_right_ref, aaah_ref, digging_ref } ^ { walk_left_dut, walk_right_dut, aaah_dut, digging_dut } ^ { walk_left_ref, walk_right_ref, aaah_ref, digging_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (walk_left_ref !== ( walk_left_ref ^ walk_left_dut ^ walk_left_ref ))\n\t\tbegin if (stats1.errors_walk_left == 0) stats1.errortime_walk_left = $time;\n\t\t\tstats1.errors_walk_left = stats1.errors_walk_left+1'b1; end\n\t\tif (walk_right_ref !== ( walk_right_ref ^ walk_right_dut ^ walk_right_ref ))\n\t\tbegin if (stats1.errors_walk_right == 0) stats1.errortime_walk_right = $time;\n\t\t\tstats1.errors_walk_right = stats1.errors_walk_right+1'b1; end\n\t\tif (aaah_ref !== ( aaah_ref ^ aaah_dut ^ aaah_ref ))\n\t\tbegin if (stats1.errors_aaah == 0) stats1.errortime_aaah = $time;\n\t\t\tstats1.errors_aaah = stats1.errors_aaah+1'b1; end\n\t\tif (digging_ref !== ( digging_ref ^ digging_dut ^ digging_ref ))\n\t\tbegin if (stats1.errors_digging == 0) stats1.errortime_digging = $time;\n\t\t\tstats1.errors_digging = stats1.errors_digging+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "review2015_fsm", "task_number": 151, "description": "We want to create a timer that:\n// (1) is started when a particular pattern (1101) is detected,\n// (2) shifts in 4 more bits to determine the duration to delay,\n// (3) waits for the counters to finish counting, and\n// (4) notifies the user and waits for the user to acknowledge the timer.\n// In this problem, implement just the finite-state machine that controls the timer. The data path (counters and some comparators) are not included here.\n// The serial data is available on the data input pin. When the pattern 1101 is received, the state machine must then assert output shift_ena for exactly 4 clock cycles. After that, the state machine asserts its counting output to indicate it is waiting for the counters, and waits until input done_counting is high.At that point, the state machine must assert done to notify the user the timer has timed out, and waits until input ack is 1 before being reset to look for the next occurrence of the start sequence (1101). The state machine should have a active high synchronous reset, setting the state to where it begins searching for the input sequence 1101.", "header": "module top_module(\n\tinput clk,\n\tinput reset,\n\tinput data,\n    output reg shift_ena,\n    output reg counting,\n    input done_counting,\n    output reg done,\n    input ack );\n", "module_code": "module top_module(\n\tinput clk,\n\tinput reset,\n\tinput data,\n    output reg shift_ena,\n    output reg counting,\n    input done_counting,\n    output reg done,\n    input ack );\n\n\ttypedef enum logic[3:0] {\n\t\tS, S1, S11, S110, B0, B1, B2, B3, Count, Wait\n\t} States;\n\t\n\tStates state, next;\n\t\n\talways_comb begin\n\t\tcase (state)\n\t\t\tS: next = States'(data ? S1: S);\n\t\t\tS1: next = States'(data ? S11: S);\n\t\t\tS11: next = States'(data ? S11 : S110);\n\t\t\tS110: next = States'(data ? B0 : S);\n\t\t\tB0: next = B1;\n\t\t\tB1: next = B2;\n\t\t\tB2: next = B3;\n\t\t\tB3: next = Count;\n\t\t\tCount: next = States'(done_counting ? Wait : Count);\n\t\t\tWait: next = States'(ack ? S : Wait);\n\t\t\tdefault: next = States'(4'bx);\n\t\tendcase\n\tend\n\t\n\talways @(posedge clk) begin\n\t\tif (reset) state <= S;\n\t\telse state <= next;\n\tend\n\t\t\n\talways_comb begin\n\t\tshift_ena = 0; counting = 0; done = 0;\n\t\tif (state == B0 || state == B1 || state == B2 || state == B3)\n\t\t\tshift_ena = 1;\n\t\tif (state == Count)\n\t\t\tcounting = 1;\n\t\tif (state == Wait)\n\t\t\tdone = 1;\n\n\t\tif (|state === 1'bx) begin\n\t\t\t{shift_ena, counting, done} = 'x;\n\t\tend\n\t\t\n\tend\n\t\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput clk,\n\tinput reset,\n\tinput data,\n    output reg shift_ena,\n    output reg counting,\n    input done_counting,\n    output reg done,\n    input ack );\n\n\ttypedef enum logic[3:0] {\n\t\tS, S1, S11, S110, B0, B1, B2, B3, Count, Wait\n\t} States;\n\t\n\tStates state, next;\n\t\n\talways_comb begin\n\t\tcase (state)\n\t\t\tS: next = States'(data ? S1: S);\n\t\t\tS1: next = States'(data ? S11: S);\n\t\t\tS11: next = States'(data ? S11 : S110);\n\t\t\tS110: next = States'(data ? B0 : S);\n\t\t\tB0: next = B1;\n\t\t\tB1: next = B2;\n\t\t\tB2: next = B3;\n\t\t\tB3: next = Count;\n\t\t\tCount: next = States'(done_counting ? Wait : Count);\n\t\t\tWait: next = States'(ack ? S : Wait);\n\t\t\tdefault: next = States'(4'bx);\n\t\tendcase\n\tend\n\t\n\talways @(posedge clk) begin\n\t\tif (reset) state <= S;\n\t\telse state <= next;\n\tend\n\t\t\n\talways_comb begin\n\t\tshift_ena = 0; counting = 0; done = 0;\n\t\tif (state == B0 || state == B1 || state == B2 || state == B3)\n\t\t\tshift_ena = 1;\n\t\tif (state == Count)\n\t\t\tcounting = 1;\n\t\tif (state == Wait)\n\t\t\tdone = 1;\n\n\t\tif (|state === 1'bx) begin\n\t\t\t{shift_ena, counting, done} = 'x;\n\t\tend\n\t\t\n\tend\n\t\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg reset,\n\toutput reg data, done_counting, ack,\n\tinput tb_match\n);\n\tbit failed = 0;\n\t\n\talways @(posedge clk, negedge clk)\n\t\tif (!tb_match) \n\t\t\tfailed <= 1;\n\t\n\tinitial begin\n\n\t\t@(posedge clk);\n\t\tfailed <= 0;\n\t\treset <= 1;\n\t\tdata <= 0;\n\t\tdone_counting <= 1'bx;\n\t\tack <= 1'bx;\n\t\t@(posedge clk) \n\t\t\tdata <= 1;\n\t\t\treset <= 0;\n\t\t@(posedge clk) data <= 0;\n\t\t@(posedge clk) data <= 0;\n\t\t@(posedge clk) data <= 1;\n\t\t@(posedge clk) data <= 1;\n\t\t@(posedge clk) data <= 0;\n\t\t@(posedge clk) data <= 1;\n\t\t@(posedge clk);\n\t\t\tdata <= 1'bx;\n\t\trepeat(4) @(posedge clk);\n\t\t\tdone_counting <= 1'b0;\n\t\trepeat(4) @(posedge clk);\n\t\t\tdone_counting <= 1'b1;\n\t\t@(posedge clk);\n\t\t\tdone_counting <= 1'bx;\n\t\t\tack <= 1'b0;\n\t\trepeat(3) @(posedge clk);\n\t\t\tack <= 1'b1;\n\t\t@(posedge clk);\n\t\t\tack <= 1'b0;\n\t\t\tdata <= 1'b1;\n\t\t@(posedge clk);\n\t\t\tack <= 1'bx;\n\t\t\tdata <= 1'b1;\n\t\t@(posedge clk);\n\t\t\tdata <= 1'b0;\n\t\t@(posedge clk);\n\t\t\tdata <= 1'b1;\n\t\t@(posedge clk);\n\t\t\tdata <= 1'bx;\n\t\trepeat(4) @(posedge clk);\n\t\t\tdone_counting <= 1'b0;\n\t\trepeat(4) @(posedge clk);\n\t\t\tdone_counting <= 1'b1;\n\t\t@(posedge clk);\n\n\t\tif (failed)\n\t\t\t$display(\"Hint: Your FSM didn't pass the sample timing diagram posted with the problem statement. Perhaps try debugging that?\");\n\t\t\n\t\t\n\t\n\t\trepeat(5000) @(posedge clk, negedge clk) begin\n\t\t\treset <= !($random & 255);\n\t\t\tdata <= $random;\n\t\t\tdone_counting <= !($random & 31);\n\t\t\tack <= !($random & 31);\n\t\tend\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_shift_ena;\n\t\tint errortime_shift_ena;\n\t\tint errors_counting;\n\t\tint errortime_counting;\n\t\tint errors_done;\n\t\tint errortime_done;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic reset;\n\tlogic data;\n\tlogic done_counting;\n\tlogic ack;\n\tlogic shift_ena_ref;\n\tlogic shift_ena_dut;\n\tlogic counting_ref;\n\tlogic counting_dut;\n\tlogic done_ref;\n\tlogic done_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,data,done_counting,ack,shift_ena_ref,shift_ena_dut,counting_ref,counting_dut,done_ref,done_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.reset,\n\t\t.data,\n\t\t.done_counting,\n\t\t.ack );\n\treference_module good1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.data,\n\t\t.done_counting,\n\t\t.ack,\n\t\t.shift_ena(shift_ena_ref),\n\t\t.counting(counting_ref),\n\t\t.done(done_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.data,\n\t\t.done_counting,\n\t\t.ack,\n\t\t.shift_ena(shift_ena_dut),\n\t\t.counting(counting_dut),\n\t\t.done(done_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_shift_ena) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"shift_ena\", stats1.errors_shift_ena, stats1.errortime_shift_ena);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"shift_ena\");\n\t\tif (stats1.errors_counting) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"counting\", stats1.errors_counting, stats1.errortime_counting);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"counting\");\n\t\tif (stats1.errors_done) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"done\", stats1.errors_done, stats1.errortime_done);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"done\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { shift_ena_ref, counting_ref, done_ref } === ( { shift_ena_ref, counting_ref, done_ref } ^ { shift_ena_dut, counting_dut, done_dut } ^ { shift_ena_ref, counting_ref, done_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (shift_ena_ref !== ( shift_ena_ref ^ shift_ena_dut ^ shift_ena_ref ))\n\t\tbegin if (stats1.errors_shift_ena == 0) stats1.errortime_shift_ena = $time;\n\t\t\tstats1.errors_shift_ena = stats1.errors_shift_ena+1'b1; end\n\t\tif (counting_ref !== ( counting_ref ^ counting_dut ^ counting_ref ))\n\t\tbegin if (stats1.errors_counting == 0) stats1.errortime_counting = $time;\n\t\t\tstats1.errors_counting = stats1.errors_counting+1'b1; end\n\t\tif (done_ref !== ( done_ref ^ done_dut ^ done_ref ))\n\t\tbegin if (stats1.errors_done == 0) stats1.errortime_done = $time;\n\t\t\tstats1.errors_done = stats1.errors_done+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "conwaylife", "task_number": 152, "description": "The \"game\" is played on a two-dimensional grid of cells, where each cell is either 1 (alive) or 0 (dead). At each time step, each cell changes state depending on how many neighbours it has:\n// (1) 0-1 neighbour: Cell becomes 0.\n// (2) 2 neighbours: Cell state does not change.\n// (3) 3 neighbours: Cell becomes 1.\n// (4) 4+ neighbours: Cell becomes 0.\n// The game is formulated for an infinite grid. In this circuit, we will use a 16x16 grid. To make things more interesting, we will use a 16x16 toroid, where the sides wrap around to the other side of the grid. For example, the corner cell (0,0) has 8 neighbours: (15,1), (15,0), (15,15), (0,1), (0,15), (1,1), (1,0), and (1,15). The 16x16 grid is represented by a length 256 vector, where each row of 16 cells is represented by a sub-vector: q[15:0] is row 0, q[31:16] is row 1, etc. \n// (1) load: Loads data into q at the next clock edge, for loading initial state. Active high synchronous.\n// (2) q: The 16x16 current state of the game, updated every clock cycle.\n// The game state should advance by one timestep every clock cycle.", "header": "module top_module(\n\tinput clk,\n\tinput load,\n\tinput [255:0] data,\n\toutput reg [255:0] q);\n", "module_code": "module top_module(\n\tinput clk,\n\tinput load,\n\tinput [255:0] data,\n\toutput reg [255:0] q);\n\t\n\t\n\tlogic [323:0] q_pad;\n\talways@(*) begin\n\t\tfor (int i=0;i<16;i++)\n\t\t\tq_pad[18*(i+1)+1 +: 16] = q[16*i +: 16];\n\t\tq_pad[1 +: 16] = q[16*15 +: 16];\n\t\tq_pad[18*17+1 +: 16] = q[0 +: 16];\n\t\t\n\t\tfor (int i=0; i<18; i++) begin\n\t\t\tq_pad[i*18] = q_pad[i*18+16];\n\t\t\tq_pad[i*18+17] = q_pad[i*18+1];\n\t\tend\n\tend\n\t\n\talways @(posedge clk) begin\n\t\tfor (int i=0;i<16;i++)\n\t\tfor (int j=0;j<16;j++) begin\n\t\t\tq[i*16+j] <= \n\t\t\t\t((q_pad[(i+1)*18+j+1 -1+18] + q_pad[(i+1)*18+j+1 +18] + q_pad[(i+1)*18+j+1 +1+18] +\n\t\t\t\tq_pad[(i+1)*18+j+1 -1]                                + q_pad[(i+1)*18+j+1+1] +\n\t\t\t\tq_pad[(i+1)*18+j+1 -1-18]   + q_pad[(i+1)*18+j+1 -18] + q_pad[(i+1)*18+j+1 +1-18]) & 3'h7 | q[i*16+j]) == 3'h3;\n\t\tend\n\t\t\n\t\tif (load)\n\t\t\tq <= data;\n\t\t\n\tend\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput clk,\n\tinput load,\n\tinput [255:0] data,\n\toutput reg [255:0] q);\n\t\n\t\n\tlogic [323:0] q_pad;\n\talways@(*) begin\n\t\tfor (int i=0;i<16;i++)\n\t\t\tq_pad[18*(i+1)+1 +: 16] = q[16*i +: 16];\n\t\tq_pad[1 +: 16] = q[16*15 +: 16];\n\t\tq_pad[18*17+1 +: 16] = q[0 +: 16];\n\t\t\n\t\tfor (int i=0; i<18; i++) begin\n\t\t\tq_pad[i*18] = q_pad[i*18+16];\n\t\t\tq_pad[i*18+17] = q_pad[i*18+1];\n\t\tend\n\tend\n\t\n\talways @(posedge clk) begin\n\t\tfor (int i=0;i<16;i++)\n\t\tfor (int j=0;j<16;j++) begin\n\t\t\tq[i*16+j] <= \n\t\t\t\t((q_pad[(i+1)*18+j+1 -1+18] + q_pad[(i+1)*18+j+1 +18] + q_pad[(i+1)*18+j+1 +1+18] +\n\t\t\t\tq_pad[(i+1)*18+j+1 -1]                                + q_pad[(i+1)*18+j+1+1] +\n\t\t\t\tq_pad[(i+1)*18+j+1 -1-18]   + q_pad[(i+1)*18+j+1 -18] + q_pad[(i+1)*18+j+1 +1-18]) & 3'h7 | q[i*16+j]) == 3'h3;\n\t\tend\n\t\t\n\t\tif (load)\n\t\t\tq <= data;\n\t\t\n\tend\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\tinput tb_match,\n\tinput [255:0] q_ref,\n\tinput [255:0] q_dut,\n\toutput reg load,\n\toutput reg[255:0] data\n);\n\n\tlogic errored = 0;\n\tint blinker_cycle = 0;\n\n\tinitial begin\n\t\tdata <= 3'h7;\t\t\t// Simple blinker, period 2\n\t\tload <= 1;\n\t\t@(posedge clk);\n\t\tload <= 0;\n\t\tdata <= 4'hx;\n\t\terrored = 0;\n\t\tblinker_cycle = 0;\n\t\trepeat(5) @(posedge clk) begin\n\t\t\tblinker_cycle++;\n\t\t\tif (!tb_match) begin\n\t\t\t\tif (!errored) begin\n\t\t\t\t\terrored = 1;\n\t\t\t\t\t$display(\"Hint: The first test case is a blinker (initial state = 256'h7). First mismatch occurred at cycle %0d.\\nHint:\", blinker_cycle);\n\t\t\t\tend\n\t\t\tend\n\t\t\t\n\t\t\tif (errored) begin\n\t\t\t\t$display (\"Hint: Cycle %0d:         Your game state       Reference game state\", blinker_cycle);\n\t\t\t\tfor (int i=15;i>=0;i--) begin\n\t\t\t\t\t$display(\"Hint:   q[%3d:%3d]     %016b      %016b\", i*16+15, i*16, q_dut [ i*16 +: 16 ], q_ref[ i*16 +: 16 ]);\n\t\t\t\tend\n\t\t\t\t$display(\"Hint:\\nHint:\\n\");\n\t\t\tend\n\t\tend\n\n\n\t\tdata <= 48'h000200010007;\t// Glider, Traveling diagonal down-right.\n\t\tload <= 1;\n\t\t@(posedge clk);\n\t\t@(posedge clk);\n\t\t@(posedge clk);\n\t\tload <= 0;\n\t\tdata <= 4'hx;\n\t\terrored = 0;\n\t\tblinker_cycle = 0;\n\t\trepeat(100) @(posedge clk) begin\n\t\t\tblinker_cycle++;\n\t\t\tif (!tb_match) begin\n\t\t\t\tif (!errored) begin\n\t\t\t\t\terrored = 1;\n\t\t\t\t\t$display(\"Hint: The second test case is a glider (initial state = 256'h000200010007). First mismatch occurred at cycle %0d.\\nHint:\", blinker_cycle);\n\t\t\t\tend\n\t\t\tend\n\t\t\t\n\t\t\tif (errored && blinker_cycle < 20) begin\n\t\t\t\t$display (\"Hint: Cycle %0d:         Your game state       Reference game state\", blinker_cycle);\n\t\t\t\tfor (int i=15;i>=0;i--) begin\n\t\t\t\t\t$display(\"Hint:   q[%3d:%3d]     %016b      %016b\", i*16+15, i*16, q_dut [ i*16 +: 16 ], q_ref[ i*16 +: 16 ]);\n\t\t\t\tend\n\t\t\t\t$display(\"Hint:\\nHint:\\n\");\n\t\t\tend\n\t\tend\n\n\n\t\tdata <= 48'h0040001000ce;\t\t\t// Acorn\n\t\tload <= 1;\n\t\t@(posedge clk);\n\t\tload <= 0;\n\t\trepeat(2000) @(posedge clk);\n\n\t\t\n\t\tdata <= {$random,$random,$random,$random,$random,$random,$random,$random};\t\t// Some random test cases.\n\t\tload <= 1;\n\t\t@(posedge clk);\n\t\tload <= 0;\n\t\trepeat(200) @(posedge clk);\n\n\t\tdata <= {$random,$random,$random,$random,$random,$random,$random,$random}&\t\t// Random with more zeros.\n\t\t\t\t{$random,$random,$random,$random,$random,$random,$random,$random}&\n\t\t\t\t{$random,$random,$random,$random,$random,$random,$random,$random}&\n\t\t\t\t{$random,$random,$random,$random,$random,$random,$random,$random};\n\t\tload <= 1;\n\t\t@(posedge clk);\n\t\tload <= 0;\n\t\trepeat(200) @(posedge clk);\n\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_q;\n\t\tint errortime_q;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic load;\n\tlogic [255:0] data;\n\tlogic [255:0] q_ref;\n\tlogic [255:0] q_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,load,data,q_ref,q_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.load,\n\t\t.data );\n\treference_module good1 (\n\t\t.clk,\n\t\t.load,\n\t\t.data,\n\t\t.q(q_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.load,\n\t\t.data,\n\t\t.q(q_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"q\", stats1.errors_q, stats1.errortime_q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"q\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (q_ref !== ( q_ref ^ q_dut ^ q_ref ))\n\t\tbegin if (stats1.errors_q == 0) stats1.errortime_q = $time;\n\t\t\tstats1.errors_q = stats1.errors_q+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "lemmings3", "task_number": 153, "description": "The game Lemmings involves critters with fairly simple brains. So simple that we are going to model it using a finite state machine. In the Lemmings' 2D world, Lemmings can be in one of two states: walking left (walk_left is 1) or walking right (walk_right is 1). It will switch directions if it hits an obstacle. In particular, if a Lemming is bumped on the left (by receiving a 1 on bump_left), it will walk right. If it's bumped on the right (by receiving a 1 on bump_right), it will walk left. If it's bumped on both sides at the same time, it will still switch directions. \n// In addition to walking left and right and changing direction when bumped, when ground=0, the Lemming will fall and say \"aaah!\". When the ground reappears (ground=1), the Lemming will resume walking in the same direction as before the fall. Being bumped while falling does not affect the walking direction, and being bumped in the same cycle as ground disappears (but not yet falling), or when the ground reappears while still falling, also does not affect the walking direction.\n// In addition to walking and falling, Lemmings can sometimes be told to do useful things, like dig (it starts digging when dig=1). A Lemming can dig if it is currently walking on ground (ground=1 and not falling), and will continue digging until it reaches the other side (ground=0). At that point, since there is no ground, it will fall (aaah!), then continue walking in its original direction once it hits ground again. As with falling, being bumped while digging has no effect, and being told to dig when falling or when there is no ground is ignored. (In other words, a walking Lemming can fall, dig, or switch directions. If more than one of these conditions are satisfied, fall has higher precedence than dig, which has higher precedence than switching directions.)\n// Implement a Moore state machine that models this behaviour. areset is positive edge triggered asynchronous reseting the Lemming machine to walk left.", "header": "module top_module (\n\tinput clk,\n\tinput areset,\n\tinput bump_left,\n\tinput bump_right,\n\tinput ground,\n\tinput dig,\n\toutput walk_left,\n\toutput walk_right,\n\toutput aaah,\n\toutput digging\n);\n", "module_code": "module top_module (\n\tinput clk,\n\tinput areset,\n\tinput bump_left,\n\tinput bump_right,\n\tinput ground,\n\tinput dig,\n\toutput walk_left,\n\toutput walk_right,\n\toutput aaah,\n\toutput digging\n);\n\tparameter WL=0, WR=1, FALLL=2, FALLR=3, DIGL=4, DIGR=5;\n\treg [2:0] state;\n\treg [2:0] next;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tWL: if (!ground) next = FALLL;\n\t\t\t\telse if (dig) next = DIGL;\n\t\t\t\telse if (bump_left) next = WR;\n\t\t\t\telse next = WL;\n\t\t\tWR: \n\t\t\t\tif (!ground) next = FALLR;\n\t\t\t\telse if (dig) next = DIGR;\n\t\t\t\telse if (bump_right) next = WL;\n\t\t\t\telse next = WR;\n\t\t\tFALLL: next = ground ? WL : FALLL;\n\t\t\tFALLR: next = ground ? WR : FALLR;\n\t\t\tDIGL: next = ground ? DIGL : FALLL;\n\t\t\tDIGR: next = ground ? DIGR : FALLR;\n\t\tendcase\n    end\n    \n    always @(posedge clk, posedge areset) begin\n\t\tif (areset) state <= WL;\n        else state <= next;\n\tend\n\t\t\n\tassign walk_left = (state==WL);\n\tassign walk_right = (state==WR);\n\tassign aaah = (state == FALLL) || (state == FALLR);\n\tassign digging = (state == DIGL) || (state == DIGR);\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput areset,\n\tinput bump_left,\n\tinput bump_right,\n\tinput ground,\n\tinput dig,\n\toutput walk_left,\n\toutput walk_right,\n\toutput aaah,\n\toutput digging\n);\n\tparameter WL=0, WR=1, FALLL=2, FALLR=3, DIGL=4, DIGR=5;\n\treg [2:0] state;\n\treg [2:0] next;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tWL: if (!ground) next = FALLL;\n\t\t\t\telse if (dig) next = DIGL;\n\t\t\t\telse if (bump_left) next = WR;\n\t\t\t\telse next = WL;\n\t\t\tWR: \n\t\t\t\tif (!ground) next = FALLR;\n\t\t\t\telse if (dig) next = DIGR;\n\t\t\t\telse if (bump_right) next = WL;\n\t\t\t\telse next = WR;\n\t\t\tFALLL: next = ground ? WL : FALLL;\n\t\t\tFALLR: next = ground ? WR : FALLR;\n\t\t\tDIGL: next = ground ? DIGL : FALLL;\n\t\t\tDIGR: next = ground ? DIGR : FALLR;\n\t\tendcase\n    end\n    \n    always @(posedge clk, posedge areset) begin\n\t\tif (areset) state <= WL;\n        else state <= next;\n\tend\n\t\t\n\tassign walk_left = (state==WL);\n\tassign walk_right = (state==WR);\n\tassign aaah = (state == FALLL) || (state == FALLR);\n\tassign digging = (state == DIGL) || (state == DIGR);\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic areset,\n\toutput logic bump_left,\n\toutput logic bump_right,\n\toutput logic dig,\n\toutput logic ground,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\tinput tb_match\n);\n\treg reset;\n\tassign areset = reset;\n\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\twire [0:13][3:0] d = {\n\t\t4'h2,\n\t\t4'h2,\n\t\t4'h3,\n\t\t4'h2,\n\t\t4'ha,\n\t\t4'h2,\n\t\t4'h0,\n\t\t4'h0,\n\t\t4'h0,\n\t\t4'h3,\n\t\t4'h2,\n\t\t4'h2,\n\t\t4'h2,\n\t\t4'h2\n\t};\n\t\n\tinitial begin\n\t\treset <= 1'b1;\n\t\t{bump_left, bump_right, ground, dig} <= 4'h2;\n\t\treset_test(1);\n\n\t\treset <= 1'b1;\n\t\t@(posedge clk);\n\t\treset <= 0;\n\t\t\n\t\t@(negedge clk);\n\t\twavedrom_start(\"Digging\");\n\t\tfor (int i=0;i<14;i++)\n\t\t\t@(posedge clk) {bump_left, bump_right, ground, dig} <= d[i];\n\t\twavedrom_stop();\n\t\t\n\t\trepeat(400) @(posedge clk, negedge clk) begin\n\t\t\t{dig, bump_right, bump_left} <= $random & $random;\n\t\t\tground <= |($random & 7);\n\t\t\treset <= !($random & 31);\n\t\tend\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_walk_left;\n\t\tint errortime_walk_left;\n\t\tint errors_walk_right;\n\t\tint errortime_walk_right;\n\t\tint errors_aaah;\n\t\tint errortime_aaah;\n\t\tint errors_digging;\n\t\tint errortime_digging;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic areset;\n\tlogic bump_left;\n\tlogic bump_right;\n\tlogic ground;\n\tlogic dig;\n\tlogic walk_left_ref;\n\tlogic walk_left_dut;\n\tlogic walk_right_ref;\n\tlogic walk_right_dut;\n\tlogic aaah_ref;\n\tlogic aaah_dut;\n\tlogic digging_ref;\n\tlogic digging_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,areset,bump_left,bump_right,ground,dig,walk_left_ref,walk_left_dut,walk_right_ref,walk_right_dut,aaah_ref,aaah_dut,digging_ref,digging_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.areset,\n\t\t.bump_left,\n\t\t.bump_right,\n\t\t.ground,\n\t\t.dig );\n\treference_module good1 (\n\t\t.clk,\n\t\t.areset,\n\t\t.bump_left,\n\t\t.bump_right,\n\t\t.ground,\n\t\t.dig,\n\t\t.walk_left(walk_left_ref),\n\t\t.walk_right(walk_right_ref),\n\t\t.aaah(aaah_ref),\n\t\t.digging(digging_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.areset,\n\t\t.bump_left,\n\t\t.bump_right,\n\t\t.ground,\n\t\t.dig,\n\t\t.walk_left(walk_left_dut),\n\t\t.walk_right(walk_right_dut),\n\t\t.aaah(aaah_dut),\n\t\t.digging(digging_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_walk_left) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"walk_left\", stats1.errors_walk_left, stats1.errortime_walk_left);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"walk_left\");\n\t\tif (stats1.errors_walk_right) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"walk_right\", stats1.errors_walk_right, stats1.errortime_walk_right);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"walk_right\");\n\t\tif (stats1.errors_aaah) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"aaah\", stats1.errors_aaah, stats1.errortime_aaah);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"aaah\");\n\t\tif (stats1.errors_digging) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"digging\", stats1.errors_digging, stats1.errortime_digging);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"digging\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { walk_left_ref, walk_right_ref, aaah_ref, digging_ref } === ( { walk_left_ref, walk_right_ref, aaah_ref, digging_ref } ^ { walk_left_dut, walk_right_dut, aaah_dut, digging_dut } ^ { walk_left_ref, walk_right_ref, aaah_ref, digging_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (walk_left_ref !== ( walk_left_ref ^ walk_left_dut ^ walk_left_ref ))\n\t\tbegin if (stats1.errors_walk_left == 0) stats1.errortime_walk_left = $time;\n\t\t\tstats1.errors_walk_left = stats1.errors_walk_left+1'b1; end\n\t\tif (walk_right_ref !== ( walk_right_ref ^ walk_right_dut ^ walk_right_ref ))\n\t\tbegin if (stats1.errors_walk_right == 0) stats1.errortime_walk_right = $time;\n\t\t\tstats1.errors_walk_right = stats1.errors_walk_right+1'b1; end\n\t\tif (aaah_ref !== ( aaah_ref ^ aaah_dut ^ aaah_ref ))\n\t\tbegin if (stats1.errors_aaah == 0) stats1.errortime_aaah = $time;\n\t\t\tstats1.errors_aaah = stats1.errors_aaah+1'b1; end\n\t\tif (digging_ref !== ( digging_ref ^ digging_dut ^ digging_ref ))\n\t\tbegin if (stats1.errors_digging == 0) stats1.errortime_digging = $time;\n\t\t\tstats1.errors_digging = stats1.errors_digging+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "count_clock", "task_number": 154, "description": "Create a set of counters suitable for use as a 12-hour clock (with am/pm indicator). Your counters are clocked by a fast-running clk, with a pulse on ena whenever your clock should increment (i.e., once per second, while \"clk\" is much faster than once per second). The signal \"pm\" is asserted if the clock is PM, or is otherwise AM. hh, mm, and ss are two BCD (Binary-Coded Decimal) digits each for hours (01-12), minutes (00-59), and seconds (00-59). Reset is the active high synchronous signal that resets the clock to \"12:00 AM.\" Reset has higher priority than enable and can occur even when not enabled.", "header": "module top_module(\n\tinput clk,\n\tinput reset,\n\tinput ena,\n\toutput reg pm,\n\toutput reg [7:0] hh,\n\toutput reg [7:0] mm,\n\toutput reg [7:0] ss);\n", "module_code": "module top_module(\n\tinput clk,\n\tinput reset,\n\tinput ena,\n\toutput reg pm,\n\toutput reg [7:0] hh,\n\toutput reg [7:0] mm,\n\toutput reg [7:0] ss);\n\t\n\twire [6:0] enable = {\n\t\t{hh[7:0],mm[7:0],ss[7:0]}==24'h115959,\n\t\t{hh[3:0],mm[7:0],ss[7:0]}==20'h95959,\n\t\t{mm[7:0],ss[7:0]}==16'h5959,\n\t\t{mm[3:0],ss[7:0]}==12'h959,\n\t\tss[7:0]==8'h59, \n\t\tss[3:0] == 4'h9, \n\t\t1'b1};\n\n\talways @(posedge clk)\n\t\tif (reset)\n\t\t\t{pm,hh,mm,ss} <= 25'h0120000;\n\t\telse if (ena) begin\n\t\t\tif (enable[0] && ss[3:0] == 9) ss[3:0] <= 0;\n\t\t\telse if (enable[0]) ss[3:0] <= ss[3:0] + 1;\n\n\t\t\tif (enable[1] && ss[7:4] == 4'h5) ss[7:4] <= 0;\n\t\t\telse if (enable[1]) ss[7:4] <= ss[7:4] + 1;\n\t\t\t\n\t\t\tif (enable[2] && mm[3:0] == 9) mm[3:0] <= 0;\n\t\t\telse if (enable[2]) mm[3:0] <= mm[3:0] + 1;\n\n\t\t\tif (enable[3] && mm[7:4] == 4'h5) mm[7:4] <= 0;\n\t\t\telse if (enable[3]) mm[7:4] <= mm[7:4] + 1;\n\t\t\t\n\t\t\tif (enable[4] && hh[3:0] == 4'h9) hh[3:0] <= 0;\n\t\t\telse if (enable[4]) hh[3:0] <= hh[3:0] + 1;\n\n\t\t\tif (enable[4] && hh[7:0] == 8'h12) hh[7:0] <= 8'h1;\n\t\t\telse if (enable[5]) hh[7:4] <= hh[7:4] + 1;\n\t\t\t\n\t\t\tif (enable[6]) pm <= ~pm;\n\t\tend\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput clk,\n\tinput reset,\n\tinput ena,\n\toutput reg pm,\n\toutput reg [7:0] hh,\n\toutput reg [7:0] mm,\n\toutput reg [7:0] ss);\n\t\n\twire [6:0] enable = {\n\t\t{hh[7:0],mm[7:0],ss[7:0]}==24'h115959,\n\t\t{hh[3:0],mm[7:0],ss[7:0]}==20'h95959,\n\t\t{mm[7:0],ss[7:0]}==16'h5959,\n\t\t{mm[3:0],ss[7:0]}==12'h959,\n\t\tss[7:0]==8'h59, \n\t\tss[3:0] == 4'h9, \n\t\t1'b1};\n\n\talways @(posedge clk)\n\t\tif (reset)\n\t\t\t{pm,hh,mm,ss} <= 25'h0120000;\n\t\telse if (ena) begin\n\t\t\tif (enable[0] && ss[3:0] == 9) ss[3:0] <= 0;\n\t\t\telse if (enable[0]) ss[3:0] <= ss[3:0] + 1;\n\n\t\t\tif (enable[1] && ss[7:4] == 4'h5) ss[7:4] <= 0;\n\t\t\telse if (enable[1]) ss[7:4] <= ss[7:4] + 1;\n\t\t\t\n\t\t\tif (enable[2] && mm[3:0] == 9) mm[3:0] <= 0;\n\t\t\telse if (enable[2]) mm[3:0] <= mm[3:0] + 1;\n\n\t\t\tif (enable[3] && mm[7:4] == 4'h5) mm[7:4] <= 0;\n\t\t\telse if (enable[3]) mm[7:4] <= mm[7:4] + 1;\n\t\t\t\n\t\t\tif (enable[4] && hh[3:0] == 4'h9) hh[3:0] <= 0;\n\t\t\telse if (enable[4]) hh[3:0] <= hh[3:0] + 1;\n\n\t\t\tif (enable[4] && hh[7:0] == 8'h12) hh[7:0] <= 8'h1;\n\t\t\telse if (enable[5]) hh[7:4] <= hh[7:4] + 1;\n\t\t\t\n\t\t\tif (enable[6]) pm <= ~pm;\n\t\tend\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg reset,\n\toutput reg ena,\n\tinput [7:0] hh_dut, mm_dut, ss_dut,\n\tinput pm_dut,\n\tinput tb_match,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\n);\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\n\tlogic bcd_fail = 0;\n\tlogic reset_fail = 0;\n\t\n\talways @(posedge clk) begin\n\t\tif ((hh_dut[3:0] >= 4'ha) ||\n\t\t\t(hh_dut[7:4] >= 4'ha) ||\n\t\t\t(mm_dut[3:0] >= 4'ha) ||\n\t\t\t(mm_dut[7:4] >= 4'ha) ||\n\t\t\t(ss_dut[3:0] >= 4'ha) ||\n\t\t\t(ss_dut[7:4] >= 4'ha))\n\t\t\tbcd_fail <= 1'b1;\t\t\n\tend\n\t\n\tinitial begin\n\t\treset <= 1;\n\t\tena <= 1;\n\t\twavedrom_start(\"Reset and count to 10\");\n\t\treset_test();\n\t\trepeat(12) @(posedge clk);\n\t\twavedrom_stop();\n\t\tena <= 1'b1;\n\t\treset <= 1'b1;\n\t\t@(posedge clk);\n\t\t@(posedge clk)\n\t\t\tif (!tb_match) begin\n\t\t\t\t$display(\"Hint: Clock seems to reset to %02x:%02x:%02x %s (Should be 12:00:00 AM).\", hh_dut, mm_dut, ss_dut, pm_dut ? \"PM\": \"AM\");\n\t\t\t\treset_fail <= 1'b1;\n\t\t\tend\n\t\t\n\t\treset <= 1'b0;\n\t\t@(posedge clk);\n\t\t@(posedge clk);\n\t\t@(posedge clk);\n\t\tena <= 1'b0;\n\t\treset <= 1'b1;\n\t\t@(posedge clk);\n\t\t@(posedge clk)\n\t\t\tif (!tb_match && !reset_fail)\n\t\t\t\t$display(\"Hint: Reset has higher priority than enable and should occur even if not enabled.\");\n\t\t\n\t\t\n\t\trepeat(400) @(posedge clk, negedge clk) begin\n\t\t\treset <= !($random & 31);\n\t\t\tena <= !($random & 3);\n\t\tend\n\t\treset <= 1;\n\t\t@(posedge clk) begin\n\t\t\t{reset, ena} <= 2'b1;\n\t\tend\n\t\t\n\t\trepeat(55) @(posedge clk);\n\t\twavedrom_start(\"Minute roll-over\");\n\t\trepeat(10) @(posedge clk);\n\t\twavedrom_stop();\n\n\t\trepeat(3530) @(posedge clk);\n\t\twavedrom_start(\"Hour roll-over\");\n\t\trepeat(10) @(posedge clk);\n\t\twavedrom_stop();\n\n\n\t\trepeat(39590) @(posedge clk);\n\t\twavedrom_start(\"PM roll-over\");\n\t\trepeat(10) @(posedge clk);\n\t\twavedrom_stop();\n\t\t\n\t\trepeat(132745) @(posedge clk);\n\t\trepeat(50) @(posedge clk, negedge clk) begin\n\t\t\tena <= !($random & 7);\n\t\tend\n\t\treset <= 1'b1;\n\t\trepeat(5) @(posedge clk);\n\t\t\n\t\t\n\t\tif (bcd_fail)\n\t\t\t$display(\"Hint: Non-BCD values detected. Are you sure you're using two-digit BCD representation for hh, mm, and ss?\");\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_pm;\n\t\tint errortime_pm;\n\t\tint errors_hh;\n\t\tint errortime_hh;\n\t\tint errors_mm;\n\t\tint errortime_mm;\n\t\tint errors_ss;\n\t\tint errortime_ss;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic reset;\n\tlogic ena;\n\tlogic pm_ref;\n\tlogic pm_dut;\n\tlogic [7:0] hh_ref;\n\tlogic [7:0] hh_dut;\n\tlogic [7:0] mm_ref;\n\tlogic [7:0] mm_dut;\n\tlogic [7:0] ss_ref;\n\tlogic [7:0] ss_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,ena,pm_ref,pm_dut,hh_ref,hh_dut,mm_ref,mm_dut,ss_ref,ss_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.reset,\n\t\t.ena );\n\treference_module good1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.ena,\n\t\t.pm(pm_ref),\n\t\t.hh(hh_ref),\n\t\t.mm(mm_ref),\n\t\t.ss(ss_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.ena,\n\t\t.pm(pm_dut),\n\t\t.hh(hh_dut),\n\t\t.mm(mm_dut),\n\t\t.ss(ss_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_pm) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"pm\", stats1.errors_pm, stats1.errortime_pm);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"pm\");\n\t\tif (stats1.errors_hh) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"hh\", stats1.errors_hh, stats1.errortime_hh);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"hh\");\n\t\tif (stats1.errors_mm) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"mm\", stats1.errors_mm, stats1.errortime_mm);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"mm\");\n\t\tif (stats1.errors_ss) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"ss\", stats1.errors_ss, stats1.errortime_ss);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"ss\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { pm_ref, hh_ref, mm_ref, ss_ref } === ( { pm_ref, hh_ref, mm_ref, ss_ref } ^ { pm_dut, hh_dut, mm_dut, ss_dut } ^ { pm_ref, hh_ref, mm_ref, ss_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (pm_ref !== ( pm_ref ^ pm_dut ^ pm_ref ))\n\t\tbegin if (stats1.errors_pm == 0) stats1.errortime_pm = $time;\n\t\t\tstats1.errors_pm = stats1.errors_pm+1'b1; end\n\t\tif (hh_ref !== ( hh_ref ^ hh_dut ^ hh_ref ))\n\t\tbegin if (stats1.errors_hh == 0) stats1.errortime_hh = $time;\n\t\t\tstats1.errors_hh = stats1.errors_hh+1'b1; end\n\t\tif (mm_ref !== ( mm_ref ^ mm_dut ^ mm_ref ))\n\t\tbegin if (stats1.errors_mm == 0) stats1.errortime_mm = $time;\n\t\t\tstats1.errors_mm = stats1.errors_mm+1'b1; end\n\t\tif (ss_ref !== ( ss_ref ^ ss_dut ^ ss_ref ))\n\t\tbegin if (stats1.errors_ss == 0) stats1.errortime_ss = $time;\n\t\t\tstats1.errors_ss = stats1.errors_ss+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "lemmings2", "task_number": 155, "description": "The game Lemmings involves critters with fairly simple brains. So simple that we are going to model it using a finite state machine. In the Lemmings' 2D world, Lemmings can be in one of two states: walking left (walk_left is 1) or walking right (walk_right is 1). It will switch directions if it hits an obstacle. In particular, if a Lemming is bumped on the left (by receiving a 1 on bump_left), it will walk right. If it's bumped on the right (by receiving a 1 on bump_right), it will walk left. If it's bumped on both sides at the same time, it will still switch directions. \n// In addition to walking left and right and changing direction when bumped, when ground=0, the Lemming will fall and say \"aaah!\". When the ground reappears (ground=1), the Lemming will resume walking in the same direction as before the fall. Being bumped while falling does not affect the walking direction, and being bumped in the same cycle as ground disappears (but not yet falling), or when the ground reappears while still falling, also does not affect the walking direction.\n// Implement a Moore state machine that models this behaviour. areset is positive edge triggered asynchronous reseting the Lemming machine to walk left.", "header": "module top_module (\n\tinput clk,\n\tinput areset,\n\tinput bump_left,\n\tinput bump_right,\n\tinput ground,\n\toutput walk_left,\n\toutput walk_right,\n\toutput aaah\n);\n", "module_code": "module top_module (\n\tinput clk,\n\tinput areset,\n\tinput bump_left,\n\tinput bump_right,\n\tinput ground,\n\toutput walk_left,\n\toutput walk_right,\n\toutput aaah\n);\n\tparameter WL=0, WR=1, FALLL=2, FALLR=3;\n\treg [1:0] state;\n\treg [1:0] next;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tWL: next = ground ? (bump_left ? WR : WL) : FALLL;\n\t\t\tWR: next = ground ? (bump_right ? WL: WR) : FALLR;\n\t\t\tFALLL: next = ground ? WL : FALLL;\n\t\t\tFALLR: next = ground ? WR : FALLR;\n\t\tendcase\n    end\n    \n    always @(posedge clk, posedge areset) begin\n\t\tif (areset) state <= WL;\n        else state <= next;\n\tend\n\t\t\n\tassign walk_left = (state==WL);\n\tassign walk_right = (state==WR);\n\tassign aaah = (state == FALLL) || (state == FALLR);\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput areset,\n\tinput bump_left,\n\tinput bump_right,\n\tinput ground,\n\toutput walk_left,\n\toutput walk_right,\n\toutput aaah\n);\n\tparameter WL=0, WR=1, FALLL=2, FALLR=3;\n\treg [1:0] state;\n\treg [1:0] next;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tWL: next = ground ? (bump_left ? WR : WL) : FALLL;\n\t\t\tWR: next = ground ? (bump_right ? WL: WR) : FALLR;\n\t\t\tFALLL: next = ground ? WL : FALLL;\n\t\t\tFALLR: next = ground ? WR : FALLR;\n\t\tendcase\n    end\n    \n    always @(posedge clk, posedge areset) begin\n\t\tif (areset) state <= WL;\n        else state <= next;\n\tend\n\t\t\n\tassign walk_left = (state==WL);\n\tassign walk_right = (state==WR);\n\tassign aaah = (state == FALLL) || (state == FALLR);\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic areset,\n\toutput logic bump_left,\n\toutput logic bump_right,\n\toutput logic ground,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\tinput tb_match\n);\n\treg reset;\n\tassign areset = reset;\n\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\tinitial begin\n\t\treset <= 1'b1;\n\t\t{bump_left, bump_right, ground} <= 3'h1;\n\t\treset_test(1);\n\t\t{bump_right, bump_left} <= 3'h0;\n\t\twavedrom_start(\"Falling\");\n\t\trepeat(3) @(posedge clk);\n\t\t{bump_right, bump_left, ground} <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\t{bump_right, bump_left, ground} <= 3;\n\t\trepeat(2) @(posedge clk);\n\t\t{bump_right, bump_left, ground} <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\t{bump_right, bump_left, ground} <= 1;\n\t\trepeat(2) @(posedge clk);\n\t\twavedrom_stop();\n\t\t\t\n\t\treset <= 1'b1;\n\t\t@(posedge clk);\n\t\trepeat(400) @(posedge clk, negedge clk) begin\n\t\t\t{bump_right, bump_left} <= $random & $random;\n\t\t\tground <= |($random & 7);\n\t\t\treset <= !($random & 31);\n\t\tend\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_walk_left;\n\t\tint errortime_walk_left;\n\t\tint errors_walk_right;\n\t\tint errortime_walk_right;\n\t\tint errors_aaah;\n\t\tint errortime_aaah;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic areset;\n\tlogic bump_left;\n\tlogic bump_right;\n\tlogic ground;\n\tlogic walk_left_ref;\n\tlogic walk_left_dut;\n\tlogic walk_right_ref;\n\tlogic walk_right_dut;\n\tlogic aaah_ref;\n\tlogic aaah_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,areset,bump_left,bump_right,ground,walk_left_ref,walk_left_dut,walk_right_ref,walk_right_dut,aaah_ref,aaah_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.areset,\n\t\t.bump_left,\n\t\t.bump_right,\n\t\t.ground );\n\treference_module good1 (\n\t\t.clk,\n\t\t.areset,\n\t\t.bump_left,\n\t\t.bump_right,\n\t\t.ground,\n\t\t.walk_left(walk_left_ref),\n\t\t.walk_right(walk_right_ref),\n\t\t.aaah(aaah_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.areset,\n\t\t.bump_left,\n\t\t.bump_right,\n\t\t.ground,\n\t\t.walk_left(walk_left_dut),\n\t\t.walk_right(walk_right_dut),\n\t\t.aaah(aaah_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_walk_left) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"walk_left\", stats1.errors_walk_left, stats1.errortime_walk_left);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"walk_left\");\n\t\tif (stats1.errors_walk_right) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"walk_right\", stats1.errors_walk_right, stats1.errortime_walk_right);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"walk_right\");\n\t\tif (stats1.errors_aaah) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"aaah\", stats1.errors_aaah, stats1.errortime_aaah);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"aaah\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { walk_left_ref, walk_right_ref, aaah_ref } === ( { walk_left_ref, walk_right_ref, aaah_ref } ^ { walk_left_dut, walk_right_dut, aaah_dut } ^ { walk_left_ref, walk_right_ref, aaah_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (walk_left_ref !== ( walk_left_ref ^ walk_left_dut ^ walk_left_ref ))\n\t\tbegin if (stats1.errors_walk_left == 0) stats1.errortime_walk_left = $time;\n\t\t\tstats1.errors_walk_left = stats1.errors_walk_left+1'b1; end\n\t\tif (walk_right_ref !== ( walk_right_ref ^ walk_right_dut ^ walk_right_ref ))\n\t\tbegin if (stats1.errors_walk_right == 0) stats1.errortime_walk_right = $time;\n\t\t\tstats1.errors_walk_right = stats1.errors_walk_right+1'b1; end\n\t\tif (aaah_ref !== ( aaah_ref ^ aaah_dut ^ aaah_ref ))\n\t\tbegin if (stats1.errors_aaah == 0) stats1.errortime_aaah = $time;\n\t\t\tstats1.errors_aaah = stats1.errors_aaah+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "countbcd", "task_number": 156, "description": "Build a 4-digit BCD (binary-coded decimal) counter. Each decimal digit is encoded using 4 bits: q[3:0] is the ones digit, q[7:4] is the tens digit, etc. For digits [3:1], also output an enable signal indicating when each of the upper three digits should be incremented. Include a synchronous active-high reset.", "header": "module top_module(\n\tinput clk,\n\tinput reset,\n\toutput [3:1] ena,\n\toutput reg [15:0] q);\n", "module_code": "module top_module(\n\tinput clk,\n\tinput reset,\n\toutput [3:1] ena,\n\toutput reg [15:0] q);\n\t\n\twire [3:0] enable = { q[11:0]==12'h999, q[7:0]==8'h99, q[3:0] == 4'h9, 1'b1};\n\tassign ena = enable[3:1];\n\talways @(posedge clk)\n\t\tfor (int i=0;i<4;i++) begin\n\t\t\tif (reset || (q[i*4 +:4] == 9 && enable[i]))\n\t\t\t\tq[i*4 +:4] <= 0;\n\t\t\telse if (enable[i])\n\t\t\t\tq[i*4 +:4] <= q[i*4 +:4]+1;\n\t\tend\n\t\nendmodule\n", "testbench": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput clk,\n\tinput reset,\n\toutput [3:1] ena,\n\toutput reg [15:0] q);\n\t\n\twire [3:0] enable = { q[11:0]==12'h999, q[7:0]==8'h99, q[3:0] == 4'h9, 1'b1};\n\tassign ena = enable[3:1];\n\talways @(posedge clk)\n\t\tfor (int i=0;i<4;i++) begin\n\t\t\tif (reset || (q[i*4 +:4] == 9 && enable[i]))\n\t\t\t\tq[i*4 +:4] <= 0;\n\t\t\telse if (enable[i])\n\t\t\t\tq[i*4 +:4] <= q[i*4 +:4]+1;\n\t\tend\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg reset,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\tinput tb_match\n);\n\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\tinitial begin\n\t\treset <= 1;\n\t\treset_test();\n\t\trepeat(2) @(posedge clk);\n\t\t@(negedge clk);\n\t\twavedrom_start(\"Counting\");\n\t\t\trepeat(12) @(posedge clk);\n\t\t@(negedge clk);\n\t\twavedrom_stop();\n\t\trepeat(71) @(posedge clk);\n\t\t@(negedge clk) wavedrom_start(\"100 rollover\");\n\t\t\trepeat(16) @(posedge clk);\n\t\t@(negedge clk) wavedrom_stop();\n\t\trepeat(400) @(posedge clk, negedge clk)\n\t\t\treset <= !($random & 31);\n\t\trepeat(19590) @(posedge clk);\n\t\treset <= 1'b1;\n\t\trepeat(5) @(posedge clk);\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_ena;\n\t\tint errortime_ena;\n\t\tint errors_q;\n\t\tint errortime_q;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic reset;\n\tlogic [3:1] ena_ref;\n\tlogic [3:1] ena_dut;\n\tlogic [15:0] q_ref;\n\tlogic [15:0] q_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,ena_ref,ena_dut,q_ref,q_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.reset );\n\treference_module good1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.ena(ena_ref),\n\t\t.q(q_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.ena(ena_dut),\n\t\t.q(q_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_ena) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"ena\", stats1.errors_ena, stats1.errortime_ena);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"ena\");\n\t\tif (stats1.errors_q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"q\", stats1.errors_q, stats1.errortime_q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"q\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { ena_ref, q_ref } === ( { ena_ref, q_ref } ^ { ena_dut, q_dut } ^ { ena_ref, q_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (ena_ref !== ( ena_ref ^ ena_dut ^ ena_ref ))\n\t\tbegin if (stats1.errors_ena == 0) stats1.errortime_ena = $time;\n\t\t\tstats1.errors_ena = stats1.errors_ena+1'b1; end\n\t\tif (q_ref !== ( q_ref ^ q_dut ^ q_ref ))\n\t\tbegin if (stats1.errors_q == 0) stats1.errortime_q = $time;\n\t\t\tstats1.errors_q = stats1.errors_q+1'b1; end\n\n\tend\nendmodule\n"}