Question: Synopsys, an American company, is the leading company by sales in the Electronic Desing Automation industry. OpenVera is a hardware verification language developed and managed by Synopsys, what is Synopsys' first and best known product?

Context articles: OpenVera
JEDA Technologies
ERM (e Reuse Methodology)
Rajeev Madhavan
Universal Verification Methodology
SystemVerilog
Synopsys
Hardware verification language
Specman
E (verification language)

OpenVera is a hardware verification language developed and managed by Synopsys.
JEDA Technologies, Inc. (“JEDA”) is a provider of software products in the front-end of electronic design automation (EDA) industry, specifically in electronic system-level (ESL) verification automation.
 JEDA products are applied to design models written in C, C++, SystemC for quality measurement, checking and improvement.
 The company is headquartered in Santa Clara, California with R&D offices in China.
The e Reuse Methodology was the first reuse methodology to emerge in the Hardware Verification Language space and was used in conjunction with the e Hardware Verification Language.
 It was invented in 2001 by Verisity Design and was released in 2002.
 The methodology was composed of methodology guidelines for such topics as:
Rajeev Madhavan is a serial entrepreneur and investor, and a founder and General Partner of Clear Ventures.
 He is perhaps best known as the founder of software company Magma Design Automation, where he served as chairman and chief executive officer from its founding in 1997 through its acquisition by Synopsys in 2012.
 He also co-founded software companies LogicVision (acquired by Mentor Graphics) and Ambit Design Systems (acquired by Cadence Design Systems). "
Red Herring" magazine named Madhavan to its “Top Innovators” list in 2002.
The Universal Verification Methodology (UVM) is a standardized methodology for verifying integrated circuit designs.
 UVM is derived mainly from the OVM (Open Verification Methodology) which was, to a large part, based on the eRM (e Reuse Methodology) for the e Verification Language developed by Verisity Design in 2001.
 The UVM class library brings much automation to the SystemVerilog language such as sequences and data automation features (packing, copy, compare) etc., and unlike the previous methodologies developed independently by the simulator vendors, is an Accellera standard with support from multiple vendors: Aldec, Cadence, Mentor Graphics, and Synopsys.
In the semiconductor and electronic design industry, SystemVerilog is a combined hardware description language and hardware verification language based on extensions to Verilog.
Synopsys, Inc., an American company, is the leading company by sales in the Electronic Design Automation industry.
 Synopsys' first and best-known product is Design Compiler, a logic-synthesis tool.
 Synopsys offers a wide range of other products used in the design of an application-specific integrated circuit.
 Products include logic synthesis, behavioral synthesis, place and route, static timing analysis, formal verification, hardware description language (SystemC, SystemVerilog/Verilog, VHDL) simulators as well as transistor-level circuit simulation.
 The simulators include development and debugging environments which assist in the design of the logic for chips and computer systems.
A hardware verification language, or HVL, is a programming language used to verify the designs of electronic circuits written in a hardware description language.
 HVLs typically include features of a high-level programming language like C++ or Java as well as features for easy bit-level manipulation similar to those found in HDLs.
 Many HVLs will provide constrained random stimulus generation, and functional coverage constructs to assist with complex hardware verification.
Specman is an EDA tool that provides advanced automated functional verification of hardware designs.
 It provides an environment for working with, compiling, and debugging testbench environments written in the "e" Hardware Verification Language.
 Specman also offers automated testbench generation to boost productivity in the context of block, chip, and system verification.
e is a hardware verification language (HVL) which is tailored to implementing highly flexible and reusable verification testbenches.