/*
 * Defines, structures, APIs for edac_core module
 *
 * (C) 2007 Linux Networx (http://lnxi.com)
 * This file may be distributed under the terms of the
 * GNU General Public License.
 *
 * Written by Thayne Harbaugh
 * Based on work by Dan Hollis <goemon at anime dot net> and others.
 *	http://www.anime.net/~goemon/linux-ecc/
 *
 * NMI handling support added by
 *     Dave Peterson <dsp@llnl.gov> <dave_peterson@pobox.com>
 *
 * Refactored for multi-source files:
 *	Doug Thompson <norsk5@xmission.com>
 *
 */

#ifndef _EDAC_CORE_H_
#define _EDAC_CORE_H_

#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/module.h>
#include <linux/spinlock.h>
#include <linux/smp.h>
#include <linux/pci.h>
#include <linux/time.h>
#include <linux/nmi.h>
#include <linux/rcupdate.h>
#include <linux/completion.h>
#include <linux/kobject.h>
#include <linux/platform_device.h>
#include <linux/sysdev.h>
#include <linux/workqueue.h>

#define EDAC_MC_LABEL_LEN	31
#define EDAC_DEVICE_NAME_LEN	31
#define EDAC_ATTRIB_VALUE_LEN	15
#define MC_PROC_NAME_MAX_LEN	7

#if PAGE_SHIFT < 20
#define PAGES_TO_MiB( pages )	( ( pages ) >> ( 20 - PAGE_SHIFT ) )
#else				/* PAGE_SHIFT > 20 */
#define PAGES_TO_MiB( pages )	( ( pages ) << ( PAGE_SHIFT - 20 ) )
#endif

#define edac_printk(level, prefix, fmt, arg...) \
	printk(level "EDAC " prefix ": " fmt, ##arg)

#define edac_mc_printk(mci, level, fmt, arg...) \
	printk(level "EDAC MC%d: " fmt, mci->mc_idx, ##arg)

#define edac_mc_chipset_printk(mci, level, prefix, fmt, arg...) \
	printk(level "EDAC " prefix " MC%d: " fmt, mci->mc_idx, ##arg)

#define edac_device_printk(ctl, level, fmt, arg...) \
	printk(level "EDAC DEVICE%d: " fmt, ctl->dev_idx, ##arg)

#define edac_pci_printk(ctl, level, fmt, arg...) \
	printk(level "EDAC PCI%d: " fmt, ctl->pci_idx, ##arg)

/* prefixes for edac_printk() and edac_mc_printk() */
#define EDAC_MC "MC"
#define EDAC_PCI "PCI"
#define EDAC_DEBUG "DEBUG"

#ifdef CONFIG_EDAC_DEBUG
extern int edac_debug_level;
extern const char *edac_mem_types[];

#define edac_debug_printk(level, fmt, arg...)                           \
	do {                                                            \
		if (level <= edac_debug_level)                          \
			edac_printk(KERN_DEBUG, EDAC_DEBUG,		\
				    "%s: " fmt, __func__, ##arg);	\
	} while (0)

#define debugf0( ... ) edac_debug_printk(0, __VA_ARGS__ )
#define debugf1( ... ) edac_debug_printk(1, __VA_ARGS__ )
#define debugf2( ... ) edac_debug_printk(2, __VA_ARGS__ )
#define debugf3( ... ) edac_debug_printk(3, __VA_ARGS__ )
#define debugf4( ... ) edac_debug_printk(4, __VA_ARGS__ )

#else				/* !CONFIG_EDAC_DEBUG */

#define debugf0( ... )
#define debugf1( ... )
#define debugf2( ... )
#define debugf3( ... )
#define debugf4( ... )

#endif				/* !CONFIG_EDAC_DEBUG */

#define PCI_VEND_DEV(vend, dev) PCI_VENDOR_ID_ ## vend, \
	PCI_DEVICE_ID_ ## vend ## _ ## dev

#define edac_dev_name(dev) (dev)->dev_name

/* memory devices */
enum dev_type {
	DEV_UNKNOWN = 0,
	DEV_X1,
	DEV_X2,
	DEV_X4,
	DEV_X8,
	DEV_X16,
	DEV_X32,		/* Do these parts exist? */
	DEV_X64			/* Do these parts exist? */
};

#define DEV_FLAG_UNKNOWN	BIT(DEV_UNKNOWN)
#define DEV_FLAG_X1		BIT(DEV_X1)
#define DEV_FLAG_X2		BIT(DEV_X2)
#define DEV_FLAG_X4		BIT(DEV_X4)
#define DEV_FLAG_X8		BIT(DEV_X8)
#define DEV_FLAG_X16		BIT(DEV_X16)
#define DEV_FLAG_X32		BIT(DEV_X32)
#define DEV_FLAG_X64		BIT(DEV_X64)

/* memory types */
enum mem_type {
	MEM_EMPTY = 0,		/* Empty csrow */
	MEM_RESERVED,		/* Reserved csrow type */
	MEM_UNKNOWN,		/* Unknown csrow type */
	MEM_FPM,		/* Fast page mode */
	MEM_EDO,		/* Extended data out */
	MEM_BEDO,		/* Burst Extended data out */
	MEM_SDR,		/* Single data rate SDRAM */
	MEM_RDR,		/* Registered single data rate SDRAM */
	MEM_DDR,		/* Double data rate SDRAM */
	MEM_RDDR,		/* Registered Double data rate SDRAM */
	MEM_RMBS,		/* Rambus DRAM */
	MEM_DDR2,		/* DDR2 RAM */
	MEM_FB_DDR2,		/* fully buffered DDR2 */
	MEM_RDDR2,		/* Registered DDR2 RAM */
	MEM_XDR,		/* Rambus XDR */
	MEM_DDR3,		/* DDR3 RAM */
	MEM_RDDR3,		/* Registered DDR3 RAM */
};

#define MEM_FLAG_EMPTY		BIT(MEM_EMPTY)
#define MEM_FLAG_RESERVED	BIT(MEM_RESERVED)
#define MEM_FLAG_UNKNOWN	BIT(MEM_UNKNOWN)
#define MEM_FLAG_FPM		BIT(MEM_FPM)
#define MEM_FLAG_EDO		BIT(MEM_EDO)
#define MEM_FLAG_BEDO		BIT(MEM_BEDO)
#define MEM_FLAG_SDR		BIT(MEM_SDR)
#define MEM_FLAG_RDR		BIT(MEM_RDR)
#define MEM_FLAG_DDR		BIT(MEM_DDR)
#define MEM_FLAG_RDDR		BIT(MEM_RDDR)
#define MEM_FLAG_RMBS		BIT(MEM_RMBS)
#define MEM_FLAG_DDR2           BIT(MEM_DDR2)
#define MEM_FLAG_FB_DDR2        BIT(MEM_FB_DDR2)
#define MEM_FLAG_RDDR2          BIT(MEM_RDDR2)
#define MEM_FLAG_XDR            BIT(MEM_XDR)
#define MEM_FLAG_DDR3		 BIT(MEM_DDR3)
#define MEM_FLAG_RDDR3		 BIT(MEM_RDDR3)

/* chipset Error Detection and Correction capabilities and mode */
enum edac_type {
	EDAC_UNKNOWN = 0,	/* Unknown if ECC is available */
	EDAC_NONE,		/* Doesnt support ECC */
	EDAC_RESERVED,		/* Reserved ECC type */
	EDAC_PARITY,		/* Detects parity errors */
	EDAC_EC,		/* Error Checking - no correction */
	EDAC_SECDED,		/* Single bit error correction, Double detection */
	EDAC_S2ECD2ED,		/* Chipkill x2 devices - do these exist? */
	EDAC_S4ECD4ED,		/* Chipkill x4 devices */
	EDAC_S8ECD8ED,		/* Chipkill x8 devices */
	EDAC_S16ECD16ED,	/* Chipkill x16 devices */
};

#define EDAC_FLAG_UNKNOWN	BIT(EDAC_UNKNOWN)
#define EDAC_FLAG_NONE		BIT(EDAC_NONE)
#define EDAC_FLAG_PARITY	BIT(EDAC_PARITY)
#define EDAC_FLAG_EC		BIT(EDAC_EC)
#define EDAC_FLAG_SECDED	BIT(EDAC_SECDED)
#define EDAC_FLAG_S2ECD2ED	BIT(EDAC_S2ECD2ED)
#define EDAC_FLAG_S4ECD4ED	BIT(EDAC_S4ECD4ED)
#define EDAC_FLAG_S8ECD8ED	BIT(EDAC_S8ECD8ED)
#define EDAC_FLAG_S16ECD16ED	BIT(EDAC_S16ECD16ED)

/* scrubbing capabilities */
enum scrub_type {
	SCRUB_UNKNOWN = 0,	/* Unknown if scrubber is available */
	SCRUB_NONE,		/* No scrubber */
	SCRUB_SW_PROG,		/* SW progressive (sequential) scrubbing */
	SCRUB_SW_SRC,		/* Software scrub only errors */
	SCRUB_SW_PROG_SRC,	/* Progressive software scrub from an error */
	SCRUB_SW_TUNABLE,	/* Software scrub frequency is tunable */
	SCRUB_HW_PROG,		/* HW progressive (sequential) scrubbing */
	SCRUB_HW_SRC,		/* Hardware scrub only errors */
	SCRUB_HW_PROG_SRC,	/* Progressive hardware scrub from an error */
	SCRUB_HW_TUNABLE	/* Hardware scrub frequency is tunable */
};

#define SCRUB_FLAG_SW_PROG	BIT(SCRUB_SW_PROG)
#define SCRUB_FLAG_SW_SRC	BIT(SCRUB_SW_SRC)
#define SCRUB_FLAG_SW_PROG_SRC	BIT(SCRUB_SW_PROG_SRC)
#define SCRUB_FLAG_SW_TUN	BIT(SCRUB_SW_SCRUB_TUNABLE)
#define SCRUB_FLAG_HW_PROG	BIT(SCRUB_HW_PROG)
#define SCRUB_FLAG_HW_SRC	BIT(SCRUB_HW_SRC)
#define SCRUB_FLAG_HW_PROG_SRC	BIT(SCRUB_HW_PROG_SRC)
#define SCRUB_FLAG_HW_TUN	BIT(SCRUB_HW_TUNABLE)

/* EDAC internal operation states */
#define	OP_ALLOC		0x100
#define OP_RUNNING_POLL		0x201
#define OP_RUNNING_INTERRUPT	0x202
#define OP_RUNNING_POLL_INTR	0x203
#define OP_OFFLINE		0x300

/*
 * There are several things to be aware of that aren't at all obvious:
 *
 *
 * SOCKETS, SOCKET SETS, BANKS, ROWS, CHIP-SELECT ROWS, CHANNELS, etc..
 *
 * These are some of the many terms that are thrown about that don't always
 * mean what people think they mean (Inconceivable!).  In the interest of
 * creating a common ground for discussion, terms and their definitions
 * will be established.
 *
 * Memory devices:	The individual chip on a memory stick.  These devices
 *			commonly output 4 and 8 bits each.  Grouping several
 *			of these in parallel provides 64 bits which is common
 *			for a memory stick.
 *
 * Memory Stick:	A printed circuit board that agregates multiple
 *			memory devices in parallel.  This is the atomic
 *			memory component that is purchaseable by Joe consumer
 *			and loaded into a memory socket.
 *
 * Socket:		A physical connector on the motherboard that accepts
 *			a single memory stick.
 *
 * Channel:		Set of memory devices on a memory stick that must be
 *			grouped in parallel with one or more additional
 *			channels from other memory sticks.  This parallel
 *			grouping of the output from multiple channels are
 *			necessary for the smallest granularity of memory access.
 *			Some memory controllers are capable of single channel -
 *			which means that memory sticks can be loaded
 *			individually.  Other memory controllers are only
 *			capable of dual channel - which means that memory
 *			sticks must be loaded as pairs (see "socket set").
 *
 * Chip-select row:	All of the memory devices that are selected together.
 *			for a single, minimum grain of memory access.
 *			This selects all of the parallel memory devices across
 *			all of the parallel channels.  Common chip-select rows
 *			for single channel are 64 bits, for dual channel 128
 *			bits.
 *
 * Single-Ranked stick:	A Single-ranked stick has 1 chip-select row of memmory.
 *			Motherboards commonly drive two chip-select pins to
 *			a memory stick. A single-ranked stick, will occupy
 *			only one of those rows. The other will be unused.
 *
 * Double-Ranked stick:	A double-ranked stick has two chip-select rows which
 *			access different sets of memory devices.  The two
 *			rows cannot be accessed concurrently.
 *
 * Double-sided stick:	DEPRECATED TERM, see Double-Ranked stick.
 *			A double-sided stick has two chip-select rows which
 *			access different sets of memory devices.  The two
 *			rows cannot be accessed concurrently.  "Double-sided"
 *			is irrespective of the memory devices being mounted
 *			on both sides of the memory stick.
 *
 * Socket set:		All of the memory sticks that are required for
 *			a single memory access or all of the memory sticks
 *			spanned by a chip-select row.  A single socket set
 *			has two chip-select rows and if double-sided sticks
 *			are used these will occupy those chip-select rows.
 *
 * Bank:		This term is avoided because it is unclear when
 *			needing to distinguish between chip-select rows and
 *			socket sets.
 *
 * Controller pages:
 *
 * Physical pages:
 *
 * Virtual pages:
 *
 *
 * STRUCTURE ORGANIZATION AND CHOICES
 *
 *
 *
 * PS - I enjoyed writing all that about as much as you enjoyed reading it.
 */

struct channel_info {
	int chan_idx;		/* channel index */
	u32 ce_count;		/* Correctable Errors for this CHANNEL */
	char label[EDAC_MC_LABEL_LEN + 1];	/* DIMM label on motherboard */
	struct csrow_info *csrow;	/* the parent */
};

struct csrow_info {
	unsigned long first_page;	/* first page number in dimm */
	unsigned long last_page;	/* last page number in dimm */
	unsigned long page_mask;	/* used for interleaving -
					 * 0UL for non intlv
					 */
	u32 nr_pages;		/* number of pages in csrow */
	u32 grain;		/* granularity of reported error in bytes */
	int csrow_idx;		/* the chip-select row */
	enum dev_type dtype;	/* memory device type */
	u32 ue_count;		/* Uncorrectable Errors for this csrow */
	u32 ce_count;		/* Correctable Errors for this csrow */
	enum mem_type mtype;	/* memory csrow type */
	enum edac_type edac_mode;	/* EDAC mode for this csrow */
	struct mem_ctl_info *mci;	/* the parent */

	struct kobject kobj;	/* sysfs kobject for this csrow */

	/* channel information for this csrow */
	u32 nr_channels;
	struct channel_info *channels;
};

struct mcidev_sysfs_group {
	const char *name;				/* group name */
	struct mcidev_sysfs_attribute *mcidev_attr;	/* group attributes */
};

struct mcidev_sysfs_group_kobj {
	struct list_head list;		/* list for all instances within a mc */

	struct kobject kobj;		/* kobj for the group */

	struct mcidev_sysfs_group *grp;	/* group description table */
	struct mem_ctl_info *mci;	/* the parent */
};

/* mcidev_sysfs_attribute structure
 *	used for driver sysfs attributes and in mem_ctl_info
 * 	sysfs top level entries
 */
struct mcidev_sysfs_attribute {
	/* It should use either attr or grp */
	struct attribute attr;
	struct mcidev_sysfs_group *grp;	/* Points to a group of attributes */

	/* Ops for show/store values at the attribute - not used on group */
        ssize_t (*show)(struct mem_ctl_info *,char *);
        ssize_t (*store)(struct mem_ctl_info *, const char *,size_t);
};

/* MEMORY controller information structure
 */
struct mem_ctl_info {
	struct list_head link;	/* for global list of mem_ctl_info structs */

	struct module *owner;	/* Module owner of this control struct */

	unsigned long mtype_cap;	/* memory types supported by mc */
	unsigned long edac_ctl_cap;	/* Mem controller EDAC capabilities */
	unsigned long edac_cap;	/* configuration capabilities - this is
				 * closely related to edac_ctl_cap.  The
				 * difference is that the controller may be
				 * capable of s4ecd4ed which would be listed
				 * in edac_ctl_cap, but if channels aren't
				 * capable of s4ecd4ed then the edac_cap would
				 * not have that capability.
				 */
	unsigned long scrub_cap;	/* chipset scrub capabilities */
	enum scrub_type scrub_mode;	/* current scrub mode */

	/* Translates sdram memory scrub rate given in bytes/sec to the
	   internal representation and configures whatever else needs
	   to be configured.
	 */
	int (*set_sdram_scrub_rate) (struct mem_ctl_info * mci, u32 bw);

	/* Get the current sdram memory scrub rate from the internal
	   representation and converts it to the closest matching
	   bandwith in bytes/sec.
	 */
	int (*get_sdram_scrub_rate) (struct mem_ctl_info * mci, u32 * bw);

	/* pointer to edac checking routine */
	void (*edac_check) (struct mem_ctl_info * mci);

	/*
	 * Remaps memory pages: controller pages to physical pages.
	 * For most MC's, this will be NULL.
	 */
	unsigned long (*ctl_page_to_phys) (struct mem_ctl_info * mci,
					   unsigned long page);
	int mc_idx;
	int nr_csrows;
	struct csrow_info *csrows;
	struct device *dev;
	const char *mod_name;
	const char *mod_ver;
	const char *ctl_name;
	const char *dev_name;
	char proc_name[MC_PROC_NAME_MAX_LEN + 1];
	void *pvt_info;
	u32 ue_noinfo_count;	/* Uncorrectable Errors w/o info */
	u32 ce_noinfo_count;	/* Correctable Errors w/o info */
	u32 ue_count;		/* Total Uncorrectable Errors for this MC */
	u32 ce_count;		/* Total Correctable Errors for this MC */
	unsigned long start_time;	/* mci load start time (in jiffies) */

	/* this stuff is for safe removal of mc devices from global list while
	 * NMI handlers may be traversing list
	 */
	struct rcu_head rcu;
	struct completion complete;

	/* edac sysfs device control */
	struct kobject edac_mci_kobj;

	/* list for all grp instances within a mc */
	struct list_head grp_kobj_list;

	/* Additional top controller level attributes, but specified
	 * by the low level driver.
	 *
	 * Set by the low level driver to provide attributes at the
	 * controller level, same level as 'ue_count' and 'ce_count' above.
	 * An array of structures, NULL terminated
	 *
	 * If attributes are desired, then set to array of attributes
	 * If no attributes are desired, leave NULL
	 */
	struct mcidev_sysfs_attribute *mc_driver_sysfs_attributes;

	/* work struct for this MC */
	struct delayed_work work;

	/* the internal state of this controller instance */
	int op_state;
};

/*
 * The following are the structures to provide for a generic
 * or abstract 'edac_device'. This set of structures and the
 * code that implements the APIs for the same, provide for
 * registering EDAC type devices which are NOT standard memory.
 *
 * CPU caches (L1 and L2)
 * DMA engines
 * Core CPU swithces
 * Fabric switch units
 * PCIe interface controllers
 * other EDAC/ECC type devices that can be monitored for
 * errors, etc.
 *
 * It allows for a 2 level set of hiearchry. For example:
 *
 * cache could be composed of L1, L2 and L3 levels of cache.
 * Each CPU core would have its own L1 cache, while sharing
 * L2 and maybe L3 caches.
 *
 * View them arranged, via the sysfs presentation:
 * /sys/devices/system/edac/..
 *
 *	mc/		<existing memory device directory>
 *	cpu/cpu0/..	<L1 and L2 block directory>
 *		/L1-cache/ce_count
 *			 /ue_count
 *		/L2-cache/ce_count
 *			 /ue_count
 *	cpu/cpu1/..	<L1 and L2 block directory>
 *		/L1-cache/ce_count
 *			 /ue_count
 *		/L2-cache/ce_count
 *			 /ue_count
 *	...
 *
 *	the L1 and L2 directories would be "edac_device_block's"
 */

struct edac_device_counter {
	u32 ue_count;
	u32 ce_count;
};

/* forward reference */
struct edac_device_ctl_info;
struct edac_device_block;

/* edac_dev_sysfs_attribute structure
 *	used for driver sysfs attributes in mem_ctl_info
 *	for extra controls and attributes:
 *		like high level error Injection controls
 */
struct edac_dev_sysfs_attribute {
	struct attribute attr;
	ssize_t (*show)(struct edac_device_ctl_info *, char *);
	ssize_t (*store)(struct edac_device_ctl_info *, const char *, size_t);
};

/* edac_dev_sysfs_block_attribute structure
 *
 *	used in leaf 'block' nodes for adding controls/attributes
 *
 *	each block in each instance of the containing control structure
 *	can have an array of the following. The show and store functions
 *	will be filled in with the show/store function in the
 *	low level driver.
 *
 *	The 'value' field will be the actual value field used for
 *	counting
 */
struct edac_dev_sysfs_block_attribute {
	struct attribute attr;
	ssize_t (*show)(struct kobject *, struct attribute *, char *);
	ssize_t (*store)(struct kobject *, struct attribute *,
			const char *, size_t);
	struct edac_device_block *block;

	unsigned int value;
};

/* device block control structure */
struct edac_device_block {
	struct edac_device_instance *instance;	/* Up Pointer */
	char name[EDAC_DEVICE_NAME_LEN + 1];

	struct edac_device_counter counters;	/* basic UE and CE counters */

	int nr_attribs;		/* how many attributes */

	/* this block's attributes, could be NULL */
	struct edac_dev_sysfs_block_attribute *block_attributes;

	/* edac sysfs device control */
	struct kobject kobj;
};

/* device instance control structure */
struct edac_device_instance {
	struct edac_device_ctl_info *ctl;	/* Up pointer */
	char name[EDAC_DEVICE_NAME_LEN + 4];

	struct edac_device_counter counters;	/* instance counters */

	u32 nr_blocks;		/* how many blocks */
	struct edac_device_block *blocks;	/* block array */

	/* edac sysfs device control */
	struct kobject kobj;
};

/*
 * Abstract edac_device control info structure
 *
 */
struct edac_device_ctl_info {
	/* for global list of edac_device_ctl_info structs */
	struct list_head link;

	struct module *owner;	/* Module owner of this control struct */

	int dev_idx;

	/* Per instance controls for this edac_device */
	int log_ue;		/* boolean for logging UEs */
	int log_ce;		/* boolean for logging CEs */
	int panic_on_ue;	/* boolean for panic'ing on an UE */
	unsigned poll_msec;	/* number of milliseconds to poll interval */
	unsigned long delay;	/* number of jiffies for poll_msec */

	/* Additional top controller level attributes, but specified
	 * by the low level driver.
	 *
	 * Set by the low level driver to provide attributes at the
	 * controller level, same level as 'ue_count' and 'ce_count' above.
	 * An array of structures, NULL terminated
	 *
	 * If attributes are desired, then set to array of attributes
	 * If no attributes are desired, leave NULL
	 */
	struct edac_dev_sysfs_attribute *sysfs_attributes;

	/* pointer to main 'edac' class in sysfs */
	struct sysdev_class *edac_class;

	/* the internal state of this controller instance */
	int op_state;
	/* work struct for this instance */
	struct delayed_work work;

	/* pointer to edac polling checking routine:
	 *      If NOT NULL: points to polling check routine
	 *      If NULL: Then assumes INTERRUPT operation, where
	 *              MC driver will receive events
	 */
	void (*edac_check) (struct edac_device_ctl_info * edac_dev);

	struct device *dev;	/* pointer to device structure */

	const char *mod_name;	/* module name */
	const char *ctl_name;	/* edac controller  name */
	const char *dev_name;	/* pci/platform/etc... name */

	void *pvt_info;		/* pointer to 'private driver' info */

	unsigned long start_time;	/* edac_device load start time (jiffies) */

	/* these are for safe removal of mc devices from global list while
	 * NMI handlers may be traversing list
	 */
	struct rcu_head rcu;
	struct completion removal_complete;

	/* sysfs top name under 'edac' directory
	 * and instance name:
	 *      cpu/cpu0/...
	 *      cpu/cpu1/...
	 *      cpu/cpu2/...
	 *      ...
	 */
	char name[EDAC_DEVICE_NAME_LEN + 1];

	/* Number of instances supported on this control structure
	 * and the array of those instances
	 */
	u32 nr_instances;
	struct edac_device_instance *instances;

	/* Event counters for the this whole EDAC Device */
	struct edac_device_counter counters;

	/* edac sysfs device control for the 'name'
	 * device this structure controls
	 */
	struct kobject kobj;
};

/* To get from the instance's wq to the beginning of the ctl structure */
#define to_edac_mem_ctl_work(w) \
		container_of(w, struct mem_ctl_info, work)

#define to_edac_device_ctl_work(w) \
		container_of(w,struct edac_device_ctl_info,work)

/*
 * The alloc() and free() functions for the 'edac_device' control info
 * structure. A MC driver will allocate one of these for each edac_device
 * it is going to control/register with the EDAC CORE.
 */
extern struct edac_device_ctl_info *edac_device_alloc_ctl_info(
		unsigned sizeof_private,
		char *edac_device_name, unsigned nr_instances,
		char *edac_block_name, unsigned nr_blocks,
		unsigned offset_value,
		struct edac_dev_sysfs_block_attribute *block_attributes,
		unsigned nr_attribs,
		int device_index);

/* The offset value can be:
 *	-1 indicating no offset value
 *	0 for zero-based block numbers
 *	1 for 1-based block number
 *	other for other-based block number
 */
#define	BLOCK_OFFSET_VALUE_OFF	((unsigned) -1)

extern void edac_device_free_ctl_info(struct edac_device_ctl_info *ctl_info);

#ifdef CONFIG_PCI

struct edac_pci_counter {
	atomic_t pe_count;
	atomic_t npe_count;
};

/*
 * Abstract edac_pci control info structure
 *
 */
struct edac_pci_ctl_info {
	/* for global list of edac_pci_ctl_info structs */
	struct list_head link;

	int pci_idx;

	struct sysdev_class *edac_class;	/* pointer to class */

	/* the internal state of this controller instance */
	int op_state;
	/* work struct for this instance */
	struct delayed_work work;

	/* pointer to edac polling checking routine:
	 *      If NOT NULL: points to polling check routine
	 *      If NULL: Then assumes INTERRUPT operation, where
	 *              MC driver will receive events
	 */
	void (*edac_check) (struct edac_pci_ctl_info * edac_dev);

	struct device *dev;	/* pointer to device structure */

	const char *mod_name;	/* module name */
	const char *ctl_name;	/* edac controller  name */
	const char *dev_name;	/* pci/platform/etc... name */

	void *pvt_info;		/* pointer to 'private driver' info */

	unsigned long start_time;	/* edac_pci load start time (jiffies) */

	/* these are for safe removal of devices from global list while
	 * NMI handlers may be traversing list
	 */
	struct rcu_head rcu;
	struct completion complete;

	/* sysfs top name under 'edac' directory
	 * and instance name:
	 *      cpu/cpu0/...
	 *      cpu/cpu1/...
	 *      cpu/cpu2/...
	 *      ...
	 */
	char name[EDAC_DEVICE_NAME_LEN + 1];

	/* Event counters for the this whole EDAC Device */
	struct edac_pci_counter counters;

	/* edac sysfs device control for the 'name'
	 * device this structure controls
	 */
	struct kobject kobj;
	struct completion kobj_complete;
};

#define to_edac_pci_ctl_work(w) \
		container_of(w, struct edac_pci_ctl_info,work)

/* write all or some bits in a byte-register*/
static inline void pci_write_bits8(struct pci_dev *pdev, int offset, u8 value,
				   u8 mask)
{
	if (mask != 0xff) {
		u8 buf;

		pci_read_config_byte(pdev, offset, &buf);
		value &= mask;
		buf &= ~mask;
		value |= buf;
	}

	pci_write_config_byte(pdev, offset, value);
}

/* write all or some bits in a word-register*/
static inline void pci_write_bits16(struct pci_dev *pdev, int offset,
				    u16 value, u16 mask)
{
	if (mask != 0xffff) {
		u16 buf;

		pci_read_config_word(pdev, offset, &buf);
		value &= mask;
		buf &= ~mask;
		value |= buf;
	}

	pci_write_config_word(pdev, offset, value);
}

/*
 * pci_write_bits32
 *
 * edac local routine to do pci_write_config_dword, but adds
 * a mask parameter. If mask is all ones, ignore the mask.
 * Otherwise utilize the mask to isolate specified bits
 *
 * write all or some bits in a dword-register
 */
static inline void pci_write_bits32(struct pci_dev *pdev, int offset,
				    u32 value, u32 mask)
{
	if (mask != 0xffffffff) {
		u32 buf;

		pci_read_config_dword(pdev, offset, &buf);
		value &= mask;
		buf &= ~mask;
		value |= buf;
	}

	pci_write_config_dword(pdev, offset, value);
}

#endif				/* CONFIG_PCI */

extern struct mem_ctl_info *edac_mc_alloc(unsigned sz_pvt, unsigned nr_csrows,
					  unsigned nr_chans, int edac_index);
extern int edac_mc_add_mc(struct mem_ctl_info *mci);
extern void edac_mc_free(struct mem_ctl_info *mci);
extern struct mem_ctl_info *edac_mc_find(int idx);
extern struct mem_ctl_info *edac_mc_del_mc(struct device *dev);
extern int edac_mc_find_csrow_by_page(struct mem_ctl_info *mci,
				      unsigned long page);

/*
 * The no info errors are used when error overflows are reported.
 * There are a limited number of error logging registers that can
 * be exausted.  When all registers are exhausted and an additional
 * error occurs then an error overflow register records that an
 * error occured and the type of error, but doesn't have any
 * further information.  The ce/ue versions make for cleaner
 * reporting logic and function interface - reduces conditional
 * statement clutter and extra function arguments.
 */
extern void edac_mc_handle_ce(struct mem_ctl_info *mci,
			      unsigned long page_frame_number,
			      unsigned long offset_in_page,
			      unsigned long syndrome, int row, int channel,
			      const char *msg);
extern void edac_mc_handle_ce_no_info(struct mem_ctl_info *mci,
				      const char *msg);
extern void edac_mc_handle_ue(struct mem_ctl_info *mci,
			      unsigned long page_frame_number,
			      unsigned long offset_in_page, int row,
			      const char *msg);
extern void edac_mc_handle_ue_no_info(struct mem_ctl_info *mci,
				      const char *msg);
extern void edac_mc_handle_fbd_ue(struct mem_ctl_info *mci, unsigned int csrow,
				  unsigned int channel0, unsigned int channel1,
				  char *msg);
extern void edac_mc_handle_fbd_ce(struct mem_ctl_info *mci, unsigned int csrow,
				  unsigned int channel, char *msg);

/*
 * edac_device APIs
 */
extern int edac_device_add_device(struct edac_device_ctl_info *edac_dev);
extern struct edac_device_ctl_info *edac_device_del_device(struct device *dev);
extern void edac_device_handle_ue(struct edac_device_ctl_info *edac_dev,
				int inst_nr, int block_nr, const char *msg);
extern void edac_device_handle_ce(struct edac_device_ctl_info *edac_dev,
				int inst_nr, int block_nr, const char *msg);
extern int edac_device_alloc_index(void);

/*
 * edac_pci APIs
 */
extern struct edac_pci_ctl_info *edac_pci_alloc_ctl_info(unsigned int sz_pvt,
				const char *edac_pci_name);

extern void edac_pci_free_ctl_info(struct edac_pci_ctl_info *pci);

extern void edac_pci_reset_delay_period(struct edac_pci_ctl_info *pci,
				unsigned long value);

extern int edac_pci_alloc_index(void);
extern int edac_pci_add_device(struct edac_pci_ctl_info *pci, int edac_idx);
extern struct edac_pci_ctl_info *edac_pci_del_device(struct device *dev);

extern struct edac_pci_ctl_info *edac_pci_create_generic_ctl(
				struct device *dev,
				const char *mod_name);

extern void edac_pci_release_generic_ctl(struct edac_pci_ctl_info *pci);
extern int edac_pci_create_sysfs(struct edac_pci_ctl_info *pci);
extern void edac_pci_remove_sysfs(struct edac_pci_ctl_info *pci);

/*
 * edac misc APIs
 */
extern char *edac_op_state_to_string(int op_state);

#endif				/* _EDAC_CORE_H_ */


/*
 * 				Twidere - Twitter client for Android
 *
 *  Copyright (C) 2012-2014 Mariotaku Lee <mariotaku.lee@gmail.com>
 *
 *  This program is free software: you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation, either version 3 of the License, or
 *  (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

package com.mcxiaoke.next.collection;

import java.util.ArrayList;
import java.util.Collection;
import java.util.concurrent.CopyOnWriteArrayList;

public class NoDuplicatesCopyOnWriteArrayList<E> extends CopyOnWriteArrayList<E> {

    public NoDuplicatesCopyOnWriteArrayList() {
        super();
    }

    public NoDuplicatesCopyOnWriteArrayList(final Collection<? extends E> collection) {
        super(collection);
    }

    public NoDuplicatesCopyOnWriteArrayList(final E[] array) {
        super(array);
    }

    @Override
    public boolean add(final E e) {
        return !contains(e) && super.add(e);
    }

    @Override
    public void add(final int index, final E element) {
        if (!contains(element)) {
            super.add(index, element);
        }
    }

    @Override
    public boolean addAll(final Collection<? extends E> collection) {
        final Collection<E> copy = new ArrayList<E>(collection);
        copy.removeAll(this);
        return super.addAll(copy);
    }

    @Override
    public boolean addAll(final int index, final Collection<? extends E> collection) {
        final Collection<E> copy = new ArrayList<E>(collection);
        copy.removeAll(this);
        return super.addAll(index, copy);
    }
}


#
# Dockerfile for elasticsearch-arm
#

FROM easypi/alpine-arm:edge
MAINTAINER EasyPi Software Foundation

ENV ELASTICSEARCH_VERSION 5.0.0
ENV ELASTICSEARCH_URL https://artifacts.elastic.co/downloads/elasticsearch/elasticsearch-$ELASTICSEARCH_VERSION.tar.gz

ENV GOSU_VERSION 1.10
ENV GOSU_URL https://github.com/tianon/gosu/releases/download/$GOSU_VERSION/gosu-armhf

WORKDIR /opt/elasticsearch

RUN set -xe \
    && apk add --no-cache ca-certificates \
                          bash \
                          curl \
                          openjdk8-jre \
                          tar \
    && curl -sSL $ELASTICSEARCH_URL | tar xz --strip 1 \
    && curl -sSL $GOSU_URL > /usr/local/bin/gosu \
    && chmod +x /usr/local/bin/gosu \
    && gosu nobody true \
    && apk del curl tar

RUN set -xe \
    && addgroup -g 1000 elasticsearch \
    && adduser -D -H -h /opt/elasticsearch -u 1000 -G elasticsearch elasticsearch \
    && mkdir -p data logs config/scripts \
    && chown -R elasticsearch:elasticsearch data logs config

COPY config ./config
COPY docker-entrypoint.sh /entrypoint.sh

VOLUME /opt/elasticsearch/data

EXPOSE 9200 9300

ENTRYPOINT ["/entrypoint.sh"]
CMD ["elasticsearch"]


using System;
using System.Collections.Generic;
using System.Linq;
using System.Text;

// TODO this should be fully commented; however it's not part of the main public API

#pragma warning disable 1591
#pragma warning disable 1570

namespace CsQuery.EquationParser.Implementation.Functions
{

    public class Abs: Function
    {
        public Abs()
            : base("abs")
        {

        }

        protected override IConvertible GetValue()
        {
            IConvertible value = FirstOperand.Value;

            if (Utils.IsIntegralType(value))
            {
                return Math.Abs(Convert.ToInt64(value));
            }
            else
            {
                return Math.Abs(Convert.ToDouble(value));
            }
        }

        public override int RequiredParmCount
        {
            get { return 1; }
        }

        public override int MaxParmCount
        {
            get { return 1; }
        }

        public override AssociationType AssociationType
        {
            get { return AssociationType.Function; }
        }

        protected override IOperand GetNewInstance()
        {
            return new Abs();
        }

        //protected override IOperand<U> CloneAsImpl<U>()
        //{
        //    throw new NotImplementedException();
        //}
    }

    //public class Abs<T> : Abs, IFunction<T> where T: IConvertible
    //{

    //    public new T Value
    //    {
    //        get {
    //            return (T)GetValue();
    //        }
    //    }

    //    public new IOperand<T> Clone()
    //    {
    //        return new Abs<T>();
    //    }
    //}
}


/*****************************************************************************
 *
 * MODULE:             PDU Manager
 *
 * COMPONENT:          pdum_app.h
 *
 * AUTHOR:             MRW
 *
 * DESCRIPTION:        PDU manager interface for application
 *                     Manages APDUs
 *
 * $HeadURL: https://www.collabnet.nxp.com/svn/lprf_sware/Projects/Cortex/Modules/PDUManager/Modules/PDUM/Trunk/Include/pdum_apl.h $
 *
 * $Revision: 84024 $
 *
 * $LastChangedBy: nxp29741 $
 *
 * $LastChangedDate: 2016-10-12 14:18:30 +0100 (Wed, 12 Oct 2016) $
 *
 * $Id: pdum_apl.h 84024 2016-10-12 13:18:30Z nxp29741 $
 *
 *****************************************************************************
 *
 * This software is owned by Jennic and/or its supplier and is protected
 * under applicable copyright laws. All rights are reserved. We grant You,
 * and any third parties, a license to use this software solely and
 * exclusively on Jennic products. You, and any third parties must reproduce
 * the copyright and warranty notice and any other legend of ownership on each
 * copy or partial copy of the software.
 *
 * THIS SOFTWARE IS PROVIDED "AS IS". JENNIC MAKES NO WARRANTIES, WHETHER
 * EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE,
 * ACCURACY OR LACK OF NEGLIGENCE. JENNIC SHALL NOT, IN ANY CIRCUMSTANCES,
 * BE LIABLE FOR ANY DAMAGES, INCLUDING, BUT NOT LIMITED TO, SPECIAL,
 * INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON WHATSOEVER.
 *
 * Copyright Jennic Ltd. 2008 All rights reserved
 *
 ****************************************************************************/

#ifndef PDUM_APP_H_
#define PDUM_APP_H_

#include "pdum_common.h"

/****************************************************************************/
/***        Macro Definitions                                             ***/
/****************************************************************************/

/****************************************************************************/
/***        Type Definitions                                              ***/
/****************************************************************************/

/* APDU instance handle */
typedef const struct pdum_tsAPduInstance_tag *PDUM_thAPduInstance;

/* APDU handle */
typedef const struct pdum_tsAPdu_tag *PDUM_thAPdu;

/****************************************************************************/
/***        External Variables                                            ***/
/****************************************************************************/

/****************************************************************************/
/***        Exported Public Functions                                     ***/
/****************************************************************************/

PUBLIC uint16 PDUM_u16APduInstanceReadNBO(PDUM_thAPduInstance hAPduInst, uint16 u16Pos, const char *szFormat, void *pvStruct);
PUBLIC uint16 PDUM_u16APduInstanceWriteNBO(PDUM_thAPduInstance hAPduInst, uint16 u16Pos, const char *szFormat, ...);
PUBLIC uint16 PDUM_u16APduInstanceWriteStrNBO(PDUM_thAPduInstance hAPduInst, uint16 u16Pos, const char *szFormat, void *pvStruct);
PUBLIC void * PDUM_pvAPduInstanceGetPayload(PDUM_thAPduInstance hAPduInst);
PUBLIC uint16 PDUM_u16APduInstanceGetPayloadSize(PDUM_thAPduInstance hAPduInst);
PUBLIC PDUM_teStatus PDUM_eAPduInstanceSetPayloadSize(PDUM_thAPduInstance hAPduInst, uint16 u16Size);
PUBLIC PDUM_thAPdu PDUM_thAPduInstanceGetApdu(PDUM_thAPduInstance hAPduInst);

PUBLIC PDUM_thAPduInstance PDUM_hAPduAllocateAPduInstance(PDUM_thAPdu hAPdu);
PUBLIC PDUM_teStatus PDUM_eAPduFreeAPduInstance(PDUM_thAPduInstance hAPduInst);
PUBLIC uint16 PDUM_u16APduGetSize(PDUM_thAPdu hAPdu);

PUBLIC uint8 u8GetMaxApdu(void);
PUBLIC uint8 u8GetApduUse(void);

#ifdef DBG_ENABLE
PUBLIC void PDUM_vDBGPrintAPduInstance(PDUM_thAPduInstance hAPduInst);
#else
#define PDUM_vDBGPrintAPduInstance(apdu)
#endif

/****************************************************************************/
/****************************************************************************/
/****************************************************************************/

#endif /*PDUM_APDU_H_*/


/*
 * Copyright 2012 Michael Ossmann <mike@ossmann.com>
 * Copyright 2012 Jared Boone <jared@sharebrained.com>
 *
 * This file is part of HackRF
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2, or (at your option)
 * any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; see the file COPYING.  If not, write to
 * the Free Software Foundation, Inc., 51 Franklin Street,
 * Boston, MA 02110-1301, USA.
 */

MEMORY
{
	/* Physical address in Flash used to copy Code from Flash to RAM */
	rom_flash (rx)  : ORIGIN = 0x80000000, LENGTH =  1M
	ram_m0 (rwx) : ORIGIN = 0x20000000, LENGTH = 28K
	ram_shared (rwx) : ORIGIN = 0x20007000, LENGTH =  4K
	ram_usb (rwx) : ORIGIN = 0x20008000, LENGTH = 32K
	/* ram_usb: USB buffer. Straddles two blocks of RAM
	 * to get performance benefit of having two USB buffers addressable
	 * simultaneously (on two different buses of the AHB multilayer matrix)
	 */
}

usb_bulk_buffer = ORIGIN(ram_usb);


/******************************************************************************
*
* Copyright (C) 2014-2017 Xilinx, Inc.  All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xzdma.h
* @addtogroup zdma_v1_5
* @{
* @details
*
* ZDMA is a general purpose DMA designed to support memory to memory and memory
* to IO buffer transfers. ZynqMP has two instance of general purpose ZDMA.
* One is located in FPD (full power domain) which is GDMA and other is located
* in LPD (low power domain) which is ADMA.
*
* GMDA & ADMA are configured each with 8 DMA channels and and each channel can
* be programmed secure or non-secure.
* Each channel is divided into two functional sides, Source (Read) and
* Destination (Write). Each DMA channel can be independently programmed
* in one of following DMA modes.
*	- Simple DMA
*		- Normal data transfer from source to destination.
*		- Write Only mode.
*		- Read Only mode.
*	- Scatter Gather DMA
*		- Only Normal mode it can't support other two modes.
* In Scatter gather descriptor can be of 3 types
*	- Linear descriptor.
*	- Linked list descriptor
*	- Hybrid descriptor (Combination of both Linear and Linked list)
* Our driver will not support Hybrid type of descriptor.
*
* Initialization & Configuration
*
* The device driver enables higher layer software (e.g., an application) to
* communicate to the ZDMA core.
*
* XZDma_CfgInitialize() API is used to initialize the ZDMA core.
* The user needs to first call the XZDma_LookupConfig() API which returns
* the Configuration structure pointer which is passed as a parameter to the
* XZDma_CfgInitialize() API.
*
*  Interrupts
* The driver provides an interrupt handler XZDma_IntrHandler for handling
* the interrupt from the ZDMA core. The users of this driver have to
* register this handler with the interrupt system and provide the callback
* functions by using XZDma_SetCallBack API. In this version Descriptor done
* option is disabled.
*
*  Virtual Memory
*
* This driver supports Virtual Memory. The RTOS is responsible for calculating
* the correct device base address in Virtual Memory space.
*
*  Threads
*
* This driver is not thread safe. Any needs for threads or thread mutual
* exclusion must be satisfied by the layer above this driver.
*
*  Asserts
*
* Asserts are used within all Xilinx drivers to enforce constraints on argument
* values. Asserts can be turned off on a system-wide basis by defining, at
* compile time, the NDEBUG identifier. By default, asserts are turned on and it
* is recommended that users leave asserts on during development.
*
*  Building the driver
*
* The XZDma driver is composed of several source files. This allows the user
* to build and link only those parts of the driver that are necessary.
*
* This header file contains identifiers and register-level driver functions (or
* macros), range macros, structure typedefs that can be used to access the
* Xilinx ZDMA core instance.
*
*

* MODIFICATION HISTORY:
*
* Ver   Who     Date     Changes
* ----- ------  -------- ------------------------------------------------------
* 1.0   vns     2/27/15  First release
* 1.1   vns    15/02/16  Corrected Destination descriptor addresss calculation
*                        in XZDma_CreateBDList API
*                        Modified XZDma_SetMode to return XST_FAILURE on
*                        selecting DMA mode other than normal mode in
*                        scatter gather mode data transfer and corrected
*                        XZDma_SetChDataConfig API to set over fetch and
*                        src issue parameters correctly.
*       ms     03/17/17  Added readme.txt file in examples folder for doxygen
*                        generation.
*       ms     04/05/17  Modified comment lines notation in functions of zdma
*                        examples to avoid unnecessary description to get
*                        displayed while generating doxygen and also changed
*                        filename tag to include the readonly mode example file
*                        in doxygen.
* 1.3   mus     08/14/17 Update cache coherency information of the interface in
*                        its config structure.
* 1.4   adk 	11/02/17 Updated examples to fix compilation errors for IAR
*			 compiler.
* 1.5   adk     11/22/17 Added peripheral test app support for ZDMA driver.
*		12/11/17 Fixed peripheral test app generation issues when dma
*			 buffers are configured on OCM memory(CR#990806).
*

*
******************************************************************************/
#ifndef XZDMA_H_
#define XZDMA_H_

#ifdef __cplusplus
extern "C" {
#endif

/***************************** Include Files *********************************/

#include "xzdma_hw.h"
#include "xil_assert.h"
#include "xstatus.h"
#include "xil_cache.h"
#include "bspconfig.h"

/************************** Constant Definitions *****************************/

/**************************** Type Definitions *******************************/

/** @name ZDMA Handler Types
 * @{
 */
typedef enum {
	XZDMA_HANDLER_DONE,	/**< For Done Handler */
	XZDMA_HANDLER_ERROR,	/**< For Error Handler */
} XZDma_Handler;
/*@}*/

/** @name ZDMA Descriptors Types
 * @{
 */
typedef enum {
	XZDMA_LINEAR,		/**< Linear descriptor */
	XZDMA_LINKEDLIST,	/**< Linked list descriptor */
} XZDma_DscrType;
/*@}*/

/** @name ZDMA Operation modes
 * @{
 */
typedef enum {
	XZDMA_NORMAL_MODE,	/**< Normal transfer from source to
				  *  destination*/
	XZDMA_WRONLY_MODE,	/**< Write only mode */
	XZDMA_RDONLY_MODE	/**< Read only mode */
} XZDma_Mode;
/*@}*/

/** @name ZDMA state
 * @{
 */
typedef enum {
	XZDMA_IDLE,		/**< ZDMA is in Idle state */
	XZDMA_PAUSE,		/**< Paused state */
	XZDMA_BUSY,		/**< Busy state */
} XZDmaState;
/*@}*/

/** @name ZDMA AXI Burst type
 * @{
 */
typedef enum {
	XZDMA_FIXED_BURST = 0,	/**< Fixed burst type */
	XZDMA_INCR_BURST	/**< Increment burst type */
} XZDma_BurstType;
/*@}*/

/******************************************************************************/
/**
* This typedef contains scatter gather descriptor fields for ZDMA core.
*/
typedef struct {
	void *SrcDscrPtr;	/**< Source Descriptor pointer */
	void *DstDscrPtr;	/**< Destination Descriptor pointer */
	u32 DscrCount;		/**< Count of descriptors available */
	XZDma_DscrType DscrType;/**< Type of descriptor either Linear or
				  *  Linked list type */
} XZDma_Descriptor;

/******************************************************************************/
/**
* This typedef contains scatter gather descriptor fields for ZDMA core.
*/
#if defined (__ICCARM__)
#pragma pack(push, 1)
#endif
typedef struct {
	u64 Address;	/**< Address */
	u32 Size;	/**< Word2, Size of data */
	u32 Cntl;	/**< Word3 Control data */
	u64 NextDscr; 	/**< Address of next descriptor */
	u64 Reserved;	/**< Reserved address */
#if defined (__ICCARM__)
}  XZDma_LlDscr ;
#pragma pack(pop)
#else
} __attribute__ ((packed)) XZDma_LlDscr;
#endif
/******************************************************************************/
/**
* This typedef contains Linear descriptor fields for ZDMA core.
*/
#if defined (__ICCARM__)
#pragma pack(push, 1)
#endif
typedef struct {
	u64 Address;	/**< Address */
	u32 Size;	/**< Word3, Size of data */
	u32 Cntl;	/**< Word4, control data */
#if defined (__ICCARM__)
}XZDma_LiDscr;
#pragma pack(pop)
#else
}  __attribute__ ((packed)) XZDma_LiDscr;
#endif
/******************************************************************************/
/**
*
* This typedef contains the data configurations of ZDMA core
*/
typedef struct {
	u8 OverFetch;		/**< Enable Over fetch */
	u8 SrcIssue;		/**< Outstanding transactions for Source */
	XZDma_BurstType SrcBurstType;
				/**< Burst type for SRC */
	u8 SrcBurstLen;		/**< AXI length for data read */
	XZDma_BurstType DstBurstType;
				/**< Burst type for DST */
	u8 DstBurstLen;		/**< AXI length for data write */
	u8 SrcCache;		/**< AXI cache bits for data read */
	u8 SrcQos;		/**< AXI QOS bits for data read */
	u8 DstCache;		/**< AXI cache bits for data write */
	u8 DstQos;		/**< AXI QOS bits for data write */
} XZDma_DataConfig;

/******************************************************************************/
/**
*
* This typedef contains the descriptor configurations of ZDMA core
*/
typedef struct{
	u8 AxCoherent;	/**< AXI transactions are coherent or non-coherent */
	u8 AXCache;	/**< AXI cache for DSCR fetch */
	u8 AXQos;	/**< Qos bit for DSCR fetch */
} XZDma_DscrConfig;

/******************************************************************************/
/**
* Callback type for Completion of all data transfers.
*
* @param 	CallBackRef is a callback reference passed in by the upper layer
*		when setting the callback functions, and passed back to the
*		upper layer when the callback is invoked.
*******************************************************************************/
typedef void (*XZDma_DoneHandler) (void *CallBackRef);

/******************************************************************************/
/**
* Callback type for all error interrupts.
*
* @param 	CallBackRef is a callback reference passed in by the upper layer
*		when setting the callback functions, and passed back to the
*		upper layer when the callback is invoked.
* @param	ErrorMask is a bit mask indicating the cause of the error. Its
*		value equals 'OR'ing one or more XZDMA_IXR_* values defined in
*		xzdma_hw.h
****************************************************************************/
typedef void (*XZDma_ErrorHandler) (void *CallBackRef, u32 ErrorMask);

/**
* This typedef contains configuration information for a ZDMA core
* Each ZDMA core should have a configuration structure associated.
*/
typedef struct {
	u16 DeviceId;		/**< Device Id of ZDMA */
	u32 BaseAddress;	/**< BaseAddress of ZDMA */
	u8 DmaType;		/**< Type of DMA */
	u8 IsCacheCoherent; /**< Describes whether Cache Coherent or not;
                              * Applicable only to A53 in EL1 NS mode */
} XZDma_Config;

/******************************************************************************/
/**
*
* The XZDma driver instance data structure. A pointer to an instance data
* structure is passed around by functions to refer to a specific driver
* instance.
*/
typedef struct {
	XZDma_Config Config;	/**< Hardware configuration */
	u32 IsReady;		/**< Device and the driver instance
				  *  are initialized */
	u32 IntrMask;		/**< Mask for enabling interrupts */

	XZDma_Mode Mode;	/**< Mode of ZDMA core to be operated */
	u8 IsSgDma;		/**< Is ZDMA core is in scatter gather or
				  *  not will be specified */
	u32 Slcr_adma;		/**< Used to hold SLCR ADMA register
				  *  contents */
	XZDma_Descriptor Descriptor;	/**< It contains information about
					  * descriptors */

	XZDma_DoneHandler DoneHandler;	/**< Call back for transfer
					  *  done interrupt */
	void *DoneRef;			/**< To be passed to the done
					  * interrupt callback */

	XZDma_ErrorHandler ErrorHandler;/**< Call back for error
					  *  interrupt */
	void *ErrorRef;			/**< To be passed to the error
					  * interrupt callback */
	XZDma_DataConfig DataConfig;	/**< Current configurations */
	XZDma_DscrConfig DscrConfig;	/**< Current configurations */
	XZDmaState ChannelState;	 /**< ZDMA channel is busy */

} XZDma;

/******************************************************************************/
/**
*
* This typedef contains the fields for transfer of data.
*/
typedef struct {
	UINTPTR SrcAddr;	/**< Source address */
	UINTPTR DstAddr;	/**< Destination Address */
	u32 Size;		/**< Size of the data to be transferred */
	u8 SrcCoherent;		/**< Source coherent */
	u8 DstCoherent;		/**< Destination coherent */
	u8 Pause;		/**< Will pause data transmission after
				  *  this transfer only for SG mode */
} XZDma_Transfer;

/***************** Macros (Inline Functions) Definitions *********************/

/*****************************************************************************/
/**
*
* This function returns interrupt status read from Interrupt Status Register.
* Use the XZDMA_IXR_DMA_*_MASK constants defined in xzdma_hw.h to interpret the
* returned value.
*
* @param	InstancePtr is a pointer to the XZDma instance.
*
* @return	The pending interrupts of the ZDMA core.
*		Use the masks specified in xzdma_hw.h to interpret
*		the returned value.
* @note
* 		C-style signature:
*		void XZDma_IntrGetStatus(XZDma *InstancePtr)
*
******************************************************************************/
#define XZDma_IntrGetStatus(InstancePtr) \
	XZDma_ReadReg((InstancePtr)->Config.BaseAddress, XZDMA_CH_ISR_OFFSET)

/*****************************************************************************/
/**
*
* This function clears interrupt(s). Every bit set in Interrupt Status
* Register indicates that a specific type of interrupt is occurring, and this
* function clears one or more interrupts by writing a bit mask to Interrupt
* Clear Register.
*
* @param	InstancePtr is a pointer to the XZDma instance.
* @param	Mask is the type of the interrupts to enable. Use OR'ing of
*		XZDMA_IXR_DMA_*_MASK constants defined in xzdma_hw.h to create
*		this parameter value.
*
* @return	None.
*
* @note
* 		C-style signature:
*		void XZDma_IntrClear(XZDma *InstancePtr)
*
******************************************************************************/
#define XZDma_IntrClear(InstancePtr, Mask) \
	XZDma_WriteReg( (InstancePtr)->Config.BaseAddress, \
	XZDMA_CH_ISR_OFFSET, ((u32)(Mask) & (u32)XZDMA_IXR_ALL_INTR_MASK))

/*****************************************************************************/
/**
*
* This function returns interrupt mask to know which interrupts are
* enabled and which of them were disabled.
*
* @param	InstancePtr is a pointer to the XZDma instance.
*
* @return	The current interrupt mask. The mask indicates which interrupts
*		are enabled/disabled.
*		0 bit represents .....corresponding interrupt is enabled.
*		1 bit represents .....Corresponding interrupt is disabled.
*
* @note
* 		C-style signature:
*		void XZDma_GetIntrMask(XZDma *InstancePtr)
*
******************************************************************************/
#define XZDma_GetIntrMask(InstancePtr) \
	XZDma_ReadReg((InstancePtr)->Config.BaseAddress,  \
			(u32)(XZDMA_CH_IMR_OFFSET))

/*****************************************************************************/
/**
*
* This function enables individual interrupts of the ZDMA core by updating
* the Interrupt Enable register.
*
* @param	InstancePtr is a pointer to the XZDma instance.
* @param	Mask is the type of the interrupts to enable. Use OR'ing of
*		XZDMA_IXR_DMA_*_MASK constants defined in xzdma_hw.h to create
*		this parameter value.
*
* @return	None.
*
* @note		The existing enabled interrupt(s) will remain enabled.
* 		C-style signature:
*		void XZDma_EnableIntr(XZDma *InstancePtr, u32 Mask)
*
******************************************************************************/
#define XZDma_EnableIntr(InstancePtr, Mask) \
	(InstancePtr)->IntrMask = ((InstancePtr)->IntrMask | (Mask))

/*****************************************************************************/
/**
*
* This function disables individual interrupts of the ZDMA core by updating
* the Interrupt Disable register.
*
* @param	InstancePtr is a pointer to the XZDma instance.
* @param	Mask is the type of the interrupts to disable. Use OR'ing of
*		XZDMA_IXR_DMA_*_MASK constants defined in xzdma_hw.h to create
*		this parameter value.
*
* @return	None.
*
* @note		The existing disabled interrupt(s) will remain disabled.
* 		C-style signature:
*		void XZDma_DisableIntr(XZDma *InstancePtr, u32 Mask)
*
******************************************************************************/
#define XZDma_DisableIntr(InstancePtr, Mask) \
	XZDma_WriteReg( (InstancePtr)->Config.BaseAddress, \
			XZDMA_CH_IDS_OFFSET, \
	((u32)XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
	XZDMA_CH_IDS_OFFSET) | ((u32)(Mask) & (u32)XZDMA_IXR_ALL_INTR_MASK)))

/*****************************************************************************/
/**
*
* This function returns source current payload address under process
* of ZDMA core.
*
* @param	InstancePtr is a pointer to the XZDma instance.
*
* @return	None.
*
* @note		This address may not be precise due to ZDMA pipeline structure
*		C-style signature:
*		u64 XZDma_SrcCurPyld(XZDma *InstancePtr)
*
******************************************************************************/
#define XZDma_SrcCurPyld(InstancePtr) \
	((u64)(XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
			XZDMA_CH_SRC_CUR_PYLD_LSB_OFFSET)) | \
	((u64)(XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
	XZDMA_CH_SRC_CUR_PYLD_MSB_OFFSET)) << XZDMA_WORD1_MSB_SHIFT))

/*****************************************************************************/
/**
*
* This function returns destination current payload address under process
* of ZDMA core.
*
* @param	InstancePtr is a pointer to the XZDma instance.
*
* @return	None.
*
* @note		This address may not be precise due to ZDMA pipeline structure
*		C-style signature:
*		u64 XZDma_DstCurPyld(XZDma *InstancePtr)
*
******************************************************************************/
#define XZDma_DstCurPyld(InstancePtr) \
	((u64)(XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
			XZDMA_CH_DST_CUR_PYLD_LSB_OFFSET)) | \
	((u64)(XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
	XZDMA_CH_DST_CUR_PYLD_MSB_OFFSET)) << XZDMA_WORD1_MSB_SHIFT))

/*****************************************************************************/
/**
*
* This function returns source descriptor current payload address under
* process of ZDMA core.
*
* @param	InstancePtr is a pointer to the XZDma instance.
*
* @return	None.
*
* @note		This address may not be precise due to ZDMA pipeline structure
*		C-style signature:
*		u64 XZDma_SrcDscrCurPyld(XZDma *InstancePtr)
*
******************************************************************************/
#define XZDma_SrcDscrCurPyld(InstancePtr) \
	((u64)(XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
			XZDMA_CH_SRC_CUR_DSCR_LSB_OFFSET)) | \
	((u64)(XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
	XZDMA_CH_SRC_CUR_DSCR_MSB_OFFSET)) << XZDMA_WORD1_MSB_SHIFT))

/*****************************************************************************/
/**
*
* This function returns destination descriptor current payload address under
* process of ZDMA core.
*
* @param	InstancePtr is a pointer to the XZDma instance.
*
* @return	None.
*
* @note		This address may not be precise due to ZDMA pipeline structure
*		C-style signature:
*		u64 XZDma_DstDscrCurPyld(XZDma *InstancePtr)
*
******************************************************************************/
#define XZDma_DstDscrCurPyld(InstancePtr) \
	((u64)(XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
			XZDMA_CH_DST_CUR_DSCR_LSB_OFFSET)) | \
	((u64)(XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
	XZDMA_CH_DST_CUR_DSCR_MSB_OFFSET)) << XZDMA_WORD1_MSB_SHIFT))

/*****************************************************************************/
/**
*
* This function gets the count of total bytes transferred through core
* since last clear in ZDMA core.
*
* @param	InstancePtr is a pointer to the XZDma instance.
*
* @return	None.
*
* @note
*		C-style signature:
*		void XZDma_GetTotalByte(XZDma *InstancePtr)
*
******************************************************************************/
#define XZDma_GetTotalByte(InstancePtr) \
	XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
			XZDMA_CH_TOTAL_BYTE_OFFSET)

/*****************************************************************************/
/**
*
* This function clears the count of total bytes transferred in ZDMA core.
*
* @param	InstancePtr is a pointer to the XZDma instance.
*
* @return	None.
*
* @note
*		C-style signature:
*		void XZDma_TotalByteClear(XZDma *InstancePtr)
*
******************************************************************************/
#define XZDma_TotalByteClear(InstancePtr) \
	XZDma_WriteReg((InstancePtr)->Config.BaseAddress, \
		XZDMA_CH_TOTAL_BYTE_OFFSET, \
	XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
		XZDMA_CH_TOTAL_BYTE_OFFSET))

/*****************************************************************************/
/**
*
* This function gets the total number of Interrupt count for source after last
* call of this API.
*
* @param	InstancePtr is a pointer to the XZDma instance.
*
* @return	None.
*
* @note		Once this API is called then count will become zero.
*		C-style signature:
*		void XZDma_GetSrcIntrCnt(XZDma *InstancePtr)
*
******************************************************************************/
#define XZDma_GetSrcIntrCnt(InstancePtr) \
	XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
			XZDMA_CH_IRQ_SRC_ACCT_OFFSET)

/*****************************************************************************/
/**
*
* This function gets the total number of Interrupt count for destination
* after last call of this API.
*
* @param	InstancePtr is a pointer to the XZDma instance.
*
* @return	None.
*
* @note		Once this API is called then count will become zero.
*		C-style signature:
*		void XZDma_GetDstIntrCnt(XZDma *InstancePtr)
*
******************************************************************************/
#define XZDma_GetDstIntrCnt(InstancePtr) \
	XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
			XZDMA_CH_IRQ_DST_ACCT_OFFSET)

/*****************************************************************************/
/**
*
* This function Enable's the ZDMA core for initiating the data transfer once the
* data transfer completes it will be automatically disabled.
*
* @param	InstancePtr is a pointer to the XZDma instance.
*
* @return	None.
*
* @note		None.
*		C-style signature:
*		void XZDma_EnableCh(XZDma *InstancePtr)
*
******************************************************************************/
#define XZDma_EnableCh(InstancePtr) \
	XZDma_WriteReg((InstancePtr)->Config.BaseAddress, \
			(XZDMA_CH_CTRL2_OFFSET), (XZDMA_CH_CTRL2_EN_MASK))

/*****************************************************************************/
/**
*
* This function Disable's the ZDMA core.
*
* @param	InstancePtr is a pointer to the XZDma instance.
*
* @return	None.
*
* @note		None.
*		C-style signature:
*		void XZDma_DisableCh(XZDma *InstancePtr)
*
******************************************************************************/
#define XZDma_DisableCh(InstancePtr) \
	XZDma_WriteReg((InstancePtr)->Config.BaseAddress,\
		(XZDMA_CH_CTRL2_OFFSET), (XZDMA_CH_CTRL2_DIS_MASK))

/************************ Prototypes of functions **************************/

XZDma_Config *XZDma_LookupConfig(u16 DeviceId);

s32 XZDma_CfgInitialize(XZDma *InstancePtr, XZDma_Config *CfgPtr,
			u32 EffectiveAddr);
s32 XZDma_SetMode(XZDma *InstancePtr, u8 IsSgDma, XZDma_Mode Mode);
u32 XZDma_CreateBDList(XZDma *InstancePtr, XZDma_DscrType TypeOfDscr,
					UINTPTR Dscr_MemPtr, u32 NoOfBytes);
s32 XZDma_SetChDataConfig(XZDma *InstancePtr, XZDma_DataConfig *Configure);
void XZDma_GetChDataConfig(XZDma *InstancePtr, XZDma_DataConfig *Configure);
s32 XZDma_SetChDscrConfig(XZDma *InstancePtr, XZDma_DscrConfig *Configure);
void XZDma_GetChDscrConfig(XZDma *InstancePtr, XZDma_DscrConfig *Configure);
s32 XZDma_Start(XZDma *InstancePtr, XZDma_Transfer *Data, u32 Num);
void XZDma_WOData(XZDma *InstancePtr, u32 *Buffer);
void XZDma_Resume(XZDma *InstancePtr);
void XZDma_Reset(XZDma *InstancePtr);
XZDmaState XZDma_ChannelState(XZDma *InstancePtr);

s32 XZDma_SelfTest(XZDma *InstancePtr);

void XZDma_IntrHandler(void *Instance);
s32 XZDma_SetCallBack(XZDma *InstancePtr, XZDma_Handler HandlerType,
	void *CallBackFunc, void *CallBackRef);

/*@}*/

#ifdef __cplusplus
}

#endif

#endif /* XZDMA_H_ */
/** @} */


.Block--CallToAction {
	@include ador-background-image('../assets/images/ador-poststatus-41.jpg');

	color: white;

	.text-wrap {
		padding: 0 48px 48px;
	}
	.text-wrap--no-subheading {
		padding-top: 0;
	}

	h2, p {
		color: inherit;
	}

	h2 {
		text-transform: uppercase;
		margin: 0;
	}

	p {
		margin: 24px 0 0 0;
	}

	img + .text-wrap--no-subheading {
		padding-top: 24px;
	}
}


# -*- coding: binary -*-
require 'msf/core/handler/find_port'

module Msf
module Handler

###
#
# This handlers implements tag-based findsock handling.
#
###
module FindTag

  include FindPort

  #
  # Returns the string representation of the handler type, in this case
  # 'find_tag'.
  #
  def self.handler_type
    return "find_tag"
  end

  #
  # Returns the connection oriented general handler type, in this case
  # 'find'.
  #
  def self.general_handler_type
    "find"
  end

  #
  # Initializes the find tag handler with the option that is required for all
  # find-tag based payloads, such as the TAG that will be searched for.
  #
  def initialize(info = {})
    super

    register_advanced_options(
      [
        OptString.new('TAG',
          [
            true,
            "The four byte tag to signify the connection.",
            Rex::Text.rand_text_alphanumeric(4),
          ])
      ], Msf::Handler::FindTag)

    # Eliminate the CPORT option.
    options.remove_option('CPORT')
  end

protected

  #
  # Prefix the stage with this.
  #
  def _find_prefix(sock)
    if (self.respond_to?('stage_prefix') == true)
      self.stage_prefix = _find_tag
    else
      _find_tag
    end
  end

  #
  # Transmits the tag.
  #
  def _send_id(sock)
    if (self.payload_type == Msf::Payload::Type::Single)
      sock.put(_find_tag)

      return _find_tag
    end

    return nil
  end

  #
  # Returns the tag we'll be using.
  #
  def _find_tag
    tag  = (datastore['TAG'] || "msf!")
    tag << ("\x01" * (tag.length - 4))

    return tag[0, 4]
  end

end

end
end


#![warn(rust_2018_idioms)]
#![cfg(feature = "sync")]

use tokio::runtime;
use tokio::sync::oneshot;

use std::sync::mpsc;
use std::thread;

#[test]
fn basic_shell_rt() {
    let (feed_tx, feed_rx) = mpsc::channel::<oneshot::Sender<()>>();

    let th = thread::spawn(move || {
        for tx in feed_rx.iter() {
            tx.send(()).unwrap();
        }
    });

    for _ in 0..1_000 {
        let rt = runtime::Builder::new().build().unwrap();

        let (tx, rx) = oneshot::channel();

        feed_tx.send(tx).unwrap();

        rt.block_on(rx).unwrap();
    }

    drop(feed_tx);
    th.join().unwrap();
}


"fonts.styles" {
	colors {
		font__basefont = "Roboto"
		font__basefont = "Roboto Regular" [$OSX]
		font__mediumfont = "Roboto Medium"
		font__heavyfont = "Roboto Bold"
		font__console = "Lucida Console"
		font__console = "Menlo" [$OSX]
	}
}


/*
	This file is part of the OdinMS Maple Story Server
    Copyright (C) 2008 Patrick Huy <patrick.huy@frz.cc>
		       Matthias Butz <matze@odinms.de>
		       Jan Christian Meyer <vimes@odinms.de>

    This program is free software: you can redistribute it and/or modify
    it under the terms of the GNU Affero General Public License as
    published by the Free Software Foundation version 3 as published by
    the Free Software Foundation. You may not use, modify or distribute
    this program under any other version of the GNU Affero General Public
    License.

    This program is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU Affero General Public License for more details.

    You should have received a copy of the GNU Affero General Public License
    along with this program.  If not, see <http://www.gnu.org/licenses/>.
*/
/*
 *@Author:  Moogra
 *@NPC:     4th Job Bowman Advancement NPC
 *@Purpose: Handles 4th job.
 */

var status;

function start() {
        status = -1;
        action(1, 0, 0);
}

function action(mode, type, selection) {
        if (mode == -1) {
                cm.dispose();
        } else {
                if (mode == 0 && status == 0) {
                        cm.dispose();
                        return;
                }
                if (mode == 1)
                        status++;
                else
                        status--;

                if(status == 0) {
                        if(cm.getLevel() < 120 || Math.floor(cm.getJobId() / 100) != 3) {
                                cm.sendOk("Please don't bother me right now, I am trying to concentrate.");
                                cm.dispose();
                        } else if (!cm.isQuestCompleted(6924)) {
                                cm.sendOk("You have not yet passed my trials. I can not advance you until you do so.");
                                cm.dispose();
                        } else if ( cm.getJobId() % 100 % 10 != 2) {
                                cm.sendYesNo("You did a marvellous job passing my test. Are you ready to advance to your 4th job?");
                        } else {
                                cm.sendSimple("If I must, I can teach you the art of your class.\r\n#b#L0#Teach me the skills of my class.#l");
                                //cm.dispose();
                        }
                } else if(status == 1) {
                        if (mode >= 1 && cm.getJobId() % 100 % 10 != 2) {
                                if (cm.canHold(2280003, 1)) {
                                        cm.changeJobById(cm.getJobId() + 1);
                                        if(cm.getJobId() == 312) {
                                                cm.teachSkill(3121002, 0, 10, -1);
                                                cm.teachSkill(3120005, 0, 10, -1);
                                                cm.teachSkill(3121007, 0, 10, -1);
                                        } else if(cm.getJobId() == 322) {
                                                cm.teachSkill(3221002, 0, 10, -1);
                                                cm.teachSkill(3220004, 0, 10, -1);
                                                cm.teachSkill(3221006, 0, 10, -1);
                                        }
                                        cm.gainItem(2280003, 1);
                                } else {
                                        cm.sendOk("Please have one slot available on #bUSE#k inventory to receive a skill book.");
                                }
                        } else if(mode >= 0 && cm.getJobId() % 100 % 10 == 2) {
                                if(cm.getJobId() == 312) {
                                        if(cm.getPlayer().getSkillLevel(3121008) == 0)
                                                cm.teachSkill(3121008 , 0, 10, -1);
                                        if(cm.getPlayer().getSkillLevel(3121006) == 0)
                                                cm.teachSkill(3121006 , 0, 10, -1);
                                        if(cm.getPlayer().getSkillLevel(3121004) == 0)
                                                cm.teachSkill(3121004 , 0, 10, -1);
                                } else if(cm.getJobId() == 322) {
                                        if(cm.getPlayer().getSkillLevel(3221007) == 0)
                                                cm.teachSkill(3221007 , 0, 10, -1);
                                        if(cm.getPlayer().getSkillLevel(3221005) == 0)
                                                cm.teachSkill(3221005 , 0, 10, -1);
                                        if(cm.getPlayer().getSkillLevel(3221001) == 0)
                                                cm.teachSkill(3221001 , 0, 10, -1);
                                }
                                cm.sendOk("It is done. Leave me now.");
                        }

                        cm.dispose();
                }
        }
}


<!doctype html>

  <title>npm-hook</title>
  <meta charset="utf-8">
  <link rel="stylesheet" type="text/css" href="../../static/style.css">
  <link rel="canonical" href="https://www.npmjs.org/doc/cli/npm-hook.html">

npm-hook

Manage registry hooks

SYNOPSIS

npm hook ls [pkg]
npm hook add <entity> <url> <secret>
npm hook update <id> <url> [secret]
npm hook rm <id>

EXAMPLE

Add a hook to watch a package for changes:

$ npm hook add lodash https://example.com/ my-shared-secret

Add a hook to watch packages belonging to the user substack:

$ npm hook add ~substack https://example.com/ my-shared-secret

Add a hook to watch packages in the scope @npm

$ npm hook add @npm https://example.com/ my-shared-secret

List all your active hooks:

$ npm hook ls

List your active hooks for the lodash package:

$ npm hook ls lodash

Update an existing hook's url:

$ npm hook update id-deadbeef https://my-new-website.here/

Remove a hook:

$ npm hook rm id-deadbeef

DESCRIPTION

Allows you to manage npm
hooks,
including adding, removing, listing, and updating.

Hooks allow you to configure URL endpoints that will be notified whenever a
change happens to any of the supported entity types. Three different types of
entities can be watched by hooks: packages, owners, and scopes.

To create a package hook, simply reference the package name.

To create an owner hook, prefix the owner name with ~ (as in, ~youruser).

To create a scope hook, prefix the scope name with @ (as in, @yourscope).

The hook id used by update and rm are the IDs listed in npm hook ls for
that particular hook.

The shared secret will be sent along to the URL endpoint so you can verify the
request came from your own configured hook.

SEE ALSO

"Introducing Hooks" blog post

npm-hook — npm@6.4.1


#include <Gosu/Platform.hpp>
#if defined(GOSU_IS_WIN)

#include <Gosu/Utility.hpp>
#include "WinUtility.hpp"
#include <windows.h>
using namespace std;

string Gosu::language()
{
    LCID lcid = GetUserDefaultLCID();
    char buffer[9];
    winapi_check(GetLocaleInfoA(lcid, LOCALE_SISO639LANGNAME, buffer, sizeof buffer));
    return buffer;
}

#endif


//-- copyright
// OpenProject is an open source project management software.
// Copyright (C) 2012-2020 the OpenProject GmbH
//
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License version 3.
//
// OpenProject is a fork of ChiliProject, which is a fork of Redmine. The copyright follows:
// Copyright (C) 2006-2017 Jean-Philippe Lang
// Copyright (C) 2010-2013 the ChiliProject Team
//
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation; either version 2
// of the License, or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
//
// See docs/COPYRIGHT.rdoc for more details.
//++

// 'Global' dependencies
//
// dependencies required by classic (Rails) and Angular application.

// Angular 4 deps. Must be loaded early!
// require('reflect-metadata');
// require('zone.js');
// require('@angular/core');

// ES6 Promise polyfill
require('expose-loader?Promise!es6-promise');

// Lodash
require('expose-loader?_!lodash');

// jQuery
require('expose-loader?jQuery!jquery');
require('jquery-ujs');

require('expose-loader?mousetrap!mousetrap/mousetrap.js');

// Angular dependencies
require('expose-loader?dragula!dragula/dist/dragula.min.js');
require('@uirouter/angular');

// Jquery UI
require('jquery-ui/ui/core.js');
require('jquery-ui/ui/position.js');
require('jquery-ui/ui/disable-selection.js');
require('jquery-ui/ui/widgets/sortable.js');
require('jquery-ui/ui/widgets/autocomplete.js');
require('jquery-ui/ui/widgets/dialog.js');
require('jquery-ui/ui/widgets/tooltip.js');

require('expose-loader?moment!moment');
require('moment/locale/en-gb.js');
require('moment/locale/de.js');

require('jquery.caret');
// Text highlight for autocompleter
require('mark.js/dist/jquery.mark.min.js');
// Micro Text fuzzy search library
require('fuse.js');

require('moment-timezone/builds/moment-timezone-with-data.min.js');

require('expose-loader?URI!urijs');
require('urijs/src/URITemplate');

require("expose-loader?I18n!core-vendor/i18n");

// Localization for fullcalendar
require("@fullcalendar/core/locales-all");


## DESCRIPTION
## Linear Algebra
## ENDDESCRIPTION

## Tagged by tda2d

## DBsubject(Linear algebra)
## DBchapter(Inner products)
## DBsection(Orthogonal and orthonormal sets)
## Date(July 2013)
## Institution(TCNJ and Hope College)
## Author(Paul Pearson)
## Level(3)
## Static(1)
## MO(1)
## TitleText1('Linear Algebra with Applications')
## AuthorText1('Jeffrey Holt')
## EditionText1('1')
## Section1('8.1')
## Problem1('')
## KEYWORDS('bases' 'basis' 'matrix')
DOCUMENT();        # This should be the first executable line in the problem.

loadMacros(
  "PGstandard.pl",
  "MathObjects.pl",
  "MatrixCheckers.pl",
  "PGcourse.pl"
);

TEXT(beginproblem());
$showPartialCorrectAnswers = 1;

Context('Matrix')->variables->are('x'=>'Real','y'=>'Real');

#$v1 = new Matrix(3,1);
#$v1->assign(1,1, -1);
#$v1->assign(2,1, -1);
#$v1->assign(3,1, 1);

$v1 = Matrix([-1,-1,1])->transpose;

$W = Matrix([['x'], ['y'], ['x + y']]);

Context()->texStrings;
BEGIN_TEXT
Let \(W\) be the set of all vectors \( $W \) with \(x\) and \(y\) real.
Find a basis of \(W^{\perp}\).
$BR
$BR
\(\Bigg\lbrace\)
\{ $v1->ans_array \}
\(\Bigg\rbrace.\)
END_TEXT
Context()->normalStrings;

ANS($v1->cmp(checker=>~~&basis_checker_one_column ));
;
ENDDOCUMENT();


<?xml version="1.0" encoding="UTF-8"?>
<config xmlns="http://www.knime.org/2008/09/XMLConfig" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.knime.org/2008/09/XMLConfig http://www.knime.org/XMLConfig_2008_09.xsd" key="settings.xml">
<entry key="factory" type="xstring" value="org.knime.base.node.util.sampledata.SampleDataNodeFactory"/>
<entry key="node-name" type="xstring" value="Data Generator"/>
<entry key="node-bundle-name" type="xstring" value="KNIME Base Nodes"/>
<entry key="node-bundle-symbolic-name" type="xstring" value="org.knime.base"/>
<entry key="node-bundle-vendor" type="xstring" value="KNIME GmbH, Konstanz, Germany"/>
<config key="factory_settings"/>
<entry key="node_file" type="xstring" value="node.xml"/>
<config key="flow_stack"/>
<config key="internal_node_subsettings">
<entry key="memory_policy" type="xstring" value="CacheSmallInMemory"/>
</config>
<config key="nodeAnnotation">
<entry key="text" type="xstring" value="read 100 rows"/>
<entry key="bgcolor" type="xint" value="16777215"/>
<entry key="x-coordinate" type="xint" value="767"/>
<entry key="y-coordinate" type="xint" value="360"/>
<entry key="width" type="xint" value="106"/>
<entry key="height" type="xint" value="15"/>
<entry key="alignment" type="xstring" value="CENTER"/>
<config key="styles"/>
</config>
<entry key="customDescription" type="xstring" isnull="true" value=""/>
<entry key="state" type="xstring" value="CONFIGURED"/>
</config>


{capture assign="page_title"}{$owner.username} | cameras{/capture}
{include file="inc_head.txt"}

{if $is_own}Your cameras{else}{$owner.username|escape}'s cameras{/if}

{foreach from=$cameras item="data" key="camera_make"}

 1}you have taken {$data.total|escape} photos with this make of camera{else}you have taken one photo with this make of camera{/if}">{$camera_make|escape}

{include file="inc_camera_models.txt" models=$data.models no_parent_links=1}

{/foreach}

{include file="inc_foot.txt"}


/*=========================================================================

  Program: GDCM (Grassroots DICOM). A DICOM library

  Copyright (c) 2006-2014 Mathieu Malaterre
  All rights reserved.
  See Copyright.txt or http://gdcm.sourceforge.net/Copyright.html for details.

     This software is distributed WITHOUT ANY WARRANTY; without even
     the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
     PURPOSE.  See the above copyright notice for more information.

=========================================================================*/
#ifndef GDCMMODALITYPERFORMEDPROCEDURESTEPCREATEQUERY_H
#define GDCMMODALITYPERFORMEDPROCEDURESTEPCREATEQUERY_H

#include "gdcmBaseQuery.h"

namespace gdcm
{
/**
 * \brief ModalityPerformedProcedureStepCreateQuery
 * \details contains: the class which will produce a dataset for n-create for Modality Performed Procedure Step sop class
 */
class GDCM_EXPORT ModalityPerformedProcedureStepCreateQuery : public BaseQuery{
  friend class QueryFactory;
public:
  ModalityPerformedProcedureStepCreateQuery( const std::string & iSopInstanceUID );

  gdcm::DataSet GetRequiredDataSet() const;
  bool ValidateQuery(bool inStrict = true) const override;
  UIDs::TSName GetAbstractSyntaxUID() const override;
};

} // end namespace gdcm

#endif // GDCMMODALITYPERFORMEDPROCEDURESTEPCREATEQUERY_H


"""Tests for KerasTuner distribution utilities."""