As described in Sect. 3.3, geometric characteristic of eNBs is a major positioning impairment which can affect the performance of trilateration based positioning; however, the conventional methods do not utilize the characteristics of hyperbola equations, when they perform weighted averaging in multiple OTDOA based method.

in this paper, we propose a novel weighting method which can reduce the weighting value of several OTDOA from unsuitable deployment of eNB in terms of geometric characteristic.


Three different algorithms are proposed for performing with the proposed switching circuit in order to achieve both energy harvesting and data communication from Wi-Fi signals.

the attenuation sharply increase when the distance increase, on the other hand the received signal strength decrease.


The important point is that the increase in the number of coordination sets imposes an overhead on the processing resources (BSs) and on the backhaul (X2 links).

there should be a trade-off between the number of coordination sets, and the overhead on the BSs and the backhaul.


This way, we are able to study the effects of upload algorithms on the UEs performance while the UE's distance from their serving BSs increases.

we used the CD++ toolkit as the platform to implement the DEVS models.


Regarding availability, quick fail-over in case of emergencies is challenging [82,88].

higher redundancy is needed a priori to achieve acceptable availability.


Subsequently, we present a general algorithmic framework to solve the QMRP in an online manner.

given the computational complexity of the problem, we employ a sampleselect approach, where in the first stage, a set of feasible paths is sampled, and subsequently one of them is selected for the actual embedding (cf. Section 4.2).


To evaluate the potential of CXPs, we map the global Internet substrate for pathlet stitching over IXPs.

we outline a novel abstraction of the Internet topology, in which vertices are IXPs and edges are virtual links connecting two IXPs over an ISP.


Thus, many servers will synchronously transmit data to the same server in data center networks.

it is desirable to design a transport protocol with zero packets dropping even there are massive concurrent flows.


Thus, the flow needs another round to take back the new congestion window W [n + 1].

in TFC, a flow will send a marked packet without any payload after the flow establishment phase to take back proper congestion window.


Thus, fast convergence can be satisfied.

3) Switches do not need to maintain states for each flow and the transport control function at end hosts become more simple.


Fastpass [31] uses a centralized arbiter to determine the time at which each packet should be transmitted as well as the path to use for that packet.

the scalability of Fastpass is limited by the centralized arbiter that needs to deal with all the packets.


This is because each flow has the same congestion window and flows n3 pass fewer hops than flows n2.

the goodput of flows n3 is a little larger than flows n2.


The source then transmits 1,500-byte packets that are received and forwarded by DF s relaying design.

the destination applies DF s ML decoding to decode the packets and measure the error rate to map the real decoding SNR.


However, note that a relay system is especially helpful when the source-destination link is too poor to ensure reliable transmissions.

the reasonable operation range of a relay system is when SNRsr > SNRsd , which means that PDF is a better relaying choice in practice.


Section 4 introduces our DF design, and Section 5 discusses some practical issues.

amplify-and-forward [1][2] is the simplest relay approach that amplifies the received signals and forwards them to the destination.


The key idea is to use the short Beam Sounding frames to probe alternate fail-over sector pairs before falling back to BFT.

mOCA retransmits the Beam Sounding frames first by traversing one level higher in the beamforming codebook, yielding a widened sector.


We implement all algorithmic aspects of MOCA in software and couple it with the FPGA software-defined-radio WARP combined with a 60 GHz frontend.

we implement a 60 GHz programmable node and testbed using VubIQ [19] transmitter and receiver waveguide system, operating in 57-64 GHz unlicensed frequency band with 1.8 GHz bandwidth (compliant with 802.11ad).


Wider beamwidth selection, on the other hand, results in sector pairs with more resilience towards mobility, at the cost of lower data rates.

in MOCA, we devise an algorithm to dynamically adapt beamwidth in response to mobility such that the average link throughput is maximized.


A successful transmission results in a bit rate of r(B) for time tslot, whereas breakage leads to training penalty tBF T .

in MIMO systems below 6 GHz, multiple streams and diversity are achieved exploiting the rich scattering propagation that is not present in the 60 GHz environment nor with switched narrow-beam antenna arrays.


In contrast to IEEE 802.11n/ac techniques to support multiple spatial streams with multiple RF chains [2], 802.11ad requires only a single RF chain for the antenna array.

802.11ad realizes Tx and Rx beamforming via analog phase shifters that are configured according to a predefined codebook of beamforming coefficients, with each codebook entry referred to as a sector.


As mentioned in Section 6.1, when there is no variation around the tags, the HL-interval of each tag is stable and distinguishable.

we collect signals from 5 Alien tags in a stable environment and distinguish them using their HL-intervals.


We show the ESD trends of two tags in Fig. 11 (a) and (b).

according to Equation 4, we can infer that when H is getting closer to T , the amplitude of the oscillation will become larger.


The failure of the above attempt implies that the COTS reader cannot a.ord the distinction on the approach behavior towards a specific target.

we design a monitor, which sits near the tagged object and passively listens to, records, Table 1: Reader Commands and Parameters and analyzes the RF communication between the COTS reader and tags.


As the ID or identifier of each tag, the EPC memory contains PC, EPC and CRC-16, which are stored in the order of the most significant bit first (MSB).

pC is 16-bit long, and its first 5 bits (denoted as PC5 ) define the EPC length.


Our emulator creates and manages virtual nodes according to user requirements.

the resulting emulated opportunistic network is composed of several opportunistic nodes.


In an opportunistic network context, end-to-end delays, delivery ratio and drop ratio are very important factors that developers want to study before deploying their applications.

this set of network-related metrics is not sufficient to describe the impact of those networks: developers also need to test their applications from a user viewpoint, and answer the question: Is my application working as expected?


To eliminate the errors in phase measurements, however, those existing systems either require high-cost dedicated hardware or labor-intensive offline training effort, which rendering them impractical.

they either use a dedicated hardware which is well designed without hardware diversity [2], or they use a learning based approach which regards the hardware phase errors as a constant that adds into the true phase measurement [4].


In the case of Macha Works, the Community Network LinkNet allowed for more community members to access the internet than just the leadership of institutions .

the network lowers the barrier for access for all community members.


Community Networks (CNs) are increasingly attracting attention from academics, donors [2], and policy makers [3].

they are being proposed as a potential solution to provide access to information and connection technologies in places where it is not profitable for the market forces to do [1].


The feasibility of creating dedicated bearers in LTE offers the potential to create such a bearer between the mobile device and an MEC server in the edge cloud.

the creation of every such bearer incurs additional overhead in the form of control messages.


The results indicate that until the network capacity is saturated (around 90 Mbps), the location of the MEC server plays the dominant role in the end-end application latency.

once the network capacity is saturated, the background traffic has a large impact to increase latency significantly in the conventional architecture.


In this paper, an underwater acoustic sensor node to perform the underwater sensing is designed and implemented.

we describe the design criteria, architecture and functional modules of underwater acoustic sensor node.


In practical, the signal approaches Gaussian distribution when large values of dispersion have been already accumulated.

a modeling error is expected for the first spans of an uncompensated system or at any number of spans for the dispersion compensated case where the residual dispersion is low.


Similar comparisons have been performed in [10,11] but they are limited in uncompensated systems only investigating just a moderate number of system parameters.

in [10] the impact of different span lengths and fiber types is not included while in [11] very restricted combinations of system parameters have been examined.


Mining these relationship will be useful to our work as well as other internet measurement researchers.

russian and Brazilian detoured paths fall mostly in the I st , IIIrd and IV th quadrant.


Typically the delay of the clock path is difficult to reduce from the initial routing result since clocks are normally hardwired with global routing resources; hence, our strategy is to add delay to the data path.

to correct the hold timing violation in our example, we must add 0.3 ns of delay across the two connections spanning between data in and register A.


The problem of solving long-path timing violations has received the vast majority of attention in past research [2].

in industry we must also solve the problem of short-path timing violations to guarantee functionality of routed designs.


Algorithms have been developed to synthesize application specific network topologies from a high-level specification consisting of connectivity and bandwidth/latency/energy requirements[10, 11, 14].

the approach[6] used by Cong et al. removes complexity from the generated network if it is known a priori that certain communication traces will never occur simultaneously.


Meanwhile, the changes to the GENIE variant yielded a small savings, requiring no major architectural changes.

gENIE's interconnect employs static, table-based routing, which is generated based on the logical Links defined by the designer in the input specification.


In a regular, homogeneous IaaS system, customizing an OpenFlow network would invariably involve software packet-processing using virtual machines.

in our infrastructure, we can use VFRs to accomplish this packet-processing at line rate.


To test the feasibility of this approach we used our source-to-source translator to instrument expressions whose results were likely to survive HLS optimization.

we instrumented several benchmarks from the assignment operations whose final result was an array read or write, add/subtract, multiply, or function call.


eCP was used for protecting hard errors.


When freeing a block, the corresponding no-use blocks are also reclaimed.

freeing a 16-page block in (1:2)-Alloc automatically forms a 32-page block after reclaiming its no-use buddy.


Write cancellation WC improves VnC but not significantly.

assume we use ECP-N where N represents the maximal number of errors that ECP can protect, and an adjacent line has accumulated X errors (WD errors and/or hard errors) before the current line write.


In this paper, we propose SD-PCM for achieving reliable write operations in super dense PCM.

we focus on mitigating WD along bit-lines such that we can construct super dense PCM chips with 4F2 cell size, i.e., the minimal for diode-switch based PCM.


Scaling PCM in deep sub-micron regime faces nonnegligible inter-cell thermal interference during programming, referred to as write disturbance (WD) phenomenon.

the heat generated for writing one cell may disseminate beyond this cell and disturb the resistance states of its neighboring cells.


At the device level, one bank stores 4096 SLC cells in one row, which spreads across eight PCM data chips.

one device row holds the content of one logical page in the OS.


In this paper, we propose to record error locations and values in the ECP region, and rectify the adjacent lines only if there are more errors than what ECP can handle.

writing adjacent lines requires additional VnC processing, resulting in cascading verification and large performance loss.


The straightforward way to encrypt data at runtime is to employ a one-way function such as AES, and use a global key, as shown in Figure 2(a).

if the same key is used for all lines, one can simply compare encrypted lines to figure out which lines store the same content, and employ a dictionary-based attack.


Disabling encryption and using FNW would improve the system performance by 40%, on average.

dEUCE bridges two-thirds of the performance gap between encrypted memory and unencrypted memory.


Our studies show that a typical writeback modifies, on average, only 12% of the bits in the cacheline.

dEUCE reduces the number of bit flips for an encrypted memory system from 50% to 24%, while incurring a storage overhead of 32 bits per line.


The reason why we are only concerned with the conflicts for the polygons creating a cutting line is because a polygon could be cut by multiple cutting lines but it creates exactly one cutting line.

the conflict cost of a path in the graph will not be over-counted and remain correct.


Because there is no coloring conflict between the polygons in different rows [8, 11], the TPL layout decomposition problem for each row can be individually solved.

the TPL layout decomposition problem can be considered as a set of single-row decomposition problems.


As we redesign the solution graph to be the simple solution graph for a cell, the solution graph for a BCP cannot be directly used to combine with a simple solution graph.

we also devise a reduced simple solution graph for the BCP of two adjacent cells ci and cj .


Besides, a polygon can be split into two sub-polygons by inserting a stitch to further resolve conflicts.

[1, 12] pointed out that even stitch insertion can not avoid coloring conflict in DPL.


The effects of passive elements (i.e. metal extensions with zero current) such as those added at cathode (reservoir), or anode (sink), or dummy vias have been investigated in many works [17].

a compact model suitable for CAD tools that can explain and model the underlying physics has not been proposed.


The total number of atoms must be equal in the initial state and in the steady state.

the number of atoms accumulated and depleted in different segments of the net is zero: ∫∫∫net Δc dV = 0


Although this model is very powerful, it does not capture the effect of segments adjacent to the path with the highest sum of the jL products, yet not belonging to it.

while the max jL product remains the same, the entire stress distribution might be affected by the segments not on the path with the maximum sum of
the jL products.


We use a practical approach based on the Bellman-Ford algorithm [5] to solve the NCD problem with a worst case run-time complexity of O(V E).

our algorithm performs much better than O(V E) on the average because it contains two early termination features.


It is well known that the variations-induced skew between sinks that are close in the topology is less than for sinks that are distant in the tree because of a lower point of divergence.

we propose to place the sinks corresponding to tight edges close in the topology, as shown in Figure 1(b).


As the cycle is of length 2, it is not possible to skew the margin in the cycle.

the maximum safety margin between the pair of sinks will be M no matter how the other safety margins are inserted in the tree.


We propose to insert a safety margin in each edge, or skew constraint, equal to the maximum margin of the edge (as defined in Section 2.1), with an upper limit of Muser.

only edges on the cycle with an average margin of M will have a safety margin of M. All other edges have safety margins strictly greater than M. All skew constraints corresponding to non-tight edges have a safety margin of Muser and do not require further consideration.


The SNES is measured with respect to a slack target of 5 ps.

sNES may still be negative although the WSL is positive.


This clustering score dc merely depends on netlist connectivity and circuit area.

many pairs of cells usually share the same score, which defers a great number of clustering choices to the actual implementation.


Similar as in FastPlace 3.0, we adapt the BestChoice clustering algorithm from [3], which iteratively clusters cells according to their netlist connectivity and size.

we compare ourselves to NTUPlace4 [13], the best participant of the contest, and to the tool of Cong et al.  [10] which achieved the best results on these benchmarks so far.


Besides netlength optimization, our framework is able to handle different objectives like timing and routability behavior.

for the congestion-driven mode of our tool, we present a heuristic which dynamically adapts the threshold used to estimate the criticality of a routing edge.


The quality of the placement has far-reaching effects on the whole design process.

the total overlap is low because only a small ratio of cells is moved.


The non-timing critical blocks can in theory operate faster, but they are synthesized at the frequency of the critical block to save area and power.

even with degraded transistors, these blocks can be synthesized to operate at the frequency of the critical block, albeit with a larger area.


Fabrication in sub-20nm technology is limited by the standard photo lithography process.

this helps in printing non-uniform device structures and in overcoming errors due to mask misalignment.


This architecture features two wide metal 1 (M1) power tracks and eleven M2 tracks for internal signal routing.

synopsys' initiatives also do not represent state-of-the-art technologies anymore.


Since the pattern generation in this method is performed by modeling the patterns in all free spaces at the same time, the dense wire patterns are pushed as far as possible from each other, so that the resulting routing is more evenly distributed.

this method cannot produce a globally even distribution, because its iterative characteristic might lead to a local optimal result.


This suggests that the QueueVadis client is pretty effective in estimating the real queuing delay experienced by a user.

given that the total wait time at the F&B venue was approx. 4 minutes (240 secs) and 10 minutes at Theaters, a 10% estimation error would translate to errors of less than minute at F&B and 2 minutes at Theater.


In Figure 5b, we compare each of the conditions with the nominal condition.

we see how many bits remain the same across multiple measurements at the nominal condition as well as the extreme condition under test.


In our observation of DRAM refresh and remanence properties, however, we noticed that certain DRAMs actually exhibit behavior similar to SRAMs, i.e. they have seemingly random startup values.

the cells do not initialize to 0 as would be expected.


In the nominal condition, DRAMs have 60% to 80% stable bits.

at high temperature the stability is actually higher at over 90% for three DRAMs).


In other words, we have a grid for memory rows and columns that can give us a very good picture of the cell distribution in the memory array.

spatial correlations (neighborhood stable cells) can be made in both x and y directions.


The LP based solution utilizes the simplex algorithm and in practice, runs faster.

note that with certain inputs, simplex algorithm may require exponential time to reach a solution [17].


The delay of the clock propagation path (the delay between the clock arrival time to the ICG cell and the clock arrival time to the register gated by this ICG cell) is at least the ICG cell delay and is bounded by the longest path within the local tree.

each ICG cell is associated with a lower and upper bound of clock propagation path delay.


Note that in existing SC-based LDPC decoders, the SB length is fixed and decided at design time.

we utilize the communication channel conditions quantified by the current Signal-to-Noise Ratio (SNR) to dynamically adjust the SB length on-the-fly to the minimum value for which the QoS requirements are still satisfied.


For such platforms, the additional data transfers cancels the performance benefits of the accelerated decision making.

existing fused architectures where the CPU and GPU share the same die, or even system-onchips integrating a CPU, an accelerator cards, and a NIC [6] have common memory spaces, and require no additional data copies.


Intuitively, the number of packets to be analyzed and forwarded in parallel should be limited by the number of cores that perform the analysis; for regular GPUs, one can have as many as hundreds such cores.

in practice, the number of parallel decisions is limited by the available memory bandwidth of the system: if every unit accesses memory in a short enough time interval, the memory bandwidth is quickly saturated, and the amount of concurrency in the system decreases.


Due to the dominance of MAC protocols over energy, a number of contributions have been made in their improvement.

contention based protocols can afford longer slots with large sleeping time and usually needs RTS/CTS exchange to enable collision free media access.


While stages 2 and 3 of our reference ConvNet can be perfectly split into 8—8 blocks and thus no performance is lost, Stage 1 has only 3 input channels and can load the core only with ..............=3/8.

stages with a small number of input or output channels also perform much less operations and efficiency in these cases is thus not that important.


The implementation of [18] suffers from the same issues, their superior energy efficiency in the processing core is gained with FDSOI technology which could also be applied to our architecture.

the effective throughput thus depends on the size of the image: ..............=(h....-h..+1)(......-....+1)h........... Table 2: Throughput and efficiency for the individual stages of our reference ConvNet.


As Cyclone always schedules instructions speculatively, a replay mechanism is implemented by using scoreboarding logic at the functional units.

when an instruction exits the queue, it checks if its operands are ready.


The counter is decremented by two on cycles where an L1 miss takes place, and incremented by one otherwise.

to get relevant numbers, we identify a region of interest in each benchmark using Simpoint 3.2 [21].


Although this lengthens the dependency chain of the second load, scheduling misspeculation associated with cache bank conflicts nearly vanish.

if bank conflicts are not predicted in some fashion, they always cost issue-to-execute cycles whether dependents were scheduled assuming an L1 hit or not.


Here, the processor tracks all the instructions that are in the shadow of a load.

all the instructions that have been issued at least load-to-use cycles after the load and that are inflight between the Issue stage and the Execute stage.


In our framework, two accesses conflict if they access a different set in the cache but map to the same bank.

two accesses to the same set do not conflict, as we consider a cache organization with a Single Line Buffer having two read ports, as described by Rivers et al. [22].


The choice of whether to put an instruction in the replay loop or in the replay queue is made by the checker.

not to be mistaken for the speculative scheduling of Stark et al. which relates to the atomicity of Wakeup & Select in the scheduler [26].


The former because µ-ops would have been replayed, and the latter because dependents would, again, have paid issue-to-execute cycles instead of bank-conflict delay cycles before re-executing.


In non-linked data structures, for example, such as simple arrays and matrices, a sequential access may depend on a running index and not on the outcome of recent accesses (and can also be prefetched by simple stride prefetchers).

we still preserve weak data dependency through the index variable that is being incremented, and consider such cases as manifestations of semantic locality.


Moreover, identifying program semantics is particularly difficult when relying only on the executable binary, which lacks type and symbol information, and whose code is mangled by compiler optimizations.

we can only approximate semantic locality.


In contrast, PBFS-biased’s false-positiveinduced rollbacks slow down the main threads’ critical paths resulting in high performance loss.

sRT-iso fares much better than PBFS-biased.


Like conventional replay, our replay re-executes all the preceding instructions irrespective of whether the triggering instruction is (transitively) dependent on a preceding instruction.

this process assumes, similar to [19], that a fault is masked if it does not affect the processor state after the run-window.


A full rollback is expensive because our false-positive rates are low but non-negligible, and avoidable as we show below.

rename faults reach the filters upon instruction completion by which time many later instructions have been fetched all of which have to be squashed.


A previous scheme employs bit-mask filters to capture value neighborhoods.

the scheme achieves low coverage improving which results in high false-positive rates, and performance and energy overheads.


Because there is only one squash state machine for all the bit positions of a first-level filter, the cost is minimal.

we implement the delay via a small delay buffer that holds a few recently-completed instructions (e.g., 6-8) for potential replay in the near future, as shown in Figure 4.


Because front-end stages are reexecuted in current pipelines only by a full pipeline rollback, we propose to squash for rename faults.

to avoid the performance and energy penalties of full rollbacks for every trigger, we need to distinguish between rename faults and false positives.


However, while replay re-executes instructions following a load, a soft-fault trigger implies that a nearby preceding instruction was likely corrupted.

we propose a mechanism to replay nearby preceding instructions upon a trigger.


Overall, these results show that FaultHound achieves both good coverage and good false-positive rates, meeting the challenge stated in Section 2.2.

the remaining faults are binned as SDC, only for which we report coverage.


In the case of the commercial workloads, SRT-iso can hide the extra copy under the cache misses of the main thread, incurring low performance degradation.

pBFS-biased s false-positiveinduced rollbacks slow down the main threads critical paths resulting in high performance loss.


Because our proposal is a best-effort scheme, the preceding instructions may pre-maturely exit the issue queue and miss the opportunity to be replayed, resulting in loss of coverage.

a full rollback squashes all previous instructions in the pipeline so that the first instruction that was corrupted by a fault, as well as all later instructions to which the fault has propagated, are likely squashed.


ESP can exploit the above characteristics of events present in a large number of asynchronous applications -mobile and web 2.0 applications, desktop GUI applications, IoT, sensor networks.

events in web servers and node.js applications are either independent or do not hold up processing of future events, making it easier to expose event-level parallelism, without needing ESP.


Also, this training happens so prematurely that other branches would have overridden it by the time it is needed.

if we are able to keep the branch predictor trained on branch outcomes of just enough future branches, it will have trained on the most relevant branches to perform well.


Fortunately, asynchronous programs also provide us with new opportunities for optimizations that are absent in synchronous programs.

if we want to reuse the computation from the pre-execution of an event, we would have to invest in some fairly complex hardware to check for any dependencies between events and recover from mis-speculations.


The entire cluster is pipelined and is implemented with a data-driven flow control mechanism using a ready state bit in the reconfigurable datapath.

mAD's versatility frees future accelerator designers from having to redesign and rethink interfacing to the core and provides a general and efficient mechanism, freeing them to focus on computation mechanisms alone.


FP benchmarks tend to be highly predictable, have low I$/ D$ miss-rates, and good MLP.

these benchmarks also feature quite biased forward branches and large basic blocks, which often permit the branch resolution to be scheduled in such a way as to avoid stalling the in-order.


While some machines will issue post-branch instructions in parallel with branch instructions (e.g., the DEC Alpha 21164 [11]), the benefit of doing so is limited, as the primary impact of control dependence is on compiler generated code schedules [20, 31].

even with perfect branch prediction, control dependence impacts performance on in-order machines.


This is because, by the time a long-latency load event has been seen, it is already too late to try and prefetch its result.

prior works have focused on executing forward slices after a miss event [4, 8, 15, 18, 26], as it is relatively easy to propagate poison bits to squash future instructions or store them for later processing.


For our silicon-photonic NoCs, we consider monolithically-integrated links [13, 25, 26].

conservative and aggressive designs employ different parameters for the photodetector sensitivity and laser efficiency (-17 dBm vs. -20 dBm in the former, and 20% vs. 30% in the latter, respectively).


However, with the decreasing size of the semiconductor technology process, the static dissipation is increasing due to rising leakage currents and is becoming the major component of the power consumption.

when evolving digital circuits with respect to the power consumption, the area of the circuit can be used to estimate the power consumption [13].


We now demonstrate how the single-core processor of Sec. 4.1 may be converted into a dual-core processor with secure shared state.

we will extend the design of Sec. 4.1 essentially by instantiating two copies of the processor core, and wrapping them with a secure harness whose design is akin to a softwarebased monadic separation kernel [15].


Caisson [20] is based on a classic security type system [32] for a Verilog-like hardware definition language.

security in Caisson inherits the strengths and weaknesses of the type-based approach; i.e., security is statically checkable, but some secure programs are excluded.


Generally speaking, the energy efficiency of a power converter is high when its input and output voltages are close to each other.

due to the high voltage of the vehicle battery pack [9], the string charger architecture has the potential for achieving high overall system efficiency.


In addition, high-voltage or highcurrent gate control is required for switches in the reconfigurable vehicular PV array.

we implement an IGBT (insulated-gate bipolar transistor)-based reconfiguration switch network to meet the above mentioned requirements.


In the sensorless PV array reconfiguration framework, the timing and energy overheads are larger due to the solar irradiance estimation procedure.

it is beneficial to make the sensorless framework also event-driven in order to limit the total number of reconfigurations and thereby total timing and energy overheads.


If additional latency is then added to sub-circuit B, it will have only a minor impact on the overall circuit's total execution cycles.

extending the latency of computations (i.e.the schedule) in sub-circuit B ensures that the critical path of the overall circuit is not within B.


They develop an efficient algorithm to discover and constrain all multi-cycle paths in a circuit, while considering every reachable circuit state.

[3] does not report the speedup offered by multi-cycling in isolation; rather, it presents results for multi-cycling combined with bitlevel optimizations and control-flow graph restructuring.


A growing portion of chip area and energy consumption is expended in caches.

emerging memory technologies such as spintronic memories that promise high density and low leakage power are of great interest in cache design.


In order to access a bit stored in the tape, we need to shift the head to the desired location on the tape via the shift controller and then perform the required operation.

the access latency for a given bit stored in such a structure is variable and depends on the number of shift operations performed.


Benchmarks (all benchmarks used in this paper are circuit matrices) are obtained from University of Florida Sparse Matrix Collection [19].

if matrices change dramatically, re-pivoting will always happen.


If so, we still use the same pivot choice as the previous factorization (line 13) so the symbolic structure of column i will not be changed.

speedup of the proposed solver compared with NICSLU.


However, searching for all dependent columns from the subsequent columns will traverse all the subsequent columns so it is timeconsuming.

we use a simple method that once a re-pivoting occurs, all the subsequent columns are computed by the normal factorization algorithm.


When a channel break happens on a transistor of a DP TIG-SiNWFET gate, the redundant structure of the pass transistors masks the e.ect of faulty transistor.

the black curves belong to the fault free device.


From the experimental results we conclude that the single bit faults (if injected) were biased at a particular bit position irrespective of the initial register states.

the frequency of occurrences of single bit faults varied for different key-IV pair initializations of the cipher.


To face with this problem, several emerging communication architectures such as 3D-stacked NoC, optical, and wireless NoC (WiNoC) architectures have been proposed [4].

the latter use a wireless backbone upon the traditional wire-based NoC [5], with the introduction of new elements such as antenna and transceiver.


Woo and J. Kim, Diversifying wear index for MLC NAND .ash memory to extend the lifetime of SSDs, in Proceedings of the 11th ACM International Conference on Embedded Software (EMSOFT 13), 2013.

this result implies that the proposed subpage programming can significantly improve the lifetime of flash memory in handling small writes.


It is demonstrated that neural network accelerators significantly reduce energy consumption [2] and at the same time exhibit a broad application scope [3].

neural networks can well accommodate the emerging high-performance machine learning applications such as recognition, mining, and synthesis (RMS) [4].


In this paper, we leverage the error resiliency of neural network to mitigate timing errors in NN accelerators.

when timing errors significantly affect the output results, we propose to retrain the accelerators to update their weights, thus circumventing critical timing errors.


Such phenomenon, however, limits the effectiveness of timing speculation due to the performance/energy penalties associated with timing error correction [9].

when errors occur in a timing-speculative circuit, the system needs to be rolled back to a pre-error state for re-computation (usually with slower frequency), which incurs both performance penalty and extra energy consumption.


They proved that conflict free memory mapping always exists to tackle collision problem for any code.

it is based on a simulated-annealing algorithm in which one cannot predict when the algorithm will end and the final architecture is not optimized.


Parameters and variables From the [O] model, we recall that a tile represents the minimal area unit considered within the FPGA grid and we denote by tileW and tileH its width and height respectively.

following one of the few approaches existing in literature, we use a Node-Arc model (better described in Section II) similar to the one used in [17] where each node is a Reconfigurable Region (RR), thus allowing high level analysis.


(1) Each multi-pin interconnect is viewed as multiple segments, each representing the signal path from the driver to a receiver.

for an interconnect with one drive (X) and two receivers (R1 and R2), we will try to characterize the delays of two segments, namely, X-to-R1 and X-to-R2, respectively.


In this work, we have presented a more flexible architecture on which the VOT-based delay characterization can be more easily applied.


As a result, the ECC is redefined to protect the other half of the content.

the ECC capability is implicitly doubled.


Besides, excessive use of bypass switches increases the cost of cooling system.

there is a trade-off between the number of switches and the power saving provided by this approach.


However, the interconnect parasitic capacitances that are major contributors to performance degradation and on-die signal integrity problems, must be accurately accounted for.

an empirical-based parasitic extraction is performed on an early-stage layout obtained from the floorplan, computing the optimal electromigration-aware wiring topology and shortest rectilinear paths in-loop, without the need for detailed routing.


Additionally, high-performance and highly-scaled CNFETs have also been demonstrated [Shulaker14b-c, Franklin12a].

cNFETs are promising candidates for building the next-generation of high-performance and energy-efficient digital systems.


We propose to write back the record to the two SSDs in the mirrored architecture, with one copy for each drive, and upon the system waking up, a correct record is loaded into the host.

in order to distinguish the correct record upon an alteration of the records by a maliciously implemented FTL, the records stored in both drives must be authenticated.


Our vector IR is similar to the original TCG IR, but the parameters buffer we put is the offset of the guest CPUState and guest SIMD registers, rather than the register's number.

we can simply and efficiently perform address calculations when generating guest SIMD instructions.


Because multiple reads are generated from a similar location in the DNA sequence, it is highly probable that multiple reads contain the same k-mer.

if the occurrence of a k-mer is very low we can assume that the kmer has erroneous bases.


Although the amount of speedup achieved is signficant, it must be noted that our implementation has not utilized the full capabilities of the FPGA device.

it is designed to scale to a larger number of threads without hassles by tweaking parameter values in the source code.


The VCO is commonly used as a voltage-to-frequency converter in ADCs.

the performance of the VCO based ADC is limited by the nonlinear behavior of the VCO, frequency drifts over time due to 1/f noise, and process, voltage, and temperature variations.


The technique proposed in the previous Section IV avoids entirely the usage of delay tables, but requires a large number of multipliers instead.

note that at the already at today s 20nm node, 3D-stacked Virtex UltraScale chips [20] feature twice the LUT count of the Virtex 7 family.


This concludes the proof of the theorem.

this measure captures the ongoing communication complexity of the scheme: In order to verify that the predicate holds, it is assumed that periodically, nodes transmit their labels to their neighbors, and each node runs the local veri.cation procedure on the complete neighborhood s label set.


In a configuration Gs, we are given a graph G = (V , E ), a state space S, and a state assignment function s : V → S. The state of a node v, denoted s(v), includes all local input to v

in a configuration Gs, we are given a graph G = (V , E ), a state space S, and a state assignment function s : V → S. The state of a node v, denoted s(v), includes all local input to v


Second, the exact value of the probability parameter E is typically not very important.

the correctness of all the schemes in this paper is oblivious to E, in the sense that E can be chosen as close to 0 as desired by straightforward adjustments of our schemes.


The goal and the prover in an RPLS remain exactly as defined for PLS.

in an RPLS the verifier v has access to a source of independent random bits at each node.


We design packet processing algorithms to extrapolate RSS values from legacy WiFi packets emitted by uncontrolled wireless devices.

we can reduce the RSS noise by orders of magnitude, thereby substantially amplifying the tiny radio RSS disturbance caused by the target's audio vibration.


However, we show that several pragmatic counter-measures may make the eavesdropping significantly hard and thwart adversaries.

we analytically provide a guideline of safety distance for a reflective victim and propose PHY-layer power randomization mechanisms for an emissive victim, which can reduce the eavesdropper's recovered audio quality by orders of magnitude.


When targeted at vanilla PC or smartphone loudspeakers, the attacker can successfully recover high-quality audio even when blocked by sound-proof walls.

we propose several pragmatic countermeasures that can effectively reduce the attacker's audio recovery quality by orders of magnitude.


Cyclostationary is complex and requires priori knowledge even though it is good at low SNR and requires high sensing time.

in a smart home environment, where the sensing time and priori knowledge comes into play, energy detection method is preferred to other.


We conduct the analysis through a stochastic approach, since the synaptic transmission is inherently stochastic.

we first analytically characterize the stochastic filtering of the spike train performed by each presynaptic terminal.


The aim is to develop radically new medical diagnosis and treatment techniques.

several questions and challenges arise to design a fully functional intrabody nanonetwork deployed inside the nervous system.


In both cases, the second capture clock pulse must be running at the nominal (normal mode) operating speed of the circuit under diagnosis.

in this case as well, scan output compaction schemes drastically reduce the diagnostic resolution.


As a result the frame-level RMS energy of the filtered baseband signal mostly corresponds to the presence or absence of body movements (figure 3).

there may be some frames where relatively high RMS energy may be caused due to aperiodic changes in the machine (e.g when the machine switches) (figure 3).


Also we can observe that orientation A yields relatively smaller error rate.

it still requires the user to either place a smartphone in their vicinity or wear a wristband while sleeping.


The runtime overhead breakdown for 100 fault-free iterations is shown in Figure 6a.

we immediately make a copy of the user-specified host memory contents to an internal host buffer and convert the blocking call to a nonblocking call.


The relative recovery time3 increases as we apply more optimizations because these decrease the VOCL-FT overhead and make executions more efficient.

when referring to (or plotting) a new optimization, those previously discussed for that particular experiment are also leveraged.


In addition to the improved QoS for endusers, CDN hosting makes a content publisher's service more scalable and reliable, saves the publisher money by reducing the load on their network backbone, and boosts pageranking on search engines [11].

an increasing number of content publishers, ranging from small personal webpages and blogs [10] to large-scale social networking websites, are hosting their content on CDN systems.


The GFW avoids IP address filtering in blocking CDN content because of its significant collateral damage, i.e., blocking (popular) non-forbidden content.

iP address blocking of forbidden websites hosted on a CDN network will disable all the legitimate websites hosted by the same CDN provider as well.


Fortunately, the Internet has been gradually diverging from the old end-to-end communication paradigm by embracing modern forms of communication.

caching Internet content, practiced to improve performance, security, and reliability, has revolutionized the way content is being communicated on the Internet.


The censors can alternatively block all IP addresses of the target CDN domain.

we have implemented a SWEET server on a Linux server in Amherst, which listens for incoming emails from Cache-Browser clients targeted to a specific email address.


Proxy-based circumvention systems, including domain fronting services like meek, FireFly proxy, and Flashlight proxy, are online services that are solely used for censorship circumvention.

the censors can pressure their hosting web services to entirely remove them.


The use of a private CDN can provide better control on content distribution and better privacy protection, however, its maintenance (e.g., ensuring security, reliability, and availability) may be complicated, costly, and prone to failures.

except for giant content producers, typical content publishers tend to use shared CDN services powered by commercial CDN providers.


We design a system called CacheBrowser that leverages the censors challenges in blocking CDN content.


Thanks to the business competition between numerous commercial CDN providers, offering low-cost or even free [13] CDN service, CDN hosting has become affordable even to host personal websites [10] and blogs [12].

some providers offer free CDN hosting services [13], including CloudFlare, Incapsula, CoralCDN, and SwarmCDN.


Many of these behaviors are physical such as punching or kicking.

there is no such a system for the vocal agitation metrics of Cohen-Mansfield Inventory.


From equation (4), we can observe that the leakage current is exponentially proportional to (Vgs-Vth).

layout of different approaches is also shown for fair comparison of different approaches.


These large LLC sizes, however, are beginning to challenge commonly held assumptions in operating system (OS) timeslice scheduling behavior.

fill times for large LLCs have grown to the point that they are a significant portion of the application’s scheduled timeslice, resulting in lost performance and efficiency, particularly in highly loaded, multi-process, multi-core environments.


With the large 16MB LLC, it takes a considerable amount of time for applications to load their working sets in the cache, thus the performance improvement increases from 15ms to 30ms timeslice length due to the increased amount of time to amortize LLC cold start cache misses.

beyond 30-45ms timeslices, there is only marginal performance improvement since the applications working set data is then loaded in the LLC and the cold start penalty amortized.


On the contrary, the graph workloads for dynamic graphs perform heavy graph structure/property updates and involve complex code structure and access patterns.

it is non-trivial to convert these workloads.


Recently, the advances in 3D stacking technology re-initiated the interest in PIM architectures.

we can have the bandwidth in FLITs as following.


Hence, in this section, we choose the breadth-first-search (BFS) as the object of our analysis.

the irregular accesses patterns of graph properties don't exist.


In this paper, we design and implement a cost-effective RFID indoor localization system for locating objects attached with passive tags.

we deploy two guide rails, x-axis and y-axis guide rails, on the ceiling of a warehouse or workshop.


By using mobile readers mounted on guide rails, we design and implement a costeffective RFID indoor localization system, which requires neither reference tags nor RSSI functions, for stock-taking and searching in warehouse operations.

we install two guide rails, which can allow a reader to move horizontally or vertically, on the ceiling of a warehouse or workshop.


Timing was possible only for the two latter numbers because the starting time of the first key press was unclear.

all errors, including those made when pressing the first key, were recorded.


To avoid generating audible 200 Hz noise as a side-effect, every other channel was turned off by setting it to 0 and every other to 1.

the gross DC signal level of the entire array is kept at 50% at all times.


Whatever part of the hand or fingers was on the location received the feedback.

the feedback was given based on the key locations, not based on the hand location and shape.


It is also worth noting that the individual elements of the set of labels we are concerned with (⇤)can be thought of as composite labels.

one can consider labels such as Return Air Temperature to be a composition of many individual tags (in this case return , air and temperature ).


The emerging Multi-Level Cells (MLC) STT-RAM memory technology improves the capacity and energy efficiency issues of large-sized memory banks.

mLC STT-RAM incurs non-negligible protection overhead to ensure reliable operations when compared to the Single-Level Cells (SLC) STT-RAM.


To achieve high compression rates HEVC tries to match the block structure according to the object shape through a recursive partitioning process which exponentially increases the motion search complexity as it has to be performed for every block partitioning.

3) An Approximation-Aware Cache Management Unit (Section 4.3) that classifies a cache set as reliable (i.e. this set needs to be stored with reliability) or ‘unreliable’ (i.e. this set does no necessarily require reliability and can tolerate approximation errors).


When a set is classified as a USet, we improve the average associativity of the cache.

data stored in a USet is not protected against read and write errors.


to achieve high performance, HEVC supports a light-weight data-parallelism support by dividing the video frame into so-called Video Tiles


Similarly, disintegration into a larger number of smaller chips requires a corresponding increase in assembly steps, for which we also do not have relevant cost information available.

in recent years, fundamental physical limitations have slowed down the rate of transition from one technology node to the next, and the costs of new fabs are sky-rocketing.


While it makes sense to run each chip's portion of the NoC at the same clock speed (otherwise the slowest portion will likely become a bottleneck), from a physical-design perspective it is easier to clock chips independently.

each chip's NoC portion operates in its own local timing domain, thereby requiring domain-crossing synchronizing FIFOs when going from CPU chip to interposer, and vice versa.


Figure 9 compares the performance (execution time) of GS-DRAM, Row Store, and Column Store on the transaction workload for various values of i, j, and k (x-axis).

we extend each cache line tag in the cache tag store with p additional bits to store the pattern ID of the corresponding cache line.


Although each bank is further divided into smaller structures [12, 26, 28, 41, 47], for the purposes of understanding our mechanism, the following abstraction of a bank is sufficient.

pseudo-random mapping schemes [38] potentially incur a small number of conficts for almost any access pattern.


Unfortunately, this approach is very costly as it significantly increases the pin count of the memory channel.

we need a simple and low cost mechanism to allow the memory controller to effciently communicate different access patterns to the DRAM module.


The administrator can decide how many times she wants to check the tag by listing the proposed positions.

there is no need for going back to the server to set the new position.


The visibility of the tags was approximately the same with different seeing positions.

sensors cover all the lab area and the invisibility of tag happened for another reason, such as high interference in the lab.


In line with this, they would like to know if exercises caused any problems or complaints and whether the exercises were understood by the patient.

they emphasized that asking these questions will not be useful for every patient.


In order to deal with the size of the database, one could use one of a number of lossless compression techniques.

the database must be uncompressed eventually, meaning, while nonvolatile memory is reduced, the volatile memory must still be large enough to store the CRPs and ECC code words.


Prominent examples include two workshop series sponsored by the National Science Foundation (NSF) and Computing Community Consortium (CCC).

these workshops assess the inadequacies of current EDA funding and education, technological challenges facing the CMOS industry, and new markets to which EDA methods can be exported.


Prior approaches that attempt to overcome the computational bottleneck of error estimation can be classified into two categories: 1) Methods that estimate the range of error: These methods capture the range of the error in approximate computation in terms of its minimum and maximum value, and are primarily based on interval and af.ne arithmetic [11], with modi.cations [3], [10], [12] suitable for asymmetric distributions of errors in approximate circuits.

these approaches are computationally intensive, may lead to storage explosion [10], and often overestimate errors [13].


OpenCL [12] is finding some success, also in commercial tools [13].

having been designed mainly for vector-based processors, it does not adapt well to irregular applications.


Finally, the back-end generates the final circuit description in Verilog, together with the simulation and synthesis scripts that enables Bambu to directly interface with 3rd-party tools.

the Convey WX (Wolverine) accelerator is a PCI-Express drop-in solution that provides similar features.


To address the limitations of HPC systems, GEMS employs a runtime that provides: a global address space across the cluster, so that data do not need to be partitioned, lightweight software multithreading, to tolerate data access latencies, and message aggregation, to improve network utilization with fine-grained transactions.

designing accelerators by employing Hardware Description Languages (HDL) is hard and time-consuming.


Here the biased multiplier is assumed to truncate the lower bits without changing the value of the highest bit to 1 .


At the same time, these applications also afford new opportunities for novel low-power implementations.

the common feature of these application domains is an inherent tolerance for limited and insignificant inaccuracies.


We use Verilog to implement the applications in hardware and use DC compiler for synthesis.

we also use MentorGraphics ModelSim to evaluate the numerical output of the designs.


Abstract Short-reach nanophotonic interconnects are promising to solve the communication bottleneck in data centers and chip-level scenarios.

the nanophotonic interconnects are sensitive to process and thermal variations, especially for the microring structures, resulting in signi.cant variation of an optical link s bit error rate (BER).


Our simulation and analysis demonstrate that the proposed adaptive tuning approach scales well with respect to different process variations, thermal variations, numbers of clusters, and laser types.

the adaptive tuning could save more power for link structures with non-uniform communication path lengths and/or using comb lasers.


As illustrated in Fig. 8, the BER decreases when the received power decreases or when the sampling time deviates from the ideal sampling point.

the voltage offsetting method or the sampling time offsetting method could be leveraged to accelerate the BER test.


Threshold logic has been revisited as a promising logic style when considering emerging technologies, such as memristors, spintronics devices and tunneling diodes.

state-of-theart threshold logic synthesis tools are not based on specific technologies when defining cost functions.


Since the k-cuts are pre-computed in the input design, it is possible to mark a matchable/unmatchable label for each cut and indicate these marks to the technology mapper.

we filter those precomputed functions and indicate only TLFs to be matched.


As shown in Table 2, the overall modeling cost is dominated by the PN simulation in this example.

once the PoMs are chosen, we need to further build a performance model to approximate the NF as a polynomial function of the PoMs.


The key idea of CL-BMF is to pass the knowledge from the low-complexity model to the high-complexity model (i.e. co-learning) to reduce its training cost.

once the low-complexity model is accurately built based on a small number of training samples, the high-complexity model can be trained by borrowing the information from the lowcomplexity model, instead of relying on the expensive training data only.


Because an attacker uses JTAG differently from a legitimate user, it is possible to detect an unauthorized access using customized machine-learning algorithms.

a JTAG protection scheme, termed SLIC-J, is proposed to monitor JTAG activity, detect malicious accesses, and ultimately protect the JTAG from being misused [31].


We assign a data to be written to each cluster.

we generate a one-to-many mapping code from each data to the codewords in the corresponding cluster.


We cluster its codeswords and generate a cluster graph satisfying the S-bit flip conditions.

we generate one-to-many mapping from each data to the codewords in the cluster.


A pipeline module is called a full buffer, e.g., PCFB, if its input and output data channels can hold distinct data tokens at the same time.

a half buffer, e.g., PCHB, WCHB, and NCL, can hold at most one data token on both of its input and output channels.


Compared with linear programming based methods, TSE cannot handle cycle times in real numbers naturally.

it can only solve the problem that has an integer (or a finite decimal rational number) solution.


It is obvious that the two operations introduce no frontier pins as the gate being inserted or removed is not connected to the current circuit.

for gate-level design modifiers we only deal with the operation repower gate.


Both operations alter the structure of the design and directly affect the timing.

we need to identify the frontier pins that capture the incremental timing update for such changes.


This is the case when there is no time remaining to solve hardware problems.

correcting hardware problems in the software seems relatively easy (Alvarez Cabrera et al. 2010, Bradley 2010).


Over the past 40 years, many definitions were presented (Colorado State University 2012).

defining a mechatronic system precisely becomes even more difficult.


The duration of each talk was set to be eight minutes (exactly as in the .rst WACI session from 1998) plus two minutes for questions.

amusing elements in the presentations are tolerated ;-) but are in fact optional.


Instead of soliciting talks via an open call and hoping for the best, we proactively invited speakers whom we believe are capable of delivering excellent WACI presentations.

this year's WACI session consists exclusively of invited speakers


Six participants stated they feel more connected to people receiving shared information and their relationship is strengthened.

sharing may have adverse effects on sharers in case of not receiving adequate feedback [5]: P12: Depends on the information or feedback, sometimes feeling better, sometimes no change at all."


To the best of our knowledge, there is lack of studies focused on cache prefetching for CGRAs platform.

the CDPM mechanism is aimed at cache prefetching in CGRAs platform and operates at the context level.


However, inaccurate prefetching can waste limited memory bandwidth and induce pollution of scarce cache resources, limiting or even crippling CGRA performance.

existing prefetching techniques are aimed at instruction driven processors, where the decision to issue prefetch requests is based on historical information that relates to independent memory accesses.


Figure 6 shows the contents of the pattern cache.

13 dwarfs [23], which were defined to design and evaluate parallel programming architectures, were chosen as benchmarks for the study.


improve performance by predicting which memory addresses will be accessed in the near future and then speculatively issuing prefetch requests.

inaccurate prefetching can waste limited memory bandwidth and induce pollution of scarce cache resources, limiting or even crippling CGRA performance.


As we will discuss in Section 3.2, source-level transformations also have drawbacks in both complexity of evaluating coding styles as well as analysis to determine how code will be affected by optimization.

we use LLVM-IR and LLVM's debug metadata to track source correspondence without these limitations.


(f ) The violating cell c2 is swapped with c6 to form a larger implant area with c5, without any area overhead.

as feature sizes decrease, design rules have become more restricted.


In this case, only c2 is moved to be clustered with c1 and the initial clusters are maintained.

if the initial clusters are not good enough, it may significantly change the clusters to find smaller wirelength as shown in Figures 4(e) (f ).


By repeating the above procedures for all large eigenvalues, a good spectral graph sparsifier can be obtained.

computing the largest eigenvalue and its eigenvector can be too costly for large-scale graph Laplacian matrices, even when state-of-the-art eigenvalue decomposition methods are considered [18].


Note that the additional bandwidth may also be used to transfer up to cache blocks per read (instead of a single cache block as is done typically) if narrow-width values are present.

in this paper, we instead experiment with transferring 64-bit sets of data stored in the cache lines.


Moreover, one child said that his sense of the self and others was confused during the game and he felt like he became a different child.

it is believed that simulating different sensory experiences between ASD and TD and creating a place to realize such people with ASD has demonstrated pluralistic possibilities in the way people perceive the world according to different sensory experiences.


This type of sensory experience that blurs the boundary between the self and others is a phenomenon that has been commonly reported in the studies done by people with ASD.

it is believed that the device developed for this study is able to give TD people the ASD sensory experience.


The interviewee reported that a high percentage of the visually impaired students he tutors give up on mathematical learning goals, particularly in the area of geometry and primarily due to challenges in visualization of the concepts.

in line with formal statistics [4], he noted that visually impaired students do have the potential to excel in this area.


As a result, while combining multiple energy sources such as MFCs improves overall reliability and functionality, it also triggers other issues; for example, the highest generated output voltage constrains or excludes the contributions from other generated voltages.

multiple MFC outputs might not be combined to the load directly through multiple power converters.


It can be seen that some output voltages are higher than the load output voltage (e.g., Voutc2, Voutc4).

these converters output energy is directed to the load.


EC simple Power Attacks (SPA) that aim at power signal observation during PM computations so as to discriminate point operations, can be thwarted by employing PM algorithm variants (e.g. Montgomery Power Ladder (MPL) or double and always add algorithm [14]).

those variants are still vulnerable to refined PA and zero PA [12] or comparative SPAs (doubling and relatively doubling attacks [10] [19]) as well as differential power analysis attacks (DPA) [16] that can only be thwarted through PM randomization [8].


investigated various visual displays for communicating privacy risks and aiding users in avoiding privacy-invasive apps.

they studied the impact of framing e.ects (e.g., displaying how privacy-preserving vs. privacy-invasive an app is) on users perceptions of an app s trustworthiness.


Because risk is a multi-dimensional concept [15, 16], multi-dimensional risk information also needs to be displayed for users that want a more detailed view of the risks posed by an app.

the main focus of the present work was (1) to identify the most meaningful dimensions of risk and understand users perceptions of those risks, and (2) to better understand other sources of risk information (in addition to permissions) and how such information is used by experts and average Android users to assess apps.


Although this seems to indicate that the risk types identified by the expert users and used in this study are appropriately comprehensive, there may be better names or descriptions that could be used to convey the scope of the risk types.

a third of the responses described things that we consider to fall under the device instability risk type, which may indicate the need for a better descriptor for that risk type.


Different apps may expose users to different types of risk, such as ones involving data privacy, monetary loss, device instability, and data integrity.

any single approach to risk communication will be deficient for some users.


We coded each of the user-supplied group labels into one of 16 different summary labels based on the risk concept that it seemed to describe.

participants were given the following instructions: (1) sort the permissions into groups based on the type of risk that you feel is associated with each permission (a single permission may be assigned to more than one group); and (2) give each group of permissions a name describing the risk type.


For example, if the phisher is attempting to emulate PayPal, there are so many previous attempts made to phish PayPal that anything that is extremely close to PayPal social website URL is either already a registered domain, or is blacklisted.

in order for a phisher to emulate a Paypal URL, they have to start introducing misspellings, such as www.paypal.com, or they must construct another domain name to look like PayPal, such as www.paypal.com.anotherurl.com.


One possible argument for involving the server in password strength estimation is that the server can check passwords against a dictionary of common words/passwords or a known database of leaked passwords.

this only makes sense if the size of such a dictionary/database is significant (in which case the secure way to implement the service is to send salted and hashed passwords over HTTPS).


Currently, most CSPs offer performance metrics to measure the physical performance and system usage of a cloud such as CPU utilization, latency, and network throughput.

there has been little effort made on information assurance and security auditing metrics [2].


Another major obstacle to the widespread adoption of cloud computing is the lack of quantitative information about the security status of a CSP.

the security-related quantitative information helps cloud stakeholders in performing the robust and accurate cloud auditing of a potential CSP.


To show the practicality of the proposed metric, we provide two case studies based on the available security information of two well-known CSPs.

the proposed metric computes a security index based on the security preferences define by the cloud users.


Biddle et al. [5] state that a system provides resilience against keystroke/mouse loggers when the keyboard/mouse entries for authentication vary across subsequent login sessions.

the variant response feature in CuedR offers better resilience against basic keystroke loggers compared to a password system where the same letters are entered during every login session.


CuedR also shows that the cued-recognition class of password schemes, a new design point in the field, can be effective for user authentication.

cuedR addresses each of the features needed in an effective graphical password scheme, as identified by Biddle et al. [5] from their comprehensive survey on the graphical password literature.


Ideally, there should be a clear separation between the passwords used for low-security websites and high-security websites [7].

cuedR can be used as a standard authentication mechanism for online accounts with high security requirements and where logins occur relatively infrequently, such as financial (e.g., online banking, brokerage services) and e-commerce accounts [23].


Since there were six legitimate users, there were 30 legitimate match attempts and thus 30 finalized decisions for each feature.

the performance of the each feature measured as the percentage of legitimate user attempts were mistakenly rejected by the system, i,e, false negative.


Through this research, we assess the performance and influence of various keystroke features on keystroke dynamics authentication systems.

we investigate the performance of keystroke features on a subset of most frequently used English words.


It covers the whole range, from no relationship (0) to a perfect relationship (3, or -3), with -3 indicating a perfect negative relation; whereas, 3 indicating a perfect positive relation.

the most common effect-size measures are Pearson r or correlation coefficient and Cohen s d (also known as the standardized mean difference).


We assume that D outputs 1 (indicating RC4) with probability 1 - β when its input is from RC4, and that D outputs 0 (indicating truly random) with probability 1 - a when its input is truly random.

a is the false positive rate for D and β is the false negative rate for D.


We see that S is required to be greater, reflecting the much weaker performance of our blockwise distinguisher when the block size is small.

the total disk size is only moderately increased and the running time of the distinguisher is further reduced (because of the reduced block size).


In particular, the users can collectively re-compute some values Λi from the data available for the users.

there is no direct way to check whether Λi+1 = Λd i if the DDH Problem is hard for the group used.


Their experiments reveal that leveraging all the 2-hop neighbors of each node signi.cantly improves the network connectivity even in the case of high unavailability.

a much larger fraction of all online honest nodes belong to the largest connected component (LCC) with the Two-Hop overlay in comparison to that of the simplistic One-Hop overlay.


Common intrusion detection systems (IDSs) generally search for single events that either show clearly malicious or at least “unusual” characteristics.

sequence attacks do not involve such characteristics and are likely to pass through unnoticed.


For both scenarios, we adopt a non-naive attacker that has a sufficient amount of knowledge to inject valid-looking position messages.

we assume these ADS-B messages are well-formed and their content is reasonable and able to withstand a superficial sanity check.


If L were zero, then a would also be a single-class best response, since its only non-zero element would be ac.

when F is high, then the problem actually becomes easier, since the adversary s strategy space will be very limited (see Theorem 2).


To build a packer classifier, we need to select a model and train it with labeled data.

two main approaches for solving this problem have arisen.


However, they can be difficult to use due to the complexity of the XCCDF and OVAL file formats.

our solution uses oscap to provide assurance reports based on XCCDF files (because of its standard status) but automates the definition of the XCCDF files.


The assurance tests have to be consistent with the security policy that has been enforced.

the processed XCCDF file should include the assurance tests that have been generated, both for the properties and for the security mechanisms.


This concept [12][13] comes from the growing complexity of systems management.

there was a need for an approach that could ease the management of systems.


Enforcing security properties in a Cloud is a difficult task, which requires expertise.

it is not the only security-related challenge met by a company migrating to a Cloud environment.


Indeed, Cloud computing can reduce the costs of the infrastructure and improve the provisioning and access to resources.

cloud computing also comes with security issues [9]: for instance, due to the higher number of users and data, the Cloud offers a more interesting target for attackers.


The tests are done using the XCCDF format.

we define a security property that will be used to launch Oscap in order to process an XCCDF file generated by the S EE .


We refer to this as promiscuous conflict-free scheduling because it maximizes the mixing of vms in a given server so long as they do not conflict.

a conservative approach minimizes the co-location of vms even though their attribute values do not conflict.


Our intent here is to validate the thesis that we can wrap Mohawk in a manner that we preserve its scalability for ATRBAC policies.

mohawk+T would scale significantly better than what has been shown for existing tools for ATRBAC-safety [6, 12].


Note that as in prior work [6], we did not try this Benchmark Class on the other existing tools.

we have the somewhat interesting situation that no single tool can be said to be good with all the input ATRBAC-safety instances we have tried.


(4) Hagström et al. motivate the distinction between delete and negative revocations mainly through the notion of resilience as defined in Section 2.

in weak revocations there can be no difference between a resilient and a non-resilient revocation, since a weak revocation does not affect authorizations issued by others than the revoker.


In this paper we studied revocation for a version of delegation that does not have any bound on the length of delegation chains.

tDL lends itself very well also to delegation with such a bound.


Carrara and Adams measured the multi-path delay spread for a common single desk closeddoor office environment at upwards of 250 ms [9].

this work examines OOB-CCs from the perspective of a passive adversary and argues that a different methodology is required in order to effectively assess OOB-CCs.


The primary consequence of this bug is that a negative value injected into a histogram can result in a term that decreases rather than increases a x2 sum, creating a closer match.

there is a more sophisticated and nefarious property of this bug: a negative value of appropriately small magnitude will produce a negligible effect if compared to a zero, and a very large effect if compared to a nonzero value.


An image and its simple LBP image is displayed in figure 1.

since histogram values are nonnegative, no fabs() call is necessary; indeed, it allows a negative value for b to be included in the sum.


The intuition behind the proof is as follows: If the adversary corrupts the party that first receives the output, then he can provoke his most preferred event E10 by aborting before sending his last message.

because this party is chosen at random, this happens only with probability 1/2; with the remaining 1/2 probability the honest party receives the output first, in which case the best choice for the adversary is to allow the protocol to terminate and provoke the event E11.


As discussed above, the notion of utilitybalanced fairness connects the ability (or willingness) of the adversary to corrupt parties with the utility he obtains.

in the second phase, if .GMW did not abort, the protocol continues in two more rounds.


If hit and dirty, fetch from untrusted storage but do not store in cache.

the ALAP update policy causes MTs incoherence: during the update, when an intermediate node is written in the cache, the update stops and the upper nodes are not hierarchical digests of their children any more.


If we consider a connection to a Red (Open) network, the user adopts the typical behaviour, they click the network name.

instead of automatically connecting and being allowed to access the network, the user is prompted upon password entry that the network may not be secure (Fig 2).


Given a running program or an OS kernel, if we can locate its function pointers, we would have been able to check their integrity and detect the control flow violations.

current practice to locate a pointer in memory requires the data structure knowledge of the corresponding program.


Finally, the system performs key labeling of each cluster to recover each keystroke by examining the distance difference between the mean TDoA of each cluster to that of the theoretical TDoAs.

we conduct following experiments: as shown in Figure 16(a), we first use the Samsung Galaxy Note 3 to play a pre-recorded chirp sound signal via a earbud, which is to make sure the sound comes below neighboring key caps and thus has multipath effects, for 20 times at each target key’s position on a regular keyboard.


Although we do not study the sound intensity level of each key, we evaluate our system with three different kinds of keyboards (i.e., an Apple wireless keyboard MC184LL/A, a Microsoft surface keyboard and a mechanical keyboard Razer Black Widow Ultimate) that produce different keystroke sound intensity levels.

the keystroke sound from the mechanical keyboard is much louder than that from the Apple keyboard.


The basic idea of our system is to perform keystroke snooping leveraging the dual-microphone on a single smartphone through studying the fine-grained acoustic signatures inherent from key typing sounds.

we consider two processing approaches, namely Single-keystroke Based Processing and Set-keystroke Based Processing.


Moreover, the mean TDoA of the keystroke sounds emitted by the same key is very close to the corresponding theoretical TDoA.

we compare the mean values of the measured TDoAs of each cluster to the theoretical TDoAs.


Although some mobile devices have three microphones, for example iPhone 5s and Samsung Galaxy Note 3, neither Apple nor Google provides API to record 3-channel audio with three microphones.

our system must be designed in a way that it can accurately identify keystrokes based on the stereo recording of two microphones.


The solution named Piratte [8] seems to be suitable in our case.

it is able to revoke only up to a predefined numbers of users/attributes.


If it comes that the same person falls in a isolated location and needs help, activation to her/his location may be vital.

access control policy must be adaptive and context-aware.


My main objectives for attending the UbiComp 2015 Doctoral School are twofold: By presenting my PhD project to experts in the field I expect valuable feedback and input on the overall idea of multi-device authentication as well as the chosen approach.

i would like to discuss the implications on both usability and security as well as reasonable trade-offs between both properties.


This paper will not address all of the possible meanings.

we will describe the definitions that have had the greatest impact on our own efforts.


The proposed input generating technique is not only more efficient while generating valid inputs as compared to randomized inputs but also more easier to use than tools such as Monkey Runner.

the idea of the proposed input generator couples the simplicity of the random approach in the Monkey tool along with the benefit of ensuring valid inputs in the Monkey Runner tool while ensuring maximum code coverage.


AnserverBot is a malware that asks users for update and installs the malicious payload.

the services in the malware itself do not need permissions.


When a receiver is defined by intent filter, it lets the other app or components of the app send implicit intents to this receiver.

an app can define the intent filter in the receiver to obtain the implicit intents that may not target the particular application, for example, getting alarms or receiving messages from the system.


if a service is bound to a component, it has access to its public method.

it is indirectly connected to other components and will die as soon as other components unbind it.


However, this approach is not immediately applicable to the evaluation of network-based MTDs because these require entire networks in order to exhibit realistic and representative behavior.

experimental processes for network-based MTDs require automated network construction and configuration, as well as automated stimuli that operate on the network.


The analytical modeling related to P(At) in the context of wireless networks with random mobility has been widely investigated in the literature (e.g., [15 17]).

a wireless network with a random node distribution can be modeled as a random geometric graph, and P(At) is a function of node density, mobility model, and network size.


Software diversity creates many different copies from an initial version of a program: each copy of the protected program is different in its binary shape, but is functionally equivalent to other copies [24].

attacks designed to work with one version might not work with other customized versions.


MiniCPS focuses on high-fidelity network emulation, which allows simulated components to exchange very similar or the same traffic as seen in the real network, from Ethernet layer up to the application layer (based on Mininet, see Section 2.2).

we aim to not only provide an abstraction of the network to perform simulations on (similar to network simulators such as NS2 [12], OMNet++ [25]), but we target a network emulation that is largely identical to a real network, without the cost or overhead of running a real network or a set of virtual machines.


In particular, we aim to not only provide an abstraction of the network to perform simulations on (similar to network simulators such as NS2 [12], OMNet++ [25]), but we target a network emulation that is largely identical to a real network, without the cost or overhead of running a real network or a set of virtual machines.

this would allow us to develop components that are directly using industrial protocols to communicate.


We identify the issue of missing generic simulation environments for applications such as cyber-physical systems.

such simulation environments should support physical interactions, parametric communication links, and specific industrial (ideally all) protocols that are used.


MiniCPS does not aim to be a performance simulator, or tool for optimizations.

we consider that full-fledged physical process simulation is out of the scope of MiniCPS.


In [7], Dong et al propose a testbed that is similar to our MiniCPS platform in several ways.

they propose to use Mininet as network emulation platform, a power grid simulation server, and a control center simulation server.


Ontologies that are created by people who lack either expert knowledge or ontology development skills may result in serious problems and wrong results.

these questions assure the targeted value of the structure is achieved.


Also, even if the resources are sufficient, project teams may not think it is necessary.

we imported classes from SUMO and Finance ontology to use the classes that are already defined in financial domain, so that we didn t need to define new classes in the finance domain.


Considering that ontologies are a web of knowledge, integrating the ontology with other ontologies will create a bigger knowledge base and extend the opportunities of integrating this ontology with the existing systems.

to increase data and information quality within a domain, we need to create an ontology that can represent that domain successfully, and creating an ontology requires expert knowledge within that specific domain as well as the skills required to create it.


The remaining data items leak no further information, as long as encrypted with probabilistic encryption.

an attacker can learn the occurrence of a data item (e.g., via the histogram attack), however he can not gain access to the actual plaintext.


The location is potentially also sensitive.

talos applies deterministic encryption, allowing encrypted queries correlating heart rate with location.


This data leakage could be theoretically avoided by utilizing recent advancements in theoretical cryptography (i.e., fully homomorphic cryptosystem [23]) that enable any computations over encrypted data, without revealing any information.

these approaches are still computationally very expensive, rendering them impractical [55].


It is possible to find secure configurations using search algorithms and machine learning approaches suited for complex spaces [1, 17, 21].

these methods were developed for tuning parameters to improve system performance (user response times), not securing applications.


Following Google's best practices for developing secure apps, the password database is saved in the app data folder, which should be accessible only to the app itself.

this defines a hierarchical relationship between domains where the bounded domain cannot have more permissions than its bounding domain (the parent).


Our approach is to 1) build a System Object Dependency Graph (SODG) so that the intrusion propagation process is captured at the system ob ject level; 2) construct a MissionTask-Asset (MTA) map to associate the missions and composing tasks with corresponding assets, which are namely the system objects such as processes, files, etc.

if such dependency relations among services can be discovered and represented with specific graphs, then a task can be viewed as the instantiation of a service dependency graph.


To ensure the task is benign, the related system objects should be benign and the operations should be performed in the right sequence.

all of the parent nodes have the AND relation for the child node to be true.


The key difficulty lies in how to extract tasks from the SODG due to its daunting size.

the extraction is ensured to be feasible by the following principles.


Due to the current limitations of intrusion detection and forensic analysis tools, reconstructing attack scenarios from evidence left behind by the attackers of an enterprise system is challenging.

reconstructing attack scenarios by using the information from IDS alerts and system logs that have a large number of false positives is a big challenge.


The system has a mechanism to develop additional rules, facts and actions, based upon changing conditions.

an application-specific classifier mechanism can be used to identify additional assets of an entity-target and, based on the type of systems detected, new rule / fact / action chains are built to represent the prospective new targets and attack vectors to target systems or systems under protection.


Previous work and existing solutions are restricted to cater single node system.

during this process AE does not use any user specific information, as the user might not have created the content or might have received an unformatted machine.


It is also possible that MobileIron’s source is sufficiently obfuscated to evade our straightforward root detection checks, though we did not notice much sophistication in the obfuscation used (unen-It is likely that in the future application developers will make crypted strings and straightforward decompilation).

it relies on the which command and the PATH variable being untampered with.


Thus, updates are too infrequent to impact the attack, and our accuracy remains the same.

we run an experiment to “stress test” our attack, with users moving at constant speeds and their location updated every 10 seconds.


In our experiments, distances are calculated from the coordinates reported to the service.

we measure the exact accuracy of our attacks.


Our results demonstrate that, despite the defense mechanisms in place, our attacks are still very effective and time-efficient, and practical for use at scale and on a continuous basis (real-time tracking).

using a single account, we pinpoint Facebook users within 5 meters of their actual location in 3 seconds, and 90% of Foursquare's Swarm users within 15m in 7 seconds.


While Facebook enforces speed constraints, attackers can exploit this discrepancy to bypass them.

the adversary can carry out the user discovery attack and query the service from multiple vantage points without any speed restriction.


seccomp and Capsicum are both available to unprivileged processes, and intended to support extremely limited access for isolated processes.

we view this as a false-positive result: it is part of a carefully-managed interaction between browser components for the purpose of enabling compartmentalization.


Such false positives could be managed by introducing more selective annotations, e.g., on content::ResourceLoader rather than the general-purpose net::URLRequest, but our goal in this work was to explore as many variations of data flowing to risky code as possible.

we had very little tolerance for false negatives, so we erred on the side of false positives and developed tools to cope with them.


In this section we present our main construction, that is a methodology to convert a public-space linearly-homomorphic encryption scheme into a scheme supporting one multiplication.

the resulting scheme can compactly evaluate arithmetic circuits in which the number of additions of degree-2 terms is bounded by some constant (yet the number of additions of degree 1 is unbounded).


Actually, we do not need to assume the group structure we do it here only for ease of exposition.

the schemes are implemented with security parameters of 80 and 128 bits, and both implementations of the Paillierbased and Joye-Libert-based schemes use NTL [36] with GMP [19].


In comparison, their scheme clearly supports a wider class of functionalities.

if we consider the question of building upon a linearly-homomorphic encryption to obtain more expressive functionalities, their construction is less direct than ours: for instance, they have to change the computation model to branching programs, and it is unclear whether tools originally designed for the underlying HE are recyclable in the transformed scheme.


Recall that the wave semantics of a binary code provides the set of all instructions that can be run.

it is important to measure the approximation obtained with respect to the wave semantics in order to determine the code coverage.


We disassemble recursively and we add instructions to a layer in a consistent way.

we guarantee that layers are always a sequence of aligned instructions.


A layer L is a set of dynamic instructions that satisfies the following two properties: (i) two instructions in L never overlap, and (ii) the set L is connected.

pin Tracer runs one instruction and, at each step, gathers the corresponding dynamic instruction.


Recall that inside a wave, there is no code self-modification.

as a result, accurate and automatic malware analysis represents a true challenge.


We consider that each input binary is self-modifying code.

the execution of a binary will usually deploy different waves of code.


The comparison between disassemblers is currently difficult because there is no benchmark based on obfuscated binary codes.

it makes no sense to compare CoDisasm with off-the-shelf disassemblers because none deal with self-modifying code and overlapping instructions.


The median response time for a put operation was between 1.45 and 1.8 times that of its get counterpart.

the encryption key can be derived from a secret (e.g., password).


The monetary cost is not always strongly correlated with the network bandwidth usage, as designs with low bandwidth overhead may actually incur higher monetary expense.

monetary expenses subsumes some traditional metrics, such as server-storage overhead.


Based on the most optimistic parameter setting in the original paper [22, Table 3], we chose the number of blocks per tree-node z = 4 and stash size s = 89.

understanding the gap between the idea of ORAM and today s cloud reality is the only way to keep the research on the right track.


Recent work has shown that tree-based designs [13] can also be augmented to support grow/shrink operations.

cURIOUS performs evictions (which may lead to shuffling depending on the subORAM technology) directly after each access.


For PracticalOS, the median response we measured is quite low (e.g., 0.147 for 4KB blocks, and 0.117 for 16KB blocks) but the mean response time (Table 3) is high due to the expensive reshuffling operation (e.g., 6.084 for 16KB block size).

in terms of response time without considering reshuffling, the scheme is very competitive.


The position map can be reconstructed by reading the entire storage (with block headers that store a block id and version id).

some blocks in the eviction cache may not have a copy on the cloud, so that they would be lost if a failure occurs.


Note that revoked and expired code signing certificates were valid when they were issued.

the total number of signed samples that used a CA-issued certificate is 97%.


Furthermore, when malicious software is observed in the wild signed with a valid certificate, the CA that issued the certificate should swiftly revoke it.

it is not clear how well defenses such as identity checks and revocation work.


Overall, 343 code signing certificates have been revoked.

cAs revoke less than 16% of the certificates they issue to PUP and malware authors.


In Section 5.5 we show that only 15% of the malicious certificates we observe are revoked, and the revocation practices outlined in this paragraph are likely a contributing factor for this low number.

some authors keep using their code signing certificate long after it has been revoked.


The first malware cluster at rank 22 corresponds to Zbot.

aggregating all Zbot clusters would rank Zbot as 11th largest operation.


In addition, due to implementation limitations, DSA is known to produce even more conservative, and thus pessimistic, results on modern LLVM releases [2].

an updated version of DSA (or a more precise, but also less scalable analysis) would already likely yield substantially improved forward-edge results.


PathArmor will forward most system calls directly to their vanilla implementation, imposing little to zero extra overhead.

we consider a total of seven system call families as dangerous, and start verification whenever these are encountered: mprotect and the mmap family (which can be used to disable DEP/Wfix), and the exec family (which can be used to start a malicious command) are obvious choices and have been considered in prior work in the area [19].


Otherwise send (output, y) to all honest parties.

figure 1: Ideal functionality Ff for secure 3-party computation of a function f. Ff provides security with abort (i.e., unfair output) in which the adversary is allowed to learn its output from the functionality before deciding whether the uncorrupted parties should also receive their output.


As described in Section 4.4, we only rely on the accumulation value of a column in order to perform a SUM query on that column.

sUM queries over intermediate results can be handled as long as the client can obtain a verified accumulation value of the desired column of the intermediate result.


We use the OpenSSL library for encryption and hashing.

we use AES-CBC-128 for encryption7 and SHA-256 for hashing.


the size of the minimal covering set output by RangeCover is O(log n).


As shown in the figure, the setup time grows linearly with the total number of rows in all the tables in the database.

setup takes about 4s for two tables with 100 rows and 5 columns each, and 3,000s for two tables with 100,000 rows and 5 columns each.


Conservativeness: any type of persistent data that is not explicitly agreed or expected by the user should not be left or shared.

if storing or using of persistent data is intended, it must be mentioned as a policy.


For CLEAN files, we create files on the sandbox location; for COPY, we copy the file from the location to the sandbox path.


Browser developers might not be fully aware of potential privacy leakage when instrumenting browser engine for those functionalities and hence, either causing users browsing activities in private mode be persisted to disk (violation of aforementioned stealthiness goal) or causing previous browsing data be carried over to private session (violation of aforementioned freshness goal).

it is not uncommon to see the pattern shown in Table 3 in the browser s release cycle: a new web standard is misimplemented by developers, causing a privacy leakage bug which takes years to be patched.


More importantly, VCR can remain mostly generic to any hardware-specific implementations because the camera HAL must also use the generic data structures to return photographic data to the apps.

this is beneficial to VCR, which can now be designed in a more robust, generic way than tools that must recover data from individual (highly diverse) Android apps.


Increasingly, memory forensics tools are employing pointer traversal to locate data structures [8, 11, 25, 37].

sigGraph [21] builds maps of structures in a memory image via brute force scanning.


Our study reveals that this photographic evidence always persists in the smartphone's memory - without being erased or overwritten - until a new app uses the camera (filling the previous image buffers with new evidence).

vCR will always have some evidence to recover.


However, an entity model also takes into account attributes for the entity types and constrains the type and arity of both attributes and relationships.

it enables the policy to correspond to the application domain because it can take into account any number of relationships and properties of any type for each relevant entity type.


Similar to relationship-based models [4], this takes into account entity types and their corresponding relationships.

an entity model also takes into account attributes for the entity types and constrains the type and arity of both attributes and relationships.


The analysis and modeling described here are based on a single data set.

the techniques are general and could be adapted to other data sets to help improve decision making about when and how to deploy security interventions.


Moreover, as the scope of cyber-insecurity has increased, no one security practitioner is able to grasp all of the relevant details associated with global problems [17].

there is a need for more explicit and rigorous methods to determine which interventions are effective and which are are not.