Path-end validation does not protect against the "2-hop attack", in which AS 2 pretends to be directly connected to a (legacy) neighbor of AS 1 (say, announces the bogus route 2 - 40 - 1).

such attacks turn out to be quite ineffective, since the path that the attacker can announce to the victim's prefix, must consist of at least two hops, and BGP paths are typically short (about 4-hops-long on average [24]), i.e., most ASes will not fall victim to the attack.


Allowing the original scheduling algorithms to be preemptive allows packets to be fragmented, which then makes replay extremely difficult even in simple networks (with store-and-forward routers).

disallowing preemption in the candidate UPS overly limits the flexibility and would again make replay impossible even in simple networks.


Furthermore, the small increased memory consumption of UNIVMON comes at a dramatically increased flexibility and generality across the suite of applications.

openSketch is in effect using K-times as many resources if there are K distinct tasks as it instantiates a separate sketch when we look at the set of applications, whereas UNIVMON uses a single universal sketch instance.


We assume that we have a single switch processing this trace and that in both cases the “controller” periodically polls the switch for the sketch every 5 seconds.

the memory numbers reported are roughly for a 5-second trace.


For brevity, we focus on each of these metrics computed over one feature, namely the source IP address.

we know G is in Stream-PolyLog and we approximate G-sum in polylogarithmic space using the universal sketch.


Sekar et al, showed empirically that flow sampling and sample-and-hold [24] can provide comparable accuracy to sketching when equipped with similar resources.

the proof of this theorem is outside the scope of this paper and we refer readers to the previous work of Braverman et al [9].


A recent proposal uses secure multi-party computation (SMPC) to achieve policy privacy [17].

transforming ar bitrary computation to SMPC is non-trivial, and it suffers from severe performance issues.


Many new designs for inter-domain routing aim at providing new features (i.e., flexible route selection [16, 36, 37] and verifiability [26, 39]).

in inter-domain routing, introducing new features often comes at the cost of privacy, which is something that ISPs are not willing to sacrifice [17, 39].


Existing approaches, such as SPIDeR [39], propose to verify whether ASes live up to their promises by collaboratively verifying the promise.

sPIDeR relies upon the condition that all neighbors of a promise-breaking AS correctly follows their design to perform the verification.


Motivated by the recent movement towards commoditization of trusted execution environments (TEEs), this paper explores alternative design choices that application and protocol designers should consider.

we explore the possibility of using Intel SGX to provide security and privacy in a wide range of network applications.


We believe many research opportunities remain in realizing or extending our suggested models.

one notable fact is that unlike other TEEs, its trusted computing base (TCB) only includes the processor and the application code inside the enclave.


is is because updated baselines’ extra control information cannot be disseminated across BGP gulfs.

we end up with this requirement: UB-R1 Disseminate updated baseline’s additional control information across gulfs.


An AS that supports MIRO [24] offers alternate paths for payment (the rightmost one).

the transit AS cannot discover the MIRO-enabled AS because BGP does not allow discovery of ASes custom services or the extra coordination required to use them.


The second feature, adding value to other protocols, is also consistent with the notion that network control functions that benefit other protocols should have an easier time being adopted.

its high p-value together with the small number of protocols in this category, make it difficult to draw strong conclusions from its selection.


To meet the requirement II, all devices including nonmesh devices and mesh APs must be authenticated to join the WMN by EAP authentication method such as PEAP or EAP-TLS.

a mesh AP need to be an authenticator as an entry point to the WMN and also a supplicant connecting another mesh AP.


As for the fair comparison, poptrie should be compared to LPMnoSSE result, since both does not employ SSE optimization.

poptrie may benefit from SSE optimization to obtain a better performance in the future.


We then consider all pairs (ti, tj ) i = j, and consider a discretised grid counting the number of services in buckets of size 10.

we count the number of pairs falling in each bucket.


Indeed, CDFs now saturate at Sim = 0.3, meaning that the activity of different users is in 70% of cases very different.

people keep accessing previously unseen services, so that the total number of distinct services keeps growing over time.


As shown, the similarity among different users is very small, and smaller than the one among the same user, cfr.

intuitively, we want to check how many times the most similar user turns out to be u in a group of a 1000 users {ui}.


This means that, independently of the volume of their activity, the sets of services contained in time bins are significantly different.

users tend to contact same services over time, but the number of new services is however fairly large, meaning that the degree of repetitiveness is low.


In this work, we focus on the exploration of users habits when browsing the Web.

we take the point of view of the network, from where DNS requests of users are observable, and from which we can extract the names of the services they are accessing.


We are currently designing an experiment aimed at overcoming the threats to conclusion validity.

it is based on a model capable of simulating parallel communication attempts, and that implements the timeout mechanism so that the effects of the transmission delay can be taken into account.


Therefore, future work should replicate the experiment here con-ducted in order to increase confidence in the results.

the design of the replicated experiments must face the remarked threats to validity and pitfalls.


The size of each routing table changes as a result of both the discovery of a new route (so a new entry is added in the routing table), and a link breakage (so an existing entry is removed from the routing table).

the size of each routing table can increase or decrease during the simulation execution.


In the latter, the aggregation process is monopolized by access points.

we actually define individual preference relationships using utility functions for B-APs and P-APs.


The closest clusters to the BS have smaller sizes compared to those farther away.

the amount of intracluster traffic is significantly reduced and the nearest sensor nodes to the BS consume less energy than distant sensor nodes.


In Section 5 the performance of the proposed approach is evaluated.

if the APs are assigned non-bonded channels only then n clients may suffer by operating with a reduced transmission rate and thereby degrading the overall network performance.


The positive impact of using a bonded channel is that the n clients can achieve a maximum data rate of 300 Mbps from their associating AP and thereby improving the network throughput [2].

use of bonded channel may increase co-channel interference among the APs and thus degrading the network performance.


Typically, the payload size is known in advance for this type of traffic.

the absence of periodicity makes it difficult to calculate the bandwidth requirement.


Energy conservation, ambient energy harvesting, incremental deployment, battery replacement, and wireless charger are among the typical suggested solutions.

the majority of these solutions didn't revisit the standard specification to implement the new proposed techniques.


The connected M2M nodes will include both resourceconstrained and resource-rich devices.

their capabilities of computation power and memory size are heterogeneous.


InitCond: This condition requires that any initial state returned  by the implementation's init function has a 0 received-message count according to Rec.

the initial state should not have received any update from any node.


In a DDoS attack, an attacker may spoof requests from UACs in order to cause the SIP proxy server to allocate resources to processing the spoofed requests, thus starving out legitimate requests (denial of service).

an attacker sends an INVITE request, but with a spoofed address from a UAC pool.


The virtualization of IP telecommunications networks provides an opportunity for deeper knowledge about security to be embedded inside such networks through a combination of real-time analysis of network behavior and the leveraging of the dynamic reconfiguration capabilities of virtualized networks.

this combination of analytics and autonomics offers the potential for networks to automatically detect security threats in real-time, dynamically reconfigure themselves to protect against these threats, and automatically immunize themselves against evolving threat, reducing the response time from days to minutes.


The following figures depict a dataset in which there are multiple peaks of malicious traffic, with increasing rates.

in this dataset, there are seven periods, with the first period having thirty INVITEs per second, increasing in each peak by an additional ten INVITEs per second.


For example, for anomalous legitimate network traffic, such as unusually high traffic associated with a natural disaster, flash mob, or other unexpected event, the underlying network could automatically grow network resources (e.g.creation of new virtual machines) in order to handle the additional traffic load.

for anomalous traffic stemming from a malicious attack, the network should dynamically instantiate new firewall rules and/or new virtual security functions in order to block the offending traffic and protect the rest of the network from the attack.


unlike global clustering coefficient, local clustering coefficient measures how a single node is connected with its neighbor nodes (either well connected or loosely connected).

local clustering coefficient calculation is based on the fraction of the number of present links over the total number of possible links between the node s neighbors as shown in Equation (4).


As the assumption of sensor devices equipped on a node, we consider the simplest case in this paper.

each node is equipped with a sensor device that can observe a single attribute environmental information.


the topology due to the energy exhaustion, the sink has to reconstruct another topology and disseminate the updated information to all nodes.

the sink estimates how many times the readings can be gathered from all representative nodes using the current topology by simulating communications for the data gathering using energy consumption model which is described in Section 4.1.


As the number of neighboring nodes increases, such nodes tend to have a large number of children.

for constructing a topology, the attribute cell energy is considered in the same way as our proposed method.


In [8], the technology of gateway framework was introduced and an experimental result was given of parallel reprogramming in a developed prototype of a central gateway; however, detail of a technical method was not provided.

in [21], a reprogramming data processing method was provided for time reduction in a central gateway-based network architecture, and the performance of an implemented central gateway was evaluated using a test environment.


If the DCU owns only one sub-network, then the PCU can transmit the reprogramming data (in the DoIP frame) to the sub-network owned by the DCU, which only identifies the IP.

if the DCU owns several sub-networks, then multiple socket connections are established dynamically between the PCU and the DCU, and the PCU transmits the reprogramming data for each ECU to the different sub-networks owned by the DCU.


However, if the DCU owns several sub-networks, then multiple socket connections are established dynamically between the PCU and the DCU, and the PCU transmits the reprogramming data for each ECU to the different sub-networks owned by the DCU.

when the PCU transmits the reprogramming data of multiple ECUs to subnetworks owned by different DCUs, the PCU transmits the segmented reprogramming data to different DCUs according to each assigned IP number alternatively; these data transfers can then be parallelized in terms of the overall reprogramming.


Therefore, the total reprogramming time is increased due to the accumulated transmission delay time, and the transmission delay time due to a single buffer usage makes it difficult to accelerate the reprogramming data transfer.

if a bandwidth of source network (interconnect with the PCU and the DCU) is larger than the bandwidth of a target network (interconnect with the DCU and the target ECU), such as the Ethernet-based source network, the DCU can apply a number of different buffers.


This means that the total reprogramming time of the parallel and sequential (one-by-one) methods is similar.

we have restricted the number of ECUs to one per sub-network, and propose multiple ECUs reprogramming on a different sub-network when multiple ECUs are reprogrammed simultaneously in parallel.


In SPIN, operations were not run in a sequential order but in a randomly chosen way.

rREQ messages may be received quickly on one side but slowly on another side.


The proposed method was verified through simulations under all possible circumstances.

existing routing protocols only support rapid recovery of lost nodes so ad-hoc networks have a problem of significantly low efficiency owing to the lack of support while data is transferred.


As micro systems and sensor technologies have advanced, with recent wireless technologies, autonomous and flexible wireless sensor networks can now be used to send or receive data between moving nodes whereby each node recognizes and measures its own sensor environment and processes data without access points (APs) or base station communication networks, which are generally used in existing infrastructure network wireless technologies.

ad-hoc network technology enables direct communication between devices so that they can send or receive signals directly between two close users without passing through APs or base station communication networks, thereby effectively providing mobility between nodes compared to existing centralized network technologies.


in Section 2, a routing protocol method used to facilitate communications between nodes in an ad-hoc network is discussed.

a routing protocol used in an ad-hoc network should respond to frequent changes in states owing to node mobility and lost nodes, as well as being simple to operate and having high reliability.


However, usually the carried information contains confidential data.

a security aggregation approach is required.


The state I and state B denote the channel conditions, and p is the transition probability from state I to state B.

q represents the transition probability from State B to State I.


This is due to the use of several nonlinear functions, such as the square root, which do not work properly in the Contiki environment due to the lack of support for floating point numbers.

it is necessary to decrease the number of calculations as much as possible.


Each application has its own requirement and corresponds to different optimal parameters [16, 15].

using Neutral Network to learn and narrow the scope of parameters is a practical method.


Cloud-assisted data broadcasting is an emerging application where cloud computing assists data broadcasting to extend the capacity of system computing and improve the interactivity of the conventional media.

with the increase in scale, it brings the difficulty on the complexity to provide the sufficient quality of service for diverse receivers.


Classical proportional scheduling algorithms are vulnerable to accumulated errors because the output is oscillatory and potentially unstable when Integral and Derivative components are reduced [12].

we can conclude that the normal pro portional algorithm can meet the criteria of coarse-grained proportions with less consideration on the system stability and the .ner quality of service.


Figure 16 shows the gap between the observed load and the output from KLEIN.

higher levels which need a more global view solve simpler problems at coarser timescales, while the lower levels which need to be more responsive to avoid performance issues can run more rapid reconfigurations.


We thus argue that this INTERMEDIATE design can serve as the basis for a minimally disruptive design for future cellular core architectures that can address today's cellular core limitations.

nFV is already a reality for carriers [7, 24, 6, 44], and there are many open-source and commercial efforts to virtualize cellular core functions [13, 19, 18, 5, 2, 3].


Our CacheFlow system "caches" the most popular rules in the small TCAM, while relying on software to handle the small amount of "cache miss" traffic.

we cannot blindly apply existing cache-replacement algorithms, because of dependencies between rules with overlapping patterns.


The idea of using DAGs for representing TCAM rule dependencies is discussed in the literature in the context of efficient TCAM rule updates [33, 34].

their aim was to optimize the time taken to install a TCAM rule by minimizing the number of existing entries that need to be reshuffled to make way for a new rule.


Composing two candidate rules to build a cache would simply involve merging their corresponding mixed-sets (and incre-menting appropriate reference counters for each rule) and decomposing would involve checking the reference counters before removing a rule from the TCAM 8.

figure 10(b) shows that the cache-hit rate for the incremental algorithm is substantially higher as the TCAM size grows towards 2000 rules.


That is, rules R2 and R5 depend on rules R1 and R4, respectively.

there is a dependency from rule R1 to R2 and from rule R4 to R5.


They do so by building a DAG that captures how different rules are placed in different TCAM banks for reducing the update churn.

the resulting DAG is not suitable for caching purposes as it is difficult to answer the question we ask: if a rule is to be cached, which other rules should go along with it?


We can do better than past algorithms by modifying the rules in various semantics-preserving ways, instead of simply packing the existing rules into the available space—this is the key observation that leads to our superior algorithm.

we “splice” the dependency chain by creating a small number of new rules that cover many low-weight rules and send the affected packets to the software switch.


If the TCAM can store four rules, we cannot select the four rules with highest traffic volume (i.e., R2, R3, R5, and R6), because packets that should match R1 (with pattern 000) would match R2 (with pattern 00*); similarly, some packets (say with header 110) that should match R4 would match R5 (with pattern 1*0).

rules R2 and R5 depend on rules R1 and R4, respectively.


A key property of the algorithms discussed so far is that each chosen rule along with its mixed (cover or dependent) set can be added/removed from the TCAM independently of the rest of the rules.

the mixed-sets for any two rules are easily composable and decomposable.


Pre-SDN era declarative networking [17, 16, 19], on the other hand, uses a distributed query engine for fast processing of customized routing protocols, where the database executes routing queries submitted by end-hosts.

ravel makes the database an active participant that uses views to incorporate multiple high-level and lowlevel abstractions of the network which are orchestrated online.


In contrast, Ravel makes the database an active participant that uses views to incorporate multiple high-level and lowlevel abstractions of the network which are orchestrated online.

we believe this is likely to be valuable both technically and as a way to encourage more rapid uptake of SDN.


Formally, a network state is consistent if it is compliant with all the application policies.

consistent network states correspond to applications with invariant-preserving views.


Reliability is achieved by sending each aggregated event packet via multiple paths to the BS.

drawback of this method is that it is not delay aware.


From the simulation study it has been observed that mobile base station based data delivery scheme in WSNs may help in reduction of end to end delay and deadline miss ratio.

we have also observed that packet delivery ratio may decrease due to mobility of base stations.


This is because it uses a conservative stepwise switch-up and aggressive switch-down strategy to avoid playback interruption, despite the fact that the network bandwidth is sufficient for transmitting a higher resolution segment.

in the scenario of small bandwidth variation, these results show that RateAdaptation is too conservative to select a higher bitrate segment, and leads to a lower average bitrate and bandwidth utilization.


Microsoft Media Services (MMS) and Real Time Streaming Protocol (RTSP) are popular solutions used by the video streaming services.

solutions based on HTTP over TCP are usually preferred owing to the following advantages [8].


It provides new ways of looking at the structure of a given environment from a real-time perspective based on dynamic up-to-date records of human presence.

through the day-to-day social activities such as lectures, seminars and regular meetings, we have strong evidence about the existence of .ner-grained relationships as opposed to the user af.liation.


Lee [10] addressed a location problem in three-dimensional space from the application perspective.

he introduces a 3D coverage location model of Wi-Fi access points (APs) in an indoor environment.


An example of mono-criterion approach is Cost-Benefit Analysis (CBA) [31] which uses, as a single criterion, the Net Present Value [31].

this approach isn’t always suited for practical problems, as it takes into consideration only one criterion that needs to be expressed in monetary terms.


Two roots can be obtained by solving (16) as expressed in Equation (17).

these techniques are not suitable for inter vehicle distance calculation.


Another GPS-free localization techniques has been presented using Received Signal Strength Indicator (RSSI) [12].


Time of Arrival (ToA) based GPS-free localization has been developed [11].

the GPS-free localization framework operates on two steps.


The term LAMP has retained its underlying rationale also in the 2000s and 2010s Internet, although the contemporary nomenclature allows shuffling; the letter P may currently refer also to Python or Perl, and MySQL may be replaced by PostgreSQL, for instance.

lAMP is best understood as an idiom for a typical open source software stack for developing and servicing web sites.


If a PHP is detected once for a domain, the remaining preprocessing is skipped for the domain.

the units of analysis reflect web-servicing domains that supposedly run PHP in at least one corner of their deployments.


These configuration and modification solutions may prevent a web site from being included in target pools of web scanners and mass-scale exploitation frameworks, but many individual practitioners would likely argue that such solutions rather represent the so-called security-by-obscurity.

ultimately, (g) applied web intelligence research should be also able to demonstrate a concrete web deployment that successfully utilizes existing big data collections for analyzing real-world questions motivated by scholarly hypotheses.


The overall situation is not as grim, however.

true horror cases are rare; only a negligible amount of identified False web-facing domains ran PHP/3.0 or earlier releases.


A faulty robot follows its assigned trajectory and is indistinguishable from a reliable robot, except that a faulty robot does not detect the target while visiting its location.

the target is detected only when its location is visited by a reliable robot.


Thus, the target is detected only when its location is visited by a reliable robot.

an algorithm for a parallel search with f faulty robots must make sure that any point on the line can be visited by at least f + 1 robots.


Thanks to the redundancy, only a subset of the coded chunks is required for reconstructing the original (uncoded) packet.

packets may be read even when only a part of their chunks is available to read without contention.


However, it is much easier for hackers to spoof the source IP address as UDP itself is connectionless and does not require a handshake like TCP does.

it is worthwhile to design a countermeasure against DDoS flooding that suited the DNS traffic.


Various types of application traverse the mesh network.

due to mobility and its multi-hop nature, dynamic network configuration is needed to seamlessly support applications for better quality under dynamic network conditions.


We consider the real 3G connection as our ground truth, which the emulator would ideally mimic perfectly.

a real 3G connection can significantly vary depending on aspects such as load or scheduling decisions at the network Mean RTT (milliseconds) operator side.


The reason is that in Wi-Fi and cellular networks the output power levels take values from a discrete set of size N, where N< 100.


For the scope of this paper however we have used average static values, which were taken when the signal strength was full for all 3 interfaces in our lab (indoors) to demonstrate our proposed approach.

dynamic measurement of bandwidth and signal strength would be critical to further improve the robustness of the proposed solution.


While the signals were clear on an antenna placed right on top of the phone, we could not see any signal over the body.

the EM signals generated by the screens of such devices do not propagate well over the body and hence do not cause interference.


It is based on an intuition that the distance between the two tags is much shorter than the distance from them to the objects in the environment.

tags at very close positions may share very similar ambient noises and multipath effects.


Theorem 2 dictates that we can always find an optimal frequency combination in a continuous frequency band so that our error tolerance is maximized.

these systems came with a variety of constraints in order to be extended to a ubiquitous real-time 3D passive device localization system.


6, the frontend antenna reflection loss S11 must be minimized for all operating frequencies.

it first decides what frequencies are transmitted based on the available bandwidth.


Client devices are unaware of whether content from a domain is available over IPv4 network or over IPv6 network.

clients must send both AAAA (IPv6) and A (IPv4) DNS queries to their local resolvers to resolve domain names.


The first are mappings between client and cellular DNS server IP addresses.

our work precisely describes the current role of a CDN in connecting mobile users to content servers in the evolving cellular ecosystem in the US.


When we run our system at the first time, the running time increases with more unknown clients.

the running time significantly decreases to 0.065 s after the system's first run, since we only need to estimate the location of the target.


When a target is running, the CSI changes may vary a lot in a short time.

liFS can not always get stable CSI changes, causing large errors.


LiFS is able to localize the two targets when they are located sparsely.

note that we have CSI from 30 subcarriers and as long as a few of them fall in the clean category, it is enough for our localization purposes.


To remove the noise on raw CSI measurements, we observe that not all subcarriers are affected equally by multipaths even in a rich multipath environment.

we introduce a novel CSI pre-processing method to filter out those subcarriers greatly affected by multipath and hardware noise.


If many workers are prepared, many context switches and high contention against the two queues occur.

hoL is not avoidable if there is only one worker.


Since the only component enqueueing to the input queue is the receiver, flow rate can be controlled to some extent.

when the receiver enqueues a certain number of requests to the input queue, it requests a context-switch to the scheduler of lightweight threads.


In this scheme, the sendfile system call cannot be used for the file type.

we adopt the pread system call, which, like the sendfile system call, also preserves offsets in the kernel.


An alternative approach would be to keep requesting every cache encountered for potentially better related content.

we believe this might put a high burden on the battery of the UE and the UE-SC traffic.


Our preprocessing scheme tries to identify the subcarriers not affected by multipath.

cSIs on the “clean” subcarriers can be modelled and utilized for accurate localization.


To identify whether a target is located on the LoS path, the key observations are (i) |At| is usually within the range of 4–9 dBm [3] when a human target blocks the LoS path, and (ii) the noise is usually within 1–3 dBm [2].

a target is more likely located on the LoS path if the averaged CSI change of all subcarriers is larger than 5 dBm.


To filter out these dirty subcarriers with abnormal CSI changes, our first step stems from the power increase observation at some subcarriers.

when the CSI amplitude of the k-th subcarrier is increased instead of decreased, we know the subcarrier is affected by multipaths and the CSI measurement at this subcarrier should be filtered out.


We choose to rely on simple local congestion monitoring in Expeditus.

the only diference is that the first packet of B is a SYN-ACK in this case.


Commodity ToR switches typically have 4.40Gbps uplinks.

each pod normally has 4 aggregation switches.


We set the benchmark parameters such that the dominant factor in server performance is the latency introduced by the networking stack at the endpoints and packet processing at VNToR, not by other server or switch bottlenecks.

we ensure that: the working set of the rules fits in the hardware table; the ASIC-SupE interconnect inside the switch is not saturated;  the servers are neither CPU-nor I/O-bottleneck-ed.


Integrating VNToR in OpenStack merely requires implementing a Neutron agent that runs on VNToR s SupE and whose role is to collect, from the Neutron controller, all the relevant security-group state.

our agent subscribes for changes to: all the local VMs, i.e., those running in the local rack;


We share the general challenge but have a different focus from this work: we design and build a caching system that meets a significantly harder performance baseline, and we achieve this by tailoring the solution to the properties of state-of-the-art datapath memory.

our agent subscribes for changes to: all the local VMs, i.e., those running in the local rack;  membership information of the security groups where the local VMs belong;  membership information of any security group with which a local VM is allowed to communicate;  all the other relevant network-wide translations defined by Neutron, e.g., encapsulating tunnels.


The ASIC handles all traffic that can be served from the hardware table and passes the rest to the software forwarders.

the moment the rule is promoted to the hardware table, there is packet reordering (directly proportional to the amount of buffering in the software forwarder and the hardware-table update latency tup), but throughput climbs to line rate within 20ms.


In order to evaluate the T-SIMn framework, we use an evaluation methodology similar to that used to evaluate T-RATE [2].

we conduct an experiment (which produces a trace) using a round-robin ordering of rate configurations and then in SIMn we conduct a simulation using a round-robin ordering that differs from the experiment.


As real devices are used, the MAC and parts of the physical layer are not simulated.

signal propagation is simulated using the FPGA to alter the signals being transmitted between devices.


In 802.11n networks, the fate of one frame can impact the number of frames that can be aggregated in the next frame due to the Block-Ack Window (BAW).

upon closer investigation, we realized that the simulator is in fact accurate and that the problem was with the methodology used to evaluate the accuracy of the framework.


During trace collection, rates are grouped by a combination of the Guard Interval (GI) and the CB.

this scenario is comprised of a mix of carrying the iPhone at walking speed and standing still in an office and hallway environment as explained in Section 4.


This suggests that SIMn accurately handles rate configurations using different physical layer transmission features.

sIMn accurately calculates the transmission time of a frame (including ACK and DCF timing) for the combinations of the physical layer features shown.


To increase the realism of emulators, hybrid approaches using traces to simulate the physical layer and emulation for the MAC layer have also been proposed [13, 24], however these have been limited to 802.11b networks and rely on measurements of Signal-to-Noise Ratio (SNR) to simulate the physical layer.

the SNR can not be used to accurately predict frame fates [9].


Being able to accurately simulate A-MPDUs of any length using frames collected using only A-MPDUs of maximum length is the  key insight and critical requirement to enable trace-based simulation of 802.11n networks.

we now evaluate SIMn’s accuracy when simulating the throughput of frames aggregated with fewer subframes during simulation than were obtained during trace collection.


We showed that such peaky signals also have, in the wide-band limit, very strong AJ properties [9, 10].

we showed that, through the use of peaky signals, energy-limited jammers do not affect capacity in the wideband regime.


Despite the impact of the traffic arrival distributions on the goodput performance, there is no impact on the goodput-efficient routing strategy.

multi-hop routing under moderate traffic loads and direct transmission under light and heavy traffic loads is the optimum choice for enhancing goodput performance in multi-hop wireless networks, independent from the traffic arrival distribution, generalizing the results in [5, 23] for the considered traffic arrival distributions.


We are focused on the feasibility of virtualization implemented as a user-level program so that the result may work on top of a diverse mix of underlying system stacks.

we are intrigued by the possibility that a specially designed P4 program itself may provide the benefits of programmable data plane virtualization by emulating other P4 programs.


HyPer4, however, moves most of the parsing decision logic into the ingress pipeline, and the actual parse graph for HyPer4 simply extracts a specified number of bytes without any higher level structure.

hyPer4 makes an end run around a restriction normally imposed by P4, for better or for worse.


HyPer4 can preemptively declare statically bound registers, counters, and meters for every table that emulates the match piece of a match-action stage, but this approach is likely to prove infeasible for many hardware P4 targets.

registers can vary in width, which for the preemptive approach would require HyPer4 registers be declared with sufficient width to cover the maximum need, resulting in a lot of wasted register memory for the average case.


Figure 1 illustrates a packet exchange procedure of the proposed scheme as an example where source (S), destination (D), and two cooperators (C1, C2) exist.

by doing this, we can verify the advantages of the cooperative method in terms of the system throughput.


The lower data transmission power is used, in other word, the larger IR of R is, the worse the LIRC problem becomes.

as a solution for the LIRC problem, we try to narrow down the interference range within RTS/CTS transmission range by allocating more power.


Since the interferer doesn’t receive RTS or CTS and thus cannot enter the sleep state, it may cause collisions with data at R.

in this paper, we propose a multi-channel based MAC protocol with power control to solve LIRC problem by separating the channels for control and data packets and allocating appropriate power for data transmission in underwater environment.


In this case, all links exhibit fairly good performance for both SL1 and SL2.

with the lower source level SL1, the phonoabsorbing surfaces tend to suppress the majority of the secondary paths: this translates into high PDR for almost all links, and in an improvement of 2 .


A specific case of technique i) above is the addition of metal dust to butyl rubber [17]: this achieves a better matching with the water impedance and increases the attenuation of sound energy in the material.

this type of rubber tends to absorb water over time, which degrades its phonoabsorbing properties.


These environments provide characteristics more akin to shallow water scenarios, giving the research team more insight as to what to expect in a real environment, and thus making it more ready for the sea experiment.

large testing pools, such as the one employed by CMRE [7], require a large infrastructure which may not be available to smaller research laboratories, e.g., as typically found in universities.


Secondary paths have a much more limited effect after applying the coating.

this is not the only impact of the phono-absorbing coating.


The SNs are a battery powered devices, and they consume their energy during the network process.

the remaining energy can be used as a metrics for selecting the CHs.


Like, if we have setup CSr in one of the bedrooms, then it may be possible that mediators of drawing room cannot pass data to CSr directly.

a data aggregation algorithm is required to aggregate all data in the network at CSr.


Data encryption and anonymization are the most common methods to protect private information for the perceptual layer of IoTs.

the connection of physical things to the Internet makes it possible to access remote sensor data and control the physical world from a distance [2].


Based on the technology of the Internet, there are many advanced methods to keep an IoTs system connect safely with external network.

these traditional technologies are not suitable for the perceptual layer of IoTs.


With Interest filtering, we could enable lights to provide service on multiple meaningful names with a single FIB entry.

the current Interest filtering is only supported by NDN client applications.


To ensure the execution of the command, each light node is required to reply with an ACK Data by appending its own light ID to the received Interest name.


Softwarebased discrete event simulators are based on a simulation clock rather then real time.

the required computation time increases dramatically with the number of simulation nodes.


If the host is ILNPv6capable, new DNS records for NID and L64 values will be returned, or the lookup in /etc/hosts will return an I-LV from a /etc/hosts file that has extended syntax as shown in Figure 3.

iLNP can offer multihomed IP connectivity as first class functionality so does not suffer the same issues, e.g. security issues, that are currently of concern for MP-TCP [31].


Expanding variety of end devices connected to the Internet has introduced high demand to flexibly authenticate and grant them the necessary access to the network.

it is not realistic to expect of all the end devices, including less capable and low-cost devices like sensors or embedded systems, to satisfy the requirement of integrated authentication procedure like 802.1x.


Note that the nodes in S are not candidates for the MCC as they represent the attackers (they are not vulnerability options for the attackers to exploit).

the nodes in T are eligible as they represent exploitation opportunities for the attackers on critical targets.


These graphs were instantiated from an attack template representing an ICS secured to industry standards.

each link in our instantiated attack graphs represented actual attack types that occur between the modeled services/entities.


The exact solution clearly grows exponentially.

each node represents a distinct vulnerability at a particular location (usually on some network host).


To calculate width, we must find the smallest set of colors such that at least one color in the set will occur on every possible attack path.

layer i contains all the nodes that are distance i from the set of attacking nodes.


Once this is done, it is free to run Docker-packaged applications in the VM environment.

there is no performance bene.t for Inter-VM Inter-Container-1Layer, which has the similar performance to the default mechanism (denoted as *-Def).


The focus of this simulation framework is to optimize WSN deployments regarding power efficiency and reliability.

a model of each WSN node, including its function, timing, and power consumption needs to specified, where the detail granularity of the model can be adapted depending on the simulation aspect that the user is interested in.


The real-world wireless bridge scenario, where the WARP nodes use their antennas for Single Input and Single Output (SISO) communication.

the measurement setup is shown in Fig. 9(a).


Besides the memory usage, an important factor for the scalability of our approach is the required computation time, as, in DES, the simulation time does not necessarily match the actual time to execute the simulation, which is influenced by many factors.

we measure the computation time for a simulation of 1 s in networks of different sizes.


The execution of WARP instances in different processes, which are coordinated via Inter-Process Communication (IPC), allows the simulation of small networks.

this approach does not scale well for larger typologies as each additional WARP node requires its own process.


CoWS only allocates the amount of memory that a simulated WARP node currently needs.

we are able to reduce the memory allocation per WARP node to about 4 MB.


For embedded devices, in contrast to systems that are managed by an OS, it is typically possible to write to any addressable part of the memory.

writing to arbitrary parts of the memory may lead to unexpected and erroneous behavior of the device, which is, in addition, difficult to track down.


Incorrect signatures make DNSSEC resolvers fail during the verification process.

an attacker on the path upstream from a validating resolver can cause signature validations to fail by modifying traversing DNS packets.


Meanwhile, ISPs formed a hierarchical structure and were classified by tiers, with higher tier ISPs cover larger geographic regions and provide transit service for lower tier ISPs.

large content providers, e.g., Google, are deploying their own wide-area networks so as to bring content closer to users and bypassing Tier-1 ISPs on many paths, which is known as the flattening phenomenon of the Internet topology


Looking at both situations it is obvious that the pass to Costa is more likely to lead to a shooting chance (i.e., higher reward) but is inherently more risky and requires more skill to execute than the pass to Fabrega.

current passing measures assign both passes with the same weighting (1 for successfully making the pass and 0 for not)


The extracted fields are then used to perform Access Control List (ACL) or forwarding table lookups in later stages to support packet classification or routing functions, e.g., a firewall makes a decision on whether to drop a packet according to a standard TCP/IP five-tuple extracted by the parser.

traditional packet parsers are designed for the specific network environment, which are too rigid to accommodate new protocols [1].


Clearly, multi-radio gateways can serve as translators among heterogeneous wireless devices with incompatible physical layers.

this solution is inherently limited in several aspects.


For example, in ZigBee devices, the packet-level RSSI information is sampled at only 31.25KHz, while the phaseshift is obtained at 4MHz by the ZigBee PHY for (de)modulation.

the throughput of packet-level CTCs is inherently bounded by a low sampling rate (e.g., KHz) in contrast to hundreds of Kbps for native ZigBee communication.


Without hardware modification, the WiFi signals transmitted in the pilot/null subcarrier cannot be controlled by software.

if the pilot subcarriers overlap with the frequency bands of ZigBee devices, WEBee cannot work properly.


These constellation points are controlled by the source bits of the WiFi payload.

source bits in a selected WiFi payload determine the QAM constellation points after the WiFi modulator.


Compared with the 16µ duration of a ZigBee symbol, a WiFi symbol occupies 4µs.

a full ZigBee symbol has to be segmented before emulated by four individual WiFi symbols , as shown in Figure 10.


The key idea of MaxSNR-MinHop is that the routing tables are constructed for a set of discrete SNR thresholds.

we relax our target to maximize the signal strength received at intended node.


If the G/L bit is 1, it is known that the BSSID is used as a local address in closed network.

this research does not target such BSSID showing the local address.


The ratio of existing decreases temporarily but it starts to increase again as the total observed days increases.

it is concluded that eight (the observed days) is the change-point since hotspots are eliminated and the amount of data is not too limited.


According to Wi-Fi radio wave characteristics, RSSI showing more than -75[dBm] are in high proportion to its distance from the RBS while RSSI less than showing -75[dBm] is in low proportion.

this research targets the RBS showing RSSI more than -75[dBm].


We run the program on the PC whose OS is Windows 8.1 Pro, processors are Intel (R) Core (TM) i7-4770CPU @ 3.40GHz, and RAM is 24.0GB.


However, variance converges to around nine regardless of the times or days.

in addition, in the process of modeling GMM[2], they can be eliminated so this research does not target to detect mobile hotspots.


We believe that a similar integration will be necessary in order for VLC to take off and, accordingly, the packaging and integration of VLC hardware within luminaires and wireless devices is a key challenge that needs to be addressed.

such integration and product readiness will force design decisions that are less expensive, less complex, and more robust – likely at the expense of overall communications performance.


In our first experiment, we analyze whether the intuition sketched in Figure 1 holds.

we study whether switching to a receive beampattern that is not the one that provides the highest gain towards a transmitter helps mitigating lateral interference.


Faulty nodes or parallel operation of incompatible standards which distort the channel, may cause signicant interference not just via main lobes but also via side lobes.

the best beampattern for a receiver may not be the one whose main lobe most accurately points towards the transmitter but the one whose side lobes do not capture any interference.


To overcome interference or signal jamming, we aim to search for an alternative beampattern that (i)maximizes the antenna gain towards the intended direction and (ii)minimizes the impact of interference.

an alternative beam should have a high correlation with the currently used beampattern but different zeros to steer the antenna away from the interference direction.


The baseline audio features provided by DSC consist of 5 formant features and 74 covarep features.

formant features consists of first 5 formants, covarep features consists of prosodic features, voice quality features and spectral features.


At the same time we transform abstract states, we perform verifications to prove that every C#minor expression evaluates safely (without blocking) in its evaluation context.

we check that every load and store is performed within bounds and with the correct alignment.


Therefore, it seems necessary to compare two channels, or at least one channel and one abstract state.

channels being records of functions, comparison is not decidable.


Our solution is to maintain the invariant that channels never contain more information than what is contained in the abstract values they are paired with.

at the top of the combination of domains, when we manipulate a pair (ab, chan) of an abstract value and a channel, we will make sure that γ(ab) ⊆ γ(chan) holds.


Analyzing mathematical, exact integers instead of machine integers greatly simplifies the implementation and proof of abstract integer operations.

there is no benefit in analyzing FP numbers using a more mathematical type such as rationals: FP operations (with rounding) behave well with respect to FP ordering, and abstract operations that use rationals are costly.


Section 2 presents the general architecture of the analyzer.

the returned channel contains no more information than what is contained in the returned abstract value and the given channel.


On the example of intervals above, our construction is very close to wrapped intervals [31].

computing (optimal) least upper bounds between sets of symbolic equalities is known to be dif.cult [21], so we settle for an overapproximation.


We use d to denote an implementation of a GC algorithm when the context is clear.

if d = 1, then GRA always selects the sealed block containing the smallest number of valid pages for GC, and we call it the GREEDY algorithm.


As d increases, both the impact of clustering and skewness on the cleaning cost vanishes.

data locality within a workload, including both clustering and skewness, has a signi.cant impact on GREEDY, but has no impact on RANDOM.


Even though skewness worsens the cleaning performance of GREEDY for locality-oblivious GC (see Figure 6(b)), it improves the performance of locality-aware GC.

incorporating locality awareness into GC design is more significant for workload with higher skewness.


Data locality affects the performance of locality-oblivious GC with a given implementation (i.e., GRA with a fixed d): (1) cleaning cost increases when either the active region size or the skewness increases, (2) the increase is more pronounced for a smaller window size.

data locality has the most significant impact on GREEDY, but has no impact on RANDOM.


Note that the design strategy of data grouping exploits data locality by eliminating the skewness within a workload.

it separates a highly-skewed workload into multiple uniform workloads with no skewness so as to reduce the cleaning cost (see Â§5.2 for the impact of skewness).


Since it is a general consensus that cleaning cost of GC algorithms may be reduced when data can be differentiated [11, 14] and a workload includes n + 1 types of data pages, it is of interest to study the performance of GC that exploits data locality using data grouping, which differentiates different types of data pages and stores them separately in different regions in an SSD.

we analyze how data grouping influences the performance of GC in SSD, and how much is the influence for workloads with different degrees of locality?


All page writes, such as external writes (due to workload) and internal writes (due to GC), are directed to the write frontier, and pages are sequentially written to the write frontier.

we formulate our workload model based on our trace analysis as follows.


In addition, DTR introduces new pipelined cells which may allow optimizations using retiming.

according to the fault-model SET (1 , K ), no error occurs within K clock cycles after the last error.


The maximum enumeration number in all our experiments will not exceed 104 and enumeration-based approach will .nish within a second.

we just use the enumeration-based approach in our experiments.


Under such circumstances, loops in an antichain may execute in parallel.

loops in an antichain will not share components with conservative scheduling.


Section 6 presents the efficiency of the proposed throughput optimization algorithm over traditional approaches with experimental results and the conclusions are presented in Section 7.

loop pipelining [17] is a key optimization technique in highlevel synthesis.


Multiplexers for resource sharing are non-shareable component candidates.

since the area of shareable component candidates are signicantly larger than the multiplexers by definition, in this paper, we made a simplification by assuming that the area of non-shareable component candidates is irrelevant to the resource allocation vectors.


A well known hardware solution to perform stride permutation in bitonic sorting is the delay feedback or delay commutator module widely used in FFT designs [10, 11].

using the delay feedback or delay commutator for sorting needs the inputs to be fed in with some particular temporal order.


These works either improve the sorting algorithms in terms of throughput and latency, or adapt the algorithms to a variety of general purpose parallel architectures such as SIMD or MIMD machines.

when considering both energy and performance as the key metrics, hardware-based sorting solutions are preferred.


In the second stage of SPN, each memory block can be implemented with single-port memory to permute a single data sequence.

when processing continuous data streams, dual-port memory is required as concurrent read and write access to different memory locations need to be performed.


Similarly, applications deployed on ASICs and FPGAs are often hindered by slow external memories.

to achieve good performance, hardware designers must optimize main memory usage.


For example, the memory sub-system for the Laplace benchmark is likely very similar to what one would select manually.

some of the memory subsystems are logical, but would likely require manual experimentation to discover.


This will be a short path, as the exception handling conditions are largely calculated before the final output.


Like an operating system, LEAP provides a unified layer of abstraction on top of device-specific drivers that interface the underlying FPGA device, on-board memory and the host system an FPGA card is plugged into.

our setup uses LEAP's scratchpads (SPs), a memory interface abstraction for FPGA applications.


The concept of shadow registers is shown in Figure 1.

both the input and output of the user register must be accessible; the input is fed into a shadow register, and the outputs of both the user and the shadow register are compared using an XOR gate.


Whilst, on the surface, it would appear that constraining the insertion process to use only spare resources that were left behind may be overly restrictive, significant flexibility is recouped from exploiting the convenient property that debugging signals can be connected to any trace-buffer input for it to be observable.

unlike the user circuit, where nets need to be routed exactly from a single source pin to a predetermined set of sink pins, debug nets need only be routed from any point along the existing user net to any one of the many trace-buffer sinks that are available.


Another area that we would like to pursue is to explore ways to effectively insert the violation detector (XOR) logic which compares the value in the user register with the shadow register.

this detection logic (and any downstream infrastructure) has the freedom to be placed anywhere on the device, as long as it does not extend Tcrit ; however, because this operation is a pairwise reduction (i.e.


If we did try to do this, placement would fail due to particular characteristics of the device chosen rather than anything inherent in the CLB architecture.

the area constraint is only applied on the CLB resources.


Instead, we interpret their waveforms as two probability density functions (PDF) or histograms of their sample index.

fortunately, Cypress provides an associated Microsoft Excel spreadsheet for power consumption in the families of various PSoC devices.


In digital domain, it is quite easy to perform such a task by using logic comparators and integer counters, which together behave like a histogram builder logically.

today, even with some of the most remarkable improvements in digital computing, many digital signal processing algorithms still can not achieve real-time performance within the power budget constraints required for many portable applications.


As shown in Figure 15, for a conventional FPGA-based convolver, the execution time increases with input vector size almost exponentially, which indicates that the execution time will be exceedingly long when the input vector is long.

once again, all circuit components in Figure 8, except all necessary resistors, can be readily found in our targeted programmable analog device, PSoC.


It is well known that analog signals are far more sensitive to noise than digital signals because digital quantization, binary numbering, and Boolean algebra jointly increases error margins during computing.

analog signals are represented as continuous voltages or currents, whose precision can be affected directly if any noises occur.


Data processing is completed much faster compared to that done by a low-power micro-controller unit that processes data in a sequential manner [1].

the configuration was done by setting the designated 140 atom switches (or 70 CASs) to the ON state in
each cell.


time programming memory allows avoidance of the external ROM and power efficient wakeup.

this has the drawback of a high programming voltage of more than 5 V, resulting in relatively lower scaling capability and higher operating power.


MyHDL is already a powerful language for hardware development.

we expect the per-device fault rates in an exascale computer will be similar to those observed in todays DRAM devices.


On the other hand, MyHDL has great support for parameterization.

myHDL did not have support for converting code that used attributes, so abstraction was limited.


However, they are simply outdated; poor parameterization limits high level design and modern abstraction features such as classes are missing.

myHDL has great support for parameterization.


The worst-case responses times calculated by the analysis tool SymTA/S are specific to the timing analysis model obtained after transformation of the MyCCM design model.

some calculated response times may be related to tasks and operations resulting from the splitting process explained in Section 3.2.


Operation calls in MyCCM are namely either synchronous (blocking) or asynchronous (non-blocking).

a major reason is the lack of engineering methods allowing the integration of the formal timing analysis in the different phases of the development process of real-time embedded systems.


Prior work has shown that DRAM vendors maintain an approximately constant fault rate per device across technology generations, despite reduced feature sizes and increased densities [9].


The wires on this bus are shared from the memory controller to each DIMM s register.

errors on these wires will be seen by all DRAM devices on a DIMM.


The figure makes clear that SRAM fault rates are dominated by faults in the L2 and L3 data caches, the two largest structures in the processor.

it is clear that faults occur in many structures, including smaller structures such as tag and TLB arrays.


The focus of this work is to provide insight and guidance to system designers and operators on characteristics of a reliable system.

our focus is on analyzing the efficacy of existing hardware resilience techniques, their impact on reliable system design, and whether they will be adequate for future systems.


We note in passing that rIOMMU relies on the predictability of the order of IOVA (un)mappings not the order by which the IOVAs are used by the device.

so long as IOVAs are valid (mapped), they can be used out of order.


Therefore, the existing IOMMU allows the I/O device to access an already unmapped buffer if the page in which it resides additionally houses a still-mapped buffer.

rIOMMU eliminates this type of vulnerability.


This property is appealing because different target buffers can, and often do, reside on the same page.

the existing IOMMU allows the I/O device to access an already unmapped buffer if the page in which it resides additionally houses a still-mapped buffer.


Importantly, ring semantics dictate that (1) the driver work through the ring in order, one descriptor after the other, and that (2) the I/O device process these descriptors in the same order.

iOVAs are short-lived and the sequence in which they are used is linearly predictable: each IOVA is allocated, placed in the ring, used in turn, and deallocated.


Write atomicity: For write atomicity, DeNovoSync0 simply uses a single-reader protocol for synchronization (at the word granularity, which is the coherence granularity for De-Novo).

a synchronization read is always required to register itself at the LLC and only one read can be registered at a time.


Correspondingly, the MLUs need to read f X 16 bits of centroids and u X f X 16 bits of testing instances at each cycle.

the read width of centroids and testing instances are different.


In different rounds of counting, the same training instance could also be reused, but the reuse distance depends on data characteristics (instead of algorithm characteristics), thus is not deterministic.

we cannot expect a predefined tiling strategy that can reduce the corresponding memory accesses.


Kernel matrix computation shares a similar locality property to distance calculations in k-NN, except that for each pair of instances, kernel matrix computation computes the value of kernel function instead of computing the distance.

we reuse the tiling mechanism designed for distance calculations.


The maximum Nmt of the sequential scheme case is fixed at gt +1 , regardless of the number of attempts of its proof generation process.

as the number of attempts of the process increases, the probability of the process completion also increases, and the time for the proof generation process with error control is faster than the proof generation process without error control.


In Juels protocols of [6], a pair of tags generates its replies until the timeout in order to limit the time for the yoking proof generation process.

the timeout occurs in each tag, independently.


One can observe a significant reduction of negative slacks at the primary outputs after optimization.

the number of primary outputs with negative slack reduced from 2004 to only 2 (i.e., more than 99% of reduction).


The priority of a location corresponds to its distance to the location assigned by Algorithm 1.

the more expressive reductions are obtained on circuit leon3: 11.89% on wns and 23.20% on tns.


on average, our technique further improves wns and tns by 13.42% and 20.18%, respectively.

the more expressive reductions are obtained on circuit vga lcd: 50.22% on wns and 89.52% on tns.


Taken the input and output TVFDs into account, each FF can find a feasible region for movement without violating timing, which we label as timing-violation-free region (TVFR) in Figure 2.

clustering a few single-bit FFs with overlapped TVFRs can optimize power and area without violating timing constraint.


Then the group of AB and the group of CD will be clustered into a 4-bit group.

the basic idea is to propose an exact formulation of the number of clusters based on the Dirac delta function, and smooth it using the Gaussian function to make it applicable in a nonlinear programming (NLP) framework with another objective in wirelength.


The solution after one step of the Nesterov s method, at line 4, may violate the timing constraint.

we apply a projection step in line 5 to find a closest solution in the feasible space to replace the intermediate infeasible solution.


As is shown in Figure 5(a), when FFi is adjacent to less than 3 FFs, FFi will attract more FFs to form a cluster of size 4; when there are more than 3 neighbors, FFi will repel the extra FFs.

it guarantees the maximization of 4-bit clusters number.


For example, two resilient processors can work at the same frequency, however due to process variation, one may have more timing errors than the other when running the same benchmark program.

the metrics of resilient system binning are more complicated than traditional binning.


Fig. 1(d) finds nearest legalization spot for each cell.


Only then (in a third step) will we be able to tackle the task of analog layout synthesis (i.e., fulfilling requirements) in a comprehensive and consistent manner.

analyzing and verifying capabilities are a precondition for synthesizing [4] (Fig. 2).


The purpose of this paper is to give an up-to-date overview of analog design automation, highlighting physical design, its specific characteristics and its current research areas from both an industrial and an academic perspective.

we will first review the analog layout design problem itself and discuss various aspects of today's design flows.


Some promising approaches are described below.

procedures re-use expert knowledge with the result of solutions previously conceived and captured in a procedural description by a human expert, thus imitating the expert's decisions in a straight-forward manner.


Some reasons are that (1) the design is too application-specific, (2) even small changes to the circuit may require large changes in layout, (3) a new technology node is used, and (4) the shape of a layout module does not fit.

careful consideration reveals that the underlying reason is that the layout view does not encompass any remaining degrees of freedom.


This shortfall is primarily rooted in the analog IC design problem itself, which is very much more complicated even for small problem sizes: it deals with a large number of specific circuit classes; it requires a customized design approach for each circuit class; and analog circuits are very susceptible to noise and process variations.

the work and costs involved in producing analog layout is a serious bottleneck in IC design, despite numerous attempts at automating the process.


If an I/O device supports single-root I/O virtualization (SRIOV), a VM is able to issue I/O instructions directly to the device in a way that is isolated from other VMs, and therefore VM exits are avoided when I/O instructions are issued.

this is achieved through careful installation of timer interrupts that the hypervisor sets up on a dedicated core and migration of timer interrupts that a VM sets up when the VM is suspended and migrated.


Their signal is also strongly affected by motion noise and usually requires complex filtering/preprocessing steps.

we achieve an error rate as low as 7% (based on eye motions alone) for the word count estimation (std = 0.5%).


This observation about pure movement and fine motor parts of the overall task has an impact on the Fitts’ index of performance, and index values (3) and (4) may signi.cantly difÂ fer, depending on the task.

the observation that the overall task can be divided into different parts implies that those indices are not competing - they are simply conveying different information.


In our implementation of the telerobotic Fitts' task, we consider two types of pegs, "thick" and "thin", with widths respectively equal to 8.00 and 4.60 millimeters.

this may indicate that the subjects are getting fatigued or annoyed (even though their performance is improving).


We currently know that, in both continuous and discrete settings, the only kernel that abides to the scale-space axioms is the heat kernel.

even though there are indications that the same kernel also applies to graphs [12, 27], a rigorous examination of graph scale-space is -to this point-missing.


Though Theorem 1 establishes the properties of graph scale-space kernels, it does not provide an explicit form.

many possible kernels may exist that satisfy the scale-space axioms.


Considering the high irregularity of wireless networks, columnstochasticity would exacerbate the phantom extrema e.ect.

with random mean and variance (as compared to seven in our simulations).


Unfortunately, the gain of the darlington changes with temperature, hence, if its temperature changes, the output current and voltage rises steadily even if the bias is constant.

for deterministic results, the temperature of the darlington must be kept constant when changing Vbe.


The power consumption of the board without the use of the LCD screen is 148 mW (24 mA).

the bottleneck of the present prototype is the 24-bit AtoD which consumes close to 72 mA.


For monitoring in an apartment, a camera is needed in each room.

activity recognition using radio signals can cover a much wider area and can see through walls, while cameras cannot.


We see from Fig. 5(c) that, when RFI is absent, this is probably feasible because walking gives rise to highly fluctuating RSI while non-walking does not.

in the presence of RFI, the distinction between walking and non-walking is not so conspicuous, as seen in Fig. 5(f).


We use these data sets to investigate the effect of bandwidth on location-oriented activity recognition.

we investigate what happens if we use a bandwidth of 5 MHz, 10 MHz, 15 MHz, 20 MHz, 40 MHz, 80 MHz and 125 MHz.


Note that, when interference sources exist, all sub-carriers in the secondary data sets are with RFI while only some of the sub-carriers in the primary data sets are with RFI.

the secondary data sets are worst case scenario with RFI.


As expected, increasing B gives a better classification accuracy.

l1-weighting achieves an accuracy of 75%, 95% and 97% when using a bandwidth window B of 5 MHz, 20 MHz and 125 MHz respectively.


Therefore, we need to consider the RFI environment when training the dictionary.

the most telling observation is that, for ws = 1, the classification accuracy is merely 57% but if ws = 10 is used, an accuracy of almost 90% can be obtained.


The wireless devices for RTI can be placed outside the walls to enable them to see through walls or smoke to locate people or objects within the walls.

rTI has a broad range of applications in emergency response, security (e.g. hostage rescue), health
care, and assisted living etc. [4, 9].


We propose our networked dynamic sensing configuration solution to achieve robust structural sensing in our system.

the resolution of the X500 signal is too low to be extracted.


The area of the single comparator/error detection block responsible to runtime Trojan detection at the final output is also considered in the above QoR function when evaluating its magnitude for both [7] and proposed approach.

since only a single comparator/error detection block is used in both approaches, hence it has no impact on the QoR of both approaches.


It is concluded that the appropriate test temperatures for such temperature-dependent defects could be found based on the location of the defects and the properties of the materials involved in those defects [8].

tests that target these defects are generated.


It is known that a test's power dissipation depends on the previously applied test.

the same set of tests when organized differently dissipates different amounts of power.


In general, hot tests excessively occupy TAM in order to receive heating sequences.

cold tests underutilize the TAM because of many required cooling intervals.


Low-Power and Reliable Clock Network Design for Through-Silicon Via (TSV) Based 3D ICs.

kOZs occupy large layout area thus might  be infeasible in case that layout whitespace is limited.


When multiple TSVs are present, we assume the TSV and silicon substrate are linearly elastic structures, then according to the stress superposition principle explained in multiple papers [8, ?, ?], the stress coming from several different bodies is the sum of the stress applied separately.

the stress value at a certain point is the accumulative TSV-induced stress caused by each TSV: .


Nicolaidis et al. [16] proposed a built-in self-repair method that can be used for on-line faulty TSV recovery.

in the first experiment, three representative cases of TSV failures, which includes that all TSVs are fault-free, only 1 TSV is faulty, and 2 TSVs are faulty respectively, are considered to verify the function of the proposed scheme.


Moreover, several types of TSV defects are latent and may easily escape detection during the manufacturing test.

these latent TSVs are prone to degrade during the field operation and may eventually become faulty and then destroy the entire 3D-stacked IC.


The yield of 3D DRAM can be significantly elevated since any 2 faulty TSVs within each group can be tolerated through this scheme.

up to 50% of additional TSVs need to be designed in this scheme, thus rendering a very high cost.


The logic low value of Pc11 will cause the Pr21 to be set to logic high value and renders disconnecting between Sginal2 and TSV2.

hence, in order to improve the yield and the quality of 3Dstacked ICs, several faulty TSV repair strategies have been proposed and typically use the neighboring TSVs to replace faulty TSVs.


Hence, as for more general discussions, we need to discuss not only the case that those assumptions are true, but also the case that those assumptions are not always true.

in this paper, as the first attempt to establish the framework of temperature dependency aware skew design, we will focus our attention on the former case.


Additionally, since an application typically processes much more data than the number of instructions executed, most prior cache locking methods, if applied directly to the data cache, would require a large data cache and/or potentially result in runtime overhead in terms of performance and/or energy, since complex runtime analysis wou6 ld be required due to the inherent runtime variability of data caching [21].

we propose a new methodology for leveraging cache locking for data cache performance and energy consumption optimizations in general purpose embedded systems.


For example, for gromacs, our methodology locked two phases x and y that comprised of 34% and 17% of the application's execution, respectively.

assuming this a priori knowledge limits these methods' applicability to general purpose embedded systems (e.g., smartphones, tablets, etc.)


Yang et al. [21] used a dynamic programming algorithm to determine the locked contents in order to improve the data cache's power consumption and performance.

Shen et al. [16] showed a strong correlation between data locality and an application's phase characteristics, and showed that data reuse patterns could be used to classify phases.


Caches are commonly used in embedded systems to bridge the processor-memory performance gap by exploiting the spatial and temporal locality of memory accesses.

caches can contribute significantly to overall system energy consumption (e.g., the ARM920T's caches consume up to 44% of the microprocessor's overall energy consumption [15]).


Much previous work studied cache locking's execution time predictability benefits and phase classification for exploiting an application's runtime variability in isolation.

little prior work exploits cache locking for optimizing the cache's performance and/or energy consumption while considering runtime variability.


Such a structure effectively reduces the transistor numbers of a single TCAM cell to 3.

all these MTJ-based TCAM designs face a severe design challenge the small difference of MTJ s high and low resistance values (usually only a few KO) produces a very limited sensing margin, which significantly degrades the reliability of TCAM design, prolongs the searching latency and induces extra power overhead.


Compared to SRAM-based TCAM with 12 transistors (12T-SRAM) [9], these designs significantly decrease the number of transistors and therefore reduce the cell area [6][7][10].

the match line (ML) is connected to a sense amplifier in reading and searching operations, while a pair of source lines (SL and SL) are used to supply the programming or searching data.


Naturally, the larger κ induces a bigger gap between the sensing voltages of match and miss conditions.


However, the atomistic treatment of BTI leads to a statistical and con.dence-based perception of those metrics.

given the variable manifestation of BTI it is imperative to employ statistical methods.


We observe that the performance is highly dependent on the design topology.

a significant portion of the datapath corresponds to variation-critical registers, reducing the performance of Algorithm 1 compared to ISCAS85 benchmarks.


Figure 4 shows that the number of functional samples decreases as we reduce the supply voltage.

decreasing VDD to meet a power constraint could lead to an increased number of non-functional modules.


Since the Nangate 45nm library consists of more than 130 standard cells, it is hard to list all the results.

ten typical standard cells are listed here.


More importantly, the standard cell library should be carefully designed to enhance the pin accessibility.

i/O pins need to be balanced distributed within a cell, as the alignment or the densely packing of pins make the cell more difficult to be accessed.


Besides, the fast method can get very comparable results, in terms of both wire-length and pin access values.

through fast cell routing the pin access value is 2% less, the wirelength is increased 0.7%.


Due to the unidirectional shapes of MOL and Metal-1 layers, the patterns are SADP friendly.

the line-space array decomposition can be applied to SADP with trim masks, with tight control on overlay and wafer-print artifacts.


The sequence of wire segments is determined based on the LP solutions in descending order.

the wire segment with the biggest xi is assigned first.


For compute-intensive applications however, due to the lower number of accesses to the memory, the higher cache access cycles at higher frequencies can be tolerated as it does not affect the IPC significantly.

for this group of applications the performance increases with the increased frequencies.


As described in Section 2.2, in order to see the ITD phenomenon, we have to operate the core at lower than nominal voltages.

for the ITD-aware schemes the operating point of 85% and 75% of the nominal voltage are investigated.


At high operating voltages, the threshold voltage change will have little effect on (Vgs - Vt) and thus, the mobility will determine the effect of the temperature on the device speed.

at low operating voltages, the threshold voltage will determine the effect of temperature.


Assuming 20% of our post-layout top critical path will be RC-delay and 80% cell-delay, the di.erence between pre-layout and post-layout speedup for 25.C to 125.C, will be 7% lower in 20nm at nominal voltage.

post-layout speedup as a result of increase in temperature is lower than that of pre-layout.


For R on=10^5 Ω, the critical falling point is around 0.66V.

the ON and OFF states of memristor can be respectively mapped to HIGH and LOW of V out if setting Vg within the range from 0.34V to 0.66V.


For spatio-temporal applications, CNNs can offer vastly superior performance and power efficiency when compared to conventional von Neumann architectures.

there are many ways in which both the performance and implementation complexity of a CNN system could be improved.


More specifically, our approach dynamically monitors the platform and adaptively adjusts to the COP among multiple cores, using lightweight checkpointing and roll-back mechanisms adapted from Hardware Transactional Memory (HTM) for error recovery.

we support two distinct types of recovery mechanisms: non-critical and critical.


Note that the data only need to be logged the first time the address is written within a specific transaction.

the log size depends on the write footprint of each transaction.


To showcase the reconfiguration aspects of our proposal with respect to the volume of faults, we present our gathered statistics in two different sets of graphs.

the top graph in Fig. 6 depicts the simulation results assuming SRAM pfails up to 10-4 (low-pfail case), whilst the graph in the bottom shows the corresponding results for pfails ranging from 5×10-4 to 5×10-3 (high-pfail case).


Furthermore, this is not the only advantage of spare mode over VS mode in high probabilities of faults.

the spare mode has the extra benefit of lower power consumption (in VS mode after a hit at the extra cache a block is exchanged between the main cache and the extra one).


At the lower level, the LRUL (left) and LRUR (right) show the least recently used subblock in the left/right array respectively.


As explained in the previous section, the victim cache, due to faulty block disabling, confronts the misses caused by faults in the main cache as conflict misses.

the victim cache copes with conflict as well as faulty misses while the spare cache mainly copes with faulty misses.


After getting the continuous solution, we usually use nearest rounding to project to discrete solution.

during the nearest rounding, it is hard to tell whether we should round up or round down the continuous size, since it may introduce extra cost when the continuous solution is either rounded up or rounded down.


This is because it is most suitable for a TCAM-based implementation of the checker which allows storing/parallel-checking against the individual test cubes, containing don t-care bits.

even after minimization, the number of test cubes can be prohibitively large.


The FA-Ag procedure results in adding more false alarms per iteration.

the number of iterations may be smaller because more minimization is possible due to a higher number of expanded cubes per iteration.


Moreover, unlike the redundant ALU case, the MUXes in (a) are not on the critical path.

these MUXes can be sized much smaller than the MUXes used for the redundancy technique in Figure 2(b).


Finally, column %Imp. represents the performance improvements resulting from the proposed synthesis strategy.

the gates that have fanout grater than '1' will be duplicated so that their output signal remains intact.


The BDI method [14] leverages redundant patterns (e.g., zero blocks, narrow values and low dynamic range patterns) exhibited by adjacent data bytes/values within a cache block.

bDI divides a cache block into several sub-blocks and represents the entire block as two base sub-blocks (a zero sub-block and the first non-zero sub-block) plus the difference information (Δ).


In contrast, SOCO's compression is dedicated to reducing power consumption in NVMs rather than the traditional goal of saving memory space.

sOCO leverages a cache-block-level delta-based compression scheme similar to the one used in prior work [14] but utilizes an essentially unmodified page management mechanism to enhance compression effectiveness and reduce overheads compared with the leading capacity oriented scheme [13].


We adopt the PCM latency and power model used in prior work [12].

sOCO s minor degradations are mainly caused by compression/decompression latencies and add a nominal 0.18% and 0.1% for STT-MRAM and PCM, respectively.


For practical use of polar codes, SCL algorithm that consists of multiple SC component decoders is usually adopted to improve the performance of polar codes.

the original SCL algorithm is challenged with its inherent long latency.


Besides, use of LLR instead of likelihood in SCL algorithm was proposed in [6-7] to save area.

this paper presents LLR-based 2b-SCL decoder that decodes 2 bits simultaneously.


Word-level compression schemes like FPC reduce bit-writes by leveraging program data statistics to eliminate redundant bit-flips.

in doing so, the bit-writes for a few of these cells are increased in comparison to other cells within the same word.


For uniform data traffic, the average Hamming distance between the existing and incoming data is the same for mirrored/un-mirrored data.

fPC and FNW operate only on un-mirrored data; this motivates MNW to take advantage of the possibility to reduce bit-writes using data mirroring, regardless of the success of FNW/FPC.


Whereas FPC reduces the cumulative bit-writes over uncompressed data with DCW (area under the curve), FPC concentrates peak bit-writes at bit indices 63, 62, and 61, which negatively affects NVM endurance.

fNW reduces the bit-writes across all bit indices in comparison to FPC, i.e., FNW is better for NVM endurance in comparison to both FPC and DCW.


In practice, this may lead to premature failure of these cells.

although FPC is successful in reducing cumulative bit-writes, it may do so at the cost of NVM endurance by increasing the peak bitwrites per cell.


To overcome these problems, a broad set of solutions that rely on dataencoding [5], write scheduling [6 9], data-migration using address translation [10 12], and architectural improvements [13, 14] have been proposed.

these techniques address either NVM latency, power/energy, or endurance explicitly; this potentially limits their effectiveness in practice.


The inclusion of an SSL makes the yield of one core in the pair dependent upon the yield of the other: if one core needs the shared spare lane, it is only available if the other core does not.

there is no straightforward formula to calculate a single core s yield when both SSL and spare cores are present.


We made the bins in Table 1 as large as possible without complicating their definition (e.g., by combining two disjoint or partially overlapping sets).

some POF designs do not fit well into the bins.


A review paper on sub-threshold design was presented in [15], in which the authors suggested an ultra dynamic voltage scaling technique, which dynamically scales the power supply voltage to subthreshold operation.

traditional dynamic voltage scaling techniques restrict the minimum supply voltage to super-threshold operation [16, 17], providing less aggressive power scaling, while ensuring that PVT variations do not become an issue.


One possible approach of identifying hotword is to upsample the accelerometer data collected at 200 Hz to 40 KHz, and then reproduce some parts of user's spoken words from the resultant audio file.

this can incur huge energy cost due to the computational complexity of upsampling as well as analyzing the additionally generated data.


More recently, in [1], the author employs an anonymous wireless USB device to spy on keystrokes from a wireless keyboard.

this work relies on the information of the data-transmission protocol of the wireless keyboard and its weak security features.


As described in the previous section, for a given location of the hacker, the orientation of the hacker relative to the user can change depending on the keystrokes pressed by the user.

for a given pair of antennas at the hacker, while they might show high sensitivity for a pair of keys pressed by the user, the same pair can demonstrate poor sensitivity for another set of keys at a different orientation.


The desired sensitivity enables the hacker to distinguish between the location of the user's finger on one key from its adjacent key.

the variance of this distribution tends to zero as we increase the delay mismatch.


We observe that the average sensitivity decreases as we increase the delay mismatch.

while the sensitivity decreases we observe that even for a delay mismatch of one sample duration, the two keys can be reliably distinguished.


This operation only determines the location of the trough and does not vary the width or robustness of the trough location.

in this operation we are not changing the delay of the signal but simply changing the phase to ensure location of the trough.


Measurement noise and multipath can cause variation in the observed phase of the two streams which in turn causes variation in the observed trough location for the same key press in the case of small delay mismatch.

as we increase the delay mismatch, we decrease the sensitivity of the hacker and the trough location for a given keystroke is more robust to measurement noise.


For this reason the training information recorded in the experiments is the sensitivity between pairs of antennas for each keystroke.

while user movements can change the absolute trough locations, the keystroke is still reliably identified by our algorithm since the relative trough location does not change.


However, when there are changes in the environment, such as a person walking in the vicinity of the user-hacker setup can cause the location of the trough in the spectrum to change.

it is important for the keystroke detection algorithm to differentiate the cause of movement of the trough location in the cancellation spectrum due to an actual keystroke from that caused due to channel variations.


With a short ≈ 10 character training input, this accuracy drops to 85%.

in addition to a trough detection algorithm, the spectrum analyzer block also runs an amplitude matching algorithm.


As expected from the discussion in Sec. 3.2 the sensitivity decreases as the delay increases.

the lack of sensitivity assists in reducing the variation of the trough location due to measurement noise.


Considering the influence of delay mismatch on the performance of the receiver, we observe that for majority of the scenarios considered in this paper, a fixed delay mismatch provides sufficient performance.

in our implementation, we fix the delay of this partial sample delay block and thus the delay mismatch between the two streams.


We place the keyboard close to the transmitting antenna and at a lower plane to mimic the setting of a typical laptop.

further, we illustrated the cancellation performance’s sensitivity.


It also applies to the quantum case whenever a classically defined oracle arithmetic function must be embodied in the quantum algorithm.

the first phase (see Fig. 1) of the QDG construction is dedicated exclusively to the forward computations, without taking into account the resetting of the possible ancillae qubits.


Generally, Adapt should have no worse slowdown than Fix4.8, which is the fastest fixed configuration.

in a few cases, Adapt is slightly worse.


For this purpose, COMeT+ keeps a pool of tested free pages to quickly service allocation requests.

too high of a rate may be harmful: Competition can be caused between testing and the workload.


The process is inherently memory bound and time consuming, particularly for the most advanced diagnostics that apply several bit patterns in many sweeps.

most memory diagnostics are done o.ine when the system is not actively serving a workload, such as during boot-up [1] or periods of low utilization (e.g., overnight) [13].


The target busy time in phase 2 can be overlapped by different instructions to boost I/O throughput in a single channel.

it doesn t mean that all instructions can be executed randomly.


Meanwhile, the multi-level cell (MLC) and triple-level cell(TLC) technologies that constantly reduce the price of flash, make NAND flash based SSDs more competitive than HDDs.

for better illustration, we have chosen four general workloads for tests, which are Sequential Write, Sequential Read, Random Write, and Random Read.


Some high-end commercially available PCIe flash storage systems are believed to have used the synchronous interface such as Huawei ES3000 [2], which is alleged to provide up to 770K (4KB block) read IOPS performance and up to 630K (4KB block) write IOPS performance.

there are few publications on design and detailed implementation of flash controllers based on source synchronous interface.


Generally, events of cache miss or replacement or garbage collection will trigger FTL to generate flash operation instructions, which are expected to be executed by downstream Dysource controllers.

the interaction between the FTL and Dysource Controller must strictly follow an interface protocol defined in Dysource Controller.


As the demands for analyzing more and more data increase, we are faced with new challenges.

traditional architectures where data needs to be fetched from memory as to be processed, are becoming a bottleneck.


In the case of SMG, the 5% maximum performance degradation set for object placement is not aggressive enough to enable the same energy savings as RaPP.

page migration is necessary to deal with these fluctuations, but page migration comes at a cost: observing characteristics, learning patterns and reading and writing page-sized chunks of memory.


Reducing the supply voltage of server CPUs is one of the most e.ective methods to lower power consumption.

the effects of process variations become more pronounced with reduction of supply voltage, leading to failures of many circuits.


Fortunately, according to [1], the fully parallelized SEC-DED design is simple and fast, with only 14k gates of hardware and one cycle for either the encoding or the decoding process.

the 4EC-5ED design needs about 50k gates and a 14-cycle decoding latency.


Afterward, our strategy to improve the FTC precision is altered from avoiding fluctuations to tracking them.

a novel version of the FTC, referred to as fuzzy compression adaptive transform (Fuzzy-CAT) is presented.


As opportunities for future work, we consider setting up predictors for mitigating the effect of long delay inherent in the compression process, as well as automating the optimization of the transform parameters.

fuzzyCAT exhibits a compelling advantage over the regular F-transform.


Matrix-vector multiplication in Eq. (1) is the core operation of one of the commonest computation (namely, “recall” process) in NCS.

cLD is an iterative scheme to update weights (resistances) of memristors according to the feedback from outputs [10].


Unsupervised learning with sparse coding is widely adopted in applications of feature extraction, pattern classification, and compressive sensing.

even with the state-of-the-art hardware platform of CPUs/GPUs, solving a sparse coding problem is still expensive in computation


The block of ETAII (a carry generator and a sum generator) is significantly simpler than those of SCSA and ACAA.

eTAII has a shorter delay and consumes less power and area than SCSA and ACAA, thus ETAII is selected for circuit comparisons.


As shown in Fig. 1, an AND gate can implement multiplication: given that the two input stochastic bit streams are independent, the probability of ones in the output bit stream equals the product of the probabilities of ones in the input streams.

a large c will not help reduce the approximation error.


To make this error small, c should be large.


We further examined the devices with the largest number of discarded blocks and found that the number of blocks that are discarded is not correlated with the amount of data written to or read from flash cells (examined in Sections 4.1 and 4.2).

platforms A and B contain SSDs with around two or more years of operation and represent 16.6% of the SSDs examined; Platforms C and D contain SSDs with around one to two years of operation and represent 50.6% of the SSDs examined; and Platforms E and F contain SSDs with around half a year of operation and represent around 22.8% of the SSDs examined.


we observe SSDs of both low and high usage across their lifetime (measured by flash cell reads and writes) that have discarded large amounts of blocks and have high failure rates.


The IEEE 30 bus power system model is used to demonstrate the effectiveness of the simulated testbed.

with delayed reclosing signal for cyber intrusion, the speed and terminal voltage of the goes out of step and control.


Smart grid is a complex cyber physical system containing a numerous and variety number of sources, devices, controllers and loads.

smart grid is vulnerable to the grid related disturbances.


Simulation of only the designed power system will not incorporate the behavior of SCADA systems.

simultaneous combination between power systems simulation and SCADA systems simulation is required.


In this paper, we will demonstrate as they can be used to automatically achieve power management since the earliest stage of the design flow.

we are focussing on the automation of power gating.


This is due to the fact that these are the smallest kernels.

when the smallest kernels are executed and the biggest are powered off, the overhead of the introduced power management logic is less than the benefits of having no switching activity in quite almost of the system.


A dedicated power controller to properly drive these latter is also required.

to perform a single-cycle reconfiguration, MDC inserts in hardware low overhead switching modules (SBoxes) placed at the crossroads between the different paths of data.


Moreover, S must also contain a partition of the set of actors Vi/of each input network.

these issues limit their extensive use to application specifc scenarios.


Very often the focus has been on the PG physical implementation optimization, sometimes developing automated flows to cluster and interface different PDs [14].

as far as we know, no automatic frameworks act at a higher level.


MDC already embeds a power saving automatic feature [12].

it is able to analyse the input dataflow models and to extract from them the optimal actors partitioning in order to implement clock gating power management strategies.


Prior research in shared memory for HPC workloads has focused on optimized memory mappings for single OS/R environments.

in each multi-enclave configuration the performance is more consistent than exhibited by the Linux-only environment, demonstrating that our approach does not add variable delays to the runtime of the simulation.


More general inter-VM message passing techniques have been implemented via shared memory [19, 22].

exascale systems will require broader support for heterogeneous environments than these techniques support.


While it may be possible to perform shared memory mappings by modifying enclave address spaces remotely, it would likely be difficult to provide such an implementation correctly, and would at least require complicated and inefficient address space synchronization mechanisms.

first, the co-kernel architecture used to perform cross-enclave message transfers (which are required for the transmission of XEMEM operations) currently restricts all IPI-based communication with the Linux management enclave to core 0 of the system, and thus the presence of multiple enclaves may cause contention for interrupt handlers on this core.


CTLB performs better than 4 KB pages on small-memory workloads, such as cactusADM, canneal, and omnetpp.

cTLB provides little benefit on big-memory workloads and performs worse than THP overall.