This technique optimizes conventional caches by removing the need for tag accesses (and TLB accesses for TCE) on hits.

but we do measure the network traffic traveling to and from the CPU in order to capture any network traffic variations caused by the stash.


In our implementation, we require 7 bits of metadata for each run, where runs can be either 2 or 3 bytes long.

accounting for the metadata, we need only 2 3-byte runs, 4 2-byte runs, or a combination or 2-byte and 3-byte runs in order to free 4 bytes for ECC.


we find that in the context of COP, a simplified run length encoding can extract the redundancy in the same sign-extended values as FPC with less metadata overhead, allowing more blocks to be compressed.


To enable these decisions, we keep a simple direct-mapped table of the running average times of different SEED regions.

similar to dataflow architectures like WaveScalar [33], control dependencies in the original program become data dependencies.


Interestingly, well known explicit-dataflow architectures eliminate these overheads by directly executing the data-dependence graph and eschewing instruction-precise recoverability.

even after decades of research, dataflow architectures have yet to come into prominence as a solution.


In fact, it has been shown that about 85% big data processing tasks can be deferred by a day [40].

even if the renewable power output is intermittent and time-varying, we can still leverage it for processing many delay-tolerant data sets.


This is mainly because many data acquisition sites are temporary or difficult to reach -they lack established utility infrastructure.

standalone power supplies such as solar/wind system (with commodity batteries as energy buffer) are often more suitable for data processing in field.


Several studies propose performing data analysis while scientific applications producing data [22, 23, 85] or moving computation from compute node to storage servers [86].

architectural Concerns in Large Datacenters Workshop held in conjunction with the 37th International Symposium on Computer Architecture (ISCA), 2010


As Figure 2 shows, we explore the opportunity to benefit from data pre-processing using a group of inexpensive, commodity servers that are placed near the data source.

we are primarily interested in in-situ datasets that need to be processed timely but do not have a very strong requirement for real-time processing.


The cost benefit of InSURE increases when local data generation rate increases.

such green energy powered standalone systems are also economical.


We observe that most of the performance statistics of seismic data are very close to video surveillance.

this paper takes the first step towards designing server clusters for data processing in the field.


The optimization effectiveness of InSURE on server-related metrics becomes greater when the solar energy is lower.

the benefit of our joint spatio-temporal power management actually increases when the standalone in-situ system becomes heavily energy-constrained.


This overhead will be more pronounced as in-package DRAM size continue to scale up in the future as integration of 4GB [28] and 16GB [3] in-package DRAM will soon be introduced into the market.

reducing the tag overhead is a primary design goal even for paged-based in-package DRAM caches.


We would like to thank Jung Ho Ahn and Young Hoon Son for their help with die-stacked DRAM modeling.

most of prior work along this avenue proposes to augment the memory controller with counters to gather access statistics [12, 30].


The caching granularity in the proposed tagless cache is aligned to OS page size.

to effectively increase TLB reach, many modern architectures support superpages (e.g., 2MB, 4MB, and 1GB for x86_64 [9, 18]).


Table 3 summarizes architectural parameters.

this approach has an advantage of being readily deployable without modifying the software stack.


In addition, we introduce a simple hardware structure that monitors the locality of data accessed by a PIM-enabled instruction at runtime to adaptively execute the instruction at the host processor (instead of in memory) when the instruction can benefit from large on-chip caches.

our architecture provides the illusion that PIM operations are executed as if they were host processor instructions.


Our memory model ensures atomicity between PEIs.

a PEI that reads from and writes to its target cache block is not interrupted by other PEIs (possibly from other host processors) that access the same cache block.


To date, most of the existing PIM architectures are based on general-purpose computation units inside memory for flexibility across different applications [14 16, 25, 28, 35, 39 41, 46, 48, 50].

this introduces two major challenges in seamlessly integrating such architectures into conventional systems in the near term.


In summary, simple PIM operations interfaced as ISA extensions have great potential for accelerating memory-intensive workloads.

after the reader PEI execution, if there are no more in-flight reader PEIs to the entry, the entry is marked as writeable.


First, a local core can continue its execution after invoking a non-blocking remote function call since the core does not have to wait for the termination of the function.

it allows hiding remote access latency because sender cores can perform their own work while messages are being transferred and processed.


Adopting a high-bandwidth alternative to DDR3-based main memory based on 3D-stacked DRAM, called Hybrid Memory Cube (HMC) [22], helps this situation to some extent, however, the speedups provided by using HMCs are far below the expected speedup from quadrupling the number of cores.

once the packet arrives at the remote vault, the network interface stores function arguments to the special registers visible from the core and emits an interrupt for the core.


For example, in AT.LJ, the partitioning scheme eliminates 53% of non-blocking remote function calls compared to random partitioning (which is our baseline).

in some workloads, graph partitioning shows only small performance improvement (CT.LJ) or even degrades performance (SP.LJ) over random partitioning.


The explosion of digital data and the ever-growing need for fast data analysis have made in-memory big-data processing in computer systems increasingly important.

large-scale graph processing is gaining attention due to its broad applicability from social science to machine learning.


if we assume that cores can use the internal memory bandwidth of HMCs2 ideally, i.e., without traversing the off-chip links, we can provide much higher performance by taking advantage of the larger number of cores.


Unlike host processors that have access to the entire address space of the HMCs, each Tesseract core is restricted to access its own local DRAM partition only.

a low-cost message passing mechanism is employed for communication between Tesseract cores.


When there are only a few access ports, the total area of a racetrack memory stripe is mainly determined by the number of domains.

the area overhead of adding one more read port is moderate (mainly from peripheral circuitry).


Qureshi et al proposed adaptive ECC to reduce the overhead of error correction for PCM [27].

since the shift operation is unique to racetrack memory, detection and correction of position errors are not covered in previous research yet.


Second, even if ECC detects that misaligned bit is incorrect, it cannot decide the direction and steps of shit errors for certain.

we have to refresh all data in stripes to refill the correct data (if possible).


In other words, the domain is not aligned properly to the access port.

then, the run-time shift intensity can be calculated as 1/Tinter, which is used to select the safe distance for the current shift operation.


Such a position error is called "stop-in-middle" error in this work.

the domain is not aligned properly to the access port.


Unsurprisingly, ShiDianNao significantly outperforms the general purpose architectures and is, on average, 46.38 Ã— faster than the CPU and 28.94Ã— faster than the GPU.

the GPU cannot take full advantage of its high computational power because the small computational kernels of the visual recognition tasks listed in Table 1 map poorly on its 2,496 hardware threads.


The spectrum of a pulse train with an arbitrary duty cycle is equivalent via Fourier analysis to a set of sinusoids with various amplitudes at fc and its multiples (harmonics).

there often are several modulated carrier signals in the same general region of the spectrum, so that their side-band signals may not be neatly separated from each other.


To avoid clutter, Figure 7 only shows the three parts of the spectrum that contain the left side-bands, the carrier, and the right side-bands of the signals.

it does not show about 40kHz worth of spectrum to the left and right of the carrier.


a clock signal becomes stronger or weaker (amplitude-modulated) depending on processor or memory activity.

modern systems create emanations at thousands of different frequencies, so it is a difficult, error-prone, and time-consuming task to find those few emanations that are AM-modulated by processor/memory activity.


When a thread is interrupted while waiting at the barrier, the BARRIER instruction would be at the top of the ROB which results in the core sending a SUSPEND request to the MSA tile.

unlike locks which will simply dequeue the requesting core, for barriers we send FAIL (or ABORT) responses to all participating cores, i.e. we force the barrier to fall back to software.


Note that one could eliminate OMU entirely by simply allocating/deallocating when an entry is initialized and destroyed.

this significantly reduces the coverage of the accelerator, since from our evaluation, some applications will use more then thousands of locks.


The difference is largest in 64-core execution of radiosity, where lock synchronization is frequent, but with many low-contention locks.

this may be an important consideration for processor manufacturers -after adding the synchronization instructions and our MSA/OMU hardware, the processor manufacturer can drop MSA/OMU support in future generations of the processor without breaking compatibility with software that uses the new instructions.


Moreover, application-specific address mapping schemes that will lead to higher parallelism and locality can be determined via profiling.

simply changing the address mapping at the runtime will result in incorrect program execution the data need to be reorganized accordingly to retain the original program semantics.


Section 3.1 discusses how SLIPs are used to determine the insertion and movement of a line in a cache level.

the latency for each operation (evaluating the energy of all the SLIPs and finding the minimum energy SLIP) was found to be 2 processor cycles at a processor clock rate of 2.4GHz and the throughput is one computation per cycle.


The for loop body in line 418 rotates the rorig array, and does a streaming access of the array elements from c to r. These array elements are then immediately used in the loop body in line 421.

the temporal locality of these lines will depend on how close the parameters c and r are to one another.


The reuse distribution for a sampling page is loaded into the TLB upon each TLB miss, and all lines in that page are inserted with the Default SLIP.

when a page is in the stable state, the reuse distance distribution is not sampled, and the SLIP stored in the PTE is used to make insertion decisions.


Both these policies increase energy consumption due to excessive line movements.

sLIP intelligently inserts lines to an initial location based on the reuse distance history of the line, and avoids excessive line movement.


NuRAPID and LRU-PEA aggressively promote lines to nearer locations and thereby have a much higher fraction of accesses from those sublevels.

as we can see from Figure 11, this higher fraction is achieved at the cost of a significant increase in movement energy, which adversely impacts cache energy.


In a shared multicore LLC, the reuse distance of each reference is higher.

more references cause misses and end up being completely bypassed from the cache.


SLIP can be employed in caches using such interconnects to further reduce the energy consumption.

6b need to be stored per page (3b for L2 and 3b for L3), which can fit in the ignored bits of a 64 bit page table entry (PTE)2 .


Another 10% of accesses, however, require a larger 256KB cache, and the remaining 24% of accesses do not fit in the cache.

the system runs Ubuntu 11.04 over Linux 2.6.


This body of earlier work uses reuse distance to reduce cache misses.

sLIP employs reuse distance to reduce cache access energy by selecting a set of locations for a line to be inserted or moved into.


When a thread acquires the global lock for the irrevocable execution of a transaction, all of the other concurrent transactions will be aborted.

a conflict over program data will abort only some of the transactions that happen to access the same data at the same time.


A callback requires three messages: {callback, write, data} or {write, callback, data} depending on the relative order between the read and the write.


The reasoning is the following: in an environment with self-invalidation and self-downgrade, responsibility for coherence is distributed to the core caches when it comes to data-race-free accesses.

there is no need to track data-race-free data in a centralized directory.


The evaluation covers a wide variety of parallel applications.

we evaluate the entire Splash-2 suite [28] with the recommended input parameters.


Because the divergent applications traverse multiple independent control flow paths, restricting L1 I-cache bandwidth results in a significant performance loss.

the inclusion of per-slice L0 I-caches, which are probed first when independent warps fetch instructions, vastly decreases the performance loss.


General Idea of Super Block The notion of super block, first proposed in [25], tries to exploit spatial locality in ORAM.

it tries to load more than one block from the path in a single ORAM access.


(a) ocean_contiguous (b) volrend (a) ocean_contiguous (b) volrend Figure 12: Sweep stash size.

having smaller Z increases the background eviction rate.


We restrict that only neighbor blocks can be merged into super blocks.

as in the static super block scheme, only blocks with addresses differing in the last several bits can be merged into super blocks.


The dynamic super block scheme does not merge blocks during Path ORAM initialization.

all blocks have sbsize = 1 after initialization.


We claim that ORAM with a dynamic super block scheme maintains the same level of security as a normal ORAM.

adding dynamic super blocks to ORAM does not change the security guarantee of the original ORAM.


Given any two access sequences A1 and A2 of the same length, ORAM guarantees that the transformed access sequences S1 and S2 are computationally indistinguishable.

the ORAM physical access pattern (S) is independent of the logical access pattern (A).


Z = 4 is chosen here to make it easier to see the performance difference.

(Note that B' is already in the cache before merging) The changes are written to the Pos-Map block.


Dynamic mapping methods can overcome the adaptability and compatibility issues that static methods face.

due to the small instruction scopes and lack of speculation, current dynamic techniques fail to make the best use of routing resources in spatial architectures [10].


But generally the accelerator does not contain memory ports.

considering hardware resources is critical when generating mappings for spatial architectures in order to make effective use of PEs and minimize the datapath usage between them.


For example, in Figure 2(a), if extra data paths (shown by dotted lines) are applied to allow for forwarding operands from one row to the next, the mapping shown in Figure 2(b) is feasible.

forwarding requires extra cycles to complete and thus leads to lower performance.


Ideally, the cache should hold all the pages and all the read operations should be cache hits in DRAM.

indirections occupy memory, and therefore cache hits in DRAM decrease.


Second, we are investigating the benefits of combining the memory and file system layers for byte-addressable persistent memories.

we are evaluating the benefits of a combined indirection layer for leveraging existing file system code as a control plane to manage persistent memory while leveraging virtual memory as a high-performance data plane to access persistent memory.


Data dominates metadata in our applications which usually map large files to memory.

having separate translations inside the SSD for metadata of the file system does not add significant overhead.


POSIX mmap specifies that the OS may pick an address of its choosing to map the file if the address requested by caller is not available.

as this scheme itself is deterministic, it is still possible for a process to map a file to the same address across reboots.


MySQL on PCIe SSD's Tpm-C was 8.7x lower compared to MySQL on DRAM for a 480GB TPCC database.

the SSD setup cost 11.1x less compared to the DRAM setup that makes the SSD setup 1.27x better when performance is normalized by cost.


to address these problems, FlashMap introduces a new virtual memory design where the page table pages needed for mapping a file belong to the file system and are system wide resources shared across processes mapping the same file.


data-intensive applications are using SSDs as slow, but high-capacity non-volatile memory [39, 35, 38, 5, 45] via memory-mapped files.


Figure 9 shows the number of networks that would be detected.

one to four random obstructions that cause 1.8dB attenuation per meter of penetration are introduced in the path.


As said before, our hypothesis is that aerial networks are less affected by building shadowing.

we have also performed this measurement in an environment where all buildings are higher than 30m.


The next bottleneck will then be the divide for DP (84 cy) and the L3 transfer time for SP (78 cy), respectively, but both of these are purely core-local.

in column 5 we give the leading dimension below which the respective layer condition is satisfied.


In the fault not activated cases, the Redundant scheme has a significantly greater overhead than the other three schemes, and the overhead increases as n increases.

for smaller values of n, the normalized runtime of Redundant is less than twice that of the baseline experiments.


FC-O has the best performance in terms of runtime when no errors are present.

when errors are present, the overhead of FC-O increases significantly, such that its performance is even worse than the Redundant scheme.


This is guaranteed by Clover as shown in the proof of Theorem 1 and 2, i.e., all the idempotent regions are resilient against DUE.

clover can achieve zero DUE as long as program is compiled by Clover.


That is, even if soft errors have already corrupted architectural states, Clover can recover from the errors, and the detection latency does not need to be zero.

idempotent processing requires soft errors to be detected within the same region as stated in Section 3.


In particular, if a region is so small that all its instructions should be protected by DMR (i.e., the tail-DMR frontier is set to the beginning of the region), the sensor may detect an error occurred in the region after it is finished.

at this moment, the error must have already been corrected based on Theorem 2.


The error detection latency determines how long the tail part of idempotent regions (tail-DMR) should be to guarantee that its execution time is greater than the detection latency.

the length of the DMR-enabled part is subject to the error detection latency, i.e., a lower soft error detection latency allows a shorter DMR-enabled part (lower performance overhead) but at the expense of more sensors on the chip (higher area overhead).


In particular, Clover avoids such high overhead by integrating idempotent processing that recovers from soft errors by simply re-executing the region in which they occur.

even if soft errors have already corrupted architectural states, Clover can recover from the errors, and the detection latency does not need to be zero.


This directly contradicts the assumption, since the DMR detects all the errors that occurs in the tail of the region.

if the error occurs in the DMRenabled part (i.e., tail) of Rc, the error must be detected by Rc.


This is necessary to prevent the errors occurring in the tail of a region from escaping to following regions.

any live-out registers, that are defined in the tail of the region, are required to have check instructions before the region boundary.


An idempotent region is a part of program code that can be freely re-executed to generate the same output.

characterizing application memory error vulnerability to optimize datacenter cost via heterogeneous-reliability memory.


This paper calls such a boundary tail-DMR frontier.

the compiler determines the frontier so that the DMR-enabled part (i.e., tail) has to be as long as the worst-case sensor-based error detection latency.


Overall, the full-DMR with with idempotent processing incurs 105% runtime overhead on average.

clover incurs only 26% runtime overhead on average, which is a 75% reduction, at the expense of only 1% chip area overhead.


Therefore, the error is to be identified by the sensor-based detector before the tail of Rc finishes.

it is impossible for the error to escape from Rc.


[25] uses a classical graph coloring to assign a color to each variable and makes all the variables with the same color share the same space.

the size of the interference graph is reduced, leading to fewer false dependencies.


A cost function is proposed for each pre-header of loops to determine whether this pre-header should be selected as a loading point.

secondly, the false dependency problem is less serious in the iterative ILP approach than in the global ILP approach due to the much smaller size of each y-projection graph of the interference graph, resulting in more eficient utilization of the D-cache.


The only difference between load and xload is that xload can still load a variable into a cache line even though the cache line is already locked.


The attacker is able to physically access the memory when the device is powered off, or at any time during application execution, and plug it into his/her own device to perform an intrusion attack.

the attacker does not know how long the program has been executed at the time intrusion is performed.


Study three will use a design science perspective to retrospectively evaluate current crowdsourcing platform designs to assess the viability of these platforms to support the interests of both services buyers and sellers examined in Studies 1 and 2.

study 3 will address the following questions: How effective are existing technology crowdsourcing platforms at delivering value to the technology workers and the technology buyers who use them?


It is posited that the same architectural standards that facilitate distributed intra-firm development, can be used to support crowdsourcing engagements Building on this thesis, Study 2 will explore the awareness, perceived preparation, usage intentions and usage levels of IT crowdsourcing services by IT services buyers.

study 2 will examine the following research question: What determines enterprise readiness to use technology crowdsourcing services?


Since the translation is purely combinational, it is also referred to as Combinational Clock Gating.

only one of these signals can participate in the final gating condition as both these signals are synchronized signals.


As we can see, LRU method provides relatively low accuracy and high falsealarm rate, which may cause significant backup energy and performance penalty.

other complicated DBP methods, which are dedicated to high performance applications, introduce unacceptable hardware overheads in an embedded system.


When combining the above constraints with tight project timelines, it is common practice that designs are taped-out when the verification confidence is deemed sufficient.

they are the dominant type of design errors that escape to silicon.


In this work, we explicitly model the uncertain characteristics of system components.

we describe the reliability of a component using arbitrary reliability functions (exponential, Weibull, custom) with parameters that are arbitrarily distributed between best-and worst-case bounds.


In our calculations, if an error causes the pipeline to stall persistently or causes an exception in a clock cycle, this exception will happen at every clock cycle from that cycle until the end of the simulation.

the propagation probabilities in these cases are skewed to the cycles closer to the end of simulation.


The aforementioned protection schemes mainly target scan chains, while protecting user-defined backdoors has gained little attention.

as chips become more complex and have more debugging functions, these backdoors have introduced more vulnerabilities that need to be addressed [7]-[11].


Field Programmable Gate Arrays (FPGAs) have some of the advantages of hardware accelerators and are also programmable [3].

their fine-grain reconfigurability incurs a very high cost in terms of energy efficiency [4].


The operations from the if-path and else-path form the set of operations Nif and Nelse respectively.


Also, the benefit of having several high-dimensional spaces with a large amount of precise information often yields a computationally difficult problem.

the remaining parts (motorized stage, EM probe, amplifiers) were made with low-cost off-the-shelf components with an overall price of less than USD 250.


While SCARE is mainly concerned with recovering individualvalues, e.g., S-box tables, of a (partially) known algorithm,SCANDAL attempts to extract code from side-channel information.

by measuring and analyzing theside-channel leakage of a ÂµC, the goal is to extract the executed instructions.


Therefore, they allow designers to explore various architectural options for different design objectives.

such exploration has exponential complexity, making it practically impossible to explore the entire design space.


Another reason for the choice of these optimization techniques is that they are commonly available in most of the HLS tools [8].

our framework can be integrated with a variety of different HLS tools.


In this work, we address the two main concerns of any digital system design: performance and hardware usage.

the framework can be applied to include other criterion as well.


In addition, bank switching results in a more complicated logic for the generation of the addresses to the memory banks, since each bank must be addressed by one of five different combinations of the (i, j) indices as the loop proceeds through the iterations.

we also need additional multiplexers driving different addresses to each of the four memory banks, depending on the iteration.


When one task finishes, it will notify all its successors.

each task should figure out how many predecessors have been finished and how many successors need to be notified.


However, due to the complexity of accumulated variations, it is hard for designers to determine which TAS strategy works best for a given MPSoC TAS problem.

quantitative evaluation of TAS strategies is becoming an important issue to guarantee the performance yield in MPSoC design.


A processed input is delivered to the Code (PIM ) through a finite buffer whose size is defined in the parameter buffer-size.

there are two cases when the processed input needs to be inserted into the buffer: (1) the buffer has an empty slot, and (2) the buffer is full.


Typical phylogeny reconstruction methods are based on genomic distance (e.g. neighbor joining), combinatorial optimization (e.g. breakpoint phylogeny), or statistical methods (e.g. maximum likelihood (ML)).

these platforms typically have mesh-like wired NoCs (obvious choice due to ease of VLSI implementation) and high power budgets.


The microprocessor power consumption is a major design constraint, which affects performance and reliability.

it is of decisive importance to co-optimize performance, reliability and power at runtime by applying fine-grained adaptation techniques.


With more accurate technology data, the inaccuracy would be lower.

if the self-calibration is employed, the inaccuracy for the combined power consumption is reduced to a negligible value.


In this regard, the efficiency of the adaptation (performance penalty vs. power/temperature reduction) strongly depends on the available spatial power information.

the final system performance employing more localized adaption techniques will be considerably better [8].


Beside the micro-models themselves, it is a challenge to select and frequently access the performance counters that are required to feed the micro-models.

the access is a very demanding task, as various SPRs (here: 31) need to be accessed at almost the same time (to make sure that the gathered data is correlated).


Compared to the linear regression based model proposed in [13] that estimates the combined power for each core, our model is much more accurate.

it can capture the workload trend, which is not possible with simpler models as shown in Fig. 2(a).


Near Threshold Computing, in which the supply voltage is only slightly higher than the transistor s threshold voltage, is a promising approach to reduce the energy per operation.

this methodology is highly sensitive to parameter variations and requires a combination of architectural adaptations or specific software techniques to mitigate the effects variability-induced heterogeneity [5].


In fact, design at the Electronic System Level (ESL)with SystemC as its de-facto standard [7] is established inindustry today.

the proposed methodology does not only pinpoint the designer to the switch but in addition to that even to the respective parts of the receiver.


Often, the documentation is not as detailed as needed or became obsolete due to changes in the implementation that have not entirely been propagated [10].

feature localization is a crucial step within the design process which, thus far, has mainly been conducted manually (e.g. by inspecting the HDL implementation).


The features a designer may look for in this system may be concerning the distribution of data.

which parts of the design are triggered when a package is sent to a specific destination might be of interest.


The dynamic behavior supported by SystemC particularly differentiating between multiple instantiations of the same type of class are not supported.


Cell voltage increases monotonously with SoC, however.

encouraged by these results, we are interested in the design of components specifically for the purpose of cell balancing.


To exploit reuse, the data in the window buffer (stage 1b) is shifted left and the next two columns of data are loaded.

this also means that the programmer has to have knowledge of hardware design and perform the optimization steps (e.g. extracting parallelism) manually.


Current design methods for accelerator synthesis, such as High-Level Synthesis, are not fully automated.

this paper investigates the use of this algorithmic skeleton methodology for FPGAs.


Note that OCL formally considers the right-hand-side of an equation as the argumentof the = -operation called on the left-hand-side.

the model element songs would be classified variable if both sides of the equation were swapped.


At the same time, we aim for not leaving the burden of generating frame conditions entirely on the designer.

a systematic methodology for the generation of frame conditions is proposed which assists the designer in a comprehensible fashion and with automatic methods in this process.


In summary, an SCC being combinational is equivalent to every loop in the SCC being dominated by one controlling side-input.

if there exists one loop whose sideinputs are all non-controlling values for an input assignment, the SCC is non-combinational.


Furthermore, if OSIs are within the fanout cones of other SCCs, they also possibly have indefinite values.

only OSIs that do not have loops in their fanin cones are considered for self-conflict detection.


Once all SCCs in a circuit pass the validation procedure, the combinationality of the circuit is guaranteed.

in the following discussion, for simplicity, we only focus on the SCC which represents a cyclic sub-circuit of the original circuit.


Mobile applications often heavily use shared libraries and system codes, leading to a large instruction working set and high instruction L1 cache miss rate [7] [8] [3].

the L1 data miss rate keeps relatively low because the data access patterns in mobile applications exhibit good locality in the L1 cache [7] [8].


Moreover, the access latency to the CIHT table is also negligible comparing with the long latency on an L2 miss.

our power model is built on top of McPat [10] and the STT-RAM is modeled by the NVSim [5].


Mobile devices are generally powered by a finite-capacity energy source - a battery, whose size and capacity are quite limited due to the restricted physical size of the mobile devices.

energy consumption is undoubtedly the most important factor in modern mobile system design, and the energy-efficient computing (i.e., achieving substantial energy savings without degrading the performance) becomes one of the key challenges faced by the computer architects and system designers.


However, the write operation of the STTRAM, takes longer time and consumes more energy.

all these motivate us to separate the user and kernel blocks in the L2 cache to preserve the useful blocks.


there is almost no performance overhead in our technique.


Aggressive technology scaling has allowed the continuous increase of processor performance while maintaining the same power consumption across generations.

the worsening of variations and the enormous design margins enforced by conventional techniques for avoiding timing failures limit the performance returns from technology scaling and lead to power overheads especially in sub-40 nm nodes.


Particularly one type of highly pessimistic margin has already burdened the traditional design flow even long before the recent rise of variability issues: the traditional synchronous design paradigm determines the operating frequency according to the worst critical path that is identified through static timing analysis under assumed worst case conditions.

this critical path is not always excited, thus leading to processors that perform (much) slower than what they can theoretically achieve.


In conventional many-core processors that dont have dark silicon constraints, there exists only one TDP mode, i.e., powering-on all cores at nominal voltage/frequency to maximizing performance within a TDP constraint.

dark silicon many-core processors exhibit a multitude of TDP modes, each resulting in a starkly distinct thermal and leakage power profile.


[1,H]) denote the coordinates of the core i.


In the nanometer era, the exponential dependence of leakage power consumption on threshold voltage has constrained further threshold-and supply-voltage scaling.

the power density is increasing with technology scaling at a rate that it cannot be sustained.


Note that if we consider only two reconfiguration points (e.g., 64/2 and 32/4), the memory overheads are 6.9%.

for a fair comparison, the overheads of DARCA must be compared against prior redundancy-based FT schemes.


This is because at the specific pfail , DARCA is configured to operate as 16/8 cache (inflection point between 32/4 and 16/8 configurations).

the 16/8 configuration depicts a strong prefetch-friendlybehavior.


Thereby, the storage requirements between DARCA and a typical 32-entries DBR scheme are comparable.

dARCA follows a different approach. The extra storage area is devoted to hold information to controlhow the cache data array disambiguates the cached elements(control-based redundancy).


Moreover, when prefetching in employed (bottom graph of Fig. 5), DARCA manages to further increase its distance from prior FT schemes.

when the block disabling technique is employed, the baseline cache will be able to keep data in cachelines even if they have some faulty subblocks i.e., four faultyÂbits are attached in each 64-bytes physical cache frame or onefaulty-bit every 16-bytes [1].


This is important since ourtarget is to increase the reliability of the latency-sensitive L1s.In order to calculate access time, we modified CACTI source code to integrate the DARCA extra components into the design.

the extra components are i) the variabletag selection logic (below tag arrays), ii) the index bit selectionlogic (before cache decoder), and iii) the extra level ofmultiplexer (below data arrays).


The thermal stability coefficient (ǻ) is dependent on the volume of the free layer and on the temperature of the device.

maintaining the same area (A), the thermal stability can be modified by modifying the thickness of the free layer.


The TMR ratio is therefore defined as: TMR= (RH RL)/RL.


It is integrated in our advanced SystemC-TLM2.0 virtual-platform setup [21].

it can also be integrated in other simulation environments like gem5.


The coverage of the test with data pattern 0xFF alone is relatively low compared to the WIDE I/O DRAM results (39-43% versus 83% for WIDE I/O).

we focus on dswG ... channel 3 only to show retention time depending bit .ips.


On the other hand, in SUOR ONoC, the worst-case SNR quickly decreases with an increasing MR passing loss.

the worst-case SNR is above 16dB when the passing loss is -0.001dB, but it is only above 2dB when the passing loss is -0.01dB.


Regarding coherent crosstalk, it is generated by the switching MRs of cluster 0 (the sending cluster).

it should be noted that there exists a case where one cluster finishes its communication on almost all clusters and injects those tokens into the waveguide.


We can observe that the impact of variations on the mean and variance of the delay for different configurations is shown in Figure 6 and Figure 7.

the mean delays of the three configurations are similar, while the spreads around the mean differ substantially.


In absence of the final clause, T4 would not necessarily execute immediately, and so the timing behaviour of T1 would change as well.

task T0 waits on the taskwait at line 16 until tasks T1 (not its descendant task T4) and T2 have completed before proceeding past the taskwait.


V denotes a sequential operation or job, characterised by a worst-case execution time (WCET) estimation.

the WCET estimation of T0 depends on the timing behaviour of T1,T2,T3 and T4.


This confidence level expresses how sure the players are about the real value of the varying parameter.

the player's confidence determines the magnitude of the variation.


Solving such large systems at frame rates of up to 30 fps is computationally very demanding and often a pixel dense solution is not required.

the problems are usually solved on around 10× sub-sampled grids in order to reduce the computational complexity.


Moreover, due to Moore’s law, ICs will be more and more densely integrated, and so this method will become more and more difficult in the next future.

there is a need for medium cost HT optical detection methods.


Standard destructive reverse-engineering techniques (usage of Chemical Metal Polishing followed by Scanning Electron Microscope image reconstruction and analysis) can be used to detect HTs if we can compare ICs with a golden circuit.

this task is very expensive since it takes a lot of time to realize properly: if the obtained images are blurry for any reason (like bad mechanical or chemical preparation), the reverse-engineering is hard.


If the HT is close to a net Na (or directly connected to a net Na), dHTa is defined as the random delay added by the HT to the net Na in an infected IC.

impact of two HTs on delays, for (P, K)no13 (up) and no47 (down) AES bits, estimated by the number decrements by clock steps One can highlight on the importance to study not only the needed to fault each considered bit.


Using this model, the probability of detecting a HT can be calculated.

we can estimate the false positive and false negative probability of HT detection as a function of HT size for a set of ICs.


The manufacturing flow is not impacted by this detection method.

each client could decide to use or not this detection method depending on his security needs.


As a result any promising solutions that require high ratio of 1-to-M and/or large multicast destination groups, are avoided [5], [6].

there is a need to eliminate these constraints and improve performance by proposing a 1-to-M interconnect architecture.


This paper proposes a novel hybrid architecture, which improves the on-chip communication bandwidth significantly using mixed wires and surface wave interconnects (SWI) fabrics.

the bandwidth of multicasting can be drastically improved.


This is especially true for chip multiprocessors (CMPs) that were introduced to provide nearlinear performance improvements when complexity increased (Pollack s rule), while maintaining lower power and frequency budget [4].

the evaluation results show significant improvements in terms of average delay and power consumption with a relatively small die area penalty compared to other architectures.


In addition, this type of interconnect has the cheapest implementation cost compared to other fabrics.

the best solution would be to combine both interconnects, metal and SW, in one hybrid wire-SW interconnects in a multi-layered network architecture; in short W-SWI, as shown in Fig. 3.


Low-cost and efficient routing solutions based on Dimension-Ordered Routing, like FDOR [9], or on turn models [10], [11] have been proposed to provide coverage on irregular topologies.

they either provide low coverage (single link faults) [9], [10] or disable a large number of faultfree nodes to extend the coverage [10], [11].


The technical scaling in the nano-era has enabled smaller, faster, and low-power transistors that provide high performance-per-power efficiency.

ultra-small dimensions and low operating-/threshold voltages have led to various reliability threats like soft errors and aging [1, 2].


So the speedup of ACSEM on quadsub is quite low, since the step value is very close to or even larger than the average length of paths in the circuit graph.

the BDFS algorithm with the step mechanism will be degraded to a full BDFS algorithm.


Ignorance of the circuit s error masking property may lead to over-design of a reliable processor or application-specific hardware accelerator circuit that may incur signi.cant power and area overhead2 .

a fast analysis of the error masking characteristics is required to evaluate and enhance the quality of a reliable processor design in a cost-effective way, while curtailing the analysis and design time to ensure fast time to market.


Thus, unlike earlier comparisons made in tables II, III and IV, we cannot give a performance guarantee for I-ordering + DP-fill over techniques proposed in [20], [21] or [22].

it is interesting to note from Table V that the proposed I-ordering + DP-fill technique actually outperforms all the these techniques for most of the benchmarks and the percentage improvement increases with increase in circuit size.


The new model retain more information of the circuit, yet it can still be efficiently handled by existing graph partitioning methods.

it is expected to provide a better partitioning compared to traditional S-graphs.


The TSV which is located at the corner is connected a 3-to-1 MUX whose inputs are its own signal, signal from the same ring and signal from the outer ring.

the TSV which is not located at the corner is connected to a 4-to-1 MUX whose inputs are its own signal, the signal from the same ring, the signal from inner ring and the signal from outer ring.


In Figure 4, ãrst, the signals of TSVs in the ãrst ring can be shifted to their neighboring TSVs in any direction.

these signals can be shifted to neighboring TSVs in the ãrst ring clockwise and counterclockwise, and to neighboring TSVs in the second ring.


As W or S shrinks, the read latency becomes larger due to larger wire resistance (inset).

we investigate the effect of synaptic device’s on-state resistance (RON) that stands for the maximum D value.


Each individual liquid crystal can be tuned by changing the electric potential applied to it in order to let more or less light pass.

a key feature of an LCD display design is the presence of a source of light to illuminate the array of liquid crystal cells from behind.


When analyzing this pirate video sequence, each screen is successively tested as a potential pirate device.

screen 1 and Screen 3 are expected to have an aliased temporal frequency ft close to 10 Hz with the Panasonic camcorder.


However, these benefits are obtained at the cost of significantly higher arithmetic effort: Due to the comparative complex underlying mathematical method, a large set of additions and multiplications is required1 .

the algorithmic performance evaluation highlights our work as very efficient in terms of arithmetic calculation effort (see Tab. 1).


Unless a thermal violation is predicted, the decisions of the default drivers such as the core and GPU frequencies, choice of big or little cluster and number of active cores, are affirmed.

the proposed DTPM approach is non-intrusive when the temperature is within permissible levels.


We emphasize that using a fan is not feasible when this chip is used in a smartphone or tablet, which is the case for Samsung Galaxy S4.

in general, this analysis is repeated for each computing resource such as the little cores and GPU to extract the corresponding leakage power model.


Constraining the maximum frequency to limit the temperature, while passively waiting for thermal violations and reacting by throttling the cores, impairs performance as well as reliability by causing large temperature variations [7].

predictive approaches can take advantage of rich set of dynamic configuration capabilities to manage temperature effectively [8].


Thermal modeling and dynamic thermal management have received significant attention due to increased power densities and reliability implications of temperature.

poor performance of reactive approaches led researchers to develop compact thermal models [7, 9] and thermal prediction techniques [8, 10, 11] which can be used in pro-active thermal management methods.


Thorough experimental evaluation shows that the proposed approach not only eliminates the need for a fan, which is not a viable choice for mobile devices, but also provides significant power, thermal, and reliability advantages.

it regulates the temperature more effectively than the default configuration which uses a fan, and on average offers 10% platform power savings with 3.3% loss in performance.


We ran each benchmark and predicted the temperature T [k+10] at every control interval T [k].

the temperature one second (10 control intervals) ahead of time is predicted using a sliding window, and the predictions are compared to the measured values at the end of each experiment.


Furthermore, traditional NoC router uses virtual channel allocator, switch allocator, arbiter and a crossbar to calculate and allocate flits to the relevant output.

in our design, we just use direction channel allocator and three separated arbiter to realize same function.


Both of them always grant real-time packets higher priority over best-effort packets and employ round-robin arbitration between packets of the same traffic priority class.

rigid round-robin is modified by giving the most recently served port the lowest priority, which increases the fairness of the arbitration as illustrated in Fig. 4.


To achieve such a writing scheme, a multi-step writing should be applied in GSHE logic device writing.

since writing of these device depends on the direction of charging current, once a device has been written, it cannot perform the same function again.


As load resistance of writing devices is reduced by parallel structure, the current is mainly determined by MTJ resistance.

such a structure will distribute charging current through each strip, the current will largely reduced depends on how many output elements there is.


However, with a fixed RM stripe length, overlapping more cells reduces the space for each cell to allocate their access ports.

without expanding the overlapped cell area, fewer ports per racetrack stripe leads to longer shift distance.


Meanwhile, the generation of magnetic field will cause additional energy consumption.

the area changes from 2.66mmto 5.03mm, by changing the optimization target from area to shift latency.


We consider the four learning procedures listed in Table I.

the BMF learning procedure is compared to the conventional learning procedure that uses as training set (a) only the late-stage real inliers, (b) a raw combination of early-stage simulation data and late-stage real inliers, and (c) only the early-stage simulation data.


The non-intrusive sensors consist of dummy analog stages and single components extracted directly from the topology of the LNA.

we consider a dummy bias stage identical to the bias stage of the LNA formed by transistor M3 and resistor R1, a dummy gain stage identical to the gain stage of the LNA formed by transistors M1 and M2, a dummy diode-connected transistor identical to the transistor M1, and a dummy capacitor identical to the capacitor Cin.


The acceleration of applications, running on a general purpose processor (GPP), by mapping parts of their execution to reconfigurable hardware is an approach which does not involve program's source code and still ensures program portability over different target reconfigurable fabrics.

the problem is very challenging, as suitable sequences of GPP instructions need to be translated/mapped to hardware, possibly at runtime.


Finally, the communication is send over a PCIe link using a kernel mode driver.

all communication between the host and the kernels goes through this layers and can cause a significant overhead.


Modern heterogeneous devices contain tightly coupled CPU and FPGA logic, allowing low latency access to accelerators.

designers of the system need to treat accelerated functions specially, with device specific code for instantiating, configuring, and executing accelerators.


DMSD needs, however, periodic measurements of end-to-end packet delays rather than of injection rate.

the receiving nodes, and not the transmitting ones, measure the delay.


A very relevant application in this domain pertains to the development of the gene therapy for HIV-1 [11], which has to tackle the dynamic variation in parameters of the biological interactions when searching for the best configuration and amount of engineered cells.

we explore the computation kernel that studies the interactions between cells and virions and enables the design of a gene therapy for HIV-1 infection, and consider it as a use-case to design and evaluate the potentials of a NoC-based multicore platform.


In the actual system, each region has a fluid boundary.

in our abstraction, we model these regions as cubes in three-dimensional space.


In this paper, we present a novel performance simulation tool with the added flexibility adequate for use in architectural optimization as the parameters of the component devices change.

this simulator is designed to handle reconfigurable quantum hardware, where device parameter (DP) values can be adjusted  handle reconfigurable quantum architecture, where resource investment scenarios can be studied  output concrete breakdown of performance metrics (e.g. total execution time and failure probability) and contents of resource overhead (such as qubits used as ancilla or for communication purposes).


The fidelity degradation of a BSC as a function of distance tends to limit its utility to short distance communication only.

eL can be realized with distance-independent fidelity, which makes it a suitable candidate for long distance communication.


However, VOSPA always outperforms OPT as long as N is larger than 2.

vOSPA achieves a reactant reduction by 22% and 37% as compared to OPT if a Mixer-4 and Mixer-8 is utilized, respectively.


For DMFBs under the (1:1) mixing model, one of the two input solutions must be a 1/2 1/2 buffer solution.

the resultant CV is always half of the 1/2 original CV after an exponential dilution operation.


A dozen of approaches have been proposed to address this problem in past few years.

to the best of our knowledge, there is still no algorithm aiming at the problem on FMFBs equipped with multi-segment mixers.


It relies on optical waveguides to carry optical signals, so as to replace electrical interconnect, and provide the low latency and high bandwidth characteristic of optical interconnect.

the temperature gradient among ONIs influences the SNR, as detailed in the following.


Then, MR heater power is explored through thermal simulations in order to reduce the gradient temperature.

the active layers are surrounded by Si/SiO2 line constituting the mirror structure, which allows coupling the light into the horizontal waveguide (optical signal shown in blue arrow) using a tapper with an estimated 70% efficiency.


For the sake of simplicity, we assume unrestricted and immediate access to all potentially shared resources such as a bus and only concentrate on the execution cycles of the target application in isolation.

our framework still improves over the naive approach.


In the available system, cores 0-7 belong to processor with ID 1, whereas cores 8-15 belong to the processor with ID 2.

thereafter, a model is estimated from the given calibration trace and the observed temperature trace (line 21), see [12].


A model is separately computed for each discrete frequency f ∈ F since the thermal properties of the system may change considerably with frequency.

it may not be possible to simply scale a given model derived at one frequency and use it at a different frequency.


One common approach is to use heat maps captured from the silicon layer of the given processor as it executes instructions, and use heuristic algorithms to back-estimate the detailed power model to be used with the Hotspot simulator, see [8].

several critical details (e.g., processor floorplan, on-chip power and/or temperature management algorithms) must still be guessed.


This process is not always conscious, therefore making it difficult to understand the process.

once they were selected, starting ideas are characaterized as either similar to previous designs (analogies [11]), combinations of existing design features [12], generalizations, e.g., through induction [7], and sudden insight (like through restructuring the knowledge representation).


The first two steps of the reasoning-based synthesis flow are the same as for the flow in Figure 3(a).

c. Causal parts present how the features of two or more concepts are combined to form a new concept that offers improved performance and/or leads to a less constrained solution.


As expected, the small delay fault coverage is generally lower than the transition fault coverage.

there are also numerable cases of small delay faults, which are detected despite their corresponding transition faults being not detected.


The host system contains 16 IntelR XeonR processors clocked at 3.4GHz and 256GB of RAM.

the peak memory consumption on the host system never exceeded 10GB.


This section describes the proposed algorithm for functional ATPG.

this means that in practice the generated test programs require a manual step to check their compliance with the SBST constraints, triggering a complex and exÂpensive transformation in the likely case that they don t match them.


The measurements collected from attached external thermistors were used as the expected value for the skin temperature and screen temperature.

we have used the CPU temperature, utilization, and frequency, as well as battery temperature collected in our log file.


If the yield value is less than the minimum required yield, the solution is eliminated and the second phase of yield analysis is not performed.

the synthesis time is reduced since many redundant simulations are not run.


For instance, slightly losing from one electrical constraint may cause much better performances for the other constraints, as a result enhances the overall circuit performance.

the design coefficients are added to the developed tool in attempt to arrange tradeoffs between each design constraints.


We logicaly divide our multi-core chip into memory islands based on the number of memory controllers.

at each node we can have maximum of 2 different routers that are optimized for 2 VF pairs (e.g, node i and node i +1 in Figure 2).


For what concerns dynamic metrics estimation, in a traditional testbench based on transient simulation, the converter samples a sinusoid according to Shannon's law.

the mismatch and the parasitics of each capacitance affect the conversion accuracy.


Ldigital should contain all the functional blocks, that form the power-down part.

structures like e.g., inverters, nand and nor gates, level shifters and pass-gates need to be detected.


The aging effects can be investigated using aging simulators [10].

approaches based on numerical simulations are computationally expensive and, therefore, infeasible for large designs.


The breakpoint-based silicon debug approach allows users to stop the normal (system) operations of the circuits under debug (CUDs), extract the internal states of the CUDs for examination, and then resume the normal operations for further debugging.

then when the CUD_MA is granted to use the bus, it will inform the PAM_IP_BUS to unlock the system and to accept data from the CUD.


If the CUD is interrupted during a transaction in which it serves as a transmitter, the receiver will never get the correct data in a valid transaction because the transaction is not replicable.

such transactions should not be interrupted.


The weight of the remaining cells are calculated base on the modified error response.

in recent years, advancement of convolutional compactors [4], [5] which are based on a finiteinput-response principle, have added a new dimension to scan response compaction.


In the swap disabled scheme, applications may get terminated by the LMK when there is no sufficient memory.

switching between those applications could take longer time as they will have to be reloaded from flash storage.


Since NVRAM is byte-addressable, all the swapped out pages can be accessed directly through load and store instructions.

one does not have to swap in pages for read requests.


However, we found that page type is usually available to the OS, and it is easy for the OS to differentiate code and data pages.

we argue that a better solution is to swap out code pages to the swap area and execute the code in-place, without copying them back to main memory.


As indicated in Figure 1 in decode, read, and write-back stages all instructions share the same logic and therefore the specific pipeline stage delay is not instruction-specific.

in the execute stages each instruction has separate dedicated logic, each with its own delay.


Consequently, even though some instructions can operate at high frequencies, the slow instructions determine the processor clock period, resulting in the underutilisation of the processor potential.

the fast instructions latent performance may be harnessed through Adaptive Clock Management (ACM), i.e., by dynamically adapting the clock frequency such that each instruction gets sufficient time for correct completion.


Incorporating PCM into FPGA designs has been attempted previously in a rather simplistic fashion; by replacing SRAM cells with 1T2R PCM cells [3].

we explore the use of PCM to exist in multiple states and thus store multiple bits per cell.


However, the exponential rise in delay due to the parasitic capacitance becomes painfully evident as the size of the LUT increases.

lUT size of 12 is over five times slower than it s SRAM counterpart.


Whilst operating in the single-output mode, the LUT utilizes an additional input signal to select either the most significant bit or the least significant bit as the output (Out A).

the above described LUT can operate either as a K-input LUT with a single output, or a single LUT with K-1 inputs with two outputs.


This results in a small area overhead when compared to a traditional SRAM-based LUT.

since every LUT memory cell can share all the sense amplifiers, the area overhead is diminished.


However, since the resistance of each of these states is higher than that of the SET state, the read speed for the cases 01 and 10 is higher than that of 00 and 11.

on an average, the overall read speed has been sacrificed.


However, the larger the memory cell, the longer the interconnect.

if we reduce the area overhead of the configuration memory, we can reduce the delay through the crossbar as well as the overall size of the CLB which in turn would reduce global routing overheads.


For an accurate model, we scaled the resistance, capacitance and delay parameters specified from 40nm to 22nm.

resistance and capacitance values for routing channels and devices were scaled, as well as delays for flip-flops, routing buffers and wire line delays.


On the other hand, any solution for U(i, S) when the current state is indeed i-reachable is non-spurious.

when a solution is found the reachability checking procedure of [9] is used to determine if the current state is i-reachable or not.


It is expected that some of the unreachable states may be intended to remain invalid by the specification.

the design being debugged is expected to satisfy some invariant properties required by the specification.


This includes all solutions that make the target state reachable one cycle after a k-reachable state, and therefore the solution set of Algorithm 2 is a superset of the solution set of Algorithm 1.

the solution set of Algorithm 2 can include solutions that would be discarded in Algorithm 1.


While unreachable code may be a symptom of an unreachable state(s) and vice versa, in practice they often manifest themselves separately.

automated techniques to aid the engineer in fixing a design when a state is shown to be unreachable are of paramount importance to reduce the verification burden and improve the design cycle.


Whilst there has been a lot of interest in researching new architectures for GALS [1][2][3], there have been few attempts at providing synthesis solutions for GALS communication.

generation of GALS from specifications has been limited to hardware description languages such as Verilog, VHDL [4] or synchronous programming languages such as C or ES-TEREL [5].


To implement the model in circuit simulators, SPICE compatibility is essential.


Therefore, each individual bit-cell can have a smaller area with increased write failure; yet, extra bits for ECC are inserted to compensate for the increased failure rate.

unlike the previous case, the individual bit-cell is positioned at the write and read dominated region, therefore, decreasing the barrier height would decrease the failure rate.


Note that for a fixed effective bit-cell area, the failure rate increases with the barrier height because JC is increased.

increasing the effective bit-cell area increases JWR and reduces the write failure rate.


As seen in Fig. 1 (a,b), the STT-MRAM bitcell consists of an MTJ and a MOSFET.

the techniques published in literature are either focused on the optimization and failure mitigation at the bit-cell level [8,9,10], or on memory architecture design techniques to improve STT-MRAM yield [11,12].


On the other hand, read-disturb failures occur because IRD is such that JC is exceeded during read operations and the stored data is accidentally overwritten.

increasing the access transistor width to mitigate write failures also increases the read-disturb failures.


Write failures occur because JWR falls below JC.

read-disturb failures occur because IRD is such that JC is exceeded during read operations and the stored data is accidentally overwritten.


This is simply because of the power-line switching overhead which becomes more notable when the system has to be turned off and on frequently.

efficient power-gating can be applied to a unit which has the following characteristics: first, it should have a low utilization in order to have a good potential of being turned off, and second, its idleness must not be fragmented so that the power-line switching overhead remains negligible [11].


Existing research efforts in formal verification of asynchronous circuits have been divided into three broad camps: hazard-freedom or conformance checking, equivalence checking, and property verification.

many techniques try to verify hazard-freedom/conformance of a gate-level implementation of a leaf-level CSP cell, a unique requirement to asynchronous design [10], [11].


The SEND and RECEIVE are asynchronous modules modeled by the 3VL operators R and S defined in Figure 1.

in each iteration, based on the value received on E, the RECEIVE primitive may or may not receive from L, but it always sends a value on R.


These leaf cells can then be implemented with a variety of asynchronous pipeline templates.

by adding constraints to the source Verilog to tell the verification tool to not consider these unreachable states, a common practice in synchronous LEC flows [21], the tool proved equivalence in 31 seconds.


We propose a method for logical equivalence check (LEC) of asynchronous circuits using commercial synchronous tools.

we verify the equivalence of asynchronous circuits which are modeled at the CSP-level in SystemVerilog as well as circuits modeled at the micro-architectural level using conditional communication library primitives.


Since each iteration can be treated as encoding an edge of the tree to a number, the resultant PrÃ¼fer code preserves the connection properties of the original tree.

in addition to the labels on a labeled tree, a circuit graph contains supplementary circuit information.


Assist Feature Insertion Sub-resolution assist features (SRAFs) are commonly employed in industry, not only to reduce EPE, but also to improve process window.

assist features are essential for isolated features


After stage 1 and 2, either all the EPE violations are fixed, or EPE cannot be further improved.

instead of simulating with dose variation, we can approximate the image by using Ith = 0.216 on the intensity values simulated at nominal condition, which saves us one simulation in each iteration.


As discussed in the example this DQBF has no equivalent QBF prefix.

there is no need for explicit elimination of the internal auxiliary variables resulting from the Tsetin encoding.


Since the scales of circuit design and macro blocks are now very large, mapping macro blocks is difficult and has become an infeasible tasks for engineers to perform manually.

it is valuable to develop a robust methodology that can utilize macro blocks automatically and efficiently.


Transistor folding is a task [2] normally done first, sometimes also taking transistor placement into account.

they are still viable for a placement instance of a few dozen of transistors.


This problem gets even harder when sporadic tasks are involved.

to demonstrate scheduling for FPPNs, we consider a practically relevant subclass of FPPNs where the use of sporadic tasks is restricted.


This suggestion is exploited in our model, Fixed Priority Process Network (FPPN).

what if the job arrives exactly on the boundary?


InputA has priority over FilterA and NormA, and hence it is joined to both of them.

in the latter case the edge is redundant due to a path from InputA to NormA.


All stages of the receiver are fully differential.

this integrated solution does not contain any stage driven by singleended signals as opposed to discrete component solutions, that need to minimize the transistor count and only have access to off-the-shelf components, which are often not available with differential inputs and outputs.


The logical simulation time of the kernel is referred to as global simulation time.

the components can keep track of their time using a local simulation time, which is usually defined as an offset to the global simulation time.


It is essential for companies to invest in making software models for meeting their time to market.

the fastest model is not a good model if it does not accurately match or predict the final design reality.


The internal memory states '0 'and '1' of a CRS cell are indistinguishable at low voltages because state ‘0’ as well as state ‘1’ show a high resistance.

no parasitic current sneak paths can arise.


These sensors are chosen for data fusion as they have been widely used in previous activity recognition attempts.

we are interested in using different classification algorithms to perform a detailed analysis of the raw data collected from eight physical activities including idle, sitting, standing, walking, running, cycling, walking upstairs and downstairs.


In this study, spectral peak tracks (SPTs) are explored to represent the trace of the advertisement call.

the time and frequency boundaries of each acoustic event are first defined by the AED method; spectral peaks are then extracted from the area of detected acoustic events.


We assume a hardware cache whose block size, associativity, and number of sets are B bytes, W , and S, respectively.

the number of bits to address a set in the cache is log S.


It also uses a new congestion detection metrics for updating local congestion information and is used to set the learning rate to keep the values as updated as possible.

when the switch is not congested the learning rate is set to a minimum value.


Moreover, the servers need to be kept in an air-conditioned environment, which are known to consume more power.

we need a system to smartly monitor and manage the power consumed and minimize the loss and wastage [8].


This ever-growing environmental problem engages health risks and major complaints of annoyance on behalf of millions of citizens.

sustainable urban planning needs to seriously take into consideration the task of mitigating environmental noise.


We have adopted a time window of 15 seconds (i.e. 40 sequential segments for each recording) where the signal exhibits homogeneous behavior with respect to audio type (context and soundscape quality).

within these time windows, both context and the soundscape quality is supposed to be stable homogeneous.


For the particular case of the soundscape quality estimation task, we have adopted an alternative approach (called indirect soundscape quality -ISQ): instead of direclty mapping points of the feature space to scalar estimates (typical regression), we have also implemented a meta-regression scheme.

we use the estimated levels for the three context classes as feature values in a meta-regression approach (see Figure 8).


In order to measure the overall latency of a system with a player with a physical disability, a system was implemented using the Xbox 360 Kinect and a Windows computer running the Kinect SDK version 1.8.

these are outliers, and the average of the absolute value of the deviation between drum and guitar was under 150ms, with times as low as 30ms.


The idea of projection-based denoising is not new and it has been effectively applied in image denoising, see e.g., [7] and [3].

to the best of our knowledge it has not been utilized in denoising PSG data streams which are extremely heterogeneous.


Through our work, we show that UrJar has the potential to channel e-waste towards the alleviation of energy poverty, thus simultaneously providing a sustainable solution for both problems.

we present one such attempt, a backup power device - called UrJar - that seeks to simultaneously address the problems of proliferation of laptop battery e-waste, and the prevalence of energy poverty in developing countries.


In this paper we claim that understanding QoE in mobile devices is paramount for cellular network operators, and present the results obtained from subjective lab tests performed for popular end-user services accessed through smartphones.

we consider the following five well-known applications in mobile devices: YouTube dynamic and non-dynamic video streaming, Facebook, Google Maps (Gmaps from now on), Web browsing through Google Chrome, and WhatsApp.


FaFNoC achieves slightly better results than FON or FTDR-H for throughput and average hopcount, whereas FTDR achieves significantly better results for those values.

the existing architectures FON and FTDR-H lose a huge amount of injected flits.


The inherent redundancy of NoCs can be used to tolerate such failures.

at FTDR and FaFNoC almost all injected flits arrive at their destinations.


This makes de.ection routing attractive for small, energy e.cient and fault tolerant NoCs.

only few fault-tolerant de.ection-routing based router architectures exist.


Because the mesh, Cmesh, and butter.y NoCs provide diverse paths between L1s and individual L2s, they lead to higher utilization of the CU.

the Crossbar, Clos and C-Crossbar, which at some point combine the tra.c to/from the L2s, achieve lower performance.


the zero-load broadcast latency of BoWNoC is scalable as it remains constant when varying the number of cores.

the MAC protocol must also be scalable (which is a challenge in itself ) in order to retain such latency advantage.


In a WNoC, a transmitting antenna radiates RF signals at a given frequency, which propagate throughout the chip and may be received by any other atenna tuned to the same frequency.

all antennas tuned at the same frequency channel share the medium similarly to in a bus.


Being located in the far field of the antenna, the core environment does not necessary have an impact on the gain and matching of the antenna.

the environment can have an effect on the link between the transmitting and receiving antennas by causing increased path and polarization losses, and limiting the data rates.


Different kinds of attacks like node replacement, node movement or man-in-the-middle were considered for investigation.

he suggested that RSSI can be used in devices which focus on energy consumption [2].


In execution activity are instrumented the desired adaptation acts by actuators or effectors.

the highly changeable environment of WSN has Pi-ADL as a suitable candidate for representing the RA.


To evaluate the RA, ProSA-RA suggests using a checklist-based inspection approach named FERA (Framework for Evaluation of Reference Architectures) [30].

we followed the recommendation and used FERA to conduct an evaluation in order to verify: (i) completeness of general information related to the construction and content of the architectural views; (ii) adequacy for releasing of the architectural description of our RA; and (iii) viability and change possibilities of our RA.


In [9], we found different approaches to provide autonomic behavior to WSNs, but they are just in preliminary stages and have still several open issues.

we noticed a lack of well-defined reference architecture designs to support the autonomy of WSN.


Empirically, we find that the 10th percentile of ranges estimates gives the least average error.

the 10th percentile aggregate of the 27 range estimates is used as the true range at each anchor.


Moreover they all produce an error of, at most, one bit.

when one of the above events occurs, a bit error may or may not be produced.


The need for providing communication strategies in these challenging environments where electromagnetic waves cannot be used, has brought attention of researchers towards molecular communications.

the possibility of moving very small amounts of matter inside microfluidic systems can be exploited to exchange information between micro-and nano-scale devices.


Inside this droplet, the luminescent process takes place or not, according to the presence or absence of signal- Figure 3: Graphic representation of the adopted encoding approach ing molecules.

downstream the signaling molecule detector, a sequence of luminescent and non luminescent droplets is produced, where the luminescent droplet represents the bit 1 and the non-luminescent droplet represents the bit 0 .


For instance, enabling multiple (more than two) Graphical Processing Units (GPUs) in a single system is nowadays problematic as the interface between them becomes a bottleneck.

providing efcient communications between various intra-computer components, such as Central Processing Units (CPUs) and GPUs, is a hot research topic nowadays.


Following the Beer-Lambert law the absorption component of the path loss is modeled as exponential function e-K(f)d, where K(f) is absorption coefficient, d is the separation distance.

well-polished metal surfaces or metal coating mirrors could act as THz reflectors [9, 10].


As one could observe, the water has exceptionally strong absorption in the THz band.

ammonia is characterized by rare absorption lines at isolated frequencies.


The use of technical refinement is playing an important role in the process of optimizing training efficiency and improving results of athletes.

we aim to develop an online monitoring and feedback tool to follow the swimming training using a single waterproofed and wireless motion sensor attached on the swimmers center of body (back).


According to the random channel selection scheme, the channels are arranged in a random sensing order and the SUs transmit in the first vacant channel they sense.

[7] proposes an intuitive channel sensing order arranging the selection of the channels in a descending order of their a priori known availability probabilities (ascending order of their occupancy probabilities).


A set of experimental measurements is presented aiming to demonstrate the experimental framework and verify the LTE/LTE-A standards.

three experiments are demonstrated according to the Reference Measurement Channels (RMCs) defined by 3GPP [5], [6].


In this paper, an experimental framework for studying and measuring LTE and LTE-A is presented, consisting of high-end laboratory equipment and software tools.

an arbitrary signal generator is exploited i.e., the Le Croy 1102D together with the ArbStudio software, providing two channels necessary for MIMO.


The C-to-ADA translator is based on the front end of a C compiler.

it performs all early stages of a compiler, including lexical, syntactical and semantical analyses.


The C programs for this benchmark are listed in Table 1.

heuristics are applied on the HLS transformations


In Proceedings of the 9th international conference on Ubiquitous computing (UbiComp '07) (pp.

note that for the same container, the impulse response differs for the different content levels.


Surprisingly, we have also noticed subtitle files with differing pace.

even when they are properly aligned at the first caption entry, they eventually get out of sync with each other.


For secondary analysis, however, the procedure is generally fixed for all samples that come off the sequencers.

further downstream analysis involves computational algorithms that directly answer the scientific questions at hand and are varied in their computational requirements.


The proposed hardwaresoftware technique leads to a mean improvement of 18% in application performance and a mean reduction of 26% in misses over a shared LLC managed by the Least Recently Used replacement policy for a set of input-annotated taskparallel programs using the OmpSs programming model implemented on the NANOS++ runtime.

the state-of-the-art thread-based partitioning scheme suffers an average performance loss of 2% and an average increase of 15% in misses over the baseline.


The insight behind FECC follows recent works which observe that compression at the cache-block granularity can free up enough space for other information [17, 18]; we use this free space for storing the ECC codes.

when compression succeeds, FECC can match the performance of a conventional ECC organization that uses dedicated ECC memory devices with less, or even zero, dedicated redundancy.


Similar to the use of difference coding for integer values, we can compress the sign and exponent with simple subtraction assuming that their values exhibit locality.

other approaches exist, similar to VECC, that embed ECC data elsewhere in the memory space to allow a more flexible use of non-ECC memory modules [6, 8].


Clearly, the uneven distribution of SBEs among GPUs make this analysis challenging.

they are an indicator of error resilience of the hardware and have implications toward the ECC page retirement error as described earlier.


Traditionally, graphics processing applications, such as video games and image processing applications, have utilized GPUs for faster processing and rendering.

with the increased thrust towards general-purpose computing on graphics processing units (GPGPU), GPUs have started to influence high performance computing (HPC) systems as well.


In this section, we want to understand the relationship between single bit error (SBE) and GPU resource utilization.

we investigate the correlation between GPU core hours, number of nodes and memory consumption with SBEs.


In addition to reporting the single bit errors, nvidia-smi output also includes double bit and ECC page retirement related errors.

we use both these methods of data collection to quantify and analyze the characteristics of GPU errors.


Our double bit error analysis so far is based on the console logs.

titan, the world’s second fastest supercomputer, consists of 18,688 NVIDIA Tesla K20X GPUs that computational scientists use routinely to perform scientific simulations and data analysis.


A huge number of VR researchers, programmers, and engineers have been trying to tackle this issue from many aspects.

reproducing the human visual sense in a remote place has been gathering attention recently, backed by many releases of sophisticated devices, omnidirectional cameras, and head mount displays (HMDs).


At the middle of the long stationary period around 280-440 seconds, there was another train having a brief stop at the opposite side of the platform.

stop probability for the stationary train temporarily dropped due to the magnetic noise, caused by acceleration/deceleration of the neighboring train.


All data was recorded using the same smartphone, but in independent sensing runs over the course of one year with long pauses between them.

data was subject to possible systematic errors due to varying temperature, slightly different experimental setup and even changed methods of data collection: The first few datasets were recorded with an older version of the sensing app, which heavily used automatic white balance and exposure compensation.


In this section, we survey these systems, noting the effect that these choices have on overall size and power draw.

we survey three commercial meters Kill-A-Watt [6], Watts Up [17], and Belkin Conserve Insight [3] and three research meters ACme [26] (two different versions), Monjolo [23], and Gemini [20] alongside PowerBlade (this work).


Hall effect sensors work by measuring the deflection of electrons in a conductor exposed to a magnetic field (like the one generated by a current).

powerBlade optimizes for size by using a power supply design that does not require an IC [21].


In this section, we discuss some limitations of the current design, explore some possible workarounds, and propose some future directions for improvement.

the accuracy could be further improved, the wireless system could be better utilized, and interval data could be collected with periodic timestamps.


Even though smartphones are typically sensitive to ultrasonic sound, their speakers are highly directional in those frequencies, which lead [20] to use audible frequencies.

in situations where the user blocks one or more transmitters while walking, or when a NLOS signal is detected, the system cannot update the location estimate.


In concordance to the 60 frame long transient phase, the CCC has a maximum at also approximately 60 frames.

the descriptor is from now on referred to as PHOG-TOP.


One important adaptation is using Lin s concordance correlation coefficient (CCC) [17] rather than Pearson s correlation coefficient to measure performance.

3.1 Audio Features The extraction of linear predictive coding coefficients (LPC) is an auto regressive approach, where the n th sample of a time series is approximated using a function of the p preceding samples [1]: LPC are still widely applied in speech processing, for example in speech recognition and speech synthesis.


Several mixnet and onion routing systems have sought to make traffic analysis more difficult using cover traffic, i.e., fake traffic on each communication link [4, 20], or delaying messages [24].

it has been shown that all these schemes still reveal information after multiple rounds of observation [26].


To address this attack, Vuvuzela uses a mixnet approach.

all requests are recursively encrypted under the public key of each server in Vuvuzela’s chain.


Although cover traffic hides the exact number of dead drops accessed once or twice, an adversary can still tell roughly how many people are talking, by looking at the number of dead drops accessed twice and subtracting the average amount of noise.

in the above configuration, clients use an average of 12 KB/sec (adding up to 30 GB over a month of continuous use, which may be high for a mobile phone with metered data service).


Vuvuzela aims to provide point-to-point messaging between users in a way that is private in the face of a strong adversary, who can observe and tamper with the entire network and all but one of Vuvuzela's servers.

an adversary should not be able to distinguish between a scenario where two particular users are communicating, and a scenario where they are not, even after interfering with the system.


The multiplicative ε provides plausible deniability: any event observed if, say, two specific users are talking has within eε times the probability if they were doing something else (e.g., within 1.1× for ε = 0.1 and within 2× for ε = ln 2), so users always have a plausible "cover story".

δ covers events that might have zero probability under some actions but happen under others.


For instance, scaling up to 2 million users increases the latency from 37 to 55 seconds.

in our analysis we assumed 10minute dialing rounds, which means a client must wait on the order of 10 minutes to start a conversation.


If the adversary controls the third server, he can now figure out whether Alice and Bob are talking!

if Alice and Bob are communicating, the third server will see two exchanges for the same dead drop; otherwise, it will not.


finally, to not let noise affect the clarity of the graphs, we configure servers to always add exactly µ noise, rather than sampling the Laplace distribution; this produces the same average results with less variance.


Ekho: Realistic and repeatable experimentation for tiny energy-harvesting sensors.

in this paper we describe Enspect, an open-source hardware/software tool which simpli.es the design of energy harvesting sensing systems by assisting in the specification of harvesting and storage devices.


For AF without SD link For AF without SD link when optimum power consumption is averaged over fading channel coofficients, the minimum average power consumtion takes places when relay node lies midway between source and destination terminal as plotted in Fig. 2.

with x axis denoting position of relay terminal and taking   power plots are shown for all the four cases.


In a practical scenario, signal transmission through the wireless channel suffers from fading, which results in unreliable reception of the signal at the receiver.

it is either positive or negative in R, then the autocorrelation function is nonnegative.


It is observed that if we increase the number of words present in a corpus, the processing time increases and this increment is larger in bigger corpus size as compared to smaller size corpuses.

keeping smaller corpus size effectively reduces the overall computation time during clustering.


Since transmitter baud rate is 18450 bps and receiver baud rate is 20000 bps , the percentage difference in their baud rates is 7.750% which is more than 4.575%.

framing error is generated at the receiver.


First, the processor chip must be redesigned to deal with having a multitude of TSVs driven through it (which has implications in terms of engineering effort, tools support, physical design, etc.).

a relatively conventional chip design can be used for 2.5D stacking as the processor die has no TSVs and does not need to undergo die thinning (risking cracking and other mechanically-related yield issues).


Wide I/O [20] has low speed and thus very large bus width with only one-to-two channels supported.

wide I/O 2 [24] has increased the number of channels to four-to-eight allowing the bus width to reduce (with larger prefetch) and increasing the frequency.


The previous analysis shows that increasing the number of channels is extremely beneficial for performance reasons.

a problem with increasing the number of channels is the reduction in DRAM density.


However, the number of cycles in which the bus is actually transferring data (the data cycles) for a given transaction size remain constant.

in the case of consecutive page misses, in which the next transaction can be sent after a minimum of tras cycles, only a few of the bus cycles will be transferring data.


On average, the combined power consumption of the processor and DRAM keeps at the same level

for the adoption of MVX, several implementation issues have to be considered, which are discussed in this section.


For high-MLP applications, the bandwidth upgrade will reduce contention among concurrent memory requests, reduce memory latency, and improve performance.

3D-stacked DRAMs cannot reduce idle-system memory latency.


TSV links shorten interconnection paths and reduce connectivity impedance.

data can be moved at higher rates with lower energy-per-bit.


The resulting extremely high access parallelism (at the expense of loss of unneeded flexibility) offers enormous power-performance-cost benefits when relevant.

the data flow graph and the assembly plant analogy expose a very important fact: any given data item is generated by one entity and is usually only required by very few others.


An illustrative example is a program operating on a stream of input data, and a situation wherein the result computed by a given ALU (instruction in the program) is used as an operand by several others.

the arrival times of the remaining operands required by each of the consuming ALUs differ and are moreover not known exactly in advance, as they are data dependent.


The similarity between spatial computing and an assembly line and with data routing in general, calls for examining the relevance of various buffering, queuing and routing schemes and constructs used there to the organization and interconnection of operand memory in a spatial computer.

it is important to create a set of such constructs and to implement them efficiently as building blocks in the hardware (just like lookup tables, flip flops, multipliers and connections).


When one chip fails or there are multiple errors in a chip, Chipkill-Correct and E-ECC Scheme 1 can correct these errors without additional memory reads.

v-ECC, LOT-ECC and Multi-ECC all require additional reads to correct errors.


In case of row failure due to random errors, Scheme 2 detects the errors with 99.9986% probability (Section 5.5) and relies on higher level protection mechanisms such as roll back to recover the data.

in such cases, Scheme 2 will incur performance and energy loss due to use of the higher level protection.


In addition, to evaluate the multi-core system performance, we create two 4-core multiprogrammed workload mixes of the aforementioned SPEC2006 benchmarks to realistically model the multiprogrammed application execution scenarios.

next, we present the various existing ECC schemes (in Section 2.3).


This code can correct an erasure from a chip that has been marked faulty and can detect one more random error in another chip.

for higher reliability, it is important that the random error in the second chip be corrected and so a stronger code is necessary.


If so, it activates single error correction; otherwise, it declares there are errors.

in this section, we analyze the reliability of the competing schemes.


In this paper, we aim to reduce the cell-spacing below the WD-free distance of ∆, and apply innovative ideas to codesign the layout and coding to eliminate WD.

it is important to realize that modifying the cell layout is constrained by the physical limits imposed by the underlying technology node.


Hence, a higher number of dies per wafer for a given density directly translates into lower cost per die.

the final cost of a die depends not only on die count, but also on the die yield since die cost is directly proportional to the inverse of yield [9].


However, this approach is increasingly at odds with technology scaling and the effect of PV due to a wider range of latency behavior, particularly in a cell's access transistor and capacitor.

the impact from PV grows stronger with decreasing transistor and capacitor size, required for increasing chip density, which may cause more yield loss due to operational timing violations.


We also analyzed the trade-off between relaxed timing and application performance.

how much does the timing have to be relaxed to regain enough yield and what is the performance cost?


Rather than relying on conventional strategies, better-than worstcase design approaches, which relax timing and manage performance, will be required, spanning DRAM design, architecture (memory controller) and even the system software.

we advocate in this paper for a new soft yield strategy in which memory timing constraints are allowed to vary by location to rescue chips that would have failed under strict global timing constraints.


Hence, the larger the block size, the more likely for blocks to be downgraded to slow blocks.

it may be possible to architect blocks to define new logical blocks composed of fast, normal, and slow physical blocks.


In particular, several memory sub-system parameters can be tweaked, possibly to mitigate the performance loss from relaxed timing.

the memory system could potentially be provisioned differently to enable relaxation of the timing; with small degrees of PV, it may be possible to adopt relaxed global timings with appropriate configuration of memory sub-system parameters, such as redundancy, buffering and bank parallelism.


GPUs appear to be ideal accelerators for streaming computations: with their many processing cores, today’s GPUs have 10X the compute power of modern CPUs, and they have close to 6X the memory bandwidth of modern CPUs,1 yet are priced as commodity components.

a number of issues had until recently prevented effective acceleration in practice.


These efforts have shifted the primary bottleneck preventing higher GPU core utilization from the PCIe link to the GPUside memory hierarchy.

three factors currently prevent further improvements in core utilization.


The decision to use thread-private cache segments is based on the fact that inter-thread data sharing is rare in the streaming applications we are targeting.

the threads mostly process data independently in disjoint locations of memory.


For accesses to non-cached data structures, the performance overhead entails the execution of four extra machine instructions.

accesses to cached data structures incur signifcantly more overhead in some cases; e.g., when evicting a cache line.


We decided on using 16-byte cache lines after experimenting with different cache line sizes — see Section 4.5.

based on our experiments, the monitoring phase accounts for less than 1% of this overhead.


A good design needs an in-depth understanding of end-user workloads.

designers rarely get insights into end-user workloads because of the proprietary nature of source code or data.


Workload cloning is an emerging approach that can bridge this gap by creating a proxy for the proprietary workload (clone).

the DRAM subsystem is organized in a hierarchical fashion consisting of channels, ranks, banks, rows and columns as shown in Figure 1.


We argue that the overhead of reuse distance in main memory is negligible and feasible for online estimation for the following two reasons: 1) The tra.c in main memory is 40-100Ã— smaller than in the cache system.

the estimation overhead can be drastically reduced.


Compared to PCache, HRank causes 7.1x more data accesses in the PCM.

the energy consumption of HRank is more than the PCache in the pF3D case.


A perfectly unequal distribution (i.e. only one memory page is ever accessed) would have a Gini coefficient of 1.0.

additionally, memory vendors see new architectures as a way to differentiate themselves and offer higher-margin products.


35% of pages account for almost 75% of memory requests.

minife, a .nite element application, has a more equal distribution (the top 35% of pages only account for 45% of accesses).


Broadly speaking, each of the 10 workloads presented in Section 5 has high memory traffic.

but hardware caches are not without their challenges.


Traditional OS page cache management policies operate as demand paging replacement policies.

when a memory access occurs to a page that is not resident in cache, the replacement policy decides which victim page to evict from the cache to make room for the freshly-accessed page.


We use another metric from Weinberg for computing spatial locality based on the average length of non-zero strides across an application within a lookback window W=32 that captures address strides.

within the previous W addresses, find the one with the minimum absolute distance to the current one and call it the stride length.


When the PCM has more levels, herniated hash tables can yield more benefits by deeper prefetching and more overlap between computation and memory accesses.

since latency is exponential with respect to the depth of the level accessed, there is a significant overhead when the highest level is accessed from PCM.


In each case, the data shows two columns, one for only accelerating the Txlog and one for accelerating both TxLog and BinLog.

direct mmap directly accesses data in PM without caching in DRAM [7].