Even when remote, the PM configuration still delivers better performance than local flash when used over Infiniband.

as latency increases substantially with Ethernet, the application performance of remote PM drops dramatically to become far less than that of local flash.


Identification and definition of guidelines for manual composition of convergent services are problems that have been investigated for years [18]; more recently, automation of different phases of convergent composition has been actively researched.

we have developed a framework called AUTO [3][4][5], which aims at supporting the automated composition of convergent services using automated planning for service composition and natural language processing for user request processing.


The data in Figure 9(a) assumes an ideal MPPT implementation.

models with better accuracy can be obtained with fewer measurements from a relatively uncontrolled environment.


For powering energy-neutral WSN, PV energy harvesters generally offer the highest volumetric power output [2], and power conversion and maximum power point tracking (MPPT) techniques for solar energy harvesters are relatively well understood.

the extent to which available energy varies over time can cause problems for system designers.


Systems-of-Systems (SoS) result from associating independent, complex systems for fulfilling given missions.

soS require software architectures that can cope with their dynamic, critical nature.


A contract expresses behavioral properties as well as specific policies and constraints that are necessary for coordinating constituents in an SoS.

furthermore, we identified desirable features for tools associated to ADLs for SoS.


Second, the mediator building block describes an architectural element that manages the interaction among heterogeneous constituents within an SoS and promotes interoperability.

mediators not only transmit data (as connectors in traditional systems), but they are also able to process such exchanged data and to coordinate the interactions among constituents.


As UML is a well established standard for modeling software systems, several tools currently support it.

the Papyrus Modeling Tool is an open-source graphical editing tool available as an extension for Eclipse.


CML is a formal language designed for supporting SoS engineering.

cML models could be derived from SysML block de.nition and state machine diagrams, thus enabling to describe the combined semantics of constituents in an SoS as synchronous events.


Some examples of formal and semi-formal ADLs identified in these studies are UML, SysML, CML, and X-UNITY.

the combination of formal and semi-formal ADLs has also been proposed for describing SoS.


X-UNITY is a formal language that addresses the description of interfaces of constituents and SoS.

constituents in a X-UNITY description present internal variables (called context) and exposed variables that are visible to other constituents.


WZeroRPC is an open source platform that takes a different approach by offering a workflow-based execution model that can be embedded within conventional programming paradigms.

it provides support for executing a directed acyclic graph (DAG) workflow, executed across a distribution of workers, along with the dependencies between them, whilst providing a Python interface for coordinating execution and data dependencies between multiple workflow instances.


In Section 4 we shall present WZeroRPC, which addresses this issue, and also explain its relationship to other WMS more generally.

we shall first explain the context within which this work has been carried out, namely the SWITCH project.


Although cloud environments are capable of providing virtualized, elastic, controllable and high quality on-demand services, they still lack the ability to control the selection and configuration of infrastructural components in response to changing requirements and environmental pressures.

current Cloud environments still do not have the tools and application programming interfaces that would allow the developers to exert such control on the underlying infrastructure in an intelligent, semi-autonomous manner.


Each node has an ID that must be unique on this server.

when requesting the telemetry server using a node ID, this node (and its subnodes depending on the request) is used for the response or none if this ID is unknown.


Despite the modularity of existing workflow engines, described in Section 2, workflow systems generally provide a language to model the entire process and logic defining the interaction of components.

dynamic interactions happen within the workflow language and structure of the workflow systems, which means that in order to create a dynamic data workflow, a developer would: Need to learn to program using the workflow language of a system.


Each Channel represents a semantic search and therefore is processed independently of other channels.

multiple Channels can exist concurrently and also channels can grow rapidly as the interest in a particular topic increases by the users of the network.


Though designed specifically for minimising transmission times, SPDY also compresses and in some cases eliminates request and response HTTP headers.

given that headers range in size from 200 bytes to 2 KB, its ability to reduce overall data traffic is limited [7].


This permits clients to retrieve precisely the required data by specifying filters on data items.

we evaluate EDGEREDUCE using three real-world mobile client applications for Twitter, Groupon and Yahoo!


The nRF24L01+ transceiver has several configurable parameters that can be tuned for the specific applications.

its most configurable parameters that impact the energy efficency of the communication are: transmission speed, transmission power, payload size, activation of acknowledgments.


Power gating without retention FFs will dump its state into memory, which helps eliminate logic SER during gating.

power gating with retention FFs will increase SER as FFs in retention mode are more vulnerable to soft errors.


The hardware evaluation platform has to be general enough for targeting different hardware configurations as well as fast enough for running system software.

implementing actual hardware for each of the configuration is impractical and simulation-based approaches are not feasible.


In order to use MVX instructions, we require no changes to source codes.

the code needs to be recompiled in order to make use of the MVX instructions.


Its evolutions as DDR 2, DDR 3, DDR 4 and so forth generally increased the I/O frequency by increasing the data burst capability and bus operating frequency.

the organization of a DDR DRAM device in all versions suffered few architectural modifications.


The branch bitmap maintains the knowledge of basic block boundaries within a block, allowing for providing the instruction fetch unit (L1-I), with multiple instructions to fetch in a single lookup.

this is a rare event when an instruction prefetcher with high miss coverage and timeliness is employed.


Hence, we proposed to design accelerators that instantiate the APIs of these commonly used libraries in hardware.

a hardware-software co-design approach is used to target memory-bounded operations within commonly used high performance libraries (e.g., BLAS and FFTW) for portable energy efficiency.


The overview of our solution is shown in Figure 6.

memory-bounded operations (e.g., scalar product, general matrix vector multiply, and fast Fourier transform) bene.t to a lesser degree on accelerators.


Directive-based programming models such as OpenACC [50] are proposed to ease the programming burden of specialized accelerators.

the end result is Memory Accelerated Library (MEALib).


Since all elements of a given data type share the same expected range of values (as discussed in Sec. 4.1), elements with relatively smaller values (e.g., interest rates) become overly susceptible to approximate similarity, leading to some inaccuracy.

all of these overheads are faithfully modeled in the energy and area results in Sec. 5.


Pages that have only been accessed twice will have only one delta available and will be restricted to using the first DPT table for prediction.

as the page is repeatedly accessed, and more history is accumulated, DPT lookups may produce matches in more than one of the DPT tables.


For the LPDDR3based point-to-point system, since all of the data are supplied by a single chip, it is easy to apply a data layout similar to what is shown here.

this paper presents MiL (More is Less), a novel data communication framework built on top of DDR4, which exploits the data bus under-utilization caused by DRAM timing constraints to selectively apply sparse codes, thereby reducing the IO energy without compromising system performance.


However, current hypervisors already track the sharing status of each page for memory management.

for vCache, its hypervisor just stores the already tracked status bit (1 bit) in the page table entry.


Due to the workonly/allocation policy with vCache (geo-mean of three conserving policy of vCache, VM1 can exploit unallocated/unused capacity along with its allocated vLLC and thus vLLC shows higher performance than pLLC while preserving VM2 s performance.

vM1 can exploit more capacity before VM2 fills its al located capacity, since VM2 does not fully utilize its allocated capacity.


In terms of normalized LLC misses, vCache also preserves the effectiveness of the page coloring schemes for all workloads.

such an illusion of resource dedication has not been supported for the last-level cache (LLC), although the LLC is the largest on-chip shared resource with a significant performance impact.


For virtualized systems, the hypervisor may directly enforce page coloring for VMs or applications to control cache allocation, but enabling vCache does not allow such hypervisor-based page coloring.

the rationale for vCache approach is to allow independent cache managements by the guest OS and hypervisor.


Consequently, sLLC shows higher performance improvement than pLLC for VM1.

for such control, each cache line keeps a VM identifier to identify the VM that loaded the cache line.


One simple method to provide a VM with an isolated LLC is to dedicate fixed physical cores and LLC slices to a single VM; a physical core is associated with a slice of LLC (e.g., a core has a 2MB LLC slice in an octacore processor with 16MB LLC [30]).

this approach is neither effective nor flexible.


A key role of machine virtualization is to provide an illusion that each workload runs on a dedicated machine, while sharing machine resources with other co-executed workloads [1].

such an illusion should be rigorously provided for utility computing that is typically offered by the public clouds where each user desires his/her workload to fairly run on the paid resources.


Such a page coloring technique can allow the OS to evenly spread accesses across LLC sets or reduce interference amongmultiple applications sharingthe LLC byassigninga suitable LLC region for each application.

it is widely supported by the mainstream operating systems such as Solaris, FreeBSD, netBSD, and Windows NT [12, 19, 13, 20, 17].


V-SR provides isolation between physical cores and the coherence scheme by mapping logical sharers used in the coherence scheme into physical cores in the system.

the coherence scheme only needs to keep track of a small number of logical sharers that get mapped into the subset of physical cores used by the application.


Based on the above implementation details, we see that SR and HR have a similar software and hardware flow.

sharer domains and home domains can be managed similarly.


A smaller line size results in an increased number of evictions.

canneal shows a higher number of clean evictions increasing CET .


Canneal, which shows high MPKI, benefits from using smaller size partitions in Phase 2, as frequent evictions lead to decrease in DET .

there is a need for an accurate cache vulnerability modeling and a lightweight online estimation technique that accounts for both spatial and temporal vulnerabilities of concurrently executing applications under changing cache configurations.


we use the average value obtained during offline characterization of the application to estimate CCF.

phase classification is based on clustering basic blocks considering their execution behavior and their frequency of occurrence.


the observations described above led us to explore the possibility of reconfiguring the cache to increase its reliability (i.e. reduce its vulnerability) while running different applications.


Fingerprint-based comparison has better performance but needs to resolve potential collision problems, compared to byte-tobyte comparison.

sHA-1 hashing is one of the most commonly used methods in generating fingerprints of selected data because SHA-1 has an extremely low collision rate and, at the same time, reasonably good performance [10, 16, 20].


The objective is to optimize the PCM space utilization with a good balance in the system performance and the space utilization, where data deduplication is adopted to increase the de facto capacity of a storage device.

a containerbased space manager is proposed to increase the efficiency of the PCM space utilization as more and more data are written.


To address this issue, we propose to adopt wear leveling for containers with the integration of the proposed two-class bucket list.

when a container is selected by procedure C ONTAINE R -ALLO C (in Algorithm 3), this container is compared with the first container of each bucket in both the compact and non-compact lists by checking their age .eld in the their container metadata records.


In order to minimize the frequency on allocating containers from the proposed bucket list and to ultimately extend the time on repacking chunks of containers, we adopt the worst-fit policy that tries to allocate containers with the largest free space and prefers to allocate the free space without any internal fragments.

the proposed strategy will scan the compact list from bucket N to bucket 0, and return the first container from the bucket that is not empty.


The rationale behind this design is that the storage device initially has more free space but less knowledge in data deduplication.

there is no need to have too many compaction activities to optimize the space usage in the beginning.


What is the last mile of the challenges in the designs would be on how to effectively provide an operating system a PCM storage device with a common storage-device interface, which is usually of fixed management units such as an LBA (or referred to as a sector for hard disks).

the technical problem falls on how to (1) efficiently manage (i.e., allocated and deallocate) free PCM storage space and (2) map fixed-sized LBAs to variable-sized chunks when CDC is supported, so that the space utilization of PCM-based storage could be ultimately improved.


Then the second field value 1024 indicates that LBA 2 starts with byte 1024 of chunk A.

by deducting 1024 from 1100, we can derive that the last 76 bytes of chunk A are stored in the beginning of LBA 2.


In this way, the number of buckets can be significantly reduced to improve the performance on scanning the buckets for containers that have enough free space for new chunks.

otherwise, the containers related to the returned tree node are merged as a larger container, which is then returned to store new chunks (Lines 4-5).


Then, we removed a specific percentage of the generated data randomly and restarted the data generation procedures.

for the high duplicate workload with large file size, such as fileserver, paging could achieve good performance.


This work is motivated by the demands of intelligent storage devices.

we are interested in the designs of intelligent storage devices with the capability to store much more data than its original storage capacity.


In Figure 6 we assume without loss of generality that the execution time of cv1 at V-fmax is less than the timing constraint (denoted by deadline).

let us consider that the power consumption at V-fmax exceeds the TDP constraint.


Figure 3 shows software vulnerability (in log scale), execution time (in terms of clock cycles) and overall reliability (see Eq.2) of different compiled versions for three applications.

the power consumption at a high V-f level may exceed the TDP constraint of the underlying Dark Silicon chip.


In the rest of the algorithm, the main computation is performed to examine all V-f level scalings and code changes for all ready tasks and then putting them into a maxheap.

the total power consumption of a core at a V-f level and threshold voltage Vth can be written as Eq.


All the stacks for a particular function share a single stack pointer.

our technique considers exactly which variables are live across recursive calls and only stores those to a shared stack, which may lead to reduced memory usage.


We represent user-defined data types as statically-sized bit vectors in hardware; if a definition is recursive, we cannot determine how many bits to assign to the recursive component at compile time.

we replace recursive portions of these data types with a pointer data type e.g. a non-empty integer list defined as Cons Int List becomes Cons Int Ref, where Ref can be defined as a primitive numeric type.


We select an energy efficient RF size for comparison against the nonoptimized and the pruned radix-2 implementations.

if the vector register width is W , the number of memory  min(m, 2N k ) subset_acc(N, m, k, W ) = (7) W We use the ceiling operator so that if the number of non-zero points is not a multiple of SIMD width W , then the additional load fetches the remaining values.


For all experiments, our approaches and Daikon extracted the same set of invariants.

from the accuracy point of view they are equivalent, while they differ from the execution time point of view.


GPUs are multi-core coprocessors originally intended to speed-up computer graphics.

their highly-parallel structure makes GPUs powerful devices also for the elaboration of general-purpose computing-intensive processes that work in parallel on large blocks of data.


Indeed, execution time of invariant mining depends on the number and length of the execution traces to be analysed, the number of considered variables, and the number of invariants actually present in the traces (due to the effect of the two optimizations described at the end of Section 4.1.

experimental results have been conducted on randomly generated execution traces with different values for such parameters by considering boolean and numeric (integer and real) data-type variables.


Indeed, a T-invariant is a TW-invariant for a time window that extends from the first to the last simulation instant of the corresponding trace.

to avoid burdening the discussion, in the following, we use the term invariant when concepts apply indistinctly to T-invariants and TWinvariants.


However, MD5 has other attributes that make it a useful complement to the various memorybandwidth and .oating-point intensive algorithms already in SHOC.

like many hash functions, MD5 contains many integer and bit-wise operations.


This python code was used as a baseline to produce both a CUDA version, using CUBLAS and hand-written CUDA, and an Intel Xeon Phi version, using OpenMP and offload primitives.

when using the newer 14.6 version of the compiler, MD5Hash would run as expected, but performance of MaxFlops dropped to less than 50% of the device peak.


An experimentation procedure, described in detail in [15], has been designed to estimate all the required parameters that cannot be obtained analytically.

[15] depicts how host and Xeon Phi power, execution time, and performance are estimated experimentally using application code instrumentation.


The model uses widely-used performance metrics, such as data movement and computational throughput, to estimate execution time and relies on static and dynamic power estimates to calculate the total power draw on each participating device.

the proposed model may be used to access the power-capping affects for a given application.


Our compiler supports VLIW and SIMD vectorization.

it is challenging for the programmer to make effective use of a complex MPSoC.


Reconstructing any specific design state is not considered more valuable than reconstructing any other state.

practical debugging experience suggests that some signals are inherently more valuable for validation and debug than others.


Consequently, signals selected to optimize SRR do not necessarily facilitate debug.

sRR is not useful for signal selection for designs with the following features.


However, this operation would overwrite the state of the flip-flops and the circuit cannot resume normal operation after it is completed.

to maintain the state of the flip-flops, the bits that are being shifted out from the scan chain are fed back into it through a multiplexer, as shown in Fig. 4.


In [24], the design of a Texas Instruments 3.5G baseband and multimedia applications processor is presented.

increasing the number of scanchains increases the size of the MISR, and therefore, more area is required to implement it.


The microcontroller can read and write to the registers on every on-chip core through this interface.

the signature and the sensor data can be accessed by the microcontroller through the I2C interface using buffer read operations.


CHStone suite is a set of 12 benchmarks, explicitly collected for the evaluation of High Level Synthesis flows, which aim at representing all the possible scenarios which have to be addressed by an High Level Synthesis tool.

this suite contains both data dominated applications (aes, blow.sh, jpeg, mpeg2, sha) and control oriented applications (adpcm, dfadd, dfdiv, dfmul, dfsin, gsm, mips).


In particular 1 obtains better results on mips thanks to the implementation of Rotation Scheduling.

3 obtains better results on dfdiv and dfsin thanks to the implementation of a better division algorithm.


For example, if we use dedicated interconnections, we can connect a given F Ui to at most max_fanin + max_fanout other FUs.

due to the recent high transistor scaling rate, reached with the use of new technologies [1] [2] [3], the transistors density per area unit is hugely increased.


However, we need to take into account the non-conflict constraint on a given buslet: for this, we need to ensure that at most one FU per clock cycle will drive the buslet (this will be done via tri-state buffers, enabled at the right clock cycle(s) by the datapath FSM controller) In order to ensure this, a proper scheduling algorithm is needed which minimizes the number of buslets required for such a constraint; a corresponding binding algorithm with other minimization goals and constraints is also needed.

our algorithms solve a variation of the MR-LCS problem that we call MRW-LCS (minimum resources and wiring, latency constrained scheduling), and is divided into two stages: 1) Scheduling algorithm, which is itself divided into two phases: a) FDCS (Force Directed Communication Scheduling), a modified version of Force-Directed Scheduling [6], minimizes the lower-bound number of buslets implied by scheduling communications between operation nodes (the number of buslets could increase from this lower bound during binding, as we need to satisfy some extra constraints there).


Dashed arrows indicate communication requested between resources, a different color indicates a different clock cycle in which a communication is scheduled; while thick lines indicate wires.

in the next section, the concept of flexible buslets and their potential bene.ts to VLSI designs will be discussed.


Here, delay bounds on paths are treated in the same way as routing space constraints.

delay violations are not banned but minimized simultaneously with routing congestion.


To calculate the down stream capacitance for each si, we traverse the net tree from sinks to source in a bottom-up manner.

the down stream capacitance of the source segment, i.e. the segment connected with the driver pin, should be calculated after all the other segments have obtained their down stream capacitances.


Although top metal layers are less resistive than those in lower (thin) metals, it is impossible to assign all wires to top layers.

layer assignment should satisfy the capacity constraints on thick metals.


Since timing requirements within a single net are usually different for different sinks, assigning all segments of a set nets on higher metal layers is not the best use of critical metal layer resources.

intelligent layer assignment should not blindly assign all segments of a net to a set (a pair, for example) of higher metal layers.


Unlike the clock tree with links between clock nodes, which is a sort of an incremental modification of the structure of clock tree, clock spine network is a completely separated structure from the structures of tree and mesh.

it is necessary and essential to develop a synthesis algorithm for clock spines, which will be compatible to the existing synthesis algorithms of clock trees and clock meshes.


Since the specification items are tightly related each other and it is practically very time consuming to explore all feasible clock spine candidates, we solve the problem of clock spine synthesis by performing four steps.

our proposed power-aware clock spine synthesis called CSPINE consists of four steps: (Step 1) Clustering clock sinks, (Step 2) Relaxing spines, (Step 3) Inserting spine buffers, and (Step 4) Constructing a top-level clock tree.


(Note that the previous power-aware clock tree synthesis algorithms (e.g., [13]) performed SPICE level simulation.


The results are stored into a on-chip non-volatile memory.

physical unclonable function (PUF), first introduced by Gassend et al. [5] based on inevitable manufacturing variations, can be used to generate unpredictable and unclonable IDs.


As reported by US Department of Commerce [1], counterfeiting accounts for more than 8% of global merchandise trade, which is in the trillion dollars range.

counterfeit electronics are increasingly being distributed throughout the market and legitimate electronic companies miss out on about $100 billion of global revenue every year because of counterfeiting, thereby posing a severe threat to the global electronic supply chain [2].


Various techniques have been presented in the literature to generate unique IDs for IC products [4].


The ARFIMA model allows for incorporating the long term memory of the process x(t) by capturing the fractality within its fractional differencing operator.

for instance, for a large scale NoCbased multicore platform capable of both wormhole packet and network coding [11] communication, the MPC-based optimization modules have to decide when to switch between the two approaches such that the power/energy consumption profile is minimized while not sacrificing overall system performance.


The length N of the SNs used in a stochastic computation controls the accuracy and the total energy consumed by the circuit.

by decreasing N, one can trade away accuracy for energy or power savings.


Our approach to this problem is a straightforward search within the operating-point space.

we will try different operating points and, for each, evaluate the accuracy and energy of the corresponding circuit.


While CSE preserves the cluster structure through the conversion from a proximity representation to a Euclidean vector representation (e.g., the cluster structure is preserved between E1 and P1 , between E2 and P2, and so on), the k-means cost function in the original feature space O1 would also be identical to the cost function of pairwise clustering in the proximity matrix derived using Euclidean distance P1 [19].

applying k-means clustering in E1 is equivalent to applying k-means clustering in O1.


From the high-dimensional base feature space FM .FB .FN , the proximities are able to reveal the underlying horizontal stripe pattern on the wafer even though in most test items this pattern are not directly observable and shadowed by some other more dominant types of spatial patterns.

such stripe spatial variation may be subtle but consistently exists in most of the test items.


In fact, the classification accuracy based on the base features plus the two kPCA based features (LOF value and the first dimension of the embedded space) never surpasses the classification accuracy based on the base features only, in the range we searched for an optimal pair of SVM parameters [18].

including both subsets of the proximity based features for classification could lead to a significantly greater test escape detection rate than including either of the subsets alone.


The idea is to generate an emulated test escape pool such that the corresponding test items of those hidden failing measurements are widely spread among a large number of test items and no single test item can directly detect a large number of emulated test escapes.

we identified test items that hiding each of them would cause an increase of test escape rate by more than 50PPM to test escapes, and removed the test escapes created by hiding these test items from the emulated test escape pool.


CSE involves eigendecomposition of the proximity matrix [14].

the embedded space is composed of the eigenvectors of the proximity matrix.


In uniform TSV placement, f-TSVs are placed uniformly, and they are considered as placement obstacles when logic cells (IP blocks) are placed in the 3D placement stage.

in non-uniform TSV placement, the f-TSVs are added to the 3D netlist as TSV cells, and then placed with the logic cells (IP blocks) simultaneously during 3D placement.


In order to boost the likelihood of successful repair when multiple TSVs are faulty in the same group, it is bene.cial to increase Ngs , but it also leads to higher hardware cost.

it is important to explore the trade-off analysis between TSV yield and hardware cost.


For s-TSVs, as discussed in Section III, they can only be inserted in whitespaces.

a branchand-bound based approach is used to extract the whitespace [34], and then the location candidates for the s-TSVs can be determined based on the amount of whitespace and the area of a single TSV.


Clustering leads to the locationdependency of TSV defect probabilities [14].

the defect probability of each TSV is related to its location.


For the uniform case, since the locations of f-TSVs are determined before logic cells are placed, s-TSVs and the supporting infrastructure (i.e., MUXes and wires) can be inserted right after f-TSV planning but prior to the placement of the logic cells and detailed routing [15].

it is not necessary to consider the whitespace constraint during s-TSV allocation.


Then, due to location dependency, the defect probability of the relocated f-TSV will change after the allocation of the s-TSVs, which can result in a situation where repair is not feasible.

the whitespace constraint must be taken into account during s-TSV allocation.


Redirection and masquerade prevention: If A sends a message m to B, then the message must be delivered to B.

it should be impossible for a (potentially rogue) IP C to masquerade as B, or for the message to be redirected to a different IP D in addition to, or instead of B.


To understand how this can be done, note that each router includes a base address register (BAR) which is used to route messages for specific destinations.

one of the routers in the proposed path, Router0 is connected to the CPU; the BARs in this router are subject to potential overwrite by the host operating system, which can consequently redirect a message passing through Router0 to a different destination.


This architecture is specifically targeted towards smartphones and provides secure separation features to enable information partition between business and personal content coexisting on the same system.

it permits hot swap between these two content worlds (e.g., without requiring system restart).


Unfortunately, the state of the practice in this area by far is extremely manual and depends heavily on human creativity and observation.

a security architect roughly iterates through the following five steps until convergence.


From another side, some HLS tools generate the SystemC simulation model after synthesis is done.

we can use the powerful loop transformation in PolyOpt to expose atomic tiles in the source code and transfer them to SystemC modules.


In practice, TLM is supported by SystemC where the computation and communication models are implemented as function calls and channels.

the creation of such a SystemC model is not easy.


Thus, the latency is highly predictable at the SystemC-level.

to achieve diversity, we choose benchmarks from computation kernels with different applications.


Second, most of these studies stay at RTL level and the accuracy of this method is limited when applied at high level (also known as behavior level), where little hardware details is available.

some assumptions and predictions must be made on the hardware implementation, which limits the accuracy.


Despite the significant speedup in simulation time, it is computationally infeasible to exhaustively simulate every design with simulation.

it is pragmatic to apply a technique, such as regression modeling, to characterize the design space with a reduced sample of fast simulations.


SynchroTrace requires generating traces once for each thread count (i.e. a trace for each 2, 4, 8, 16, 32, and 64 threads per benchmark) and has a total compute time on the order of 100 years.

the area of these design configurations is calculated with Cacti 6.5 [22] for the caches and Orion 2.0 [23] for the NoC using the 65nm technology.


Overall, as shown in Table II, the proposed regression modeling methodology enables a .ltered optimal design space, on the order of 100s to 1000s of design configurations, to be discovered out of the total 2.4 million design configurations.

the regression models constructed with uniformat-random sampling all have a systematic bias.


the simulation is partitioned into multiple threads across the irregular line a Simics thread representing the base platform with the IA core, uncore, system memory, Peripheral Control Hub (PCH), network interface and the South bridge components needed to boot the platform, and one or more SystemC threads each running a SystemC device model as part of the VP.


Fifth, we demonstrate how the visualization tool can be used to assist architects to better design the system by a case study for the NUCA design.

the GAM maintains a resource table to track the available hardware accelerators (or accelerator building blocks, i.e., ABBs), and the waiting time of those that are currently in use.


To make a TMG (pipeline network) deadlock-free, all empty cycles must be broken.

since the TMG is derived from the original pipeline network, we cannot simply add tokens to empty cycles.


Both methods can pull cells toward their corresponding regions.

when cells are already in their corresponding regions, only the method with two anchors can avoid further interference from pseudo nets.


Moreover, an initial solution without considering fence region constraints might lead to longer convergence time in the following analytical global placement stage.

we propose a two-round quadratic placement algorithm to spread fence cells to the corresponding regions more closely by the following three steps: (1) we first apply a first-round QP to obtain a solution (see Figure 3(a)).


Therefore, a cell assigned to this fence region tends to move toward the center even it is already in this region, which is not desirable.

rather than adopting an anchor assignment technique, we propose a new density model which considers fence region constraints and minimizes cell overlaps simultaneously.


Divide and conquer used to be applied in global placement, such as partitioning based methods [4, 5, 7, 29 31].

since analytical techniques were proposed, partitioning based approaches are considered inferior.


Each sub-placement would use at most two threads, for example, when generating (or solving) linear systems (3) and (4) simultaneously.


In such scenario, timing estimates that consider only logic synthesis were accurate enough.

in technologies below 90nm the delays of interconnections became much more significant as compared to the delays of logic gates [9] [22].


Observe how our technique drastically reduces the electrical effort (up to -9) of some critical gates that were overloaded before our optimization.

it is possible to conclude that such unloading helps to improve both WNS and TNS since a critical gate may influence several other near-critical ones.


The security wrappers provide a standardized way for E-IIPS to obtain such collateral while abstracting the details of internal implementation of individual IPs.

the wrappers implement a protocol to communicate with E-IIPS during the execution.


Unauthorized or malicious access to these assets can result in leakage of company trade secrets for device manufacturers or content providers, identity theft for end users, and even destruction of human life.

it is vital to ensure that secure assets in computing devices are adequately protected.


This allows us to say that for a greater value of the mean mutual information we will see a greater mean success rate indicating greater information leakage.

both success rate and mutual information are able to describe timing leakage for cryptographic hardware architectures.


That is due to the fact that architecture stops its execution after it reaches the most significant 1 bit of the key.

we can determine with great accuracy where this one 1 bit resides due to the overall runtime of the algorithm.


This shows how much information leaks from the i-th key bit when encryption time is known.

how much does the total runtime depend on the i-th bit of the key


We assume that the attacker can determine the amount of cycles for each execution of the hardware component.

abstract Cryptographic function implementations are known to leak information about private keys through timing information.


the attacker can determine the cycle in which the execution begins and ends.


In the conventional method, the sample number N must be larger than 2FtTg to avoid aliasing of gd[n].

with the constraint in (41), our method requires much less samples of the channel's frequency response than the conventional method.


Most typically, the number of chemical species and reactions are much smaller than the number of possible states and transitions between these states.

in the stochastic chemical kinetics formalism, both the sparsity of possible transitions between the states, and more importantly, the special structure of these transitions caused by a small set of reactions, are exploited to arrive at a very compact representation for a MC that may be otherwise very unwieldy to deal with.


Most often, a well-stirred system is assumed so that concentration of molecules of each type is uniform over the entire spatial domain [38].

instead of tracking the spatial positions of each and every molecule in the system, the system state is compactly represented by a vector containing the number of molecules of each type [21].


Nevertheless, if the generic MC neither has a sparse state transition diagram nor possesses any special structure, using such a formalism does not result in a more compact representation compared with the state transition diagram.

for a generic MC with no special structure, the required number of abstract species and reactions will be equal to the number of states and transitions.


The intricacies in the numerical treatment of (2) arise due to the square root expression in the time-dependent diffusion part of the SDE.

the possibility of the square root becoming imaginary needs to be addressed.


Our merging is more powerful than BRMap’s packing [8], since BRMap only packs operations from if-path and elsepath of ITE guarded by an identical predicate.

operations in the loop kernel updating the same variable may be predicated by various of combinations of predicates when confront nested ITE (NITE) (see figure 6).


With such capability, the proposed design framework can potentially be used for increasing design productivity for any heterogeneously integrated CMOS-NEM design (e.g.

design capture is based on a NEM relaybased standard-cell library.


It varies depending on how soon the relay is reactuated, because a de-actuated relay beam oscillates until the stored potential energy of the beam is dissipated through damping.

the switching-on time is dependent on the position and velocity of the beam at the time of actuation.


Inter-die coupling E-.elds are mostly limited between a few metal layers because of E-field shielding from metal wires.

it is safe to ignore a few metal layers as in our in-context extraction, which still captures most of inter-die coupling E-.elds.


Note that though inter-die coupling capacitance is a large portion of total coupling capacitance, ground capacitance and pin capacitance are major contributors to the load of a net.

inter-die coupling only affects slightly on the switching power consumption of F2F designs.


Overall, total capacitance always increases with a closer dieto-die distance, and the portion of inter-die coupling keeps increasing as well.

die-by-die extraction, which is unaware of the neighbouring die and ignores the E-field sharing, cannot extract the inter-die coupling capacitance accurately.


As long as the total weight of both dies is equal to one, there is no overestimation in inter-die coupling.

for a double-counted capacitor, the weight ratio between the bottom in-context die and the top in-context die is proportional to the product of R ratios of both layers the capacitor connects to.


For example, it can be seen in Fig. 5 that for the gate nets of transistors M1 and M4, the conditions for the unswitchability property for p edges are fulfilled.

the p edges belonging to M1 and M4 are unswitchable.


In this work, we are going one step beyond verification to an automatic, i.e., fault free synthesis of power-down circuitry.

this would introduce head or foot switches which disconnect the ground and/or supply from the circuit.


For each rip-up path, it has to be decided where it should be ripped up following the objectives (B)-(E).

the following algorithm was implemented: In order to achieve a rip-up of current mirrors like it would be done in a handcrafted design (see Fig. 6), current mirrors are detected by a structure recognition method [14], [15], [11].


When receiving the response, NIC inspects the SSV of the response to check if the response is sent from the latest data owner.

the response is confirmed to be valid if there is no preceding write request for the cache line which is not snooped in the SSV from the response(Accordingly, the SSV only needs to provide the snooping status for preceding requests.).


Outgoing coherence request from the local processor is kept at the outgoing request buffer (oRB) until it receives the data response and completes coherence operation.


NIC issues notifications only at the start of each time window, which is set greater than the maximum broadcast latency.

all nodes receive the same set of notifications at the end of each time window.


Further, if two or more processors attempt to write the same memory location simultaneously, processors might observe write values in different orders from each other.

we need well-defined rules specifying correct shared memory behavior so as to provide a basis in writing parallel programs.


Cache coherence defines memory access ordering for the same memory location by two constraints: (1) write must be eventually seen by other processors; (2) writes to the same location must be seen in the same order by all processors.

to show the generality of our proposed Ordered-NoC
platform, we applied it to MPSoC designs running atop two different topologies (2D-mesh and butterfly fat tree) and supporting two alternative memory models, total store order(TSO) and relaxed memory consistency.


The STAGE algorithm can benefit if we can specify the starting state distribution using some domain knowledge.

we also consider a starting-state distribution named a-Greedy.


In this work, we advocate that the concept of small-worldness should be adopted in 3D NoCs too.

the vertical links in 3D NoC should enable the design of long-range shortcuts necessary for a SW network.


To compensate for the loss in performance due to TSV failure, fault tolerant router and NoC architectures with redundant vertical links [10] were proposed.

these designs give rise to additional area and power overheads.


This problem is generally addressed by adding a penalty term to discourage complex functions.

efficient optimization can overcome such limitations.


Apparently, the frequency resolution of such a representation is fmax/n.

in many IPs, it is common that the wire cap is more than the device parasitics cap, which has been silicon validated on on-market products [22].


It needs to be clarified that since entropy production has only been experimentally proved on metals, our fatigue analysis only focuses on the TSV body and the attached landing pad.


In the simulations, we also discover that the rate of entropy production increase in the landing pad and the TSV body through cycles remain the same.

single cycle modeling is sufficient for TSV fatigue analysis using entropy production, which will be used in the remaining of the paper.


According to the second law of the thermodynamics, entropy is generated when the permanent degradation is presented through an irreversible process, which leads to a monotonic increase of disorder in a system.

the component of material degradation can be measured by entropy and thermodynamics energy [13], [14].


In the experiment, the chain has 50 links repeatedly, alternating between M2 and MC, which are local interconnects linking to other stacks.

this unsymmetrical structure would lead to a non-homogeneous stress on vias.


Furthermore, by applying the entropy degradation theory related thermodynamic forces, Amiri [16] experimentally determined the critical damage value of specimens subjected to different operations based on the entropy flow.

this method has only been applied to large scale analysis (in scale of meters), not to micro structure.


In F2B bonding, TSVs are used for vertical interconnects.

since TSVs penetrate through the silicon substrate and occupy area, using excessive TSVs lead to area overhead, which designers should avoid.


Block-folding technique helps to reduce significant power in three-tier design.

in this effort, three-dimensional integrated circuits (3D ICs) using through-silicon vias (TSVs) have gained a great deal of attention as a viable solution for low-power IC designs.


SEU behavior on logic resources, e.g. LUTs, has been well discussed in [1].

the m inputs of each multiplexor are individually controlled in a fully decoded style [16] and the n multiplexors are sharing the same m con.guration bits.


In the synchronous execution model, data from the previous iteration is accessed by the neighbors.

asynchronous model allows access to the latest data available.


Methods such as [7], [8] skip over the noncompliant stimuli by re-seeding the LFSR to a functionally-compliant value.

the methods from [12], [13] let the LFSR run autonomously, however the stimuli are corrected in real-time using a set of encoded cubes placed on-chip.


In particular, by setting WX = m, the algorithm will select cubes with large implied space first strategy.

it collects the cubes with the largest implied space, and selects one with the lowest correlation.


The addressing logic can record the status of cubes and overwrite the used cubes by new cubes that can be uploaded after all the patterns from the initial cube set have been exhausted.

the cube RAM serves as a fist-in-first-out cube queue and refreshes its content as the validation process progresses.


However, a fixed length LFSR as used in [12], [13] lacks the flexibility of varying distribution of the sequences according to cubes, which causes stimuli repetition.

a dynamic LFSR is designed based on it, and we select ξ (defined in Equation 2 from Section III) to control the behaviour of the dynamic LFSR as a degenerated ξ-bit LFSR, as detailed next.


First, on the one IP block that got full coverage, it happened at the same time that all instrumented CMs were covered.

full coverage was only achieved when all instrumented CMs were set.


we found that even the naaive method provided good guidance in prioritizing which CMs are better to monitor.

the fatal flaw with the native method is that it can severely miscompute the probability of full coverage: under the assumption of independence, Eq.


For the naÂ¨ive method, there are no scalability issues, and the selection algorithm is simply to pick the hardest-to-cover CMs greedily.

as noted earlier, the naÂ¨ive method miscalculates the probability of full coverage, so if we wanted a probability of greater than 98%, the naÂ¨ive computation often suggests including all or almost all CMs.


non-uniform cooling that increases on-chip thermal gradients giving rise to reliability issues and shorter lifetimes.

it is fundamental to optimize several parameters, such as the pressure drop across the channels, the number of fluid inlet and outlet ports, and the fluid network, to achieve optimized cooling in terms of energy efficiency, thermal gradient and peak temperature.


In the former, improving the slacks of a subset of paths does not guarantee an improvement on total negative slack (TNS) or worst negative slack (WNS).

improving the slack on one failing path can cause several originally-passing paths to now fail.


As the logic function for cells was not known in the original ICCAD-2012 contest benchmarks, the methodology in [15] created a (unverified) mapping to standard cells based on their sizes and pin counts.

a given cell would be mapped to a cell type that has the same input/output pin counts and the same or slightly smaller width in the given cell library.


FHT also removes duplicated and circulated traffic from the rings.

the FHT approach significantly reduces redundant unicast traffic in HSR networks.


Traffic-filtering based techniques mainly focus on solving the HSR s issues.

these techniques try to filter unicast traffic for unused rings in HSR networks and remove duplicated and circulated traffic from the rings.


FPGA-based image processing can run parallel calculations and stream processing.

fPGA-based image processing has latency, not delay [11] and can operate faster than PC-based processes.


If the reference count is more than two, proposed algorithm regards the page as a hot page and the page is migrated to the MRU position of DRAM [Figure 2d].

clean pages on PCM are not migrated to DRAM even if its reference count is more than two because read latency of PCM is similar to that of DRAM [Figure 2e].


Especially, our algorithm performs better in the range of small size memory.

our algorithm is suitable for the process which issues a lot of read/write requests at critical state.


LMK does not kill the process whose oom_adj value is below zero such as system process and foreground process.

the pages, which are accessed by non-critical processes, are firstly placed on PCM because non-critical processes do not need fast response time.


These two types of processes can affect to the user directly or indirectly because they are visible to user.

algorithms need considerably long time to run the same workload because they do not give higher priority to critical process.


We present EnhancedTouch, a novel bracelet-type wearable device for facilitating human-human physical touch.

we aim to support children with autism spectrum disorder (ASD), who often exhibit particular communication patterns, such as lack of physical touch.


A possible solution is to employ electric field PAN technology, where the electric field induced around the surface of human body is used as a communication channel and the electrodes do not have to attach to the skin.

in this case, accurately differentiating the touch and proximity is a challenging task because RSSI depends not only on the contact states but also on the spatial relationship between the devices.


In such scenarios, a particular CL still follows the most suitable hierarchy at run-time.

a CL follows a two-level hierarchy when there are multiple copies of itself; the same CL follows a three level hierarchy when there is only a single-copy in the system, thus optimizing the access in both cases.


To this end, the Simulink model of the control design is updated with extra delay blocks.

a parametrised rule-based model transformation is created as depicted in Figure 3.


For example, at time stamp 8 s the driver issues a lower-command resulting in an ideal reaction time of 52 ms.

after deployment the reaction time appears to be 221 ms which is 10 % higher than required.


During these successive iterations, the available ADL can be used to enhance the deployment process.

the Design-Space Exploration (DSE) process for optimal deployment can be influenced by taking into account information available in the ADL.


The GAP algorithm that is used in the CALIC design, also tries to take several different edge types into account.

it accumulates all absolute vertical changes and compares it with the accumulation of all the absolute horizontal changes.


For the red and blue color, this is sufficient.

in this paper, it is proven that a synergy can be reached by combining a color filter array (e.g. Bayer pattern) with known predictive-corrective coding filters and an entropy encoding for a higher overall lossless compression of images.


To be correct, it must be mentioned that for this research the GBRG Bayer pattern (as in figure 6) has been chosen and reverted from the benchmark images.

the results only give a good indication, but are not the most correct values.


Also, all the image details need to be preserved for improving the computational usage in a later stage.

this research is focused on predictive-corrective coding filters with entropy encoding (i.e. Huffman coding) and apply these on the raw image sensor data to compress the huge amount of data in a lossless manner.


As the image sensor will transmit the 2D image in a pixel serial order (i.e. left to right for each row and from top to bottom), a prediction can only be done for the next pixel in line.

none of the future information (i.e. on the right and below the current pixel) can be used, unless there is a framebuffer.


Meanwhile, the LEA will encrypt all candidate jmp destinations and triggers jmp decryption while executing jmp instructions, but some instructions at candidate destination addresses of jmp may also be executed sequentially (e.g. do-while or if-statement alone) without being the destination of the jmp.

recent research aim at balancing the tradeoff between security and such overheads [8-12] by revising the software or modifying processor’s instruction set architecture (ISA).


The simulation results show that the false negative rate is less than 1%.

attackers often overflow the stack to modify the return address and then chain the gadgets to launch a ROP attack.


The most general solution is control-flow integrity (CFI) [7] approach, where the control flow graph (CFG) [7] of the program is generated during compilation and is enforced at run-time [11].

this has high memory and performance overheads that make it impractical in many applications.


Dynamically updating the key would make the attack be harder since attackers must focus on each chip to launch an attack due to the uniqueness of PUF key for each chip, and even though the attackers can get the key luckily, but the key may be updated at regular intervals.

a successful attack on a chip cannot be easily applied to another one due to the dynamic key.


the first task of EDU is to encrypt return addresses and some bytes of the first instruction at jmp destinations.


In this work, we consider interconnects as groups of patterns belonging to different classes of frequently used layout pattern shapes.

the full-chip reliability analysis can be carried out by independently evaluating the dielectric breakdown of interconnect patterns existed in the layout.


The x-coordinates of the modules are well defined by the tree structure, starting from the root node n1 whose bottom-left coordinate is (0, 0).

no published work achieves the optimal time complexity for general geometrical constraint handling and module packing.


CB-trees augment B*-trees with the corner stitching to provide a comprehensive system for analog placement problems.


In addition to neglecting the PBTI effects in nMOS transistors, the mathematical model itself is not able to consider the slope of rise and fall signals of a cell.

this method fails to analyze multi-stage cells (e.g., buffers, flip-flops, etc.) and multi-gate paths.


Note that the obtained C P delay here is already in the presence of aging and hence no additional guardband needs to be applied.

the included guardband can be computed as the timing difference between analyzing our design with the initial (i.e. degradation-unaware) and degradationaware libraries.


As illustrated in Section 2, the path that was initially (i.e. before aging) critical may not remain critical after aging.

both aging-aware and aging-unaware designs will operate with no (required or contained ) guardband.


This work considers a 512-bit cache line consisting of eight 64-bit words.

size of our meta-data (i.e., zero-flags and energy-flags) is 16 bits (2 bits/word).


In practical systems, N-point DFT is usually performed with the Fast Fourier Transformation (FFT) algorithm, which enables significant reduction in computing complexity from O(N2) to O(NlogN).

from the perspective of hardware design, the computation-intensive FFT is still a resource-hungry block since an N-point FFT requires 0.5NlogN complex multiplications and NlogN complex additions, which cause very high hardware resource consumption in large N cases.


Figure 8: Comparison of .ne-grained (per set) and coarse-grained (global) rationing for symmetric co-runs.

if resets are too infrequent, protection dominates sharing.


We have tested an extension of this policy for multiple cache-sharing programs.

for each program, the determination of the hint bit is based on its ration size r.


They show that symptoms are more prevalent in failed devices.

a large fraction of healthy devices have no symptoms, and even if the symptoms occur, they are very mild in intensity, e.g., 80% of healthy devices have fewer than 2 reallocated sectors.


There is a higher likelihood of the symptoms (captured by SMART) preceding SSD failures, with an intense manifestation preventing their survivability beyond a few months.

our analysis shows that these symptoms are not a sufficient indicator for diagnosing failures.


The reason is that industry is urgently exploring beyond-silicon and beyond-CMOS device, interconnect and memory options, as well as heterogeneous, More-than-Moore integration and packaging technologies, in order to maintain Moore s-Law scaling of integration value.

silicon photonics stands out as the most promising technology to overcome the limitations of electronic interconnects as the system scale increases.


In this section, we evaluate the proposed method with the dataset collected from households with simple sensors and user-generated activity labels.

we focus on the question whether the unknown activity classes are correctly estimated.


The off-line training cost is very high.

they require a large number of training data of each previous program (e.g. Khan et al. [9], Guo et al. [12] and Dubach et al. [10, 11] require 1000, 500 and 512 training instances of each prior program, respectively).


Inspired by the recent advances of transfer learning, we propose a transfer learning based DSE framework TrDSE to build a more efficient and effective predictive model for the target program with only a few simulations by borrowing knowledge from previous programs.

trDSE includes two phases: 1) clustering the programs based on the proposed orthogonal array sampling and the distribution related features, and 2) with the guidance of clustering results, predicting the responses of configurations in design space of the target program by a transfer learning based regression algorithm.


TrDSE is much more efficient than PSM and EAC to achieve a similar prediction performance, as TrDSE only needs less than one fifth simulations of PSM and one third simulations of EAC.

trDSE could dramatically reduce the simulation time in DSE.


Moreover, even in case a wearer can choose a size that perfectly fits, the pressure reduces over time and the original effect is lost.

a pressure sensor and a measuring equipment that can correctly evaluate the pressure on each part of an individual's leg need to be developed for adequate use and investigation.


Each semester, full-time students received a $25 printing allotment and part-time students received a $15 printing allotment We used a networking tool provided by HP to notify the help desk of paper jams, low toner, paper outages and maintenance needs.

printing was both free and unmetered printing was not tracked at all.


In [3], the authors use the EEG evoked potential to issue movement commands.

the geometrical shape of the interface can be circular or rectangular, while the number of directions can be 4 or 8.


Furthermore, these systems are not portable, they can only be used in particular spaces which the systems have been set up.

these kind of motion capture systems are not suitable for daily activities monitoring.


Otherwise, the authors of [25] highlight the importance of efficient utilization of renewable energy sources within Cloud computing platform.

to cope with the complexity, the authors introduce a fuzzy logic based on heuristic for GLB which improve the overall cost and the renewable energy utilization.


The fact of introducing the fuzzy control theory into resources scheduling, enables us to optimize the overall performance.

this methodology makes it possible to reduce at the same time the response time, the processing time and the cost.


This business model has the particularity to offer unlimited capacity to final users.

we highlight different categories of Cloud based on deployment models or service models (see Figure 1).


These aspects are mainly, the security and the performance.

performance optimization has been a strategic weapon in multiple scientific and industrial areas.


The maximization of this GPI allows us to achieve the best response time and processing at low cost.


The scheduling methods in distributed systems aims to share the load on different processors and enhance their utilization while reducing the total task execution time.

task scheduling is identified as combinatorial optimization problems which could increase the performance of the system.


For instance, it can hold a component firmly while the human is performing an assembly task.

copyrights for third-party components of this work must be honored.


validating personas in this manner became tricky, as interviews elicited powerful emotional responses from participants, necessitating caution.


These operations are essential to modern multimedia and signal processing engines, and form the basis of several industry standards [2].

the scope of approximations in this experimental evaluation is restricted to floating point division only.


Architectures such as the proposed evaluation system can hence become essential for automatic performance analysis and style judging systems in future.

a well-balanced data base for the subsequent machine learning task could not be ensured.


In this work, we presented a human activity recognition system for wearable motion sensor data specialized in the error classification of ski jumping motions.

we developed a multi-dimensional convolutional network model based on the idea of a three-dimensional motion image connected along the temporal, skeletal and sensor domain.


Deep one-dimensional CNNs were demonstrated to outperform conventional classi.ers on sensor data from activity recognition data sets [20, 22].

they are not known to have been compared to a multi-dimensional network as proposed in this work.


Moreover, it offers the chance to considerably enhance the credibility of judged sports known to suffer from biased evaluation [28]: to prevent controversies and allegations of subjectivity or even fraud, it is reasonable to include objective measures whose output cannot be manipulated in the final performance scores.

the creation of autonomous machine intelligence that retrieves and classifies style information from an easily accessible stream of motion data appears an important future issue in affected sports.


On the other hand, the ball speed estimation shows slightly better results in comparison to existing methods like [15] or [16], which achieve an overall speed accuracy of 70 % to 85 %.

for all results the standard deviations are clearly higher than the mean values, which indicates a high error distribution.


Since the friction coefficient is always high enough, the ball will usually roll during the impact.

the sliding case was not considered further.


Data was stored on an integrated memory and later processed for characterization of bowling deliveries.

it is not possible to instrument a table tennis ball due to its very low weight.


For that, we needed a known resting point in the world frame, but only had inertial data in the local and moving racket frame.

the intention of this approach is not to provide an exact description of racket movements resulting in accurate ball properties, but to proof that it is possible to apply different assumptions and simplifications for unknown occurrences to estimate the ball speed and spin shortly after impact.


In particular, transient HR increases caused by walking activities happen to be similar to 1st HR peak, and causes incorrect recognitions.

heart rate data around walking duration is removed.


Preprocess Heart rate data is preprocessed to reduce temporal noises caused by various physical and psychological factors.

transient HR increases caused by walking activities happen to be similar to 1st HR peak, and causes incorrect recognitions.


Still, hardware design is also more challenging, simply because it is bound to interaction with physicality  which can change drastically during the lifetime of a system.

it could have been the case that the transmission characteristics were rougher than in previous tests.


Still, hardware design is also more challenging, simply because it is bound to interaction with physicality - which can change drastically during the lifetime of a system.

a software system uses standardized interfaces to the world, which dramatically reduces possible problems and errors.


This proved to be difficult for the younger children, and expected to be even more so for children with compromised motor abilities.

in the subsequent design we require only a single press to activate the recording, while its termination is done automatically by detecting silence longer than 500 milliseconds.


Hence it is interesting to understand what exactly can be enforced under this black box constraint.

essentially EPxor (C) will now be a program that echoes inputs on outputs, and hence it is a secure program.


Edit automata are similar to our approach in that they offer a black box mechanism capable of monitoring and/or editing the input/output behavior of programs.

to enforce infinite renewal properties, they have to buffer program actions  something that is undesirable for reactive programs.


Student feedback indicated that there were problems.

student responses on a post-class survey revealed that students felt that the exercise was worthwhile and that it increased their interest in cybersecurity education (one-tailed t-test found ratings well above neutral p < .01).


This workshop uncovered several issues with remote configuration and set up of the infrastructure, that were subsequently fixed.

some exercises clearly involve networks and subnets.


Traffic of these clients can be closely monitored and forecasted.

attack prediction module can be implemented at any of these locations -(i) only victim end (ii) only upÂstream defense nodes (iii) both victim and upstream defense nodes by splitting the functionalities.


When a transmission is corrupted, the sender is aware of this event and it sends a rewind symbol ‘←’ on the next time it has the right to speaks.

when the order of speaking is fixed (say, alternating), the parties “lose” one slot: while we would like the sender to repeat the transmission that was corrupted, the receiver is the next party to speak after the round where the ‘←’ symbol is sent.


So far, perfect profiling was assumed in the previous subsections.

the computation is more time consuming and the solution cannot be written in a simple algebraic equation.


The definition does not demand that a security-mechanism actually does render the duplication more difficult, but only that an implemented mechanism is meant to do so.

a classification of such architectures as two independent security and storage architectures is more appropriate.


For quantum-token based PUFs [11], the security objective D2 is reached via proving that the s-challenge is necessary to extract the previously stored information.

this PUF prevents mathematical duplication with the help of the NC mechanism and cryptostorage with the EUR mechanism.


In an attempt to construct two-pass leakage-resilient AKE protocols based on the eCK model, three models and protocols have been proposed: The first formalization was the Moriyama-Okamoto (MO) model [8] which allows bounded amount of leakage.

adversary: The adversary M is a probabilistic polynomial time (PPT) algorithm which controls all interaction and communication between parties.


For efficient data management and economic benefits, organizations are increasingly moving towards the paradigm of database as a service" by which their data are managed by a database management system (DBMS) hosted in a public cloud.

we observe that there is an overall increase by 44% on the server side.


By outsourcing data to the cloud, organizations save the cost of building and maintaining a private database system and have to pay only for the services they actually use.

organizations are increasingly interested in the paradigm of "database as a service".


Further, in such schemes achieving forward and backward security requires only to change the public information and does not affect the secrets given to existing subscribers.

bGKM schemes do not support group membership policies over a set of attributes.


Samanthula et al. [21] propose an approach that relies on homomorphic encryption and PRE to handle user revocations without requiring re-encryption of relational data and also supports expressive policies.

such approach incurs a heavy cost on the end user as all processing is done at the client side since the server does not perform secure query processing.


There are plenty of open sources towards how to use motion sensors to infer position of smartphones publicly available on many websites.

attackers can easily get those code and add them into the repackaged app to make the stealthy picture taking triggered by motion sensors.


for version 4.1.2 phones from 5 vendors, the success rate of transplantation attack is 75%.


They cannot be used outside their definition class.

starting at the connect function does not work, and we should look for another start point.


This thread can know when and which API is called, and can get the caller s UID (user ID) and PID (process ID).

through this thread, Android API auditing can be easily done.


It may be considered that a camera indicator light may be shown when taking pictures.

all the experiment phones used by our labmates (see Table 3) do not show it.


They mainly focus on understanding security risks in vendors' customization process; and their attack is inspired by a security flaw that vendors have mistakenly configured the camera device node with permission of 666.

at the beginning, our focus is to construct a transplantation attack to evade API auditing.


To avoid the second defence, the attacker could use a standard picture-taking app instead of QR-code scanner app to add spy-on-user code.

as the malicious app is already set as a member of the camera group.


At last, attackers can submit the repackaged app(s) to, e.g., third party markets to distribute it.

privacy-harming pictures can be taken by the malware without the Android API auditing being aware of it.


For the convenience of test, we let the malicious app show the preview window on the screen.

to check whether a phone's screenshots (generated by the test platform) contain the preview window or not, we can verify whether the picture taking is successful or not.


Second, the image data may exist in the kernel space since the camera driver runs in the Linux kernel, and native code running in the user space cannot get the data.

there are several message types enabled in the mediaserver process when taking a picture.


The difference between the two is that the first one compares all signatures with each page of memory, whereas the second one scans memory byte-by-byte, reading 32-bits at a time, and identifies more relevant signatures that can be matched with the page.

we would expect the second approach to be more efficient for working with a large number as it shifts the primary dependence of processing time from the number of signatures to the size of pages.


Unlike prior work, which relies heavily on deep manual analysis and results in fragile methods that are not guaranteed to work on newer versions, CodeIdenti.er presents a fully automated solution that is fast, accurate, and robust.

second, it identifies the kernel code the PGD is used to make clusters of the similar read-only pages, assuming that the kernel-code pages are read-only for code protection.


Conceptually, the filtering does not alter the asymtpotic complexity–in the worst case, all signatures could end up in the same set.

under the assumption of relatively uniform distribution of the O-P keys (which we have observed empirically), it does reduce the number of signature comparisons by a substantial constant factor.


Since data structure definitions vary across operating systems, Siggraph can be used for OS .ngerprinting.

the only reliable approach is to directly examine the physical memory of the VM.


This special case can be detected by simply keeping a crypto hash of the page, and depending on use case turn hash-based page matches on/off.

the baseline version starts much lower but rises at a much steeper angle than the second algorithm, which filters the candidate signatures before comparison; the crossover point is around 1,000 signatures.


Several approaches are proposed to automate the triggering of UI events, from random event generation [32] to more advanced approaches like AppsPlayground [39] and SmartDroid [48].

all of them still have many limitations on the type of events they can handle and the coverage.


StaDynA extends the initial MCG generated with a traditional static analyzer with the information detected at runtime.

if an application exposes dynamic behavior all mentioned approaches can benefit from the expanded MCG obtained with StaDynA.


These ellipses show the cases when the MOIs are resolved and corresponding nodes and edges are added to the MCG.

the client side can run either on a real device or on an emulator.


One may attempt to distribute the dataset into multiple hashtables across several machines and coordinate the nodes to compute set intersections for leak scanning.

such a system is nontrivial to implement from scratch and has not been reported in the literature.


One collection consists of shingles obtained from the content segment and the other collection consists of shingles from the sensitive sequence.

to compute the intersection rate of two fingerprint collections Irate, we design two MapReduce algorithms, Divider and Reassembler, each of which has a map and a reduce operation.


If the sets are relatively small, then a faster implementation is to use a hashtable to store set A and then testing whether items in B exist in the hashtable or not, giving O(n + m) complexity.

section 4 presents the security analysis of our approach especially on the con.dentiality of sensitive data.


We group the nodes that are closest (in terms of number of hops) to one another into an anonymity set.

given an anonymity set S, we have an ordering of them d1, . . . , d|S| such that di and di+1 are one hop from one another


For example, consider an alternative to source-routing, which is table-based routing, but with shortest-paths.

the client does not provide a route; rather, the nodes in the wireless sensor network are capable of routing by themselves.


We do not constrain the attacker A in any way other than to require that it is an algorithm.

the attacker may have access to any information he wants before he starts the game (see, however, the caveat in the next paragraph).


In MakeLeftHeavy, we reorder the children of every node so that they are ordered left to right in non-increasing height.

the leftmost child has the maximum height amongst all the node's children, the next child to the right has height at most the height of its left sibling and so on.


Presumably, the client has placed that node in the same partition as the two nodes colored blue.

the client queries all three nodes when it intends to query the node shaded black only.


Our particular intent with the empirical evaluation is to validate the assertions on sufficiency in Theorems 4 5, 7 and 8.

we simulate the DAS protocol, measure the communication-cost it incurs in various settings, and observe that it is indeed upper-bounded as the analytical assertions tell us.


Clustering is executed on the set of flows that will be used to build the training dataset.

after performing the clustering the training dataset will be composed as follow.


In this section we describe our framework.

section 3.1 introduces the pre-processing steps that allow us to model the network traffic.


In the last years, several concerns have been raised about the capabilities of those portable devices to invade the privacy of the users and to become actual tracking devices .

the median value and the third quartile have been used as thresholds to limit the maximum length of the generated time series.


However, often times intrusions on the database level are not properly reflected in the network or OS level [11].

a few intrusion detection systems have been proposed that uses the database audit trails (i.e., SQL query trace) to identify an intrusion against the underlying DBMS.


We generate our queries in such a way that any query on T P is equally likely.

our query generation procedure is unbiased.


However, these queries would be easily detected if they are evaluated with respect to the context they are submitted to the database.

they would be detected by a DIDS which takes into account the previously submitted queries.


Role threshold values greatly depend on the query behavior of the users of the corresponding role.

we propose the following heuristic-based threshold generation in this paper.


A valid user, on the other hand, have incentives to access both sensitive and insensitive parts of the database.

a database intrusion detection system, when equipped with the knowledge of data sensitivity values, is more likely to distinguish a sequence of anomalous database accesses from sequences of valid accesses.


However, the query access pattern of an intruder largely depends on data sensitivity.

an IDS should take into account data sensitivities to isolate intrusive queries from the valid ones.


This is because, it is usual for Jane to submit queries to retrieve customer account information.

these queries would be easily detected if they are evaluated with respect to the context they are submitted to the database.


Android applications are formed by logically separated components that mainly communicate with each other through Intents, which carry data and request the execution of a procedure to another application.

the Android Intent Passing mechanisms do not provide the receiving component with any information concerning the origin of an intent, thus facilitating the creation of spoofed intents with malicious input data [1, 2].


One of them is a method by Sawamura et al. for personal identification in which individuals are identified by four types of verification with a multi-touch panel [8].

the method has a problem that paths by fingers can be traceable by fingerprints which remain on the special panel since the panel is never touched for purposes except personal identification.


When the finger horizontally moves plus one millimeter at the first trial, and it horizontally moves minus one millimeter at the second trial, the average is zero although the standard deviation is not zero.

we eliminate the value of the characteristic from CVK when the value of the average of the characteristic is zero.


In this chapter, existing researches in which characteristics of personal actions are used for personal identification are introduced.

m is narrowed, if characters for a password consist of the past candidate characters.


Some of the characters for the password is presumable when attackers did not gaze at the screen since the arrangement of software keys is fixed and passwords are usually short for convenience.

we proposed a method for enhancement of security of password lock for smart phones by applying the comparison of personal characteristics when passwords are inputted with flicks.


However, they choose ten most effective gestures for their method.

two hundred trials are much enough to break their personal identification method since twenty trials for one gesture is required and there are ten gestures.


Candidate characters for password decrease according to the increase of the number of registered users.

we renew the method by using double stage C.V. filtering in order to solve the problem [4].


The number of recommended characters for password is shown in Table 2.

fSi-1 is almost equal to FSi and GVi-1 is equal to GVi.


There already exists open source software that allows for multiple keys per access to one file.

both user A s key and user B s key can decrypt their corresponding symmetric keys with the same result.


The first party would be the DM, preferably an always-on desktop computer secured with the enterprise; the second party would be the DC, a mobile device that would need access to cloud-based data from any location; and the third party would be a third-party Keying as a Service Provider (KaaSP).

our proposed system does allow for a threshold of at least 2 parties with minimal overhead.


Larger keys, however, will not solve all the problems because as more devices can handle sufficiently large keys, and more employees migrate their work to mobile devices such as smart phones, the total number of keys that an organization has to manage may continue to increase.

even though more devices will be able to use longer key lengths, the total number of keys may also become unmanageable for businesses as each employee's device is given its own unique key.


As mentioned, portable devices are becoming more popular, and computing power is increasing.

we suggest that access of the files is within a bigger framework that allows for easy and instantaneous return to the work environment upon reauthentication.


Because, it is for a Vary header returning the contents which change with kinds of User-Agent.

the public key for creating the Bloom filter which stores a user's ontological kind and numerical value is required N.


Moreover, the number of crimes on Internet increases according as Internet spreads.

a system for identification of users is required by specific administrators.


That is to say, users must be identified or grouped by specific administrators while their anonymity must be assured for the third party.

we propose a method in which information of users' favorites is encrypted and stored in HTTP request header using a Bloom filter.


On the other hand, the pursuit measure with cookie can discern client computers without depending on IP address.

website operators, Internet advertisement distribution contractors, etc. use the measure for acquiring detailed access histories of users.


We expect the ASR performance to be higher when adapting the recognition dictionary to the exact vocabulary (including nonsense speech) of the CAPTCHA.

this would increase the attacking costs considerably as it requires a large number of labeled CAPTCHAs.


To be able to perform the required number of observation attacks, we randomized pattern generation and simulated user input.

some real-world factors were not considered.


In addition, our perception analysis indicates that more complex patterns are perceived hard to enter.

we assume that "special moves" like overlaps and knight moves are hardly used in the wild.


If the time window is enlarged to 15 minutes, then 99.8% of HTTP requests and their dependencies are included.

the HTTP requests with dependents are temporally close to each other, despite some rare cases.


Compared with the original view, our condensed view significantly reduces the redundancy of displaying leaf nodes.

it helps users identify abnormal nodes due to its visually salient.


Their main drawback is that, given the enormous number of different traffic types of interest, building a well-defined profile encompassing all normal traffic is extremely difficult.

they suffer from high false alarm rates.


Since UBM is trained on a large pool of data, one expects that a higher number of components could lead to a more precise model.

when the number of components rises tight, we may have no access to enough training data for some of the components.


In the present snippets, we have inserted an attacker action between the two relevant defender operations.

we have also identified several small changes to the POSIX API that would make it easier to write race-free code.


In this case, the PATHR E S call would fail to open the file, also indicating a race.

no matter what the attacker does, he will be detected.


This analysis indicates that the FileObserver based light monitoring malScan lacks comprehensiveness.

all 30 tested AVDs have designed the heavy sweeping malScan operation, which is a comprehensive malware scan.


Bearing this assumption in mind, we would like to understand if there are still deficiencies in the malware scan (malScan) mechanism itself that can cause potential hazards.

our research sheds the light on the importance of taking the secure and preventive design strategies for AVD or other mission critical apps for fast-evolving mobile-systems.


In this way, Fsetup always knows from which participant a message comes in, and to which participant a message is to be sent to.

for participants and their algorithms, there is no guarantee that the “plugging” and/or the input-manipulation runs correctly.


In order to ensure that the VOIP services are always available, the iOS system will relaunch the VOIP app in the background immediately after system boot.

unless the customer terminates the app manually, the app can always monitor phone call events even after rebooting the device.


Note that because there is no app review process for enpublic apps, the app can use any dynamic loading techniques (e.g., NS-Bundle and dlopen()) to load the private frameworks at runtime.

in addition to checking the static links of frameworks, iAnalytics also analyzes the dynamic loading behaviors at runtime.


Although IOKit framework does not belong to the private frameworks, there is no public API calls in this framework.

any API calls in this framework also belong to private APIs.


Although ad hoc distribution has a 100 device install limit, hackers can rename the Bundle name of the app, iTunes will then treat the renamed app as a new app with another 100 device limitation.

hackers can use this method to attract customers to download free pirated apps which are not free in Apple Store from their third–party markets, and then use advertisement to gain money.


Cloud application marketplaces of modern cloud infrastructures offer a new software deployment model, integrated with the cloud environment in its configuration and policies.

similar to traditional software distribution which has been suffering from software piracy and reverse engineering, cloud marketplaces face the same challenges that can deter the success of the evolving ecosystem of cloud software.


The selected disk image is then written to the virtual disk of the VM, so the application can be used by the cloud users.


Our binary rewriter enforces the same set of rules as Native Client (NaCl) [38, 48].

instruc tions are grouped into equal-sized bundles (16 bytes), and indirect branch instructions such as indirect call and return must target the boundary of a bundle.


It then retrieves the bytecode of the method to decode and execute it.

dex sandbox is implemented in the Java and C++ programming language, while native sandbox is implemented in C and the ARM assembly.


specifically, bytecode rewriting-based approaches insert inline reference monitors to regulate apps behaviors.

dynamically loaded classes (e.g., classes loaded by DexClassLoader) could pose serious challenges to these systems since the dynamically loaded bytecode is not available when statically rewriting the app.


This trend is accompanied by the vigorous increase of third-party Android apps that are available for users to download and install.

recent studies reveal that third-party apps, including popular ones, could leak private information without user consent or awareness [12,19].


It costs about 3.9 seconds in total for this app to complete.

the average time for each policy retrieval is about 0.39 millisecond.


Based on the recent surveys [5, 14], the total number of IP blocks in a full circuit is around 80 on average.

we partition each benchmark circuit into 80 blocks, where the size of each block is slightly different.


And the cost of each simulation is in proportional to the size of circuits, i.e., the number of gates and interconnects [25].

on a modern PC with an Intel 3.6GHz CPU, it takes nearly an hour on a circuit with about 25, 000 logic gates to perform 64, 000 Monte Carlo simulations [7].


Usually, we need two separate proofs that prove the security of SBE scheme under two different modes, Select-mode and Cut-mode, respectively.

we found that these two proofs has too many similarities according to the comparison result in Table 1.


Without doubt, the data mining-as-a-service benefits business intelligence.

there exists a serious privacy issue in the paradigms, that is, the server has access to the data of the company and may learn business secrets from it.


Consequently, it is only possible to have a fast and complete addition law when a = -1 is a square in the underlying prime field Fp, which is the case if and only if p ≡ 1 mod 4.

a MoTE curve can only be generated over a prime field Fp whose order is congruent to 1 modulo 4 [6, 16].


In 2004, Gura et al [7] published a now-classical paper in which they demonstrated that, in contrast to conventional wisdom, strong PKC is feasible for small battery-powered sensor nodes.

they showed that Elliptic Curve Cryptography (ECC) [8], when carefully implemented and optimized, is computationally less costly than was believed at that time.


A serious attacker would never attempt to break the ECDLP in a 160-bit group as he can get the secret key in a much cheaper way via reverse engineering.

we decided to use elliptic curves with orders of about 2160 and 2192 ; both orders are well established and supported in the WSN research community.


All previous implementations of ECC for MSP430 processors used either a conventional Weierstraß curve (e.g. [20, 23, 27]) or a Montgomery curve of unreasonably large order (e.g. [10]), both of which wastes execution time and, thus, energy.

our software supports Montgomery and Edwards curves over a 159 and a 191-bit prime field, which represents a good compromise between performance and security.


SafeCurves requires f to be at least 2200, in which case computing the ECDLP is infeasible with today's technology.

a so-called pseudo-Mersenne prime has the form p = 2k - c where c is small in relation to 2k; typically, c is chosen to fit into a register of the target processor.


Public key based protocols [1, 2, 10] enables the verifier to verify arbitrary anonymous groups without overwhelming computational cost.

low-cost passive tags usually cannot afford these protocols due to the extensive computation requirements and therefore, we do not consider this type of solutions as it is rather expensive and impractical.


Second, the use of SYN proxy limits the number of connections that can be forwarded.

the maximum number of connections forwarded to a specific {I P, port} pair is 64513 (see Section 4.2).


Indeed, as discussed in Section 4, while being an effective mechanism to protect against SYN flooding attacks, proxying introduces several problems which derive from breaking the end-to-end paradigm.

its use should be limited as much as possible.


Note that, according to TCP protocol specifications [5, 13] each ISN is computed in a non-predictable way.

it is impossible for R to predict the ISN that B would generate and, as a consequence ISNR will be different from the sequence number B will use.


Breaking TCP end-to-end semantics introduces the need to store state, which in turn opens the system to attacks exploiting buffer saturation.

there is a strong need to reduce its use as much as possible while retaining its beneficial effects against control plane saturation attacks.


This number can be quickly reached if we consider extremely popular HTTP services (e.g., Google or Facebook).

for completeness, we compared the average overhead introduced by Avant-Guard with the overhead introduced by LineSwitch, evaluating both a scenario without attack, and a scenario under SYN flooding based control plane saturation attack.


For instance, our observation indicates that read and write are among the most frequently used system calls.

a process must first open a file before it could perform read/write operations on the file, and the usage of open and close system calls are over an order of magnitude less.


A popular way to find the period from data sequences is via Fast Fourier Transform (FFT).

the IT group is responsible for managing computers in the classrooms, faculty offices, and student laboratories.


E-Autocorrelation shares the same property with the conventional autocorrelation, that is, when a periodic event sequence is shifted with a lag that is exactly a multiple of the period, re achieves its maximum.

e-Autocorrelation is suitable for periodicity detection in event sequences.


Note that in a perfectly periodic sequence, E-Autocorrelation values as 1 indicate periodicity.

since the event sequences could be noisy, choosing smaller values than 1 as peaks provides a chance for our approach to better tolerate noises and thus remain robust.


For category I processes, because of their complete idleness, the constraining will be in effect immediately.

any system call from these process will be considered as anomaly and thus will trigger manual intervention.


In this work, we simply choose to design a simple model based on system call instrumentation only to illustrate that idling processes can be easily constrained.

we intercept all system calls of the target idling process, and build its “idling behavior” profile, which comprises of the variety of system calls as well as their calling context (CC) [36].


As shown in Figure 2, The Delivery Mode (DM) of the I/O redirection table can be configured as SMI instead of Fixed normally.

we are able to deliver an SMI to the CPU for every keyboard interrupt; that is, every key press causes our code to execute in SMM.


Note that the transmit queue may become empty before finding the login packet, so we may miss the first transmit descriptor that arrives at the empty transmit queue.

we insert a transmit descriptor whenever the transmit queue becomes empty until identifying the login packet.


Then, we enable TrustLogin and login to the FTP server again.

the password recorded by the keylogger has been changed to a random string generated by TrustLogin.


As stated in the paper, higher frequency of polling may affect the proper display of the graphics, and the user may notice the abnormal event.

trustLogin is able to defend a GPU-based keylogger as long as the polling interval does not pass below 15 microseconds.


Physical layer message integrity protection and authentication by countering signal-cancellation has been shown as a promising alternative to traditional pure cryptographic message authentication protocols, due to the non-necessity of neither pre-shared secrets nor secure channels.

the security of such an approach remained an open problem due to the lack of systematic security modeling and quantitative analysis.


Through correlated jamming, the attacker has the potential to modify/cancel any signal in wireless channel, and the message integrity will not be protected.

it is essential to investigate the possibility of signal cancellation in the real-world, so as to provide quantitative security guarantees.


Observe that in Game 1, all oracle outputs are not related to r * .

the encryption oracle does not help the attacker to win the game.


This paper presents a novel deanonymization attack on Tor that exploits a fundamental weaknesses of low-latency anonymization networks.

we show that an attacker capable of providing web content to users, e.g., through banner advertisements or cross-site scripting, is able to deanonymize users via a sidechannel attack.


Several authors demonstrated the effectiveness of such attacks [6, 9].

the security of Tor is based on the use of strong encryption and the large number of relays that can be used to establish a path, thus significantly lowering the ability of an attacker to easily eavesdrop a communication or link senders and receivers.