sadat2307/MSciNLI huggingface dataset:
Domain: Networks
Sentence 1: For example, in ZigBee devices, the packet-level RSSI information is sampled at only 31.25KHz, while the phase­shift is obtained at 4MHz by the ZigBee PHY for (de)modulation.
Sentence 2: the throughput of packet-level CTCs is inherently bounded by a low sampling rate (e.g., KHz) in contrast to hundreds of Kbps for native ZigBee communication.
Relationship: entailment
Domain: Hardware
Sentence 1: Our solution is to maintain the invariant that channels never contain more information than what is con­tained in the abstract values they are paired with.
Sentence 2: at the top of the combination of domains, when we manipulate a pair (ab, chan) of an abstract value and a channel, we will make sure that γ(ab) ⊆ γ(chan) holds.
Relationship: entailment
Domain: Hardware
Sentence 1: Data locality affects the performance of locality-oblivious GC with a given implementation (i.e., GRA with a fixed d): (1) cleaning cost increases when either the active region size or the skewness increases, (2) the increase is more pronounced for a smaller window size.
Sentence 2: data locality has the most significant impact on GREEDY, but has no impact on RANDOM.
Relationship: entailment
Domain: Hardware
Sentence 1: Since it is a general consensus that cleaning cost of GC algorithms may be reduced when data can be differenti­ated [11, 14] and a workload includes n + 1 types of data pages, it is of interest to study the performance of GC that exploits data locality using data grouping, which differenti­ates different types of data pages and stores them separately in different regions in an SSD.
Sentence 2: we analyze how data grouping influences the performance of GC in SSD, and how much is the influence for workloads with different degrees of locality?
Relationship: entailment
Domain: Hardware
Sentence 1: Whilst, on the surface, it would appear that constraining the insertion process to use only spare resources that were left behind may be overly restrictive, significant flexibility is recouped from exploiting the convenient property that debugging signals can be connected to any trace-buffer input for it to be observable.
Sentence 2: unlike the user circuit, where nets need to be routed exactly from a single source pin to a predetermined set of sink pins, debug nets need only be routed from any point along the existing user net to any one of the many trace-buffer sinks that are available.
Relationship: reasoning
Domain: Hardware
Sentence 1: Another area that we would like to pursue is to explore ways to effectively insert the violation detector (XOR) logic which compares the value in the user register with the shadow register.
Sentence 2: this detection logic (and any downstream infrastructure) has the freedom to be placed anywhere on the device, as long as it does not extend Tcrit ; however, because this operation is a pairwise reduction (i.e.
Relationship: entailment
Domain: Hardware
Sentence 1: As shown in Figure 15, for a conventional FPGA-based convolver, the execution time increases with input vector size almost exponentially, which indicates that the execution time will be exceedingly long when the input vector is long.
Sentence 2: once again, all circuit components in Figure 8, except all necessary resistors, can be readily found in our targeted programmable analog device, PSoC.
Relationship: neutral
Domain: Hardware
Sentence 1: Importantly, ring semantics dictate that (1) the driver work through the ring in order, one descriptor after the other, and that (2) the I/O device process these descriptors in the same order.
Sentence 2: iOVAs are short-lived and the sequence in which they are used is linearly predictable: each IOVA is allocated, placed in the ring, used in turn, and deallocated.
Relationship: reasoning
Domain: Hardware
Sentence 1: This shortfall is primarily rooted in the analog IC design problem itself, which is very much more complicated even for small problem sizes: it deals with a large number of specific circuit classes; it requires a customized design approach for each circuit class; and analog circuits are very susceptible to noise and process variations.
Sentence 2: the work and costs involved in producing analog layout is a serious bottleneck in IC design, despite numerous attempts at automating the process.
Relationship: entailment
Domain: Hardware
Sentence 1: If an I/O device supports single-root I/O virtualization (SRIOV), a VM is able to issue I/O instructions directly to the device in a way that is isolated from other VMs, and therefore VM exits are avoided when I/O instructions are issued.
Sentence 2: this is achieved through careful installation of timer interrupts that the hypervisor sets up on a dedicated core and migration of timer interrupts that a VM sets up when the VM is suspended and migrated.
Relationship: neutral
Domain: Hardware
Sentence 1: This observation about pure movement and fine motor parts of the overall task has an impact on the Fitts’ index of performance, and index values (3) and (4) may signi.cantly difÂ­ fer, depending on the task.
Sentence 2: the observation that the overall task can be divided into different parts implies that those indices are not competing - they are simply conveying different information.
Relationship: contrasting
Domain: Hardware
Sentence 1: When multiple TSVs are present, we assume the TSV and silicon substrate are linearly elastic structures, then according to the stress superposition principle explained in multiple papers [8, ?, ?], the stress coming from several different bodies is the sum of the stress applied separately.
Sentence 2: the stress value at a certain point is the accumulative TSV-induced stress caused by each TSV: .
Relationship: entailment
Domain: Hardware
Sentence 1: Nicolaidis et al. [16] proposed a built-in self-repair method that can be used for on-line faulty TSV recovery.
Sentence 2: in the first experiment, three representative cases of TSV failures, which includes that all TSVs are fault-free, only 1 TSV is faulty, and 2 TSVs are faulty respectively, are considered to verify the function of the proposed scheme.
Relationship: neutral
Domain: Hardware
Sentence 1: The logic low value of Pc11 will cause the Pr21 to be set to logic high value and renders disconnecting between Sginal2 and TSV2.
Sentence 2: hence, in order to improve the yield and the quality of 3Dstacked ICs, several faulty TSV repair strategies have been proposed and typically use the neighboring TSVs to replace faulty TSVs.
Relationship: neutral
Domain: Hardware
Sentence 1:  Additionally, since an application typically processes much more data than the number of instructions executed, most prior cache locking methods, if applied directly to the data cache, would require a large data cache and/or potentially result in runtime overhead in terms of performance and/or energy, since complex runtime analysis wou6 ld be required due to the inherent runtime variability of data caching [21].
Sentence 2: we propose a new methodology for leveraging cache locking for data cache performance and energy consumption optimizations in general purpose embedded systems.
Relationship: reasoning
Domain: Hardware
Sentence 1: Such a structure effectively reduces the transistor numbers of a single TCAM cell to 3.
Sentence 2: all these MTJ-based TCAM designs face a severe design challenge the small difference of MTJ s high and low resistance values (usually only a few KO) produces a very limited sensing margin, which significantly degrades the reliability of TCAM design, prolongs the searching latency and induces extra power overhead.
Relationship: contrasting
Domain: Hardware
Sentence 1: Compared to SRAM-based TCAM with 12 transistors (12T-SRAM) [9], these designs significantly decrease the number of transistors and therefore reduce the cell area [6][7][10].
Sentence 2: the match line (ML) is connected to a sense amplifier in reading and searching operations, while a pair of source lines (SL and SL) are used to supply the programming or searching data.
Relationship: neutral
Domain: Hardware
Sentence 1: Assuming 20% of our post-layout top critical path will be RC-delay and 80% cell-delay, the di.erence between pre-layout and post-layout speedup for 25.C to 125.C, will be 7% lower in 20nm at nominal voltage.
Sentence 2: post-layout speedup as a result of increase in temperature is lower than that of pre-layout.
Relationship: entailment
Domain: Hardware
Sentence 1: To showcase the reconfiguration aspects of our proposal with respect to the volume of faults, we present our gathered statistics in two different sets of graphs.
Sentence 2: the top graph in Fig. 6 depicts the simulation results assuming SRAM pfails up to 10-4 (low-pfail case), whilst the graph in the bottom shows the corresponding results for pfails ranging from 5×10-4 to 5×10-3 (high-pfail case). 
Relationship: entailment
Domain: Hardware
Sentence 1: The BDI method [14] leverages redundant patterns (e.g., zero blocks, narrow values and low dynamic range patterns) exhibited by adjacent data bytes/values within a cache block.
Sentence 2: bDI divides a cache block into several sub-blocks and represents the entire block as two base sub-blocks (a zero sub-block and the first non-zero sub-block) plus the difference information (Δ).
Relationship: entailment
Domain: Hardware
Sentence 1: In contrast, SOCO's compression is dedicated to reducing power consumption in NVMs rather than the traditional goal of saving memory space.
Sentence 2: sOCO leverages a cache-block-level delta-based compression scheme similar to the one used in prior work [14] but utilizes an essentially unmodified page management mechanism to enhance compression effectiveness and reduce over­heads compared with the leading capacity oriented scheme [13].
Relationship: entailment
Domain: Hardware
Sentence 1: For uniform data traffic, the average Hamming distance between the existing and incoming data is the same for mirrored/un-mirrored data.
Sentence 2: fPC and FNW operate only on un-mirrored data; this motivates MNW to take advantage of the possibility to reduce bit-writes using data mirroring, regardless of the success of FNW/FPC.
Relationship: contrasting
Domain: Hardware
Sentence 1: Whereas FPC reduces the cumulative bit-writes over uncompressed data with DCW (area under the curve), FPC concentrates peak bit-writes at bit indices 63, 62, and 61, which negatively affects NVM endurance.
Sentence 2: fNW reduces the bit-writes across all bit indices in comparison to FPC, i.e., FNW is better for NVM endurance in comparison to both FPC and DCW.
Relationship: contrasting
Domain: Hardware
Sentence 1: A review paper on sub-threshold design was presented in [15], in which the authors suggested an ultra dynamic voltage scaling technique, which dynamically scales the power supply voltage to subthreshold operation.
Sentence 2: traditional dynamic voltage scaling techniques restrict the minimum supply voltage to super-threshold operation [16, 17], providing less aggressive power scaling, while ensuring that PVT variations do not become an issue.
Relationship: contrasting
Domain: Hardware
Sentence 1: As described in the previous section, for a given location of the hacker, the orientation of the hacker relative to the user can change depending on the keystrokes pressed by the user.
Sentence 2: for a given pair of antennas at the hacker, while they might show high sensitivity for a pair of keys pressed by the user, the same pair can demonstrate poor sensitivity for another set of keys at a different orientation.
Relationship: reasoning
Domain: Hardware
Sentence 1: Measurement noise and multipath can cause varia­tion in the observed phase of the two streams which in turn causes variation in the observed trough location for the same key press in the case of small delay mismatch.
Sentence 2: as we increase the delay mismatch, we decrease the sensitivity of the hacker and the trough location for a given keystroke is more robust to measurement noise.
Relationship: contrasting
Domain: Hardware
Sentence 1: Some high-end commercially available PCIe flash storage systems are believed to have used the synchronous interface such as Huawei ES3000 [2], which is alleged to provide up to 770K (4KB block) read IOPS performance and up to 630K (4KB block) write IOPS performance.
Sentence 2: there are few publications on design and detailed implementation of flash controllers based on source synchronous interface.
Relationship: contrasting
Domain: Hardware
Sentence 1: We further examined the devices with the largest number of discarded blocks and found that the number of blocks that are discarded is not correlated with the amount of data written to or read from flash cells (examined in Sections 4.1 and 4.2).
Sentence 2: platforms A and B contain SSDs with around two or more years of operation and represent 16.6% of the SSDs examined; Platforms C and D contain SSDs with around one to two years of operation and represent 50.6% of the SSDs examined; and Platforms E and F contain SSDs with around half a year of operation and represent around 22.8% of the SSDs examined.
Relationship: neutral
Domain: Hardware
Sentence 1: We further examined the devices with the largest number of discarded blocks and found that the number of blocks that are discarded is not correlated with the amount of data written to or read from flash cells (examined in Sections 4.1 and 4.2).
Sentence 2: we observe SSDs of both low and high usage across their lifetime (measured by flash cell reads and writes) that have discarded large amounts of blocks and have high failure rates.
Relationship: entailment
Domain: Hardware
Sentence 1: While it may be possible to perform shared memory mappings by modifying enclave address spaces remotely, it would likely be difficult to provide such an implementation correctly, and would at least require complicated and inefficient address space synchronization mechanisms.
Sentence 2: first, the co-kernel architecture used to perform cross-enclave message transfers (which are required for the transmission of XEMEM operations) currently restricts all IPI-based communication with the Linux management enclave to core 0 of the system, and thus the presence of multiple enclaves may cause contention for interrupt handlers on this core.
Relationship: neutral
Domain: Hardware
Sentence 1: In our imple­mentation, we require 7 bits of metadata for each run, where runs can be either 2 or 3 bytes long.
Sentence 2: accounting for the metadata, we need only 2 3-byte runs, 4 2-byte runs, or a combination or 2-byte and 3-byte runs in order to free 4 bytes for ECC.
Relationship: reasoning
Domain: Hardware
Sentence 1: Adopting a high-bandwidth alternative to DDR3-based main memory based on 3D-stacked DRAM, called Hybrid Memory Cube (HMC) [22], helps this situation to some extent, however, the speedups provided by using HMCs are far below the expected speedup from quadrupling the number of cores.
Sentence 2: once the packet arrives at the remote vault, the network interface stores function arguments to the special registers visible from the core and emits an interrupt for the core.
Relationship: neutral
Domain: Hardware
Sentence 1: Adopting a high-bandwidth alternative to DDR3-based main memory based on 3D-stacked DRAM, called Hybrid Memory Cube (HMC) [22], helps this situation to some extent, however, the speedups provided by using HMCs are far below the expected speedup from quadrupling the number of cores.
Sentence 2: if we assume that cores can use the internal memory bandwidth of HMCs2 ideally, i.e., without traversing the off-chip links, we can provide much higher performance by taking advantage of the larger number of cores.
Relationship: contrasting
Domain: Hardware
Sentence 1: Unsurprisingly, ShiDianNao significantly outperforms the general purpose architectures and is, on average, 46.38 Ã— faster than the CPU and 28.94Ã— faster than the GPU.
Sentence 2: the GPU cannot take full advantage of its high computational power because the small computational kernels of the visual recognition tasks listed in Table 1 map poorly on its 2,496 hardware threads.
Relationship: entailment
Domain: Hardware
Sentence 1: When a thread is interrupted while waiting at the barrier, the BARRIER instruction would be at the top of the ROB which results in the core sending a SUSPEND request to the MSA tile.
Sentence 2: unlike locks which will simply dequeue the requesting core, for barriers we send FAIL (or ABORT) responses to all participating cores, i.e. we force the barrier to fall back to software.
Relationship: contrasting
Domain: Hardware
Sentence 1: The difference is largest in 64-core execution of radiosity, where lock synchronization is frequent, but with many low-contention locks.
Sentence 2: this may be an important consideration for processor manufacturers -after adding the synchronization instructions and our MSA/OMU hardware, the processor man­ufacturer can drop MSA/OMU support in future generations of the processor without breaking compatibility with software that uses the new instructions.
Relationship: neutral
Domain: Hardware
Sentence 1: Section 3.1 discusses how SLIPs are used to determine the insertion and movement of a line in a cache level.
Sentence 2: the latency for each operation (evaluating the energy of all the SLIPs and finding the minimum energy SLIP) was found to be 2 processor cycles at a processor clock rate of 2.4GHz and the throughput is one computation per cycle.
Relationship: neutral
Domain: Hardware
Sentence 1: The error detection latency determines how long the tail part of idempotent regions (tail-DMR) should be to guarantee that its execution time is greater than the detection latency.
Sentence 2: the length of the DMR-enabled part is subject to the error detection latency, i.e., a lower soft error detection latency allows a shorter DMR-enabled part (lower performance overhead) but at the expense of more sensors on the chip (higher area overhead).
Relationship: reasoning
Domain: Hardware
Sentence 1: A cost func­tion is proposed for each pre-header of loops to determine whether this pre-header should be selected as a loading point.
Sentence 2: secondly, the false dependency problem is less serious in the iterative ILP approach than in the global ILP approach due to the much smaller size of each y-projection graph of the interference graph, resulting in more eficient utilization of the D-cache.
Relationship: neutral
Domain: Hardware
Sentence 1: Study three will use a design science perspective to retrospectively evaluate current crowdsourcing platform designs to assess the viability of these platforms to support the interests of both services buyers and sellers examined in Studies 1 and 2.
Sentence 2: study 3 will address the following questions: How effective are existing technology crowdsourcing platforms at delivering value to the technology workers and the technology buyers who use them?
Relationship: entailment
Domain: Hardware
Sentence 1: It is posited that the same architectural standards that facilitate distributed intra-firm development, can be used to support crowdsourcing engagements Building on this thesis, Study 2 will explore the awareness, perceived preparation, usage intentions and usage levels of IT crowdsourcing services by IT services buyers.
Sentence 2: study 2 will examine the following research question: What determines enterprise readiness to use technology crowdsourcing services?
Relationship: entailment
Domain: Hardware
Sentence 1: Mobile devices are generally powered by a finite-capacity energy source - a battery, whose size and capacity are quite limited due to the restricted physical size of the mobile devices.
Sentence 2: energy consumption is undoubtedly the most important factor in modern mobile system design, and the energy-efficient computing (i.e., achieving substantial energy savings without degrading the performance) becomes one of the key challenges faced by the computer architects and system designers. 
Relationship: reasoning
Domain: Hardware
Sentence 1: Particularly one type of highly pessimistic margin has already burdened the traditional design flow even long before the recent rise of variability issues: the traditional synchronous design paradigm determines the operating frequency according to the worst critical path that is identified through static timing analysis under assumed worst case conditions.
Sentence 2: this critical path is not always excited, thus leading to processors that perform (much) slower than what they can theoretically achieve.
Relationship: contrasting
Domain: Hardware
Sentence 1: Moreover, when prefetching in employed (bottom graph of Fig. 5), DARCA manages to further increase its distance from prior FT schemes.
Sentence 2: when the block disabling technique is employed, the baseline cache will be able to keep data in cachelines even if they have some faulty subblocks i.e., four faultyÂ­bits are attached in each 64-bytes physical cache frame or onefaulty-bit every 16-bytes [1].
Relationship: neutral
Domain: Hardware
Sentence 1: This is important since ourtarget is to increase the reliability of the latency-sensitive L1s.In order to calculate access time, we modified CACTI source code to integrate the DARCA extra components into the design.
Sentence 2: the extra components are i) the variabletag selection logic (below tag arrays), ii) the index bit selectionlogic (before cache decoder), and iii) the extra level ofmultiplexer (below data arrays).
Relationship: entailment
Domain: Hardware
Sentence 1: Standard destructive reverse-­engineering techniques (usage of Chemical Metal Polishing followed by Scanning Electron Microscope image reconstruction and analysis) can be used to detect HTs if we can compare ICs with a golden circuit.
Sentence 2: this task is very expensive since it takes a lot of time to realize properly: if the obtained images are blurry for any reason (like bad mechanical or chemical preparation), the reverse-engineering is hard.
Relationship: contrasting
Domain: Hardware
Sentence 1: If the HT is close to a net Na (or directly connected to a net Na), dHTa is defined as the random delay added by the HT to the net Na in an infected IC.
Sentence 2: impact of two HTs on delays, for (P, K)no13 (up) and no47 (down) AES bits, estimated by the number decrements by clock steps One can highlight on the importance to study not only the needed to fault each considered bit.
Relationship: neutral
Domain: Hardware
Sentence 1: Low-cost and efficient routing solutions based on Dimension-Ordered Routing, like FDOR [9], or on turn models [10], [11] have been proposed to provide coverage on irregular topologies.
Sentence 2: they either provide low coverage (single link faults) [9], [10] or disable a large number of faultfree nodes to extend the coverage [10], [11].
Relationship: contrasting
Domain: Hardware
Sentence 1: Ignorance of the circuit s error masking property may lead to over-design of a reliable processor or application-specific hardware accelerator circuit that may incur signi.cant power and area overhead2 .
Sentence 2: a fast analysis of the error masking characteristics is required to evaluate and enhance the quality of a reliable processor design in a cost-effective way, while curtailing the analysis and design time to ensure fast time to market.
Relationship: reasoning
Domain: Hardware
Sentence 1: Thus, unlike earlier comparisons made in tables II, III and IV, we cannot give a performance guarantee for I-ordering + DP-fill over techniques proposed in [20], [21] or [22].
Sentence 2: it is interesting to note from Table V that the proposed I-ordering + DP-fill technique actually outperforms all the these techniques for most of the benchmarks and the percentage improvement increases with increase in circuit size.
Relationship: contrasting
Domain: Hardware
Sentence 1: The TSV which is located at the corner is connected a 3-to-1 MUX whose inputs are its own signal, signal from the same ring and signal from the outer ring.
Sentence 2: the TSV which is not located at the corner is connected to a 4-to-1 MUX whose inputs are its own signal, the signal from the same ring, the signal from inner ring and the signal from outer ring.
Relationship: contrasting