sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: The non-intrusive sensors consist of dummy analog stages and single components extracted directly from the topology of the LNA.
Sentence 2: we consider a dummy bias stage identical to the bias stage of the LNA formed by transistor M3 and resistor R1, a dummy gain stage identical to the gain stage of the LNA formed by transistors M1 and M2, a dummy diode-connected transistor identical to the transistor M1, and a dummy capacitor identical to the capacitor Cin.
Relationship: entailment
Domain: Hardware
Sentence 1: The acceleration of applications, running on a general purpose processor (GPP), by mapping parts of their execution to reconfigurable hardware is an approach which does not involve program's source code and still ensures program porta­bility over different target reconfigurable fabrics.
Sentence 2: the problem is very challenging, as suitable sequences of GPP in­structions need to be translated/mapped to hardware, possibly at runtime.
Relationship: contrasting
Domain: Hardware
Sentence 1: A very relevant application in this domain pertains to the development of the gene therapy for HIV-1 [11], which has to tackle the dynamic variation in parameters of the biological interactions when searching for the best configuration and amount of engineered cells.
Sentence 2: we explore the computation kernel that studies the interactions between cells and virions and enables the design of a gene therapy for HIV-1 infection, and consider it as a use-case to design and evaluate the potentials of a NoC-based multicore platform.
Relationship: reasoning
Domain: Hardware
Sentence 1: In this paper, we present a novel performance simulation tool with the added flexibility adequate for use in architectural optimization as the parameters of the component devices change.
Sentence 2: this simulator is designed to handle reconfigurable quantum hardware, where device parameter (DP) values can be adjusted  handle reconfigurable quantum architecture, where re­source investment scenarios can be studied  output concrete breakdown of performance metrics (e.g. total execution time and failure probability) and contents of resource overhead (such as qubits used as ancilla or for communication purposes).
Relationship: entailment
Domain: Hardware
Sentence 1: One common approach is to use heat maps captured from the silicon layer of the given processor as it executes instructions, and use heuristic algorithms to back-estimate the detailed power model to be used with the Hotspot simulator, see [8].
Sentence 2: several critical details (e.g., processor floorplan, on-chip power and/or temperature management algorithms) must still be guessed.
Relationship: contrasting
Domain: Hardware
Sentence 1: The breakpoint-based silicon debug approach allows users to stop the normal (system) operations of the circuits under debug (CUDs), extract the internal states of the CUDs for examination, and then resume the normal operations for further debugging.
Sentence 2: then when the CUD_MA is granted to use the bus, it will inform the PAM_IP_BUS to unlock the system and to accept data from the CUD.
Relationship: neutral
Domain: Hardware
Sentence 1: Whilst there has been a lot of interest in researching new architectures for GALS [1][2][3], there have been few attempts at providing synthesis solutions for GALS communication.
Sentence 2: generation of GALS from specifications has been limited to hardware description languages such as Verilog, VHDL [4] or synchronous programming languages such as C or ES-TEREL [5].
Relationship: reasoning
Domain: Hardware
Sentence 1: As seen in Fig. 1 (a,b), the STT-MRAM bit­cell consists of an MTJ and a MOSFET.
Sentence 2: the techniques published in literature are either focused on the optimization and failure mitigation at the bit-cell level [8,9,10], or on memory architecture design techniques to improve STT-MRAM yield [11,12].
Relationship: neutral
Domain: Hardware
Sentence 1: This is simply because of the power-line switching overhead which becomes more notable when the system has to be turned off and on frequently.
Sentence 2: efficient power-gating can be applied to a unit which has the following characteristics: first, it should have a low utilization in order to have a good potential of being turned off, and second, its idleness must not be fragmented so that the power-line switching overhead remains negligible [11].
Relationship: reasoning
Domain: Hardware
Sentence 1: For the particular case of the soundscape quality estimation task, we have adopted an alternative approach (called indirect soundscape quality -ISQ): instead of direclty mapping points of the feature space to scalar estimates (typical regression), we have also implemented a meta-regression scheme. 
Sentence 2: we use the estimated levels for the three context classes as feature values in a meta-regression approach (see Figure 8).
Relationship: entailment
Domain: Hardware
Sentence 1: In order to measure the overall latency of a system with a player with a physical disability, a system was implemented using the Xbox 360 Kinect and a Windows computer running the Kinect SDK version 1.8.
Sentence 2: these are outliers, and the average of the absolute value of the deviation between drum and guitar was under 150ms, with times as low as 30ms.
Relationship: neutral
Domain: Hardware
Sentence 1: Through our work, we show that UrJar has the potential to channel e-waste towards the alleviation of energy poverty, thus simultaneously providing a sustainable solution for both problems. 
Sentence 2: we present one such attempt, a backup power device - called UrJar - that seeks to simultaneously address the problems of proliferation of laptop battery e-waste, and the prevalence of energy poverty in developing countries.
Relationship: neutral
Domain: Hardware
Sentence 1: In this paper we claim that understanding QoE in mobile devices is paramount for cellular network operators, and present the results obtained from subjective lab tests performed for popular end-user services accessed through smartphones. 
Sentence 2: we consider the following five well-known applications in mobile devices: YouTube dynamic and non-dynamic video streaming, Facebook, Google Maps (Gmaps from now on), Web browsing through Google Chrome, and WhatsApp.
Relationship: entailment
Domain: Hardware
Sentence 1: To evaluate the RA, ProSA-RA suggests using a checklist-based inspection approach named FERA (Framework for Evaluation of Reference Architectures) [30].
Sentence 2: we followed the recommendation and used FERA to conduct an evaluation in order to verify: (i) completeness of general information related to the construction and content of the architectural views; (ii) adequacy for releasing of the architectural description of our RA; and (iii) viability and change possibilities of our RA.
Relationship: reasoning
Domain: Hardware
Sentence 1: Inside this droplet, the luminescent process takes place or not, according to the presence or absence of signal- Figure 3: Graphic representation of the adopted encoding approach ing molecules.
Sentence 2: downstream the signaling molecule detector, a sequence of luminescent and non luminescent droplets is produced, where the luminescent droplet represents the bit 1 and the non-luminescent droplet represents the bit 0 .
Relationship: reasoning
Domain: Hardware
Sentence 1: The proposed hardwaresoftware technique leads to a mean improvement of 18% in application performance and a mean reduction of 26% in misses over a shared LLC managed by the Least Recently Used replacement policy for a set of input-annotated taskparallel programs using the OmpSs programming model implemented on the NANOS++ runtime.
Sentence 2: the state-of-the-art thread-based partitioning scheme suffers an average performance loss of 2% and an average increase of 15% in misses over the baseline.
Relationship: contrasting
Domain: Hardware
Sentence 1: The insight behind FECC follows recent works which observe that compression at the cache-block granularity can free up enough space for other information [17, 18]; we use this free space for storing the ECC codes. 
Sentence 2: when compression succeeds, FECC can match the performance of a conventional ECC organization that uses dedicated ECC memory devices with less, or even zero, dedicated redundancy.
Relationship: reasoning
Domain: Hardware
Sentence 1: All data was recorded using the same smart­phone, but in independent sensing runs over the course of one year with long pauses between them.
Sentence 2: data was sub­ject to possible systematic errors due to varying temperature, slightly different experimental setup and even changed methods of data collection: The first few datasets were recorded with an older version of the sensing app, which heavily used automatic white balance and exposure compensation.
Relationship: reasoning
Domain: Hardware
Sentence 1: In this section, we survey these systems, noting the effect that these choices have on overall size and power draw.
Sentence 2: we survey three commercial meters Kill-A-Watt [6], Watts Up [17], and Belkin Conserve Insight [3] and three research meters ACme [26] (two different versions), Monjolo [23], and Gemini [20] alongside PowerBlade (this work).
Relationship: entailment
Domain: Hardware
Sentence 1: One important adaptation is using Lin s concordance correlation coefficient (CCC) [17] rather than Pearson s correlation coefficient to measure performance.
Sentence 2: 3.1 Audio Features The extraction of linear predictive coding coefficients (LPC) is an auto regressive approach, where the n th sample of a time series is approximated using a function of the p preceding samples [1]: LPC are still widely applied in speech processing, for example in speech recognition and speech synthesis.
Relationship: neutral
Domain: Hardware
Sentence 1: Although cover traffic hides the exact number of dead drops accessed once or twice, an adversary can still tell roughly how many people are talking, by looking at the number of dead drops accessed twice and subtracting the average amount of noise.
Sentence 2: in the above configuration, clients use an average of 12 KB/sec (adding up to 30 GB over a month of continuous use, which may be high for a mobile phone with metered data service).
Relationship: neutral
Domain: Hardware
Sentence 1: Vuvuzela aims to provide point-to-point messaging between users in a way that is private in the face of a strong adversary, who can observe and tamper with the entire network and all but one of Vuvuzela's servers.
Sentence 2: an adversary should not be able to distinguish between a scenario where two particular users are communicating, and a scenario where they are not, even after interfering with the system.
Relationship: entailment
Domain: Hardware
Sentence 1: The multiplicative ε provides plausible deniability: any event observed if, say, two specific users are talking has within eε times the probability if they were doing something else (e.g., within 1.1× for ε = 0.1 and within 2× for ε = ln 2), so users always have a plausible "cover story".
Sentence 2: δ covers events that might have zero probability under some actions but happen under others.
Relationship: contrasting
Domain: Hardware
Sentence 1: Vuvuzela aims to provide point-to-point messaging between users in a way that is private in the face of a strong adversary, who can observe and tamper with the entire network and all but one of Vuvuzela's servers.
Sentence 2: finally, to not let noise affect the clarity of the graphs, we configure servers to always add exactly µ noise, rather than sampling the Laplace distribution; this produces the same average results with less variance.
Relationship: neutral
Domain: Hardware
Sentence 1: First, the processor chip must be redesigned to deal with having a multitude of TSVs driven through it (which has implications in terms of engineering effort, tools support, physical design, etc.).
Sentence 2: a relatively conventional chip design can be used for 2.5D stacking as the processor die has no TSVs and does not need to undergo die thinning (risking cracking and other mechanically-related yield issues).
Relationship: contrasting
Domain: Hardware
Sentence 1: The similarity between spatial computing and an assembly line and with data routing in general, calls for examining the relevance of various buffering, queuing and routing schemes and constructs used there to the organization and interconnection of operand memory in a spatial computer.
Sentence 2: it is important to create a set of such constructs and to implement them efficiently as building blocks in the hardware (just like lookup tables, flip flops, multipliers and connections).
Relationship: entailment
Domain: Hardware
Sentence 1: Rather than relying on conventional strategies, better-than worst­case design approaches, which relax timing and manage performance, will be required, spanning DRAM design, architecture (mem­ory controller) and even the system software.
Sentence 2: we advocate in this paper for a new soft yield strategy in which memory timing constraints are allowed to vary by location to rescue chips that would have failed under strict global timing constraints.
Relationship: entailment
Domain: Hardware
Sentence 1: In particular, several memory sub-system parameters can be tweaked, possibly to miti­gate the performance loss from relaxed timing.
Sentence 2: the memory system could potentially be provisioned differently to enable relaxation of the timing; with small degrees of PV, it may be possible to adopt relaxed global timings with appropriate configuration of memory sub-system parameters, such as redundancy, buffering and bank parallelism.
Relationship: entailment
Domain: Hardware
Sentence 1: Identification and definition of guidelines for manual composition of convergent services are problems that have been investigated for years [18]; more recently, automation of different phases of convergent composition has been actively researched.
Sentence 2: we have developed a framework called AUTO [3][4][5], which aims at supporting the automated composition of convergent services using automated planning for service composition and natural language processing for user request processing.
Relationship: entailment
Domain: Hardware
Sentence 1: WZeroRPC is an open source platform that takes a different approach by offering a workflow-based execution model that can be embedded within conventional programming paradigms.
Sentence 2: it provides support for executing a directed acyclic graph (DAG) workflow, executed across a distribution of workers, along with the dependencies between them, whilst providing a Python interface for coordinating execution and data dependencies between multiple workflow instances.
Relationship: entailment
Domain: Hardware
Sentence 1: Although cloud environments are capable of providing virtualized, elastic, controllable and high quality on-demand services, they still lack the ability to control the selection and configuration of infrastructural components in response to changing requirements and environmental pressures.
Sentence 2: current Cloud environments still do not have the tools and application programming interfaces that would allow the developers to exert such control on the underlying infrastructure in an intelligent, semi-autonomous manner.
Relationship: entailment
Domain: Hardware
Sentence 1: Since all elements of a given data type share the same expected range of values (as discussed in Sec. 4.1), elements with relatively smaller values (e.g., interest rates) become overly susceptible to approximate similarity, leading to some inaccuracy. 
Sentence 2: all of these overheads are faithfully modeled in the energy and area results in Sec. 5.
Relationship: neutral
Domain: Hardware
Sentence 1: For the LPDDR3based point-to-point system, since all of the data are supplied by a single chip, it is easy to apply a data layout similar to what is shown here.
Sentence 2: this paper presents MiL (More is Less), a novel data communication framework built on top of DDR4, which exploits the data bus under-utilization caused by DRAM timing constraints to selectively apply sparse codes, thereby reducing the IO energy without compromising system performance.
Relationship: neutral
Domain: Hardware
Sentence 1: Due to the workonly/allocation policy with vCache (geo-mean of three conserving policy of vCache, VM1 can exploit unallocated/unused capacity along with its allocated vLLC and thus vLLC shows higher performance than pLLC while preserving VM2 s performance.
Sentence 2: vM1 can exploit more capacity before VM2 fills its al located capacity, since VM2 does not fully utilize its allocated capacity.
Relationship: entailment
Domain: Hardware
Sentence 1: Such a page coloring technique can allow the OS to evenly spread accesses across LLC sets or reduce interference amongmultiple applications sharingthe LLC byassigninga suitable LLC region for each application.
Sentence 2: it is widely supported by the mainstream operating systems such as Solaris, FreeBSD, netBSD, and Windows NT [12, 19, 13, 20, 17].
Relationship: reasoning
Domain: Hardware
Sentence 1: Fingerprint-based comparison has better performance but needs to resolve potential collision problems, compared to byte-tobyte comparison.
Sentence 2: sHA-1 hashing is one of the most commonly used methods in generating fingerprints of selected data because SHA-1 has an extremely low collision rate and, at the same time, reasonably good performance [10, 16, 20].
Relationship: entailment
Domain: Hardware
Sentence 1: To address this issue, we propose to adopt wear leveling for containers with the integration of the proposed two-class bucket list.
Sentence 2: when a container is selected by procedure C ONTAINE R -ALLO C (in Algorithm 3), this container is compared with the first container of each bucket in both the compact and non-compact lists by checking their age .eld in the their container metadata records.
Relationship: entailment
Domain: Hardware
Sentence 1: In order to minimize the frequency on allocating containers from the proposed bucket list and to ultimately extend the time on repacking chunks of containers, we adopt the worst-fit policy that tries to allocate containers with the largest free space and prefers to allocate the free space without any internal fragments.
Sentence 2: the proposed strategy will scan the com­pact list from bucket N to bucket 0, and return the first container from the bucket that is not empty.
Relationship: entailment
Domain: Hardware
Sentence 1: What is the last mile of the challenges in the designs would be on how to effectively provide an operating system a PCM storage device with a common storage-device interface, which is usually of fixed management units such as an LBA (or referred to as a sector for hard disks).
Sentence 2: the technical problem falls on how to (1) efficiently manage (i.e., allocated and deallocate) free PCM storage space and (2) map fixed-sized LBAs to variable-sized chunks when CDC is supported, so that the space utilization of PCM-based storage could be ultimately improved.
Relationship: entailment
Domain: Hardware
Sentence 1: We represent user-defined data types as statically-sized bit vectors in hardware; if a definition is recursive, we cannot determine how many bits to assign to the recursive component at compile time.
Sentence 2: we replace recursive portions of these data types with a pointer data type e.g. a non-empty integer list defined as Cons Int List becomes Cons Int Ref, where Ref can be defined as a primitive numeric type.
Relationship: reasoning
Domain: Hardware
Sentence 1: We select an energy efficient RF size for comparison against the nonoptimized and the pruned radix-2 implementations.
Sentence 2: if the vector register width is W , the number of memory  min(m, 2N k ) subset_acc(N, m, k, W ) = (7) W We use the ceiling operator so that if the number of non-zero points is not a multiple of SIMD width W , then the additional load fetches the remaining values.
Relationship: neutral
Domain: Hardware
Sentence 1: Indeed, execution time of invariant mining depends on the number and length of the execution traces to be analysed, the number of considered variables, and the number of invariants actually present in the traces (due to the effect of the two optimizations described at the end of Section 4.1.
Sentence 2: experimental results have been conducted on randomly generated execution traces with different values for such parameters by considering boolean and numeric (integer and real) data-type variables.
Relationship: reasoning
Domain: Hardware
Sentence 1: This python code was used as a baseline to produce both a CUDA version, using CUBLAS and hand-­written CUDA, and an Intel Xeon Phi version, using OpenMP and offload primitives.
Sentence 2: when using the newer 14.6 version of the compiler, MD5Hash would run as expected, but performance of MaxFlops dropped to less than 50% of the device peak.
Relationship: neutral
Domain: Hardware
Sentence 1: CHStone suite is a set of 12 benchmarks, explicitly collected for the evaluation of High Level Synthesis flows, which aim at representing all the possible scenarios which have to be addressed by an High Level Synthesis tool.
Sentence 2: this suite contains both data dominated applications (aes, blow.sh, jpeg, mpeg2, sha) and control oriented applications (adpcm, dfadd, dfdiv, dfmul, dfsin, gsm, mips).
Relationship: entailment
Domain: Hardware
Sentence 1: However, we need to take into account the non-conflict constraint on a given buslet: for this, we need to ensure that at most one FU per clock cycle will drive the buslet (this will be done via tri-state buffers, enabled at the right clock cycle(s) by the datapath FSM controller) In order to ensure this, a proper scheduling algorithm is needed which minimizes the number of buslets required for such a constraint; a corresponding binding algorithm with other minimization goals and constraints is also needed.
Sentence 2: our algorithms solve a variation of the MR-LCS problem that we call MRW-LCS (minimum resources and wiring, latency constrained scheduling), and is divided into two stages: 1) Scheduling algorithm, which is itself divided into two phases: a) FDCS (Force Directed Communication Scheduling), a modified version of Force-Directed Scheduling [6], minimizes the lower-bound number of buslets implied by scheduling communications between operation nodes (the number of buslets could increase from this lower bound during binding, as we need to satisfy some extra constraints there).
Relationship: entailment
Domain: Hardware
Sentence 1: Since the specification items are tightly related each other and it is practically very time consuming to explore all feasible clock spine candidates, we solve the problem of clock spine synthesis by performing four steps.
Sentence 2: our proposed power-aware clock spine synthesis called CSPINE consists of four steps: (Step 1) Clustering clock sinks, (Step 2) Relaxing spines, (Step 3) Inserting spine buffers, and (Step 4) Constructing a top-level clock tree.
Relationship: entailment
Domain: Hardware
Sentence 1: As reported by US Department of Commerce [1], counterfeit­ing accounts for more than 8% of global merchandise trade, which is in the trillion dollars range.
Sentence 2: counter­feit electronics are increasingly being distributed throughout the market and legitimate electronic companies miss out on about $100 billion of global revenue every year because of counterfeiting, thereby posing a severe threat to the global electronic supply chain [2].
Relationship: entailment
Domain: Hardware
Sentence 1: The ARFIMA model allows for incorporating the long term memory of the process x(t) by capturing the fractality within its fractional differencing operator.
Sentence 2: for instance, for a large scale NoCbased multicore platform capable of both wormhole packet and network coding [11] communication, the MPC-based optimization modules have to decide when to switch between the two approaches such that the power/energy consumption profile is minimized while not sacrificing overall system performance.
Relationship: neutral