[deleted]

I'm sorry if I'm misunderstanding your post, but DRAM *does not* have to
be refreshed on *each access cycle*.  So cycle time does *not* have to be
twice the access time *because of refresh phase*.

The access time usually means the delay time from falling edge of raw
address strobe (RAS) to data bus driven.

DRAM access cycle timing chart can be roughly shown as following (some
signals are intentionally omitted);

ADDR --<RA><CA>-------<RA><CA>--------- RA=Raw Address, CA=Column Address
RAS  ~~~~\________/~~~~~\________/~~~~~		~=High, _=Low, -=Floating
CAS  ~~~~~~~\_______/~~~~~~\_______/~~~		<..>=driven either H or L
DATA ---------<VALID>--------<VALID>---
         |-------+------|
         |-+--|  |
           |     +----------- cycle time
           +---- access time (or RAS access time)

Yes, the cycle time is more than twice as the access time but *not*
because of the refresh phase.  The refresh can be done either as a
trailing phase of normal access cycle or as an individual cycle.

[other stuff deleted]

Ken Nakata