

Assuming 68HC11...
In expanded muxed mode, you *could* do it. Much easier if you get a DRAM
controller IC. The MMI 673102 could be used to implement this, or you
could use a counter and a huge multiplexer to provide row/column/refresh
address multiplexing. The thing with DRAMs is that they require wierd
timing, address multiplexing, and refresh.

Actually, if you wanted to use a 68008 IC, you could look at AN897, which
has a neat controller built in. There is also the 683xx, I think one
of those has the DRAM controller built in. This one is for the 6664
DRAM, however, the 41256 has only one more address line, adding only
another component or so. The 256k SIMMs are basically 8 or 9 41256
DRAM chips (or their equivalent in fewer packages).