



	Yes, but... the minimization of gates is important in part
because of TIMING considerations.  A TTL gate has the basic structure
of AND/OR/INVERT, and an inversion of a sum of a product is just
exactly ONE gate delay.  The reason to find a minimal sum of products
is that this matches a hardware optimization.

	A positive-OR gate (such as the 9-gate solution uses) has
TWO gate delays (and there's another gate delay in the second term)
so that the second solution, while simpler in logic symbols, can 
be expected to be something less than optimal in the real world.
ECL is similar to TTL, in that it can support an OR/AND
gate with the minimum delay (unlike TTL, you get both true and
inverse outputs for 'free' when using ECL).

	PALs are basically large programmable AND/OR/INVERT
gates (with your choice of internal connections between the
various sections, and perhaps some latches), so a minimum sum
of products ALSO is a way to shoehorn a logic design into 
a few PALs.  It's not comparably easy to design with a minimization
of logic gates, but some software packages claim to allow you to
do so, and will take just about any mess of gates (as a nodelist
with 74xxx series logic ICs) and produce a description of
a logic cell array to do the same job.  Xilinx's XACT software
does this by treating each logic block as a macro, and expanding
it all out, then simplifying.