Repository: raspberrypi/pico-sdk
File: src/rp2_common/pico_multicore/include/pico/multicore.h (C/C++)

Code before:
 *
 * \param entry Function entry point
 * \param stack_bottom The bottom (lowest address) of the stack
 * \param stack_size_bytes The size of the stack in bytes (must be a multiple of 4)
 * \see multicore_reset_core1
 */
void multicore_launch_core1_with_stack(void (*entry)(void), uint32_t *stack_bottom, size_t stack_size_bytes);

/*! \brief  Launch code on core 1 with no stack protection
 *  \ingroup pico_multicore
 *
 * Wake up (a previously reset) core 1 and enter the given function using the passed sp as the initial stack pointer.
 *
 * core 1 must previously have been reset either as a result of a system reset or by calling \ref multicore_reset_core1
 *
 * This is a bare bones functions that does not provide a stack guard even if USE_STACK_GUARDS is defined
 *
 * \param entry Function entry point
 * \param sp Pointer to the top of the core 1 stack
 * \param vector_Table address of the vector table to use for core 1
 * \see multicore_reset_core1
 */
void multicore_launch_core1_raw(void (*entry)(void), uint32_t *sp, uint32_t vector_table);

/*!
 * \defgroup multicore_fifo fifo
 * \ingroup pico_multicore
 * \brief Functions for the inter-core FIFOs
 *
 * The RP2040 contains two FIFOs for passing data, messages or ordered events between the two cores. Each FIFO is 32 bits
 * wide, and 8 entries deep. One of the FIFOs can only be written by core 0, and read by core 1. The other can only be written
 * by core 1, and read by core 0.
 *
 * \note The inter-core FIFOs are a very precious resource and are frequently used for SDK functionality (e.g. during
 * core 1 launch or by the \ref multicore_lockout functions). Additionally they are often required for the exclusive used by
 * an RTOS (e.g. FreeRTOS SMP). For these reasons it is suggested that you do not use the FIFO for your own purposes
 * unless none of the above concerns apply; the majority of cases for transferring data between cores can be eqaully
 * well handled  by using a \ref queue
 */

/*! \brief Check the read FIFO to see if there is data waiting sent by the other core
 *  \ingroup multicore_fifo
 *
 * See the note in the \ref multicore_fifo section for considerations regarding use of the inter-core FIFOs
 *
 * \return true if the FIFO has data in it, false otherwise
 */
static inline bool multicore_fifo_rvalid(void) {
    return !!(sio_hw->fifo_st & SIO_FIFO_ST_VLD_BITS);
}


Review comment (suggestion):
This seems to be the only "launch" function that allows a vector table to be passed? I know nothing about low-level multicore programming, but would e.g. a `multicore_launch_core1_with_stack_and_vector_table` be useful? :man_shrugging: 

Code after:
 *
 * core 1 will use the same vector table as core 0
 *
 * \param entry Function entry point
 * \param stack_bottom The bottom (lowest address) of the stack
 * \param stack_size_bytes The size of the stack in bytes (must be a multiple of 4)
 * \see multicore_reset_core1
 */
void multicore_launch_core1_with_stack(void (*entry)(void), uint32_t *stack_bottom, size_t stack_size_bytes);

/*! \brief  Launch code on core 1 with no stack protection
 *  \ingroup pico_multicore
 *
 * Wake up (a previously reset) core 1 and start it executing with a specific entry point, stack pointer
 * and vector table.
 *
 * This is a low level function that does not provide a stack guard even if USE_STACK_GUARDS is defined
 *
 * core 1 must previously have been reset either as a result of a system reset or by calling \ref multicore_reset_core1
 *
 * \param entry Function entry point
 * \param sp Pointer to the top of the core 1 stack
 * \param vector_table address of the vector table to use for core 1
 * \see multicore_reset_core1
 */
void multicore_launch_core1_raw(void (*entry)(void), uint32_t *sp, uint32_t vector_table);

/*!
 * \defgroup multicore_fifo fifo
 * \ingroup pico_multicore
 * \brief Functions for the inter-core FIFOs
 *
 * The RP2040 contains two FIFOs for passing data, messages or ordered events between the two cores. Each FIFO is 32 bits
 * wide, and 8 entries deep. One of the FIFOs can only be written by core 0, and read by core 1. The other can only be written
 * by core 1, and read by core 0.
 *
 * \note The inter-core FIFOs are a very precious resource and are frequently used for SDK functionality (e.g. during
 * core 1 launch or by the \ref multicore_lockout functions). Additionally they are often required for the exclusive use
 * of an RTOS (e.g. FreeRTOS SMP). For these reasons it is suggested that you do not use the FIFO for your own purposes
 * unless none of the above concerns apply; the majority of cases for transferring data between cores can be eqaully
 * well handled  by using a \ref queue
 */

/*! \brief Check the read FIFO to see if there is data available (sent by the other core)
 *  \ingroup multicore_fifo
 *
 * See the note in the \ref multicore_fifo section for considerations regarding use of the inter-core FIFOs
 *
 * \return true if the FIFO has data in it, false otherwise
 */
static inline bool multicore_fifo_rvalid(void) {