Repository: firecracker-microvm/firecracker
File: tests/integration_tests/functional/test_cpu_features_x86_64.py (Python)

Code before:
                "tme",
                "tpr_shadow",
                "vmx",
                "vnmi",
                "vpid",
                "xtpr",
            }
            host_guest_diff_6_1 = host_guest_diff_5_10 - {
                "bts",
                "dtes64",
                "dts",
                "pebs",
            }

            if global_props.host_linux_version_tpl < (6, 1):
                assert host_feats - guest_feats == host_guest_diff_5_10
            else:
                assert host_feats - guest_feats == host_guest_diff_6_1

            assert guest_feats - host_feats == {
                "hypervisor",
                "tsc_known_freq",
            }
        case CpuModel.AMD_GENOA:
            # Return here to allow the test to pass until CPU features to enable are confirmed
            return
        case _:
            if os.environ.get("BUILDKITE") is not None:
                assert False, f"Cpu model {cpu_model} is not supported"


# From the `Intel® 64 Architecture x2APIC Specification`
# (https://courses.cs.washington.edu/courses/cse451/24wi/documentation/x2apic.pdf):
# > The X2APIC MSRs cannot to be loaded and stored on VMX transitions. A VMX transition fails
# > if the VMM has specified that the transition should access any MSRs in the address range
# > from 0000_0800H to 0000_08FFH
X2APIC_MSRS = [hex(i) for i in range(0x0000_0800, 0x0000_08FF + 1)]


# Some MSR values should not be checked since they can change at guest runtime
# and between different boots.
# Current exceptions:
# * FS and GS change on task switch and arch_prctl.
# * TSC is different for each guest.
# * MSR_{C, L}STAR used for SYSCALL/SYSRET; can be different between guests.
# * MSR_IA32_SYSENTER_E{SP, IP} used for SYSENTER/SYSEXIT; same as above.
# * MSR_KVM_{WALL, SYSTEM}_CLOCK addresses for struct pvclock_* can be different.
# * MSR_IA32_TSX_CTRL is not available to read/write via KVM (known limitation).
#
# More detailed information about MSRs can be found in the Intel® 64 and IA-32
# Architectures Software Developer’s Manual - Volume 4: Model-Specific Registers

Review comment (bug):
as a first pass, don't we want to know what the differences are?

Maybe it belongs in the default case below:

`assert guest_feats == host_feats`

We know that will fail, but it will dump the diff than we can then copy paste into the test?


Code after:
                "tme",
                "tpr_shadow",
                "vmx",
                "vnmi",
                "vpid",
                "xtpr",
            }
            host_guest_diff_6_1 = host_guest_diff_5_10 - {
                "bts",
                "dtes64",
                "dts",
                "pebs",
            }

            if global_props.host_linux_version_tpl < (6, 1):
                assert host_feats - guest_feats == host_guest_diff_5_10
            else:
                assert host_feats - guest_feats == host_guest_diff_6_1

            assert guest_feats - host_feats == {
                "hypervisor",
                "tsc_known_freq",
            }
        case CpuModel.AMD_GENOA:
            # Return here to allow the test to pass until CPU features to enable are confirmed
            return
        case _:
            if os.environ.get("BUILDKITE") is not None:
                assert (
                    guest_feats == host_feats
                ), f"Cpu model {cpu_model} is not supported"


# From the `Intel® 64 Architecture x2APIC Specification`
# (https://courses.cs.washington.edu/courses/cse451/24wi/documentation/x2apic.pdf):
# > The X2APIC MSRs cannot to be loaded and stored on VMX transitions. A VMX transition fails
# > if the VMM has specified that the transition should access any MSRs in the address range
# > from 0000_0800H to 0000_08FFH
X2APIC_MSRS = [hex(i) for i in range(0x0000_0800, 0x0000_08FF + 1)]


# Some MSR values should not be checked since they can change at guest runtime
# and between different boots.
# Current exceptions:
# * FS and GS change on task switch and arch_prctl.
# * TSC is different for each guest.
# * MSR_{C, L}STAR used for SYSCALL/SYSRET; can be different between guests.
# * MSR_IA32_SYSENTER_E{SP, IP} used for SYSENTER/SYSEXIT; same as above.
# * MSR_KVM_{WALL, SYSTEM}_CLOCK addresses for struct pvclock_* can be different.
# * MSR_IA32_TSX_CTRL is not available to read/write via KVM (known limitation).
#