Repository: raspberrypi/pico-sdk
File: src/rp2_common/pico_runtime_init/runtime_init_clocks.c (C)

Code before:
        // Configure clocks

        // RP2040 CLK_REF = XOSC (usually) 12MHz / 1 = 12MHz
        // RP2350 CLK_REF = XOSC (XOSC_MHZ) / N (1,2,4) = 12MHz

        // clk_ref aux select is 0 because:
        //
        // - RP2040: no aux mux on clk_ref, so this field is don't-care.
        //
        // - RP2350: there is an aux mux, but we are selecting one of the
        //   non-aux inputs to the glitchless mux, so the aux select doesn't
        //   matter. The value of 0 here happens to be the sys PLL.

        clock_configure_undivided(clk_ref,
                        CLOCKS_CLK_REF_CTRL_SRC_VALUE_XOSC_CLKSRC,
                        0,
                        XOSC_HZ);

        /// \tag::configure_clk_sys[]
        // CLK SYS = PLL SYS (usually) 125MHz / 1 = 125MHz
        clock_configure_undivided(clk_sys,
                        CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX,
                        CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS,
                        SYS_CLK_HZ);
        /// \end::configure_clk_sys[]

        // CLK USB = PLL USB 48MHz / 1 = 48MHz
        clock_configure_undivided(clk_usb,
                        0, // No GLMUX
                        CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB,
                        USB_CLK_HZ);

        // CLK ADC = PLL USB 48MHZ / 1 = 48MHz
        clock_configure_undivided(clk_adc,
                        0, // No GLMUX
                        CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB,
                        USB_CLK_HZ);

#if HAS_RP2040_RTC
        // CLK RTC = PLL USB 48MHz / 1024 = 46875Hz
#if (USB_CLK_HZ % RTC_CLOCK_FREQ_HZ == 0)
        // this doesn't pull in 64 bit arithmetic
        clock_configure_int_divider(clk_rtc,
                        0, // No GLMUX
                        CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB,
                        USB_CLK_HZ,
                        USB_CLK_HZ / RTC_CLOCK_FREQ_HZ);

#else
        clock_configure(clk_rtc,
                        0, // No GLMUX

Review comment (suggestion):
This might be a stupid question, but given that there's a division by 1000000 in there, would it be possible to rearrange this calculation to not use 64-bit arithmetic? (given that we've already got at least one PR that is attempting to reduce the amount of 64-bit maths)

Code after:
        /// \end::pll_init[]

        // Configure clocks

        // RP2040 CLK_REF = XOSC (usually) 12MHz / 1 = 12MHz
        // RP2350 CLK_REF = XOSC (XOSC_MHZ) / N (1,2,4) = 12MHz

        // clk_ref aux select is 0 because:
        //
        // - RP2040: no aux mux on clk_ref, so this field is don't-care.
        //
        // - RP2350: there is an aux mux, but we are selecting one of the
        //   non-aux inputs to the glitchless mux, so the aux select doesn't
        //   matter. The value of 0 here happens to be the sys PLL.

        clock_configure_undivided(clk_ref,
                        CLOCKS_CLK_REF_CTRL_SRC_VALUE_XOSC_CLKSRC,
                        0,
                        XOSC_HZ);

        // This must be done after we've configured CLK_REF to XOSC due to the need to time a delay
#if SYS_CLK_VREG_VOLTAGE_AUTO_ADJUST && defined(SYS_CLK_VREG_VOLTAGE_MIN)
        if (vreg_get_voltage() < SYS_CLK_VREG_VOLTAGE_MIN) {
            vreg_set_voltage(SYS_CLK_VREG_VOLTAGE_MIN);
            // wait for voltage to settle; must use CPU cycles as TIMER is not yet clocked correctly
            busy_wait_at_least_cycles((uint32_t)((SYS_CLK_VREG_VOLTAGE_AUTO_ADJUST_DELAY_US * (uint64_t)XOSC_HZ) / 1000000));
        }
#endif

        /// \tag::configure_clk_sys[]
        // CLK SYS = PLL SYS (usually) 125MHz / 1 = 125MHz
        clock_configure_undivided(clk_sys,
                        CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX,
                        CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS,
                        SYS_CLK_HZ);
        /// \end::configure_clk_sys[]

        // CLK USB = PLL USB 48MHz / 1 = 48MHz
        clock_configure_undivided(clk_usb,
                        0, // No GLMUX
                        CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB,
                        USB_CLK_HZ);

        // CLK ADC = PLL USB 48MHZ / 1 = 48MHz
        clock_configure_undivided(clk_adc,
                        0, // No GLMUX
                        CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB,
                        USB_CLK_HZ);

#if HAS_RP2040_RTC
        // CLK RTC = PLL USB 48MHz / 1024 = 46875Hz