Repository: llvm/llvm-project
File: llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp (C++)

Code before:
    const Register DstReg = I.getOperand(0).getReg();

    // Sources
    bool HasPassthruOperand = IntrinID != Intrinsic::riscv_vlm;
    unsigned CurOp = 2;
    SmallVector<SrcOp, 4> SrcOps; // Source registers.

    // Passthru
    if (HasPassthruOperand) {
      auto PassthruReg = I.getOperand(CurOp++).getReg();
      SrcOps.push_back(PassthruReg);
    } else {
      SrcOps.push_back(Register(RISCV::NoRegister));
    }

    addVectorLoadStoreOperands(I, SrcOps, CurOp, IsMasked, IsStrided);

    RISCVVType::VLMUL LMUL = RISCVTargetLowering::getLMUL(getMVTForLLT(VT));
    const RISCV::VLEPseudo *P =
        RISCV::getVLEPseudo(IsMasked, IsStrided, /*FF*/ false, Log2SEW,
                            static_cast<unsigned>(LMUL));

    MachineInstrBuilder PseudoMI =
        BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(P->Pseudo), DstReg);
    for (const auto &SrcOp : SrcOps)
      SrcOp.addSrcToMIB(PseudoMI);

    // Select VL
    auto VLOpFn = renderVLOp(I.getOperand(CurOp++));
    for (auto &RenderFn : *VLOpFn)
      RenderFn(PseudoMI);

    // SEW
    PseudoMI.addImm(Log2SEW);

    // Policy
    uint64_t Policy = RISCVVType::MASK_AGNOSTIC;
    if (IsMasked)
      Policy = I.getOperand(CurOp++).getImm();
    PseudoMI.addImm(Policy);

    // Memref
    PseudoMI.cloneMemRefs(I);

    I.eraseFromParent();
    constrainSelectedInstRegOperands(*PseudoMI, TII, TRI, RBI);
    return true;
  }
  case Intrinsic::riscv_vloxei:
  case Intrinsic::riscv_vloxei_mask:
  case Intrinsic::riscv_vluxei:

Review comment (suggestion):
The `SrcOp` type is also part of MachineInstrBuilder. I don't think we should be using it here either.

Code after:
    const Register DstReg = I.getOperand(0).getReg();

    // Sources
    bool HasPassthruOperand = IntrinID != Intrinsic::riscv_vlm;
    unsigned CurOp = 2;
    SmallVector<Register, 4> SrcOps; // Source registers.

    // Passthru
    if (HasPassthruOperand) {
      auto PassthruReg = I.getOperand(CurOp++).getReg();
      SrcOps.push_back(PassthruReg);
    } else {
      SrcOps.push_back(Register(RISCV::NoRegister));
    }

    addVectorLoadStoreOperands(I, SrcOps, CurOp, IsMasked, IsStrided);

    RISCVVType::VLMUL LMUL = RISCVTargetLowering::getLMUL(getMVTForLLT(VT));
    const RISCV::VLEPseudo *P =
        RISCV::getVLEPseudo(IsMasked, IsStrided, /*FF*/ false, Log2SEW,
                            static_cast<unsigned>(LMUL));

    MachineInstrBuilder PseudoMI =
        BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(P->Pseudo), DstReg);
    for (Register Reg : SrcOps)
      PseudoMI.addReg(Reg);

    // Select VL
    auto VLOpFn = renderVLOp(I.getOperand(CurOp++));
    for (auto &RenderFn : *VLOpFn)
      RenderFn(PseudoMI);

    // SEW
    PseudoMI.addImm(Log2SEW);

    // Policy
    uint64_t Policy = RISCVVType::MASK_AGNOSTIC;
    if (IsMasked)
      Policy = I.getOperand(CurOp++).getImm();
    PseudoMI.addImm(Policy);

    // Memref
    PseudoMI.cloneMemRefs(I);

    I.eraseFromParent();
    constrainSelectedInstRegOperands(*PseudoMI, TII, TRI, RBI);
    return true;
  }
  case Intrinsic::riscv_vloxei:
  case Intrinsic::riscv_vloxei_mask:
  case Intrinsic::riscv_vluxei: