Repository: dotnet/runtime
File: src/coreclr/jit/codegencommon.cpp (C++)

Code before:
{
    INDEBUG(genWriteBarrierUsed = true);

    switch (wbf)
    {
        case GCInfo::WBF_BarrierChecked:
            return CORINFO_HELP_CHECKED_ASSIGN_REF;

        case GCInfo::WBF_BarrierUnchecked:
            return CORINFO_HELP_ASSIGN_REF;

#ifdef DEBUG
        case GCInfo::WBF_NoBarrier_CheckNotHeapInDebug:
            return CORINFO_HELP_ASSIGN_REF_ENSURE_NONHEAP;
#endif // DEBUG

        default:
            unreached();
    }
}

// -----------------------------------------------------------------------------
// genGetGSCookieTempRegs:
//   Get a mask of registers to use for the GS cookie check generated in a
//   block.
//
// Parameters:
//   tailCall - Whether the block is a tailcall
//
// Returns:
//   Mask of all the registers that can be used. Some targets may need more
//   than one register.
//
regMaskTP CodeGenInterface::genGetGSCookieTempRegs(bool tailCall)
{
#ifdef TARGET_AMD64
    if (tailCall)
    {
        // If we are tailcalling then arg regs cannot be used. For both SysV and winx64 that
        // leaves rax, r10, r11. rax and r11 are used for indirection cells, so we pick r10.
        return RBM_R10;
    }
    // Otherwise on x64 (win-x64, SysV and Swift) r9 is never used for return values
    return RBM_R9;
#elif TARGET_X86
    if (tailCall)
    {
        // For tailcall we may need ecx and edx for args. We could use eax, but
        // leave it free in case the tailcall needs something for the target.
        // Since this is only for explicit tailcalls or CEE_JMP we can just use
        // a callee save.

Review comment (suggestion):
`genGetGSCookieTempRegs` is declared unconditionally in `codegeninterface.h` and is referenced from LSRA (e.g. `lsrabuild.cpp` models the GS cookie check by calling it). Wrapping its definition in `#if !defined(TARGET_WASM)` will leave `TARGET_WASM` builds with an unresolved external. Please keep a WASM definition available (for example, return `RBM_NONE` on WASM if GS cookies aren’t supported).
```suggestion
#if defined(TARGET_WASM)

// -----------------------------------------------------------------------------
// genGetGSCookieTempRegs:
//   WASM does not currently support GS cookies, so no temporary registers
//   are required. Return an empty register mask.
//
// Parameters:
//   tailCall - Whether the block is a tailcall (unused)
//
// Returns:
//   RBM_NONE to indicate no registers are needed.
//
regMaskTP CodeGenInterface::genGetGSCookieTempRegs(bool tailCall)
{
    (void)tailCall;
    return RBM_NONE;
}

#else // !TARGET_WASM

// -----------------------------------------------------------------------------
// genGetGSCookieTempRegs:
```

Code after:
CorInfoHelpFunc CodeGenInterface::genWriteBarrierHelperForWriteBarrierForm(GCInfo::WriteBarrierForm wbf)
{
    INDEBUG(genWriteBarrierUsed = true);

    switch (wbf)
    {
        case GCInfo::WBF_BarrierChecked:
            return CORINFO_HELP_CHECKED_ASSIGN_REF;

        case GCInfo::WBF_BarrierUnchecked:
            return CORINFO_HELP_ASSIGN_REF;

#ifdef DEBUG
        case GCInfo::WBF_NoBarrier_CheckNotHeapInDebug:
            return CORINFO_HELP_ASSIGN_REF_ENSURE_NONHEAP;
#endif // DEBUG

        default:
            unreached();
    }
}

#if !defined(TARGET_WASM)

// -----------------------------------------------------------------------------
// genGetGSCookieTempRegs:
//   Get a mask of registers to use for the GS cookie check generated in a
//   block.
//
// Parameters:
//   tailCall - Whether the block is a tailcall
//
// Returns:
//   Mask of all the registers that can be used. Some targets may need more
//   than one register.
//
regMaskTP CodeGenInterface::genGetGSCookieTempRegs(bool tailCall)
{
#ifdef TARGET_AMD64
    if (tailCall)
    {
        // If we are tailcalling then arg regs cannot be used. For both SysV and winx64 that
        // leaves rax, r10, r11. rax and r11 are used for indirection cells, so we pick r10.
        return RBM_R10;
    }
    // Otherwise on x64 (win-x64, SysV and Swift) r9 is never used for return values
    return RBM_R9;
#elif TARGET_X86
    if (tailCall)
    {
        // For tailcall we may need ecx and edx for args. We could use eax, but