I am learning VHDL from zero using Altera CPLD. Already got Quartis II 12.1 and a 15-lines example VHDL (like Hello World for C learner). 

To avoid learning bad coding style or digging too deep too early, what should I look out for?


Question: both "will" "would" in one sentence
Answer: As Jon Hanna points out in a comment, the quoted language clearly includes a mistake of a type that no one at the BBC would make out of ignorance; rather it involves a stray word that the author and/or editor forgot to remove after tinkering with the wording of the sentence. It isn't accurate to call mistakes of this type typos; at the publications where I've worked, we call them brainos.

It's easy to see what triggered the tinkering: The sentence starts in present tense ("The rise comes") but shifts to past tense in order to handle the paraphrasing of the communique from Russia ("as Russia said")—leaving the author or editor to fiddle with deciding whether to pick up from the present tense rises or from the past tense said to handle the "it will resume shipments"/"it would resume shipments" section of the sentence, bearing in mind that the sentence eventually returns to present tense with "makes its first payment."

The odd verb out is evidently said, since it casts Russia's promises of future action as past, even though that action and the conditions precedent to it have not yet occurred. Under the circumstances, the writer/editor would probably have been better off putting the sentence this way:


  The rise coincides with an assurance from Russia that it will resume shipments of natural gas to Ukraine after Kiev makes its first payment next week for supplies previously delivered.