I have a graphics card for a laptop whose driver kills itself if it runs for longer than two minutes with no external monitor attached. To solve that, I decided to make a sort of dummy plug that would be detected as a monitor by PC. 

I have managed to find out what impedances video card  expects for most of the pins, but for H-Sync and V-Sync, Google brought up numerous conflicting answers, mostly from people who are guessing. 


Question: Timing inside a shift register
Answer: 
  My problem with all this is that it's not robust (maybe not the best word). Visualizing stuff on a logic analyzer will be less useful because data lines practically change in sync with clock rising edge. Random errors caused by Th>Tpd are not really visible and go undetected. If I connect another shift register in series from a different technology, which requires longer hold times, the circuit won't work, no matter how slow clock I chose.


You bring up two issues. Let's call the two synchronous circuits A and B, where A feeds into B, and both share the same clock


Circuit won't work if total Tpd(A) &lt; Th(B) where Tpd is the combinational delay of the clock. Is this true? Absolutely! You're the circuit designer and it's your final responsibility to make sure the circuit works. In reality, it's not usually a source of worry; even if you feed one register output right into another's input, the design margin of the chip's specs is high. For a NXP 74HC595, for example, typical propagation delay at 4.5V supply is 19ns, required hold time is 3nsec, and typical hold time is -2nsec -- no problem there. For a TI SN74LV595A at 5V, typical propagation delay is 4.5nsec, minimum propagation delay is 1nsec, required hold time is 2nsec. Could this be a problem if the propagation delay and hold times are at their worst case? Absolutely. Could it be a problem if you cascade a SN74LV595A into an NXP74HC595? Absolutely. In those cases you may need to add combinational elements (buffers) with enough delay to make sure the hold time is met.
"Visualizing stuff on a logic analyzer will be less useful because data lines practically change in sync with clock rising edge." True. Take a tip from SPI buses, and set the logic analyzer so that it samples the data on the clock falling edge. SPI's rules are simple: you update outputs on one edge, and you sample inputs on the other.