| 1 | A | B | C | D | E | F | G |
| --- | --- | --- | --- | --- | --- | --- | --- |
| 2 | Motorola 68000 series - Feature map |  |  |  |  |  |  |
| 3 | Year | CPU | Package | Frequency (max) [in MHz] | Address bus bits | MMU | FPU |
| 4 | 1979 | 68000 | 64-pin dual in-line package (DIP), 68-pin LCC, 68-pin pin grid array (PGA) | 8–20 | 24 | - | - |
| 5 | 1982 | 68010 | 64-pin DIP, 68-pin PLCC, 68-pin PGA | 8–16.67 | 24 | 68451 | - |
| 6 | 1984 | 68020 | 114-pin PGA | 12.5–33.33 | 32 | 68851 | 68881 |
| 7 | - | 68EC020 | 100-pin Quad Flat Package (QFP) | 16.7–25 | 24 | - | - |
| 8 | 1987 | 68030 | 132-pin QFP (max 33 MHz), 128-pin PGA | 16–50 | 32 | MMU | 68881 |
| 9 | - | 68EC030 | 132-pin QFP, 128-pin PGA | 25 | 32 | - | 68881 |
| 10 | 1991 | 68040 | 179-pin PGA, 184-pin QFP | 20–40 | 32 | MMU | FPU |
| 11 | - | 68LC040 | PGA, 184-pin QFP | 20–33 | 32 | MMU | - |
| 12 | - | 68EC040 | - | 20–33 | 32 | - | - |
| 13 | 1994 | 68060 | 206-pin PGA | 50–75 | 32 | MMU | FPU |
| 14 | - | 68LC060 | 206-pin PGA, 208-pin QFP | 50–75 | 32 | MMU | - |
| 15 | - | 68EC060 | 206-pin PGA | 50–75 | 32 | - | - |

Question: What naming protocol did Motorola use for its CPU cores?
Answer: Motorola used numbers for CPU core such as 68000, 68020, 68040 and 68060.