Position: FPGA designer
Category: C++
English level: upper
Years of experience: 5


Job responsibilities: 
• Digital Signal Processing, working with hardware ADC, DDC; 
• Software defined platforms: Zynq Ultrascale+, ADRV9008-1, AD-FMCOMMS5, bladeRF micro, usrp b205, rtl-sdr, airspy hf+, sdrplay;
• Developing and verifying of digital signal processing algorithms for satellite communication using MATLAB (filtering, demodulation, FEC);
• Developing and testing of complex VHDL/Verilog projects in FPGAs, drive projects from    studies and simulations to implementation and testing;
• Perform timing optimization of FPGA designs to achieve timing closure;
• Working with RF test equipment (Signal Generators, Spectrum Analyzers, Oscilloscope).