Position: Senior DSP/FPGA Engineer
Category: C++
English level: upper
Years of experience: 9

Motivated, creative, efficient & responsible
SKILLS

-	RTL Design:  Verilog, System Verilog
-	High Level Synthesis/Model-Based Design: Matlab/Simulink, HDL Coder, DSP Builder, Intel/Xilinx HLS
-	FPGA: MAX 10, Cyclone V, Arria 10, less experience with Xilinx Artix 7, Zynq 7000 & UltraScale
-	FPGA Interfaces: DDR, 10G Ethernet, JESD204B, obviously SPI, UART, I2C, etc
-	Programming languages: Assemblers (x86, MIPS), C, C++, Python, Matlab Language, scripting (bash, TCL)
-	Embedded Programming: Linux drivers for FPGA based SoCs, IRQs, DMA
-	Verification: layered testbenches in System Verilog, SVA assertions, random constraints, code & functional coverage, DPI, Python & Cocotb, SystemC
-	SoC: Intel FPGA Platform Designer (NIOS II, ARM), Litex (RISC-V), Xilinx Block Design (Microblaze, ARM)
-	Tools: Quartus Prime, Vivado/Vitis, Modelsim/Questasim, Verilator, Matlab/Simulink, Litex, GNURadio, make, git

WORK EXPERIENCE
									     	       
-	Implementing DSP/SDR stuff in FPGAs: DDCs, DUCs, FIR, IIR, CIC filters, resamplers, Farrow structures, streaming STFT/iSTFT, persistence spectrum analyzer
-	Multichannel TDM implementation of DSP blocks, super sample processing (multiple samples per clock cycle)
-	Creating FPGA based means for measuring signal parameters in frequency and time domains
-	Implementing parameterizable WOLA PFB channelizers with custom window function for hundreds of channels
-	Radio links interception systems: analog/digital modulators/demodulators, AGCs in time/frequency domains, circuits for phase, frequency and timing synchronization, modulation classification
-	Implementing direction finding systems
-	Managing complex SoC with a lot of DSP implemented in FPGA part, writing fragments of its Linux driver for preliminary testing of implemented DSP functionality, creating simple RISC-V based SoCs for peripheral RF devices
-	Transmitting dozens of IQ streams or demodulated bitstreams over 10G Ethernet
I would like to design state of the art miltech systems in a professional team with perfect (or at least good) company management. Also reservation from mobilization is a must