Source: {"pile_set_name": "USPTO Backgrounds"}

Considerable interest is presently attached to multi-level memories due to a demand for ever larger capacity of the storage devices. In a recent article, "A Multilevel-Cell 32 Mb Flash Memory", ISSCC95. Session 7, Paper TA 7.7, February 1995, a FLASH storage device of the multi-level type is concisely presented which can store two binary information units, or bits, per memory element, or cell. In particular, the following items are illustrated therein: the distribution of the cell threshold voltage for levels corresponding to the four possible states/values of the two bits in FIG. 1, the reading circuit diagram in FIG. 2, and the architecture of the writing circuit in FIG. 4 of the article.
It can be appreciated, from the distribution presented therein, that both the writing/reading processes and the physical structure of the cell are quite critical, much more so than with two-level memories, especially when the supply voltage is decreased to, e.g., 3.3 volts. The criticality becomes still greater as the number of the levels is raised to more than four. The outcome of this criticality is an increased error rate.
A like increase in criticality is also to be expected when the electrical parameter, whereby the cell storage state is discriminated, instead of being the threshold voltage of a floating gate MOS transistor, is a charge stored in a capacitor, as is the case with DRAM memories. This is so because it would then be necessary to compare the value of an electrical parameter with a multiplicity of reference values lying in close proximity to one another.
A known expedient in the field of two-level memories for lowering the error rate is that of using error detecting and/or correcting words, and having them stored additionally to the information words. This results in a not negligible portion of the die area being "wasted" to that object.