Source: {"pile_set_name": "USPTO Backgrounds"}

Circuitized substrates, and particularly printed circuit boards (PCBs), present a substantially planar surface on which electronic components are to be mounted. Circuit paths for these components are provided by forming conductive lines on the surface that connect component-mounting “thru-holes” in the board, for those components to which such connections are required, as well as simply between pads or the like if only surface coupling is desired, e.g., where solder balls are used as in the case of ball grid array (BGA) package structures. Electrical leads that extend from the components are electrically connected to the conductive lines when the components are mounted to the board thru-holes, or just to the pads if pad-to-pad and/or solder ball connections are used. PCBs can be single-sided, in which case components are mounted on only one surface of the circuit board, or double-sided, in which case components are mounted on opposing surfaces (and often connected to one another through the board). Today's PCBs typically include several dielectric (e.g., a glass fiber-resin combination material known as “FR4”) layers interspersed with the requisite number of conductor (e.g., copper) layers, which may be in the form of signal, power or ground layers. For such internal signal layers, the connecting lines thereof are also typically formed using the same processing as the external surface conductors, with the formed dielectric-conductor sub-composite then aligned and bonded to other sub-composites, typically using conventional lamination processes, to form the final multilayered (composite) structure.
PCBs are generally manufactured using either a subtractive etch process, a pattern plating process, or an electro-less pattern plating process, the latter also referred to as additive pattern plating. In all of these processes, a circuit mask that lays out the desired pattern of the conductive lines is transferred to the circuit board by printing the circuit mask pattern onto a polymeric radiation-sensitive resist material deposited on the board. The resist material is irradiated in the pattern of the circuit mask so that it is physically transformed where it is irradiated and is unchanged where shielded by the circuit mask. The resist material is then “developed” by exposing it to a fast-reacting chemical solution that selectively removes either the irradiated material (called a positive resist) or removes the non-irradiated material (called a negative resist).
Subtractive etching of PCBs typically begins with a board substrate comprised of a non-conductive material on which a layer of conductive material such as copper has been plated. A layer of photo-resist material is then deposited and “developed” in the circuit mask pattern so as to expose the conductive material where circuit paths are not desired. The exposed conductive material in the photo-resist voids is then etched away. Finally, the remaining photo-resist material is removed, leaving behind conductive lines wherever circuit paths were desired. The subtractive etch process provides good control over circuit path height because the amount of conductive material plated onto the substrate can be generally controlled very well. Precisely controlled circuit path height is especially important with surface mount techniques, especially when forming fine line circuitry with highly dense patterns. Unfortunately, the subtractive etch process generally does not provide precise control over circuit path width, due to plating variation and lack of sharply defined path edges. The lack of width control is disadvantageous with current demands for increasingly high component mounting densities that require relatively thin conductive lines placed in close proximity to each other.
Pattern plating, also referred to as acid plate pattern plating, uses electro-plating techniques to deposit conductive lines in circuit paths defined by photo-resist material voids. More specifically, a conductive foil layer on the circuit board is connected to an electrode and the conductive material is deposited onto the board in the resist material voids using an oppositely charged electrode. The width of the conductive lines is generally dependant on the developed photo-resist pattern, which typically is of photographic sharpness. Pattern plating thereby provides good control over circuit path width and permits conductive lines of relatively fine width. The circuit path height, however, is not as easily controlled because such height is dependent on the density of the desired conductive lines. As a result, isolated conductive lines are typically thicker than densely packed (closely spaced) conductive lines. Thus, line height is not precisely controlled by the acid plate process.
The additive (electro-less) plating process is similar to the acid plate pattern process, except that chemical plating processes are used rather than electro-plating processes. Additive plate fabrication generally requires more time to complete as compared to acid plate pattern fabrication but is not as susceptible to circuit path height variation according to line density. Additive plating does occasionally result in copper nodule formation, however.
The surfaces of pattern plated circuit boards need to be planarized prior to successfuil plating. Planarization methods such as surface machining remove non-planar regions of the board. Chemical mechanical polish, another often used method also employed in the semiconductor and ceramic industries, contains abrasive slurry materials which attack both resist and copper surfaces. Such polishing techniques are not compatible with many organic-based substrates, which are often used in conjunction with surface-mount technology circuit boards. Surface-mount technology is gaining in popularity because it permits higher component densities and faster component mounting as compared with more conventional wire-bonding techniques in which it is necessary to electrically interconnect several small contacts and conductor sites with fine, delicate wires. Such polishing techniques are generally incompatible with organic based substrates because such substrates are somewhat flexible and typically have surface undulations. The surface undulations are due to variations in substrate thickness and also to the inherent flexibility of the boards, which permits bowing and warping. Conventional chemical-mechanical polishing techniques will not follow these undulations and contours of flexible substrates. As a result, board areas of extra thickness or that bow outward will be left with conductive lines having areas that are too thin, and board areas of reduced thickness will be left with conductive lines having areas that are too thick.
In U.S. Pat. No. 6,547,974, issued Apr. 15, 2003, there is described producing a PCB using a process which includes patterning a photo-resist layer according to a circuit mask that defines desired circuit paths. The photo-resist pattern layer is formed by removing the photo-resist from the board in the desired circuit paths and a conductive material is plated onto the board in the voids defined by the circuit mask so that the height of the conductive material relative to the substrate equals or exceeds the height of the photo-resist layer relative to the substrate. A low-reactive solution is applied over the conductive material and removes a surface portion thereof. As the solution removes the conductive layer, it forms a film barrier and the solution composition changes, both of which substantially inhibit any further removal of the conductive material. Next, the film barrier is removed from the board allowing another film barrier to form stimulating the removal of further conductive material. The removal step is repeated until the conductive material is at a desired height relative to the height of the resist layer. The board is then finished using conventional circuit board fabrication techniques.
In U.S. Pat. No. 5,502,893, issued Apr. 2, 1996, there is described a PCB manufacturing method in which an organic non-conductive layer does not separate from the PCB's “metal core” (e.g., of aluminum) even in an environment of high temperature and high humidity since both the metal core and the organic non-conductive layer are firmly adhered. An organic non-conductive layer is formed over the metal core with a metal plated layer (e.g., nickel) there-between for protecting the metal core. A metal oxide layer is also used for enhancing adhesive force. By utilizing such a metal oxide layer, it is possible to more effectively prevent the organic non-conductive layer from separating from the plated layer (and thus the metal core). Further, the protecting metal plated layer can protect the metal core from erosion caused by contact with a strong alkali solution, etc. as may be used in a process of forming the metal oxide layer. Still further, copper plating inside the through hole can be performed easily.
In U.S. Pat. No. 5,494,781, issued Feb. 27, 1996, there is described a method for manufacturing a PCB in which there is formed on a top surface of an insulating substrate a layer of plating ground layer as a metal film, irradiating using electromagnetic waves such as provided by a laser, a boundary edge zone of what are referred to as “non-circuit parts” with respect to circuit-printing parts on the insulating substrate in correspondence to a pattern of the non-circuit parts to remove the plating ground layer at the part irradiated by the electromagnetic waves, and thereafter to form a plating on the surface of the plating ground layer at the non-irradiated parts. The apparent result is that the laser irradiation is carried out only with respect to the boundary edge zone of the non-circuit parts, without irradiating all of the non-circuit parts.
In U.S. Pat. No. 5,468,409, issued Nov. 21, 1995, there is described an etching solution for precision etching of vapor-deposited copper films of complex curvature on PCBs. Cupric chloride, sodium chloride and de-ionized water are constituents of the etching solution, which the authors claim are able to produce circuit lines of about three to ten mils.
In U.S. Pat. No. 5,358,622, issued Oct. 25, 1994, there is described a procedure for producing PCBs with pads for insertion of surface-mount devices (called SMDs by the authors). A copper lined base plate is provided with a positive photo-protective layer with a coating thickness lesser or equal to the depth of the pads to be built up for the connection of the SMD components. The positive photo-