Source: {"pile_set_name": "USPTO Backgrounds"}

This invention generally relates to integrated circuits, and more particularly to integrated circuits (ICs) including on-chip inductors.
Low-loss on-chip inductors (i.e., that are integrated on an IC substrate) are desirable in wireless communication devices such as cellular phones, pagers, GPS receivers, warehouse management RF identification tags, wireless computer local area networks (WLANs), personal digital assistants, and satellite telecommunication. Small portable devices, in particular, require the lowest possible power consumption for extended battery life and a maximal circuit integration to reduce device size and PC board complexity. The quest for low-loss inductors is driven by a fundamental trade-off between power consumption on one hand and the need for low-loss circuit passives (i.e., inductors and capacitors) on the other. Lowering the transistor bias in radio circuits reduces the power dissipation, but also significantly degrades amplifier gains, oscillator stability and filter selectivity. Using low-loss passives is the only viable technique to overcome this problem. However, many state-of-the art integrated coil architectures are still too lossy to be of use in integrated RF designs. Most present RF chipsets, therefore, are limited to using discrete inductors that take up valuable board space and increase board complexity. In addition, connections must be provided between an IC device and the discrete inductors, thereby requiring an IC package with a higher pin count (i.e., to support a connection between the IC device and the discrete inductors) than that required if the inductors were integrated (i.e., fabricated directly on) the IC device. Higher pin count IC packages are typically larger and more expensive than lower pin count packages.
Accordingly, the integration of small inductors on silicon substrates has been the subject of intense worldwide research for many years. The structures proposed so far, however, have been variations of devices in which, due to technological constraints, the coil windings have almost always been implemented as spirals parallel to the underling substrate.
FIG. 22 is a perspective view showing a simplified in-plane spiral coil winding 2200 formed on an IC substrate 2210, which in turn is mounted on a package or printed circuit board (PCB) 2220. Note that coil winding 2200 is substantially disk-shaped, and lies in a plane that is parallel to the upper surface of substrate 2210. Contact pads 2212, which are formed on the upper surface of IC substrate 2210, are connected by conventional bonding wires 2215 to corresponding pads 2222 formed on package/PCB 2220.
FIG. 23 is a perspective cut-away view showing a portion of in-plane coil winding 2200 and indicating the magnetic fields (i.e., dashed lines) generated in the vicinity of coil winding 2200 during operation. This figure illustrates two major drawbacks of in-plane coil winding 2200. First, when substrate 2210 is conducting, such as silicon, the coil magnetic fields (dashed lines in FIG. 23) induce eddy currents in underlying substrate 2210. These currents cause resistive dissipation that contributes to the coil losses. The second problem arises when coil winding 2200 is operated at high frequencies, where skin and proximity effects force the coil current to flow along the outer surfaces A05 of coil winding 2200 (as indicated by shaded regions located at the outer edges of coil winding 2200). The xe2x80x9cskin depthxe2x80x9d is about 2 to 3 microns for typical conductors at frequencies of interest for wireless communication, for example, 900 MHz, 1.9 GHz and 2.4 GHz. The AC resistance of the coil conductor becomes appreciably higher than its DC resistance because the cross section of the conductor is not fully used.
Solutions have been proposed and tried in the past to address the drawbacks associated with in-plane inductors. Eddy currents can be reduced, for example, by etching away the substrate underneath the coil. However, this approach is not practical as it sacrifices structural integrity and impedes placing electronic circuitry on the substrate underneath the coil, thereby wasting expensive silicon real estate. As coil quality factor fundamentally scales with the coil dimensions, coils tend to be much larger than the other circuit components. To reduce the AC resistance of the device in FIG. 23, the conductor can be made very thick using micromachining techniques such as LIGA (see xe2x80x9cThe LIGA Techniquexe2x80x94What are the New Opportunitiesxe2x80x9d, A. Rogner et al., J. Micromech. Microeng., vol. 2, 1992, pages 133-140). However, processing high aspect ratio structures is difficult and expensive.
Various out-of-plane techniques have been suggested that address the induced current eddy problems of in-plane coil: structures. One such out-of-plane miniature coil structure that can be used as an on-chip inductor is disclosed in co-owned U.S. Pat. No. 6,392,524, entitled xe2x80x9cPhotolithographically-patterned out-of-plane coil structures and method of makingxe2x80x9d. The coil structure includes a lithographically produced elastic member having an intrinsic stress profile that is formed on the IC substrate. An anchor portion remains fixed to the substrate. The free portion end becomes a second anchor portion that may be connected to the substrate via soldering or plating. Alternately, the loop winding can be formed of two elastic members whose free ends are joined in mid-air. A series of individual coil structures can be joined via their anchor portions to form out-of-plane inductors and transformers.
Although out-of-plane coil structures, such as those disclosed in U.S. Pat. No. 6,392,524, reduce capacitive substrate coupling and minimize eddy current induction by taking the bulk of the magnetic fields out of the underlying substrate, the residual magnetic coupling leads to some level of performance degradation that is only avoided with toroidal out-of-plane microcoil structures.
What is needed is an out-of-plane solenoid-type microcoil structure that minimizes performance degradation caused by both capacitive substrate coupling and eddy current induction.
The present invention is directed to integrated circuit (IC) devices including an out-of-plane solenoid-type microcoil structure formed over an IC substrate, wherein one or more ground plane structures are provided on the IC device to reduce losses caused by capacitive coupling of the microcoil structure to the IC substrate, and to reduce magnetic losses due to eddy currents generated in the IC substrate by magnetic fields produced by the microcoil structure.
Each out-of-plane solenoid-type microcoil structure is formed on a suitable dielectric layer (e.g., Benzocyclobutene: (BCB) formed on passivation, or a relatively thick passivation layer), which in turn is formed over the IC structure. The microcoil structure includes several base (contact) portions that are formed on the upper surface of the dielectric layer, and several loop structures extending over the dielectric layer and connecting the base pads in series. Contact pads located at each end of the microcoil are connected by via structures extending through the dielectric layer to the underlying IC structure.
In accordance with a first aspect of the present invention, the ground plane structure is formed directly under the base pads of the microcoil to minimize capacitive coupling between the microcoil loop structures and the IC substrate. In one embodiment, the ground plane structure is formed using the top metal layer of the underlying IC structure. In another embodiment, the ground plane structure is formed using a low-resistance plated layer (e.g., copper) formed on the upper passivation layer of the IC substrate (i.e., between the passivation layer and a separate dielectric film upon which the microcoil is formed). In either embodiment, a width of the ground plane structure may be less than a diameter defined by the microcoil loop structures.
In accordance with a second aspect of the present invention, a low-resistance ground plane structure is provided between the passivation layer and the separate dielectric film of the dielectric layer, and extends past the end loop structures of the microcoil to reduce eddy current dissipation in the underlying IC substrate. In one embodiment, the ground plane structure comprises a sheet of low-resistance material (e.g., copper) that is formed between the upper passivation layer and the dielectric film, and has a peripheral boundary that extends well beyond the sides and ends of the microcoil, thereby allowing eddy currents to run freely without causing significant losses and minimizing magnetic coupling between the microcoil and the IC substrate. In another embodiment, the ground plane structure is slotted in a direction parallel to the microcoil axis to reduce the loop size of eddy current pathways induced by the microcoil. In another embodiment, the ground plane structure is xe2x80x9cIxe2x80x9d shaped, and includes end sections extending beyond the ends of the microcoil to reduce eddy currents, and a narrow section extending under the base pads between the end sections to reduce capacitive coupling.
The present invention is applicable to any of several out-of-plane solenoid-type microcoil structures, including microcoil structures in which both the base pads and loop structures are formed from a stress-engineered spring metal film (i.e., a metal film intentionally formed with an internal stress gradient), microcoil structures formed using wire bonding techniques to connect base pad traces formed on the dielectric layer, and planar spiral inductors that are mechanically lifted out of the substrate plane. In one embodiment, the spring metal film is etched to form spaced-apart (offset) islands, each island including a central base pad and two fingers extending in opposite directions away from the base pad.