Source: {"pile_set_name": "USPTO Backgrounds"}

1. Field of the Invention
The invention relates to a method for misalignment/alignment compensation, and more particularly to a misalignment/alignment compensation method, a system and a patterning method for a semiconductor process.
2. Description of the Related Art
A semiconductor process refers to a process used to create a large number of semiconductor devices on a wafer using a multiple-step sequence of photolithographic and chemical processing steps. In such a highly-laminating process, when one of laminated layers is misaligned, the subsequent layers may thus be affected and further misaligned, thereby leading to failure of electrical connections among semiconductor devices and the layers, function losses, or short circuits. Therefore, precise and stable overlay control is a relatively important factor for process management to ensure yield of the semiconductor devices and efficiency of production.
For example, a conventional step-and-repeat aligner (i.e., a stepper or scanner) usually has an alignment sensor for detecting alignment marks that are disposed at specific locations of a wafer before a lithography exposure process, and an alignment offset of the aligner may be calculated according to the detected misalignment/alignment. If a subsequent rework process is required for the wafer, the overlay offset may be used to calibrate the aligner for ensuring optimal alignment between patterns of a current patterning layer (or an upper layer) and a previous patterning layer (or a lower layer).
Conventionally, the alignment or overlay offset is obtained by using the overlay misalignment data in symmetry or independent calculation in both X-direction and Y-direction, which is unable to satisfy asymmetry overlay compensation requirements between the X-direction and the Y-direction, especially in advanced process generation with single orientation layout for resolution consideration. Referring to FIG. 1 as an example, in a common process of fabricating metal-oxide-semiconductor (MOS) devices, a required overlay distance or alignment margin x between a contact hole 11, and an edge of a diffusion region 12, is different from a required distance or alignment margin y between the contact hole 11 and a poly gate 13. Since the overlay distance requirement or alignment margin x in the X-direction and the overlay distance requirement or alignment margin y in the Y-direction are different (in FIG. 1, x<y), a theoretical weight of an offset in the X-direction should be greater than that in the Y-direction. However, conventional calculations of the overlay offset uses symmetry or independent calculation for compensations in the X-direction and the Y-direction, which is not suitable for a structure that has asymmetric alignment requirements in the X-direction and the Y-direction, and which may result in non-optimization of alignment or non-optimization of the overlay offset after compensation. For example, a short circuit risk may occur between the contact hole 11 and the poly gate 13, as shown by an overlap of a dotted circle and the poly gate 13 in FIG. 1.