Source: {"pile_set_name": "USPTO Backgrounds"}

The process of production of semiconductors includes processing of a circular silicon wafer typically 8" in diameter. The processing includes repetition of series of steps: oxidation and deposition; lithography; etching; and doping (implanting and diffusing). Depending on the maturity of the production process used, the wafer might be inspected for particles/production defects, mask alignment and critical dimension metrology between the processing steps. The frequency of inspection can be as often as every wafer in the development phase of a process, or on wafers from alternate production lots from mature processes.
Particle (production defect) detection detects either the presence of contaminant particles introduced in the manufacturing process, or areas where processing has been defective so as to produce unwanted features in the structures of the device. Current methods of particle detection, such as those provided by Tencor Instruments or KLA Instruments, involve obtaining topological information from the surface of the wafer using optical techniques as described in U.S. Pat. Nos. 4,347,001; 4,378,159; 4,755,874; 4,766,324; 4,845,558; 4,898,471; 5,030,008; 5,131,755; 5,264,912; 5,276,498; 5,355,212; 5,416,594,5,438,413 and European Patent Application 624787A, or topographical imaging scanning electron microscope techniques, such as the KLA SEMSpec system or those techniques described in JP 61 88294
These current techniques make no distinction between defects (particles) which will affect the operation of the completed integrated circuit (IC), which are known as "killer" defects, and those which have no detrimental effect, known as "nuisance" defects. Since nuisance defects can account for 90% of detected defects, some form of review is required to ensure that wafers which would otherwise produce acceptable yields of operational ICs are not rejected. This review is currently a manual operation. Defects are classified by inspection of an image of the wafer including the defect identified by the inspection system. Review is typically performed on optical or scanning electron microscope (SEM) review stations. Operators classify and tabulate defects based on prior experience and defect location. Relatively slow, manual, defect classification is the only current way to reduce the number of nuisance defects affecting wafer yields. This process still gives no direct information as to whether a defect will affect the performance of a completed device.
These methods also suffer from the problem that they cannot detect defects which are invisible from the surface, be they nuisance or killer. Invisible killer defects include problems such as open vias, incomplete via holes and gate oxide integrity problems. All of these can result in an inoperative device but are undetectable with present in-line defect detection systems. Furthermore, as the geometries of semiconductors become smaller, optical techniques become less useful due to accuracy being limited by the optical diffraction limit of resolution. It is believed that for 0.25 .mu.m geometry integrated circuits, less than 50% of killer defects commonly encountered in a semiconductor manufacturing process are observable using optical techniques, even when operating in the short wavelength UV range. Optical techniques also operate less successfully after chemical mechanical polishing steps due to the formation of a planar surface which means that defects are less likely to scatter light, a key factor in some optical defect detection methods.
SEM-based inspection systems have been proposed using die-to-die comparison methods. Such systems are optimized to obtain topographical information. Known techniques have small pixel size (0.1 .mu.m) and consequently very long inspection times, of the order of 10 to 80 hours for a complete wafer. This, combined with a high incidence of nuisance defect detection makes such techniques undesirable for production uses. Topographical data also does not reveal hidden defects and so suffers from the drawbacks of optical methods. It has been previously proposed to use an electron beam prober to obtain voltage contrast images of wafers. However, these techniques are slow since they require the electron beam to be scanned over the wafer several times before a good image can be obtained.
SEMs, and electron beam probers, a variant of the SEM well known for functional probing of structures in integrated circuit devices, are also often used to obtain voltage contrast images of devices. In a voltage contrast image, the voltage of a structure being imaged determines the brightness of that structure in the image. This is achieved by using a filter electrode grid to control the detection of secondary electrons depending on their energy so as to enhance the voltage contrast. Such an approach has been used to image test structures formed in the wafer as an indicator of the reliability of the manufacturing process.
SEMs have been used to detect invisible faults in the part-finished multi-chip module substrates (MCMs) and examples of these techniques are found in U.S. Pat. No. 4,415,851, U.S. Pat. No. 4,417,203 and U.S. Pat. No. 4,443,278. These patents describe a technique in which a 2 keV electron flood gun is used to apply charge to the conductive nets of an MCM substrates, the nodes of which are then examined using an electron beam probe which is vectored from node to node to measure the voltage present at the nodes and discharge the nets. The voltage measurements are used to indicate the presence of faults in the nets. The MCMs examined with this technique are intended to locate and connect a number of completed IC devices. Similar techniques using higher and lower energy flood guns to pre-charge the conductors have been applied to MCMs
It is an object of the present invention to provide a system suitable for inspecting semiconductor wafers which does not suffer from the deficiencies of known optical systems outlined above and which is capable of revealing hidden defects.