Source: {"pile_set_name": "USPTO Backgrounds"}

1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor package, and a molding apparatus used in the method, and more particularly, to a method of manufacturing a wafer-level chip-size package, and a molding apparatus used in the method.
2. Description of the Related Art
In keeping with the trend toward miniaturization in the development of electronic devices, i.e., the trend toward making ever smaller and ever thinner packages, wafer-level chip-size packages. Such packages, which are about the same size as the incorporated semiconductor chips and which are substantially complete before being separated from the wafer, have been the subject of increasing interest. During the manufacture of a wafer-level chip-size package, typically both a rewiring process and an encapsulating process are performed while the chips remain in a wafer state, after which the individual chip packages are separated from the wafer using a dicing process.
If a thin wafer is used for making a wafer-level chip-size package, the wafer tends to have insufficient strength and is more susceptible to deformation such as bending and/or warping. Both the likelihood and seriousness of such wafer warping formation tends to increase as the diameter of the wafer increases. Similar problems are associated with larger semiconductor chip geometries which may experience or be susceptible to chip warping. Both wafer warping and/or chip warping are detrimental to the fabrication process and tend to decrease the overall process yield and may degrade the quality and reliability of the wafer-level chip-size packages that are produced.
In particular, conventional wafer-level chip-size packages are susceptible to wafer warping because only the front surface of the wafer is molded using an encapsulant. Further, when a wafer is molded only on its front surface, the edges of chips of the wafer may be more susceptible to cracking or chipping during the subsequent dicing processing and associated handling. Moreover, conventional wafer-level chip-size packages having and encapsulant layer provided only on the front surface tend to be more susceptible to semiconductor chip cracking resulting from impacts associated with the handling during subsequent wafer level testing, board mounting processes and package test processes.