Source: {"pile_set_name": "USPTO Backgrounds"}

The present invention relates to frequency synthesizers in general, and more particularly, to a frequency synthesizer that produces an output pulse based upon a mathematical calculation with the output pulse synchronized to an input pulse train on a pulse-by-pulse basis.
In image processing applications it is often desirable to alter the size of a scanned image on a real-time basis. Generally such a process is referred to as image magnification. However, the actual theory and hardware described herein functions in a manner to provide changes from 1X to some fraction of 1X in the size of the original copy. Thus, the concept of changing the size of an image becomes a demagnification exercise. The problem of adjusting the size of an image to a value greater than 1X is accomplished by employing an additional pre-processing step of 2X, or greater, enlargement, and then de-magnifying that intermediate result to obtain the desired output size.
The concept of demagnification is related to deriving a preselectable output frequency from a given input frequency. Basic demagnification can be accomplished by employing a standard phase locked loop (PLL) design that contains a feedback counter functioning as a programmable divider. Commercial radio equipment employs this technique to derive different transmit and/or receive frequencies.
The problem, however, is that in a PLL system with divide by N counter feedback, only a very limited (relatively speaking) number of output frequencies can be realized. The PLL technique requires that the feedback counter be some integer value. This integer value constructs the new output frequency, as a function of the designed channel spacing.
Some image processing applications require that extremely small, and in some cases, non-integer value channel step sizes, be employed to process real time picture information and to reduce this copy in increments of 0.1 percent. A conventional PLL cannot be used in these applications. Furthermore, in addition to the limited number of output frequencies available from a PLL, the output pulse inaccuracies present when a PLL system is searching for lock, are intolerable in such applications.
It is accordingly a general object of the invention to provide an improved frequency synthesizer.
It is a specific object of the invention to provide a frequency synthesizer that produces an output pulse based upon a mathematical calculation that is synchronized to an input pulse train on a pulse-by-pulse basis.
It is a feature of the invention that the frequency synthesizer produces an output pulse train having a frequency that is a selected fractional percent of the frequency of the input pulse train.
It is another feature of the invention that the invention can be implemented with conventional and readily available electronic components.