Source: {"pile_set_name": "USPTO Backgrounds"}

The present invention relates to the field of measuring propagation delay, and more particularly, to measuring such delays with circuitry embedded in semiconductor chips.
All electrical signals transmitted through a conduction path experience a propagation delay. Propagation delays generally result from properties of the conduction path such as load capacitance and signal line length.
Propagation delays affect systems differently depending upon the nature of those systems, but most systems can be affected adversely by relative propagation delay, which is the difference in propagation speeds between two paths. For example, in synchronous (clocked) circuits, differences in propagation delays between clock signals on different lines leads to clock skew, which degrades the performance of the circuit. Likewise, in high-performance, asynchronous (non-clocked) pipelines, knowing the relative propagation delay between the control and data signals is an important step in ensuring that the signals arrive in their correct order at a pipeline stage.
Therefore, accurate measurement of propagation delay on a semiconductor chip is desirable when designing and testing fabricated semiconductor chips. Conventional technologies for measuring propagation delay time typically involve on-chip probing techniques. Usually, these techniques involve physically inserting a probe at points on the chip that are to be tested.
Today's high-speed semiconductor circuits may experience delay times in the sub-nanosecond or picosecond range. The shortness of these delay times makes accurate measurements exceedingly difficult, even with the most advanced on-chip probing techniques. There is a need, therefore, to accurately and reliably measure absolute and relative signal path propagation delay times on a semiconductor chip.