Source: {"pile_set_name": "USPTO Backgrounds"}

1. Field of the Invention
This invention relates to electronic systems and, more particularly, to methods and apparatus for providing an off-chip driver circuit implemented in complementary metal oxide silicon (CMOS) technology which has a supply voltage less than the supply voltage of external circuits which may be connected to the output of the driver circuit.
2. History of the Prior Art
In modern day integrated circuits much attention is focused on the design of output driver circuits that must provide signals to various bus types having various loading conditions. An off-chip driver circuit should be designed not only to successfully drive logic levels relating to the supply voltage of the off-chip circuit but should also be protected against any high voltages which may occur when the off-chip driver circuit is disabled and its output terminal is coupled to an external circuit operating at a higher supply voltage. It is desirable to provide this protection while minimizing the number of transistors and therefore the chip area utilized by the off-chip driver.
FIG. 1 is a circuit diagram of a known off-chip driver circuit 10. This circuit is described in U.S. Pat. No. 5,151,619 assigned to International Business Machines Corporation. The off-chip driver circuit 10 has first and second input terminals IN1 and IN2 which are connected to a pre-driver circuit (not shown). The off-chip driver circuit 10 is arranged to drive a signal received at the input terminals IN1 and IN2 to an output terminal OUT during an output mode. The off-chip driver circuit includes a first p-channel MOS transistor device 12 and a second n-channel MOS transistor device 14 which are serially arranged between a supply voltage Vdd and a point of reference potential Vss (which is typically at ground). The output terminal OUT is connected to a circuit node between the pull-up transistor 12 and the pull-down transistor 14. A pass gate 16 is formed by a n-channel transistor device 18 having its gate connected to the supply voltage Vdd and its drain/source path connected between the input terminal IN1 and the gate of the pull-up transistor 12. The n-channel transistor 18 acts in parallel with a p-channel transistor device 20 having its drain/source path connected to the same nodes and its gate connected to the output terminal OUT.
The pull-down transistor 14 has its gate connected to the second input terminal IN2. The off-chip driver circuit 10 includes a control transistor device 22 which has its gate connected to a control voltage Vref (typically equal to the source voltage Vdd) and its drain/source path connected in series between the pass gate p-channel transistor 20 and the output terminal OUT. The p-channel transistor 20 and the control transistor 22 are formed in a common n-well 26. An additional p-channel transistor device 24 has its gate connected to the terminal OUT to provide the supply voltage Vdd to bias the n-well 26 in certain conditions.
The off-chip driver circuit 10 has its output terminal OUT selectively connectable to an external circuit 28 which has a supply voltage Vcc and which is used in an input mode of the off-chip driver circuit 10 to supply signals to the chip via the output terminal OUT which is connected to an input signal line (not shown).
The voltage supply Vdd for the off-chip driver circuit 10 is typically about 3.3 volts+/-0.3 volts. However, the external circuit 28 may operate at a higher source voltage such as a conventional CMOS level of five volts. When used as an off-chip driver circuit, the circuit 10 should be capable of driving the output terminal OUT at zero volts to indicate a logical zero or 3.3 volts to indicate a logical one. However, when the circuit 10 is not driving out, it must be able to tolerate voltages as high as seven volts at the terminal OUT.
When the off-chip driver circuit is used in the output mode, the same signal level is applied at each of the first input terminal IN1 and the second input terminal IN2 to provide an output level at output terminal OUT. As is more fully discussed in the above-referenced U.S. Pat. No. 5,151,619, with the input terminals IN1 and IN2 low (typically ground), the voltage at the output terminal OUT is at the source voltage Vdd. With the input terminals IN1 and IN2 high (typically 3.3 volts), the voltage at the output terminal OUT is a low voltage (approximately ground). To disable the output mode of the off-chip driver circuit 10, the pre-driver circuit which furnishes input signals to the first and second input terminals IN1 and IN2 is tristated by driving the first input terminal IN1 high and the second input terminal IN2 low. In this condition, both the pull-up p-channel transistor 12 and the pull-down n-channel transistor 14 are off.
The circuit 10 of FIG. 1 is designed to receive signals at the terminal OUT when in this disabled condition. With a voltage of zero volts at the output terminal OUT, the pass gate p-channel transistor 20 is turned on and passes the 3.3 volts present on the first input terminal IN1 to the gate of the pull-up transistor 12, turning the transistor 12 off. Thus, there is no leakage current through the pull-up transistor 12. When a high voltage, for example five volts, is applied to the output terminal OUT by the external circuit 28, the p-channel pass gate transistor 20 is turned off. However, the p-channel control transistor 22 is turned on because the voltage applied at its source exceeds the control voltage Vref (3.3 volts) at its gate. The path through the transistor 22 furnishes the voltage at the output terminal OUT to the gate of the pull-up p-channel transistor 12, turning it off. In this condition, the voltages at the gate and the source of the p-channel transistor 12 are approximately the same; and, consequently, the oxide of the p-channel transistor 12 is not subject to any significant stress. Therefore, in the disabled condition when the likely extreme values of voltages are imposed by the external circuit 28, the prior art circuit 10 of FIG. 1 works well.
However, problems arise both when voltages at the terminal OUT are at middle values between the extremes and during transition states. When the value of the voltage at the terminal OUT is in a range between the reference voltage (Vref) minus the p-channel threshold voltage (Vpt) and Vref plus Vpt, neither the pass gate transistor 20 nor the control transistor 22 is on. In this range, the voltage at the gate of the pull-up transistor 12 is not tracking either the supply voltage Vdd or the output voltage. This can cause leakage current to be referred to the input of the circuit 10 from the device 12. This leakage can cause specification violation in certain applications such as PCI drivers where the input leakage must be below seventy microamperes with the input in a range from zero to five volts.
For example, in order to turn the control transistor 22 on, the voltage at the output terminal OUT must be at least a threshold voltage Vpt above the control voltage Vref at the gate of the control transistor 22. If this condition is not satisfied, the control transistor 22 will remain off. If the voltage at the terminal OUT is slightly above or slightly below the reference voltage (normally 3.3 volts), the voltage is neither low enough to turn on the p-channel pass gate transistor 20 nor high enough to turn on the control transistor 22. Thus, both the transistors 20 and 22 are off. The n-channel transistor 18 of the pass gate will try and pull up the gate of the p-channel transistor 12, but it will be only able to pull it up to a threshold value Vnt below the voltage on the input IN1 (about 2.6/2.7 volts). This is inadequate to reliably turn off the pull-up p-channel transistor 12, and therefore there will be a leakage current through that transistor. Thus, with voltages at the terminal OUT closer than a threshold Vpt to the supply voltage Vdd, the prior art circuit 10 has a major disadvantage.
One solution to the problem is proposed in an article entitled "3.3 V-5 V Compatible I/O Circuit without Thick Gate Oxide" by Takahashi et al, IEEE 1992 Custom Integrated Circuits Conference 23.3.1-23.3.4. In that solution, different types of transistors are introduced to exclude undesirable leakage paths and to prevent oxide stress. This solution suffers from the disadvantage that it requires different fabrication techniques to produce the entire circuit, an expensive option.
Another problem displayed by the circuit 10 is that the p-channel device 12 does not provide any electrostatic discharge (ESD) clamping action for over-shoot conditions of any voltage present at the terminal OUT. Since the device 12 is held off under all over-shoot conditions of the voltage at the terminal OUT, the device 12 can not be used to clamp the output when electrostatic discharge occurs (in conventional output drivers the output devices and junction diodes are combined to reduce damage from electrostatic discharge). With this prior art circuit 10, additional devices (not shown) must be added to eliminate problems caused by electrostatic discharge; and this addition results in the circuit 10 occupying additional silicon area.
The circuit 10 also includes a method for isolating the n-well of the p-channel devices when the P+/N- diodes would otherwise be forwarded biased resulting in leakage current. P-channel transistor device 24 acts as a switch between the positive supply Vdd and the well bias source. The device 24 is directly controlled by the voltage at the terminal OUT and is disabled when the input voltage at the OUT terminal comes within a threshold voltage Vpt of the 3.3 volt source voltage therefore eliminating the leakage path to the well before the diodes can