Source: {"pile_set_name": "USPTO Backgrounds"}

The present invention relates to semiconductor memories. In particular, the present invention relates to semiconductor memories having redundancy thereon. In particular, the present invention relates to semiconductor memories which are organized to output more than one bit simultaneously, e.g. to a memory which is organized according to nine-bit bytes, so that each read cycle provides nine bits of information simultaneously at nine I/O pads.
As is well known in the art, there are substantial advantages to byte-wide memory organization. ("Byte-wide" is frequently used to refer only to by-8 memories, but is used in the present application to refer to any memory which is more than one bit wide.) This reduces the board-level overhead, and in general provides additional convenience to the system-level designer.
A further known desideratam in large memories is redundancy. Most bad memory chips at reasonable maturity of process have only a few bad bits. If these bad bits can be replaced by redundant elements, yield improvement can be obtained. Initially when yields with an aggressive design are small, redundancy can enhance the yield by as much as an order of magnitude. Even in a mature product the loss in yield due to increased chip area is likely to be offset by yield improvement due to repaired chips.
Memory chips which are organized as byte-wide are particularly desirable for small systems. Where the whole memory requirements of a sub-system can be satisfied with, e.g., three or four 64k memory chips, it would be exceedingly wasteful to go to a memory board using a by-one organization. A further advantage of byte-wide chips from a designer's point of view is in expandable memory configuration systems. That is, where a board can be used with various memory size options, and the smallest option is at most a small multiple of the number of bits per chip, it is much more efficient from the system designer's point of view to be able to use byte-wide memory chips.
One method of implementing redundancy in a byte-wide memory would be to have a whole redundant block, which could be substituted for one redundant bit position. That is, for example, in a 4k.times.9 half-array, one entire 16 column by 256 row block could be provided as a redundant bit position which could be substituted for any bit position which happens to contain one or more defects. However, this approach is not only tremendously wasteful of area, but also would not solve the problems of defects in more than one bit position.
It is desirable to minimize the row decode delays, which means (preferably) minimizing the length of word lines. In a large memory, this means that the memory is preferably partitioned in subarrays. This in turn means that redundancy is preferably provided separately for each subarray. The present invention could be implemented in an embodiment where a redundancy block was shared between subarrays, but this is not preferable due to the increased complexity of wiring, and at chip-level logic (i.e. subarray-select logic).
A byte-wide memory could be organized as, for example, two half-arrays each containing nine bit positions. Each "bit position" is a set of 16 columns side by side, all of these columns (with their respective 16 primary sense amplifiers) being multiplexed into a secondary sense amplifier corresponding to that bit position. Thus, where there are 256 rows, each half array contains 16.times.256 nine-bit words and each of these words can be provided from the half array as a completely parallel output.
However, there have heretofore been difficulties in combining these two improvements. That is, it has not been practical to configure a byte-wide memory having redundancy.
Thus it is an object of the present invention to provide a byte-wide semiconductor memory having redundancy.
A problem in the prior art of redundant memory circuits is the conservation of wiring space. Redundant memory designs have typically been modifications of memory designs which do not incorporate redundancy. This subsequent modification of an existing design is likely to induce great pressure on the available wiring space on the chip.
It is an object of the present invention to provide a memory, incorporating redundancy, which requires only a minimal amount of metal wiring to embody the redundancy.
In particular, it would be relatively simple to provide one redundant column for each bit position, but this approach is far from optimal, for a least two reasons. First, this occupies an excessive amount of real estate with redundancy circuits. That is, in an 8k.times.9 memory at least nine redundancy circuits would be required (or, even worse, 18, if each bit position includes columns in each half-array), rather than the 2 or 3 redundant columns per array unit which would otherwise be desirable. A second problem is that this approach would be hopeless in the case where more than one defective column is found within a single bit position. That is, in a 4k.times.9 half array, of those half arrays which have exactly two defective columns, approximately one-ninth of them will have the two defective columns located in the same bit position. Thus, a significant fraction of defect cases could not be fixed by this approach.
A further reason for using column redundancy rather than row redundancy is that upper-level metal patterning is typically a lower-yielding process than polysilicon, polycide or first-level metal patterning. That is, upper level metal patterning is not only subject to much more topographic excursion, but metal patterning in general is less intimately involved in cell area and is therefore typically not as intensively refined as polysilicon patterning processes. Thus, patterning defects which will cause a whole column of the memory array to fail are more likely than patterning defects which will cause a whole row to fail. That is, defective bits are not randomly distributed, but exhibit an anomalous correlation along the column access, and the redundancy mechanism should replicate this for optimal efficiency.
In conventional memory architecture, column redundancy is generally preferable to row redundancy. That is, metal is typically used for the bit lines, whereas the word lines are usually made of polysilicon or some other higher-resistance material. Thus, the bottleneck in access time is the row line delays. Thus a small amount of logic can be incorporated in the column-selection circuitry without increasing the total accessing delay of the memory, whereas no such additions can be made to the row-line logic. For this reason, it is preferable to incorporate both the logic for byte-wide parallel access and also the logic for redundancy in the column organization. It would obviously be easier from a design standpoint to organize these along orthogonal axes of the array, but this would increase the total delay of the memory, and is therefore not acceptable. However, it should be noted that, even if the physical organization of these elements can not be orthogonal, their functions are properly orthogonal. That is, a redundant column should preferably be capable of substitutions for any column in any bit position in the array, and multiple redundant columns should be capable of independent substitution decisions, including substitution for multiple columns at a single bit position of the array.
It is an object of the present invention to provide a semiconductor memory having byte-wide organization by columns and also having redundant columns which can each be substituted for any defective columns within any one of multiple bit positions.
It an object of the present invention to provide a semiconductor memory organized in sub-arrays each containing columns corresponding to two or more bit positions, and each subarray containing a plurality of redundant columns which can each be substituted for a defective column in any bit position of that sub array.
One important constraint on the memory system which incorporates redundant columns available to any bit position in a byte-wide memory is the relative timing between select and deselect. It is important that the defective column be deselected before it can again provide erroneous output information, when its address is accessed. That is, it is desirable that the defective column should be disabled before the row access time has elapsed. It is also preferable, to avoid excessive delay, that the redundant column should be enabled before the row access time has elapsed. Finally, it is also desirable that the defective bit position be disabled before the redundant column is enabled. This is not strictly necessary, but is a desirable precaution to avoid the possibility of the sense amplifier of the defective column fighting against the sense amplifier of the redundant column, which could lead to excessive current on the buss and possible damage to the devices.
It is an object of the present invention to provide a semiconductor memory having byte wide column organization and column redundancy, wherein a predetermined defective column position is always disabled prior to enablement of a redundant column which replaces that defective column position.
Many of the problems of redundant memories are most easily solved in laser-selected redundancy, wherein a laser (or electron beam) can destroy inter-connects or devices at essentially any position on the chip. That is, the problem of overhead circuitry is immensely simplified when the whole chip area can be spatially addressed during an independent redundancy programming process, and high-current pathways can be made or broken. However, the problem with such approaches is that they require an expensive and slow processing step which is preferably performed prior to final packaging of the device. Thus, not only is throughput greatly degraded, which sacrifices many of the advantages of redundancy programming in the first place, but since subsequent processing is required after redundancy programming, defects which first manifest themselves during the subsequent processing steps may not even be compensated for or even detected.
The alternative to such externally spatially-addressed redundancy programmation schemes is electrical redundancy programmation typically using a fuse-blowing operation. That is, after the chip has been probed, on-chip fuses using thermal-write/electrical read mechanisms (such as blowing a thin polysilicon fuse link or spiking through a junction) are used to change the static voltage on certain circuit nodes. (This can even be done after final packaging, if sufficient pin-outs are provided, but is preferably done at the multiprobe stage.) Not only are these electrically written