Source: {"pile_set_name": "USPTO Backgrounds"}

1. Field of the Invention
The present invention relates to a wafer scale integration semiconductor device (referred to as WSI semiconductor device hereinafter) comprising a plurality of semiconductor circuit chips all integrated on one wafer and more particularly, to a circuit for supplying a power-supply voltage to each of the semiconductor circuit chips.
2. Description of the Prior Art
As an example of a WSI semiconductor device, a Full-Wafer MOS RAM is described in IEEE JOURNAL OF SOLID STATE CIRCUITS, VOL. SC-15, NO. 4, AUGUST 1980 and DIGEST OF TECHNICAL PAPERS in ISSCC 79, pp. 18-19.
FIG. 1 is a diagram showing a structure of a Full-Wafer MOS RAM (Metal Oxide Semiconductor Random Access Memory).
Referring to FIG. 1, a lot of RAM chips 2 are formed on a wafer 1. Each of the RAM chips 2 comprises a V.sub.CC power supply line coupled to a power-supply voltage V.sub.CC and a V.sub.SS power supply line coupled to a ground voltage V.sub.SS. The V.sub.CC power supply lines in the RAM chips 2 are coupled to each other by an aluminum interconnection 3 and connected to a V.sub.CC power supply terminal 4. The V.sub.SS power supply lines in the RAM chips 2 are coupled to each other by an aluminum interconnection 5 and connected to a V.sub.SS power supply terminal 6. In addition, each of the RAM chips 2 comprises an address line and a control line. The address line and the control line in each of the RAM chips 2 are coupled to each other by another interconnection (not shown) and connected to a common address terminal and a common control terminal, respectively.
FIG. 2 is a diagram showing one of the RAM chips 2 shown in FIG. 1.
Referring to FIG. 2, an MOS circuit 7 constituting a RAM (Random Access Memory) is formed on the RAM chip 2. In addition, a power supply terminal 8 coupled to a power supply voltage V.sub.CC and a ground terminal 9 coupled to a ground voltage are formed on the RAM chip 2. The power supply terminal 8 is connected to the MOS circuit 7 through a V.sub.CC power supply line 10, and the ground terminal 9 is connected to the MOS circuit 7 through a V.sub.SS power supply line 11.
In the above described Full-Wafer MOS RAM, when the power-supply voltage V.sub.CC is applied between the V.sub.CC power supply terminal 4 and the V.sub.CC power supply terminal 6, the power-supply voltage V.sub.CC is applied to each of the RAM chips 2 through the aluminum interconnections 3 and 5, so that each of the MOS circuits 7 is operated.
However, in the above described conventional WSI semiconductor device, if and when an electrically short-circuited state as represented by a resistor 12 exists between the V.sub.CC power supply line 10 and the V.sub.SS power supply line 11 in one of the RAM chips 2 on the wafer 1, excessive short-circuit current flows in the RAM chip 2. Therefore, the power-supply voltage drops, so that a power-supply voltage at a normal level is not applied to the other normal RAM chips 2. Furthermore, if the power-supply voltage continues to be applied to one of the RAM chips 2 on the wafer 1 with the electrically short-circuited state existing, an external power supply which applies the power-supply voltage is destroyed. Thus, if one of the semiconductor circuit chips on the wafer is defective, the entire WSI semiconductor device can not be used.