Source: {"pile_set_name": "USPTO Backgrounds"}

Referring to FIG. 1, a block diagram of a circuit 10 illustrating a conventional approach to providing a 2-input phase-locked loop is shown. The circuit 10 generally comprises a phase frequency detector (PFD) 12, a charge pump 14, a voltage controlled oscillator (VCO) 16, a loop filter 18, a feedback counter 20, and an input multiplexer 22. The phase frequency detector 12, the charge pump 14 and the VCO 16 provide the basic components of a standard phase-locked loop. An output 24 presents a signal VCOCLK to an input 26 of the feedback counter 20. The feedback counter 20 has an output 28 that presents a signal REFOUT that may also be presented to an input 30 of the PFD 12 as a feedback signal FBCLK. The input multiplexer 22 has an input 32 that receives a first reference clock REFCLK0 and a second input 34 that receives a second clock REFCLK1. An input 36 receives a select signal REFSEL that presents a signal REFCLK at an output 38 by selecting between the clocks received at the inputs 32 and 34. The signal REFCLK is presented to an input 40 of the PFD 12. While the circuit 10 may provide switching between the input clocks REFCLK0 and REFCLK1 without glitching REFOUT, a data stream that is clocked with the signal VCOCLK (e.g., a SONET data stream) may not be recovered properly due to the lack of slew rate limitation of the circuit 10. To properly recover a high-rate data stream clocked with the signal VCOCLK, the overall slew rate of the circuit 10 needs to be reduced.
Referring to FIG. 2, an example of a circuit 50 illustrating a slew rate window generator is shown. The circuit 50 generally comprises a delay block 52 and a gate 54. The delay block 52 has an input 56 that receives a reference clock signal REFCLK and an output 58 that presents a delayed clock signal REF.sub.-- DEL that may be presented to an input 60 of the gate 54. The signal REFCLK may also be presented to an input 62 of the gate 54. The gate 54 presents a signal SLEW.sub.-- WIN that may be derived from the signal REFCLK. The addition of a delay block 52 may take significant die area to implement. Furthermore, the amount of delay presented by the delay block 52 is sensitive to process and temperature variations. Since the circuit 50 is always in an active state, the overall noise introduced into the circuit 10 will be increased.