Source: {"pile_set_name": "USPTO Backgrounds"}

An STI technology has been studied so as to improve a LOCOS method that is widely used in manufacturing process of microelectronic devices. According to this STI technology, a semiconductor substrate is etched so that a shallow trench is formed therein, and an insulating material is filled in the shallow trench thereby forming an isolation region. If a conventional LOCOS method is used, the insulating material is formed by thermal oxidation for long time. However, if the conventional STI method is used, a thermal oxidation process is not required. Therefore, problems caused by the thermal oxidation process can be reduced by using the STI technology. For example, during the conventional LOCOS process, a bird's beak phenomenon which is formed at a boundary of an isolation region and an active region, can be reduced.
The conventional STI region is formed as follows.
First, a trench is formed in a semiconductor substrate. An insulating layer is deposited so as to fill inside the trench. The insulating layer is polished by a chemical vapor polishing("CMP") process until a surface of the semiconductor substrate is exposed, thereby filling the insulating layer within the trench.
However, there are problems in the conventional method of forming STI region. During the CMP process to the insulating layer until the surface of the semiconductor substrate is exposed, the insulating layer within the trench is removed faster than the insulating layer on the surface of the semiconductor substrate. Accordingly, a surface of the insulating layer within the trench is partially removed thereby occurring a dishing phenomenon.
Due to the dishing phenomenon, the surface of the semiconductor substrate is not planarized and the STI layer does not have sufficient insulating characteristic.
Accordingly, there have been suggested methods for preventing the dishing phenomenon at the surface of the insulating layer within the trench conventionally.
Referring to FIG. 1A, a pad oxide 12, a silicon nitride 14 are successively deposited on a semiconductor substrate 10. The pad oxide 12 is formed by a surface oxidation process and the silicon nitride 14 is formed by an LPCV or APCVD process.
Next, as shown in FIG. 1B, a trench mask 15 is formed by etching the silicon nitride 14 and the pad oxide 12 by a known photolithography process until a selected portion of the semiconductor substrate 10 is exposed. Herein, the exposed semiconductor substrate 10 is a region where a device isolation may be performed.
Referring to FIG. 1C, by using the trench mask 15, the exposed semiconductor substrate 10 is anisotropically etched by a selected depth thereby forming a trench T. Next, an insulating layer 16 with selected thickness capable of filling the trench T, is deposited on a resultant surface of the semiconductor substrate 10. At this time, an oxide film deposited according to the CVD process, for example, is used for the insulating layer 16. Herein, a recess r is formed in the insulating layer 16 formed at a portion of the trench T by a step difference of the trench T.
Afterward, referring to FIG. 1D, a polysilicon film 18 is formed on a surface of the insulating layer 16. The polysilicon film 18 serves for delaying the etch rate in the insulating layer 16 within the trench.
And then, a resultant surface of the semiconductor substrate 10 is washed. Continuously, the polysilicon film 18 is polished by the CMP process until a surface of the insulating layer 16 is exposed. As shown in FIG. 1E, then the polysilicon film 18 is filled in a recess r of the insulating layer 16. Herein, the polysilicon film 18 filled in the recess r, is called as a mask polysilicon 18a.
Next, the surface of the insulating layer 16 is washed so that remaining slurry and other contaminants are removed. As shown in FIG. 1F, the insulating layer 16 and the mask polysilicon 18a are etched-back by a selected thickness. Herein, the insulating layer 16 covered with the mask polysilicon 18a is not etched-back relatively due to the difference of etch rate between the polysilicon and the insulating layer. Accordingly, the insulating layer 16 at the trench portion T is relatively protruded to the upside.
Referring to FIG. 1G, the insulating layer 16 is polished according to the CMP process until a surface of the silicon nitride 14 is exposed. Herein, although the CMP process is performed, there is occurred no dishing phenomenon at an upper part of the insulating layer 16 within the trench T since the insulating layer 16 within the trench T is relatively thicker than the insulating layer on the silicon nitride 14.
Referring to FIG. 1H, the silicon nitride 14 and the pad oxide 12 are removed by a known method, thereby forming an STI 18 incurring no dishing phenomenon.
However, the conventional method of forming the STI requires a number of processing steps such as steps of etching trenches; forming oxide and polysilicon films; polishing the polysilicon film by the CMP method; etching-back the oxide film; and polishing the oxide film by the CMP method.
Especially, this method required two times of CMP processes, and the manufacturing process thereof is complicated thereby degrading productivity.