Source: {"pile_set_name": "USPTO Backgrounds"}

(a) Field of the Invention
The invention relates to a PDP (plasma display panel) driving circuit for generating ramp pulses. More specifically, the invention relates to a PDP driving circuit for compensating for temperature variation of parts installed for generating ramp pulses, and allowing stable operation of the ramp pulses.
(b) Description of the Related Art
A PDP has a plurality of discharge tubes in a matrix pattern, and selectively has them emit to restore image data input as electrical signals.
FIG. 1 shows a PDP electrode arrangement diagram.
As shown, the PDP electrodes have an (m x n) matrix pattern. Generally, the m address electrodes A1 through Am are arranged in columns and the n scan electrodes Y1 through Yn and then sustain electrodes X1 through Xn are alternately arranged in rows. Hereinafter, the scan electrodes will be referred to as Y electrodes and the sustain electrodes as X electrodes. The reference numeral 12 in FIG. 1 represents a discharge cell.
In this instance, a number of respective electrodes on the PDP is determined according to its resolution. The PDP realizes gradation so as to output color display performance.
Realization of gradation on the PDP is executed, for example, by dividing one TV field into six subfields and performing time-division control on each of the subfields.
FIG. 2 shows a method for realizing gray sales in a PDP. As shown, the PDP divides a single TV field into six subfields to represent 6-bit grays, and each single subfield has an address interval and a sustain interval.
Current commercial PDPs generally have ten to twelve or more subfields in a single TV field rather than six subfields. Since an increase in the number of subfields in a PDP reduces the contour noise, which is an important factor of image quality, studies for increasing the number of subfields using various methods have been undertaken.
PDPs can use a ramp reset to obtain operational margins. When using a ramp reset to drive a PDP, wall charges are erased except the amount of wall charges that will be used for a subsequent address operation. Wall charges for a subsequent address are accumulated on the panel because of weak discharging, thereby allowing a low-voltage address operation.
FIG. 3 shows a PDP driving waveform using a ramp pulse, and FIG. 4 shows a PDP driving circuit for the driving waveform of FIG. 3. Dotted parts in FIGS. 3 and 4 respectively indicate a ramp pulse waveform and a simple ramp pulse generation part.
One of the methods for generating ramp pulses is by operating a switch of a driving circuit as a static current source so as to output ramp waveforms in the PDP modeled as a capacitive load.
When the voltage at the panel is set to be Vc, the voltage linearly increases with respect to the time axis in the case of a ramp pulse according to Equation 1. Accordingly, a differential value of Vc is a constant.
                                                                        V                c                            =                                                1                  C                                ⁢                                  ∫                                      i                    ⁢                                          ⅆ                      t                                                                                                                                                                                ⅆ                                      V                    c                                                                    ⅆ                  t                                            =                                                                    1                    C                                    ·                  i                                =                Constant                                                                        Equation        ⁢                                  ⁢        1            
In Equation 1, C is a capacitance of the panel. Because the capacitance value C is constant, in order to output a ramp pulse, the current (i) applied to the panel also needs to be constant.
FIG. 5 shows a ramp pulse generation circuit using a capacitor. As shown in FIG. 5, a capacitor C1 is arranged between a gate and a drain of an FET (field-effect transistor) to generate a ramp pulse. That is, in order to completely turn on the FET, it is required to charge a parasitic capacitance Cgs between the gate and the source of the FET, and to charge a parasitic capacitance Cgd between the gate and the drain thereof.
In this instance, when the capacitor C1 is added to the parasitic capacitance Cgd to charge the parasitic capacitance Cgs, a time frame from a time when the FET having a voltage greater than a threshold value starts being turned on to a time when the FET is completely turned on can be extended to some degree.
Accordingly, the parasitic capacitance Cgs is charged through a path {circle around (1)} to slightly open the FET, the gate current is applied to the panel through a path {circle around (2)}, and the charged parasitic capacitance Cgs is discharged to close the FET. In this instance, path {circle around (1)} and path {circle around (2)} cause a negative feedback effect to each other to allow the FET to operate as a constant current source.
FIG. 6 shows a ramp pulse generation circuit using a resistor. As shown in FIG. 6, a resistor R2 is arranged between a source of the FET and a terminal Vs of a FET drive IC to generate a constant current source.
As shown in FIG. 5, when the gate current charges the parasitic capacitance Cgs to open the FET, the current Id starts flowing. The current Id charges the parasitic capacitance Cgd and steeply rises, but it generates a voltage drop of Vr at the resistor R2 to reduce the intensity of the voltage charged to the parasitic capacitance Cgs, because the potential difference between the terminal Vs of the FET drive IC and a terminal HO for outputting a gate signal has a constant voltage Vcc (generally about 12 to 18V).
When the voltage at Cgs reduces, the FET is closed to reduce the current Id. When the current Id reduces, the voltage drop Vr also reduces, and the voltage at Cgs increases to open the FET again.
The above-noted operation is a negative feedback effect to allow the FET to operate as a constant current source.
FIG. 7 shows gradients of the ramp pulse generated by the ramp pulse generation circuits in FIGS. 5 and 6.
When a switch on the PDP modeled as a capacitance load is operated using the constant current source, the ramp pulse shown in FIG. 7 is obtained.
In this instance, the gradients of the ramp pulse can be adjusted in the direction of arrow {circle around (1)} and arrow {circle around (2)} using resistor R1 and capacitor C1 of FIG. 5, and resistor R1 and resistor R2 of FIG. 6. The gradients of the ramp pulse increase or decrease depending on the time constants of parts and the surrounding temperatures, because the gradients depend on the temperature characteristics of the parts.
Application of the ramp pulse for execution of weak discharging in the PDP closely relates to the operational margin of the panel. When the gradient of the ramp pulse varies according to the surrounding temperature of the PDP, the discharging of the panel becomes unstable, and bad discharging occurs.
Therefore, it is required to maintain the gradient of the ramp pulse regardless of the surrounding temperature and other conditions so as to acquire stable discharging on the PDP.