Source: {"pile_set_name": "USPTO Backgrounds"}

The present inventions relate generally to integrated circuits, and more particularly to bias schemes for active device stacks on MOS integrated circuits having low supply voltages.
Stacked devices are used commonly on analog and RF integrated circuits (ICs) in both single-ended and differential embodiments. As the operating voltages of integrated circuits decrease with succeeding generations of process technology, however, the stacked devices must be biased optimally to maintain the devices in saturation and maximize signal-handling ability. Particularly, for proper operation of N stacked devices plus a current source, the minimum supply voltage, VDD, must be N+1 times the gate-source voltage minus a threshold voltage plus a peak output signal swing, i.e., VDD greater than =(N+1)(VGSxe2x88x92VT)+VS, where VGS is the gate-source voltage, VT is the effective threshold voltage and VS is the peak output signal swing. The gate-source voltage, VGS, is typically 250 mV more than the effective threshold voltage, VT, which is about 400 mV. The NMOS threshold voltage, VT=VTO+g[sqrt(2PhiF+VSB)+sqrt(2PhiF)] (Equation 1), where VTO is the effective threshold voltage when the bulk and source are at the same potential, g is the bulk effect factor, PhiF is the absolute value of the Fermi potential, and VSB is the source-bulk voltage.
In a circuit having two stacked devices, for example, the supply voltage needs to be at least 0.75 V plus the peak signal swing, which is well within the maximum supply voltage of 1.8 V typical of present day ICs, but works only if the stacked devices are biased optimally.
A. R. Shahani et al. disclose a low threshold voltage process utilizing active common-mode feedback and resistor dividers to bias three stacked devices and a current source from a 1.5 V supply in xe2x80x9cA 12-mW Wide Dynamic Range CMOS Front-End for a Portable GPS Receiverxe2x80x9d, IEEE Journal of Solid State Circuits, vol. 32, pp. 2061-2070, December 1997. The active common-mode feed back and resistor dividers of Shahani et al. however are relatively complex and require substantial area on the IC.
It is also known to bias a stack of circuit devices with a stack of diode-connected devices, which has the advantage of simplicity and small area on the IC. In the schematic diagram of Prior Art FIG. 1, the gate of each bias device M1-M3 is coupled to the gate of the corresponding active device M4-M6, respectively, in a single-ended embodiment but could represent a simplification of a differential embodiment. In FIG. 1, the bodies of the diode-connected bias devices M1-M3 and the bodies of the active devices M4-M6 are coupled to ground. In FIG. 1, the gate-source voltage, VGS, increases at each level of the stack above the first level because the bulk of the devices are connected to ground. The circuit of FIG. 1 is biased less than optimally and requires a relatively high supply voltage due to the body effect, which is characterized by a voltage between the source and bulk of each device. The body effect causes an increase in the effective threshold voltage, VT, according to Equation 1. In FIG. 1, the required minimum supply voltage VDD is the larger of (N+1)VGS for the bias stack or (N+1)VGSxe2x88x92VTxe2x80x2+VS for the active stack and is more than the typical available supply voltage of 1.8 V, where VTxe2x80x2 is VT+deltV and VGS, VT and VS are as defined above and deltV is the increase in threshold voltage caused by the body effect according to Equation 1.
The various aspects, features and advantages of the present invention will become more fully apparent to those having ordinary skill in the art upon careful consideration of the following Detailed Description of the Invention with the accompanying drawings described below.