Source: {"pile_set_name": "USPTO Backgrounds"}

This invention relates generally to a technique and resulting structure which compensates for performance differences of devices due to process variations in the process of manufacturing integrated circuit devices and in particular, circuits utilizing CMOS technolgy. In more particular aspects, this invention relates to a technique and resulting structure which compensates for process variables, and variables in supply voltage, and operating temperature in the manufacture and operation of device drivers for integrated circuits on chips utilizing CMOS technology.
In the production of integrated circuit devices, and particularly in the production of circuits using CMOS technology, process variables or variations can significantly affect the performance of many of the devices particularly device drivers which are formed on the chip. These performance variables include delay, rise and fall time, impedance, etc., and indeed in uncompensated CMOS circuits the 3-sigma statistical combination of these independent variations on driver devices can be as much as .+-.60%. These process variables which affect the performance include variation of channel length (which typically can vary up to .+-.35%); threshold voltage (.+-.20%) the thickness of the dielectric in the gate electrode channel (.+-.20%); diffusion channel width (.+-.2%); and supply voltage (.+-.10%). As indicated above, all of these various independent factors can have a significant effect even to the accumulative effect of as much as .+-.60% difference in device characteristic between worst case performance i.e. slowest, and best case performance i.e. fastest. (As used herein "best case" and "worst case" are not qualitative values, but rather are quantitative in that "best case" denotes fastest response time and "worst case" denotes slowest response time). These variations have a significant effect on the performance of the devices in various circuits. In the driver circuit when the driver circuit is designed to drive a certain load, if the driver circuit operates too fast and too many drivers are switched on at once, noise will be generated which will be very high due to inductance which will interfere with or even prevent the proper signal recognition. Therefore, a circuit cannot be designed which operates too fast under any given load or the design will be selfdefeating. On the other hand, if the device driver circuit is designed to operate at an extremely slow speed, performance time is lost. Thus, if simultaneous operation of a known number of drivers is required, the inherent variation in performance of the drivers due to process variations prevent the designer from designing close to the optimum rate of performance. Expressed another way, if there is a wide variation in performance characteristics of a driver circuit and a circuit designer designs a circuit to drive at a "nominal" rate which is slow enough to prevent excessive noise being produced but rapid enough to produce good desirable speed, then under certain process conditions the resulting circuit may in fact operate so fast that it encounters noise or inductance problems and is unsatisfactory because of process variations. Therefore, without circuit compensation, the circuit designer is forced to design to a speed which, even under "best" conditions of process varibles which result in the fastest speed of the device driver, will result in a speed which is not so fast that it will induce excessive noise. Of course this designed speed, when there is a significant amount of variation in the process parameters, will be a very low speed, and in fact, in worse case conditions i.e. the slowest operation of the driver's circuit due to process variations, will have an extremely slow driver circuit this speed being significantly slower than that at which it could optimately perform without producing excessive noise. Of course, it would be desirable to reduce to a minimum level the amount of variations introduced by the processing techniques utilized in the manufacture of integrated circuits. However, with the present state of the art of such processing, there are not available any viable commercially acceptable cost effective means to substantially reduce these variables; hence, it becomes necessary to compensate for these process variables. There have in fact been several techniques suggested for compensating for such process variables. One such technique is the so called "serpentine gates", which helps to compensate for delay in which output device gates are connected by connecting the gates in series instead of parallel and thus the turn-on time for each successive finger is delayed by a time proportionate to the resistance of the gate and its capacitance. Since gate resistance increases as channel length decreases, this technique reduces the delay variation with channel length variation which is the most sensitive process parameter. While this technique does reduce certain process related variations somewhat, it does nothing to compensation for variations in supply voltage or other process parameters. This also has other potential difficulties in that with certain types of silicides, an extra mask may be required to generate a precision resistor when this technique is used.
Another technique for reducing the effect of processing variables is shown and described in U.S. patent application Ser. No. 240,853, filed Sept. 2, 1988, Entitled "Performance Enhancing for Integrated Circuit Chips". This technique consists of counting the number of stages in an on-chip delay path that switch within one cycle of an off-chip oscillator and using the count as a basis for digitally adjusting the performance of all drivers on the chip. The complexity of this technique makes it unattractive. Also, in this technique, the same compensation is applied to all drivers on the chip, regardless of localized process differences on the chip. For example, N/FET'S and P/FET'S are given identical compensation even if there are differences in their respective characteristics.
Another technique utilizes feedback from the output node which is shown and described in U.S. patent application No. 07/419,341 filed: Oct. 10, 1989 entitled: CMOS Driver Circuit. However, this is a technique which compensates for off-chip load and not for process variations.
Other various prior art patents suggest various circuits and compensations which include U.S. Pat. No. 4,613,772 which compensates for leakage currents in internal logic gates but does not compensate for process variations; U.S. Pat. No. 4,584,492 compensates trigger points on input buffers but doesn't use opposition currents in prebuffers to control gate voltage on buffer devices; U.S. Pat. No. 4,634,893 discloses a PROM programmed drive, but there is no compensation for the process variations; U.S. Pat. No. 4,570,091 is a dynamic logic precharge with cascode voltage switch and logic for improved performance, but it does not disclose any compensation for process variations; IBM Technical Disclosure Bulletin 31, No. 1, June 1988, pages 21-23 shows a series of devices for certain compensation but does not show opposition devices to control gate voltage; IBM Technical Disclosure Bulletin 27, No. 10B, Mar. 1985, pages 6,012 to 6,013 shows CVS logic which improves logic performances but does not show any means for compensating for various process variable.