Source: {"pile_set_name": "USPTO Backgrounds"}

Modern integrated circuits are generally produced by creating several identical integrated circuit dies (usually square or rectangular areas) in an area on a single (usually round) semiconductor wafer, then scribing and slicing the wafer to separate (singulate, dice) the dies (chips) from one another. An orthogonal grid of "scribe line" (kerf) areas extends between adjacent dies, and sometimes contain test structures, for evaluating the fabrication process. These scribe lines areas, and anything contained within them, will be destroyed when the dies are singulated from the wafer. The singulated (separated) dies are then individually packaged, and may be tested after packaging.
Under ordinary circumstances, pressure to maximize the useful, or productive area of a wafer dictates that scribe line area be kept as small as possible. Dies are laid out on a wafer in a pattern that is packed as tightly as possible. Scribe line widths are only large enough to ensure that the dies can be separated without damage to the area of the dies.
Circuits and active elements on the dies are created while the dies are still together (un-singulated) on the wafer by ion deposition, electron beam lithography, plasma etching, mechanical polishing, sputtering, and numerous other methods which are well known to those skilled in the art of semiconductor fabrication. These processes are highly developed and are capable of producing extremely complicated circuits on the dies at a relatively low cost.
The complexity of integrated circuits is limited, in part, by the purity of the semiconductor wafers available. These wafers contain minuscule defects which may be distributed randomly throughout the wafer, especially the surface where integrated circuit elements are fabricated. The larger the integrated circuit (i.e., the greater its "die size"), the greater the probability that it will be affected by such a defect. Integrated circuits which intersect a defect on the semiconductor wafer are generally rendered non-functional, and therefore useless. Improvements in the wafer production process are yielding purer wafers with smaller defect sizes and densities.
By reducing the size of individual circuit elements, e.g. transistors, it has become possible to place more circuitry in the same area (e.g., die site) which would previously have been occupied by larger circuit elements of lesser complexity. However, the same size reductions which enable greater circuit complexity also render the resulting smaller circuits more sensitive to more minuscule defects in the semiconductor wafer.
Trade-offs between circuit complexity (i.e., number of transistors and circuit area) and anticipated yield (i.e., the number of "good" circuits per wafer) are made by integrated circuit manufacturers based upon a number of factors. The higher the yield, the less a circuit costs the manufacturer to produce, permitting a lower market price.
Among the problems faced by integrated circuit manufacturers are packaged chips (dies) which fail in final test and, even worse, chips which pass final test but which have undetected flaws due to an inability to test them completely. The inability to test an integrated circuit completely arises from the fact that while circuit density and complexity has increased dramatically, the number of Input/Output (I/O) pads which can feasibly be disposed to a chip has not increased correspondingly. Generally, pads are much larger than individual circuit elements. This creates serious testing problems, since ever-increasing amounts of test information must be obtained through the use of a relatively limited number of I/O pads (test points).
"Burn-in" is a process whereby a chip (die) is either simply powered up ("static" burn-in), or is powered up and has signals exercising to some degree the functionality of the chip ("dynamic" burn-in). In both cases, burn-in is typically performed at an elevated temperature--the object being to detect chips that are defective. Burn-in is usually performed on a die-by-die basis, after the dies are separated (diced) from the wafer.
Another technique for burning-in dies, prior to dicing (on the wafer), is to mechanically place test probes or bond wires on each die, or on pads associated with each individual die and located in the scribe lines between the dies.
Another technique for burning-in dies, prior to dicing (on the wafer), is to provide a common network of power and ground conductors in the scribe lines, the power and ground lines connected to all of the dies on a wafer. Generally, the power and ground lines simply power up the device for static burn-in, but built-in self test (self-starting, signal-generating) circuitry on the chip can also provide signals on power up to exercise some of the functionality of the chip. This is discussed in copending, commonly-owned U.S. patent application No. (Docket No. LLC-2087/LSI1P006), entitled METHODS FOR DIE BURN-IN, filed by Rostoker and Dell'Oca.
It should be noted that where "power and ground" are referred to herein, any and all power connections are included. Recent trends in technology have tended to push the design of semiconductor devices in the direction of single voltage supplies, and this terminology reflects this trend. However, herein, the term "power and ground" refers to all required power supply voltages.
Another technique for die burn-in, on the wafer, is discussed in the aforementioned copending, commonly-owned U.S. patent application Ser. No. 07/933,325, filed Aug. 21, 1992, now abandoned. This technique involves bonding wires to the wafer either (1) to bond pads on each die, or (2) to bond pads for each die in adjacent scribe lines.
Generally, for either burn-in or testing, difficulties arise in a few areas:
1) Traditional methods of testing do not provide adequate fault coverage to guarantee that the dies identified as functional ("good") are indeed fully functional; PA1 2) A large number of test points is generally required, necessitating cumbersome expensive equipment to interface with the wafer for testing; and PA1 3) Routing channels for signal interconnections can require a great deal of surface area. PA1 1. Placing an appropriate, minimum number of conductors in the scribe line areas on a wafer, including: PA1 2. Providing a means of isolating short circuits, whether these shorts occur on a particular die (more likely) or in the conductors (especially power and ground) in the scribe lines (less likely). This is accomplished by: PA1 3. Providing a mechanism for implementing die selection, such PA1 4. Providing an electronic mechanism in an area of the wafer for selecting individual dies for testing and/or burn in by either: PA1 5. Providing a unique address for each die, on the die, by either: PA1 6. Rather than placing the power and ground, and/or the probe and sense lines in the scribe lines, or through or on adjacent dies, providing the power, ground, probe and sense lines in a grid of overlying metal lines, whereby: PA1 7. Integrating signal exercising circuits, signal generators, power-on reset circuits, or self-starting self-test circuits onto the wafer for generating signals for dynamic burn-in, thereby avoiding a plurality of dynamic-burn-in signal lines, permitting automatic power-on initialization of dies and test circuitry, and minimizing the number of physical probe points required to control elaborate test sequences. This circuitry may be placed in mutant die sites, normal die sites, in the scribe line area, or any combination of these. PA1 8. Using a separate E-beam tool to: PA1 9. Mounting the wafer, such as by a vacuum chuck to a heating platform, to elevate the temperature of the dies on the wafer for burn-in. PA1 10. Providing redundant die selection circuitry in conjunction with appropriate isolation circuitry (e.g. fusible links) to minimize the likelihood that a flawed selection circuitry will prevent testing and burning in of dies prior to dicing.
In recent years, a number of schemes have arisen to address the testability problems of large, complex integrated circuits. Some example of these techniques are known as SCAN or "Scan-path testing" (ref. T. W. Williams and K. P. Parker, "Design for Testability--A survey" Proc. IEEE, Vol. 71, pp. 98-112, January, 1983), BIST or "Built-in Self-Test" (ref. E. B. Eichelberger and T. W. Williams, "A logic Design Structure for LSI Testing", Proc. 14th Design Automation Conf., June, 1977, 77CH1216-1C, pp. 462-468; also, E. J. McClusky, "Built-In Self-Test Techniques" and "Built-In Self-Test Structures" IEEE Design and Test, Vol. 2, No. 2, pp. 437-452, April, 1985). These techniques deal with testing large integrated circuit structures by incorporating on-chip test facilities (structures) which allow stimuli to be applied to portions of the circuit and responses to be readily read back and observed. SCAN and BIST testing are based on providing a means for accessing the storage elements of a sequential circuit (e.g. flip-flops) and using them to control and/or observe various portions of the integrated circuit to which they are applied.
U.S. Pat. Nos. 3,806,891; 4,293,919; and 4,513,418 (assigned to the IBM Corporation) describe methods whereby the flip-flops of a circuit may be used as test points by re-configuring them into a serial chain (shift-register) and used to shift in test data and to shift out test results.
U.S. Pat. No. 4,340,857 (Fas