Source: {"pile_set_name": "USPTO Backgrounds"}

1. Field of the Invention
The present invention relates to integrated nonvolatile memory circuits (preferably integrated flash memory circuits) which apply high voltage to selected transistors during one or more operating modes (e.g., during various stages of a memory erase operation), monitor one or more selected nodes to detect an illegal condition, and generate a halt signal (for causing the halting or aborting of circuit operation) in response to detection of an illegal condition. The nonvolatile memory circuit of the invention includes logic means for asserting a halt signal in response to an illegal condition, but only following application of a high voltage to components of the circuit (if the illegal condition occurs during application of the high voltage to such components).
2. Description of Related Art
Throughout the specification, including in the claims, the term "connected" is used (in the context of an electronic component being "connected" to another electronic component) in a broad sense to denote that the components are electrically or electromagnetically coupled with sufficient strength under the circumstances. It is not used in a narrow sense requiring that an electrically conducting element is physically connected between the two components.
Nonvolatile memory chips (integrated circuits) are becoming increasingly commercially important. The present invention pertains to a method and apparatus for halting operation of a nonvolatile memory chip in response to detection of an undesired ("illegal") operating condition of the chip. In order to appreciate the invention, it will be helpful initially to describe the structure and normal operating modes of a typical nonvolatile memory chip.
A typical nonvolatile memory chip includes an array of nonvolatile memory cells, each cell comprising a transistor having a floating gate capable of semipermanent charge storage. The current drawn by each cell depends on the amount of charge stored on the corresponding floating gate. Thus, the charge stored on each floating gate determines a data value that is stored "semipermanently" in the corresponding cell.
One particularly useful type of nonvolatile memory chip includes an array of flash memory cells, with each cell comprising a flash memory device (a transistor). The charge stored on the floating gate of each flash memory device (and thus the data value stored by each cell) is erasable by appropriately changing the voltage applied to the gate and source (in a well known manner).
FIG. 1 is a simplified block diagram of a conventional nonvolatile memory chip. Integrated circuit 3 of FIG. 1 includes at least one I/O pad 30 (for asserting output data to an external device or receiving input data from an external device), input/output buffer circuit 10 for I/O pad 30, address buffers A0 through Ap for receiving memory address bits from an external device, row decoder circuit (X address decoder) 12, column multiplexer circuit (Y multiplexer) 14, and memory array 16 (comprising columns of nonvolatile memory cells, such as column 16A). Each of address buffers A0 through Ap includes an address bit pad for receiving (from an external device) a different one of address bit signals X0 through Xn and Y0 through Ym.
I/O buffer circuit 10 includes a "write" branch and a "read" branch. The write branch comprises input buffer 18. The read branch comprises sense amplifier 19 and output buffer 20. Chip 3 executes a write operation by receiving data (to be written to memory array 16) from an external device at I/O pad 30, buffering the data in the write branch, and then writing the data to the appropriate memory cell. Chip 3 can also be controlled to execute a read operation in which it amplifies and buffers data (that has been read from array 16) in the read branch, and then assert this data to I/O pad 30.
Although only one I/O pad (pad 30) is shown in FIG. 1, typical implementations of the FIG. 1 circuit include a plurality of I/O pads, and each I/O pad is buffered by an I/O buffer circuit similar or identical to circuit 10. For example, one implementation of the FIG. 1 circuit includes eight I/O pads, eight buffer circuits identical to circuit 10, one line connected between the output of the output buffer 20 of each buffer circuit and one of the I/O pads (so that eight data bits can be read in parallel from buffers 20 to the pads), and one line connected between the input of the input buffer 18 of each buffer circuit and one of the I/O pads (so that eight data bits can be written in parallel from the pads to buffers 18). Each I/O pad (including I/O pad 30) typically has high impedance when the output buffer is not enabled.
Each of the cells (storage locations) of memory array circuit 16 is indexed by a row index (an "X" index determined by decoder circuit 12) and a column index (a "Y" index output determined by decoder circuit 14). FIG. 2 is a simplified schematic diagram of two columns of cells of memory array 16 (with one column, e.g., the column on the right, corresponding to column 16A of FIG. 1). The column on the left side of FIG. 2 comprises "n" memory cells, each cell implemented by one of floating-gate N-channel transistors N1, N3, . . . , Nn. The drain of each of transistors N1-Nn is connected to bitline 13, and the gate of each is connected to a different wordline (a different one of wordline 0 through wordline n). The column on the right side of FIG. 2 also comprises "n" memory cells, each cell implemented by one of floating-gate N-channel transistors N2, N4, . . . , Nm. The drain of each of transistors N2-Nm is connected to bitline 15, and the gate of each is connected to a different wordline (a different one of wordline 0 through wordline n). The source of each of transistors N1, N3, . . . , Nn, and N2, N4, . . . , Nm is held at a source potential (which is usually ground potential for the chip during a program or read operation).
In the case that each memory cell is a nonvolatile memory cell, each of transistors N1, N3, . . . , Nn, and N2, N4, . . . , Nm has a floating gate capable of semipermanent charge storage. The current drawn by each cell (i.e., by each of transistors N1, N3, . . . , Nn, and N2, N4, . . . , Nm) depends on the amount of charge stored on the corresponding floating gate. Thus, the charge stored on each floating gate determines a data value that is stored "semipermanently" in the corresponding cell. In cases in which each of transistors N1, N3, . . . , Nn, N2, N4, . . . , and Nm is a flash memory device (as indicated in FIG. 2 by the symbol employed to denote each of transistors N1, N3, . . . , Nn, N2, N4, . . . , and Nm), the charge stored on the floating gate of each is erasable (and thus the data value stored by each cell is erasable) by appropriately changing the voltage applied to the gate and source (in a well known manner).
In response to address bits Y0-Ym, circuit 14 (of FIG. 1) determines a column address which selects one of the columns of memory cells of array 16 (connecting the bitline of the selected column to Node 1 of FIG. 1), and in response to address bits X0-Xn, circuit 12 (of FIG. 1) determines a row address which selects one cell in the selected column. Consider an example in which the column address selects the column on the right side of FIG. 2 (the column including bitline 15) and the row address selects the cell connected along wordline 0 (the cell comprising transistor N2). To read the data value stored in the selected cell, a signal (a current signal) indicative of such value is provided from the cell's drain (the drain of transistor N2, in the example), through bitline 15 and circuit 14, to node 1 of FIG. 1. To write a data value to the selected cell, a signal indicative of such value is provided to the cell's gate and drain (the gate and drain of transistor N2, in the example).
More specifically, the FIG. 1 circuit executes a write operation as follows. Each of address buffers A0 through An asserts one of bits X0-Xn to decoder circuit 12, and each of address buffers An+1 through Ap asserts one of bits Y0-Ym to decoder circuit 14. In response to these address bits, circuit 14 determines a column address (which selects one of the columns of memory cells of array 16, such as column 6A), and circuit 12 determines a row address (which selects one cell in the selected column). In response to a write command (which can be supplied from control unit 29, or other circuitry not shown in FIG. 1), a signal (indicative of data) present at the output of input buffer 18 is asserted through circuit 14 to the cell of array 16 determined by the row and column address (e.g., to the drain of such cell). During such write operation, output buffer 20 may be disabled. A data latch (not shown) is typically provided between input buffer 18 and I/O pad 30 for storing data (to be written to a memory cell) received from I/O pad 30. When the latched data is sent to input buffer 18, input buffer 18 produces a voltage at Node 1 which is applied to the selected memory cell. Input buffer 18 is typically implemented as a tri-statable driver having an