Source: {"pile_set_name": "USPTO Backgrounds"}

Disposal of patterned semiconductor substrates, including patterned product substrates that do not meet wafer acceptance criteria (WAC) and patterned monitor substrates, pose two types of challenges. On one hand, the patterned semiconductor substrates contain patterned physical features of circuits or devices that are protected by intellectual property. Disposal of such patterned semiconductor substrates may expose the intellectual property to an inadvertent unwanted disclosure. On the other hand, the patterned semiconductor substrate typically contains environmentally hazardous material such as boron, gallium, indium, arsenic, antimony, etc. Uncontrolled release of such environmentally hazardous material in the patterned semiconductor substrate may result in environmental contamination, of which the remedy can be extremely costly.
A conventional remedy to these problems has been to crush the patterned semiconductor substrates into fine powders so that the microelectronic features in the patterned semiconductor substrates are destroyed. The fine powders from the patterned semiconductor substrate are thereafter put in a sealed container, which may be buried in a designated location to minimize the environmental impact.
Recent efforts to reduce the environmental impact and reduce processing cost of substrate crushing and containment have resulted in methods for substrate reclamation. The patterned portion of a patterned semiconductor substrate is removed. The resulting semiconductor substrate, which does not contain any pattern, is a reclaimed semiconductor substrate that may be employed in semiconductor processing as a monitor substrate or a dummy substrate.
According to prior art, chemical stripping may be employed to remove a patterned portion of a patterned semiconductor substrate. In this method, a chemical is employed to dissolve soluble materials, while insoluble materials are undercut and subsequently removed. However, the dissolution rates across common materials employed in the patterned semiconductor substrates, e.g., silicon oxide, silicon nitride, low-k dielectric materials, polyimide, copper, aluminum, silicon, etc., vary by orders of magnitude. The variations in the dissolution rates typically cause paths to open up down to a surface of a semiconductor layer before the entirety of a back-end-of-line (BEOL) stack including metallization structures are undercut. Such paths cause extensive loss of the semiconductor material in the semiconductor layer. Further, the chemicals employed in chemical stripping tend to be extremely corrosive with accompanying environmentally adverse impacts. For these reasons, chemical stripping tends to consume a large amount of semiconductor material in a semiconductor layer, form large cavities on the surface of the reclaimed semiconductor substrate, contain some incompletely removed structures, and/or cause significantly negative environmental impacts.
An alternate prior art method includes chemical mechanical planarization (CMP) to remove a patterned portion of a patterned semiconductor substrate. A polishing slurry is employed in chemical mechanical planarization to provide selective removal of one material relative to another material. The polishing slurry may be acidic or alkaline. Examples of the polishing slurry include aluminum oxide and fumed silica. The pH of the polishing slurry during chemical mechanical planarization may be adjusted by adding a chemical, e.g., hydrogen peroxide, an alkali metal hydroxide, or ammonia. The removal rate of chemical mechanical planarization depends on the material being removed and the selection of the slurry. Since the composition of material in patterned semiconductor substrate varies significantly, the local polish rate will depend on the material and amount of material present, causing significant differences in polish rate across the wafer. For this reason, uniform removal rate is difficult to achieve with chemical mechanical planarization on all patterned semiconductor substrates, and normally requires chemical stripping to remove materials with low polish rates, as well as the chemical mechanical polish itself. Further, the chemical mechanical planarization requires a polishing slurry, which is a consumable material that needs to be supplied during the CMP process, to enable removal of the material in the patterned portion. In addition, the removed material is mixed with the residual slurry to produce contaminated liquid chemical waste, which is difficult to neutralize for environmental purposes.
Prior art methods employing mechanical removal include grinding of material for reclamation of substrates. Such mechanical removal results in generation of a damaged layer on a reclaimed semiconductor substrate. The surface topography of such reclaimed semiconductor substrate contains significant irregularity after removal of a patterned portion. To remove variations in the topography of the surface, as well as crystal defects extending well into the silicon lattice of the reclaimed semiconductor substrate after such mechanical removal, an additional chemical etching step and lapping to remove bulk silicon steps need to be employed.
In view of the above, there exists a need for a method of removing a patterned portion of a patterned semiconductor substrate at a uniform, material-independent rate without generating significant surface topography or crystal defects to reclaim the patterned semiconductor substrate.
Further, there exists a need for a method of removing the patterned portion of the patterned semiconductor substrate without employing slurry or generating a slurry-containing liquid chemical waste.
Yet further, there exist a need for a method of removing the patterned portion of the patterned semiconductor substrate with sufficient planarity to obviate any need for employing an additional chemical etch step or a lapping step.