Source: {"pile_set_name": "USPTO Backgrounds"}

1. Field of the Invention
This invention relates to computer systems. More particularly, this invention relates to memory transactions within a dual processor computer system.
2. Art Background
The heart of a personal computer system is usually a central processing unit (CPU) that resides on a microprocessor chip. When a microprocessor operates at a high speed, computer instructions and data must be supplied to the microprocessor chip quickly if the speed of the microprocessor is to be utilized effectively. The bus that provides instructions for the microprocessor to execute, and that also provides the data that the microprocessor will use when executing these instructions, can become a bottle neck in a computer system having a fast microprocessor.
If the next instruction to be executed is not available when the microprocessor needs it, then the microprocessor must wait idly while the required instruction is retrieved and provided to the microprocessor. This idling also occurs when the microprocessor has the next instruction to be executed available, but the next instruction to be executed requires data that is not immediately available to the microprocessor. In order to decrease the frequency with which the microprocessor encounters these wait cycles, many modern high performance microprocessors have a small internal cache sometimes called a primary cache. Instructions that are likely to be executed, and data that is likely to be required by the executing instructions, are stored in the internal cache so that they can be accessed immediately by the CPU of the microprocessor.
When an instruction is to be executed or data is required, the cache is checked to determine whether a copy of the required instruction or data is immediately available within the cache. If a copy is stored within the cache (called a cache hit), then the copy can be supplied to the CPU immediately from the cache, and there is no need for the CPU to wait while the instruction or data is retrieved to the microprocessor chip from wherever it is stored within the computer system. On the other hand, if a copy is not stored within the cache (called a cache miss), then the CPU must wait while the instruction or data is retrieved to the microprocessor chip from wherever it is stored within the computer system.
When executing a program, the CPU may modify the copy of a line stored in the cache. In a write through caching scheme, the main memory is immediately updated when a cached copy has been modified. A write through caching scheme has the advantage that data in the cache is always consistent with data in main memory. This is especially advantageous in multiprocessor systems and in systems having direct memory access devices because the main memory always contains the most recent copy of the data. A disadvantage of the write through caching scheme is that it increases the traffic on the bus. This is because the bus is immediately used to send the modified data to the main memory so that the main memory can be updated every time that data in the cache is modified. This is particularly disadvantageous when a memory location is used to store temporary results that change frequently because the main memory must be updated each time the temporary result data changes.
By contrast, in a write back caching scheme, the main memory is not updated every time that a copy stored within the cache is modified. Instead, in a write back caching scheme, the copy stored within the cache may be modified several times before the main memory is updated. This has the advantage of reducing the traffic on the bus because the main memory is not updated as frequently. Furthermore, because the main memory update can be deferred, it is frequently possible to select a time when the bus is idle to update the main memory with the modified data. A disadvantage of the write back caching scheme is that the main memory can contain stale data. This happens when the data within the cache has been modified and the main memory has yet to be updated with the modified data. In multiprocessor systems, or systems having direct memory access devices, care must be taken to maintain cache coherency by ensuring that stale data within the main memory is not used by a co-processor or direct memory access device.
A cache consistency protocol is a set of rules by which states are assigned to cached entries (lines) in order to help maintain cache consistency. The rules apply for memory read and write cycles. Every line in a cache is assigned a state dependent on both processor generated activities and activities generated by other bus masters (e.g., snooping).
The MESI cache consistency protocol consists of four states that define whether a line is valid (i.e., hit or miss), whether it is available in other caches, and whether it has been modified. The four states are: M (Modified), E (Exclusive), S (Shared) and I (Invalid). A M-state line is available in only one cache and it is also modified (i.e., it is different from main memory). An E-state line is also available in only one cache in the system, but the line is not modified (i.e., it is the same as main memory). A write to an E-state line will cause the line to become modified. A line with a S-state indicates that the line is potentially shared with other caches (i.e., the same line may exist in more than one cache). A write to a shared line will generate a write through cycle. The write through cycle may invalidate this line in other caches. Finally, an I-state indicates that the line is not available in the cache. A read to this line will be a miss and may cause a line fill operation (i.e., a fetch of the whole line into the cache from main memory). A write to an invalid line will typically cause the processor to execute a write through cycle on the bus.
Inquire cycles, also called snoop cycles, are initiated by the system to determine if a line is present in a code or data cache, and, if the line is present, what state the line has. Inquire cycles are typically driven to a processor when a bus master other than the processor initiates a read or write bus cycle. Inquire cycles are driven to the processor when the bus master initiates a read to determine if the processor data cache contains the latest information. If the snooped line is in the processor data cache in the modified state, the processor has the most recent information and must schedule a write back of the data. Inquire cycles are driven to the processor when the other bus master initiates a write to determine if the processor code or data cache contains the snooped line and to invalidate the line if it is present.
It is also common to implement the main memory using DRAM, and then to supplement the DRAM based main memory with a SRAM based external cache memory (i.e., a second level cache memory that is external to the microprocessor chip). Because the external cache is not contained on the microprocessor chip, it can typically be made to store more data and instructions than can be stored by the internal cache. Because the external cache is not located on the microprocessor chip, however, it must supply the data and instructions to the microprocessor using one of the buses that often form bottlenecks for data and instructions entering and leaving the microprocessor chip.
A high speed microprocessor chip typically interfaces with the rest of the computer system using one or two high speed buses. The first of these buses is a relatively high speed asynchronous bus called a main memory bus. The second of these buses is a relatively high speed synchronous bus called a local bus. High bandwidth devices such as graphics adapter cards and fast input/output (I/O) devices can be coupled directly to the local bus. Each device coupled to the local bus, however, has an associated capacitive load. As the load on the local bus is increased, the maximum operating speed for the local bus decreases and the power required to drive the bus increases. Therefore, one device coupled to the local bus can be a peripheral bus bridge from the local bus to another bus called a high speed peripheral bus (e.g., a peripheral component interconnect (PCI) bus). The bus bridge isolates the load of the devices coupled to the high speed peripheral bus from the high speed local bus. Another device coupled to the local bus is typically an expansion bus bridge that couples the high performance local bus to a lower performance expansion bus. The low bandwidth components of the computer system are then coupled to the lower performance expansion bus.
The standard PCI specification is targeted to support the functions of an I/O bus. A high speed peripheral bus, such as the PCI bus, has adequate bandwidth to be used as a memory bus for low end systems (i.e., memory bus functionality can be overlaid onto the I/O bus functionality). The trend in mobile computers is towards smaller, faster, less expensive and lighter units. In entry level or mobile systems, part or all of the system memory may be coupled directly to the PCI bus. This may include read-only program modules as well as DRAM, both of which must be cacheable by the processor. The PCI cache support option provides a standard interface between PCI memory agent(s) and the bridge (or caching agent), that allows the use of an inquiry (snooping) cache coherency mechanism. This caching option assumes a flat address space (i.e., a single address has a unique destination regardless of access origin) and a single level bridge topology. This support option is optimized for simple, entry level systems, rather than for maximum processor-cache-memory performance. Thus, advanced mechanisms for cache consistency cycles, cache attribute mapping, and dual processor support are all beyond the scope of a high speed peripheral bus such as set forth in the standard PCI specification.