Source: {"pile_set_name": "USPTO Backgrounds"}

Power consumption and speed are inherently coupled for a given semiconductor technology. Contact resistances and transport properties are related to the band gap of the semiconductors, which affects current levels and drive voltages. In order to reduce the power consumption and to increase the performance of certain key circuits, for instance for wireless communication, it would be attractive to fabricate those circuits in a different material than Si.
Semiconductor nanowire transistors are considered as one of the candidates in the post-CMOS electronics era. In particular a vertical nanowire configuration allows for a wrap gate formation that efficiently controls the electrostatic potential inside the wires, which enhances the transconductance and reduces the sub-threshold slope.
The growth of nanowires offers new possibilities in heterostructure design as radial strain relaxation allows a large range of new compositions to be fabricated. InP can, for example, be grown on InAs without defects as described in U.S. Pat. No. 7,335,908 or US 2004/0075464 by the same applicant as the present invention. It is also possible to use a substrate that is not lattice matched to the wires, which offers even more design flexibility and opens up a route to integrate III-V semiconductors on Si.
Semiconductor nanowires are in this context defined as rod-shaped structures with a diameter less than 200 nm and a length of several μm. The growth of semiconductor nanowires can be done in various ways, for example by Vapor Phase Epitaxi (VPE) using metal particles to assist the anisotropic growth as disclosed in US 2004/0075464 A1.
In the nanowire geometry of the FET the gate will surround the narrow nanowires providing good gate coupling, and heterostructures can be placed in the current channel as described in WO 2006/05020, forcing the source-drain current to pass through the heterostructure interfaces. This offers the possibility to improve the device characteristics.
FIG. 1 shows data for a prior art InAs nanowire wrap gate transistor. The drive current level in transistors with individual nanowires like this one is typically limited to below 100 μA, which is too low for most analogue and mixed-mode circuit applications. Also for digital applications the current level is critical. This problem may be eliminated by placing nanowires in a row, or a matrix, and addressing all the nanowires simultaneously. A patterned substrate will be used as one of the source/drain contacts, on which the nanowires will be grown by controlled nucleation, while the other source/drain contact is formed on top of the wires. The gate level metallization is formed in an interconnection level between the substrate and the top contact.
Transistor pairs (NMOS and PMOS in CMOS, and enhancement mode FETs and depletion mode FETs in different variations of directly coupled field logic, DCFL) are fundamental building blocks for digital, analogue, and mixed-mode applications. Using nanowire circuit architecture, transistors with complementary function may be placed in a vertically stacked configuration, with ohmic contacts to a center region of the wires acting as an output node. In many applications, like a ring-oscillator, this output node should be connected to both gates in the next stage, which requires a three-level interconnection metallization scheme for the gates only. Connections between the various interconnection levels are further required.
In addition to transistors passive elements such as resistors and capacitors has to be added to enable the design of a wider range of circuits including, sample-and-hold circuits and comparators. This increases the complexity of the interconnections of the circuits. The integration of the resistors, capacitors, and transistors enables a wide variety of circuits including, sample-and-hold circuits and comparators.