Source: {"pile_set_name": "USPTO Backgrounds"}

The present invention relates to electrically conductive, hermetic vias and the formation of such vias in hermetically sealed IC chip packages and the like. There are a wide array of high temperature applications for electronic components. Such applications include deep well drilling sensors and engine control units. The latter category of applications is one of the fastest growing areas of high temperature electronics. Electronic engine controllers are often mounted very close to or directly upon the engine itself in order to minimize the number of leads, plugs, connectors and pins between engine and controller, thus subjecting the electronics to the high temperature of the engine. Chip packages are commonly utilized to enclose the fragile electronic component or IC chip, and so must be able to withstand the often harsh environments in which they are placed.
Chip packages typically utilize ceramic substrate bases. The ceramic substrates contain circuit traces printed on one or more of their surfaces for providing electrical connection between the chip within the package and the package exterior. Electrically conductive pathways or vias are provided which extend through the thickness of one or more of the ceramic bases. Vias may be formed in a ceramic substrate by providing a passage or opening extending through the thickness of the substrate and filling with an electrically conductive filler material. Vias may provide an electrical pathway between different levels of circuit traces disposed on ceramic substrates in the package or provide electrical connection through a substrate to the package interior.
It is desirable that the chip package be completely and reliably hermetically sealed so that all foreign materials, such as dust particles, gases and liquids, are prevented from contacting the chip contained within the package. To achieve such hermeticity, it is necessary to provide a sealed enclosure around the chip to prevent leakage between the interior and exterior of the package. One possible path of leakage is through the vias since such vias often extend along the entire thickness of the base of the chip package.
Exposure to temperatures as high as 500.degree. C. and the temperature cycling incident to reaching such high temperatures presents a major threat to the hermeticity of a chip package especially at vias. In addition large temperature deviations, even at relatively low temperatures such as a temperature fluctuation from -65.degree. C. to 300.degree. C., induce extreme thermal expansion or contraction of the ceramic substrate and via fill material and may cause degradation or complete seal failure of the package at the vias. Expansion effects from temperature changes often cause stress induced fracture at or near the via, loss of seal integrity at the via and bond failure between the via fill material and substrate material.
Prior artisans have attempted to form hermetic vias. One such approach, as in U.S. Pat. No. 5,200,249 to Dolhert el al., attempts to match the thermal expansion properties of the via fill material to those of the chip substrate. That approach relies on incorporating particles of the substrate material in the via fill material to approximate the thermal expansion properties of the substrate That approach is undesirable in view of the additional processing steps and related costs in forming the via fill material. Moreover, the addition of particles of substrate material, which is often a dielectric, adversely affects the electrical characteristics of the fill material for chip package vias. Thus, there is a need for an electrically conductive, hermetic via which is capable of withstanding relatively high temperatures and accompanying large temperature fluctuations without loss of hermeticity.