End Equality.
(** *Extension Phases*)
Section Extensions.
Record fsim_properties_ext: Type :=
{
Extindex: Type;
Extorder: Extindex -> Extindex -> Prop;
Extmatch_states: Extindex -> state L1 -> state L2 -> Prop;
Extfsim_order_wf: well_founded Extorder;
Extfsim_match_meminj: forall i s1 s2, Extmatch_states i s1 s2 ->  Mem.extends (get_mem1 s1) (get_mem2 s2);
Extfsim_match_start_stacks:
forall s1 f arg m0, start_stack L1 m0 s1 f arg  ->
exists i s2, start_stack L2 m0 s2 f arg /\ Extmatch_states i s1 s2;
Extfsim_match_initial_states:
forall s1, initial_state L1 s1 ->
exists i s2, initial_state L2 s2 /\ Extmatch_states i s1 s2;
Extfsim_match_final_states:
forall i s1 s2 r ,
Extmatch_states i s1 s2 -> final_state L1 s1 r -> (final_state L2 s2 r);
Extfsim_simulation:
forall s1 t s1', Step L1 s1 t s1' ->
forall i s2, Extmatch_states i s1 s2 ->
exists i', exists s2',
(Plus L2 s2 t s2' \/ (Star L2 s2 t s2' /\ Extorder i' i))
/\ Extmatch_states i' s1' s2';
Extfsim_public_preserved:
forall id, Senv.public_symbol (symbolenv L2) id = Senv.public_symbol (symbolenv L1) id
}.

(** An alternate form of the simulation diagram *)
Lemma Extfsim_simulation':
forall (SIM:fsim_properties_ext),
forall i s1 t s1',
Step L1 s1 t s1' ->
forall s2, Extmatch_states SIM i s1 s2 ->
(exists i', exists s2', Plus L2 s2 t s2' /\
Extmatch_states SIM i' s1' s2')
\/ (exists i', Extorder SIM i' i /\ t = E0 /\ Extmatch_states SIM i' s1' s2).