(************************************************************************)
(*         *      The Rocq Prover / The Rocq Development Team           *)
(*  v      *         Copyright INRIA, CNRS and contributors             *)
(* <O___,, * (see version control and CREDITS file for authors & dates) *)
(*   \VV/  **************************************************************)
(*    //   *    This file is distributed under the terms of the         *)
(*         *     GNU Lesser General Public License Version 2.1          *)
(*         *     (see LICENSE file for the text of the license)         *)
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(** Axiomatization of some bitwise operations *)
Module Type Bits (Import A : Typ).
Parameter Inline testbit : t -> t -> bool.
Parameters Inline shiftl shiftr land lor ldiff lxor : t -> t -> t.
Parameter Inline div2 : t -> t.
End Bits.
Module Type BitsNotation (Import A : Typ)(Import B : Bits A).
Notation "a .[ n ]" := (testbit a n) (at level 5, format "a .[ n ]").
Infix ">>" := shiftr (at level 30, no associativity).
Infix "<<" := shiftl (at level 30, no associativity).
End BitsNotation.
Module Type Bits' (A:Typ) := Bits A <+ BitsNotation A.
Module Type NZBitsSpec
(Import A : NZOrdAxiomsSig')(Import B : Bits' A).
#[global]
Declare Instance testbit_wd : Proper (eq==>eq==>Logic.eq) testbit.

Axiom shiftr_spec : forall a n m, 0<=m -> (a >> n).[m] = a.[m+n].