Opaque lockRes.

(** Performing a store on some disjoint (coherent) part of the memory, retains a [mem_obs_eq] for data and [ctl_inj], using the id injection, for threads*)
Lemma strong_tsim_store_id:
forall tp tp' m m' i b ofs v pmap
(pfi: containsThread tp i)
(pfi': containsThread tp' i)
(Hresi: getThreadR pfi' = getThreadR pfi)
(Hcodei: getThreadC pfi' = getThreadC pfi)
(Hcomp: mem_compatible tp m)
(Hcomp': mem_compatible tp' m')
(Hlt: permMapLt pmap (getMaxPerm m))
(Hno_race: permMapCoherence (getThreadR pfi).1 pmap \/
permMapsDisjoint (getThreadR pfi).1 pmap)
(Hmem_wd: valid_mem m)
(Htp_wd: tp_wd (id_ren m) tp)
(Hstore: Mem.store Mint32 (restrPermMap Hlt) b ofs v = Some m'),
(ctl_inj (id_ren m) (getThreadC pfi) (getThreadC pfi')) /\
(mem_obs_eq (id_ren m) (restrPermMap (compat_th _ _ Hcomp pfi).1)
(restrPermMap ((compat_th _ _ Hcomp' pfi').1))) /\
(Mem.nextblock m = Mem.nextblock m').