(*Some (ThreadPool.getThreadR Htid, virtue1)*)
(*Some virtue2*)

(* Specifications: *)
Lemma make_step_diagram:
forall (U : list nat) (tr1 tr2 : HybridMachineSig.event_trace)
(st1 : ThreadPool (Some hb)) (m1 m1' : mem)
(tid : nat) (cd : option compiler_index)
(st2 : ThreadPool (Some (S hb))) (mu : meminj)
(m2 : mem) (Htid : ThreadPool.containsThread st1 tid)
(c : semC) (b : block) (ofs : Integers.Ptrofs.int)
(pmap_tid' : access_map * access_map),
concur_match cd mu st1 m1 st2 m2 ->
List.Forall2 (inject_mevent mu) tr1 tr2 ->
forall Hcmpt : mem_compatible st1 m1,
HybridMachineSig.schedPeek U = Some tid ->
invariant st1 ->
ThreadPool.getThreadC Htid = Kblocked c ->
semantics.at_external
(semantics.csem (event_semantics.msem semSem)) c
(restrPermMap (fst (ssrfun.pair_of_and (Hcmpt tid Htid)))) =
Some (MKLOCK, (Vptr b ofs :: nil)%list) ->
Mem.store AST.Mint32
(restrPermMap (fst (ssrfun.pair_of_and (Hcmpt tid Htid)))) b
(Integers.Ptrofs.intval ofs) (Vint Integers.Int.zero) =
Some m1' ->
Mem.range_perm
(restrPermMap (fst (ssrfun.pair_of_and (Hcmpt tid Htid)))) b
(Integers.Ptrofs.intval ofs)
(BinInt.Z.add (Integers.Ptrofs.intval ofs) LKSIZE) Cur Writable ->
setPermBlock (Some Nonempty) b (Integers.Ptrofs.intval ofs)
(fst (ThreadPool.getThreadR Htid)) LKSIZE_nat =
fst pmap_tid' ->
setPermBlock (Some Writable) b (Integers.Ptrofs.intval ofs)
(snd (ThreadPool.getThreadR Htid)) LKSIZE_nat =
snd pmap_tid' ->
ThreadPool.lockRes st1 (b, Integers.Ptrofs.intval ofs) = None ->
exists
e' (st2' : t) (m2' : mem) (cd' : option compiler_index)
(mu' : meminj),
concur_match cd' mu'
(ThreadPool.updLockSet
(ThreadPool.updThread Htid (Kresume c Vundef) pmap_tid')
(b, Integers.Ptrofs.intval ofs) (empty_map, empty_map))
m1' st2' m2' /\
List.Forall2 (inject_mevent mu') (seq.cat tr1 (Events.external tid (Events.mklock (b, Integers.Ptrofs.intval ofs)) :: nil))
(seq.cat tr2 (Events.external tid e' :: nil)) /\
HybridMachineSig.external_step
(scheduler:=HybridMachineSig.HybridCoarseMachine.scheduler)
U tr2 st2 m2 (HybridMachineSig.schedSkip U)
(seq.cat tr2
(Events.external tid e' :: nil))
st2' m2'.
Lemma free_step_diagram:
forall (U : list nat) (tr1 tr2 : HybridMachineSig.event_trace)
(st1 : ThreadPool (Some hb)) (m1' : mem)
(tid : nat) (cd : option compiler_index)
(st2 : ThreadPool (Some (S hb))) (mu : meminj)
(m2 : mem) (Htid : ThreadPool.containsThread st1 tid)
(c : semC) (b : block) (ofs : Integers.Ptrofs.int)
(pmap_tid' : access_map * access_map)
(pdata : nat -> option permission) (rmap : lock_info),
concur_match cd mu st1 m1' st2 m2 ->
List.Forall2 (inject_mevent mu) tr1 tr2 ->
forall Hcmpt : mem_compatible st1 m1',
HybridMachineSig.schedPeek U = Some tid ->
bounded_maps.bounded_nat_func' pdata LKSIZE_nat ->
invariant st1 ->
ThreadPool.getThreadC Htid = Kblocked c ->
semantics.at_external
(semantics.csem (event_semantics.msem semSem)) c
(restrPermMap (fst (ssrfun.pair_of_and (Hcmpt tid Htid)))) =
Some (FREE_LOCK, (Vptr b ofs :: nil)%list) ->
ThreadPool.lockRes st1 (b, Integers.Ptrofs.intval ofs) =
Some rmap ->
(forall (b0 : BinNums.positive) (ofs0 : BinNums.Z),
(fst rmap) !! b0 ofs0 = None /\ (snd rmap) !! b0 ofs0 = None) ->
Mem.range_perm
(restrPermMap (snd (ssrfun.pair_of_and (Hcmpt tid Htid)))) b
(Integers.Ptrofs.intval ofs)
(BinInt.Z.add (Integers.Ptrofs.intval ofs) LKSIZE) Cur Writable ->
setPermBlock None b (Integers.Ptrofs.intval ofs)
(snd (ThreadPool.getThreadR Htid)) LKSIZE_nat =
snd pmap_tid' ->
(forall i : nat,
BinInt.Z.le 0 (BinInt.Z.of_nat i) /\
BinInt.Z.lt (BinInt.Z.of_nat i) LKSIZE ->
Mem.perm_order'' (pdata (S i)) (Some Writable)) ->
setPermBlock_var pdata b (Integers.Ptrofs.intval ofs)
(fst (ThreadPool.getThreadR Htid)) LKSIZE_nat =
fst pmap_tid' ->
exists
e' (st2' : t) (m2' : mem) (cd' : option compiler_index)
(mu' : meminj),
concur_match cd' mu'
(ThreadPool.remLockSet
(ThreadPool.updThread Htid (Kresume c Vundef) pmap_tid')
(b, Integers.Ptrofs.intval ofs)) m1' st2' m2' /\
List.Forall2 (inject_mevent mu') (seq.cat tr1 (Events.external tid (Events.freelock (b, Integers.Ptrofs.intval ofs)) :: nil))
(seq.cat tr2 (Events.external tid e' :: nil)) /\
HybridMachineSig.external_step
(scheduler:=HybridMachineSig.HybridCoarseMachine.scheduler)
U tr2 st2 m2
(HybridMachineSig.schedSkip U)
(seq.cat tr2 (Events.external tid e' :: nil)) st2' m2'.
Lemma acquire_fail_step_diagram:
forall (U : list nat) (tr1 tr2 : HybridMachineSig.event_trace)
(st1' : ThreadPool (Some hb)) (m1' : mem)
(tid : nat) (cd : option compiler_index)
(st2 : ThreadPool (Some (S hb))) (mu : meminj)
(m2 : mem) (Htid : ThreadPool.containsThread st1' tid)
(b : block) (ofs : Integers.Ptrofs.int)
(c : semC) (Hcmpt : mem_compatible st1' m1'),
concur_match cd mu st1' m1' st2 m2 ->
List.Forall2 (inject_mevent mu) tr1 tr2 ->
HybridMachineSig.schedPeek U = Some tid ->
semantics.at_external
(semantics.csem (event_semantics.msem semSem)) c
(restrPermMap (fst (ssrfun.pair_of_and (Hcmpt tid Htid)))) =
Some (LOCK, (Vptr b ofs :: nil)%list) ->
Mem.load AST.Mint32
(restrPermMap (snd (ssrfun.pair_of_and (Hcmpt tid Htid)))) b
(Integers.Ptrofs.intval ofs) = Some (Vint Integers.Int.zero) ->
Mem.range_perm
(restrPermMap (snd (ssrfun.pair_of_and (Hcmpt tid Htid)))) b
(Integers.Ptrofs.intval ofs)
(BinInt.Z.add (Integers.Ptrofs.intval ofs) LKSIZE) Cur Readable ->
ThreadPool.getThreadC Htid = Kblocked c ->
invariant st1' ->
exists
e' (st2' : t) (m2' : mem) (cd' : option compiler_index)
(mu' : meminj),
concur_match cd' mu' st1' m1' st2' m2' /\
List.Forall2 (inject_mevent mu') (seq.cat tr1 (Events.external tid (Events.failacq (b, Integers.Ptrofs.intval ofs)) :: nil))
(seq.cat tr2 (Events.external tid e' :: nil)) /\
HybridMachineSig.external_step
(scheduler:=HybridMachineSig.HybridCoarseMachine.scheduler)
U tr2 st2 m2
(HybridMachineSig.schedSkip U)
(seq.cat tr2 (Events.external tid e' :: nil))
st2' m2'.
Lemma external_step_diagram:
forall (U : list nat) (tr1 tr2 : HybridMachineSig.event_trace) (st1 : ThreadPool.t)
(m1 : mem) (st1' : ThreadPool.t) (m1' : mem) (tid : nat) (ev : Events.sync_event),
forall (cd : option compiler_index) (st2 : ThreadPool.t) (mu : meminj) (m2 : mem),
concur_match cd mu st1 m1 st2 m2 ->
List.Forall2 (inject_mevent mu) tr1 tr2 ->
forall (Htid : ThreadPool.containsThread st1 tid) (Hcmpt : mem_compatible st1 m1),
HybridMachineSig.schedPeek U = Some tid ->
syncStep true Htid Hcmpt st1' m1' ev ->
exists ev' (st2' : t) (m2' : mem) (cd' : option compiler_index)
(mu' : meminj),
concur_match cd' mu' st1' m1' st2' m2' /\
List.Forall2 (inject_mevent mu') (seq.cat tr1 (Events.external tid ev :: nil)) (seq.cat tr2 (Events.external tid ev' :: nil)) /\
HybridMachineSig.external_step
(scheduler:=HybridMachineSig.HybridCoarseMachine.scheduler) U tr2 st2 m2 (HybridMachineSig.schedSkip U)
(seq.cat tr2 (Events.external tid ev' :: nil)) st2' m2'.
Lemma start_step_diagram:
forall (m : option mem) (tge : HybridMachineSig.G)
(U : list nat) (st1 : ThreadPool (Some hb))
(m1 : mem) (tr1 tr2 : HybridMachineSig.event_trace)
(st1' : ThreadPool (Some hb)) (m' : mem)
(cd : option compiler_index) (st2 : ThreadPool (Some (S hb)))
(mu : meminj) (m2 : mem) (tid : nat)
(Htid : ThreadPool.containsThread st1 tid),
concur_match cd mu st1 m1 st2 m2 ->
List.Forall2 (inject_mevent mu) tr1 tr2 ->
HybridMachineSig.schedPeek U = Some tid ->
HybridMachineSig.start_thread m1 Htid st1' m' ->
exists
(st2' : ThreadPool (Some (S hb))) (m2' : mem)
(cd' : option compiler_index) (mu' : meminj),
concur_match cd' mu' st1' (HybridMachineSig.diluteMem m') st2'
m2' /\
List.Forall2 (inject_mevent mu') tr1 tr2 /\
machine_semantics.machine_step(HybConcSem (Some (S hb)) m) tge
U tr2 st2 m2 (HybridMachineSig.yield
(Scheduler:=HybridMachineSig.HybridCoarseMachine.scheduler)
U) tr2 st2' m2'.
Lemma resume_step_diagram:
forall (m : option mem) (tge : HybridMachineSig.G)
(U : list nat) (st1 : ThreadPool (Some hb))
(tr1 tr2 : HybridMachineSig.event_trace)
(st1' : ThreadPool (Some hb)) (m1' : mem)
(cd : option compiler_index) (st2 : ThreadPool (Some (S hb)))
(mu : meminj) (m2 : mem) (tid : nat)
(Htid : ThreadPool.containsThread st1 tid),
concur_match cd mu st1 m1' st2 m2 ->
List.Forall2 (inject_mevent mu) tr1 tr2 ->
HybridMachineSig.schedPeek U = Some tid ->
HybridMachineSig.resume_thread m1' Htid st1' ->
exists
(st2' : ThreadPool (Some (S hb))) (m2' : mem)
(cd' : option compiler_index) (mu' : meminj),
concur_match cd' mu' st1' m1' st2' m2' /\
List.Forall2 (inject_mevent mu') tr1 tr2 /\
machine_semantics.machine_step (HybConcSem (Some (S hb)) m) tge
U tr2 st2 m2
(HybridMachineSig.yield(Scheduler:=HybridMachineSig.HybridCoarseMachine.scheduler)
U) tr2 st2' m2'.
Lemma suspend_step_diagram:
forall (m : option mem) (tge : HybridMachineSig.G)
(U : list nat) (st1 : ThreadPool (Some hb))
(tr1 tr2 : HybridMachineSig.event_trace)
(st1' : ThreadPool (Some hb)) (m1' : mem)
(cd : option compiler_index) (st2 : ThreadPool (Some (S hb)))
(mu : meminj) (m2 : mem) (tid : nat)
(Htid : ThreadPool.containsThread st1 tid),
concur_match cd mu st1 m1' st2 m2 ->
List.Forall2 (inject_mevent mu) tr1 tr2 ->
HybridMachineSig.schedPeek U = Some tid ->
HybridMachineSig.suspend_thread m1' Htid st1' ->
exists
(st2' : ThreadPool (Some (S hb))) (m2' : mem)
(cd' : option compiler_index) (mu' : meminj),
concur_match cd' mu' st1' m1' st2' m2' /\
List.Forall2 (inject_mevent mu') tr1 tr2 /\
machine_semantics.machine_step (HybConcSem (Some (S hb)) m) tge
U tr2 st2 m2 (HybridMachineSig.schedSkip U) tr2 st2' m2'.
Lemma schedfail_step_diagram:
forall (m : option mem) (tge : HybridMachineSig.G)
(U : list nat) (tr1 tr2 : HybridMachineSig.event_trace)
(st1' : ThreadPool (Some hb)) (m1' : mem)
(st2 : ThreadPool (Some (S hb))) (m2 : mem)
(tid : nat) cd mu,
concur_match cd mu st1' m1' st2 m2 ->
List.Forall2 (inject_mevent mu) tr1 tr2 ->
HybridMachineSig.schedPeek U = Some tid ->
~ ThreadPool.containsThread st1' tid ->
HybridMachineSig.invariant st1' ->
HybridMachineSig.mem_compatible st1' m1' ->
exists
(st2' : ThreadPool (Some (S hb))) (m2' : mem)
(cd' : option compiler_index) (mu' : meminj),
concur_match cd' mu' st1' m1' st2' m2' /\
List.Forall2 (inject_mevent mu') tr1 tr2 /\
machine_semantics.machine_step (HybConcSem (Some (S hb)) m) tge
U tr2 st2 m2 (HybridMachineSig.schedSkip U) tr2 st2' m2'.
Lemma machine_step_diagram:
forall (m : option mem) (sge tge : HybridMachineSig.G) (U : list nat)
(tr1 : HybridMachineSig.event_trace) (st1 : ThreadPool (Some hb))
(m1 : mem) (U' : list nat) (tr1' : HybridMachineSig.event_trace)
(st1' : ThreadPool (Some hb)) (m1' : mem),
machine_semantics.machine_step (HybConcSem (Some hb) m) sge U tr1 st1 m1 U' tr1' st1' m1' ->
forall (cd : option compiler_index) tr2 (st2 : ThreadPool (Some (S hb)))
(mu : meminj) (m2 : mem),
concur_match cd mu st1 m1 st2 m2 ->
List.Forall2 (inject_mevent mu) tr1 tr2 ->
exists
tr2' (st2' : ThreadPool (Some (S hb))) (m2' : mem) (cd' : option compiler_index)
(mu' : meminj),
concur_match cd' mu' st1' m1' st2' m2' /\
List.Forall2 (inject_mevent mu') tr1' tr2' /\
machine_semantics.machine_step (HybConcSem (Some (S hb)) m) tge U tr2 st2 m2 U' tr2' st2'
m2'.
Lemma initial_diagram:
forall (m : option mem) (s_mem s_mem' : mem) (main : val) (main_args : list val)
(s_mach_state : ThreadPool (Some hb)) (r1 : option res),
machine_semantics.initial_machine (HybConcSem (Some hb) m) r1 s_mem s_mach_state s_mem'
main main_args ->
exists
(j : meminj) (cd : option compiler_index) (t_mach_state : ThreadPool (Some (S hb)))
(t_mem t_mem' : mem) (r2 : option res),
machine_semantics.initial_machine (HybConcSem (Some (S hb)) m) r2 t_mem t_mach_state
t_mem' main main_args /\ concur_match cd j s_mach_state s_mem' t_mach_state t_mem'.
Lemma compile_one_thread:
forall m,
HybridMachine_simulation_properties
(HybConcSem (Some hb) m)
(HybConcSem (Some (S hb)) m)
(concur_match).