Section SIMU_F.
Variables StateA StateC: Type.
Record mapping: Type := mkMapping {
mState: Type;
mInit: StateC -> mState;
mNext: mState -> StateC -> mState;
mDelay: mState -> StateC -> Time -> mState;
mabs: mState -> StateC -> StateA
}.
Variable m: mapping.
Record simu (Pred: Type) (a: TTS StateA) (c: TTS StateC) (tra: Pred -> LP (Predicate _ a)) (trc: Pred -> LP (Predicate _ c)): Type := simuPrf {
inv: (mState m) -> StateC -> Prop;
invInit: forall st, Init _ c st -> inv (mInit m st) st;
invDelay: forall ex1 st1 st2 d, Delay _ c st1 d st2 -> inv ex1 st1 -> inv (mDelay m ex1 st1 d) st2;
invNext: forall ex1 st1 st2, Next _ c st1 st2 -> inv ex1 st1 -> inv (mNext m ex1 st1) st2;
simuInit: forall st, Init _ c st -> Init _ a (mabs m (mInit m st) st);
simuDelay: forall ex1 st1 st2 d, Delay _ c st1 d st2 -> inv ex1 st1 ->
Delay _ a (mabs m ex1 st1) d (mabs m (mDelay m ex1 st1 d) st2);
simuNext: forall ex1 st1 st2, Next _ c st1 st2 -> inv ex1 st1 ->
Next _ a (mabs m ex1 st1) (mabs m (mNext m ex1 st1) st2);
simuPred: forall ext st, inv ext st ->
(forall p, lpSat (Satisfy _ c) st (trc p) <-> lpSat (Satisfy _ a) (mabs m ext st) (tra p))
}.

Theorem satProd: forall State Ind Pred (Sat: forall i, State -> Pred i -> Prop) (st:State) i (f: LP (Pred i)),
lpSat (Sat i) st f
<->
lpSat
(fun (st : State) (p : {i : Ind &  Pred i}) => Sat (projT1 p) st (projT2 p)) st
(addIndex Ind _ i f).