Module Type VERISTAR_MODEL.
Declare Module VeriStarLogic : VERISTAR_LOGIC.
Inductive lseg : val -> val -> heap -> Prop :=
| lseg_nil : forall x s, identity s -> nil_or_loc x -> lseg x x s
| lseg_cons : forall x x' y s h0 h1 z,
x<>y -> val2loc x = Some x' ->
rawnext x' z h0 -> lseg z y h1 -> join h0 h1 s ->
lseg x y s.
Notation stack := env.
Instance Join_stack : Join stack := Join_equiv stack.
Instance Perm_stack : Perm_alg stack := Perm_equiv stack.
Instance Sep_stack : Sep_alg stack := Sep_equiv stack.
Instance Canc_stack : Canc_alg stack := Canc_equiv stack.
Definition stack_get (s : stack) (x : option var) : val :=
match x with
| Some i => env_get s i
| None => empty_val
end.
Definition upd_stack (x : var) (v : val) (s : stack) : stack :=
env_set x v s.
(*Definition empstack : stack := empty_env. Axiom emp_stack : forall (x : option var), stack_get empstack x = empty_val.*)
Inductive state := State: forall (s: stack) (h: heap), state.
Definition stk (st : state) := match st with State s h => s end.
Definition hp  (st : state) := match st with State s h => h end.
Instance Join_state : Join state :=
fun (s1 s2 s3 : state) =>
join (stk s1) (stk s2) (stk s3) /\ join (hp s1) (hp s2) (hp s3).
Definition state_bij: bijection (heap * stack) state.

Lemma var_nil_or_loc : forall (z : var) (e : env), nil_or_loc (env_get e z).