Module Type VERISTAR_MODEL.
Declare Module VeriStarLogic : VERISTAR_LOGIC.
Inductive lseg : val -> val -> heap -> Prop :=
| lseg_nil : forall x s, identity s -> nil_or_loc x -> lseg x x s
| lseg_cons : forall x x' y s h0 h1 z,
x<>y -> val2loc x = Some x' ->
rawnext x' z h0 -> lseg z y h1 -> join h0 h1 s ->
lseg x y s.
Notation stack := env.
Instance Join_stack : Join stack := Join_equiv stack.
Instance Perm_stack : Perm_alg stack := Perm_equiv stack.
Instance Sep_stack : Sep_alg stack := Sep_equiv stack.
Instance Canc_stack : Canc_alg stack := Canc_equiv stack.
Definition stack_get (s : stack) (x : option var) : val :=
match x with
| Some i => env_get s i
| None => empty_val
end.
Definition upd_stack (x : var) (v : val) (s : stack) : stack :=
env_set x v s.

Axiom stack_nil : forall s : stack, stack_get s None = empty_val.