Module Type ErasureSig.
(*  Module SCH: Scheduler with Module TID:=NatTID:= THESCH. Import SCH.*)
Declare Instance Sem (ge : Clight.genv) : Semantics.
Declare Instance JR : Resources.
Declare Instance JTP (ge : Clight.genv) : ThreadPool.ThreadPool(Sem := Sem ge).
Declare Instance JMS (ge : Clight.genv) : MachineSig(ThreadPool := JTP ge).
Declare Instance DilMem : DiluteMem.
Declare Instance scheduler : Scheduler.
Declare Instance JuicyMachine (ge : Clight.genv) : HybridMachine(machineSig:=JMS ge).
Notation JMachineSem ge := (MachineSemantics(HybridMachine := JuicyMachine ge)).
Notation jres := (@res JR).
Notation jstate ge := (@ThreadPool.t _ _ (JTP ge)).
Notation jmachine_state ge := (@MachState _ _ (JTP ge)).
Declare Instance DR : Resources.
Declare Instance DTP (ge : Clight.genv) : ThreadPool.ThreadPool(Sem := Sem ge).
Declare Instance DMS (ge : Clight.genv) : MachineSig(ThreadPool := DTP ge).
Declare Instance DryMachine (ge : Clight.genv) : HybridMachine(machineSig := DMS ge).
Notation DMachineSem ge := (MachineSemantics(HybridMachine := DryMachine ge)).
Notation dres := (@res DR).
Notation dstate ge := (@ThreadPool.t _ _ (DTP ge)).
Notation dmachine_state ge := (@MachState _ _ (DTP ge)).
(*Parameter parch_state : jstate ->  dstate.*)
Parameter match_st : forall (ge : Clight.genv), jstate ge -> dstate ge -> Prop.
(*Variable genv: G. Variable main: Values.val.*)
(*  Variable match_rmap_perm: jres -> dres -> Prop. Variable no_locks_perm: jres ->  Prop.   Axiom init_diagram: forall ge (j : Values.Val.meminj) (U:_) (js : jstate ge) (vals : list Values.val) (m m' : mem) (rmap: jres) (pmap: dres) main h, init_inj_ok j m -> match_rmap_perm rmap pmap -> no_locks_perm rmap -> initial_core (JMachineSem ge U (Some rmap)) h m (U, nil, js) m' main vals -> exists (ds : dstate ge), initial_core (DMachineSem ge U (Some pmap)) h m (U, nil, ds) m' main vals /\ invariant ds /\ match_st ge js ds.*)
(* There's no good generic way to describe the actual initial state, since it depends on the relationship between initial rmap/pmap and memory. *)

Axiom halted_diagram:
forall ge U (ds : dmachine_state ge) (js : jmachine_state ge)  rmap pmap,
fst (fst js) = fst (fst ds) ->
halted (JMachineSem ge U rmap) js = halted (DMachineSem ge U pmap) ds.