Section SyncCallsDiagrams.
Context (hb: nat).
(*Instantiate definitions in Concur with the current hybridbound*)
Notation concur_match:= (concur_match hb).
Notation match_thread:= (match_thread hb).
Notation match_thread_source:= (match_thread_source hb).
Notation match_thread_target:= (match_thread_target hb).
Notation memcompat2:= (memcompat2 hb).
Notation memcompat1:= (memcompat1 hb).
Notation contains12:= (contains12 hb).
Notation mtch_target:= (mtch_target hb).
Notation mtch_compiled:= (mtch_compiled hb).
Notation mtch_source:= (mtch_source hb).
Notation thread_perms st i cnt:= (fst (@getThreadR _ _ st i cnt)).
Notation lock_perms st i cnt:= (snd (@getThreadR  _ _ st i cnt)).
(* Thread states *)
(* angel,lock permissions and new thread permissions *)
(*Hangel_bound: sub_map_virtue angel (getMaxPerm m1)*)
(* Thread states *)
(* angel, lock permissions and new thread permissions *)
(* Thread states *)
(* The following two things are not needed *)
(* angel, lock permissions and new thread permissions *)
(* Thread states *)
(* angel, lock permissions and new thread permissions *)

Lemma acquire_fail_step_diagram_self Sem:
let CoreSem:= sem_coresem Sem in
forall (m1 m2: mem)
(SelfSim: (self_simulation (@semC Sem) CoreSem))
(st1 : mach_state hb) (st2 : mach_state (S hb))
(mu : meminj) tid i b b' ofs delt
(Hinj_b : mu b = Some (b', delt))
cnt1 cnt2 (* Threads are contained *)
(CMatch: concur_match i mu st1 m1 st2 m2)
(th_state1: @semC Sem) th_state2 sum_state1 sum_state2
(HState1: coerce_state_type _ sum_state1 th_state1
(CSem, Clight.state) (AsmSem,Asm.state) (Sem,@semC Sem))
(HState2: coerce_state_type (@semC Sem) sum_state2 th_state2
(CSem, Clight.state) (AsmSem,Asm.state) (Sem,@semC Sem))
(Hget_th_state1: @getThreadC _ _ tid st1 cnt1 = Kblocked sum_state1)
(Hget_th_state2: @getThreadC _ _ tid st2 cnt2 = Kblocked sum_state2)
(Hthread_mem1: access_map_equiv (thread_perms tid st1 cnt1) (getCurPerm m1))
(Hthread_mem2: access_map_equiv (thread_perms tid st2 cnt2) (getCurPerm m2))
(Amatch : match_self (code_inject _ _ SelfSim) mu th_state1 m1 th_state2 m2)
(Hat_external: semantics.at_external CoreSem th_state1 m1 =
Some (LOCK, (Vptr b ofs :: nil)%list))
(Hlock_lt: permMapLt (lock_perms _ _ cnt1) (getMaxPerm m1)),
let m1_locks:= restrPermMap Hlock_lt in
forall (Hload: Mem.load AST.Mint32 m1_locks b (unsigned ofs) = Some vzero)
(Hrange_perm: perm_interval m1_locks b (unsigned ofs) LKSIZE Cur Readable),
let evnt1 := Events.failacq (b, unsigned ofs) in
exists evnt2,
inject_sync_event mu evnt1 evnt2 /\
forall perm Hlt_perm,
let m2_any:= @restrPermMap perm m2 Hlt_perm in
forall (Hcmpt2: mem_compatible st2 m2_any),
syncStep(Sem:=HybridSem (Some (S hb))) true cnt2 Hcmpt2 st2 m2_any evnt2.