Section Parching.
Context (ge : Clight.genv).
Instance Sem : Semantics := ClightSemanticsForMachines.Clight_newSem ge.
Instance JR : Resources := LocksAndResources.
Instance JTP : ThreadPool.ThreadPool := OrdinalPool.OrdinalThreadPool.
Instance JMS : MachineSig := Concur.JuicyMachineShell.
Instance DilMem : DiluteMem := HybridMachineSig.HybridCoarseMachine.DilMem.
Instance scheduler : Scheduler := HybridCoarseMachine.scheduler.
Instance JuicyMachine : HybridMachine := HybridCoarseMachine.HybridCoarseMachine.
Definition jstate := jstate ge.
Instance DR : Resources := DryHybridMachine.dryResources.
Instance DTP : ThreadPool.ThreadPool := OrdinalPool.OrdinalThreadPool.
Instance DMS : MachineSig := DryHybridMachine.DryHybridMachineSig.
Instance DryMachine : HybridMachine := HybridCoarseMachine.HybridCoarseMachine.
Definition dstate := ThreadPool.t
(ThreadPool := OrdinalPool.OrdinalThreadPool)
(* @t dryResources DSem (@OrdinalPool.OrdinalThreadPool dryResources DSem) *).  Definition dmachine_state:= MachState(ThreadPool := OrdinalPool.OrdinalThreadPool).  Import event_semantics threadPool.ThreadPool.  (** * Match relation between juicy and dry state : *)
(* 1-2. Same threads are contained in each state: 3.   Threads have the same c 4-5.   Threads have the same permissions up to erasure 6.   the locks are in the same addresses. 7-8-9. Lock contents match up to erasure. *)
Inductive match_st' : jstate ->  dstate -> Prop:=
MATCH_ST: forall (js:jstate) (ds:dstate)
(mtch_cnt: forall {tid},  containsThread js tid -> containsThread ds tid )
(mtch_cnt': forall {tid}, containsThread ds tid -> containsThread js tid )
(mtch_gtc: forall {tid} (Htid:containsThread js tid)(Htid':containsThread ds tid),
getThreadC Htid = getThreadC Htid' )
(mtch_perm1: forall b ofs {tid} (Htid:containsThread js tid)(Htid':containsThread ds tid),
juicy_mem.perm_of_res (resource_at (getThreadR Htid) (b, ofs)) =
((getThreadR Htid').1 !! b) ofs )
(mtch_perm2: forall b ofs {tid} (Htid:containsThread js tid)(Htid':containsThread ds tid),
juicy_mem.perm_of_res_lock (resource_at (getThreadR Htid) (b, ofs)) =
((getThreadR Htid').2 !! b) ofs )
(mtch_locks: forall a,
ssrbool.isSome (lockRes js a) = ssrbool.isSome (lockRes ds a))
(mtch_locksEmpty: forall lock dres,
lockRes js lock = Some (None) ->
lockRes ds lock = Some dres ->
dres = (empty_map, empty_map))
(mtch_locksRes: forall lock jres dres,
lockRes js lock = Some (Some jres) ->
lockRes ds lock = Some dres ->
forall b ofs,
juicy_mem.perm_of_res (resource_at jres (b, ofs)) = (dres.1 !! b) ofs )
(mtch_locksRes: forall lock jres dres,
lockRes js lock = Some (Some jres) ->
lockRes ds lock = Some dres ->
forall b ofs,
juicy_mem.perm_of_res_lock (resource_at jres (b, ofs)) = (dres.2 !! b) ofs )
(** *SyncStep simulation*)
(** Proof of the step diagram when the step is a synchronization step. TODO: Split the proof in each diagram. *)
Inductive deltaMap_cases (dmap:delta_map) b ofs:=
| DMAPS df p:  dmap ! b = Some df -> df ofs = Some p -> deltaMap_cases dmap b ofs
| DNONE1 df:  dmap ! b = Some df -> df ofs = None -> deltaMap_cases dmap b ofs
| DNONE2:  dmap ! b = None -> deltaMap_cases dmap b ofs.

Lemma core_diagram:
forall (m : Mem.mem)  (U0 U U': schedule) rmap pmap
(ds : dstate) dtr (js js': jstate) jtr jtr'
(m' : Mem.mem),
corestep (JMachineSem U0 rmap) (U, jtr, js) m (U', jtr', js') m' ->
match_st js ds ->
invariant ds ->
exists (ds' : dstate),
invariant ds' /\
match_st js' ds' /\
exists dtr', corestep (ClightMachineSem U0 pmap) (U, dtr, ds) m (U', dtr ++ dtr', ds') m'.