Repository: steveicarus/iverilog

Issue #1133: Adding signal output will cause abnormal simulation output in iverilog
Created: 2024-05-21T10:48:28Z
In the following two code snippets, y is the output wire.
assign y = {
            forvar19
           };

assign y = {
            wire7,
            forvar19
           };

The original design of the two statements generated syn_vivado.v after synthesis in Vivado, and I simulated the synthesized code.
Theoretically, if all other conditions remain the same, the simulation output in the forvar19 section should be consistent, meaning that the lower bits of y should be the same for the forvar19 value in both cases.
However, when I simulated using iverilog, with all other conditions being equal, the two produced different simulation outputs.
(both wire7 and forvar19 I constructed are 2-bit).

The left side only includes the forvar19 output as shown (highlighted in yellow for the forvar19 output section);
the right side includes the output with the wire7 signal as shown (highlighted in yellow for the forvar19 output section).
Inconsistencies appeared on lines 6, 7, and 14.
Therefore, I used Vivado's simulation tool to simulate the synthesized output of the two statements, and the lower bits of the forvar19 output were consistent.

The left side only includes the forvar19 output as shown (highlighted in yellow for the forvar19 output section);
the right side includes the output with the wire7 signal as shown (highlighted in yellow for the forvar19 output section).
Comparing the outputs of the two simulation tools mentioned above, I think that the issue might be caused by adding signal output, leading to abnormal simulation results in iverilog.
Here is the directory structure of the zip file:


├── 1/
│   ├── data/
│   │   ├── cells_cmos.v
│   │   ├── cells_cyclone_v.v
│   │   ├── cells_verific.v
│   │   ├── cells_xilinx_7.v
[Uploading iverilog_5_21.zip…]()

│   │   ├── README.md
│   │   └── cells_yosys.v
│   ├── rtl.v
│   ├── syn_vivado.v
│   ├── vivado.log
│   ├── vivado_main
│   ├── vivado_testbench.v
│   └── vvp_vivado.log
├── 2/
│   ├── data/
│   │   ├── cells_cmos.v
│   │   ├── cells_cyclone_v.v
│   │   ├── cells_verific.v
│   │   ├── cells_xilinx_7.v
│   │   ├── README.md
│   │   └── cells_yosys.v
│   ├── rtl.v
│   ├── syn_vivado.v
│   ├── vivado.log
│   ├── vivado_main
│   ├── vivado_testbench.v
│   └── vvp_vivado.log

Descriptions:


1/ or 2/:  These two documents correspond to the two different designs mentioned above


data/: Contains module files referenced by Vivado synthesis.

cells_cmos.v
cells_cyclone_v.v
cells_verific.v
cells_xilinx_7.v
cells_yosys.v



rtl.v: Original design.


syn_vivado.v: File synthesized using Vivado.


vivado_testbench.v: Testbench file.


vvp_vivado.log: Simulation results using Icarus Verilog (iverilog).


vivado.log: Simulation results using Vivado.

Duplicate issue #1132: The simulation of iverilog and other tools is inconsistent
Created: 2024-05-21T03:20:13Z
The simulation results of syn_vivado.v synthesized by Vivado using iverilog and Vivado are inconsistent
For this, I tried on edaplayground.
https://www.edaplayground.com/x/Fd7p
You can use Aldec Riviera Pro 2023.04 and Icarus Verilog 12.0 for separate simulations.
This is the simulation result of iverilog
101000000000000001100
101000000000000010100
101000000000000001000
101000001000000011000
101000001000000001010
101000001000000011000
101000001000000000000
101000001000000011000
101000001000000010000
101000001000000011100
101000001000000011100
101000001000000001110
101000001000000001000
101000001000000001100
101000001000000010010
101000001000000010000
101000001000000001000
101000001000000010100
101000001000000001000
101000001000000000110
101000000000000011000

Here are the simulation results of Aldec Riviera Pro 2023.04
# KERNEL: 101000000000000001100
# KERNEL: 101000000000000010100
# KERNEL: 101000000000000001000
# KERNEL: 101000000000000011000
# KERNEL: 101000000000000001010
# KERNEL: 101000000000000011000
# KERNEL: 101000000000000000000
# KERNEL: 101000000000000011000
# KERNEL: 101000000000000010000
# KERNEL: 101000000000000011100
# KERNEL: 101000000000000011100
# KERNEL: 101000000000000001110
# KERNEL: 101000000000000001000
# KERNEL: 101000000000000001100
# KERNEL: 101000000000000010010
# KERNEL: 101000001000000010000
# KERNEL: 101000001000000001000
# KERNEL: 101000001000000010100
# KERNEL: 101000001000000001000
# KERNEL: 101000001000000000110
# KERNEL: 101000000000000011000

I also used Vivado for simulation, and the following are the results
## current_wave_config
101000000000000001100
101000000000000010100
101000000000000001000
101000000000000011000
101000000000000001010
101000000000000011000
101000000000000000000
101000000000000011000
101000000000000010000
101000000000000011100
101000000000000011100
101000000000000001110
101000000000000001000
101000000000000001100
101000000000000010010
101000001000000010000
101000001000000001000
101000001000000010100
101000001000000001000
101000001000000000110
101000000000000011000
$finish called at time : 210 ps : 

It can be clearly seen that the simulation of iverilog is different from the latter two

Closing comment (2024-06-08T20:15:40Z): This looks to be the same as #1133. Again, if there is a race in your design, different simulators can quite legitimately produce different results.