ppxscal/embedding_network huggingface dataset:
A Framework for Parallel Tree-Based Scientific Simulations
Authors: Pangfeng Liu, Jan-Jan Wu
Venue: Proceedings of the international Conference on Parallel Processing (1997)

This paper describes an implementation of a platform-independent parallel C++ N-body framework that can support various scientific simulations that involve tree structures, such as astrophysics, semiconductor device simulation, molecular dynamics, plasma physics, and fluid mechanics. Within the framework the users will be able to concentrate on the computation kernels that differentiate different N-body problems, and let the framework take care of the tedious and error-prone details that are common among N-body applications. %In addition, we will use MPI to implement the communication routines so %that the framework will be portable across many parallel platforms, %including massively parallel processors and workstation clusters. This framework was developed based on the techniques we learned from previous CM-5 C implementations, which have been rigorously justified both experimentally and mathematically. This gives us confidence that our framework will allow fast prototyping of different N-body applications, to run on different parallel platforms, and to deliver good performance as well.
Multiple View Consistency for Data Warehousing
Authors: Yue Zhuge, Hector Garcia-Molina, Janet L. Wiener
Venue: Proceedings of the Thirteenth International Conference on Data Engineering (1997)

A data warehouse stores integrated information from multiple distributed data sources. In effect, the warehouse stores materialized views over the source data. The problem of ensuring data consistency at the warehouse can be divided into two components: ensuring that each view reflects a consistent state of the base data, and ensuring that multiple views are mutually consistent. In this paper we study the latter problem, that of guaranteeing multiple view consistency (MVC). We identify and define formally three layers of consistency for materialized views in a distributed environment. We present a scalable architecture for consistently handling multiple views in a data warehouse, which we have implemented in the WHIPS(WareHousing Information Project at Stanford) prototype. Finally, we develop simple, scalable, algorithms for achieving MVC at a warehouse.
Accuracy and Speedup of Parallel Trace-Driven Architectural Simulation
Authors: Anthony-Trung Nguyen, Pradip Bose, Kattamuri Ekanadham, Ashwini K. Nanda, Maged M. Michael
Venue: Proceedings of the 11th International Symposium on Parallel Processing (1997)

Trace-driven simulation continues to be one of the main evaluation methods in the design of high performance processor-memory sub-systems. In this paper, we examine the varying speed-up opportunities available by processing a given trace in parallel on an IBM SP-2 machine. We also develop a simple, yet effective method of correcting for cold-start cache miss errors, by the use of overlapped trace chunks. We then report selected experimental results to validate our expectations. We show that it is possible to achieve near-perfect speed-up without loss of accuracy. Next, in order to achieve further reduction in simulation cost, we combine uniform sampling methods with parallel processing with a slight loss of accuracy for finite-cache timer runs. We then show that by using warm-start sequences from preceding trace chunks, it is possible to reduce the errors back to acceptable bounds.
Unified vs. split TLBs and caches in shared-memory MP systems
Authors: Qidong Xu, Patricia J. Teller
Venue: Proceedings of the 9th International Symposium on Parallel Processing (1995)

Data references in shared-memory multiprocessors (SMMPs) are targeted to private and shared data. Thus, conflicts between private and shared data occur in unified translation-lookaside buffer (TLBs) and caches. Separate private and shared data TLBs and caches eliminate such conflicts and might decrease miss ratios. But these split TLBs and caches would be smaller than their unified counterparts and might increase miss ratios. We use trace-driven simulations to compare the performance of unified vs. split data TLBs and caches. Our results show (1) a small number of unified TLB/cache conflicts for two workloads and a substantial number for another; and (2) split TLB/cache miss ratio reductions due to conflict removal smaller than miss ratio increases due to reduced size. Although split data TLBs and caches do not offer performance gains in SMMPs for such workloads, it is not clear whether or not they would for different workloads.
ESOW: Parallel/Distributed Programming on the Web
Authors: Denivaldo Lopes, Slimane Hammoudi, Zair Abdelouahab
Venue: Proceedings of the 13th International Workshop on Database and Expert Systems Applications (2002)

This paper presents an environment for supporting parallel/distributed programming using Java with RMI and RMI-IIOP (CORBA). The environment implements the notion of Shared Objects (SO), Distributed Shared Objects (DSO) and introduces Active Shared Mobile Objects (ASMO). The Environment of Shared Objects for Web (ESOW) provides an environment to passive objects (lists, queues and stacks) and active objects (process). This environment simulates a Distributed Shared Memory (DSM) with security, good performance (load balancing), reliability (fault tolerance) and transparency. It makes possible that computers share two "abundant" resources in the Web: memory and processor. Then the Web is seen as a Pool of Processors for sharing. We will present a test with evolution strategies to solve multimodal functions with many local minimum. We confirm also that others tests have validated the use of ESOW in Metacomputing.
Experience with active messages on the Meiko CS-2
Authors: Klaus E. Schauser, Chris J. Scheiman
Venue: Proceedings of the 9th International Symposium on Parallel Processing (1995)

Active messages provide a low latency communication architecture which on modern parallel machines achieves more than an order of magnitude performance improvement over more traditional communication libraries. This paper discusses the experience we gained while implementing active messages on the Meiko CS-2, and discusses implementations for similar architectures. During our work we have identified that architectures which only support efficient remote write operations (or DMA transfers as in the case of the CS-2) make it difficult to transfer both data and control as required by active messages. Traditional network interfaces avoid this problem because they have a single point of entry which essentially acts as a queue. To efficiently support active messages on modern network communication co-processors, hardware primitives are required which support this queue behavior The overcame this problem by producing specialized code which runs on the communications co-processor and supports the active messages protocol. Our implementation of active messages results in a one-way latency of 12.3 /spl mu/s and achieves up to 39 MB/s for bulk transfers. Both numbers are close to optimal for the current Meiko hardware and are competitive with performance of active messages on other hardware platforms.
Efficient Collective Communication on Heterogeneous Networks of Workstations
Authors: Mohammad Banikazemi, Vijay Moorthy, Dhabaleswar K. Panda
Venue: Proceedings of the 1998 International Conference on Parallel Processing (1998)

Networks of Workstations (NOW) have become an attractive alternative platform for high performance computing. Due to the commodity nature of workstations and interconnects and due to the multiplicity of vendors and platforms, the NOW environments are being gradually redefined as Heterogeneous Networks of Workstations (HNOW) environments. This paper presents a new framework for implementing collective communication operations (as defined by the Message Passing Interface (MPI) standard) efficiently for the emerging HNOW environments. We first classify different types of heterogeneity in HNOW and then focus on one important characteristic: communication capabilities of workstations. Taking this characteristic into account, we propose two new approaches (Speed-Partitioned Ordered Chain (SPOC) and Fastest-Node First (FNF)) to implement collective communication operations with reduced latency. We also investigate methods for deriving optimal trees for broadcast and multicast operations. Generating such trees is shown to be computationally intensive. It is shown that the FNF approach, in spite of its simplicity, can deliver performance within 1% of the performance of the optimal trees. Finally, these new approaches are compared with the approach used in the MPICH implementation on experimental as well as on simulated testbeds. On a 24-node existing HNOW environment with SGI workstations and ATM interconnection, our approaches reduce the latency of broadcast and multicast operations by a factor of up to 3.5 compared to the approach used in the existing MPICH implementation. On a 64-node simulated testbed, our approaches can reduce the latency of broadcast and multicast operations by a factor of up to 4.5. Thus, these results demonstrate that there is significant potential for our approaches to be applied towards designing scalable collective communication libraries for current and future generation HNOW environments.
Extending VLSI design with higher-order logic
Authors: Anand Chavan, Shiu-Kai Chin, Shahid Ikram, Jang Dae Kim, Juin-Yeu Zu
Venue: Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors (1995)

Extending VLSI CAD with higher-order logic integrates formal verification with synthesis. The benefits of doing so are: 1) relating instruction-set descriptions to implementations, 2) designing at a higher level of abstraction than at the level of schematics, 3) verifying by proof 4) reusing verified parameterized designs, 5) automatically compiling designs in higher-order logic to parameterized cell generators and layouts, and 6) validating electrical and functional properties by simulation. Such an integration is demonstrated by linking the Cambridge Higher-Order Logic (HOL) theorem-prover with the Mentor Graphics GDT design environment. We illustrate its applications by creating a parameterized macro-cell generator for an n-bit Am2910 microprogram sequencer whose design is formally verified with respect to its instruction-set architecture specification.
Implicit B-Trees: New Results for the Dictionary Problem
Authors: Gianni Franceschini, Roberto Grossi, J. Ian Munro, Linda Pagli
Venue: Proceedings of the 43rd Symposium on Foundations of Computer Science (2002)

We reopen the issue of finding an implicit data structure for the dictionary problem. In particular, we examine the problem of maintaining n data values in the first n locations of an array in such a way that we can efficiently perform the operations insert, delete and search. No information other than n and the data is to be retained; and the only operations which we may perform on the data values (other than reads and writes) are comparisons. Our structure supports these operations in 0(\log ^2 n/\log \log n) time, marking the first improvement on the problem since the mid 1980's. En route we develop a number of space efficient techniques for handling segments of a large array in a memory hierarchy. We achieve a cost of 0(\log _B n) block transfers like in regular B-trees, under the realistic assumption that a block stores B = \Omega (\log n) keys, so that reporting r consecutive keys in sorted order has a cost of 0(\log _B n + {r \mathord{\left/ {\vphantom {r B}} \right. \kern-\nulldelimiterspace} B}) block transfers. Being implicit, our B-tree occupies exactly \left\lceil {{\raise0.7ex\hbox{$n$} \!\mathord{\left/ {\vphantom n B}}\right.\kern-\nulldelimiterspace} \!\lower0.7ex\hbox{$B$}}} \right\rceilblocks after each update.
Fault-tolerant sorting in SIMD hypercubes
Authors: Amitabh Mishra, Yeimkuan Chang, Laxmi N. Bhuyan, Fabrizio Lombardi
Venue: Proceedings of the 9th International Symposium on Parallel Processing (1995)

This paper considers sorting in SIMD hypercube multiprocessors in the presence of node failures. The proposed algorithm correctly sorts up to 2/sup n/=N keys in a faulty SIMD hypercube of dimension n containing up to n-1 faulty nodes. The proposed fault-tolerant algorithm employs radix sort. We use a pair of flood dimensions which helps to route data around the faulty processors during the movement of data. If all the key values to be sorted belong to the range 0 to M-1, sorting can be accomplished efficiently in O(log M*log N)+O(log/sup 2/N) time.
Rational clocking [digital systems design]
Authors: Luis F. G. Sarmenta, Gill A. Pratt, Stephen A. Ward
Venue: Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors (1995)

Communication between independently-clocked digital subsystems typically involves a finite probability of synchronization failure whose minimization introduces delays and consequent performance costs. This paper explores a technique that eliminates both the inherent unreliability of such communication and the performance overhead it implies. Our approach maintains a known phase relationship, between clocks whose frequencies are related by a rational factor, and exploits the predictability of their relative phases to algorithmically time communications without run-time arbitration contests.
Retrieval methods for English-text with missrecognized OCR characters
Authors: Manabu Ohta, Atsuhiro Takasu, Jun Adachi
Venue: Proceedings of the 4th International Conference on Document Analysis and Recognition (1997)

This paper presents three probabilistic text retrieval methods designed to carry out a full-text search of English documents containing OCR errors. By searching for any query term on the premise that there are errors in the recognized text, the methods presented can tolerate such errors, and therefore costly manual post-editing is not required after OCR recognition. In the applied approach, confusion matrices are used to store characters which are likely to be interchanged when a particular character is missrecognized, and the respective probability of each occurrence. Moreover, a 2-gram matrix is used to store probabilities of character connection, i.e., which letter is likely to come after another. Multiple search terms are generated for an input query term by making reference to confusion matrices, after which a full-text search is run for each search term. The validity of retrieved terms is determined based on error-occurrence and character connection probabilities. The performance of these methods is experimentally evaluated by determining retrieval effectiveness, i.e., by calculating recall and precision rates. Results indicate marked improvement in comparison with exact matching.
Packing 2-Dimensional Bins in Harmony
Authors: Alberto Caprara
Venue: Proceedings of the 43rd Symposium on Foundations of Computer Science (2002)

We consider 2-Dimensional (Finite) Bin Packing (2BP), which is one of the most important generalizations of the well-known Bin Packing (BP) and calls for orthogonally packing a given set of rectangles (that cannot be rotated) into the minimum number of unit size squares.There are many open questions concerning the approximability of 2BP, whereas the situation for the 2-stage case, in which the items must first be packed into shelves that are then packed into bins, is essentially settled. For this reason, we study the asymptotic worst-case ratio between the optimal solution values of the 2-stage and general 2BP, showing that it is equal to {\rm T}\infty= 1.691 \ldots, the well-known worst-case ratio of the Harmonic algorithm for BP. This ratio is achieved by packing the items into shelves by decreasing heights as in the Harmonic algorithm and then optimally packing the resulting shelves into bins. This immediately yields polynomial time approximation algorithms for 2BP whose asymptotic worst-case ratio is arbitrarily close to {\rm T}\infty, i.e. substantially smaller than 2 + \varepsilon, that was the best ratio achievable so far and constituted the first (recent) improvement over the 2.125 ratio shown in the early 80s. In particular, we manage to push the approximability threshold below 2, which is often a critical value in approximation.The main idea in our analysis is to use the fact that the fractional and integer BP solutions have almost the same value, which is implicit in the approximation schemes for the problem, as a stand-alone structural result. This implies the existence of modified heights for the shelves whose sum yields approximately the number of bins needed to pack them. With this in mind, our proof can easily be adapted to different cases. For instance, we can derive new upperbounds on the worst-case ratio of several shelf heuristics for 2BP, among which a bound of(\frac{{17}}{{10}})(\frac{{11}}{9}) = 2.077 \ldots (rather than 2:125) on the 20-years-lasting champion mentioned above. Moreover, we can easily derive the asymptotic worst-case ratio between the 2-stage and general 2BP solution values as a function of the maximum width of the rectangles, showing that this ratio is independent of the maximum height. Finally, under a conjecture that appears to be supported by experimental evidence, we show that our main heuristic has an asymptotic worst-case ratio in the interval (1:490, 1:507) when all the rectangles to be packed are squares. This would improve the current best worst-case ratio of \frac{{14}}{9} = 1.555 \ldots for this special case.
A Fast and Efficient Projection-Based Approach for Surface Reconstruction
Authors: M. Gopi, Shankar Krishnan
Venue: Proceedings of the 15th Brazilian Symposium on Computer Graphics and Image Processing (2002)

Abstract. We present a fast and memory efficient algorithm that generates a manifold triangular mesh S with or without boundary passing through a set of unorganized points P \subset R3 with no other additional information. Nothing is assumed about the geometry or topology of the sampled manifold model, except for its reasonable smoothness. The speed of our algorithm is derived from a projection-based approach we use to determine the incident faces on a point. Our algorithm has successfully reconstructed the surfaces of unorganized point clouds of sizes varying from 10,000 to 100,000 in about 3 - 30 seconds on a 250 MHz, R10000 SGI Onyx2. Our technique can be specialized for different kinds of input and applications. For example, our algorithm can be specialized to handle data from height fields like terrain and range scan, even in the presence of noise. We have successfully generated meshes for range scan data of size 900,000 points in less than 40 seconds.
Turn Grouping for Efficient Barrier Synchronization in Wormhole Mesh Networks
Authors: Kuo-Pao Fan, Chung-Ta King
Venue: Proceedings of the international Conference on Parallel Processing (1997)

Barrier is an important synchronization operation. On scalable parallel computers, it is often implemented as a collective communication with a reduction operation followed by a distribution operation. In this paper, we introduce a systematic way of generating efficient algorithms to perform barrier synchronization in mesh networks. The scheme works with any base routing algorithm derivable from the turn model. Our scheme extends the turn grouping method proposed with two new algorithms, Tail to Central and Central to Tail, for scheduling the message transmission in the reduction and distribution phase respectively. Simulation results show that our approach can take advantage of the adaptivity of the turn-model based routing algorithms and outperform methods proposed previously.
A Fuzzy Petri Nets Based Mechanism for Fuzzy Rules Reasoning
Authors: Stephen J. H. Yang, William C. Chu, Jonathan Lee, Wei T. Huang
Venue: Proceedings of the 21st International Computer Software and Applications Conference (1997)

This paper presents a mechanism for normalizing fuzzy rules of a rule-based system, transforming the rules into a fuzzy Petri net, and answering queries based on the net with imprecise information. In addition, we are presenting an algorithm utilizing the formalism of Petri nets to compute the degree of truth of the resulting answers to the queries. The degree of truth is computed in algebraic form based on the state equation which can be implemented in matrix computation in Petri nets.
Efficient implementation of mutual exclusion locks in large multiprocessors
Authors: Nian-Feng Tzeng, Shiwa S. Fu
Venue: Proceedings of the 9th International Symposium on Parallel Processing (1995)

To ensure proper mutual exclusion, a lock is often employed to determine the processor among those which compete for the critical section. Accesses to such a mutual exclusion lock may create heavy synchronization traffic and/or serious contention over the network, thereby degrading system performance considerably. In this paper, we introduce an efficient lock scheme which keeps synchronization traffic low and avoids serious hot-spot contention. This is made possible by constructing a ring of the processors waiting for the critical section and by dispersing accesses to the lock. Our simulation results demonstrate that the proposed scheme indeed achieves better performance than prior techniques, promising good scalability.
Requirements Specifications Evolution in a Multi-Perspective Environment
Authors: Ana Belén Barragáns-Martínez, Jorge Garcia Duque, José J. Pazos Arias, Ana Fernández Vilas, Rebeca P. Díaz Redondo
Venue: Proceedings of the 26th International Computer Software and Applications Conference on Prolonging Software Life: Development and Redevelopment (2002)

We adapt in this paper an analysis-revision cycle to the SCTL-MUS methodology to support the modification and evolution of requirements specifications in a multi-perspectiveenvironment.To illustrate the advantages of using our approach in the analysis and revision phases, we employ two viewpoints of a thermostat system. Both viewpoints are merged in order to be able to reason over the properties of the composed system. The refinements over the merged model are transferred into each one of the viewpoints and then into the requirements in which both ones are expressed. In this way, we obtain requirements refinements close to the system domain of each viewpoint, facilitating to the stakeholders the decision of what system requirements refinements must be included in the system requirements specification.
Run-Time Selection of Block Size in Pipelined Parallel Programs
Authors: David K. Lowenthal, Michael James
Venue: Proceedings of the 13th International Symposium on Parallel Processing and the 10th Symposium on Parallel and Distributed Processing (1999)

Parallelizing compiler technology has improved in recent years. One area in which compilers have made progress is in handling DOACROSS loops, where cross-processor data dependencies can inhibit efficient parallelization. In regular DOACROSS loops, where dependencies can be determined at compile time, a useful parallelization technique is pipelining, where each processor (node) performs its computation in blocks; after each, it sends data to the next processor in the pipeline. The amount of computation before sending a message is called the block size; its choice, although difficult for a compiler to make, is critical to the efficiency of the program. Compilers typically use a static estimation of workload, which cannot always produce an effective block size. This paper describes a flexible run-time approach to choosing the block size. Our system takes measurements during the first iteration of the program and then uses the results to build an execution model and choose an appropriate block size which, unlike those chosen by compiler analysis, may be nonuniform. Performance on a network of workstations shows that programs using our run-time analysis outperform those that use static block sizes when the workload is either unbalanced or unanalyzable. On more regular programs, our programs are competitive with their static counterparts.