Hardware architectures of elliptic curve based cryptosytems over binary fields
Authors: Kris Gaj
Venue:  (2007)

Public key cryptosystems were invented in 1976 by Whitfield Diffie and Martin Hellman to solve the security problems such as confidentiality, authenticity, integrity and non-repudiation during communications in public networks. The first practical realization, namely RSA, was proposed by Ron Rivest, Adi Shamir and Len Adleman in 1977. The security of RSA is based on the hardness of factoring large integers. In 1985, Neal Koblitz and Victor Miller independently discovered elliptic curve cryptography (ECC), which can provide the same functionality as RSA. Its security is based on the elliptic curve discrete logarithm problem (ECDLP). Compared with RSA, ECC can achieve the same security strength with smaller key sizes. Weil and Tate pairings were originally used to break elliptic curve protocols. However since Joux proposed the idea of applying pairings in tripartite Diffe-Hellman protocol many scholars have been interested in constructing new cryptographic protocols based on pairing schemes. This thesis concentrates on the efficient hardware architectures of elliptic curve based cryptosystems over binary fields. These architectures require superior design for finite field arithmetic. We derive the digit-serial multiplier for these underlying fields constructed via low Hamming weight irreducible polynomials such as trinomials or pentanomials. For normal basis (NB) multipliers, the methods of shortening the critical path and simplifying the complexity are also covered. We present a new hybrid architecture whereby not only the circuit complexity can be decreased but also the basis conversion can be simplified. Aside from the field arithmetic unit, other issues such as top architecture, parallel computations, sharing resource and efficient control should be necessarily considered to improve the design efficiency. Different target platforms for ECC are investigated. We have designed a low latency ECC accelerator via a single FPGA device based on L&oacute;pez-Dahab algorithm, which can run 1.5-to-3 times faster than the one designed by the research group of Sun Microsystems, with approximately the same cost. Furthermore the design methodology for ECC library aimed for a reconfigurable computer, SRC-6, is addressed. Tate pairing based cryptosystems have recently emerged as an alternative to traditional public key cryptosystems, because of their ability to be used in multi-party identity-based key management schemes. Due to the inherent parallelism of the existing pairing algorithms, high performance can be achieved via hardware realizations. In this work, a new FPGA-based architecture of the Tate pairing-based computation over binary fields was proposed. The computational latency for one pairing has been reduced, and our implementation runs 10-to-20 times faster than the equivalent implementations of other pairing-based schemes at the same level of security strength. Additionally, an improvement in the product of latency by area by a factor between 12 and 46 for an equivalent type of implementation has been achieved. Furthermore, we have also ported our pairing designs for 8 field sizes ranging from 239 to 557 to the reconfigurable computer, SGI Altix-4700 supported by Silicon Graphics, Inc., and the performance and cost have been characterized. Our research demonstrates that both software and hardware implementations of pairing-based cryptosytems can operate at a similar speed and security level as traditional elliptic curve cryptosystems.