ppxscal/embedding_network huggingface dataset:
Autonomous development of relationships among web servers for facilitating information utilization
Authors: Shin-Ya Sato, Masanori Harada, Kazuhiro Kazama
Venue: Systems and Computers in Japan (2004)

A Web server can play a role as an agent for people who create information, and Web servers with related information can be searched by the agent in order to facilitate efficient information utilization on the Web. Web servers exchange information with other servers and select which ones to keep or abandon, resulting in an increase in the links with servers with greater relevance. As a result, a community, a group of Web servers that are mutually linked, is created. A Web server community can be used as a place for various forms of information utilization and exchange, such as meta-searches and contents syndication. In this paper, the authors propose an algorithm for creating communities after evaluating the meaning of facilitating information utilization via a community. They then verify the validity of their idea through simulations. &copy; 2004 Wiley Periodicals, Inc. Syst Comp Jpn, 35(10): 40&ndash;49, 2004; Published online in Wiley InterScience (). DOI 10.1002&sol;scj.10659
Reducing Power with Performance Constraints for Parallel Sparse Applications
Authors: G. Chen, K. Malkowski, M. Kandemir, P. Raghavan
Venue: Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 11 - Volume 12 (2005)

Sparse and irregular computations constitute a large fraction of applications in the data-intensive scientific domain. While every effort is made to balance the computational workload in such computations across parallel processors, achieving sustained near machine-peak performance with close-to-ideal load balanced computationto-processor mapping is inherently difficult. As a result, most of the time, the loads assigned to parallel processors can exhibit significant variations. While there have been numerous past efforts that study this imbalance from the performance viewpoint, to our knowledge, no prior study has considered exploiting the imbalance for reducing power consumption during execution. Power consumption in large-scale clusters of workstations is becoming a critical issue as noted by several recent research papers from both industry and academia. Focusing on sparse matrix computations in which underlying parallel computations and data dependencies can be represented by trees, this paper proposes schemes that save power through voltage/frequency scaling. Our goal is to reduce overall energy consumption by scaling the voltages/frequencies of those processors that are not in the critical path; i.e., our approach is oriented towards saving power without incurring performance penalties.
Too many cooks
Authors: Dustin Beltram
Venue: interactions (2005)

This is the first in a series of articles dedicated to exploring the unique challenges facing designers, customers and users of enterprise software. "Enterprise software?" you say. "What a snooze fest." Well, yes, I might agree with you there. But I'll work hard to make this as interesting and useful as possible. In the months ahead, I'll explore scenarios that illuminate these challenges and, hopefully, shed a little light on how to deal with them. I'll also be talking with practitioners in the field to get their opinions and insights. If you have thoughts you'd like to share on the subject, feel free to send me an email at dbeltramo@acm.org. See you next issue.
Hierarchical Binary Set Partitioning in Cache Memories
Authors: Hamid Reza Zarandi, Hamid Sarbazi-Azad
Venue: The Journal of Supercomputing (2005)

In this paper, a new cache placement scheme is proposed to achieve higher hit ratios with respect to the two conventional schemes namely set-associative and direct mapping. Similar to set-associative, in this scheme, cache space is divided into sets of different sizes. Hence, the length of tag fields associated to each set is also variable and depends on the partition it is in. The proposed mapping function has been simulated with some standard trace files and statistics are gathered and analyzed for different cache configurations. The results reveal that the proposed scheme exhibits a higher hit ratio compared to the two well-known mapping schemes, namely set-associative and direct mapping, using LRU replacement policy.
Probabilistic Modeling-Based Vessel Enhancement in Thoracic CT Scans
Authors: Gady Agam, Changhua Wu
Venue: Proceedings of the 2005 IEEE Computer Society Conference on Computer Vision and Pattern Recognition (CVPR'05) - Volume 2 - Volume 02 (2005)

Vessel enhancement in volumetric data is a necessary prerequisite in various medical imaging applications with particular importance for automated nodule detection. Ideally, vessel enhancement filters should enhance vessels and vessel junctions while suppressing nodules and other non-vessel elements. A distinction between vessels and nodules is normally obtained through eigenvalue analysis of the curvature tensor which is a second order differential quantity and so is sensitive to noise. Furthermore, by relying on principal curvatures alone, existing vessel enhancement filters are incapable of distinguishing between nodules and vessel junctions. In this paper we propose probabilistic vessel models from which novel vessel enhancement filters capable of enhancing junctions while suppressing nodules are derived. The proposed filters are based on eigenvalue analysis of the structure tensor which is a first order differential quantity and so are less sensitive to noise. The proposed filters are evaluated and compared to known techniques based on actual clinical data.
Toric Initial Ideals of Δ-Normal Configurations: Cohen-Macaulayness and Degree Bounds
Authors: Edwin O'Shea, Rekha R. Thomas
Venue: Journal of Algebraic Combinatorics: An International Journal (2005)

A normal (respectively, graded normal) vector configuration $${\cal A}$$ defines the toric ideal $${I}_{\cal A}$$ of a normal (respectively, projectively normal) toric variety. These ideals are Cohen-Macaulay, and when $${\cal A}$$ is normal and graded, $${I}_{\cal A}$$ is generated in degree at most the dimension of $${I}_{\cal A}$$ . Based on this, Sturmfels asked if these properties extend to initial ideals--when $${\cal A}$$ is normal, is there an initial ideal of $${I}_{\cal A}$$ that is Cohen-Macaulay, and when $${\cal A}$$ is normal and graded, does $${I}_{\cal A}$$ have a Gröbner basis generated in degree at most dim( $${I}_{\cal A}$$ ) ? In this paper, we answer both questions positively for ¿-normal configurations. These are normal configurations that admit a regular triangulation ¿ with the property that the subconfiguration in each cell of the triangulation is again normal. Such configurations properly contain among them all vector configurations that admit a regular unimodular triangulation. We construct non-trivial families of both ¿-normal and non-¿-normal configurations.
Waiting patterns for a printer
Authors: D. Merlini, R. Sprugnoli, M. C. Verri
Venue: Discrete Applied Mathematics (2004)

We introduce a model based on some combinatorial objects, which we call l-histograms, to study the behaviour of devices like printers and use the combinatorial properties of these objects to study some important distributions such as the waiting time for a job and the length of the device queue. This study is based on an important relation between 1-histograms, generating trees and binary trees.
Windows XP: Visual QuickStart Guide (2nd Edition) (Visual Quickstart Guides)
Authors: Chris Fehily
Venue:  (2005)

If you've recently installed the latest Windows XP update, Service Pack 2, or just want to get to know your operating system a little better, you'll want this thoroughly updated, task-based reference from veteran author Chris Fehily.In typical, to-the-point, Visual QuickStart style, Chris gets right down to business, introducing you to the Window XP interface before moving on to topics such as installing and removing programs; working with documents, accessories, and multimedia; going online; printing; handling hardware issues; and maintenance.Step-by-step instructions and loads of tips, tricks, and visual aids make all of Windows XP's features instantly accessible, including those new in Service Pack 2: Windows Security Center, Pop-Up Blocker, Windows Firewall, and more! In no time, you'll be using the desktop, working with files, and using Internet Explorer, Outlook Express, Windows Media Player, Movie Maker, and more.
Hopfield Neural Networks for Parametric Identification of Dynamical Systems
Authors: Miguel Atencia, Gonzalo Joya, Francisco Sandoval
Venue: Neural Processing Letters (2005)

In this work, a novel method, based upon Hopfield neural networks, is proposed for parameter estimation, in the context of system identification. The equation of the neural estimator stems from the applicability of Hopfield networks to optimization problems, but the weights and the biases of the resulting network are time-varying, since the target function also varies with time. Hence the stability of the method cannot be taken for granted. In order to compare the novel technique and the classical gradient method, simulations have been carried out for a linearly parameterized system, and results show that the Hopfield network is more efficient than the gradient estimator, obtaining lower error and less oscillations. Thus the neural method is validated as an on-line estimator of the time-varying parameters appearing in the model of a nonlinear physical system.
Parallel parsing of MPEG video on a shared-memory symmetric multiprocessor
Authors: Suchendra M. Bhandarkar, Shankar R. Chandrasekaran
Venue: Parallel Computing (2004)

Video parsing refers to the detection and classification of abrupt and gradual scene changes in a video stream. The detection of these changes forms an important preprocessing step in applications that treat videos as sources of information. The parsed video is subsequently indexed to support content-based retrieval, navigation and browsing. Analysis of video streams is computationally intensive with high data processing bandwidth requirements. Shared-memory symmetric multiprocessors (SMPs) have become increasingly ubiquitous and affordable. Parallel processing on an shared-memory symmetric multiprocessor is hence proposed as a means of dealing with the computational demands of video parsing. Parallel versions of two algorithms that detect scene transitions in compressed video streams are proposed. Both algorithms entail minimal decompression of the MPEG video. Three granularities of parallelism based on data decomposition and task decomposition are investigated; Group of Pictures (GOP), Frame and Slice. Results of an SMP implementation show that the GOP-level implementation, which represents the coarsest granularity of task and data decomposition, performs the best in terms of speedup and synchronization overhead. The slice and frame levels of granularity take second and third place, respectively. The speedup is observed to be almost linear in the case of the GOP level of granularity, whereas the synchronization overheads are observed to be high for the flame and slice levels of granularity.
The importance of presentation skills in the classroom: students and instructors perspectives
Authors: Khaled Alshare, Nitham M. Hindi
Venue: Journal of Computing Sciences in Colleges (2004)

Employers are demanding graduates with excellent communication (written, oral, and listening) skills. Thus, a student's presentation in the classroom becomes an important element in delivering positive learning experiences. This paper explored the role of students' presentation in the classroom from students and instructors' perspectives. The results of the study showed that forty-three percent of respondents indicated students were required to present in two classes per semester for an average of 10 minutes. Students and instructors agreed that critical objectives of presentations were to improve communication skills and to train students to talk to a group of people. However, the two groups differed on ranking the presentation evaluation. While instructors ranked "the content of presentation" in the first place, students ranked "the organization of the presentation" as their first choice. Both groups, however, agreed that "well-organized presentation" and "enjoyable content" were the two most important measures of presentation effectiveness. Students' responses showed no statistical significance between the grade assigned and the grade that should be assigned for presentation. While the majority of graduate students (70 percent) reported 11--20 minutes for presentation period, undergraduates indicated 10 minutes (68 percent). Undergraduate students thought handouts were the most important visual aid compared to graduate students who preferred PowerPoint. The paper concluded by providing a checklist of items for effective and ineffective presentations.
Post-Adoption Variations in Usage and Value of E-Business by Organizations: Cross-Country Evidence from the Retail Industry
Authors: Kevin Zhu, Kenneth L. Kraemer
Venue: Information Systems Research (2005)

Grounded in the innovation diffusion literature and the resource-based theory, this paper develops an integrative research model for assessing the diffusion and consequence of e-business at the firm level. Unlike the typical focus on adoption as found in the literature, we focus on postadoption stages, that is, actual usage and value creation. The model thus moves beyond dichotomous "adoption versus nonadoption" and accounts for the "missing link"--actual usage--as a critical stage of value creation. The model links technological, organizational, and environmental factors to e-business use and value, based on which a series of hypotheses are developed. The theoretical model is tested by using structural equation modeling on a dataset of 624 firms across 10 countries in the retail industry. To probe deeper into whether e-business use and value are influenced by economic environments, two subsamples from developed and developing countries are compared. The study finds that technology competence, firm size, financial commitment, competitive pressure, and regulatory support are important antecedents of e-business use. In addition, the study finds that, while both front-end and back-end capabilities contribute to e-business value, back-end integration has a much stronger impact. While front-end functionalities are becoming commodities, e-businesses are more differentiated by back-end integration. This is consistent with the resource-based theory because back-end integration possesses the value-creating characteristics of resources (e.g., firm specific, difficult to imitate), which are strengthened by the Internet-enabled connectivity. Our study also adds an international dimension to the innovation diffusion literature, showing that careful attention must be paid to the economic and regulatory factors that may affect technology diffusion across different countries.
An FPGA design of AES encryption circuit with 128-bit keys
Authors: Hui Qin, Tsutomu Sasao, Yukihiro Iguchi
Venue: Proceedings of the 15th ACM Great Lakes symposium on VLSI (2005)

This paper addresses a pipelined partial rolling (PPR) architecture for the AES encryption. The key technique is the PPR architecture, which is suitable for FPGA implementation. Using the proposed architecture on the Altera Stratix EP1S20F780C5 FPGA, the AES-4SM achieves a throughput of 5.61 Gbps by using 20 M4Ks, and the AES-8SM achieves a throughput of 10.49 Gbps by using 40 M4Ks. Compared with the unrolling implementation that achieves a throughput of 20.48 Gbps by using 80 M4Ks on the same FPGA, implementations with the PPR architecture reduce the amount of memory up to 75% while increasing the memory efficiency (i.e., throughput divided by the size of memory for core) up to 9.6%.The PPR architecture.lls the gap between unrolling and rolling architectures,and.ts on less expensive FPGAs.
Current awareness on comparative and functional genomics: Current Awareness
Authors: Staff
Venue: Comparative and Functional Genomics (2005)

In order to keep subscribers up-to-date with the latest developments in their field, this current awareness service is provided by John Wiley & Sons and contains newly-published material on comparative and functional genomics. Each bibliography is divided into 16 sections. 1 Reviews & symposia; 2 General; 3 Large-scale sequencing and mapping; 4 Genome evolution; 5 Comparative genomics; 6 Gene families and regulons; 7 Pharmacogenomics; 8 Large-scale mutagenesis programmes; 9 Functional complementation; 10 Transcriptomics; 11 Proteomics; 12 Protein structural genomics; 13 Metabolomics; 14 Genomic approaches to development; 15 Technological advances; 16 Bioinformatics. Within each section, articles are listed in alphabetical order with respect to author. If, in the preceding period, no publications are located relevant to any one of these headings, that section will be omitted. The ACM Portal is published by the Association for Computing Machinery. Copyright © 2010 ACM, Inc. Terms of Usage Privacy Policy Code of Ethics Contact Us Useful downloads: Adobe Acrobat QuickTime Windows Media Player Real Player
ChipLock: support for secure microarchitectures
Authors: Taeho Kgil, Laura Falk, Trevor Mudge
Venue: ACM SIGARCH Computer Architecture News (2005)

The increasing need for security has caused system designers to consider placing some security support directly at the hardware level. In fact, this is starting to emerge as an important consideration in processor design, because the performance overhead of supporting security in hardware is usually significantly lower than a complete software solution. In this paper, we investigate integrating some security support into hardware. We show that security support can be added at some acceptable cost in area and performance. We propose a processor extension called ChipLock. It provides hardware security support for a mostly untrusted operating system to ensure the integrity and confidentiality of all computational results. ChipLock's modular design can be easily integrated into existing hardware platforms with only slight modification to the operating system. ChipLock includes a built-in hardware Key Manager that supports symmetric key assignment, and a read-only-memory, TrustROM, that executes secure hardware routines. The software required is a small trusted portion of the operating system called Trust-Code. We modeled ChipLock's architecture on a full system simulator and showed that, for SPEC2000 benchmarks, it adds about an average of 20% to the execution time, primarily from cryptographic and verification latencies. In addition, layout studies show an area cost of about 8 mm2 in 180 nm technology. This translates to an area overhead of 5% ~ 15% depending on the processor type.
Adaptive Resource Utilization via Feedback Control for Streaming Applications
Authors: Hasnain A. Mandviwala, Nissim Harel, Umakishore Ramachandran, Kathleen Knobe
Venue: Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Papers - Volume 01 (2005)

A large emerging class of interactive multimedia streaming applications that are highly parallel can be represented as a coarse-grain, pipelined, data-flow graph. One common characteristic of these applications is their use of current data: A task would obtain the latest data from preceding stages, skipping over older data items if necessary to perform its computation. When parallelized, such applications waste resources because they process and keep data in memory that is eventually dropped from the application pipeline. To overcome this problem, we have designed and implemented an Adaptive Resource Utilization (ARU) mechanism that uses feedback to dynamically adjusts the resources each task running thread utilizes so as to minimize wasted resource use by the entire application. A color-based people tracker application is used to explore the performance benefits of the proposed mechanism. We show that ARU reduces the application's memory footprint by two-thirds compared to our previously published results, while also improving latency and throughput of the application.
Hardware Based Online Profiling in AMIDAR Processors
Authors: Stephan Gatzka, Christian Hochberger
Venue: Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04 (2005)

Dynamically reconfigurable architectures offer the opportunity to migrate software into hardware functional units at runtime. Architectures derived from the AMIDAR model exhibit such possibilities. Yet, the question has to be answered, which parts of the running application should be transformed into hardware. The migration of complete methods or procedures into hardware is often not feasible. In this contribution we show a hardware circuit that enables the processor to collect an execution profile of Java methods with a high resolution. We also show, how this profile information can be used to make reasonable choices for candidate instruction sequences.
A unified processor architecture for RISC & VLIW DSP
Authors: Tay-Jyi Lin, Chie-Min Chao, Chia-Hsien Liu, Pi-Chen Hsiao, Shin-Kai Chen, Li-Chun Lin, Chih-Wei Liu, Chein-Wei Jen
Venue: Proceedings of the 15th ACM Great Lakes symposium on VLSI (2005)

This paper presents a unified processor core with two operation modes. The processor core works as a compiler-friendly MIPS-like core in the RISC mode, and it is a 4-way VLIW in its DSP mode, which has distributed and ping-pong register organization optimized for stream processing. To minimize hardware, the DSP mode has no control construct for program flow, while the data manipulation RISC instructions are executed in the DSP datapath. Moreover, the two operation modes can be changed instruction by instruction within a single program stream via the hierarchical instruction encoding, which also helps to reduce the VLIW code sizes significantly. The processor has been implemented in the UMC 0.18um CMOS technology, and its core size is 3.23mmx3.23mm including the 32KB on-chip memory. It can operate at 208MHz while consuming 380.6mW average power.