ppxscal/embedding_network huggingface dataset:
Implementing a GKS-like graphics package on a microcomputer
Authors: Michael K. Mahoney
Venue: ACM SIGCSE Bulletin (1989)

A variable-length project for an introductory upper-division computer graphics course for majors is described. The project consists of the implementation of a graphics package based on the Graphical Kernel System (GKS, an ISO and ANSI standard) and application programs which demonstrate features of GKS. Any microcomputer with graphics capabilities equipped with an appropriate compiler can be used for the project. It is assumed that the reader is familiar with the basic concepts of 2D computer graphics. A brief introduction to GKS is included.
Next: the elimination of Goto-patches?
Authors: D. Jonsson
Venue: ACM SIGPLAN Notices (1989)

It is argued that the elimination of goto-statements within the context of structured programming has often been achieved through the introduction of 'goto-patches'. Seven common goto-patches are identified and exemplified. Finally, it is suggested that the control structures used in 'pancode' make it possible to eliminate goto-patches as well as goto-statements.
APL2 implementation of numerical asset pricing models
Authors: W. Foote, J. Kraemer, G. Foster
Venue: ACM SIGAPL APL Quote Quad (1987)

The practice of modern finance theory depends on an ability to generate accurate and timely forecasts of asset returns. In this field, considerable effort has been expended to base the generation of asset returns on a set of state variables driven by the dynamics of the environment. This requires the solution of a fundamental parabolic partial differential equation, often with variable coefficient, and with a wide range of specification of boundary and initial value conditions. A major drawback in financial management of large, real-time problems of this sort is that they require numerical intensive computing. Approximations or simplifications are used. The one state variable model of Black and Scholes [Bla73] leads to a closed form solution of the value of a call option, as explored in an APL solution by Bogart [Bog87]. The two state variable model of Brennan and Schwartz [Bre79, Sch84] determines the value of an intermediate maturity bond whose value depends upon the dynamic evolution of: a short-term rate, such as the 3 month Treasury Bill rate, and a long term rate, such as the 30 year Treasury bond rate. This solution does not have a closed form and must be solved numerically or approximately. This paper describes a formulation of the Brennan and Schwartz model; develops a finite difference representation; describes the strategy for an APL2 implementation; and illustrates the results with the run of an application.
Optical link and processor clustering in the delft parallel processor
Authors: L. Dekker, E. E. E. Frietman
Venue: Proceedings of the 2nd international conference on Supercomputing (1988)

The avoidance of transfer-bound processing in large parallel computers is first analyzed with respect to the processor interconnectability. A quantitative measure is introduced for the processor substask interactivity, based on the number on nonzeroes in the interaction matrix. A similar quantitative measure can be introduced for the processor interconnectability in case of a multi-bus communication system. For a parallel computer with p processors and p busses the asymptotic speedup for large p is proportional to p, both for tightly and loosely coupled tasks. In case of 2-level parallelization considerably more speedup can be obtained by application of powerful interconnects at both levels. As to the question compute- versus transfer-bound processing, it is discussed that also the choice of the data exchange protocol is of great importance. It proves that the 'newspaper' protocol in combination with full processor interconnectability is an appropriate way to avoid transfer-bound processing. For a parallel computer with many processors one global newspaper for all processors may frequently result in a too small efficiency. An improvement can be obtained through the introduction of a multi-newspaper protocol, based on the interaction matrix as a function of time. It is elucidated that this protocol requires dynamic processor clustering during a parallel run. The Delft Parallel Processor DPP84 (with maximally 16 processors) is mentioned as an example of a parallel processor, based on complete processor interconnectability, where electrical interconnects have been applied. It is discussed that for large parallel computers, like the DPP8X (with maximally 1000 processors) full interconnectability is only feasible by the way of optical interconnects, consisting of a combination of optical wave guides and free space kaleidoscopic devices and provided with multi-input, multi-output electro-to-optic and opto-o-electric transducers. As an example of an opto-to-electric transducer, the POWERRAM is discussed. This transducer has been realized as a prototype multi-accessible processor input memory IC capable to accept a multi-variable input in one data transfer clock cycle.
Plugging the holes in the sieve of eratosthenes
Authors: K. Dritc
Venue: ACM SIGAda Ada Letters (1989)

Several subtle errors in an Ada tasking realization of the well-known Sieve of Eratosthenes algorithm are revealed and corrected. By discussing them here, we hope to increase the tutorial value of the original publication (G. E. Anderson in Ada Letters, September/October 1988).
A denotational semantics of inheritance and its correctness
Authors: W. Cook, J. Palsberg
Venue: ACM SIGPLAN Notices (1989)

This paper presents a denotational model of inheritance. The model is based on an intuitive motivation of the purpose of inheritance. The correctness of the model is demonstrated by proving it equivalent to an operational semantics of inheritance based upon the method-lookup algorithm of object-oriented languages. Although it was originally developed to explain inheritance in object-oriented languages, the model shows that inheritance is a general mechanism that may be applied to any form of recursive definition.
Parallel pattern fault simulation of path delay faults
Authors: M. Schulz, F. Fink, K. Fuchs
Venue: Proceedings of the 26th ACM/IEEE Design Automation Conference (1989)

This paper presents an accelerated fault simulation approach for path delay faults. The distinct features of the proposed fault simulation method consist in the application of parallel processing of patterns at all stages of the calculation procedure, its versatility to account for both robust and non-robust detection of path delay faults, and its capability of efficiently maintaining large numbers of path faults to be simulated.
A graphics interface for linear programming
Authors: Pai-Chun Ma, Frederic H. Murphy, Edward A. Stohr
Venue: Communications of the ACM (1989)

We describe the interface to a software system that assists users in the process of formulating linear programming models. The main idea is to introduce a new representation that allows modelers to depict their problems in a graphical rather than mathematical form. This representation is described in detail together with a number of other interface design principles that we believe will aid modelers&mdash;including hierarchical decomposition, multiple model representations, alternative formulation approaches, the use of model templates, and database and model management facilities. These features are illustrated using the output of a prototype system formulating a realistic LP problem.
Multiplier/Shifter Design Tradeoffs in a 32-bit Microprocessor
Authors: V. Milutinovic, M Bettinger, W. Helbig
Venue: IEEE Transactions on Computers (1989)

The authors concentrate on design tradeoffs between the bit-serial multiplier and the full barrel shifter combined with a large register file. They analyze and compare three alternatives for a given set of technology related parameters and a given set of higher level language (HLL) benchmarks. Although their basic concern is the design of a 32-bit GaAs microprocessor on a single chip, the implications of the results are more general.
MIOS: a flexible system for PCB manufacturing
Authors: A. C. Hung, P. M. Reddy, P. J. Hammer
Venue: Proceedings of the 26th ACM/IEEE Design Automation Conference (1989)

A machine insertion and onsertion system (MIOS) for printed-circuit board (PCB) assembly has been developed. This system features linkage from multiple PCB CAD systems to multiple placement machines. We have found that the MIOS is well suited for flexible manufacturing in a multi-CAD, multi-machine, and multi-site environment. The system maintains manufacturing data independent of its source CAD systems and its destination placement machines. Because of this data independency, the MIOS also enables resource sharing&mdash;including equipment and personnel&mdash;among all sites. Higher quality comes as a result of automatic program generation. Faster turnaround makes prototyping and production equally efficient. Visualization through the graphical user interface enhances sense of participation. Additionally, the complexity of software development has been reduced significantly.
Some statistics on Gaussian elimination with partial pivoting
Authors: A. J. Macleod
Venue: ACM SIGNUM Newsletter (1989)

There has recently been an upsurge of work on the (by now) classical problem of the stability of Gaussian elimination e.g., the papers of Trefethen amp; Schreiber [5], and Higham and Higham [2]. This short note describes some experimental results in this area derived by the author. They are described more fully in a technical report [4].
Quantifier elimination: Optimal solution for two classical examples
Authors: Daniel Lazard
Venue: Journal of Symbolic Computation (1988)

Optimal solutions are given for the two following problems: the condition for a degree 4 polynomial to have only positive values and the condition for an ellipse to be inside the unit circle.
Parallel processing on supercomputers: a set of computional experiments
Authors: N. Balram, C. Belo, J. M. F. Moura
Venue: Proceedings of the 1988 ACM/IEEE conference on Supercomputing (1988)

One of the trends in supercomputer evolution lies in the direction of multiprocessor systems with increasing numbers of powerful processors. The user who is interested in attaining the maximum achievable computation rates on these machines must understand the philosophy underlying the parallel processing mechanisms provided on them. This paper focuses on the three types of parallelism currently available on the Cray: vectorization, microtasking, and macrotasking. Experiences with all three constructs are presented with a view to exposing the improvements possible with each of them. While this paper deals with a particular machine, the Cray X-MP/48, many of the observations, comments, and conclusions derived can be generalized to other shared-memory multiprocessor systems.
Ray tracing deterministic 3-D fractals
Authors: J. C. Hart, D. J. Sandin, L. H. Kauffman
Venue: ACM SIGGRAPH Computer Graphics (1989)

As shown in 1982, Julia sets of quadratic functions as well as many other deterministic fractals exist in spaces of higher dimensionality than the complex plane. Originally a boundary-tracking algorithm was used to view these structures but required a large amount of storage space to operate. By ray tracing these objects, the storage facilities of a graphics workstation frame buffer are sufficient. A short discussion of a specific set of 3-D deterministic fractals precedes a full description of a ray-tracing algorithm applied to these objects. A comparison with the boundary-tracking method and applications to other 3-D deterministic fractals are also included.
SIM: a database system based on the semantic data model
Authors: D. Jagannathan, B. L. Fritchman, R. L. Guck, J. P. Thompson, D. M. Tolbert
Venue: Proceedings of the 1988 ACM SIGMOD international conference on Management of data (1988)

SIM is a fully featured, commercially available database management system based on a semantic data model similar to Hammer and McLeod's SDM SIM has two primary modeling goals. The first is to narrow the gap between a user's real-world perception of data and the conceptual view imposed by the database system because of modeling presuppositions or limitations. The second goal is to allow, as much as possible, the semantics of data to be defined in the schema and make the database system responsible for enforcing its integrity SIM provides a rich set of constructs for schema definition, including those for specifying generalization hierarchies modeled by directed acyclic graphs, interobject relationships and integrity constraints. It also features a novel, easy-to-use, English-like DML. This paper describes the key modeling features of SIM, the architecture of the system and its implementation considerations.
On Serial-Input Multipliers for Two's Complement Numbers
Authors: L. Dadda
Venue: IEEE Transactions on Computers (1989)

The author shows that a multiplier already proposed by T. Rhyne and N.R. Strader for unsigned numbers can be used for two's complement numbers as well, provided only that the content of the input registers is held constant, after the introduction of the operand's sign bits, for a number of clock periods equal to the operand's length. The result is derived by the properties of sign-extended two's complement numbers. The known multiplier includes a linear array of (5, 3) parallel counters and a set of three static registers for the internal carriers. It is shown that a logically equivalent multiplier can be built using two linear arrays of full adders and two carry registers. In a faster circuit, an additional carry register is required.
Tradeoffs in instruction format design for horizontal architectures
Authors: Gurindar S. Sohi, Sriram Vajapeyam
Venue: ACM SIGARCH Computer Architecture News (1989)

With recent improvements in software techniques and the enhanced level of fine grain parallelism made available by such techniques, there has been an increased interest in horizontal architectures and large instruction words that are capable of issuing more that one operation per instruction. This paper investigates some issues in the design of such instruction formats. We study how the choice of an instruction format is influenced by factors such as the degree of pipelining and the instruction's view of the register file. Our results suggest that very large instruction words capable of issuing one operation to each functional unit resource in a horizontal architecture may be overkill. Restricted instruction formats with limited operation issuing capabilities are capable of providing similar performance (measured by the total number of time steps) with significantly less hardware in many cases.
A trade-off between space and efficiency for routing tables
Authors: David Peleg, Eli Upfal
Venue: Journal of the ACM (JACM) (1989)

Two conflicting goals play a crucial role in the design of routing schemes for communication networks. A routing scheme should use paths that are as short as possible for routing messages in the network, while keeping the routing information stored in the processors' local memory as succinct as possible. The efficiency of a routing scheme is measured in terms of its stretch factor-the maximum ratio between the length of a route computed by the scheme and that of a shortest path connecting the same pair of vertices. Most previous work has concentrated on finding good routing schemes (with a small fixed stretch factor) for special classes of network topologies. In this paper the problem for general networks is studied, and the entire range of possible stretch factors is examined. The results exhibit a trade-off between the efficiency of a routing scheme and its space requirements. Almost tight upper and lower bounds for this trade-off are presented. Specifically, it is proved that any routing scheme for general n-vertex networks that achieves a stretch factor k &ge; 1 must use a total of &OHgr;(n1+1/(2k+4)) bits of routing information in the networks. This lower bound is complemented by a family K(k) of hierarchical routing schemes (for every k &ge; l) for unit-cost general networks, which guarantee a stretch factor of O(k), require storing a total of O(k3n1+(1/h)logn)- bits of routing information in the network, name the vertices with O(log2n)-bit names and use O(logn)-bit headers.
Declustering using error correcting codes
Authors: C. Faloutsos, D. Metaxas
Venue: Proceedings of the eighth ACM SIGACT-SIGMOD-SIGART symposium on Principles of database systems (1989)

The problem examined is to distribute a binary Cartesian product file on multiple disks to maximize the parallelism for partial match queries. Cartesian product files appear as a result of some secondary key access methods, such as the multiattribute hashing [10], the grid file [6] etc.. For the binary case, the problem is reduced into grouping the 2n binary strings on n bits in m groups of unsimilar strings. The main idea proposed in this paper is to group the strings such that the group forms an Error Correcting Code (ECC). This construction guarantees that the strings of a given group will have large Hamming distances, i.e., they will differ in many bit positions. Intuitively, this should result into good declustering. We briefly mention previous heuristics for declustering, we describe how exactly to build a declustering scheme using an ECC, and we prove a theorem that gives a necessary condition for our method to be optimal. Analytical results show that our method is superior to older heuristics, and that it is very close to the theoretical (non-tight) bound.
Dynamic query evaluation plans
Authors: G. Graefe, K. Ward
Venue: ACM SIGMOD Record (1989)

In most database systems, a query embedded in a program written in a conventional programming language is optimized when the program is compiled. The query optimizer must make assumptions about the values of the program variables that appear as constants in the query, the resources that can be committed to query evaluation, and the data in the database. The optimality of the resulting query evaluation plan depends on the validity of these assumptions. If a query evaluation plan is used repeatedly over an extended period of time, it is important to determine when reoptimization is necessary. Our work aims at developing criteria when reoptimization is required, how these criteria can be implemented efficiently, and how reoptimization can be avoided by using a new technique called dynamic query evaluation plans. We experimentally demonstrate the need for dynamic plans and outline modifications to the EXODUS optimizer generator required for creating dynamic query evaluation plans.
The architecture of a user interface toolkit
Authors: Carl Binding
Venue: Proceedings of the 1st annual ACM SIGGRAPH symposium on User Interface Software (1988)

This paper describes an architecture for a user interface toolkit. It presents the proper layering of the software, describes the architectural model of user interface components or tools, and discusses the software engineering implications of the architecture. We also present a sample toolkit that was built using the presented architecture and that has been in use since 1985.
The fuzzball
Authors: D. L. Mills
Venue: Symposium proceedings on Communications architectures and protocols (1988)

The Fuzzball is an operating system and applications library designed for the PDP11 family of computers. It was intended as a development platform and research pipewrench for the DARPA/NSF Internet, but has occasionally escaped to earn revenue in commercial service. It was designed, implemented and evolved over a seventeen-year era spanning the development of the ARPANET and TCP/IP protocol suites and can today be found at Internet outposts from Hawaii to Italy standing watch for adventurous applications and enduring experiments. This paper describes the Fuzzball and its applications, including a description of its novel congestion avoidance/control and timekeeping mechanisms.
Workspace `Maze'
Authors: A. Camacho
Venue: ACM SIGAPL APL Quote Quad (1989)

Devised to solve a problem in the design of coloured mazes, the maze workspace strikingly improved the competitive advantage of Minotaur Designs.The differences between monochrome and coloured mazes call for unexpected variations in the processing.The system described was a finalist in the Peat Marwick Mitchell/PC User BenefIT awards competition in 1988.
Analysis of Thinning Algorithms Using Mathematical Morphology
Authors: B. K. Jang, R. T. Chin
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1990)

A precise definition of digital skeletons and a mathematical framework for the analysis of a class of thinning algorithms, based on morphological set transformation, are presented. A particular thinning algorithm (algorithm A) is used as an example in the analysis. Precise definitions and analyses associated with the thinning process are presented, including the proof of convergence, the condition for one-pixel-thick skeletons, and the connectedness of skeletons. In addition, a necessary and sufficient condition for the thinning process in general is derived, and an algorithm (algorithm B) based on this condition is developed. Experimental results are used to compare the two thinning algorithms, and issues involving noise immunity and skeletal bias are addressed.
IShell: a visual UNIX shell
Authors: Kjell Borg
Venue: Proceedings of the SIGCHI conference on Human factors in computing systems: Empowering people (1990)

IShell is a visual user interface for interaction using gestures under the UNIX operating system. A visual script language for building commands &mdash; IScript &mdash; is an integral part of the IShell environment. The user can directly describe and execute pipelined command sequences using gestures. The user is constantly guided by visual cues.
Boolean Feature Discovery in Empirical Learning
Authors: Giulia Pagallo, David Haussler
Venue: Machine Learning (1990)

We investigate the problem of learning Boolean functions with a short DNF representation using decision trees as a concept description language. Unfortunately, Boolean concepts with a short description may not have a small decision tree representation when the tests at the nodes are limited to the primitive attributes. This representational shortcoming may be overcome by using Boolean features at the decision nodes. We present two new methods that adaptively introduce relevant features while learning a decision tree from examples. We show empirically that these methods outperform a standard decision tree algorithm for learning small random DNF functions when the examples are drawn at random from the uniform distribution.
An Upper Bound on Expected Clock Skew in Synchronous Systems
Authors: Steven D. Kugelmass, Kenneth Steiglitz
Venue: IEEE Transactions on Computers (1990)

A statistical model is considered for clock skew in which the propagation delays on every source-to-processor path are sums of independent contributions, and are identically distributed. Upper bounds are derived for expected skew, and its variance, in tree distribution systems with N synchronously clocked processing elements. The results are applied to two special cases of clock distribution. In the first, the metric-free model, the total delay in each buffer stage is Gaussian with a variance independent of stage number. In this case, the upper bound on skew grows as Theta (log N). The second, metric, model, is meant to reflect VLSI constraints. Here, the clock delay in a stage is Gaussian with a variance proportional to wire length, and the distribution tree is an H-tree embedded in the plane. In this case, the upper bound on expected skew is Theta (N/sup 1/4/ (log N)/sup 1/2/).