ppxscal/embedding_network huggingface dataset:
Decomposing Heterogeneous Inter-Entity Relationship Updates
Authors: J. R. Horowitz, A. F. Cardenas
Venue: IEEE Transactions on Knowledge and Data Engineering (1992)

New problems of updating views involving inter-entity relationships or joins are identified, beyond those reported previously in the literature. A general purpose method and a set of algorithms are presented for correctly decomposing multilingual update requests on a network of distributed heterogeneous databases. The method and algorithm also apply to both homogeneous nondistributed and distributed database environments. The method, called prototype views and update rules, applies to individual relationships in an entity relationship (ER) view of the network database and gives a floorplan for update decomposition. The network database view represents a unified conceptual view of all the individual databases in the heterogeneous network (i.e. of the objects shared across the network). The update request is decomposed into a sequence of intermediate control language steps to subsequently guide the particular updates to each of the underlying databases in the network. Individual database updates are performed by each particular database management system (DBMS).
Non-photorealistic volume rendering using stippling techniques
Authors: Aidong Lu, Christopher J. Morris, David S. Ebert, Penny Rheingans, Charles Hansen
Venue: Proceedings of the conference on Visualization '02 (2002)

Simulating hand-drawn illustration techniques can succinctly express information in a manner that is communicative and informative. We present a framework for an interactive direct volume illustration system that simulates traditional stipple drawing. By combining the principles of artistic and scientific illustration, we explore several feature enhancement techniques to create effective, interactive visualizations of scientific and medical datasets. We also introduce a rendering mechanism that generates appropriate point lists at all resolutions during an automatic preprocess, and modifies rendering styles through different combinations of these feature enhancements. The new system is an effective way to interactively preview large, complex volume datasets in a concise, meaningful, and illustrative manner. Volume stippling is effective for many applications and provides a quick and efficient method to investigate volume models.
New Linear Codes with Covering Radius 2 and Odd Basis
Authors: Alexander A. Davydov, Patric R. J. Osterga Rd
Venue: Designs, Codes and Cryptography (1999)

On the way of generalizing recent results by Cock and the second author, it is shown that when the basis q is odd, BCH codes can be lengthened to obtain new codes with covering radius R=2. These constructions (together with a lengthening construction by the first author) give new infinite families of linear covering codes with codimension r=2k+1 (the case q=3, r=4k+1 was considered earlier). New code families with r=4k are also obtained. An updated table of upper bounds on the length function for linear codes with r\leq 24, R=2, and q=3,5 is given.
Secure Code Distribution
Authors: X. Nick Zhang
Venue: Computer (1997)

The Java Virtual Machine does not offer a way for code obtained from trusted sources to be granted extra rights. This article describes two approaches to authentification for code distribution: One extends the JVM to include a digital signature in applets; the other uses MIME encapsulation to take advantage of available security infrastructures. The signed-applet approach gives a programmer more flexibility because it addresses the security issues at a more fundamental level. However, signed-applet security mechanisms may vary for different code distribution schemes, making integration difficult. The MIME-based approach provides a unified security interface. It is more efficient in the sense that all classes can be encapsulated in one multipart attachment, and a single signature or verification operation will cover all classes. The approaches can also be combined and tailored to satisfy various requirements. Ultimately, operating systems must support the concept of a secure compartment so that separate resource management policies can be implemented for the secure compartment and the rest of the system.
Speculative synchronization: applying thread-level speculation to explicitly parallel applications
Authors: José F. Martínez, Josep Torrellas
Venue: ACM SIGOPS Operating Systems Review (2002)

Barriers, locks, and flags are synchronizing operations widely used programmers and parallelizing compilers to produce race-free parallel programs. Often times, these operations are placed suboptimally, either because of conservative assumptions about the program, or merely for code simplicity.We propose Speculative Synchronization, which applies the philosophy behind Thread-Level Speculation (TLS) to explicitly parallel applications. Speculative threads execute past active barriers, busy locks, and unset flags instead of waiting. The proposed hardware checks for conflicting accesses and, if a violation is detected, offending speculative thread is rolled back to the synchronization point and restarted on the fly. TLS's principle of always keeping a safe thread is key to our proposal: in any speculative barrier, lock, or flag, the existence of one or more safe threads at all times guarantees forward progress, even in the presence of access conflicts or speculative buffer overflow. Our proposal requires simple hardware and no programming effort. Furthermore, it can coexist with conventional synchronization at run time.We use simulations to evaluate 5 compiler- and hand-parallelized applications. Our results show a reduction in the time lost to synchronization of 34% on average, and a reduction in overall program execution time of 7.4% on average.
The Influence of Evolutionary Selection Schemes on the Iterated Prisoner's Dilemma
Authors: David Van Bragt, Cees Van Kemenade, Han La Poutré
Venue: Computational Economics (2001)

Many economic and social systems are essentially large multi-agent systems. By means of computational modeling, the complicated behavior of such systems can be investigated. Modeling a multi-agent system as an evolutionary agent system, several important choices have to be made for evolutionary operators. Especially, it is to be expected that evolutionary dynamics substantially depend on the selection scheme. We therefore investigate the influence of evolutionary selection mechanisms on a fundamental problem: the iterated prisoner's dilemma (IPD), an elegant model for the emergence of cooperation in a multi-agent system. We observe various types of behavior, cooperation level, and stability, depending on the selection mechanism and the selection intensity. Hence, our results are important for (1) the proper choice and application of selection schemes when modeling real economic situations and (2) assessing the validity of the conclusions drawn from computer experiments with these models. We also conclude that the role of selection in the evolution of multi-agent systems should be investigated further, for instance using more detailed and complex agent interaction models.
Modelling finite geometries on surfaces
Authors: Arthur T. White
Venue: Discrete Mathematics (2002)

The usual model of the Fano plane has several deficiencies, all of which are remedied by imbedding the complete graph K7 on the torus. This idea is generalized, in two directions: (1) Let q be a prime power. Efficient topological models are described for each PG(2,q), and a study is begun for AG(2,q). (2) A 3-configuration is a geometry satisfying: (i) each line is on exactly 3 points; (ii) each point is on exactly r lines, where r is a fixed positive integer; (iii) two points are on at most one line. Surface models are found for 3-configurations of low order, including those of Pappus and Desargues. Special attention is paid to AG(2,3). A study is begun of partial geometries which are also 3-configurations, and four general constructions are given.
Design and evaluation of compiler algorithms for pre-execution
Authors: Dongkeun Kim, Donald Yeung
Venue: ACM SIGPLAN Notices (2002)

Pre-execution is a promising latency tolerance technique that uses one or more helper threads running in spare hardware contexts ahead of the main computation to trigger long-latency memory operations early, hence absorbing their latency on behalf of the main computation. This paper investigates a source-to-source C compiler for extracting pre-execution thread code automatically, thus relieving the programmer or hardware from this onerous task. At the heart of our compiler are three algorithms. First, program slicing removes non-critical code for computing cache-missing memory references, reducing pre-execution overhead. Second, prefetch conversion replaces blocking memory references with non-blocking prefetch instructions to minimize pre-execution thread stalls. Finally, threading scheme selection chooses the best scheme for initiating pre-execution threads, speculatively parallelizing loops to generate thread-level parallelism when necessary for latency tolerance. We prototyped our algorithms using the Stanford University Intermediate Format (SUIF) framework and a publicly available program slicer, called Unravel [13], and we evaluated our compiler on a detailed architectural simulator of an SMT processor. Our results show compiler-based pre-execution improves the performance of 9 out of 13 applications, reducing execution time by 22.7%. Across all 13 applications, our technique delivers an average speedup of 17.0%. These performance gains are achieved fully automatically on conventional SMT hardware, with only minimal modifications to support pre-execution threads.
CMOS Differential and Absolute Thermal Sensors
Authors: Ashish Syal, Victor Lee, André Ivanov, Josep Altet
Venue: Journal of Electronic Testing: Theory and Applications (2002)

This paper treats the test of CMOS digital ICs by using the thermal mapping of the silicon surface as a test observable. Two different temperature-sensing strategies are presented. The novel sensors developed are an on-chip CMOS Differential Temperature (DT) sensor and a Proportional to Absolute Temperature (PTAT) sensor. The sensors have been implemented in a standard .18 &mu;m CMOS technology.
On the Exact Analysis of a Discrete-Time Queueing System with Autoregressive Inputs
Authors: Gang Uk Hwang, Khosrow Sohraby
Venue: Queueing Systems: Theory and Applications (2003)

In this paper, we provide an exact analysis of a discrete-time queueing system driven by a discrete autoregressive model of order 1 (DAR(1)) characterized by an arbitrary marginal batch size distribution and a correlation coefficient. Closed-form expressions for the probability generating function and mean queue length are derived. It is shown that the system performance is quite sensitive to the correlation of the arrival process. In addition, a comparison with traditional Markovian processes shows that arrival processes of DAR(1) type exhibit larger queue length as compared with the traditional Markovian processes when the marginal densities and correlation coefficients are matched.
Image Processing by Neural Networks
Authors: Marc Duranton
Venue: IEEE Micro (1996)

To fulfill the computing power required by real-time and embedded applications of image processing such as pattern recognition, shape analysis (using classical or less classical methods such as Neural-Networks), LEP has developed the fully programmable vectorial processor L- Neuro 2.3 which is composed of an array of 12 DSPs (Digital Signal Processors). This chip was designed to reduce the cost at the system level, without scarifying performances in real-time image processing (sorting objects by vision, image analysis), digital signal processing (such as digital transversal filtering - 12 taps filter with 16-bit inputs at 60 MHz, 1-D and 2-D digital convolution and correlation, template matching, Fourier transforms and so on), neurocomputing, fuzzy logics applications and all applications that can take advantage of cooperating DSP. The now available chip is able to perform up to 2 Giga arithmetic operations per second, and has a peak transfer throughput of 2 Gbytes per second.
State-dependent M/G/1 type queueing analysis for congestion control in data networks
Authors: Eitan Altman, Kostya Avrachenkov, Chadi Barakat
Venue: Computer Networks: The International Journal of Computer and Telecommunications Networking (2002)

We study a linear-increase multiplicative-decrease flow control mechanism. We consider congestion signals that arrive in batches according to a Poisson process. We focus on the case when the transmission rate cannot exceed a certain maximum value. The distribution of the transmission rate in steady state as well as its moments are determined. Our model is particularly useful to study the behavior of TCP (Transmission Control Protocol) the congestion control mechanism in the Internet. Burstiness of packet losses is captured by allowing congestion signals to arrive in batches. By a simple transformation, the problem can be reformulated in terms of an equivalent M/G/1 queue, where the transmission rate in the original model corresponds to the workload in the 'dual' queue. The service times in the queueing model are not i.i.d., and they depend on the workload in the system.
Multiagent Interaction Models for Constructing the Needs-and-Means Networks in Open Systems
Authors: V. A. Vittikh, P. O. Skobelev
Venue: Automation and Remote Control (2003)

Multiagent models for constructing the needs-and-means networks in open systems were presented together with an example of using them in transport logistics.
Hardware-Software Codesign of Embedded Systems
Authors: Massimilano Chiodo, Paolo Giusto, Attila Jurecska, Harry C. Hsieh, Alberto Sangiovanni-Vincentelli, Luciano Lavagno
Venue: IEEE Micro (1994)

Designers generally implement embedded controllers for reactive real-time applications as mixed software-hardware systems. In our formal methodology for specifying, modeling, automatically synthesizing, and verifying such systems, design takes place within a unified framework that prejudices neither hardware nor software implementation. After interactive partitioning, this approach automatically synthesizes the entire design, including hardware-software interfaces. Maintaining a finite-state machine model throughout, it preserves the formal properties of the design. It also allows verification of both specification and implementation, as well as the use of specification refinement through formal verification.
ZYX-A Multimedia Document Model for Reuse and Adaptation of Multimedia Content
Authors: Susanne Boll, Wolfgang Klas
Venue: IEEE Transactions on Knowledge and Data Engineering (2001)

Advanced multimedia applications require adequate support for the modeling of multimedia content by multimedia document models. More and more this support calls for not only the adequate modeling of the temporal and spatial course of a multimedia presentation and its interactions, but also for the partial reuse of multimedia documents and adaptation to a given user context. However, our thorough investigation of existing standards for multimedia document models such as HTML, MHEG, SMIL, and HyTime leads to us the conclusion that these standard models do not provide sufficient modeling support for reuse and adaptation. Therefore, we propose a new approach for the modeling of adaptable and reusable multimedia content, the ZYX model. The model offers primitives that provide¿beyond the more or less common primitives for temporal, spatial, and interaction modeling¿a variform support for reuse of structure and layout of document fragments and for the adaptation of the content and its presentation to the user context. We present the model in detail and illustrate the application and effectiveness of these concepts by samples taken from our Cardio-OP application in the domain of cardiac surgery. With the ZYX model, we developed a comprehensive means for advanced multimedia content creation: support for template-driven authoring of multimedia content and support for flexible, dynamic composition of multimedia documents customized to the user's local context and needs. The approach significantly impacts and supports the authoring process in terms of methodology and economic aspects.
Matisse: An Architectural Design Tool for Commodity ICs
Authors: Kayhan Küçükçakar, Chih-Tung Chen, Jie Gong, Wim Philipsen, Thomas E. Tkacik
Venue: IEEE Design Test (1998)

As today's market conditions require design organizations to create products in shorter time, there is also a significant change in the product mix due to fast growing markets such as wireless, automotive, multimedia and network applications. The nature of the current market conditions forces design organizations to move into product areas in which they don't have past experience and to design products with higher complexity, lower power, higher performance, better reusability, and lower cost in shorter turn-around time. It is accepted that the traditional RTL design methodologies cannot sustain the needed productivity increase.Behavioral synthesis offers a methodology which promises significant productivity increase by raising the abstraction level of digital design. Behavioral synthesis is a process of mapping an algorithmic description of a computation into a Register-Transfer Level (RTL) implementation. This methodology includes creating an algorithmic behavior, scheduling, allocating resources, sharing resources, creating interconnect, mapping of the algorithmic behavior to structure (binding), and generating finite-state-machine (FSM). During scheduling the cycle-by-cycle execution of each algorithmic statement is decided. The numbers and types of functional units and registers are decided during resource allocation. Multiplexers, tristate drivers, and wires are created to route the values in the data path from their sources to their destinations during the interconnect creation. Finally, an FSM is generated to control data-path elements and the interconnect according to the schedule and bindings.
Controllability of Right-Invariant Systems on Solvable Lie Groups
Authors: Yu. L. Sachkov
Venue: Journal of Dynamical and Control Systems (1997)

We study controllability of right-invariant control systems \Gamma = A+{\Bbb R}B on Lie groups. Necessary and sufficient controllability conditions for Lie groups not coinciding with their derived subgroup are obtained in terms of the root decomposition corresponding to the adjoint operator ad B. As an application, right-invariant systems on metabelian groups and matrix groups, and bilinear systems are considered.
A Knowledge-Based Control Architecture with Interactive Reasoning Functions
Authors: Gerald A. Sullivan
Venue: IEEE Transactions on Knowledge and Data Engineering (1996)

A knowledge-based system architecture called IPEX is presented that uses a time distributed, interactive reasoning paradigm for process control applications. Structural features of the system are presented, and it is shown that temporal considerations are included in each of the system's data structures either explicitly or implicitly. Diagnostic planning is discussed, and explanations of the algorithms that formulate and maintain diagnostic/control plans are given. In particular, it is shown that the IPEX system can manage concurrently executing interactive diagnostic plans for multiple problem hypotheses.
Assertion-based verification turns the corner
Authors: Aarti Gupta
Venue: IEEE Design Test (2002)

The "formal verification method: Getting around the Brick Wall" panel at the 2002Design Automation Conference highlighted the industrial emergence of assertion-based verification and the need to go beyond current methods. Moderator David Dill initiated a discussion on the three brick walls to formal verifcation methods: handling high computational complexity, formulating properties to check, and characterizing the set of legal inputs to the design underverification. The panelists addressed moving to higher abstraction levels and assertion-based.verification as two strategies to solve these problems.
Properties of the Miss Ratio for a 2-Level Storage Model with LRU or FIFO Replacement Strategy and Independent References
Authors: J. van den Berg, D. Toswley
Venue: IEEE Transactions on Computers (1993)

The behavior of a two-level storage system operating with the least recently used (LRU) or the first-in, first-out (FIFO) replacement strategy, where accesses to the main storage are described by the independent reference model (IRM), is discussed. Let the size of main storage be m. It is proved that the miss ratio (i.e., the steady-state probability that the item currently required is not in main storage) exhibits the following properties: the miss ratio is a convex function of m under LRU, the function (1-miss ratio)/m is nonincreasing in m under FIFO, and the miss ratio is a Schur-convex function of the reference probabilities under FIFO.
Bilateral Trade and `Small-World' Networks
Authors: Allen Wilhite
Venue: Computational Economics (2001)

Trade requires search, negotiation, and exchange, which are activities that absorb resources. This paper investigates how different trade networks attend to these activities. An artificial market is constructed in which autonomous agents endowed with a stock of goods seek out partners, negotiate a price, and then trade with the agent offering the best deal. Different trade networks are imposed on the system by restricting the set of individuals with whom an agent can communicate. We then compare the path to the eventual equilibrium as well as the equilibrium characteristics of each trade network to see how each system dealt with the tasks of search, negotiation, and exchange. Initially, all agents are free to trade with any individual in the global market. In such a world, global resources are optimally allocated with few trades, but only after a tremendous amount of search and negotiation. If trade is restricted within disjoint local boundaries, search is simple but global efficiency elusive. However, a hybrid model in which most agents trade locally but a few agents trade globally results in an economy that quickly reaches a Pareto optimal equilibrium with significantly lower search and negotiation costs. Such `small-world' networks occur in nature and may help explain the ease with which most of us acquire goods from around the world. We also show that there are private incentives for such a system to arise.
Approximating Probabilistic Inference in Bayesian Belief Networks
Authors: P. Dagum, R. M. Chavez
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1993)

A belief network comprises a graphical representation of dependencies between variables of a domain and a set of conditional probabilities associated with each dependency. Unless rho =NP, an efficient, exact algorithm does not exist to compute probabilistic inference in belief networks. Stochastic simulation methods, which often improve run times, provide an alternative to exact inference algorithms. Such a stochastic simulation algorithm, D-BNRAS, which is a randomized approximation scheme is presented. To analyze the run time, belief networks are parameterized, by the dependence value D/sub xi /, which is a measure of the cumulative strengths of the belief network dependencies given background evidence xi . This parameterization defines the class of f-dependence networks. The run time of D-BNRAS is polynomial when f is a polynomial function. Thus, the results prove the existence of a class of belief networks for which inference approximation is polynomial and, hence, provably faster than any exact algorithm.