ppxscal/embedding_network huggingface dataset:
Online Current Testing
Authors: Jien-Chung Lo
Venue: IEEE Design Test (1998)

As we approaching the deep-submicron era, the ever-increasing level of integration has begun to bring much attention to the product reliability. Besides the traditional critical, highly reliable and high safety missions, online VLSI testing will soon be needed in other fault-tolerant applications such as highly available, high maintainability and highly failure resilient missions. New on-ine testing methods must be used to provide cost efficiency in these not-so-critical applications. Analogous to the offline testing, we may examine either the voltage output or the current usage during online testing to determine the vitality of the circuit. Online current testing can be used with the traditional online (function) testing methods or can be used independently. Since there is a wide spectrum of fault tolerant missions and goals, the use of online current testing plus traditional methods will help fill the gaps.When using only the current monitoring online, we have an option to reuse the existing on-chip current sensors for online testing. These sensors are an integral part of the circuit and have been placed to aid in production tests. Consequently, such a method needs no extra hardware and no extra designing effort. In other words, an IC chip equipped with built-in current sensors already has online testing potential.
Analyzing Safety Requirements for Process-Control Systems
Authors: Rogério de Lemos, Amer Saeed, Tom Anderson
Venue: IEEE Software (1995)

An alarming trend is appearing in the development of safety-critical systems: Demands for dependability are rising faster than what can currently be achieved, especially for complex systems. For these systems, the software's functional criticality is increasing in tandem with its complexity, posing a major challenge for software developers.1 As the trend continues, researchers are looking more closely at the requirements phase as the solution for managing errors. Experience shows that mistakes made during this phase can easily introduce faults that lead to accidents, so preventing faults during this phase should produce more dependable systems. However, in safety-critical systems, you cannot assess the adequacy of software safety requirements except with respect to overall system risk. This means that you must also conduct a safety analysis of the resulting safety specifications to ensure that the software's contribution to system risk is acceptable. Safety-requirements analysis is typically conducted either ad hoc or with the unbridled use of formal methods. At the University of Newcastle upon Tyne, we have investigated these issues and have developed an approach that comprises safety-enhancing methods and techniques for identifying safety requirements and analyzing them. The methods and techniques are targeted to safety-critical process-control systems, which include domains such as power generation, aerospace, and transportation. Our approach provides for a systematic analysis of system requirements to determine mission and safety requirements, an analysis of safety requirements, the recording of safety specifications, and a safety analysis of safety specifications. This approach offers the freedom to mix formal and traditional engineering methods and apply them at different abstraction levels to give a higher assurance that the software's contribution to system risk is acceptable. We have demonstrated the feasibility of our approach by applying it to a chemical batch-processing plant. We believe our approach increases the visibility of the requirements process by partitioning the analysis into distinct phases that are based on the domains of analysis established from the system structure. Freedom to tailor a technique to a specific domain of analysis and perspective ensures that the most appropriate techniques are applied. Formally recording the safety specifications helps in building and comparing safety strategies. Finally, using both qualitative and quantitative techniques gives a precise picture of the specification's contribution to overall system risk.
Overlay High-Density Interconnect: A Chips-First Multichip Module Technology
Authors: Wolfgan Daum, William E. Burdick,  Jr., Raymond A. Fillion
Venue: Computer (1993)

A high-density interconnection (HDI) technology that involves placing bare chips into cavities on a base substrate and fabricating the thin-film interconnect structure on top of the components is described. The interconnects to the chip I/O pads are formed as part of the thin-film fabrication process, thus eliminating the need for wire bonds, tape-automated bonds (TABs), or solder bumps. The need for advanced packaging and interconnection and the standard chips-last multichip module (MCM) technologies are reviewed. The HDI chips-first MCM technology's IC pretest requirements and approaches, substrate and packaged parts test, and substrate packaging are discussed.
FLUVSIM: a program for object-based stochastic modeling of fluvial depositional systems
Authors: C. V. Deutsch, T. T. Tran
Venue: Computers Geosciences (2002)

This paper presents a FORTRAN program for hierarchical object-based modeling of complex fluvial facies. Unique features of this program include (1) a simple approach to place channel, levee, and crevasse sands within a matrix of floodplain shales, (2) templates for fast rastering of fluvial facies objects, leading to fast CPU times, and (3) the use of simulated annealing and non-random perturbation rules for conditioning to extensive soft facies-proportion data and local well data. Object-based modeling techniques are widely applicable to modeling fluvial depositional systems. Public domain software for such modeling is rare and inflexible with respect to the variety of conditioning data that can be handled. Commercial software is costly and also of limited flexibility. The fluvsim program overcomes many of these limitations with an accessible research code.
Implementing Fuzzy Rule-Based Systems on Silicon Chips
Authors: Meng-Hiot Lim, Toshiyasu Takefuji
Venue: IEEE Expert: Intelligent Systems and Their Applications (1990)

The authors address the implementation of a fuzzy simulator (FSIM) and discuss architectures for a general-purpose VLSI fuzzy-inference processor. The FSIM tool aids in the rapid prototyping of fuzzy production system (FPS), and represents a convenient transitional step in the implementation of an FPS on silicon. They present a brief theoretical review of fuzzy reasoning, introduce the FSIM, and discuss FPS development using the FSIM. An overall picture of the various stages involved in developing a fuzzy-inference processor is provided. The authors then outline the general architecture of a VLSI inference processor for FPSs. To further illustrate the development of a fuzzy inference processor, they describe an FPS example from conceptualization to implementation on silicon chips.
Krein parameters and antipodal tight graphs with diameter 3 and 4
Authors: Aleksandar Jurisić, Jack Koolen
Venue: Discrete Mathematics (2002)

We determine which Krein parameters of nonbipartite antipodal distance-regular graphs of diameter 3 and 4 can vanish, and give combinatorial interpretations of their vanishing. We also study tight distance-regular graphs of diameter 3 and 4. In the case of diameter 3, tight graphs are precisely the Taylor graphs. In the case of antipodal distance-regular graphs of diameter 4, tight graphs are precisely the graphs for which the Krein parameter q114 vanishes.
Local Surface Shape Estimation of 3-D Textured Surfaces using Gaussian Markov Random Fields and Stereo Windows
Authors: M. A. S. Patel, F. S. Cohen
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1993)

The problem of extracting the local shape information of a 3-D texture surface from a single 2-D image by tracking the perceived systematic deformations the texture undergoes by virtue of being present on a 3-D surface and by virtue of being imaged is examined. The surfaces of interest are planar and developable surfaces. The textured objects are viewed as originating by laying a rubber planar sheet with a homogeneous parent texture on it onto the objects. The homogeneous planar parent texture is modeled by a stationary Gaussian Markov random field (GMRF). A probability distribution function for the texture data obtained by projecting the planar parent texture under a linear camera model is derived, which is an explicit function of the parent GMRF parameters, the surface shape parameters. and the camera geometry. The surface shape parameter estimation is posed as a maximum likelihood estimation problem. A stereo-windows concept is introduced to obtain a unique and consistent parent texture from the image data that, under appropriate transformations, yields the observed texture in the image. The theory is substantiated by experiments on synthesized as well as real images of textured surfaces.
Navigational Accesses in a Temporal Object Model
Authors: Elisa Bertino, Elena Ferrari, Giovanna Guerrini
Venue: IEEE Transactions on Knowledge and Data Engineering (1998)

A considerable research effort has been devoted in past years to query languages for temporal data in the context of both the relational and the object-oriented model. Object-oriented databases provide a navigational approach for data access based on object references. In this paper, we investigate the navigational approach to querying object-oriented databases. We formally define the notion of temporal path expression, and we address on a formal basis issues related to the correctness of such expressions. In particular, we focus on static analysis and give a set of conditions ensuring that an expression always results in a correct access at runtime.
Achieving Fault-Tolerant Software with Rejuvenation and Reconfiguration
Authors: William Yurcik, David Doss
Venue: IEEE Software (2001)

The authors present two complementary ways to deal with soft-ware aging. Their approach pro-actively reinitializes software to a known operating state, before failure occurs, or reactively reconfigures soft-ware after a failure such that service remains operational.
Parallel Self-Index Integer Sorting
Authors: Hazem M. Bahig, Sameh S. Daoud, Mahmoud K. A. Khairat
Venue: The Journal of Supercomputing (2002)

We consider the problem of sorting n integers when the elements are drawn from the restricted domain [1&hellip;n]. A new deterministic parallel algorithm for sorting n integers is obtained. Its running time is O(lognlog(n/logn)) using n/logn processors on EREW (exclusive read exclusive write) PRAM (parallel random access machine). Also, our algorithm was modified to become optimal when we use \sqrt{n} processors. This algorithm belongs to class EP (Efficient, Polynomial fast).
Parallel Computation in Biological Sequence Analysis
Authors: Tieng K. Yap, Ophir Frieder, Robert L. Martino
Venue: IEEE Transactions on Parallel and Distributed Systems (1998)

A massive volume of biological sequence data is available in over 36 different databases worldwide, including the sequence data generated by the Human Genome project. These databases, which also contain biological and bibliographical information, are growing at an exponential rate. Consequently, the computational demands needed to explore and analyze the data contained in these databases is quickly becoming a great concern. To meet these demands, we must use high performance computing systems, such as parallel computers and distributed networks of workstations. We present two parallel computational methods for analyzing these biological sequences. The first method is used to retrieve sequences that are homologous to a query sequence. The biological information associated with the homologous sequences found in the database may provide important clues to the structure and function of the query sequence. The second method, which helps in the prediction of the function, structure, and evolutionary history of biological sequences, is used to align a number of homologous sequences with each other. These two parallel computational methods were implemented and evaluated on an Intel iPSC/860 parallel computer. The resulting performance demonstrates that parallel computational methods can significantly reduce the computational time needed to analyze the sequences contained in large databases.
Hardware-Software Interactions on Mpact
Authors: Paul Kalapathy
Venue: IEEE Micro (1997)

The Mpact-1 media processor is a member of a new class of processor architectures that accelerates a number of multimedia functions concurrently through a combination of hardware and software. Both the unique hardware architecture and software approach contribute to this ability to accelerate multimedia functions.
Distributed Optimistic Concurrency Control Methods for High-Performance Transaction Processing
Authors: Alexander Thomasian
Venue: IEEE Transactions on Knowledge and Data Engineering (1998)

There is an ever-increasing demand for more complex transactions and higher throughputs in transaction processing systems leading to higher degrees of transaction concurrency and, hence, higher data contention. The conventional two-phase locking (2PL) Concurrency Control (CC) method may, therefore, restrict system throughput to levels inconsistent with the available processing capacity. This is especially a concern in shared-nothing or data-partitioned systems due to the extra latencies for internode communication and a reliable commit protocol. The optimistic CC (OCC) is a possible solution, but currently proposed methods have the disadvantage of repeated transaction restarts. We present a distributed OCC method followed by locking, such that locking is an integral part of distributed validation and two-phase commit. This method ensures at most one re-execution, if the validation for the optimistic phase fails. Deadlocks, which are possible with 2PL, are prevented by preclaiming locks for the second execution phase. This is done in the same order at all nodes. We outline implementation details and compare the performance of the new OCC method with distributed 2PL through a detailed simulation that incorporates queueing effects at the devices of the computer systems, buffer management, concurrency control, and commit processing. It is shown that for higher data contention levels, the hybrid OCC method allows a much higher maximum transaction throughput than distributed 2PL in systems with high processing capacities. In addition to the comparison of CC methods, the simulation study is used to study the effect of varying the number of computer systems with a fixed total processing capacity and the effect of locality of access in each case. We also describe several interesting variants of the proposed OCC method, including methods for handling access variance, i.e., when rerunning a transaction results in accesses to a different set of objects.
Have We Witnessed a Real-Life Turing Test?
Authors: Marina Krol
Venue: Computer (1999)

IBM's announcement of its intention to "retire" the Deep Blue computer from chess revived the interest of both the mass media and the general public in the chess match between World Champion Gary Kasparov and Deep Blue. In a sense, by refusing a rematch with Kasparov or a new match with another grand master, IBM closes a chapter in the history of artificial intelligence. AI researchers had long investigated building a machine that could defeat a world-class chess champion, and now one had. But what did this mean? Did Deep Blue ace the Turing Test? Did it do much more? It seems that the IBM creation not only beat the reigning world champion but also took a large step, in some people's eyes, toward true artificial intelligence.
REDI: an efficient fault oriented procedure to identify redundant faults in combinational logic circuits
Authors: Chen Wang, Irith Pomeranz, Sudhakar M. Reddy
Venue: Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design (2001)

In this work, a new and effective procedure, called REDI, to efficiently identify redundant single stuck-at faults in combinational logic circuits is proposed. The method is fault oriented and uses sensitizability of partial paths to determine redundant faults. It uses only implications and hence may not determine all the redundant faults of a circuit. However, experimental results presented on benchmark circuits show that the procedure identifies nearly all the redundant faults in most of the benchmark circuits. The key features of REDI that make it efficient are: partial path sensitization, blockage learning, dynamic branch ordering and fault grouping. Experimental results on benchmark circuits demonstrate the efficiency of the proposed procedure in identifying redundant faults in combinational logic circuits.
Concurrent-Development Process Model
Authors: Mikio Aoyama
Venue: IEEE Software (1993)

The lessons learned in managing a model that lets a user develop multiple functions concurrently over the entire development process, from requirements specification to system test are reviewed. The structure and dynamic behavior of a concurrent development process are discussed. The process management, project management, product management, organization management, and software-engineering environment elements of the concurrent development model are all described, although the focus is on process management. The concurrent development process is compared to sequential development, lean production, software factory, and capability maturity model processes.
Barrier Trees on Poset-Valued Landscapes
Authors: Peter F. Stadler, Christoph Flamm
Venue: Genetic Programming and Evolvable Machines (2003)

Fitness landscapes have proved to be a valuable concept in evolutionary biology, combinatorial optimization, and the physics of disordered systems. Usually, a fitness landscape is considered as a mapping from a configuration space equipped with some notion of adjacency, nearness, distance, or accessibility, into the real numbers. In the context of multi-objective optimization problems this concept can be extended to poset-valued landscapes. In a geometric analysis of such a structure, local Pareto points take on the role of local minima. We show that the notion of saddle points, barriers, and basins can be extended to the poset-valued case in a meaningful way and describe an algorithm that efficiently extracts these features from an exhaustive enumeration of a given generalized landscape.
Copy Protection Technology is Doomed
Authors: Dan S. Wallach
Venue: Computer (2001)

Despite how easy copying has always been, vendors continue selling content and people continue to buy it, even when they can get that content illegally. When records and, later, radio were introduced, artists and record companies feared it was the end of their world. It wasn't. When VCRs were introduced, they didn't destroy movie theaters¿they led to creation of the video rental business. History tells us that the ease of digitally copying music, video, and any other media won't destroy the copyright holders.Now, with the ubiquity of CD burners, technology has again advanced, making audio CDs trivial to copy, bit for bit. The record companies could potentially address this situation by creating some fundamental advance in how music is delivered to consumers. Instead, technology companies are offering the record companies a wide variety of snake-oil schemes to help them maintain their previous business models. These schemes can be defeated¿doing so only requires that somebody study how they work.The only way to prevent teenage girls from freely sharing boy-band MP3s will be to provide a service that's reasonably priced and irresistibly better than free file sharing. Any other technology, business model, or legal framework is simply doomed.
Parallel Implementation of the Schur Berlekamp-Massey Algorithm on a Linearly Connected Processor Array
Authors: Christopher J. Zarowski
Venue: IEEE Transactions on Computers (1995)

The Berlekamp-Massey algorithm (BMA) is important in the decoding of Reed-Solomon (RS), and more generally, Bose-Chaudhuri-Hocquenghem (BCH) block error-control codes. For a t-error correcting code the BMA has time complexity O(t2) when implemented on a sequential computer. However, the BMA does not run efficiently on a parallel computer. The BMA can be mapped into the Schur BMA. This paper presents the implementation of the BMA and Schur BMA together on a linearly connected array of 2t processors. The resulting machine computes the error-locator polynomial with a time complexity of O(t).
A Behavioral Fault Simulator for Ideal
Authors: Ajay Khoche, S. D. Sherlekar, G. Venkatesh, R. Venkateswaran
Venue: IEEE Design Test (1992)

A method of performing fault simulation at the behavioral level by propagating faults through behavioral hardware descriptions is presented. The method is accurate because it uses fault models only at the gate level. Since it does not duplicate computations at the behavioral level for each fault, it is, on the average, faster than existing methods. Examples in the Ideal hardware description language are used to discuss the basis for a fast behavioral fault simulator.
A Distributed Prolog System with And Parallelism
Authors: Mike Carlton, Peter Van Roy
Venue: IEEE Software (1988)

Design details and benchmark results are given for a Prolog interpreter that can be executed across a network by using message passing to implement AND-parallelism. The system is simple and easy to use, yet significantly speeds up existing programs. The system hardware is a group of Sun 3/50 workstations connected to a 10-Mb/s Ethernet. The number of machines actually used by the system is determined when it is initialized. The benchmark programs to test the system are a Prolog compiler, a recursive Fibonacci program, an implementation of the standard quicksort algorithm, and a simple chess program.
Can Internet-Based Applications Be Engineered?
Authors: Roger S. Pressman, Ted Lewis, Ben Adida, Ellen Ullman, Tom DeMarco, Thomas Gilb, Brent Gorda, Watts Humphrey, Ray Johnson
Venue: IEEE Software (1998)

Do the old tried and true principles of software engineering make any sense on the completely new playing field of the Internet? See what nine software leaders have to say.
Eliminating Memory for Fragmentation Within Partitionable SIMD/SPMD Machines
Authors: M. A. Nichols, H. J. Siegel, H. G. Dietz, R. W. Quong, W. G. Nation
Venue: IEEE Transactions on Parallel and Distributed Systems (1991)

Efficient data layout is an important aspect of the compilation process. A model for the creation of perfect memory maps for large-scale parallel machines capable ofuser-controlled partitionable single-instruction-multiple data/single-program-multiple data (SIMD/SPMD) operation is developed. The term perfect implies that no memory fragmentation occurs and ensures that the memory map size is kept to a minimum. A major constraint on solving this problem is based on the single program nature of both the SIMD and SPMD modes of parallelism. It is assumed that all processors within the same submachine used identical addresses to access corresponding data items in each of their local memories. Necessary and sufficient conditions are derived for being able to create perfect memory maps, and results are applied to several partitionable interconnection networks.