ppxscal/embedding_network huggingface dataset:
Graphs satisfying inequality &#x03B8;(G2)≤θ(G)
Authors: Ilwon Kang, Suh-Ryung Kim, Yangmi Shin, Yunsun Nam
Venue: Discrete Mathematics (2002)

In this paper, we study the edge clique cover number of squares of graphs. More specifically, we study the inequality θ(G2) ≤ θ(G) where θ(G) is the edge clique cover number of a graph G. We show that any graph G with at most θ(G) vertices satisfies the inequality. Among the graphs with more than θ(G) vertices, we find some graphs violating the inequality and show that dually chordal graphs and power-chordal graphs satisfy the inequality. Especially, we give an exact formula computing θ(T2) for a tree T.
Using Viewpoints to Define Domain Requirements
Authors: Mike Mannion, Barry Keepence, David Harper
Venue: IEEE Software (1998)

Although requirement s reuse has many potential benefits, a lack of accepted methodology for sorting through a domain's myriad requirement specifications makes the task daunting. The authors' VODRD method relies on stakeholder viewpoint s to organize user requirement s . Here, they describe their method and its application in a mission planning system for the European Space Agency.
Analysis of Replication in Distributed Database Systems
Authors: B. Ciciani, D. M. Dias, P. S. Yu
Venue: IEEE Transactions on Knowledge and Data Engineering (1990)

The authors develop an approximate analytical model to study the tradeoffs of replicating data in a distributed database environment. Several concurrency control protocols are considered, including pessimistic, optimistic, and semi-optimistic protocols. The approximate analysis captures the effect of the protocol on hardware resource contention and data contention. The accuracy of the approximation is validated through detailed simulations. It is found that the benefit of replicating data and the optimal number of replicates are sensitive to the concurrency control protocol. Under the optimistic and semi-optimistic protocols, replications can significantly improve response time with an additional MIPS (million instructions per second) requirement to maintain consistency among the replicates. The optimal degree of replication is further affected by the transaction mix (e.g. the fraction of read-only transactions), the communications delay and overhead, the number of distributed sites, and the available MIPS. Sensitivity analyses have been carried out to examine how the optimal degree of replication changes with respect to these factors.
A D&T Roundtable: Power Delivery and Distribution
Venue: IEEE Design Test (2000)

D&T: The motivation behind this roundtable discussion is to educate the readers of IEEE Design & Test Magazine...some industry...area with respect to what are the challenges that we are going to be facing with respect to power delivery and distribution? And what are the power supply noise management strategies that we need to adopt as microprocessors and high-end DSTs ...keep upward stretching. So...here we have microprocessors, DSTs are approaching greater than...in the next couple of generations. And the fundamental challenge that we have in front of us is how do we deliver and distribute about 100 amps at less than one volt for less than fifty dollars? This is the kind of current and voltages that we are looking at two technology generations ahead.Secondly, on-die power density has now become very, very greater than the hot...power density. We have crossed this cross-over point way back in the .6 micron technology base. Unfortunately, the DI by DB noise is only worsening with technology, so it's not scaling at current scale, because the...are improving. The DI by DB is only worsening as technology is scaling. So these are the area challenges ahead of us, and there is some data to show what's happening as technology scales. With technology scaling, we are going from one architecture to another; one micro architecture to another with a new technology. And the DI by DB's only increasing. We are not seeing that scaling down. That means as the architecture evolves, micro architecture from one generation to another, they're only seeing the DI by DB noise worsen. It's not improving. So something is happening in the architecture that's making the DI by DB go up.
A domain-independent system for sketch recognition
Authors: Bo Yu, Shijie Cai
Venue: Proceedings of the 1st international conference on Computer graphics and interactive techniques in Australasia and South East Asia (2003)

Freehand sketching is a natural and powerful means of interpersonal communication. But to date, it still cannot be supported effectively by human-computer interface. In this paper, we describe a domain-independent system for sketch recognition. Our system allows users to draw sketches as naturally as how they do on paper, and it recognizes the drawing through imprecise stroke approximation which is implemented in a unified and incremental procedure. This method can handle smooth curves and hybrid shapes as gracefully as it does to polylines. With a feature-area verification mechanism and the intelligent adjustment in the post-process, the system can produce user-intended results. Moreover, the output is organized in a hierarchical structure which includes syntactic and semantic information as well as raw data. Our system mainly utilizes low-level geometric features and does not rely on any domain-specific knowledge. Therefore, it will serve as a general and solid foundation for future high-level applications.
Comments on "Theory and Applications of Cellular Automata in Cryptography"
Authors: S. r. Blackburn, S. Murphy, K. g. Paterson
Venue: IEEE Transactions on Computers (1997)

The cipher systems based on Cellular Automata proposed by Nandi et al. [3] are affine and are insecure.
Folded-crossed hypercube: a complete interconnection network
Authors: Yan-Qing Zhang
Venue: Journal of Systems Architecture: the EUROMICRO Journal (2002)

In this paper, the complete folded-crossed hypercube FCQn is proposed based on the folded hypercube [IEEE Trans. Parall. Distrib. Syst. 2(1) (1991) 31], the enhanced hypercube [IEEE Trans. Comput. 40 (3) (1991) 284] and the crossed hypercube CQn [IEEE Trans. Parall. Distrib. Syst. 3 (5) (1992) 513]. FCQn has such appealing properties as diameter of [n/2], degree of n + 1, much short mean internode distance about 75-62.5% of that of n-cube for n ≥ 6, and very low message traffic density only about 0.667-0.625 for n ≥ 4. Therefore, FCQn is a high-performance-low-cost architecture. Additionally, a general formula of mean internode distance of the complete hypercube-type architecture is given in order to analyze different hypercube-type architectures easily.
A Parallel, Scalable, Microprocessor-Based Database Computer for Performance Gains and Capacity Growth
Authors: David Hsiao
Venue: IEEE Micro (1991)

A multiback-end database supercomputer, or MDBS, that embodies the architecture and performance of an experimental database computer and a number of database processors and their corresponding database stores, is discussed. Two studies are described. One focused on the design and architecture of the microprocessor-based MDBS, and the other on the performance and benchmark results for various loads and configurations.
Effective Data Mining Using Neural Networks
Authors: Hongjun Lu, Rudy Setiono, Huan Liu
Venue: IEEE Transactions on Knowledge and Data Engineering (1996)

Classification is one of the data mining problems receiving great attention recently in the database community. This paper presents an approach to discover symbolic classification rules using neural networks. Neural networks have not been thought suited for data mining because how the classifications were made is not explicitly stated as symbolic rules that are suitable for verification or interpretation by humans. With the proposed approach, concise symbolic rules with high accuracy can be extracted from a neural network. The network is first trained to achieve the required accuracy rate. Redundant connections of the network are then removed by a network pruning algorithm. The activation values of the hidden units in the network are analyzed, and classification rules are generated using the result of this analysis. The effectiveness of the proposed approach is clearly demonstrated by the experimental results on a set of standard data mining test problems.
Least Upper Bounds on OBDD Sizes
Authors: M. A. Heap, M. R. Mercer
Venue: IEEE Transactions on Computers (1994)

This paper derives exact equations for the maximum number of nonterminal vertexes in reduced and quasi-reduced ordered binary decision diagrams (OBDD's). A reduced OBDD is reduced by both merging and deleting vertices, and a quasi-reduced OBDD is reduced only by merging. These formulas are used to tighten Lee's original bounds, and to correct the bounds recently reported by H.T. Liaw and C.S. Lin (1992).
Defect Detection from Visual Abnormalities in Manufacturing Process Using IDDQ
Authors: Masaru Sanada
Venue: Journal of Electronic Testing: Theory and Applications (2001)

Abnormal IDDQ (Quiescent VDD supply current) indicates the existence of physical damage in a circuit. Using this phenomenon, a CAD-based fault diagnosis technology has been developed to enhance the manufacturing yield of logic LSI. This method to detect the fatal defect fragments in several abnormalities identified with wafer inspection apparatus includes a way to separate various leakage faults, and to define the diagnosis area encircling the abnormal portions. The proposed technique progressively narrows the faulty area by using logic simulation to extract the logic states of the diagnosis area, and by locating test vectors related to abnormal IDDQ. The fundamental diagnosis way employs the comparative operation of each circuit element to determine whether the same logic state with abnormal IDDQ exists in normal logic state or not.
Synchronizing Hypercube Networks in the Presence of Faults
Authors: M. Harrington, A. K. Somani
Venue: IEEE Transactions on Computers (1994)

Synchronizing distributed networks allows nodes to share resources efficiently, run synchronous programs and vote on redundant results in fault tolerant systems. Due to the low connectivity of hypercube networks, neither the fault tolerant hardware synchronization schemes, phased locked loops nor multistage synchronizers can be used without adding additional links. We describe a new hardware method developed to synchronize hypercube networks. Our analysis shows that the method can sustain one fault if the connectivity of the hypercube, n, is at least three, and it can tolerate up to m/spl ges/2 Byzantine faults as long as the connectivity of the hypercube, n, is greater than max{2m+1,3m-2). This scheme has been implemented in an ASIC design for a hypercube of dimension five. It will be used in the Proteus parallel computer system to synchronize the circuit switching communication network.
Visualizing uncertainty in multi-spectral remotely sensed imagery
Authors: Lucy Bastin, Peter F. Fisher, Jo Wood
Venue: Computers Geosciences (2002)

Error and uncertainty in remotely sensed data come from several sources, and can be increased or mitigated by the processing to which that data is subjected (e.g. resampling, atmospheric correction). Historically the effects of such uncertainty have only been considered overall and evaluated in a confusion matrix which becomes high-level meta-data, and so is commonly ignored. However, some of the sources of uncertainty can be explicitly identified and modelled, and their effects (which often vary across space and time) visualized. Others can be considered overall, but their spatial effects can still be visualized. This process of visualization is of particular value for users who need to assess the importance of data uncertainty for their own practical applications. This paper describes a Java-based toolkit, which uses interactive and linked views to enable visualization of data uncertainty by a variety of means. This allows users to consider error and uncertainty as integral elements of image data, to be viewed and explored, rather than as labels or indices attached to the data.
An Expert System to Automate Timing Design
Authors: Atsushi Kara, Ravi Rastogi, Kazuhiko Kawamura
Venue: IEEE Design Test (1988)

Presents a novel approach for automating the timing design of interfaces between VLSI chips in microcomputer systems. The Prolog-based expert system, called TDS (for timing design system), incorporates the heuristic knowledge of the hardware designer. TDS is a rule-based system that interprets the specification sheets of VLSI chips and can synthesize, diagnose, and verify timing charts at the expert's level. The system uses a functional model based on timing specifications, not the structural information. TDS can model other interfaces that are based on timing specifications, such as standard bus interfaces.
Maximizing Multiprocessor Performance with the SUIF Compiler
Authors: Mary W. Hall, Jennifer M. Anderson, Saman P. Amarasinghe, Brian R. Murphy, Shih-Wei Liao, Edouard Bugnion, Monica S. Lam
Venue: Computer (1996)

Multiple processors can work together to speed up single applications, but sequential programs must be rewritten to take advantage of the extra processors. One way to do this is through automatic parallelization with a compiler. Multiprocessors pose especially challenging problems for parallelizing compilers. Sufficient work must be performed in parallel to overcome processor synchronization and communication overhead. Moreover, multiprocessor memory hierarchies are complex, containing both shared memory and multiple levels of cache memory. Thus, two techniques are essential in obtaining good multiprocessor performance for array-based numerical programs: locating coarse-grain parallelism and managing multiprocessor memory use. The authors describe new technology in the Stanford SUIF compiler that enables it to successfully carry out these techniques. First, a suite of robust analysis techniques operate across procedure boundaries to locate coarse-grain parallelism so that large computations can execute independently in parallel. Then, to help eliminate cache misses, affine partitioning is used to improve processor reuse of data, and data permutation and data strip-mining make contiguous the data accessed by each processor in the shared address space. When employed in the automatic parallelizing compiler, these techniques significantly affect the performance of half the NAS and SPECfp95 benchmark suites.
UCFS-A Novel User-Space, High Performance, Customized File System for Web Proxy Servers
Authors: Jun Wang, Rui Min, Yingwu Zhu, Yiming Hu
Venue: IEEE Transactions on Computers (2002)

Web proxy caching servers play a key role in today's Web infrastructure. Previous studies have shown that disk I/O is one of the major performance bottlenecks of proxy servers. Most conventional file systems do not work well for proxy server workloads and have high overheads. This paper presents a novel, User-space, Customized File System, called UCFS, that can drastically improve the I/O performance of proxy servers. UCFS is a user-level software component of a proxy server which manages data on a raw disk or disk partition. Since the entire system runs in the user space, it is easy and inexpensive to implement. It also has good portability and maintainability. UCFS uses efficient in-memory meta-data tables to eliminate almost all I/O overhead of meta-data searches and updates. It also includes a novel file system called Cluster-structured File System (CFS). Similarly to the Log-structured File Systems (LFS), CFS uses large disk transfers to significantly improve disk write performance. However, CFS can also markedly improve file read operations and it does not generate garbage. Comprehensive simulation experiments using five representative real-world traces show that UCFS can significantly improve proxy server performance. For example, UCFS achieves 8-19 times better I/O performance than the state-of-the-art SQUID server running on a Unix Fast File System (FFS), 4-7.5 times better than SQUID on asynchronous FFS, and 3-9 times better than the improved SQUIDML.
Ubiquitous Computing
Authors: M. Weiser
Venue: Computer (1993)

The author suggests that, due to the trends of unobtrusive technology and more intrusive information, the next phase of computing technology will develop nonlinearly. He states that, in the long run, the personal computer and the workstation will become practically obsolete because computing access will be everywhere: in the walls, on your wrist, and in 'scrap' computers (i.e., like scrap paper) lying about to be used as needed. The current research on ubiquitous computing is reviewed.
Analysis of Asynchronous Polynomial Root Finding Methods on a Distributed Memory Multicomputer
Authors: M. Cosnard, P. Fraigniaud
Venue: IEEE Transactions on Parallel and Distributed Systems (1994)

We have studied various implementations of iterative polynomial root finding methods on a distributed memory multicomputer. These methods are based on the construction of a sequence of approximations that converge to the set of zeros. The synchronous version consists in sharing the computation of the next iterate among the processors and updating their data through a total exchange of their results. In order to decrease thecommunication cost, we introduce asynchronous versions. The computation of the nextiterate is still shared among the processor, but the updating is done by using only nearestneighbor communications. We prove that under weak conditions, these asynchronousversions are still locally convergent, even if their convergence orders are reduced. Weanalyze the behavior of the asynchronous methods in function of their delay, thetopology of the interconnection network, and the elementary computation andcommunication times. We have implemented and compared these methods on ahypercube multicomputer.
A Study of Adaptive Forward Error Correction for Wireless Collaborative Computing
Authors: Philip K. McKinley, Chiping Tang, Arun P. Mani
Venue: IEEE Transactions on Parallel and Distributed Systems (2002)

This paper addresses the problem of reliably multicasting Web resources across wireless local area networks (WLANs) in support of collaborative computing applications. An adaptive forward error correction (FEC) protocol is described, which adjusts the level of redundancy in the data stream in response to packet loss conditions. The proposed protocol is intended for use on a proxy server that supports mobile users on a WLAN. The software architecture of the proxy service and the operation of the adaptive FEC protocol are described. The performance of the protocol is evaluated using both experimentation on a mobile computing testbed as well as simulation. The results of the performance study show that the protocol can quickly accommodate worsening channel characteristics in order to reduce delay and increase throughput for reliable multicast channels.
Fuzzy expert systems architecture for image classification using mathematical morphology operators
Authors: R. M. de Moraes, G. J. F. Banon, S. A. Sandri
Venue: Information Sciences&mdash;Informatics and Computer Science: An International Journal (2002)

We propose a fuzzy expert systems architecture for image classification, whose rules are implemented through translation invariant mathematical morphology operators. The use of the architecture is illustrated by an expert system that classifies an area of the Tapajós National Forest, in Brazil.
Beating in Membrane Potential Mediated by Cortical &gamma;-Oscillations for Reading Out Synchronous Neuronal Activities Over Distant Cortical Areas
Authors: Osamu Hoshino
Venue: Neural Processing Letters (2002)

I investigate whether cortical &gamma;-oscillations are relevant to reading out synchronous neuronal firings that are distributed over the brain. A cortical neural network model is proposed and simulated. The model consists of two sensory networks (SI and SII) and one coincidence-sensitive network (CS). &gamma;-oscillatory inputs and external stimuli are applied to interneurons and projection neurons of the sensory networks, respectively. The SI and SII networks project to the CS network in a divergent/convergent manner. Here I show that beating in membrane potential of CS neurons mediates the detection of synchronous neuronal firings between the SI and SII networks. A slight increase (a few Hz) in difference between frequencies of the &gamma;-oscillations in the SI and SII networks generates the beating in the CS network. The synchronous neuronal firings are detected at each peak of the beating, regardless of difference in signal transmission time between SI-to-CS and SII-to-CS pathways.
Reexamining the Fault Density-Component Size Connection
Authors: Les Hatton
Venue: IEEE Software (1997)

Conventional wisdom, that smaller components contain proportionately fewer faults, may be wrong. This author found that medium-sized components were proportionately more reliable than large or small ones. Moreover, he says, there may be limits on the fault density we can achieve.
Motorola's 88000 Family Architecture
Authors: Mitch Alsup
Venue: IEEE Micro (1990)

The initial members of the 88000 family of high-performance 32-bit microprocessor are the 88100 processor and the 88200 cache and memory management unit (CMMU). The processor manipulates integer and floating-point data and initiates instruction and data memory transactions. The CMMU minimizes the latency of main memory requests by maintaining a cache for data transaction and a cache for memory management translations. A typical system consists of one processor and two identical cache chips, one servicing instruction fetch requests, the other servicing data read and write requests. The overall design process for the 88000 family is described, and the integer instructions are discussed. Decisions made with respect to the processor, cache, and software are examined. Some data on the use of the instruction set by the available compilers and the efficiency of the cache and memory systems are presented.
Distance-Constrained Scheduling and Its Applications to Real-Time Systems
Authors: Ching-Chih Han, Kwei-Jay Lin, Chao-Ju Hou
Venue: IEEE Transactions on Computers (1996)

In hard real-time systems, each task must not only be functionally correct but also meet its timing constraints. A common approach to characterizing hard real-time tasks with repetitive requests is the periodic task model [1]. In the periodic task model, every task needs to be executed once during each of its periods. The execution of a task in one period is independent of the execution of the same task in another period. Hence, the executions of the same task in two consecutive periods may be right next to each other, or at the far ends of the two periods. While the periodic task model can serve as a simple paradigm for scheduling tasks with repetitive requests, it may not be suitable for all real-time applications. For example, in some real-time systems, the temporal distance between the finishing times of any two consecutive executions of the same task must be less than or equal to a given value. In other words, each execution of a task has a deadline relative to the finishing time of the previous execution of the same task. Scheduling algorithms designed for the periodic task model may not provide efficient solutions for tasks with temporal distance constraints.In this paper, we propose the (preemptive) distance-constrained task system model which can serve as a more intuitive and adequate scheduling model for "repetitive" task executions. We design an efficient scheduling scheme for the model, and derive a schedulability condition for the scheduling scheme. The schedulability condition is a measure for providing the fundamental predictability requirement in hard real-time applications. To show the usefulness of the distance-constrained task model and its scheduling scheme, we also discuss how to apply the scheduling scheme to real-time sporadic task scheduling and to real-time communications.