ppxscal/embedding_network huggingface dataset:
On Coupling Multiple Systems With A Global Buffer
Authors: Ming-Syan Chen, Philip S. Yu, Tao-Heng Yang
Venue: IEEE Transactions on Knowledge and Data Engineering (1996)

In this paper, we conduct a performance study of coupling multiple systems with a global buffer, and present several results obtained from a multiple-system simulator. This simulator has been run against three workloads, and the coupled system behavior with these three different inputs is studied. Several statistics, including those on local and global buffer hits, page writes to the global buffer, cross-invalidations, and castouts are reported. Their relationship to the degree of data skew is explored. Moreover, in addition to the update-caching approach, a design alternative for the use of a global buffer, namely read-caching, is explored. In read-caching, not only updated pages but also pages read by each node are kept in the global buffer, thereby facilitating other nodes' access to the same pages at the cost of a higher global buffer usage. Also investigated is the case of no-caching, i.e., without using a global buffer. Several simulation results are presented and analyzed.
Architecture For A Low Complexity Rate-Adaptive Reed-Solomon Encoder
Authors: V. k. Bhargava, M. a. Hasan
Venue: IEEE Transactions on Computers (1995)

Multiple error-correcting Reed-Solomon (RS) codes have many practical applications. The complexity of an RS encoder depends on multiplications in the finite field over which the code is defined. In this article, we consider a triangular basis for representing the field elements, and present architecture for a rate-adaptive RS encoder using a triangular basis multiplication algorithm. The architecture supports pipeline and bit-serial operations, and has a low circuit complexity.
Proceedings of the 10th international conference on Architectural support for programming languages and operating systems
Venue: Architectural Support for Programming Languages and Operating Systems (2002)

We are pleased to welcome you to ASPLOS-X in Silicon Valley. We have the opportunity to celebrate both the 10th ASPLOS conference and the 20th year anniversary of ASPLOS since the first conference took place in Palo Alto in March 1982.While much has changed in the computer industry during the past two decades, the interdisciplinary nature of ASPLOS has allowed it to become a premier conference and a vibrant forum for discussing emerging technologies and promoting cross-fertilizing research that encompasses a wide range of areas, including hardware, architecture, compilers, operating systems, networking, and applications. ASPLOS-X is sponsored by ACM Special Interest Groups on Architecture (SIGARCH), Programming Languages (SIGPLAN), and Operating Systems (SIGOPS). In addition, we acknowledge the generous financial support from this year's corporate donors.
New algorithms for multidimensional discrete Hartley transform
Authors: Yonghong Zeng, Guoan Bi, Abdul Rahim Leyman
Venue: Signal Processing (2002)

New fast algorithms for multidimensional discrete Hartley transform (MD-DHT) are presented. Based on the index mapping and multidimensional polynomial transform (PT), the MD-DHT is converted into a series of one-dimensional type-II discrete W transform and PTs. The proposed fast algorithms achieve considerable savings on the number of operations. For example, the number of multiplications for computing an r-dimensional DHT is only 1/r times that needed by the row-column method, and the number of additions is also reduced considerably. Detailed analysis of the computational complexity is also presented.
Reducing Run Queue Contention in Shared Memory Multiprocessors
Authors: Sivarama P. Dandamudi
Venue: Computer (1997)

A run queue is a critical data structure that can affect overall performance in shared memory multiprocessor systems. Both of the basic run queue organizations, centralized and distributed, present performance problems. Among the techniques that mitigate these problems, none is completely satisfactory. This article compares uniform-memory-access multiprocessors with nonuniform-memory-access multiprocessors and describes the two basic run queue organizations, citing their main drawbacks. A look at the techniques for improving performance in these basic organizations sets the stage for the introduction of the hierarchical run queue organization. The hierarchical organization inherits the best features of the centralized and the distributed organizations while avoiding their pitfalls. In the hierarchical organization, a set of task queues is organized as a tree, and the processors with their local queues are attached to the bottom level of the tree as leaf nodes. The tree branching factor and the transfer factor, which indicates the number of tasks transferred from a parent queue to a child queue in the hierarchy, are shown to be the key design issues. Average response time of the three organizations as a function of system utilization reveals that the hierarchical organization provides the best performance for all levels of system utilization. The article concludes that this run queue organization will prove to be a useful mechanism for building large-scale shared memory multiprocessor systems.
Circular Self-Test Path for FSMs
Authors: Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
Venue: IEEE Design Test (1996)

The Circular Self-Test Path (CSTP) technique is an attractive method for automatically transforming sequential circuits generated by automatic synthesis tools into BIST structures. The first goal of this article is to assess the effectiveness of this technique from an experimental point of view; the CSTP version of several circuits from the ISCAS'89 benchmark set, as well as of a set of industrial circuits, has been built, and the attainable fault coverage has been evaluated through fault simulation experiments.The results show that in many cases a very high fault coverage is attained with a limited number of clock cycles; in other cases the fault coverage remains very low no matter the length of the test session. This is due to the circuit entering a loop, which often happens with small and medium FSMs or when short chains must be used. This danger cannot be avoided even if clever strategies for ordering the flip-flops are adopted to reduce the functional adjacency among the cells of the chain.The second goal of the article is therefore to state that the test length before a cycle in the State Transition Graph is entered can be increased and fault coverage improved by carefully choosing the initial state. Eventually, the article presents an approach based on binary decision diagrams and symbolic traversal Techniques to solve the problem. The approach is particularly suited for FSMs deriving from synthesized control parts, and it is being integrated into an industrial design flow supporting testable synthesis.
Implementing Reuse with RAD Tools' Native Objects
Authors: John C. Zubeck
Venue: Computer (1997)

The majority of objects reused in business applications are native to the development tool and designed by tool manufacturers, not application programmers. If developers confine a project's scope to these native business objects, they can achieve rapid programming and implementation, even for large applications, with quality adequate to meet clear and specific business needs. However, developers must carefully match the RAD tool to the target project's business needs. If this isn't done, the majority of development time will be spent trying to force the wrong tool to work against itself. This article describes the six business objects common to Microsoft's Visual Basic, Powerbuilder, Lotus Notes, and Magic MSE. Comparing RAD tools has become increasingly significant as interpretations of formal methodologies have become ingrained in the tools and languages. What if tools and integrated development environments could constrain and guide programmers to enforce formal design methods like those of Edsger Dijkstra or James Rumbaugh?
A framework for a dynamic interactive 3D GIS for non-expert users
Authors: Arron R. Walker, Binh Pham, Anthony Maeder
Venue: Proceedings of the 1st international conference on Computer graphics and interactive techniques in Australasia and South East Asia (2003)

Many substantial geographic information systems (GIS) have been designed for use by expert users. As a result, non-expert users often find them difficult to use. This paper presents a framework to facilitate the use of such GIS by non-expert users. The framework achieves this by allowing the creation of vague visual queries which use data abstraction and relevance feedback to obtain a final result. The data abstraction model is dynamically updated to improve future query performance.
Coping with Java Programming Stress
Authors: Roger T. Alexander, James M. Bieman, John Viega
Venue: Computer (2000)

Despite Java attributes (memory management, strong type checking, and built-in support for exception handling) that promote reliable, bug-free software, some features contribute to, rather than alleviate, programmer stress because they create obscure places for bugs to hide. The authors have identified seven features that can lead to particularly resistant bugs. Their goal is not to indict Java--they are strong supporters, and their own organizations have adopted Java as their primary programming language. Rather, they want programmers to better understand Java's weaknesses and know how to cope with them.Being aware of these design weaknesses (Java's false sense of protection, constructor confusion, finalizer methods, subclass substitution, container limitations, final parameters, and initialization diffusion), programmers can make sure that Java's design flaws don't make implementation more difficult than it has to be.
Built-In Self-Test of the Macrolan Chip
Authors: Richard Illman, Stephen Clarke
Venue: IEEE Design Test (1990)

The implementation of self-test in the medium access controller chip for Macrolan, a fibre-optic, local area network, is described. The test style for 80% of the chip's combinational logic is quasiexhaustive testing. This approach, despite its apparent inefficiency in terms of the number of patterns used, gives considerable flexibility to the designer in arranging linear-feedback shift registers and so is easier to implement than some other techniques. The chip also uses a form of random-pattern test, not normally considered for memory testing, instead of a specialized pattern generator. Built-in self-test was implemented without using fault simulation or approximate testability measures.
Camera Calibration from Surfaces of Revolution
Authors: Kwan-Yee K. Wong, Paulo R. S. Mendonça, Roberto Cipolla
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (2003)

This paper addresses the problem of calibrating a pinhole camera from images of a surface of revolution. Camera calibration is the process of determining the intrinsic or internal parameters (i.e., aspect ratio, focal length, and principal point) of a camera, and it is important for both motion estimation and metric reconstruction of 3D models. In this paper, a novel and simple calibration technique is introduced, which is based on exploiting the symmetry of images of surfaces of revolution. Traditional techniques for camera calibration involve taking images of some precisely machined calibration pattern (such as a calibration grid). The use of surfaces of revolution, which are commonly found in daily life (e.g., bowls and vases), makes the process easier as a result of the reduced cost and increased accessibility of the calibration objects. In this paper, it is shown that two images of a surface of revolution will provide enough information for determining the aspect ratio, focal length, and principal point of a camera with fixed intrinsic parameters. The algorithms presented in this paper have been implemented and tested with both synthetic and real data. Experimental results show that the camera calibration method presented here is both practical and accurate.
Distortion Invariant Object Recognition in the Dynamic Link Architecture
Authors: M. Lades, J. C. Vorbruggen, J. Buhmann, J. Lange, C. von der Malsburg, R. P. Wurtz, W. Konen
Venue: IEEE Transactions on Computers (1993)

An object recognition system based on the dynamic link architecture, an extension to classical artificial neural networks (ANNs), is presented. The dynamic link architecture exploits correlations in the fine-scale temporal structure of cellular signals to group neurons dynamically into higher-order entities. These entities represent a rich structure and can code for high-level objects. To demonstrate the capabilities of the dynamic link architecture, a program was implemented that can recognize human faces and other objects from video images. Memorized objects are represented by sparse graphs, whose vertices are labeled by a multiresolution description in terms of a local power spectrum, and whose edges are labeled by geometrical distance vectors. Object recognition can be formulated as elastic graph matching, which is performed here by stochastic optimization of a matching cost function. The implementation on a transputer network achieved recognition of human faces and office objects from gray-level camera images. The performance of the program is evaluated by a statistical analysis of recognition results from a portrait gallery comprising images of 87 persons.
The Convergence of Graphics and Vision
Authors: Jed Lengyel
Venue: Computer (1998)

Computer graphics and computer vision are inverse problems. Traditional computer graphics starts with input geometric models and produces image sequences. Traditional computer vision starts with input image sequences and produces geometric models. Lately, there has been a meeting in the middle, and the center--the prize--is to create stunning, photorealistic images in real time. Vision researchers now work from images backward just as far as necessary to create models that capture a scene without going to full geometric models. Graphics researchers now work with hybrid geometry and image models. These models use images as partial results, reusing them to take advantage of similarities in the image stream. There are several current trends that make this an exciting time for image synthesis: The combined graphics and vision approaches have a hybrid vigor, much of which stems from sampled representations. This use of captured scenes (enhanced by vision research) yields richer rendering and modeling methods (for graphics) than methods that synthesize everything from scratch. Exploiting temporal and spatial coherence (similarities in images) via the use of layers and other techniques is boosting runtime performance. The explosion in PC graphics performance is making powerful computational techniques more practical. This article surveys cutting edge work in this exciting field, some of which will debut at Siggraph 98.
Parallel Computing: Glory and Collapse
Authors: Borko Furht
Venue: Computer (1994)

A decade ago, university researchers were in love with parallel computers, and the US government amorously responded. Those were the days of glory, but times have changed: the market for massively parallel computers has collapsed, and many companies have gone out of business, but the researchers are still in love with parallel computing.
Dependability Measurement and Modeling of a Multicomputer System
Authors: D. Tang, R. K. Iyer
Venue: IEEE Transactions on Computers (1993)

A measurement-based analysis of error data collected from a DEC VAXcluster multicomputer system is presented. Basic system dependability characteristics such as error/failure distributions and hazard rate are obtained for both the individual machine and the entire VAXcluster. Markov reward models are developed to analyze error/failure behavior and to evaluate performance loss due to errors/failures. Correlation analysis is then performed to quantify relationships of error/failures across machines and across time. It is found that shared resources constitute a major reliability bottleneck. It is shown that for measured system, the homogeneous Markov model, which assumes constant failure rates, overestimates the transient reward rate for the short-term operation, and underestimates it for the long-term operation. Correlation analysis shows that errors are highly correlated across machines and across time. The failure correlation coefficient is low. However, its effect on system unavailability is significant.
Wisdom: A Software Engineering Method for Small Software Development Companies
Authors: Nuno J. Nunes, João F. Cunha
Venue: IEEE Software (2000)

Wisdom is a new software engineering method addressing the specific needs of small teams that develop and maintain interactive systems. Because Wisdom defines a process, notation, and project philosophy, it can smoothly be applied in small companies leveraging on their communication, speed, and flexibility.
Multiple-Valued Counter
Authors: T. -H. Kuo, H. C. Lin, R. C. Potter, D. Schupe
Venue: IEEE Transactions on Computers (1993)

The use of resonant tunneling diodes (RTDs) in multivalued counters, which greatly simplify the counter circuitry, is described. In order to achieve this implementation, a unique state-dependent current source is used to successively trigger RTD-based counter.
Usability Basics for Software Developers
Authors: Xavier Ferré, Natalia Juristo, Helmut Windl, Larry Constantine
Venue: IEEE Software (2001)

This tutorial discusses the general usability process and the design-evaluate-redesign cycle it follows. It also suggests how managers should implement the process in their software development organizations.
A Mathematical Model for Integrated Diagnostics
Authors: John W. Sheppard, William R. Simpson
Venue: IEEE Design Test (1991)

The authors expand on the form of the information flow model they introduced previously, (see ibid., vol.8, no.3, p.16-30 (1991)). Compiling the model requires three algorithms for determining higher-order relationships. One of these, the algorithm for computing logical closure, helps to simplify the modeling task. The authors also introduce a hypothetical antitank missile launcher to illustrate concepts and computations presented previously.
Iterative User-Interface Design
Authors: Jakob Nielsen
Venue: Computer (1993)

A method for developing user interfaces by refining them iteratively over several versions is presented. Each iteration is subjected to user testing or other usability-evaluation methods designed to uncover usability problems. This method not only eliminates problems of this nature, but also allows designers to take advantage of any insights into user needs that emerge from the tests. The author describes four case studies where the median improvement in overall usability from the first to the last iteration was 165%, and the median improvement per iteration was 38%.
Practical scientific visualization examples
Authors: Russell M. Taylor,  II
Venue: ACM SIGGRAPH Computer Graphics (2000)

Scientific visualization has yet to become a discipline founded on well-understood principles. In some cases we have rules of thumb, and there are studies that probe the capabilities and limitations of specific techniques. For the most part, however, visualization consists of a collection of ad hoc techniques and lovely examples. This article collects examples where visualization was found to be useful for particular insights or where it enabled new and fruitful types of experiment.
How Much Logic Should Go in an FPGA Logic Block?
Authors: Vaughn Betz, Jonathan Rose
Venue: IEEE Design Test (1998)

The logic blocks of most modern FPGAs contain clusters of look-up tables and flip flops, yet little is known about good choices for several key architectural parameters related to these clusters. There are three basic questions: how many look-up tables should a cluster contain, how should the flexibility of FPGA routing change as the cluster size changes, and how many inputs should the programmable routing provide to each cluster? We first show that logic clusters require fewer inputs from the routing than current commercial FPGAs provide. Secondly, we show that for best area-efficiency the flexibility of FPGA routing should be significantly reduced as the cluster size is increased. Finally, we find that clusters containing between 1 and 8 look-up tables all provide reasonable area-efficiency, as long as the number of cluster inputs and the FPGA routing flexibility are chosen appropriately.
Sites of construction: language learning, multimedia, and the international engineer
Authors: Andrea Dlaska
Venue: Computers Education (2002)

This article discusses the role of a multimedia learning environment in teaching foreign languages to engineering students. Arguing for a subject-specific and skills-oriented approach in teaching Languages for Specific Purposes (LSP) in the university, it outlines possible targets and skills for a language course for engineers. The paper goes on to discuss the advantages of using new language learning technologies in the LSP-classroom. It is argued that multimedia technology has a particular role to play in integrating complex subject matter and language learning, and that it facilitates the creation of authentic learning situations in an LSP-context. The discussion stresses the importance of combining technical aspects with pegagogical considerations, particularly with a view to promoting learner autonomy and a constructivist approach to language learning. Particular attention is given to the potential of computer technology in encouraging collaborative learning processes and in involving learners in the production of exercises and materials. The paper also considers the tutor-learner relationship in a technology-enhanced learning environment. Practical suggestions for language and skills training in a multimedia setting include a discussion of tutorial CALL (Computer-Assisted Language Learning), multimedia authoring tools, and the Internet. In conjunction with the Internet as a learning resource, the aspect of culture learning for engineering students is touched upon briefly.
Continuous and discontinuous software evolution: aspects of software evolution across multiple product lines
Authors: Mikio Aoyama
Venue: Proceedings of the 4th International Workshop on Principles of Software Evolution (2001)

This article discusses continuous and discontinuous evolutions across multiple products lines of software systems. As an empirical study, we analyzed the evolution of mobile phone software systems, which have undergone an extremely fast evolution from voice communication systems through mobile Internet terminals, to mobile Javaenabled terminals for the last four years. Along with the evolution, the software systems created three product lines and the size has quadrupled. This article discusses aspects of such extremely fast evolution and reveals continuity and discontinuity of software evolution. We claim that discontinuity is essential aspect of software evolution and taming discontinuous evolution is the challenge in the evolutionary development of software systems.
Mechanism Design for Networking Research
Authors: Jun Shu, Pravin Varaiya
Venue: Information Systems Frontiers (2003)

We propose a pricing mechanism for statistically guaranteed service in packet-switched networks. The mechanism provides congestion control and efficient resource allocation. For users, the mechanism offers better quality and lower price. Service providers can base service and revenue models in the mechanism. We apply this mechanism to the Internet.