ppxscal/embedding_network huggingface dataset:
The classical AI planning problems in the mirror of Horn linear logic: semantics, expressibility, complexity
Authors: Max Kanovich, Jacqueline Vauzeilles
Venue: Mathematical Structures in Computer Science (2001)

We introduce Horn linear logic as a comprehensive logical system capable of handling the typical AI problem of making a plan of the actions to be performed by a robot so that he could get into a set of final situations, if he started with a certain initial situation. Contrary to undecidability of propositional Horn linear logic, the planning problem is proved to be decidable for a reasonably wide class of natural robot systems. The planning problem is proved to be <tt>EXPTIME</tt>-complete for the robot systems that allow actions with non-deterministic effects. Fixing a finite signature, that is a finite set of predicates and their finite domains, we get a polynomial time procedure of making plans for the robot system over this signature. The planning complexity is reduced to <tt>PSPACE</tt> for the robot systems with only pure deterministic actions. As honest numerical parameters in our algorithms we invoke the length of description of a planning task &lsquo;from W to Z&tilde;&rsquo; and the Kolmogorov descriptive complexity of <tt>Ax</tt>T, a set of possible actions.
Using two heads in practice
Authors: Fredrik Karlsson
Venue: Proceedings of the 4th international workshop on End-user software engineering (2008)

Group development has been proposed as a way of improving quality in end user development. Earlier experiments have shown promising results on error rates. However, these studies have been carried out on students, often, in laboratory settings. This study reports on a field experiment on group development during spreadsheeting. Experienced business managers have been working alone (monads) and in groups of two (dyads), solving a context specific problem. The results show that dyads made 36% fewer errors than monads. Hence, the results verify earlier findings and that group development can be recommended as a technique to include in end user development processes to improve quality.
Detection and estimation of spectral change
Authors: P. O'shea, M. Farquharson, G. Ledwich, Z. M. Hussain
Venue: Proceedings of the 2nd WSEAS International Conference on Electronics, Control and Signal Processing (2003)

Spectral change estimation is important in many applications, because changes in spectra often correspond to changes in important physical parameters. Most attempts at detecting and estimating spectral change simply difference conventional spectra; this approach is flawed, however, because conventional spectra implicitly assume the observed signal is stationary over the measurement interval. This paper proposes a spectral change estimator which makes no such assumptions about stationarity. It is effective for signals with rapidly changing spectral components, even in the presence of heavy noise.
The impact of software process standardization on software flexibility and project management performance: Control theory perspective
Authors: Julie Yu-Chih Liu, Victor J. Chen, Chien-Lung Chan, Ting Lie
Venue: Information and Software Technology (2008)

It has been assumed for years that process standardization in the development of software will improve the efficiency of the development project by the virtues of applying a learned procedure and tight controls. Past research, however, is inconclusive in the elements that must be in place to achieve the benefits. In this study, we employ the software quality principle of flexibility as a mediator variable to determine if certain design aspects play a key role in achieving the benefits to the project of process standardization. A survey of computer professionals indicates that software flexibility is a positive influence. System designers should apply standard processes but with an eye toward quality design principles.
Improving Evidence about Software Technologies: A Look at Model-Based Testing
Authors: Arilo Dias Neto, Rajesh Subramanyan, Marlon Vieira, Guilherme Horta Travassos, Forrest Shull
Venue: IEEE Software (2008)

Model-based testing (MBT) approaches help automatically generate test cases using models extracted from software artifacts, and hold the promise to greatly affect how we build software. A review of the literature shows that certain specialized domains are applying MBT, but it does not yet seem to be a mainstream approach. The authors therefore conducted a systematic review of the literature to investigate how much evidence is available on MBT's costs and benefits, especially regarding how these techniques compare to other common testing approaches. They use these results to derive suggestions regarding what types of studies might further increase the deployment of these techniques.
Low-Cost Highly-Robust Hardened Cells Using Blocking Feedback Transistors
Authors: Michael Nicolaidis, Renaud Perez, Dan Alexandrescu
Venue: Proceedings of the 26th IEEE VLSI Test Symposium (2008)

CMOS nanometric technologies are increasingly sensitive to soft errors, including SEUs affecting storage cells and SETs initiated in the combinational logic, and eventually captured by some latches or flip-flops. SEUs affecting latches or flip-flops are by far the largest soft error rate (SER) contributor in logic. Thus, developing cost-efficient hardened storage cells to cope with SEUs in latches and flip-flops (but also in some memories difficult to protect by ECC ) is of increasing importance. This paper proposes a new principle for designing low-cost highly robust storage cells and several transistor level implementations.
The complexity of tree automata and logics of programs
Authors: E. A. Emerson, C. S. Jutla
Venue: Proceedings of the 29th Annual Symposium on Foundations of Computer Science (1988)

The computational complexity of testing nonemptiness of finite-state automata on infinite trees is investigated. It is shown that for tree automata with m states and n pairs nonemptiness can be tested in time O((mn)/sup 3n/), even though the problem is in general NP-complete. The nonemptiness algorithm is used to obtain exponentially improved, essentially tight upper bounds for numerous important modal logics of programs, interpreted with the usual semantics over structures generated by binary relations. For example, it is shown that satisfiability for the full branching time logic CTL* can be tested in deterministic double exponential time. It also follows that satisfiability for propositional dynamic logic with a repetition construct (PDL-delta) and for the propositional mu-calculus (L mu ) can be tested in deterministic single exponential time.
Inferring evolutionary history from DNA sequences
Authors: S. Kannan
Venue: Proceedings of the 31st Annual Symposium on Foundations of Computer Science (1990)

Two related problems are considered. The first is determining whether it is possible to triangulate a vertex-colored graph without introducing edges between vertices of the same color. This is related to a fundamental problem for geneticists, that of using character state information to construct evolutionary trees. The polynomial equivalence of these problems is demonstrated. An important subproblem arises when the characters are based on DNA sequences. Such characters assume up to four states. An O(n/sup 2/k) algorithm, where n is the number of species and k is the number of characters, is presented for this case.
A survey of solved problems and applications on bandwidth, edgesum, and profile of graphs
Authors: Yung-Ling Lai, Kenneth Williams
Venue: Journal of Graph Theory (1999)

This article provides a survey of results on the exact bandwidth, edgesum, and profile of graphs. A bibliography of work in these areas is provided. The emphasis is on composite graphs. This may be regarded as an update of the original survey of solved bandwidth problems by Chinn, Chv&aacute;talov&aacute;, Dewdney, and Gibbs [10] in 1982. Also several of the application areas involving these graph parameters are described. &copy; John & Sons, Inc. Graph Theory 31: 75&ndash;94, 1999
An Adaptive Overlay Network for World-Wide Geographic Messaging
Authors: Frank Duerr, Kurt Rothermel
Venue: Proceedings of the 22nd International Conference on Advanced Information Networking and Applications (2008)

In this paper, we propose an overlay network supporting world-wide geographic messaging. Our approach is based on hierarchical symbolic coordinates like /usa/fl/miami/. Although hierarchical network topologies lend themselves to the implementation of such overlay networks, they may lead to bottlenecks at the root of the hierarchy, long message paths, and inefficient bandwidth utilization. To avoid these problems, we propose an overlay network that adapts its structure to the users' communication patterns bydynamically adding "shortcut" links to the hierarchy leading to a routing mesh. We present an algorithm that carefully selects shortcuts based on their utility to assure short message paths on the one hand and to reduce the induced overhead on the other hand. Through simulations we show that this approach decreases the average path length significantly and reduces network load to about 50% comparedto hierarchical routing.
Binary de Bruijn on-chip network for a flexible multiprocessor LDPC decoder
Authors: Hazem Moussa, Amer Baghdadi, Michel Jézéquel
Venue: Proceedings of the 45th annual Design Automation Conference (2008)

This paper proposes a novel on-chip interconnection network adapted to a flexible multiprocessor LDPC decoder based on the de Bruijn network. The main characteristics of this network -- including its logarithmic diameter, scalable aggregate bandwidth, and optimized routing technique- allow it to efficiently support the communication intensive nature of the application. We present a detailed hardware implementation of the routers and the network interfaces as well as the packet format and the routing algorithm. The latter is a parallelized version of the shortest path with deflection routing algorithm. In order to evaluate the performance of the proposed network, a generic RTL VHDL description has been developed and synthesized with CMOS STMicroelectronics 0.18 &mu;m technology. The flexibility and the scalability of this onchip communication network enable it to be used for any kind of LDPC code.
The Brave New World of Multiplayer Online Games: Synchronization Issues with Smart Solutions
Authors: Marco Roccetti, Stefano Ferretti, Claudio E. Palazzi
Venue: Proceedings of the 2008 11th IEEE Symposium on Object Oriented Real-Time Distributed Computing (2008)

The technology supporting Multiplayer Online Games (MOGs) has greatly improved in the past few years. This represents great news both for players all over the world and for researchers that are struggling behind tough problems in real-time distributed systems. Indeed, MOGs represent apeculiar class of distributed systems, sharing features, requirements, challenges, and thereby also feasible solutions. To this aim, we focus on issues and state-of-art solutions related to a crucial aspect in MOG deployment: the synchronization of its nodes. In particular, we review techniques able to guarantee that the system evolves in a quick and consistent way and highlight how they canbe made more effective by exploiting specific game features. To further support this claim, we also present results from an experimental evaluation we performed.
The vertex degree distribution of passive random intersection graph models
Authors: Jerzy Jaworski, Dudley Stark
Venue: Combinatorics, Probability and Computing (2008)

In a random passive intersection graph model the edges of the graph are decided by taking the union of a fixed number of cliques of random size. We give conditions for a random passive intersection graph model to have a limiting vertex degree distribution, in particular to have a Poisson limiting vertex degree distribution. We give related conditions which, in addition to implying a limiting vertex degree distribution, imply convergence of expectation.
Towards Identifying Features of Trust in Mobile Ad Hoc Network
Authors: Normalia Samian, Mohd Aizaini Maarof, Shukor Abd Razak
Venue: Proceedings of the 2008 Second Asia International Conference on Modelling & Simulation (AMS) (2008)

In a mobile ad hoc network (MANET) where security is a crucial issue, trust plays an important factor that could improve the number of successful data transmission process. The higher the numbers of nodes that trust each other in the network means the higher successful communication process rates could be expected. To determine trust, there are several criteria need to be considered. These criteria which are also known as features or evidences can be used to represent each node’s trust properties in the trust evaluation process prior to initiating certain packet forwarding task. Nodes that are able to present valid features requested by source node will be included in the MANET operations. The aim of this paper is to provide an overview of security vulnerabilities in MANET and the use of trust concept to enhance the security. This paper also discusses several potential features that have been used in existing works which are expected to be suitable to be used in the trust evaluation process to create a trusted MANET community.
Learning to rank with ties
Authors: Ke Zhou, Gui-Rong Xue, Hongyuan Zha, Yong Yu
Venue: Proceedings of the 31st annual international ACM SIGIR conference on Research and development in information retrieval (2008)

Designing effective ranking functions is a core problem for information retrieval and Web search since the ranking functions directly impact the relevance of the search results. The problem has been the focus of much of the research at the intersection of Web search and machine learning, and learning ranking functions from preference data in particular has recently attracted much interest. The objective of this paper is to empirically examine several objective functions that can be used for learning ranking functions from preference data. Specifically, we investigate the roles of ties in the learning process. By ties, we mean preference judgments that two documents have equal degree of relevance with respect to a query. This type of data has largely been ignored or not properly modeled in the past. In this paper, we analyze the properties of ties and develop novel learning frameworks which combine ties and preference data using statistical paired comparison models to improve the performance of learned ranking functions. The resulting optimization problems explicitly incorporating ties and preference data are solved using gradient boosting methods. Experimental studies are conducted using three publicly available data sets which demonstrate the effectiveness of the proposed new methods.
A Low Energy Two-Step Successive Approximation Algorithm for ADC Design
Authors: Ricky Yiu-kee Choi, Chi-ying Tsui
Venue: Proceedings of the 9th international symposium on Quality Electronic Design (2008)

This paper proposes a new method for switching the capacitors in the DAC capacitor array of a successive approximation register (SAR) ADC. By separating the decoding of the most significant bits and the least significant bits, and using two different capacitor arrays with unequal size to determine their values, respectively, the average switching energy of the capacitor arrays can be dramatically reduced compared to the conventional switching methods. The analysis of the switching energy reduction is presented. Experiments were carried out on a 10-bit SAR-ADC designed using a 0.35um CMOS process. HSPICE simulations show that significant reduction in energy consumption is achieved using the proposed design.
Speedpath prediction based on learning from a small set of examples
Authors: Pouria Bastani, Kip Killpack, Li-C. Wang, Eli Chiprout
Venue: Proceedings of the 45th annual Design Automation Conference (2008)

In high performance designs, speed-limiting logic paths (speedpaths) impact the power/performance trade-off that is becoming critical in our low power regimes. Timing tools attempt to model and predict the delay of all the paths on a chip, which may be in the millions. These delay predictions often have a significant error and when silicon is measured there is a large variation of path delays as compared to the prediction of the tools. This variation may be caused by process, environmental or other effects that are often unpredictable. It is therefore desirable to use early silicon data to better predict and model potential speedpaths for subsequent silicon steppings. In this paper, we present a novel machine learning-based approach that uses a small number of identified speedpaths to predict a larger set of potential speedpaths, thus significantly enhancing the traditional timing prediction flows post-silicon. We demonstrate the feasibility of this approach and summarize our findings based on the analysis of silicon speedpaths from a 65nm P4 microprocessor.
Waiting time distribution of generalized later patterns
Authors: Donald E. K. Martin, John A. D. Aston
Venue: Computational Statistics Data Analysis (2008)

In this paper the concept of later waiting time distributions for patterns in multi-state trials is generalized to cover a collection of compound patterns that must all be counted pattern-specific numbers of times, and a practical method is given to compute the generalized distribution. The solution given applies to overlapping counting and two types of non-overlapping counting, and the underlying sequences are assumed to be Markovian of a general order. Patterns are allowed to be weighted so that an occurrence is counted multiple times, and patterns may be completely included in longer patterns. Probabilities are computed through an auxiliary Markov chain. As the state space associated with the auxiliary chain can be quite large if its setup is handled in a naive fashion, an algorithm is given for generating a ''minimal'' state space that leaves out states that can never be reached. For the case of overlapping counting, a formula that relates probabilities for intersections of events to probabilities for unions of subsets of the events is also used, so that the distribution is also computed in terms of probabilities for competing patterns. A detailed example is given to illustrate the methodology.
Analysis of Ad Hoc Network Performance in Emergency Communication Models
Authors: Koichi Gyoda, Nam Hoang Nguyen, Kazunori Okada, Osamu Takizawa
Venue: Proceedings of the 22nd International Conference on Advanced Information Networking and Applications - Workshops (2008)

We arrange information and communication required after a disaster from the viewpoint of time elapsed since the disaster. We propose a practical communication model for developing ad hoc network configuration technologies. We analyze the performance of ad hoc networks on this model by using a network simulator. Changing the attributes of ad hoc network protocols keep the data arrival rates high even when terminal are moving very fast. We also discuss the effect on data arrival rate of the probability that a terminal will change directions and of blocked areas where travel is impossible.
Contour compression using centroid method
Authors: Andrzej Dziech, Remigiusz Baran, Ali Ukasha
Venue: Proceedings of the 4th WSEAS International Conference on Applied Mathematics and Computer Science (2005)

A new approach for contour data compression is presented in the paper - Cartesian co-ordinates of an input contour are processed in such a way that final contour is represented by one-dimensional set of distances with constant, regular angle between them. The selection of vertices and the final algorithm for contour compression are described. Comparison of proposed method with the Ramer algorithm was also performed. For comparison the mean square error and SNR criteria were used. Finally, results of the experiments and advantages and drawbacks of proposed method are discussed.
VCluster: a thread-based Java middleware for SMP and heterogeneous clusters with thread migration support
Authors: Hua Zhang, Joohan Lee, Ratan Guha
Venue: Software&mdash;Practice Experience (2008)

Clusters, composed of symmetric multiprocessor (SMP) machines and heterogeneous machines, have become increasingly popular for high-performance computing. Message-passing libraries, such as message-passing interface (MPI) and parallel virtual machine (PVM), are de facto parallel programming libraries for clusters that usually consist of homogeneous and uni-processor machines. For SMP machines, MPI is combined with multithreading libraries like POSIX Thread and OpenMP to take advantage of the architecture. In addition to existing parallel programming libraries that are in C-C++ and FORTRAN programming languages, the Java programming language presents itself as another alternative with its object-oriented framework, platform neutral byte code, and ever-increasing performance. This paper presents a new parallel programming model and a library, VCluster, which implements this model. VCluster is based on migrating virtual threads instead of processes to support clusters of SMP machines more efficiently. The implementation uses thread migration, which can be used in dynamic load balancing. VCluster was developed in pure Java, utilizing the portability of Java to support clusters of heterogeneous machines. Several applications are developed to illustrate the use of this library and compare the usability and performance of VCluster with other approaches. Copyright &copy; 2007 John Wiley & Sons, Ltd.
A Certificateless Signature and Group Signature Schemes against Malicious PKG
Authors: Guoyan Zhang, Shaohui Wang
Venue: Proceedings of the 22nd International Conference on Advanced Information Networking and Applications (2008)

Identity-based cryptosystem has many advantages over PKI-based cryptosystem in key distribution, but key escrow is always an inherent drawback. In order to solve the problem, certificateless public key cryptography was introduced by Al-Riyami and Paterson in {8}. In this paper, we first introduce a certificateless signature scheme secure against both malicious PKG attack and DODattack without random oracle, which is the first scheme satisfying theses properties in the literature. Based on the certificateless signature scheme, we also present a constant-size group signature scheme against malicious group manager.
A Robust and Efficient Pre-Silicon Validation Environment for Mixed-Signal Circuits on Intel's Test Chips
Authors: Nathaniel August
Venue: Proceedings of the 9th international symposium on Quality Electronic Design (2008)

In the past, it was possible to validate analog CMOS circuits through transistor-level (schematic netlist) simulation. As manufacturing processes grow in complexity, the ever-increasing amount of design-for-test/manufacturability/yield/quality (DFx) circuitry renders transistor-level simulation impractical; and digital behavioral simulation ignores crucial analog interactions. This paper presents a more robust and efficient methodology for pre-silicon validation of such mixed-signal circuits. We adopt a top-down strategy and model all blocks at the behavioral level. However, we also represent select analog blocks at the transistor level. This strategy precludes the need for what is currently a weakness in mixed-signal validation – equivalence checking between analog behavioral models and analog schematics. In addition, this strategy enables performance validation to be seamlessly integrated with functional validation. Further, by leveraging the industry standard languages of SPICE, SystemVerilog and Verilog-AMS, we are able to build and simulate all modeling and validation constructs with a single tool. On Intel’s most recent test chip, our validation methodology found more bugs with fewer person-hours than previous attempts with purely digital or transistor-level validation.