ppxscal/embedding_network huggingface dataset:
Creating a system to share user experience best practices at eBay
Authors: Preston Smalley, Jeff Herman
Venue: CHI '05 extended abstracts on Human factors in computing systems (2005)

Increasingly, organizations are looking for ways to use technology to document and share information in order to increase effectiveness and foster a sense of community [1, 3]. As one example of a "community of practice" [4, 10], the eBay User Experience & Design group recently created a knowledge management system known as the Playbook to enable the eBay design community to share design best practices and other information. This paper describes the considerations that went into creating the Playbook and how the working team enabled the rest of the eBay design community throughout the world to contribute their best practices. We also discuss how the group as a whole has benefited from this system as well as lessons learned during this process which may help other design communities outside of eBay.
Scheduling for broadcast operation in heterogeneous parallel computing environments
Authors: Fukuhito Ooshita, Susumu Matsumae, Toshimitsu Masuzawa, Nobuki Tokura
Venue: Systems and Computers in Japan (2004)

Parallel computing utilizes heterogeneous parallel computing environments in which multiple processors of various kinds are connected by communication links. Efficient collective communication operations are needed to realize efficient parallel computing in parallel computing environments. Although methods for realizing efficient collective communication operations have previously been proposed for homogeneous parallel computing environments, these methods applied as they are to heterogeneous parallel computing environments cannot realize efficient collective communication operations. In this paper, we consider design of an efficient broadcast, which is one of the most important collective communication operations. We show that we can extend the known sufficient condition for Fastest-Node-First (FNF) to output an optimal schedule, where FNF is an efficient heuristic algorithm for the broadcast. We show that we can reduce the time cost of the branch-and-bound search for the optimal schedule. &copy; 2004 Wiley Periodicals, Inc. Syst Comp Jpn, 35(5): 44&ndash;54, 2004; Published online in Wiley InterScience (). DOI 10.1002&sol;scj.10533
Minimizing quadratic functions subject to bound constraints with the rate of convergence and finite termination
Authors: Zdeněk Dostál, Joachim Schöberl
Venue: Computational Optimization and Applications (2005)

A new active set based algorithm is proposed that uses the conjugate gradient method to explore the face of the feasible region defined by the current iterate and the reduced gradient projection with the fixed steplength to expand the active set. The precision of approximate solutions of the auxiliary unconstrained problems is controlled by the norm of violation of the Karush-Kuhn-Tucker conditions at active constraints and the scalar product of the reduced gradient with the reduced gradient projection. The modifications were exploited to find the rate of convergence in terms of the spectral condition number of the Hessian matrix, to prove its finite termination property even for problems whose solution does not satisfy the strict complementarity condition, and to avoid any backtracking at the cost of evaluation of an upper bound for the spectral radius of the Hessian matrix. The performance of the algorithm is illustrated on solution of the inner obstacle problems. The result is an important ingredient in development of scalable algorithms for numerical solution of elliptic variational inequalities.
Polynomial Algorithms for a Two-Class Multiprocessor Scheduling Problem in Mobile Telecommunications Systems
Authors: Paolo Detti, Alessandro Agnetis, Gianfranco Ciaschetti
Venue: Journal of Scheduling (2005)

In Universal Mobile Telecommunications Systems radio access, information packets of different services and users are sent across the air interface organized into radio frames. A radio frame is divided into a fixed number of time slots, different packets can share the same time slot and exactly one slot must be assigned to each packet. The packets of different services have divisible sizes and the slot capacity is limited. Quality of Service requirements set time intervals within which each packet must be scheduled. In this work, we address the problem of scheduling packets related to two different services to the time slots of a radio frame. The problem is a variant of the High-Multiplicity Multiprocessor Scheduling Problem in which there are two classes of jobs with divisible sizes, and the jobs must satisfy assignment restrictions. Two polynomial--time scheduling algorithms, maximizing the number of scheduled packets, and the weighted throughput, are provided.
Quality-of-service and error control techniques for mesh-based network-on-chip architectures
Authors: Praveen Vellanki, Nilanjan Banerjee, Karam S. Chatha
Venue: Integration, the VLSI Journal (2005)

Network-on-a-chip (NoC) has been proposed as a solution for addressing the design challenges of future high-performance system-on-chip architectures in the nanoscale regime. Many real-time applications require input data that arrives with low delay jitter. Such communication traffic can only be supported by incorporating multiple levels of service in the interconnection network. Further, as technology scales toward deep submicron, on-chip interconnects are becoming more and more sensitive to noise sources such as power supply noise, crosstalk, and radiation induced effects, that are likely to reduce the reliability of data. Hence, effective error control schemes are required for ensuring data integrity. This paper addresses two important aspects of NoC architectures, quality of service and error control schemes and makes the following contributions: (i) it presents techniques for supporting guaranteed throughput (for low delay jitter traffic) and best-effort traffic quality levels in NoC router, (ii) it presents architectures for integrating error control schemes in the NoC router architecture, and (iii) it presents cycle accurate power and performance models of the two architecture enhancements for a mesh based NoC architecture.
Proceedings of the twenty-third ACM SIGMOD-SIGACT-SIGART symposium on Principles of database systems
Venue: Symposium on Principles of Database Systems (2004)

This volume contains the proceedings of the Twenty-third ACM SIGMOD-SIGACT-SIGART Symposium on Principles of Database Systems (PODS 2004), held at Le Maison de la Chimie, Paris, France, on June 14-16, 2004 in conjunction with the 2004 ACM SIGMOD International Conference on Management of Data. It consists of a paper based on the invited talk by Georg Gottlob, and 30 contributed papers that were selected by the program committee for presentation at the symposium.The program committee has selected the contributed papers from 183 submissions. Some of the papers are \extended abstracts" and are preliminary reports on work in progress. While the program committee has read them carefully and discussed them intensively, they have not been formally refereed. It is expected that much of the research described in these papers will be published in detail in computer science journals, where they will go through a formal review.The program committee selected Conditional XPath, the First Order Complete XPath Dialect by Maarten Marx for both the PODS 2004 Best Paper Award and the Best Newcomer Award. Warmest congratulations to the author.The year 2004 marks the first time when the SIGMOD/PODS event was located outside of North America. This recognizes the international status of the event, and will hopefully start a beautiful new tradition.
Kinesthetic Haptics Integration into Large-Scale Virtual Environments
Authors: Urs Kunzler, Christoph Runde
Venue: Proceedings of the First Joint Eurohaptics Conference and Symposium on Haptic Interfaces for Virtual Environment and Teleoperator Systems (2005)

In this paper we investigate the hardware and software challenges to integrate kinesthetic haptic force feedback into large-scale (i.e. human-sized or larger) Virtual Environments (VE). Based on a literature survey of current haptic interface technologies, we introduce a qualitative schema for the evaluation of large-scale haptic immersion of various haptic display types suitable to be used within such large VEs. The other focus of our research concentrates on the elaboration of a distributed software architecture for an adaptable and extendable framework for VE haptics integration. In particular we describe a specific Haptics-Server prototype implementation integrated into a three wall passive stereo CAVE system currently being built at the Fraunhofer IPA institute in Stuttgart.
Spatial Priors for Part-Based Recognition Using Statistical Models
Authors: David Crandall, Pedro Felzenszwalb, Daniel Huttenlocher
Venue: Proceedings of the 2005 IEEE Computer Society Conference on Computer Vision and Pattern Recognition (CVPR'05) - Volume 1 - Volume 01 (2005)

We present a class of statistical models for part-based object recognition that are explicitly parameterized according to the degree of spatial structure they can represent. These models provide a way of relating different spatial priors that have been used for recognizing generic classes of objects, including joint Gaussian models and tree-structured models. By providing explicit control over the degree of spatial structure, our models make it possible to study the extent to which additional spatial constraints among parts are actually helpful in detection and localization, and to consider the tradeoff in representational power and computational cost. We consider these questions for object classes that have substantial geometric structure, such as airplanes, faces and motorbikes, using datasets employed by other researchers to facilitate evaluation. We find that for these classes of objects, a relatively small amount of spatial structure in the model can provide statistically indistinguishable recognition performance from more powerful models, and at a substantially lower computational cost.
Parallel LU factorization of sparse matrices on FPGA-based configurable computing engines: Research Articles
Authors: Xiaofang Wang, Sotirios G. Ziavras
Venue: Concurrency and Computation: Practice Experience (2004)

Configurable computing, where hardware resources are configured appropriately to match specific hardware designs, has recently demonstrated its ability to significantly improve performance for a wide range of computation-intensive applications. With steady advances in silicon technology, as predicted by Moore's Law, Field-Programmable Gate Array (FPGA) technologies have enabled the implementation of System-on-a-Programmable-Chip (SOPC or SOC) computing platforms, which, in turn, have given a significant boost to the field of configurable computing. It is possible to implement various specialized parallel machines in a single silicon chip. In this paper, we describe our design and implementation of a parallel machine on an SOPC development board, using multiple instances of a soft IP configurable processor; we use this machine for LU factorization. LU factorization is widely used in engineering and science to solve efficiently large systems of linear equations. Our implementation facilitates the efficient solution of linear equations at a cost much lower than that of supercomputers and networks of workstations. The intricacies of our FPGA-based design are presented along with tradeoff choices made for the purpose of illustration. Performance results prove the viability of our approach. Copyright &copy; 2004 John Wiley & Sons, Ltd.
The SOFG anatomy entry list (SAEL): an annotation tool for functional genomics data: Conference Papers - Report of a workshop on integration of anatomy ontologies, held at the MRC human genetics unit, Edinburgh, 7&ndash;8 April 2004
Authors: Helen Parkinson, Stuart Aitken, Richard A. Baldock, Jonathan B. L. Bard, Albert Burger, Terry F. Hayamizu, Alan Rector, Martin Ringwald, Jeremy Rogers, Cornelius Rosse, Christian J. Stoeckert,  Jr., Duncan Davidson
Venue: Comparative and Functional Genomics (2004)

A great deal of data in functional genomics studies needs to be annotated with low-resolution anatomical terms. For example, gene expression assays based on manually dissected samples (microarray, SAGE, etc.) need high-level anatomical terms to describe sample origin. First-pass annotation in high-throughput assays (e.g. large-scale in situ gene expression screens or phenotype screens) and bibliographic applications, such as selection of keywords, would also benefit from a minimum set of standard anatomical terms. Although only simple terms are required, the researcher faces serious practical problems of inconsistency and confusion, given the different aims and the range of complexity of existing anatomy ontologies. A Standards and Ontologies for Functional Genomics (SOFG) group therefore initiated discussions between several of the major anatomical ontologies for higher vertebrates. As we report here, one result of these discussions is a simple, accessible, controlled vocabulary of gross anatomical terms, the SOFG Anatomy Entry List (SAEL). The SAEL is available from and is intended as a resource for biologists, curators, bioinformaticians and developers of software supporting functional genomics. It can be used directly for annotation in the contexts described above. Importantly, each term is linked to the corresponding term in each of the major anatomy ontologies. Where the simple list does not provide enough detail or sophistication, therefore, the researcher can use the SAEL to choose the appropriate ontology and move directly to the relevant term as an entry point. The SAEL links will also be used to support computational access to the respective ontologies. Copyright &copy; 2004 John Wiley & Sons, Ltd.
High-level heterogeneous distributed parallel programming
Authors: Chia-Chu Chiang
Venue: Proceedings of the 2004 international symposium on Information and communication technologies (2004)

Low-level language constructs are considered harmful for heterogeneous distributed parallel programming. A program makes unstructured use of these low-level language constructs may be difficult to understand and debug. In this paper, we discuss that IP (interacting process) is an ideal language for heterogeneous distributed parallel programming. An approach is proposed to realize IP programs through Multiparty Interaction (MI) protocol. The approach provides a synergy of heterogeneity, communication, distribution, and parallelism for programmers to transparently develop heterogeneous distributed parallel applications.
On stalling in LogP
Authors: Gianfranco Bilardi, Kieran Herley, Andrea Pietracaprina, Geppino Pucci
Venue: Journal of Parallel and Distributed Computing (2005)

We investigate the issue of stalling in the LogP model. In particular, we introduce a novel quantitative characterization of stalling, referred to as @d-stalling, which intuitively captures the realistic assumption that once the network's capacity constraint is violated, it takes some time (at most @d) for this information to propagate to the processors involved. We prove a lower bound that shows that LogP under @d-stalling is strictly more powerful than the stall-free version of the model where only strictly stall-free computations are permitted. On the other hand, we show that @d-stalling LogP with @d=L can be simulated with at most logarithmic slowdown by a BSP machine with similar bandwidth and latency values, thus extending the equivalence (up to logarithmic factors) between stall-free LogP and BSP argued in Bilardi et al. (Algorithmica 24 (1999) 405) and Ramachandran et al. (J. Parallel Distributed Comput. 63 (2003) 1175) to the more powerful L-stalling LogP.
Research on meaning-representation in natural languages: U. of California at Berkeley
Authors: L. A. Zadeh
Venue: Issue 79 (January 1982) (1982)

A basic assumption underlying our approach to the problem of meaning-representation in natural languages is that almost everything that relates to natural languages is a matter of degree. Viewed in this perspective, the classical two-valued logic does not provide a suitable basis for a comprehensive theory of natural languages and, especially, for the representation of meaning, knowledge and strength of belief.
Named graphs, provenance and trust
Authors: Jeremy J. Carroll, Christian Bizer, Pat Hayes, Patrick Stickler
Venue: Proceedings of the 14th international conference on World Wide Web (2005)

The Semantic Web consists of many RDF graphs nameable by URIs. This paper extends the syntax and semantics of RDF to cover such Named Graphs. This enables RDF statements that describe graphs, which is beneficial in many Semantic Web application areas. As a case study, we explore the application area of Semantic Web publishing: Named Graphs allow publishers to communicate assertional intent, and to sign their graphs; information consumers can evaluate specific graphs using task-specific trust policies, and act on information from those Named Graphs that they accept. Graphs are trusted depending on: their content; information about the graph; and the task the user is performing. The extension of RDF to Named Graphs provides a formally defined framework to be a foundation for the Semantic Web trust layer.
Verification of distributed programs using representative interleaving sequences
Authors: Shmuel Katz, Doron Peled
Venue: Distributed Computing (1992)

We present a formal proof method for distributed programs. The semantics used to justify the proof method explicitly identifies equivalence classes of execution sequences which are equivalent up to permuting commutative operations. Each equivalence class is called an interleaving set or a run. The proof rules allow concluding the correctness of certain classes of properties for all execution sequences, even though such properties are demonstrated directly only for a subset of the sequences. The subset used must include a representative sequence from each interleaving set, and the proof rules, when applicable, guarantee that this is the case. By choosing a subset with appropriate sequences, simpler intermediate assertions can be used than in previous formal approaches. The method employs proof lattices, and is expressed using the temporal logic ISTL.
Parallel-Beam Backprojection: An FPGA Implementation Optimized for Medical Imaging
Authors: Miriam Leeser, Srdjan Coric, Eric Miller, Haiqian Yu, Marc Trepanier
Venue: Journal of VLSI Signal Processing Systems (2005)

Medical image processing in general and computerized tomography (CT) in particular can benefit greatly from hardware acceleration. This application domain is marked by computationally intensive algorithms requiring the rapid processing of large amounts of data. To date, reconfigurable hardware has not been applied to the important area of image reconstruction. For efficient implementation and maximum speedup, fixed-point implementations are required. The associated quantization errors must be carefully balanced against the requirements of the medical community. Specifically, care must be taken so that very little error is introduced compared to floating-point implementations and the visual quality of the images is not compromised. In this paper, we present an FPGA implementation of the parallel-beam backprojection algorithm used in CT for which all of these requirements are met. We explore a number of quantization issues arising in backprojection and concentrate on minimizing error while maximizing efficiency. Our implementation shows approximately 100 times speedup over software versions of the same algorithm running on a 1 GHz Pentium, and is more flexible than an ASIC implementation. Our FPGA implementation can easily be adapted to both medical sensors with different dynamic ranges as well as tomographic scanners employed in a wider range of application areas including nondestructive evaluation and baggage inspection in airport terminals.
Proceedings of the 2004 workshop on Interpreters, virtual machines and emulators
Venue: Interpreters, Virtual Machines And Emulators (2004)

Welcome to IVME'04! This second workshop on Interpreters, Virtual Machines, and Emulators is the occasion for presenting new research and experience reports in an exciting field of modern computing. Three invited talks from key industrial research teams are also featured this year.We have received fifteen paper submissions. The review process worked as follows. Shortly after the submission deadline, program committee (PC) members were asked to indicate their preferences on papers to review and declare any conflict of interest using a web based system. Then papers were distributed to review by PC members based on their preferences, while also guaranteeing that each paper was reviewed by at least three PC members. 48 reviews were submitted. Finally, a virtual committee meeting was held by e-mail on April 15-16, 2004. A sub-committee which did not include any PC member with a conflict of interest was also formed to discuss separately (and concurrently) papers involved in conflicts of interest. Finally six papers were selected for publication (acceptance rate of 40%).
Regular meshes
Authors: Ergun Akleman, Jianer Chen
Venue: Proceedings of the 2005 ACM symposium on Solid and physical modeling (2005)

This paper presents our preliminary results on regular meshes in which all faces have the same size and all vertices have the same valence. A regular mesh is denoted by (n, m, g) where n is the number of the sides of faces, m is the valence of vertices and g is the genus of the mesh. For g = 0, regular meshes include regular platonic solids, all two sided polygons. For g = 1 regular meshes include regular tilings of infinite plane. Our work shows that there exist infinitely many regular meshes for g > 1. Moreover, we have constructive proofs that describe how to create high genus regular meshes that consist of triangles and quadrilaterals (3, m, g) and (4, m, g).
Mining Web Log Sequential Patterns with Position Coded Pre-Order Linked WAP-Tree
Authors: C. I. Ezeife, Yi Lu
Venue: Data Mining and Knowledge Discovery (2005)

Sequential mining is the process of applying data mining techniques to a sequential database for the purposes of discovering the correlation relationships that exist among an ordered list of events. An important application of sequential mining techniques is web usage mining, for mining web log accesses, where the sequences of web page accesses made by different web users over a period of time, through a server, are recorded. Web access pattern tree (WAP-tree) mining is a sequential pattern mining technique for web log access sequences, which first stores the original web access sequence database on a prefix tree, similar to the frequent pattern tree (FP-tree) for storing non-sequential data. WAP-tree algorithm then, mines the frequent sequences from the WAP-tree by recursively re-constructing intermediate trees, starting with suffix sequences and ending with prefix sequences.This paper proposes a more efficient approach for using the WAP-tree to mine frequent sequences, which totally eliminates the need to engage in numerous re-construction of intermediate WAP-trees during mining. The proposed algorithm builds the frequent header node links of the original WAP-tree in a pre-order fashion and uses the position code of each node to identify the ancestor/descendant relationships between nodes of the tree. It then, finds each frequent sequential pattern, through progressive prefix sequence search, starting with its first prefix subsequence event. Experiments show huge performance gain over the WAP-tree technique.