ppxscal/embedding_network huggingface dataset:
Bayesian analysis of the Logit model and comparison of two Metropolis-Hastings strategies
Authors: Anas Altaleb, Didier Chauveau
Venue: Computational Statistics Data Analysis (2002)

We examine some Markov chain Monte Carlo (MCMC) methods for a generalized non-linear regression model, the Logit model. It is first shown that MCMC algorithms may be used since the posterior is proper under the choice of non-informative priors. Then two non-standard MCMC methods are compared: a Metropolis-Hastings algorithm with a bivariate normal proposal resulting from an approximation, and a Metropolis-Hastings algorithm with an adaptive proposal. The results presented here are illustrated by simulations, and show the good behavior of both methods, and superior performances of the method with an adaptive proposal in terms of convergence to the stationary distribution and exploration of the posterior distribution surface.
Commonality and Variability in Software Engineering
Authors: James Coplien, Daniel Hoffman, David Weiss
Venue: IEEE Software (1998)

The article describes how to perform domain engineering by identifying the commonalities and variabilities within a family of products. Through interesting examples dealing with reuse libraries, design patterns, and programming language design, the authors suggest a systematic Scope, Commonalities, and Variabilities approach to formal analysis. Their SCV analysis has been an integral part of the FAST (Family-oriented Abstraction, Specification, and Translation) technology applied to over 25 domains at Lucent Technologies.
A Non-Parametric Approach to Pricing and Hedging Derivative Securities: With an Application to LIFFE Data
Authors: J. A. Barria, S. G. Hall
Venue: Computational Economics (2002)

It is important for financial institutions to develop methods to predict their exposure and keep their risk under control. Portfolio managers can insure themselves against the value (of a diversified stock portfolio) dropping below a certain level, by holding in conjunction with the stock portfolio, an index option derivative security. The work reported in this paper is concerned with the study of non-parametric methods for estimating the pricing formula of option derivative securities. Two non-parametric approaches, the projection pursuit method (PPR) and the local polynomial approach (LOESS), are studied and compared to a benchmark parametric Black&ndash;Scholes (B&ndash;S) approach. The practical relevance of these approaches is tested, when applied to pricing and hedging of real-world LIFFE FTSE 100 index options from April 1997 to November 1997. We compare the two methods by means of constructing a riskless portfolio of stocks, bonds and option derivatives securities. The portfolio is then delta-hedged on a daily basis using a dynamic trading strategy in stocks and bonds during the lifetime of the option instrument. The tests carried out show that both methods generate similar responses, although each method can outperform the others depending on market conditions, such as, time to maturity of the option instrument.
Efficient Algorithms for Array Redistribution
Authors: Rajeev Thakur, Alok Choudhary, J. Ramanujam
Venue: IEEE Transactions on Parallel and Distributed Systems (1996)

Dynamic redistribution of arrays is required very often in programs on distributed memory parallel computers. This paper presents efficient algorithms for redistribution between different cyclic(k) distributions, as defined in High Performance Fortran. We first propose special optimized algorithms for a cyclic(x) to cyclic(y) redistribution when x is a multiple of y, or y is a multiple of x. We then propose two algorithms, called the GCD method and the LCM method, for the general cyclic(x) to cyclic(y) redistribution when there is no particular relation between x and y. We have implemented these algorithms on the Intel Touchstone Delta, and find that they perform well for different array sizes and number of processors.
Fast Parallel Algorithm for Ternary Multiplication Using Multivalued I/sup 2/L Technology
Authors: M. De, B. P. Sinha
Venue: IEEE Transactions on Computers (1994)

Presents an algorithm for parallel multiplication of two n-bit ternary numbers. This algorithm uses the technique of column compression and computes the product in (2 upper bound /spl lsqb/log/sub 2/n/spl rsqb/+2) units of addition time of a single-bit ternary full adder. This algorithm requires regular interconnection between any two types of cells and hence is very suitable for VLSI implementation. The same algorithm is also applicable to the multiplication of negative numbers.
A spiking neuron model: applications and learning
Authors: Chris Christodoulou, Guido Bugmann, Trevor G. Clarkson
Venue: Neural Networks (2002)

This paper presents a biologically inspired, hardware-realisable spiking neuron model, which we call the Temporal Noisy-Leaky Integrator (TNLI). The dynamic applications of the model as well as its applications in Computational Neuroscience are demonstrated and a learning algorithm based on postsynaptic delays is proposed. The TNLI incorporates temporal dynamics at the neuron level by modelling both the temporal summation of dendritic postsynaptic currents which have controlled delay and duration and the decay of the somatic potential due to its membrane leak. Moreover, the TNLI models the stochastic neurotransmitter release by real neuron synapses (with probabilistic RAMs at each input) and the firing times including the refractory period and action potential repolarisation. The temporal features of the TNLI make it suitable for use in dynamic time-dependent tasks like its application as a motion and velocity detector system presented in this paper. This is done by modelling the experimental velocity selectivity curve of the motion sensitive HI neuron of the visual system of the fly. This application of the TNLI indicates its potential applications in artificial vision systems for robots. It is also demonstrated that Hebbian-based learning can be applied in the TNLI for postsynaptic delay training based on coincidence detection, in such a way that an arbitrary temporal pattern can be detected and recognised. The paper also demonstrates that the TNLI can be used to control the firing variability through inhibition; with 80% inhibition to concurrent excitation, firing at high rates is nearly consistent with a Poisson-type firing variability observed in cortical neurons. It is also shown with the TNLI, that the gain of the neuron (slope of its transfer function) can be controlled by the balance between inhibition and excitation, the gain being a decreasing function of the proportion of inhibitory inputs. Finally, in the case of perfect balance between inhibition and excitation, i.e. where the average input current is zero, the neuron can still fire as a result of membrane potential fluctuations. The firing rate is then determined by the average input firing rate. Overall this work illustrates how a hardware-realisable neuron model can capitalise on the unique computational capabilities of biological neurons.
A Computationally Tractable Nonmonotonic Logic
Authors: T. J. Weigert, J. J. -P. Tsai
Venue: IEEE Transactions on Knowledge and Data Engineering (1994)

Nonmonotonic logic is intended to apply specifically to situations where the initial information is incomplete. Using nonmonotonic reasoning procedures we shall be able to jump to conclusions, but withdraw them later when we gain additional information. A number of nonmonotonic logics have been introduced and widely discussed. Nonmonotonic logics tend to be introduced proof theoretically, and little attention is paid to their semantic characteristics or their computational tractability. We address both of these issues by presenting a nonmonotonic logic for the Herbrand subset of first-order predicate logic. This nonmonotonic logic is shown to be both sound and complete. Theories formulated in this logic can be executed in logic programming fashion.
Self-dual and maximal self-orthogonal codes over F7
Authors: Masaaki Harada, Patric R. J. Östergård
Venue: Discrete Mathematics (2002)

In this note, we give the classification of self-dual F7-codes of length 12 and maximal self-orthogonal codes of lengths 10, 11 and 13. It is also shown that there is no self-dual [16,8,d ≥ 8] code over F7.
3-D Pose from 3 Points Using Weak-Perspective
Authors: T. D. Alter
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1994)

This correspondence discusses computing the pose of a model from three matching point pairs under weak-perspective projection. A new approach to the problem that is motivated geometrically is described. Like previous methods, the method here involves solving a biquadratic equation, but here the biquadratic's solutions, comprised of an actual and a false solution, are interpreted graphically. The final equations take a new form, which leads to a simple expression for the image position of any unmatched model point.
Nonmonotonic Reasoning as Prioritized Argumentation
Authors: J. -H. You, X. Wang, L. -Y. Yuan
Venue: IEEE Transactions on Knowledge and Data Engineering (2001)

This paper proposes a formalism for nonmonotonic reasoning based on prioritized argumentation. We argue that nonmonotonic reasoning in general can be viewed as selecting monotonic inferences by a simple notion of priority among inference rules. More importantly, these types of constrained inferences can be specified in a knowledge representation language where a theory consists of a collection of rules of first order formulas and a priority among these rules. We recast default reasoning as a form of prioritized argumentation and illustrate how the parameterized formulation of priority may be used to allow various extensions and modifications to default reasoning. We also show that it is possible, but more difficult, to express prioritized argumentation by default logic: Even some particular forms of prioritized argumentation cannot be represented modularly by defaults under the same language.
Architectural differences of efficient sequential and parallel computers
Authors: Martti J. Forsell
Venue: Journal of Systems Architecture: the EUROMICRO Journal (2002)

In this paper we try to conclude what kind of a computer architecture is efficient for executing sequential problems, and what kind of an architecture is efficient for executing parallel problems from the processor architect's point of view. For that purpose we analytically evaluate the performance of eight general purpose processor architectures representing widely both commercial and scientific processor designs in both single processor and multiprocessor setups. The results are interesting. The most efficient architecture for sequential problems is a two-level pipelined VLIW (very long instruction word) architecture with few parallel functional units. The most efficient architecture for parallel problems is a deeply inter-thread superpipelined architecture in which functional units are chained. Thus, designing a computer for efficient sequential computation leads to a very different architecture than designing one for efficient parallel computation and there exists no single optimal architecture for general purpose computation.
Real-time implementation of the relative position estimation algorithm using the aerial image sequence
Authors: Kwan-Suk Kim, Jae-Hong Park, Rin-Chul Kim, Rae-Hong Park, Sang Uk Lee, In Chul Kim
Venue: Real-Time Imaging (2002)

This paper deals with an implementation of the navigation parameter extraction algorithm on the TMS320C80 multimedia video processor (MVP). Especially, this paper focuses on the relative position estimation algorithm which plays an important role in the real-time operation of the overall system. Based on the relative position estimation algorithm proposed in [1], we develop a sliding window method that can reduce the computational complexity of the feature block extraction greatly. Then, we make the algorithm fit into four fixed-point processors in the MVP, considering the data dependency and the effects due to the finite register length. As a result, we demonstrate that the navigation parameter extraction system implemented on the MVP can operate at full-frame rate, by exploiting the computational power of the MVP fully.
Transversal-Free Translation Nets
Authors: Vikram Jha, Norman L. Johnson
Venue: Designs, Codes and Cryptography (2002)

Translation planes of order q2 containing non-Desarguesian Baer subplanes are used to construct transversal-free translation nets with very small deficiencies. Also, a generalization of the ideas of Bruen shows that any non-Desarguesian spread in PG(3, q) produces a transversal-free net of small deficiency.
A 15-colouring of 3-space omitting distance one
Authors: D. Coulson
Venue: Discrete Mathematics (2002)

It is known that the number χ(R3) of colours necessary to colour each point of 3-space so that no two points lying distance 1 apart have the same colour lies between 5 and 18. All optimal colourings (which establish the upper bound for χ(Rn)) have to date been found using lattice-sublattice colouring schemes. This paper shows that in Rn such colouring schemes must use at least 2n+1 - 1 colours to have an excluded distance. In addition this paper constructs a 1-excluded colouring of R3 using a lattice--sublattice scheme with 15 colours---the least number of colours possible for such schemes.
Designing reflective dialogue to support learning from experience
Authors: Mark Aakhus
Venue: ACM SIGGROUP Bulletin (2001)

This paper discusses the design and use of a web-based application-"virtual dialectic"-created to facilitate learning from experience among distributed participants who are also engaged in work. The approach taken in developing this application embraces the observation that language is a form of action and the importance of technological design in helping people manage "break down" in ongoing activities [1]. The virtual dialectic, unlike many CSCW systems, is not designed to directly support the conduct of some particular work practice. Instead, the application addresses how people make sense of communication at work and in professional life with the goal of helping individuals develop their self-understanding and identity as professionals. The application draws users attention to aspects of organizational action they might otherwise take for granted by providing "micro" and "macro" tools for participants to orchestrate their distant interaction as a type of reflective dialogue.The virtual dialectic application is an interesting case for those interested in the language action perspective on communication modeling because this application explores, essentially, how to articulate cooperation at conflict. Such a design goal may, on its face, seem odd since many CSCW systems are geared toward the achievement of consensus and intersubjectivity among users. Alterity, disagreement, and conflict, however, are important collaborative achievements that contribute to learning, decision-making, and innovation processes.This paper has two parts. First, the key aspects of the virtual dialectic application are described relative to the background assumptions, and the context of development, that inform its design. This section outlines the rationale for framing design as the management of disagreement rather than the management of consensus. The broader design assumptions, requirements, and procedures of the virtual dialectic are described in derail elsewhere [2]. Second, an example of online interaction using the virtual dialectic is discussed to illustrate the complex ways in which participants avoid and express opposition. The main purpose is to explore the important puzzle managing disagreement presents for designing systems to support processes such as learning and deliberation.
A stateless, content-directed data prefetching mechanism
Authors: Robert Cooksey, Stephan Jourdan, Dirk Grunwald
Venue: Proceedings of the 10th international conference on Architectural support for programming languages and operating systems (2002)

Although central processor speeds continues to improve, improvements in overall system performance are increasingly hampered by memory latency, especially for pointer-intensive applications. To counter this loss of performance, numerous data and instruction prefetch mechanisms have been proposed. Recently, several proposals have posited a memory-side prefetcher; typically, these prefetchers involve a distinct processor that executes a program slice that would effectively prefetch data needed by the primary program. Alternative designs embody large state tables that learn the miss reference behavior of the processor and attempt to prefetch likely misses.This paper proposes Content-Directed Data Prefetching, a data prefetching architecture that exploits the memory allocation used by operating systems and runtime systems to improve the performance of pointer-intensive applications constructed using modern language systems. This technique is modeled after conservative garbage collection, and prefetches "likely" virtual addresses observed in memory references. This prefetching mechanism uses the underlying data of the application, and provides an 11.3% speedup using no additional processor state. By adding less than &frac12;% space overhead to the second level cache, performance can be further increased to 12.6% across a range of "real world" applications.
An Interconnect Architecture for Networking Systems on Chips
Authors: Faraydon Karim, Anh Nguyen, Sujit Dey
Venue: IEEE Micro (2002)

Network processor systems on chips meet the speed and flexibility requirements of next-generation internet routers. The octagon on-chip communication architecture, with its cost, performance, and scalability advantages, supports these network processor SOCs.
An Integrated CAD Environment for Low-Power Design
Authors: Paul Landman, Renu Mehra, Jan M. Rabaey
Venue: IEEE Design Test (1996)

A CAD environment for low-power design is presented. The environment supports a high-level approach to power reduction, emphasizing optimizations at the algorithm and architecture levels of abstraction. This methodology is consistent with current state-of-the-art techniques for low-power design. The framework consists of a set of analysis and optimization tools that span the design hierarchy. These tools are integrated in a way that allows the designer to employ a systematic approach to low-power design through a top-down exploration and refinement of solutions in the area-time-power (ATP) design space. The efficacy of the CAD environment and tools is illustrated by a case study which leads to a low-power implementation of a digital bandpass filter. The proposed approach is shown to lead to more than an order of magnitude savings in power. This result is achieved by a thorough search of the area-time-power design space, which would not have been possible without the assistance of high-level design tools.
The SIMS: Unleashed
Authors: Prima Temp, Mark Cohen
Venue:  (2002)

:Welcome to the Animal House ·Strategies for housebreaking and obedience training your dog ·How to put your best paw forward in the pet show ·Details on what's new in the neighborhood ·Complete pet interaction tables ·Learn the secret to growing monster vegetables ·How to keep bunnies and gophers from devouring your garden ·New career track tables
Future WAN Telecommunications
Authors: Alexander G. Fraser
Venue: IEEE Micro (1996)

We are about to see a major investment in telecommunications, one that will substantially impact the lives of our children and their children for probably the better part of the next century. At the least, there will be a new access network that gives us multi-megabit per second communication from our homes to other people and to businesses across the nation. Impetus for this change can be seen in today's use of the Internet and on-line services. Web browsers bring interactive communication with computer graphics to millions of hitherto unsophisticated computer users. They promise on-line commerce, audio and video entertainment on demand, and a much improved quality of communication between ordinary people.For the moment, the Internet experience is severely compromised by the low speed of networks that reach into our homes. That will change as cable television providers, regional telephone companies and others compete to bring about a two or three order of magnitude increase in the speed of network access.
Clocking Arbitrarily Large Computing Structures Under Constant Skew Bound
Authors: A. El-Amawy
Venue: IEEE Transactions on Parallel and Distributed Systems (1993)

A scheme for global synchronization of arbitrarily large computing structures such thatclock skew between any two communicating cells is bounded above by a constant isdescribed. The scheme utilizes clock nodes that perform simple processing on clocksignals to maintain a constant skew bound irrespective of the size of the computingstructure. Among the salient features of the scheme is the interdependence betweennetwork topology, skew upper bound, and maximum clocking rate achievable. A 2-D mesh framework is used to present the concepts, introduce three network designs, and toprove some basic results. For each network the (constant) upper bound on clock skewbetween any two communicating processors, is established, and its independence ofnetwork size is shown. Simulations were carried out to verify correctness and to checkthe workability of the scheme. A 4*4 network was built and successfully tested forstability. Such issues as node design, clocking of nonplanar structures such ashypercubes, and the concept of fuse programmed clock networks are addressed.
Interrupts: Just a Minute Never Is
Authors: Rini van Solingen, Egon Berghout, Frank van Latum
Venue: IEEE Software (1998)

Software development is a highly abstract process that requires intense concentration. The authors show that interrupting this process can significantly reduce a developer's efficiency and can even contribute to project delays.
Mobile Computing and Databases-A Survey
Authors: Daniel Barbará
Venue: IEEE Transactions on Knowledge and Data Engineering (1999)

The emergence of powerful portable computers, along with advances in wireless communication technologies, has made mobile computing a reality. Among the applications that are finding their way to the market of mobile computing¿those that involve data management¿hold a prominent position. In the past few years, there has been a tremendous surge of research in the area of data management in mobile computing. This research has produced interesting results in areas such as data dissemination over limited bandwidth channels, location-dependent querying of data, and advanced interfaces for mobile computers. This paper is an effort to survey these techniques and to classify this research in a few broad areas.
Business-Driven Product Planning Using Feature Vectors and Increments
Authors: Brian Nejmeh, Ian Thomas
Venue: IEEE Software (2002)

Agile development processes emphasize prioritizing product features, but most don't tell you how to do it. Based on notions of feature vectors, feature levels, and release increments, this product-planning method takes a business-oriented approach to feature selection. Central to the method is a decision framework within which business managers can assess combinations of features, time, and costs to choose those that deliver the highest return on development investment.
On Binary Resilient Functions
Authors: Xiang-Dong Hou
Venue: Designs, Codes and Cryptography (2003)

Using a lifting formula for the coefficients of Boolean functions, we characterize binary resilient functions as binary matrices with certain row or column intersection properties. We give some new constructions of binary resilient functions based on this characterization. In particular, we show that the incidence matrix of a Steiner system can be used to construct binary resilient functions.