ppxscal/embedding_network huggingface dataset:
Simulation and Analysis of FC Network
Authors: Chao-Yang Wang, Feng Zhou, Yao-Long Zhu, Chong Tow Chong, Bo Hou, Wei-Ya Xi
Venue: Proceedings of the 28th Annual IEEE International Conference on Local Computer Networks (2003)

The modeling and simulation are the flexible and effectivemethods to design and evaluate FC-SAN. We studythe impact of link failure on performance of FC networkwith a core/edge topology using SANSim, a simulationtool for storage area network. Simulation results showthat the maximum network throughputs are reduced to50% in the worst case with one network link failure evenin the full redundant FC network design. The results alsoshow that the network performance is sensitive to the locationof failure.
Using Program Transformation to Secure C Programs Against Buffer Overflows
Authors: Christopher Dahn, Spiros Mancoridis
Venue: Proceedings of the 10th Working Conference on Reverse Engineering (2003)

Buffer overflows are the most common source of securityvulnerabilities in C programs. This class of vulnerability,which is found in both legacy and modern software, coststhe software industry hundreds of millions of dollars peryear.The most common type of buffer overflow is the run-timestack overflow. It is common because programmersoften use stack allocated arrays. This enables the attackerto change a program's control flow by writing beyond theboundary of an array onto a return address on the run-timestack. If the arrays are repositioned to the heap at compiletime, none of these attacks succeed. Furthermore, repositioningbuffers to the heap should perturb the heap memoryenough to prevent many heap overflows as well.We have created a tool called Gemini that repositionsstack allocated arrays at compile time using TXL. Thetransformation preserves the semantics of the program witha small performance penalty. This paper discusses thesemantics-preserving transformation of stack allocated arraysto heap allocated "pointers to arrays". A program thatis amenable to a buffer overflow attack and several Linuxprograms are used as examples to demonstrate the effectivenessand overhead of our technique.
Image reducing words and subgroups of free groups
Authors: D. S. Ananichev, A. Cherubini, M. V. Volkov
Venue: Theoretical Computer Science (2003)

A word w over a finite alphabet Σ is said to be n-collapsing if for an arbitrary finite automaton A = 〈Q,Σ_._〉, the inequality |Q ċ w| ≤ |Q|- n holds provided that |Q ċ u| ≤ |Q|- n for some word u (depending on A). We give an algorithm to test whether a word is 2-collapsing. To this aim we associate to every word w a finite family of finitely generated subgroups in finitely generated free groups and prove that the property of being 2-collapsing reflects in the property that each of these subgroups has index at most 2 in the corresponding free group. We also find a similar characterization for the closely related class of so-called 2-synchronizing words.
Solving the XOR problem and the detection of symmetry using a single complex-valued neuron
Authors: Tohru Nitta
Venue: Neural Networks (2003)

This letter presents some results on the computational power of complex-valued neurons. The main results may be summarized as follows. The XOR problem and the detection of symmetry problem which cannot be solved with a single real-valued neuron (i.e. a two-layered real-valued neural network), can be solved with a single complex-valued neuron (i.e. a two-layered complex-valued neural network) with the orthogonal decision boundaries, which reveals the potent computational power of complex-valued neurons. Furthermore, the fading equalization problem can be successfully solved with a single complex-valued neuron with the highest generalization ability.
The composite element method applied to free vibration analysis of trusses and beams
Authors: Marcos Arndt, Roberto Dalledone Machado, Mildred Ballin Hecke
Venue: Applied Numerical Mathematics (2003)

This work deals with an enrichment technique of the finite element solution to the free vibration problems, called the composite element method [J. Sound Vibration 218 (1998) 619, 659, Key Engrg. Mater. 145-149 (1998) 773]. The enrichment of the solution space is obtained combining the FEM and the high accuracy of closed form solutions from the classical theory. The analytical solutions must be in accordance with some special boundary conditions in such a way they do not change the nodal values of FEM and, also, they must be the solutions to the frequency equation. The CEM can be improved using two types of approach: h and c-versions. The h-version, the same as FEM, consists of the refinement of the element mesh. The c-version is the increase of degrees of freedom related to the classical theory. Truss and beams elements are used in order to verify the numerical efficiency of the CEM. Some examples are presented and the frequencies and mode shapes of vibration obtained by CEM are compared with the FEM solution, and also the classical theory. The numerical results have shown that CEM is more accurate than FEM with the same number of total degrees of freedom. The CEM is also more accurate to determine higher frequencies than the FEM, except for the last ones. The results suggest that, for higher frequencies, numerical instabilities are presented.
Extension of spatial metadata and agent-based spatial Data navigation mechanism
Authors: Yingwei Luo, Xiaolin Wang, Zhuoqun Xu
Venue: Proceedings of the 11th ACM international symposium on Advances in geographic information systems (2003)

Fast navigation to distributed spatial data has been the keystone of distributed GIS. In this paper, a hierarchical spatial metadata Database framework is presented based on the existing spatial metadata standard. This framework can efficiently organize the distributed spatial data in network. With the support of the hierarchical spatial metadata Databases, a user-oriented descriptive specification for spatial data requirement is proposed. A map (map-layer) is described as a tuple consisting of four basic elements of <subject, scope, stratum, time>. An agent-based searching scheme for spatial query is also introduced, which can satisfy the requirement of fast navigation in terms of spatial query that can often be non-deterministic or with uncertainty.
An inequality for polymatroid functions and its applications
Authors: E. Boros, K. Elbassioni, V. Gurvich, L. Khachiyan
Venue: Discrete Applied Mathematics (2003)

An integral-valued set function f:2v ↦ Z is called polymatroid if it is submodular, nondecreasing, and f(φ) = 0. Given a polymatroid function f and an integer threshold t ≥ 1, let α = α(f,t) denote the number of maximal sets X ⊆ V satisfying f(X) < t, let β = β(f,t) be the number of minimal sets X ⊆ V for which f(X) ≥ t, and let n = |V|. We show that if β ≥ 2 then α ≤ β(log t)/c, where c = c(n,β) is the unique positive root of the equation 1 = 2c(nc/log β - 1). In particular, our bound implies that α ≤ (nβ)log t for all β ≥ 1. We also give examples of polymatroid functions with arbitrarily large t, n, α and β for which α ≥ β(0.551 log t)/c. More generally, given a polymatroid function f : 2v ↦ Z and an integral threshold t ≥ 1, consider an arbitrary hypergraph H' such that |H'| ≥ 2 and f(H) ≥ t for all H ∈ H'. Let f' be the family of all maximal independent sets X of H' for which f(X) < t. Then |f'| ≤ |H'|(log t)/c(n,|H'|). As an application, we show that given a system of polymatroid inequalities f1(X) ≥ t1,..., fm(X) ≥ tm with quasi-polynomially bounded right-hand sides t1,....,tm, all minimal feasible solutions to this system can be generated in incremental quasi-polynomial time. In contrast to this result, the generation of all maximal infeasible sets is an NP-hard problem for many polymatroid inequalities of small range.
Achieving organizational IT goals through integrating the balanced scorecard and software measurement frameworks
Authors: Nancy Eickelmann
Venue: Technologies & methodologies for evaluating information technology in business (2003)

Provided in this chapter is an integrated measurement system that links the organization's strategic goals with the operational and tactical directives for information technology (IT) projects. The measurement system consists of the Balanced Scorecard (BSC); Software Engineering Institute, Capability Maturity Model (SEI/ CMM); and the International Standard Organization (ISO/IEC- 9126) for information technology measurement of software quality. The integration of these measurement frameworks provides the necessary multitier granularity of measures to successfully predict and assess organizational performance relative to IT investments.
Tree-adjoining grammar parsing and boolean matrix multiplication
Authors: Giorgio Satta
Venue: Computational Linguistics (1994)

The computational problem of parsing a sentence in a tree-adjoining language is investigated. An interesting relation is studied between this problem and the well-known computational problem of Boolean matrix multiplication: it is shown that any algorithm for the solution of the former problem can easily be converted into an algorithm for the solution of the latter problem. This result bears on at least two important computational issues. First, we realize that a straightforward method that improves the known upper bound for tree-adjoining grammar parsing is hard to find. Second, we understand which features of the tree-adjoining grammar parsing problem are responsible for the claimed difficulty.
Hardware Support for Control Transfers in Code Caches
Authors: Ho-Seop Kim, James E. Smith
Venue: Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture (2003)

Many dynamic optimization and/or binary translationsystems hold optimized/translated superblocks in a codecache. Conventional code caching systems suffer fromoverheads when control is transferred from one cachedsuperblock to another, especially via register-indirectjumps. The basic problem is that instruction addresses inthe code cache are different from those in the original programbinary. Therefore, performance for register-indirectjumps depends on the ability to translate efficiently fromsource binary PC values to code cache PC values.We analyze several key aspects of superblock chainingand find that a conventional baseline code cache withsoftware jump target prediction results in 14.6% IPC lossversus the original binary. We identify the inability to usea conventional return address stack as the most significantperformance limiter in code cache systems. We introduce amodified software prediction technique that reduces theIPC loss to 11.4%. This technique is based on a techniqueused in threaded code interpreters.A number of hardware mechanisms, including a specializedreturn address stack and a hardware cache fortranslated jump target addresses, are studied for efficientlysupporting register-indirect jumps. Once all the chainingoverheads are removed by these support mechanisms, asuperblock-based code cache improves performance due toa better branch prediction rate, improved I-cache locality,and increased chances of straight-line fetches. Simulationresults show a 7.7% IPC improvement over a current generation4-way superscalar processor.
Dynamic Weighted Majority: A New Ensemble Method for Tracking Concept Drift
Authors: Jeremy Z. Kolter, Marcus A. Maloof
Venue: Proceedings of the Third IEEE International Conference on Data Mining (2003)

Algorithms for tracking concept drift are important formany applications. We present a general method basedon the Weighted Majority algorithm for using any on-linelearner for concept drift. Dynamic Weighted Majority(DWM) maintains an ensemble of base learners, predictsusing a weighted-majority vote of these "experts",and dynamically creates and deletes experts in response tochanges in performance. We empirically evaluated two experimentalsystems based on the method using incrementalnaive Bayes and Incremental Tree Inducer (ITI) as experts.For the sake of comparison, we also included Blum's implementationof Weighted Majority. On the STAGGER Conceptsand on the SEA Concepts, results suggest that the ensemblemethod learns drifting concepts almost as well as the basealgorithms learn each concept individually. Indeed, we reportthe best overall results for these problems to date.
Formal sizing rules of CMOS circuits
Authors: D. Auvergne, N. Azemard, V. Bonzom, D. Deschacht, M. Robert
Venue: Proceedings of the conference on European design automation (1991)

In this paper we present a local strategy for sizing CMOS circuits. We show how the explicit definition of delays can be used to define delay/area optimal sizing rules. Examples are given for sizing irregular inverter arrays, NAND gates and adder cells, starting from an initial electrical netlist and ending with the fully automatically generated layout. Direct comparisons of speed / area performances are given for a linear matrix style layout implementation.
Fast spherical Fourier algorithms
Authors: Stefan Kunis, Daniel Potts
Venue: Journal of Computational and Applied Mathematics (2003)

Spherical Fourier series play an important role in many applications. A numerically stable fast transform analogous to the fast Fourier transform is of great interest. For a standard grid of O(N2) points on the sphere, a direct calculation has computational complexity of O(N4), but a simple separation of variables reduces the complexity to O(N3). Here we improve well-known fast algorithms for the discrete spherical Fourier transform with a computational complexity of O(N2 log2 N). Furthermore we present, for the first time, a fast algorithm for scattered data on the sphere. For arbitrary O(N2) points on the sphere, a direct calculation has a computational Complexity of O(N4), but we present an approximate algorithm with a computational complexity of O(N2 log2 N).
Simplified time series representations for efficient analysis of industrial process data
Authors: Esa Alhoniemi
Venue: Artificial Intelligence for Engineering Design, Analysis and Manufacturing (2003)

The data storage capacities of modern process automation systems have grown rapidly. Nowadays, the systems are able to frequently carry out even hundreds of measurements in parallel and store them in databases. However, these data are still rarely used in the analysis of processes. In this article, preparation of the raw data for further analysis is considered using feature extraction from signals by piecewise linear modeling. Prior to modeling, a preprocessing phase that removes some artifacts from the data is suggested. Because optimal models are computationally infeasible, fast heuristic algorithms must be utilized. Outlines for the optimal and some fast heuristic algorithms with modifications required by the preprocessing are given. In order to illustrate utilization of the features, a process diagnostics framework is presented. Among a large number of signals, the procedure finds the ones that best explain the observed short-term fluctuations in one signal. In the experiments, the piecewise linear modeling algorithms are compared using a massive data set from an operational paper machine. The use of piecewise linear representations in the analysis of changes in one real process measurement signal is demonstrated.
A new hardware algorithm for fast IP routing targeting programmable routers
Authors: Mahmoud Meribout, Massato Motomura
Venue: Network control and engineering for Qos, security and mobility II (2003)

While deployment of embedded and distributed network services imposes new demands for flexibility and programmability, IP address lookup has become significant performance bottleneck for the highest performance routers. Amid their vast array of academic and commercial solutions to the problem, few achieve a favorable balance of performance, efficiency, and cost. New commercial products utilize Content Addressable Memory (CAM) devices that achieve high lookup speeds and an exorbitantly high hardware cost with limited flexibility. In this paper a new IP forwarding hardware algorithm, based on gray-code encoding, along with its dedicated scalable lookup engine is proposed. The corresponding programmable router is able to achieve high performance with the use of a small portion of Dynamic Reconfigurable Logic (DRL) device and a commodity Random Access Memory (RAM) logic. Experimental evaluation using Ns2 simulator and a small routing table from Mae West [1] has been conducted. The results show that the programmable router can be scaled to achieve guaranteed worst-case performance of over 66 million lookups per second with a single SRAM operation at the fairly clock of 100 MHz.
Flowcharting by stepwise refinement
Authors: O. Ferstl
Venue: ACM SIGPLAN Notices (1978)

This paper describes a flowchart technique, which supports the method of program development by stepwise refinement.Flowcharts made by this technique have a tree structure, which simplifies program test and coding the chart into a programming language. For design of the overall control structure the basic forms concatenation, selection, repetition and restricted GOTO statements are available.
Bayesian Robot Programming
Authors: Olivier Lebeltel, Pierre Bessière, Julien Diard, Emmanuel Mazer
Venue: Autonomous Robots (2004)

We propose a new method to program robots based on Bayesian inference and learning. It is called BRP for Bayesian Robot Programming. The capacities of this programming method are demonstrated through a succession of increasingly complex experiments. Starting from the learning of simple reactive behaviors, we present instances of behavior combination, sensor fusion, hierarchical behavior composition, situation recognition and temporal sequencing. This series of experiments comprises the steps in the incremental development of a complex robot program. The advantages and drawbacks of BRP are discussed along with these different experiments and summed up as a conclusion. These different robotics programs may be seen as an illustration of probabilistic programming applicable whenever one must deal with problems based on uncertain or incomplete knowledge. The scope of possible applications is obviously much broader than robotics.
Low Cost Analog Testing of RF Signal Paths
Authors: Marcelo Negreiros, Luigi Carro, Altamiro A. Susin
Venue: Proceedings of the conference on Design, automation and test in Europe - Volume 1 (2004)

A low cost method for testing analog RF signal paths suitable for BIST implementation in a SoC environment is described. The method is based on the use of a simple and low-cost one-bit digitizer that enables the reuse of processor and memory resources available in the SoC, while incurring little analog area overhead. The proposed method also allows a constant load to be observed by the circuit, since no switches or muxes are needed for digitizing specific test points. Mathematical background and experimental results are presented in order to validate the test approach.
Hierarchical topical segmentation in instructional films based on cinematic expressive functions
Authors: Dinh Q. Phung, Svetha Venkatesh, Chitra Dorai
Venue: Proceedings of the eleventh ACM international conference on Multimedia (2003)

In this paper, we propose a novel solution for segmenting an instructional video into hierarchical topical sections. Incorporating the knowledge of education-oriented film theory with our previous study of expressive functions namely the content density and the thematic functions, we develop an algorithm to effectively structuralize an instructional video into a two-tiered hierarchy of topical sections at the main and sub-topic levels. Our experimental results on a set of ten industrial instructional videos demonstrate the validity of the detection scheme.
The Immersive Visualization Probe for Exploring n-Dimensional Spaces
Authors: James R. Miller, Estela A. Gavosto
Venue: IEEE Computer Graphics and Applications (2004)

A new tool uses two types of dimensional navigation to display continuous 4D subsets of n-dimensional data. Thanks to the tool's embedded coordinate systems, researchers can better understand a model's underlying physical or mathematical process.
Process and Product Improvement in Manufacturing Systems with Correlated Stages
Authors: Paul F. Zantek, Gordon P. Wright, Robert D. Plante
Venue: Management Science (2002)

Manufacturing systems typically contain processing and assembly stages whose output quality is significantly affected by the output quality of preceding stages in the system. This study offers and empirically validates a procedure for (1) measuring the effect of each stage's performance on the output quality of subsequent stages including the quality of the signal product, and (2) identifying stages in a manufacturing system where management should concentrate investments in process quality improvement. Our proposed procedure builds on the precedence ordering of the stages in the system and uses the information provided by correlations between the product quality measurements across stages.The starting point of our procedure is acomputer executable network representation of the statistical relationships between the product quality measurements; execution automatically converts the network to a simultaneous-equations model and estimates the model parameters by the method of least squares. The parameter estimates are used to measure and rank the impact of each stage's performance on variability in intermediate stage and final product quality. We extend our work by presenting an economic model, which uses these results, to guide management in deciding on the amount of investment in process quality improvement for each stage.We report some of the findings from an extensive empirical validation of our procedure using circuit board production line data from a major electronics manufacturer. The empirical evidence presented here highlights the importance of accounting for quality linkages across stages in (a) identifying the sources of variation in product quality and (b) allocating investments in process quality improvement.
The mindful camera: common sense for documentary videography
Authors: Barbara Barry
Venue: Proceedings of the eleventh ACM international conference on Multimedia (2003)

Cameras with story understanding can help videographers reflect on their process of content capture during documentary construction. This paper describes a set of tools that use common sense knowledge to support documentary videography.
Equalities among Capacities of (d,k)-Constrained Systems
Authors: Navin Kashyap, Paul H. Siegel
Venue: SIAM Journal on Discrete Mathematics (2004)

In this paper, we consider the problem of determining when the capacities of distinct (d,k)-constrained systems can be equal. A (d,k)-constrained system consists of binary sequences which have at least d zeros and at most k zeros between any two successive ones. If we let C(d,k) denote the capacity of a (d,k)-constrained system, then it is known that C(d,2d) = C(d+1,3d+1) and C(d,2d+1) = C(d+1,\infty)$. Repeated application of these two identities also yields the chain of equalities C(1,2) = C(2,4) = C(3,7) = C(4,\infty)$. We show that these are the only equalities possible among the capacities of (d,k)-constrained systems. In the process, we also provide useful factorizations of the characteristic polynomials for these constraints.
Using BDDs and ZBDDs for Efficient Identification of Testable Path Delay Faults
Authors: Saravanan Padmanaban, Spyros Tragoudas
Venue: Proceedings of the conference on Design, automation and test in Europe - Volume 1 (2004)

We present a novel framework to identify all the robustly testable and untestable path delay faults in a circuit. The method uses a combination of decision diagrams for manipulatingpath delay faults and boolean functions. The approach bene.ts from processing partial paths or fanout free segments in the circuit rather than the entire path. The effectiveness of the proposed framework is demonstrated experimentally. It is observed that the methodology identifies 350% more testable faults in the ISCAS'85 benchmark C6288 than any existing technique by utilizing only a fraction of the time compared to earlier work.