ppxscal/embedding_network huggingface dataset:
(Almost) Optimal parallel block access for range queries
Authors: Mikhail J. Atallah, Sunil Prabhakar
Venue: Information Sciences&mdash;Informatics and Computer Science: An International Journal (2003)

Range queries are an important class of queries for several applications can be achieved by tiling the multi-dimensional data and distributing it among multiple disks or nodes. It has been established that schemes that achieve optimal parallel block access exist only for a few special cases. Though several schemes for the allocation of tiles to disks have been developed, no scheme with non-trivial worst-case bound is known. We establish that any range query on a 2q × 2q-block grid of blocks can be performed using k = 2t disks (t ≤ q), in at most ⌈m/k⌉ + O(logk) parallel block accesses. We achieve this result by judiciously distributing the blocks among the k nodes or disks. Experimental data show that the algorithm achieves very close to ⌈m/k⌉ performance (on average less than 0.5 away from ⌈m/k⌉, with a worst-case of 3). Although several declustering schemes for range queries have been developed, prior to our work no additive non-trivial performance bounds were known. Our scheme guarantees performance within a (small) additive deviation from ⌈m/k⌉. Subsequent to this work, Bhatia et al. [Hierarchical declustering schemes for range queries, in: Proceedings of International Conference on Extending Database Technology, Konstanz, Germany, March 2000, p. 525] have proved that such a performance bound is essentially optimal for this kind of scheme, and have also extended our results to the case where the number of disks is a product of the form k1 * k2 * ... * kt where the kis need not all be 2.
Design synthesis knowledge and inductive machine learning
Authors: S. Potter, M. J. Darlington, S. J. Culley, P. K. Chawdhry
Venue: Artificial Intelligence for Engineering Design, Analysis and Manufacturing (2001)

A crucial early stage in the engineering design process is the conceptual design phase, during which an initial solution design is generated. The quality of this initial design has a great bearing on the quality and success of the produced artefact. Typically, the knowledge required to perform this task is only acquired through many years of experience, and so is often at a premium. This has led to a number of attempts to automate this phase using intelligent computer systems. However, the knowledge of how to generate designs has proved difficult to acquire directly from human experts, and as a result, is often unsatisfactory in these systems. The application of inductive machine learning techniques to the acquisition of this sort of knowledge has been advocated as one approach to overcoming the difficulties surrounding its capture. Rather than acquiring the knowledge from human experts, the knowledge would be inferred automatically from a set of examples of the design process. This paper describes the authors' investigations into the general viability of this approach in the context of one particular conceptual design task, that of the design of fluid power circuits. The analysis of a series of experiments highlights a number of issues that would seem to arise regardless of the working domain or particular machine learning algorithm used. These issues, presented and discussed here, cast serious doubts upon the practicality of such an approach to knowledge acquisition, given the current state of the art.
Increasing Inspection Efficiency through Group Support Systems
Venue: Proceedings of the Proceedings of the 37th Annual Hawaii International Conference on System Sciences (HICSS'04) - Track 1 - Volume 1 (2004)

Previous research has found that that software inspection teams that use group support systems (GSS) are more effective and efficient in finding defects than inspection teams using the traditional paper logging method. In an earlier study, GSS-supported teams found forty percent more major defects and forty percent more defects per inspection hour. This paper extends previous research by examining the underlying factors that led to these improvements. This study found two major contributing factors: 1) greater attention focused on finding defects for both inspectors and moderators, and 2) greater adherence to target preparation rates overtime. Both factors significantly improve inspections efficiency and effectiveness.
Aggregation-based feature invention and relational concept classes
Authors: Claudia Perlich, Foster Provost
Venue: Proceedings of the ninth ACM SIGKDD international conference on Knowledge discovery and data mining (2003)

Model induction from relational data requires aggregation of the values of attributes of related entities. This paper makes three contributions to the study of relational learning. (1) It presents a hierarchy of relational concepts of increasing complexity, using relational schema characteristics such as cardinality, and derives classes of aggregation operators that are needed to learn these concepts. (2) Expanding one level of the hierarchy, it introduces new aggregation operators that model the distributions of the values to be aggregated and (for classification problems) the differences in these distributions by class. (3) It demonstrates empirically on a noisy business domain that more-complex aggregation methods can increase generalization performance. Constructing features using target-dependent aggregations can transform relational prediction tasks so that well-understood feature-vector-based modeling algorithms can be applied successfully.
Exact Inference Using Variable Integrating Constant ImportanceDistributions
Authors: Charles J. Romeo, Teruo Nakatsuma
Venue: Computational Economics (2004)

In this paper a new class of importance distributions that are based on normal and t-distributions are introduced. They are labeled variable integrating constant distributions or VIC distributions. The main innovation in this class of distributions is that the standard error associated with each prameter is expanded in an exponential polynomial function of the scaled distance from its mode, with a different polynomial used in each direction and for each parameter. Resulting variances differ at each point in the parameter space, thereby breaking the flexibility limitations that are inherent in normal and t-distributions allowing them to be closely matched to the posterior distribution whose moments are the goal of the inference exercise. Two illustrations are presented in which the performance of normal, t, normal-VIC, and t-VIC importance distributions are compared. Results show the VIC distributions to produce globally stable weights and substantial improvements in the numerical efficiency of importance sampling and independence Metropolis estimates.
Atomic scale defects involved in MOS reliability problems
Authors: P. M. Lenahan
Venue: Microelectronic Engineering (2003)

For quite some time, it has been known that two types of silicon dangling bond centers play important roles in metal-oxide-silicon reliability problems. Silicon dangling bonds at the Si/SiO2 boundary defects (called Pb centers) dominate Si/SiO2 interface trapping. Silicon dangling bond defects (called E' centers) dominate deep levels in the oxide. Recent observations provide a more detailed understanding of the relationship between the structure and electronic properties of the Pb interface centers. Recent work also helps explain the frequently noted correlation between oxide deep level defects and Si/SiO2 interface trap defects.
Optimal Schwarz Waveform Relaxation for the One Dimensional Wave Equation
Authors: Martin J. Gander, Laurence Halpern, Frédéric Nataf
Venue: SIAM Journal on Numerical Analysis (2003)

We introduce a nonoverlapping variant of the Schwarz waveform relaxation algorithm for wave propagation problems with variable coefficients in one spatial dimension. We derive transmission conditions which lead to convergence of the algorithm in a number of iterations equal to the number of subdomains, independently of the length of the time interval. These optimal transmission conditions are in general nonlocal, but we show that the nonlocality depends on the time interval under consideration, and we introduce time windows to obtain optimal performance of the algorithm with local transmission conditions in the case of piecewise constant wave speed. We show that convergence in two iterations can be achieved independently of the number of subdomains in that case. The algorithm thus scales optimally with the number of subdomains, provided the time windows are chosen appropriately. For continuously varying coefficients we prove convergence of the algorithm with local transmission conditions using energy estimates. We then introduce a finite volume discretization which permits computations on nonmatching grids, and we prove convergence of the fully discrete Schwarz waveform relaxation algorithm. We finally illustrate our analysis with numerical experiments.
A Structural Approach to the Model Generalization of an Urban Street Network
Authors: B. Jiang, C. Claramunt
Venue: Geoinformatica (2004)

This paper proposes a novel generalization model for selecting characteristic streets in an urban street network. This model retains the central structure of a street network. It relies on a structural representation of a street network using graph principles where vertices represent named streets and links represent street intersections. Based on this representation, so-called connectivity graph, centrality measures are introduced to qualify the status of each individual vertex within the graph. We show that these measures can be used for characterizing the structural properties of an urban street network, and for the selection of important streets. The proposed approach is validated by a case study applied to a middle-sized Swedish city.
An Area-Efficient Pipelined Array Architecture for Euclidean Distance Transformation and Its FPGA Implementation
Authors: N. Sudha
Venue: Proceedings of the 17th International Conference on VLSI Design (2004)

The Euclidean Distance Transform (EDT) is an importanttool in image analysis and machine vision.This paper provides an area-efficient hardware solutionto the computation of EDT on a binary image.An O(n) hardware algorithm for computing EDT OF ANn × n image is presented.A pipelined 2-D array architecturefor harware implementation is designed.Thearchitecture has a regular structure with locally connectedidentical processing elements.Furthermore, pipeliningreduces hardware resources.Results of FPGA-basedimplementation shows that the hardware can processabout 6000 images of size 512 × 512 per second whichis much higher than the video rate of 30 frames per second.
Identification of Experimental Trends by the L&khgr;-Transformation Methods
Authors: L. G. Sobolev
Venue: Automation and Remote Control (2004)

Identification of experimental trends by the integral L&khgr;-transformation (the generalization of Carson transformation) methods is investigated. Identification algorithms for determining the analytical expression of trend are designed. Examples are given.
The design and implementation of the cortex visualization system
Authors: Deb Banerjee, Chris Morley, Wayne Smith
Venue: Proceedings of the conference on Visualization '94 (1994)

Cortex has been designed for interactive analysis and display of simulation data generated by CFD applications based on unstructured-grid solvers. Unlike post-processing visualization environments, Cortex is designed to work in co-processing mode with the CFD application. This significantly reduces data storage and data movement requirements for visualization and also allows users to interactively steer the application. Further, Cortex supports high-performance by running on massively parallel computers and workstation clusters.An important goal for Cortex is to provide visualization to a variety of solvers which differ in their solution methodologies and supported flow models. Coupled with the co-processing requirement, this has required the development of a well defined programming interface to the CFD solver that lets the the visualization system communicate efficiently with the solver, and requires minimal programming effort for porting to new solvers. Further, the requirement for targeting multiple solvers and application niches demands that the visualization system be rapidly and easily modifiable. Such flexibility is attained in Cortex by using the high-level, interpreted language Scheme for implementing user-interfaces and high-level visualization functions. By making the Scheme interpreter available from the Cortex text interface, the user can also customize and extend the visualization system.
Interpolated mappings for musical instruments
Authors: Camille Goudeseune
Venue: Organised Sound (2002)

Software-based musical instruments have controls for input, a sound synthesizer for output, and mappings connecting the two. An effective layout of controls considers how many degrees of freedom each has, as well as the overhead of selecting each one while performing. An isolated mapping from one control to one synthesis parameter needs an appropriate choice of proportional, integral or derivative control (the control's value, or that value's rate of change, drives the synthesis parameter's value, or that value's rate of change). Beyond this, a compound mapping cross-coupling several controls and synthesis parameters can surprisingly increase the performer's intuitive understanding of the instrument.
Comparing and improving centralized and distributed techniques for coordinating massively parallel shared-memory systems
Authors: Allan Gottlieb
Venue:  (2003)

Two complementary approaches have been proposed to achieve high performance inter-process coordination on highly parallel shared-memory systems. Gottlieb et. al. introduced the technique of combining concurrent memory references, thereby reducing hot spot contention and enabling the &ldquo;bottleneck-free&rdquo; execution of algorithms referencing a small number of shared variables. Mellor-Crummey and Scott introduced an alternative &ldquo;distributed local-spin&rdquo; technique that minimizes hot spot contention by not polling hotspot variables and exploiting the availability of processor-local shared memory. My principal contributions are a comparison of these two approaches, and significant improvements to the former. The NYU Ultra3 prototype is the only system built that implements memory reference combining. My research utilizes micro-benchmark simulation studies of massively parallel Ultra3 systems executing coordination algorithms. This investigation detects problems in the Ultra3 design that result in higher-than-expected memory latency for reference patterns typical of busy-wait polling. This causes centralized coordination algorithms to perform poorly. Several architectural enhancements are described that significantly reduce the latency of these access patterns, thereby improving the performance of the centralized algorithms. I investigate existing centralized algorithms for readers-writers and barrier co-ordination, all of which require fetch-and-add, and discovered variants that require fewer memory accesses (and hence have shorter latency). In addition, my evaluation includes novel algorithms that; require only a restricted form of fetch-and-add. Coordination latency of these algorithms executed on the enhanced combining architecture is compared to the latency of the distributed local-spin alternatives. These comparisons indicate that the distributed local-spin &ldquo;dissemination&rdquo; barrier, which generates no hot spot traffic, has latency slightly inferior to the best centralized algorithms investigated. However, for the less structured readers-writers problem, the centralized algorithms significantly outperform the distributed local-spin algorithm.
Decidability of bounded second order unification
Authors: Manfred Schmidt-Schauß
Venue: Information and Computation (2004)

It is well-known that first order unification is decidable, whereas second order (and higher order) unification is undecidable. Bounded second order unification is second order unification under the restriction that only a bounded number of bound variables in the instantiating terms for second order variables is permitted, however, the size of the instantiation is not restricted. In this paper, a decision algorithm for bounded second order unification is described. This is the first nontrivial decidability result for second order unification, where the signature is not restricted and there are no restrictions on the occurrences of variables. This supports the claim that bounded second order unification is easier than context unification, whose decidability is currently an open question.
Automatic Tuning of Two-Level Caches to Embedded Applications
Authors: Ann Gordon-Ross, Frank Vahid, Nikil Dutt
Venue: Proceedings of the conference on Design, automation and test in Europe - Volume 1 (2004)

The power consumed by the memory hierarchy of a microprocessor can contribute to as much as 50% of the total microprocessor system power, and is thus a good candidate for optimizations. We present an automated method for tuning two-level caches to embedded applications for reduced energy consumption. The method is applicable to both a simulation-based exploration environment and a hardware-based system prototyping environment. We introduce the two-level cache tuner, or TCaT - a heuristic for searching the huge solution space of possible configurations. The heuristic interlaces the exploration of the two cache levels and searches the various cache parameters in a specific order based on their impact on energy. We show the integrity of our heuristic across multiple memory configurations and even in the presence of hardware/software partitioning -- a common optimization capable of achieving significant speedups and/or reduced energy consumption. We apply our exploration heuristic to a large set of embedded applications. Our experiments demonstrate the efficacy of our heuristic: on average the heuristic examines only 7% of the possible cache configurations, but results in cache sub-system energy savings of 53%, only 1% more than the optimal cache configuration. In addition, the configured cache achieves an average speedup of 30% over the base cache configuration due to tuning of cache line size to the application's needs.
Temporal interaction diagrams for multi-process environments
Authors: T. Y. Chen, Iyad Rahwan, Yun Yang
Venue: Practicing software engineering in the 21st century (2003)

This chapter introduces a novel notion of temporal interaction diagrams for distributed and parallel programming. An interaction diagram is a graphical view of computation processes and communication between different entities in distributed and parallel processes. It can be used for the specification, implementation and testing of interaction policies in distributed and parallel systems. Expressing interaction diagrams in a linear form, known as fragmentation, facilitate automation of design and testing of such systems. Existing interaction diagram formalisms lack the flexibility and capability of describing more general temporal order constraints. They only support rigid temporal order, and, hence, have limited semantic expressiveness. We propose an improved interaction diagram formalism in which more general temporal constraints can be expressed. This enables us to capture multiple valid interaction sequences using a single interaction diagram.
Compositional Memory Systems for Data Intensive Applications
Authors: A. M. Molnos, M. J. M. Heijligers, S. D. Cotofana, J. T. J. van Eijndhoven
Venue: Proceedings of the conference on Design, automation and test in Europe - Volume 1 (2004)

To alleviate the system performance unpredictability of multitasking applications running on multiprocessor platforms with shared memory hierarchies we propose a task level set based cache partitioning. We evaluate our approach on a CAKE platformwith three Trimedias, one MIPS and a shared level 2 cache using a picture in picture benchmark. We compare the performance implications of two types of cache partitioning namely set based. Our experimentsindicates that associativity based cache partitioning induces at least 30% performance degradation, whereas set-based partitioning provide 27% performance improvement when compared to non-partitioned cache scenario.
Reducing the Technical Complexity and Business Risk of Major Systems Projects
Authors: Alan Thorogood, Philip Yetton
Venue: Proceedings of the Proceedings of the 37th Annual Hawaii International Conference on System Sciences (HICSS'04) - Track 8 - Volume 8 (2004)

Shared IT infrastructure achieves returns to scale and facilitates co-ordination. Determining the optimal investment is difficult because demand is derived from business projects that can "free-ride" once the infrastructure is established. Organisations control infrastructure investments by justifying them in business projects that are Net Present Value (NPV) positive, such as business process re-engineering projects. This increases the technical complexity of the business project and misleadingly couples the project's business goals with shared infrastructure goals.Field research uncovered an alternative "deviant" model where a flexible, or agile, infrastructure is installed and justified ahead of the business needs. Those needs were then satisfied with multiple small business application projects, as each became NPV positive. Themanagers' intuition was that this gave them valuable options to capture benefits from uncertain future business scenarios.This paper draws on these insights to uncouple infrastructure projects from business projects while still aligning the two. Real options theory is applied both to control the costs and to specify the infrastructure flexibility. The assumption is that uncoupling would reduce technical complexity and lower business risk. The paper then shows how to improve business performance by using infrastructure flexibility either to suppress the cost variance of the IT projects or to amplify their business benefit variance, as called for by McGrath [1] and Sambamurthy et al. [2]
A DSP56002-based Frequency Response Network Analyzer
Authors: G. Miramontes de León, F. Gómez Aguilera, E. García Domínguez
Venue: Proceedings of the 14th International Conference on Electronics, Communications and Computers (2004)

In this work, a multi-sine DSP-based network analyzeris presented. The system is based on the Motorola'sDSP56002EVM evaluation board and it givesthe ability to measure the frequency response of lineartime-invariant systems. The development of the systemincludes the implementation of a steep descent algorithmfor the generation of a low peak factor multi-sinedriving signal. The DSP board reads back the system's responseat different frequencies and evaluates magnitudeand phase data for plotting and analysis purposes. Futureapplications include analysis, verification and systemidentification projects.
Finding the first K shortest paths in a time-window network
Authors: Yen-Liang Chen, Hsu-Hao Yang
Venue: Computers and Operations Research (2004)

The time-constrained shortest path problem is an important generalization of the classical shortest path problem and has attracted much research interest in recent years. We consider a time-window network, where every node in the network has a list of pre-specified windows and departure from a node may take place only in these window periods. The objective of this paper is to find the first K shortest paths in a time-window network. An algorithm of time complexity of O(Kr|V|3) is developed to find the first K shortest paths, where |V| is the numbers of nodes in the network and r represents the maximum number of windows associated with a node.