ppxscal/embedding_network huggingface dataset:
The effect of sharing on the cache and bus performance of parallel programs
Authors: S. J. Eggers, R. H. Katz
Venue: ACM SIGARCH Computer Architecture News (1989)

Bus bandwidth ultimately limits the performance, and therefore the scale, of bus-based, shared memory multiprocessors. Previous studies have extrapolated from uniprocessor measurements and simulations to estimate the performance of these machines. In this study, we use traces of parallel programs to evaluate the cache and bus performance of shared memory multiprocessors, in which coherency is maintained by a write-invalidate protocol. In particular, we analyze the effect of sharing overhead on cache miss ratio and bus utilization. Our studies show that parallel programs incur substantially higher miss ratios and bus utilization than comparable uniprocessor programs. The sharing component of these metrics proportionally increases with both cache and block size, and for some cache configurations determines both their magnitude and trend. The amount of overhead depends on the memory reference pattern to the shared data. Programs that exhibit good per-processor-locality perform better than those with fine-grain-sharing. This suggests that parallel software writers and better compiler technology can improve program performance through better memory organization of shared data.
A novel algorithm for improving convergence behavior of circuit simulators
Authors: Z. Yu, W. Zhao, Z. Yang, Y. E. Lien
Venue: Proceedings of the 26th ACM/IEEE Design Automation Conference (1989)

A novel algorithm based on the Newton projection scheme [1] is proposed to improve the convergence behavior of circuit simulation. The computation experiment shows that the number of iterations to achieve convergence in Newton-Raphson method can be cut by as much as twenty nine-fold, and the convergence behavior of the Newton iteration is made much more robust using this algorithm. Moreover, the implementation of the proposed algorithm in conventional circuit simulators such as SPICE is very easily done. Both the theoretical background and actual implementation of the algorithm are discussed. The experimental circuit and simulation results are also shown.
Optical reading of voltages on printed circuit boards
Authors: Gérard Tremblay, Paul Meyrueix
Venue: Microelectronic Engineering (1988)

Electro-optic detection has been shown to be a very powerful technique for making measurements of fast electronic devices. In this paper, we show a new technique to test large printed circuit boards. We use a laser beam deflection and no mechanical movement of probes.
An implementation model for reasoning with complex objects
Authors: Qiming Chen, Georges Gardarin
Venue: Proceedings of the 1988 ACM SIGMOD international conference on Management of data (1988)

In this paper, we first propose a natural syntactical extension of DATALOG called NESTED_DATALOG for dealing with complex objects represented as nested predicates. Then, we introduce the token object model which is a simple extension of the relational model with tokens to represent complex objects and support referential information sharing. An implementation model of a NESTED_DATALOG program is defined by mapping it to the token object model which remains a straightforward extension of classical logical databases. Through this work, we can accommodate two basic requirements. The availability of a rule language for reasoning with complex objects, and the mechanism for mapping a complex object rule program to a relational DBMS offering a pure DATALOG rule language. In summary, the main contributions of the paper are the definition of a rule language for complex objects and the development of a technique to compile this complex object rule language to classical DATALOG.
Hands-on interaction with virtual environments
Authors: D. J. Sturman, D. Zeltzer, S. Pieper
Venue: Proceedings of the 2nd annual ACM SIGGRAPH symposium on User interface software and technology (1989)

In this paper we describe the evolution of a whole-hand interface to our virtual-environment graphical system. We present a set of abstractions that can be used to implement device-independent interfaces for hand measurement devices. Some of these abstractions correspond to known logical device abstractions, while others take further advantage of the richness of expression in the human hand. We describe these abstractions in the context of their use in our development of virtual environments.
On the Localization Performance Measure and Optimal Edge Detection
Authors: H. D. Tagare, R. J. P. deFigueiredo
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1990)

The localization performance measure of edge detectors is addressed. A one-dimensional formulation of the problem is considered. A linear space-invariant filter is used for the detection. The locations of local maxima in the thresholded output of the filter are declared to be the edges. The limitations of conventional performance measures are shown, and a localization performance measure for edge detection is suggested. This performance measure is based on the theory of zero-crossings of stochastic processes. It is shown that the derivative of a Gaussian is the optimal edge detector for the measure.
Adding regular expressions to Pascal
Authors: D. Sharpe
Venue: ACM SIGPLAN Notices (1988)

One generally praiseworthy characteristic of Pascal is that it allows the programmer to define new data types. However, not all operations that can be performed on indigenous types can also be performed on programmer-defined types. I/O is an example. This paper proposes an extension to Pascal that allows generalized input of enumerated types. Syntax is defined which lets the programmer use regular expressions to exercise considerable control over the translation of strings of input characters into the internal representation used for enumerated types.
Finding tailored partitions
Authors: J. Hershberger, S. Suri
Venue: Proceedings of the fifth annual symposium on Computational geometry (1989)

We consider the following problem: given a planar set of points S, a measure &mgr; acting on S, and a pair of values &mgr;1 and &mgr;2, does there exist a bipartition S = S1 U S2 satisfying &mgr;(Si) &le; &mgr;i for i = 1,2? We present algorithms of complexity &Ogr;(n log n) for several natural measures, including the diameter (set measure), the area, perimeter or diagonal of the smallest enclosing axes-parallel rectangle (rectangular measure), and the side length of the smallest enclosing axes-parallel square (square measure). The problem of partitioning S into k subsets, where k &ge; 3, is known to be NP-complete for many of these measures.
EPEP: an operating system designed for experiment-control
Authors: J. H. Emck, J. H. Voskamp, A. J. van der Wal
Venue: ACM SIGOPS Operating Systems Review (1989)

This paper describes an operating system and programming environment designed specifically for use in data-acquisition and experiment-control. The system, EPEP, is interpreter-based, object-oriented and very flexible. Features include easy-to-handle library and multitasking facilities, as well as facilities for interactive intervention in experiments running under program control. The same facilities allow the development of programs while an experiment is running on the same system. After describing how EPEP presents itself to the user, a few aspects of the implementation are discussed. The EPEP operating system, together with the loaded libraries and user program(s), form a database. The construction of the objects in this database, including program data structure and process descriptor, is discussed.
Expressiveness of restricted recursive queries
Authors: F. Afrati, S. S. Cosmadakis
Venue: Proceedings of the twenty-first annual ACM symposium on Theory of computing (1989)

We study the effect of various syntactic restrictions on the expressive power of database logic programs. We find natural examples of programs which require recursively defined predicates of arbitrarily large width, require rules with arbitrarily many recursive calls, or require nonlinear rules, but can be evaluated in NC2.
Knowledge-based modeling and simulation components
Authors: J. Kaminski, C. Cosic, G. Strohm, J. Kepner, J. Bycura
Venue: Proceedings of the 21st conference on Winter simulation (1989)

Carnegie Group, Inc. has developed a series of programming modules that can be used separately or en masse in the areas of modeling and simulation. This paper briefly describes the modules and the domains in which they can potentially be applied. The paper also includes a description of an actual application involving four of the six software packages.
Minimum Distance: A Method for Partitioning Recurrences for Multiprocessors
Authors: J.-K. Peir, R. Cytron
Venue: IEEE Transactions on Computers (1989)

Parallel execution of nonvectorizable uniform recurrences is considered. When naively scheduled, such recurrences could create unacceptable communication and synchronization on a multiprocessor. The minimum-distance method partitions such recurrences into totally independent computations without increasing redundancy or perturbing numerical stability. The independent computations are well suited for execution on a multiprocessor, but they may not utilize all available processors. How extra processors can be applied to the independent computations is addressed. The methods are especially attractive for multiprocessors comprised of clusters.
On reordering instruction streams for pipelined computers
Authors: J.-J. Shieh, C. Papachristou
Venue: ACM SIGMICRO Newsletter (1989)

This paper describes a method to reorder the straight line instruction streams for pipelined computers which have one instruction issue unit but may contain multiple function units. The objective is to make the most efficient usage of the pipelines within the computer system. The input to the scheduler is the intermediate code of a compiler, and is represented by a data dependence graph (DDG). The scheduler is a kind of list scheduler. The data dependence and the pipeline effect of the function units within the system have been considered for finding a most suitable time slot for each node during reordering time. The scheduler has been implemented and several scientific application programs have been tested. The results show that in most of the cases the scheduler will achieve the optimal result. The average instruction issue rate is over 96%. As a comparison, the issue rate of an ordinary compiler is only 22%; and the issue rate of a compiler with the effect of pipeline but without reordering the instruction stream is about 45%.
A pseudo-machine for packet monitoring and statistics
Authors: R. T. Braden
Venue: Symposium proceedings on Communications architectures and protocols (1988)

This paper concerns the design of a flexible and efficient packet monitoring program for analyzing traffic patterns and gathering statistics on a packet network. This monitor operates in real time, using an analyzer which is an interpretive pseudo-machine driving object-oriented data collection programs. The pseudo-program for the interpreter is &ldquo;compiled&rdquo; from configuration commands written in a monitoring control language.
A fast method dispatcher for compiled languages with multiple inheritance
Authors: R. Dixon, T. McKee, M. Vaughan, P. Schweizer
Venue: ACM SIGPLAN Notices (1989)

This paper addresses the problem of an efficient dispatch mechanism in an object-oriented system with multiple inheritance. The solution suggested is a direct table indexed branch such as is used in C++. The table slot assignments are made using a coloring algorithm. The method is applicable to strongly typed languages such as C++ (with multiple inheritance added) and Eiffel, and in a slightly slower form to less strongly typed languages like Objective C.
A protocol conversion software toolkit
Authors: J. Auerbach
Venue: ACM SIGCOMM Computer Communication Review (1989)

This paper describes a &ldquo;toolkit&rdquo; (a software function library) for synthesizing conversions between different transport interfaces. The method employed involves classifying these interfaces according to their &ldquo;transport abstraction type.&rdquo; Each actual interface is converted to or from a canonical form depending on its type, and the library also contains sufficient &ldquo;abstraction converters&rdquo; to convert between all of the canonical forms. The overall conversion is accomplished by combining some number of elementary conversions which execute in series. The paper describes the toolkit, contrasts it with other approaches, and shows how it can be used to solve various problems in protocol conversion and the &ldquo;migration&rdquo; of distributed services to new network contexts.
Region growing on a hypercube multiprocessor
Authors: M. Willebeek-LeMair, A. P. Reeves
Venue: Proceedings of the third conference on Hypercube concurrent computers and applications - Volume 2 (1989)

The region growing paradigm for image segmentation groups neighboring pixels into regions depending upon a predetermined homogeneity criteria. A parallel method for region growing on an MIMD multiprocessor system is presented. Since the region growing problem exhibits non-uniform and unpredictable load fluctuations, it requires a dynamic load balancing scheme to achieve a balanced load distribution. The results of implementing a parallel region growing algorithm on the Intel-iPSC hypercube are discussed.
Separable image warping with spatial lookup tables
Authors: G. Wolberg, T. E. Boult
Venue: ACM SIGGRAPH Computer Graphics (1989)

Image warping refers to the 2-D resampling of a source image onto a target image. In the general case, this requires costly 2-D filtering operations. Simplifications are possible when the warp can be expressed as a cascade of orthogonal 1-D transformations. In these cases, separable transformations have been introduced to realize large performance gains. The central ideas in this area were formulated in the 2-pass algorithm by Catmull and Smith. Although that method applies over an important class of transformations, there are intrinsic problems which limit its usefulness.The goal of this work is to extend the 2-pass approach to handle arbitrary spatial mapping functions. We address the difficulties intrinsic to 2-pass scanline algorithms: bottlenecking, foldovers, and the lack of closed-form inverse solutions. These problems are shown to be resolved in a general, efficient, separable technique, with graceful degradation for transformations of increasing complexity.
Programming atomic actions in Ada
Authors: A. Burns, A. J. Wellings
Venue: ACM SIGAda Ada Letters (1989)

Atomic actions are often seen as an important structuring aid in the design and construction of fault tolerant programs. In this paper we consider whether recoverable atomic action can be implemented in Ada using the language's communication and synchronisation mechanisms. Whilst simple atomic actions can be programmed in Ada, recoverable actions cannot because the language does not have an asynchronous exception facility.
Integrating non-intering versions of programs
Authors: S. Horwitz, J. Prins, T. Reps
Venue: Proceedings of the 15th ACM SIGPLAN-SIGACT symposium on Principles of programming languages (1988)

The need to integrate several versions of a program into a common one arises frequently, but it is a tedious and time consuming task to integrate programs by hand. The main contribution of this paper is an algorithm, called integrate, that takes as input three programs A, B, and Base, where A and B are two variants of Base. Whenever the changes made to Base to create A and B do not &ldquo;interfere&rdquo; (in a sense defined in the paper), Integrate produces a program M that integrates A and B.
Mark IIIfp hypercube concurrent processor architecture
Authors: J. Tuazon, J. Peterson, M. Pniel
Venue: Proceedings of the third conference on Hypercube concurrent computers and applications: Architecture, software, computer systems, and general issues - Volume 1 (1988)

The Mark lllfp Hypercube is a new generation of hypercube concurrent processor system developed at JPL/Caltech, with peak performance of 5 Mips, 14 Mflops per node, and a peak communication rate of 6 Mbytes per second. Each node utilizes two Motorola MC68020 microprocessors, an MC68882 scalar floating- point coprocessor, and a Weitek 8000 floating-point chip set. One of the MC68020 processors serves as the application and computational processor, the other is dedicated to communication. The three processors are interconnected through a common system bus and share 4 Mbytes of dynamic memory. Each processor has his own fast local memory, which increases parallelism, minimizes shared memory referencing, reduces memory contentions and improves system performance.
Probabilistic testing of protocols
Authors: D. P. Sidhu, C.-S. Chang
Venue: ACM SIGCOMM Computer Communication Review (1989)

Test sequences are used for the conformance testing of communication protocols to standards. This paper discusses a new approach to generating test sequences. The approach is based on probabilistic concepts about protocol state transitions and communication channels. The novel feature of the test sequences generated by this technique is that the most probable states of a protocol will be tested more promptly.
An APL-tutoring adventure game
Authors: A. Geyer-Schulz, A. Taudes, J. Mitlöhner
Venue: Conference proceedings on APL as a tool of thought (1989)

This paper is concerned with the development of a program system that assists the teaching of APL2. Rather than presenting the teaching material in a book-like sequential manner, we would like to embed the learning component in an object oriented adventure game environment written itself in APL2. The game's actors, objects and places, which are implemented as hierarchical classes of communicating automata, can be freely defined, using a "game definition language". The game is driven by a game simulator.The teaching aspect is integrated as follows: The adventurer/student is a specific actor who is presented with a number of exercises that are selected by "teachers", another special class of actors, on the basis of the APL2-knowledge obtained by the student so far. The solutions entered into the system are analysed by the teachers, who use an LR(1)-parser generator and "critic programs" to give advice on proper APL2-programming.
A high-level user interface management system
Authors: G. Singh, M. Green
Venue: ACM SIGCHI Bulletin (1989)

A high-level UIMS which automatically generates the lexical and syntactic design of graphical user interfaces is presented. The interfaces generated by the UIMS can easily and rapidly be refined by the designer by using highly interactive and graphical facilities. The UIMS accepts a high-level description of the semantic commands supported by the application, a description of the implementation device, and optionally, the end user's preferences. Based on these inputs the UIMS generates graphical user interfaces in which the commands are selected from menus and command arguments are provided through interaction with graphical interaction techniques.
A new approach to processor allocation and task migration in an N-cube multiprocessor
Authors: J. E. Jang, S. W. Choi, W. K. Cho
Venue: Proceedings of the 1989 ACM/IEEE conference on Supercomputing (1989)

We propose a new strategy to recognize the maximum subcube in an n-cube multiprocessor. This subcube recognition algorithm can be done in both serial and parallel and analyzed. This strategy will enhance the performance drastically so that our algorithm will outperform the buddy system by a factor nCk, the gray strategy by nCk/2 and Al-Dhelaan [8] by nCk/(k(n-k)+1) in cube recognition. We present a very efficient processor allocation strategy which makes larger contiguous spaces for the new coming job than buddy, gray strategy and Al-Dhelaan [8] do. Furthermore, this new strategy is suitable for static as well as dynamic processors allocation and it results in a less fragmentation and higher fault tolerance. Also we describe an efficient procedure for task migration under the new strategy: 1) goal configuration under the new strategy 2) node-mapping between source and destination node 3) the shortest deadlock-free routing algorithm.
APL and finite elements for solving convection-diffusion problems, with examples from gas bearing design
Authors: F. Hendriks
Venue: Proceedings of the international conference on APL (1987)

The increasing popularity of finite element techniques to solve fluid flow problems has been due, in large part, to its geometric flexibility and adaptability. APL shares that property. Therefore, it is a natural companion to finite element modelling. The closeness of control that APL allows during algorithm and program development is especially welcome during the pre-processing stages of the solution of field problems, in particular during grid generation. This leads to very reasonable &ldquo;door-to-door&rdquo; solution times, especially for problems that occur in a R D environment, where a large percentage of the time is spent formulating, changing and maintaining code. Using examples from engineering practice, the adaptability of APL is illustrated in gas bearing design, as applied to magnetic sliders in hard disk files and laser mirror scanners in electrophotographic printers. APL was also used to teach finite element techniques and grid generation. It proved effective in affording a more immediate view of the key steps of finite element modelling, such as assembly of the stiffness matrix, and the effect of node numbering on the bandwidth of the sparse linear system.
The 9373 and 9375 pipelined processing unit
Authors: Ron Kalla
Venue: ACM SIGMICRO Newsletter (1988)

The IBM 9370 processor family uses System/370 (S/370) architecture, which consists of three parts: the central processing unit (CPU), memory, and I/O control. This paper explains how the 9373 and 9375 CPU instruction processing cards fetch and execute S/370 instructions.To obtain the maximum performance, the CPU is designed as a pipelined processor. Pipelining is a method used in processor design to optimize performance of a sequential stream of instructions. In a sequential stream of instructions, the processor knows what the next instruction is before the current one is completed; consequently, it can begin execution of it. In some cases, the processor can start some phase of the execution of several instructions before executing the current one, thus giving depth to the pipe. The 9373 and 9375 CPU cards take full advantage of pipelining to deliver optimum performance.