ppxscal/embedding_network huggingface dataset:
Learning Compatibility Coefficients for Relaxation Labeling Processes
Authors: M. Pelillo, M. Refice
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1994)

Relaxation labeling processes have been widely used in many different domains including image processing, pattern recognition, and artificial intelligence. They are iterative procedures that aim at reducing local ambiguities and achieving global consistency through a parallel exploitation of contextual information, which is quantitatively expressed in terms of a set of "compatibility coefficients." The problem of determining compatibility coefficients has received a considerable attention in the past and many heuristic, statistical-based methods have been suggested. In this paper, the authors propose a rather different viewpoint to solve this problem: they derive them attempting to optimize the performance of the relaxation algorithm over a sample of training data; no statistical interpretation is given: compatibility coefficients are simply interpreted as real numbers, for which performance is optimal. Experimental results over a novel application of relaxation are given, which prove the effectiveness of the proposed approach.
Verification of integer multipliers on the arithmetic bit level
Authors: Dominik Stoffel, Wolfgang Kunz
Venue: Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design (2001)

One of the most severe short-comings of currently available equivalence checkers is their inability to verify integer multipliers. In this paper, we present a bit level reverse-engineering technique that can be integrated into standard equivalence checking flows. We propose a Boolean mapping algorithm that extracts a network of half adders from the gate netlist of an addition circuit. Once the arithmetic bit level representation of the circuit is obtained, equivalence checking can be performed using simple arithmetic operations. Experimental results show the promise of our approach.
Consistent policy enforcement in distributed systems using mobile policies
Authors: Susan Chapin, Don Faatz, Sushil Jajodia, Amgad Fayad
Venue: Data Knowledge Engineering (2002)

This paper briefly traces the evolution of information system architectures from mainframe-connected terminals to distributed multi-tier architectures. It presents the challenges facing developers of multitier information systems in providing effective consistent data policy enforcement, such as access control in these architectures. Finally, it introduces "Mobile Policy" (MoP) as a potential solution and presents a framework for using mobile policy in the business logic tier of multi-tier information systems.
Increasing Productivity at Saturn
Authors: Earl Long, Amit Misra, Janos Sztipanovits
Venue: Computer (1998)

To remain competitive, manufacturing enterprises must increase throughput and simultaneously reduce costs. This requires daily and long-term examination and analysis of a plant's functions and operations. Using this data, an enterprise can identify production flow bottlenecks and analyze capacity and other factors, which in turn helps identify improvement opportunities. While such information is critical, it is often a challenge to obtain in a complex manufacturing environment. The automotive industry provides some prime examples of complex manufacturing environments. At Saturn Corp., we turned to academic research--work involving model-integrated computing (MIC)--as a framework to organize the diverse types of data our information system must deal with. Using MIC and working with the Vanderbilt University researchers, Saturn built the Saturn Site Production Flow system. This system provides real-time information--culled from 80,000 data points--to Saturn personnel across the plant. Using SSPF-provided information helped Saturn improve throughput at its plant by 10 percent. Through models, we can readily explain a complex data structure in a virtual view of a manufacturing-plant floor. Diverse services are required for applications such as process monitoring and control, process simulation, statistical analysis packages, and other data manipulation tools. MIC integrates these tools into a common problem-solving environment.
Fast Algorithms for Online Generation of Profile Association Rules
Authors: Charu C. Aggarwal, Zheng Sun, Philip S. Yu
Venue: IEEE Transactions on Knowledge and Data Engineering (2002)

The results discussed in this paper are relevant to a large database consisting of consumer profile information together with behavioral (transaction) patterns. We introduce the concept of profile association rules, which discusses the problem of relating consumer buying behavior to profile information. The problem of online mining of profile association rules in this large database is discussed. We show how to use multidimensional indexing structures in order to actually perform the mining. The use of multidimensional indexing structures to perform profile mining provides considerable advantages in terms of the ability to perform very generic range-based online queries.
A meta-communication model for structuring intercultural communication action patterns
Authors: Fahri Yetim
Venue: ACM SIGGROUP Bulletin (2001)

This paper presents a meta-communication model for discursive construction of communication action patterns that may be part of an information system which supports communication and cooperation in virtual intercultural communities. The paper also provides a brief review of previous ideas on meta-communication from the language action perspective.
The TMS320C30 Floating-Point Digital Signal Processor
Authors: Panos Papamichalis, Ray Simar,  Jr.
Venue: IEEE Micro (1988)

The 320C30 is a fast processor with a large memory space and floating-point-arithmetic capabilities. The authors describe the 320C30 architecture in detail, discussing both the internal organization of the device and the external interfaces. They also explain the pipeline structure, addressing software-related issues and constructs, and examine the development tools and support. Finally, they present examples of applications. Some of the major features of the 320C30 are: a 60-ns cycle time that results in execution of over 16 million instructions per second (MIPS) and over 33 million floating-point operations per second (Mflops); 32-bit data buses and 24-bit address buses for a 16M-word overall memory space; dual-access, 4 K*32-bit on-chip ROM and 2 K*32-bit on-chip RAM; a 64*32-bit program cache; a 32-bit integer/40-bit floating-point multiplier and ALU; eight extended-precision registers, eight auxiliary registers, and 23 control and status registers; generally single-cycle instructions; integer, floating-point, and logical operation; two- and three-operand instructions; an on-chip DMA controller; and fabrication in 1- mu m CMOS technology and packaging in a 180-pin package. These facilitate FIR (finite impulse response) and IIR (infinite impulse response) filtering, telecommunications and speech applications, and graphics and image processing applications.
Classifying Packets with Hierarchical Intelligent Cuttings
Authors: Pankaj Gupta, Nick McKeown
Venue: IEEE Micro (2000)

Increasing demands on Internet router performance and functionality create a need for algorithms that classify packets quickly with minimal storage requirements and allow frequent updates. Unlike previous algorithms, the algorithm proposed here meets this need well by using heuristics that exploit structure present in classifiers.
Recovery, Redemption, and Extreme Programming
Authors: Peter Schuh
Venue: IEEE Software (2001)

The author retells a downtrodden project's attempt to rejuvenate itself by doing Extreme Programming, discussing successes, shortcomings, and, ultimately, lessons learned. In particular, the author credits the team's composition for its ultimate success. Although XP wasn't the team's immediate salvation, it made the application sustainable past the project's deadline.
Power-delay modeling of dynamic CMOS gates for circuit optimization
Authors: J. L. Rossello, Jaume Segura
Venue: Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design (2001)

We present an accurate analytical expression to compute power and delay of domino CMOS circuits from a detailed description of internal capacitor switching and discharging currents. The expression obtained accounts for the main effects in complex sub-micron gates like velocity saturation effects, body effect, device sizes and coupling capacitors. The energy-delay product is also evaluated and analyzed. Results are compared to HSPICE simulations (level 50) for a 0.18&mu;m CMOS technology.
An Efficient Dynamic Scheduling Algorithm for Multiprocessor Real-Time Systems
Authors: G. Manimaran, C. Siva Ram Murthy
Venue: IEEE Transactions on Parallel and Distributed Systems (1998)

Many time-critical applications require predictable performance and tasks in these applications have deadlines to be met. In this paper, we propose an efficient algorithm for nonpreemptive scheduling of dynamically arriving real-time tasks (aperiodic tasks) in multiprocessor systems. A real-time task is characterized by its deadline, resource requirements, and worst case computation time on p processors, where p is the degree of parallelization of the task. We use this parallelism in tasks to meet their deadlines and, thus, obtain better schedulability compared to nonparallelizable task scheduling algorithms. To study the effectiveness of the proposed scheduling algorithm, we have conducted extensive simulation studies and compared its performance with the myopic [8] scheduling algorithm. The simulation studies show that the schedulability of the proposed algorithm is always higher than that of the myopic algorithm for a wide variety of task parameters.
Development of a Multichip Module DSP
Authors: Robert K. Scannell, John K. Hagge
Venue: Computer (1993)

The signal processor packaging design (SPPD) general-purpose digital signal processor (DSP) architecture is discussed. SPPD is a highly modular processor architecture that is based on off-the-shelf components and that supports a multichip module (MCM) design implementation that delivers 400 million floating-point operations per second in a 75-g package. The interconnect-substrate design, MCM package assembly, MCM testing, and tradeoffs in size, weight, and cost of the SPPD packaging are described.
Protecting deductive databases from unauthorized retrieval and update requests
Authors: Steve Barker
Venue: Data Knowledge Engineering (2002)

We show how deductive databases may be protected against unauthorized retrieval and update requests issued by authenticated users. To achieve this protection, a deductive database is expressed in a form that guarantees that only authorized access requests are permitted. Authorized retrieval and update requests are specified by using an access control theory that is expressed in normal clause logic. The approach has a number of attractive technical results associated with it, can be efficiently implemented, and can be used to protect the information in any normal deductive database.
On the optimality of the random hyperplane rounding technique for max cut
Authors: Uriel Feige, Gideon Schechtman
Venue: Random Structures Algorithms (2002)

MAX CUT is the problem of partitioning the vertices of a graph into two sets, maximizing the number of edges joining these sets. This problem is NP-hard. Goemans and Williamson proposed an algorithm that first uses a semidefinite programming relaxation of MAX CUT to embed the vertices of the graph on the surface of an n-dimensional sphere, and then uses a random hyperplane to cut the sphere in two, giving a cut of the graph. They show that the expected number of edges in the random cut is at least α . sdp, where α ∼ 0.87856 and sdp is the value of the semidefinite program, which is an upper bound on opt, the number of edges in the maximum cut. This manuscript shows the following results: (1) The integrality ratio of the semidefinite program is α. The previously known bound on the integrality ratio was roughly 0.8845. (2) In the presence of the so-called "triangle constraints," the integrality ratio is no better than roughly 0.891. The previously known bound was above 0.95. (3) There are graphs and optimal embeddings for which the best hyperplane approximates opt within a ratio no better than α, even in the presence of additional valid constraints. This strengthens a result of Karloff that applied only to the expected number of edges cut by a random hyperplane.
Graph Partitioning Using Learning Automata
Authors: B. John Oommen, Edward V. de St. Croix
Venue: IEEE Transactions on Computers (1996)

Given a graph G, we intend to partition its nodes into two sets of equal size so as to minimize the sum of the cost of the edges having end-points in different sets. This problem, called the uniform graph partitioning problem, is known to be NP-Complete. In this paper we propose the first reported learning-automaton based solution to the problem. We compare this new solution to various reported schemes such as the Kernighan-Lin's algorithm, and two excellent recent heuristic methods proposed by Rolland et al.¿an extended local search algorithm and a genetic algorithm. The current automaton-based algorithm outperforms all the other schemes. We believe that it is the fastest algorithm reported to date. Additionally, our solution can also be adapted for the GPP (See note at end of Section 1) in which the edge costs are not constant but random variables whose distributions are unknown.
Improved Inclusion-Exclusion Identities and Bonferroni Inequalities with Reliability Applications
Authors: Klaus Dohmen
Venue: SIAM Journal on Discrete Mathematics (2003)

This paper establishes a connection between the theory of convex geometries, the principle of inclusion-exclusion, and the topological concept of an abstract tube. In particular, it is shown that convex geometries give rise to improved inclusion-exclusion identities and improved Bonferroni inequalities. In this way, several known results from the literature are rediscovered in a concise and unified way. The results are applied in identifying a new class of hypergraphs for which the reliability covering problem can be solved in polynomial time.
Scheduling of unstructured communication on the Intel iPSC/860
Authors: Jhy Chun Wang, Sanjay Ranka
Venue: Proceedings of the 1994 ACM/IEEE conference on Supercomputing (1994)

In this paper we present several algorithms for decomposing all-to-many personalized communication into a set of disjoint partial permutations. These partial permutations avoid node contention as well as link contention. We discuss the theoretical complexity of these algorithms and study their effectiveness both from the view of static scheduling and from runtime scheduling. Experimental results for our algorithms are presented on the iPSC/860.
Vector Field Analysis for Oriented Patterns
Authors: C. F. Shu, R. C. Jain
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1994)

Presents a method, based on the properties of vector fields, for the estimation of a set of symbolic descriptors (node, saddle, star-node, improper-node, center, and spiral) from linear orientation fields. Planar first-order phase portraits are used to model the linear orientation fields. A weighted linear estimator is developed to estimate linear phase portraits, using only the flow orientation. A classification scheme for planar first-order phase portraits, based on their local properties: curl, divergence, and deformation is developed. The authors present results of experiments on noise-added synthetic flow patterns and real oriented textures.
STARS in VCC: complementing simulation with worst-case analysis
Authors: Felice Balarin
Venue: Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design (2001)

STARS is a methodology for worst-case analysis of embedded systems. STARS manipulates abstract representations of system components to obtain upper bounds on the number of various events in the system, as well as a bound on the response time. VCC is a commercial discrete event simulator, that can be used both for functional and performance verification. We describe an extension of VCC to facilitate STARS. The extension allows the user to specify abstract representations of VCC modules. These abstractions are used by STARS, but their validity can also be checked by VCC simulation. We also propose a mostly automatic procedure to generate these abstractions. Finally, we illustrate on an example how STARS can be combined with simulation to find bugs that would be hard to find by simulation alone.
A Software-Hardware Cosynthesis Approach to Digital System Simulation
Authors: Kunle A. Olukotun, Rachid Helaihel, Jeremy Levitt, Ricardo Ramirez
Venue: IEEE Micro (1994)

Our approach to digital system simulation compiles a high-level system model into a high-performance simulator that consists of software and hardware components. The target architecture for the simulation compiler is a tightly coupled processor and field-programmable gate array. We describe the simulation compiler and show how it can be used to improve simulation performance by up to a factor of two over an all-software simulator.
Structural Fault Testing of Embedded Cores Using Pipelining
Authors: M. Nourani, C. A. Papachristou
Venue: Journal of Electronic Testing: Theory and Applications (1999)

The purpose of this paper is to develop a global design for test methodology for testing a core-based system in its entirety. This is achieved by introducing a &ldquo;bypass&rdquo; mode for each core by which the data can be transferred from a core input port to the output port without interfering the core circuitry itself. The interconnections are thoroughly tested because they are used to propagate test data (patterns or signatures) in the system. The system is modeled as a directed weighted graph in which the accessibility (of the core input and output ports) is solved as a shortest path problem. Finally, a pipelined test schedule is made to overlap accessing input ports (to send test patterns) and output ports (to observe the signatures). The experimental results show higher fault coverage and shorter test time.
Coordination for Internet Application Development
Authors: Andrea Omicini, Franco Zambonelli
Venue: Autonomous Agents and Multi-Agent Systems (1999)

The adoption of a powerful and expressive coordination model represents a key-point for the effective design and development of Internet applications. In this paper, we present the TuCSoN coordination model for Internet applications based on network-aware and mobile agents, and show how the adoption of TuCSoN can positively benefit the design and development of such applications, firstly in general terms, then via a TuCSoN-coordinated sample application. This is achieved by providing for an Internet interaction space made up of a multiplicity of independently programmable communication abstractions, called tuple centres, whose behaviour can be defined so as to embody the laws of coordination.
Parallel N-ary Speculative Computation of Simulated Annealing
Authors: Andrew Sohn
Venue: IEEE Transactions on Parallel and Distributed Systems (1995)

Simulated annealing is known to be an efficient method for combinatorial optimization problems. Its usage for realistic problem size, however, has been limited by the long execution time due to its sequential nature. This report presents a practical approach to synchronous simulated annealing for massively parallel distributed-memory multiprocessors. We use an n-ary speculative tree to execute n different iterations in parallel on n processors, called Generalized Speculative Computation (GSC). Execution results of the 100- to 500-city Traveling Salesman Problems on the AP1000 massively parallel multiprocessor demonstrate that the GSC approach can be an effective method for parallel simulated annealing as it gave over 20-fold speedup on 100 processors.
Structuring Fault-Tolerant Object Systems for Modularity in a Distributed Environment
Authors: S. K. Shrivastava, D. L. McCue
Venue: IEEE Transactions on Parallel and Distributed Systems (1994)

The object-oriented approach to system structuring has found widespread acceptanceamong designers and developers of robust computing systems. The authors propose asystem structure for distributed programming systems that support persistent objects anddescribe how properties such as persistence and recoverability can be implemented. Theproposed structure is modular, permitting easy exploitation of any distributed computingfacilities provided by the underlying system. An existing system constructed according tothe principles espoused here is examined to illustrate the practical utility of the proposedapproach to system structuring.
Cobol Tools: Overview and Taxonomy
Authors: Edmund C. Arranga
Venue: IEEE Software (2000)

One of the biggest challenges post-Y2K is legacy renewal, yet many developers have no idea of the num-ber of tools available. The four tools highlighted here represent a range of legacy renewal options, from new GUI front ends to creating components. The tool taxonomy list covers more than 100 tools in various categories along with their URLs.
Solution of Switching Equations Based on a Tabular Algebra
Authors: P. P. Trabado, A. Lloris-Ruiz, J. Ortega-Lopera
Venue: IEEE Transactions on Computers (1993)

Several problems in switching theory such as automatic test pattern generation, can be exactly and elegantly investigated by using switching equations. An efficient tabular method is presented to solve these switching equations. The solutions of a given equation are compacted into a table, and a Boolean algebra is defined for these tables. The proposed procedure is based on the use of this Boolean algebra. The compactness and simplicity of the method are outstanding, and it is straightforward to implement for computer processing. The complexity of the procedure is computed, and some experimental results for a set of benchmark equations are provided in order to point out the effectiveness of this method.
How Perspective-Based Reading Can Improve Requirements Inspections
Authors: Forrest Shull, Ioana Rus, Victor Basili
Venue: Computer (2000)

Because defects constitute an unavoidable aspect of software development, discovering and removing them early is crucial. Over-looked defects (like faults in the software system requirements, design, or code) propagate to subsequent development phases where detecting and correcting them becomes more difficult. At best, developers will eventually catch the defects, but at the expense of schedule delays and additional product-development costs. At worst, the defects will remain, and customers will receive a faulty product.The authors explain their perspective-based reading (PBR) technique that provides a set of procedures to help developers solve software requirements inspection problems. PBR reviewers stand in for specific stakeholders in the document to verify the quality of requirements specifications. The authors show how PBR leads to improved defect detection rates for both individual reviewers and review teams working with unfamiliar application domains.
Positive Bases in Numerical Optimization
Authors: I. D. Coope, C. J. Price
Venue: Computational Optimization and Applications (2002)

The theory of positive bases introduced by C. Davis in 1954 does not appear in most modern texts on linear algebra but has re-emerged in publications in optimization journals. In this paper some simple properties of this highly useful theory are highlighted and applied to both theoretical and practical aspects of the design and implementation of numerical algorithms for nonlinear optimization.