ppxscal/embedding_network huggingface dataset:
Ten Commandments of Formal Methods
Authors: Jonathan P. Bowen, Michael G. Hinchey
Venue: Computer (1995)

The formal methods community is in general very good at undertaking research into the mathematical aspects of formal methods, but not so good at promulgating the use of formal methods in an engineering environment and at an industrial scale. Technology transfer is an extremely important part of the overall effort necessary in the acceptance of formal techniques. This paper explores some of the more informal aspects of applying formal methods and presents some maxims with associated discussion that may help in the application of formal methods in an industrial setting.
Runge---Kutta methods in elastoplasticity
Authors: Jörg Büttner, Bernd Simeon
Venue: Applied Numerical Mathematics (2002)

Runge-Kutta methods for the constitutive equations of elastoplasticity are presented. These equations form a differential-algebraic equation (DAE) of index 2 with unilateral constraints. For the numerical solution, implicit Runge-Kutta methods are combined with the return mapping strategy of computational plasticity. It turns out that the convergence order depends crucially on the switching point detection. Furthermore, it is shown that algebraically stable Runge-Kutta methods preserve the contractivity of the elastoplastic flow.
An Empirical Study of the Simulation of Various Models used for Images
Authors: A. J. Gray, J. W. Kay, D. M. Titterington
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1994)

Markov random fields are typically used as priors in Bayesian image restoration methods to represent spatial information in the image. Commonly used Markov random fields are not in fact capable of representing the moderate-to-large scale clustering present in naturally occurring images and can also be time consuming to simulate, requiring iterative algorithms which can take hundreds of thousands of sweeps of the image to converge. Markov mesh models, a causal subclass of Markov random fields, are, however, readily simulated. We describe an empirical study of simulated realizations from various models used in the literature, and we introduce some new mesh-type models. We conclude, however, that while large-scale clustering may be represented by such models, strong directional effects are also present for all but very limited parameterizations. It is emphasized that the results do not detract from the use of Markov random fields as representers of local spatial properties, which is their main purpose in the implementation of Bayesian statistical approaches to image analysis. Brief allusion is made to the issue of parameter estimation.
Reducing Branch Delay to Zero in Pipelined Processors
Authors: A. M. Gonzalez, J. M. Llaberia
Venue: IEEE Transactions on Computers (1993)

A mechanism to reduce the cost of branches in pipelined processors is described and evaluated. It is based on the use of multiple prefetch, early computation of the target address, delayed branch, and parallel execution of branches. The implementation of this mechanism using a branch target instruction memory is described. An analytical model of the performance of this implementation makes it possible to measure the efficiency of the mechanism with a very low computational cost. The model is used to determine the size of cache lines that maximizes the processor performance, to compare the performance of the mechanism with that of other schemes, and to analyze the performance of the mechanism with two alternative cache organizations.
The HP PA-8000 RISC CPU
Authors: Ashok Kumar
Venue: IEEE Micro (1997)

The PA-8000 RISC CPU is the first implementation of a new generation of microprocessors from Hewlett-Packard Company. The processor was designed for high-end systems and to support the new 64-bit PA-RISC 2.0 architecture. The aggressive four-way superscalar implementation also features speculative, out-of-order execution combined with ten independent functional units, allowing it to attain true leadership performance. Large single-level caches are provided off-chip. At the heart of the out-of-order execution capability of the machine is a high performance, 56-entry Instruction Reorder Buffer. The complexities of tracking many types of dependencies in this large instruction window and determining which instructions to issue for execution will be included. The chip is fabricated in a 0.5 micron, 3.3V CMOS process, resulting in a 17.68x19.1 mm die with 3.8 million transistors. A robust 64-bit, 768 MB/s split-transaction system bus supplies the CPU with instructions and data, and provides for multiprocessing.
The Hierarchical Hypercube: A New Interconnection Topology for Massively Parallel Systems
Authors: Q. M. Malluhi, M. A. Bayoumi
Venue: IEEE Transactions on Parallel and Distributed Systems (1994)

Interconnection networks play a crucial role in the performance of parallel systems. Thispaper introduces a new interconnection topology that is called the hierarchical hypercube(HHC). This topology is suitable for massively parallel systems with thousands ofprocessors. An appealing property of this network is the low number of connections perprocessor, which enhances the VLSI design and fabrication of the system. Other alluringfeatures include symmetry and logarithmic diameter, which imply easy and fast algorithms for communication. Moreover, the HHC is scalable; that is it can embed HHC's of lower dimensions. The paper presents two algorithms for data communication in the HHC. The first algorithm is for one-to-one transfer, and the second is for one-to-all broadcasting. Both algorithms take O(log/sub 2/k), where k is the total number of processors in the system. A wide class of problems, the divide & conquer class (D&Q), is shown to be easily and efficiently solvable on the HHC topology. Parallel algorithms are provided to describe how a D&Q problem can be solved efficiently on an HHC structure. The solution of a D&Q problem instance having up to k inputs requires a time complexity of O(log/sub 2/k).
Increasing web server throughput with network interface data caching
Authors: Hyong-youb Kim, Vijay S. Pai, Scott Rixner
Venue: ACM SIGARCH Computer Architecture News (2002)

This paper introduces network interface data caching, a new technique to reduce local interconnect traffic on networking servers by caching frequently-requested content on a programmable network interface. The operating system on the host CPU determines which data to store in the cache and for which packets it should use data from the cache. To facilitate data reuse across multiple packets and connections, the cache only stores application-level response content (such as HTTP data), with application-level and networking headers generated by the host CPU. Network interface data caching can reduce PCI traffic by up to 57% on a prototype implementation of a uniprocessor web server. This traffic reduction results in up to 31% performance improvement, leading to a peak server throughput of 1571 Mb/s.
Job-Shop Development Model: A Case Study
Authors: Corey A. Leonhard, J. Steve Davis
Venue: IEEE Software (1995)

A realistic model for estimating software project time would account for division of staff time among several competing projects and would model individual productivity. A good model would also adequately address software rework due to errors and changes in requirements identified before or after installation. Specifically it should consider that rework could require effort in any previous phase, and not just the preceding one. Correction of an error or implementation of a change could involve only part of the software. While that part is undergoing rework the rest could continue to later phases of development. These characteristics find a close analogy in the job shop model which is commonly used in manufacturing. In the adaptation of this model to software, jobs (software items needing work) are handled by machines (people). The model is represented by a stochastic network which routes jobs from multiple projects through the phases of a modified waterfall life cycle. It handles rerouting due to errors, post installation work and individual productivity levels. When calibrated for a sample firm, the model performed rather well in predicting project effort and installation dates.
A Circular List-Based Mutual Exclusion Scheme for Large Shared-Memory Multiprocessors
Authors: Shiwa S. Fu, Nian-Feng Tzeng
Venue: IEEE Transactions on Parallel and Distributed Systems (1997)

Mutual exclusion in shared-memory multiprocessors is realized by employing a lock to determine the processor among those which compete for the critical section. Accesses to such a mutual exclusion lock may create heavy synchronization traffic and/or serious contention over the network, thereby degrading system performance considerably. In this paper, we introduce an efficient scheme which keeps synchronization traffic low and avoids serious hot-spot contention. This is made possible by constructing a circular list of the processors waiting for the critical section and by dispersing accesses to the lock. Extensive simulation of the proposed approach was conducted and the lower bound on the elapsed time was derived. Our simulation results demonstrate that the proposed scheme indeed achieves better performance than prior techniques, with its elapsed time close to the lower bound for the whole range of simulated system sizes, thus promising good scalability for large systems.
Energy-Aware Runtime Scheduling for Embedded-Multiprocessor SOCs
Authors: Peng Yang, Chun Wong, Paul Marchal, Francky Catthoor, Dirk Desmet, Diederik Verkest, Rudy Lauwereins
Venue: IEEE Design Test (2001)

This task-scheduling method for embedded systems combines the low runtime complexity of a design-time scheduling phase with the flexibility of a runtime scheduling phase.
Arrangement: A Spatial Relation Between Parts for Evaluating Similarity of Tomographic Section
Authors: Hemant D. Tagare, Frans M. Vos, Conrade C. Jaffe, James S. Duncan
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1995)

Medical tomographic images are formed by the intersection of the image plane and an object. As the image plane changes, different parts of the object come in view or drop out of view. However, for small changes of the image plane, most parts continue to remain visible and their qualitative embedding in the image remains similar. Therefore, similarity of part embeddings can be used to infer similarity of image planes. Part embeddings are useful features for other vision applications as well.In view of this, a spatial relation called ¿arrangement¿ is proposed to describe part embeddings. The relation describes how each part is surrounded by its neighbors. Further, a metric for arrangements is formulated by expressing arrangements in terms of the Voronoi diagram of the parts.Arrangements and their metric are used to retrieve images by image plane similarity in a cardiac magnetic resonance image database. Experiments with the database are reported whichvalidate the observation that similarity of image planes can be inferred from similarity of part embeddings, andcompare the performance of arrangement based image retrieval with that of expert radiologists.
Planning the Reengineering of Legacy Systems
Authors: Harry M. Sneed
Venue: IEEE Software (1995)

As the manager of a small software-reengineering company, I am continually confronted with the task of justifying reengineering. The user wants to know what the benefits are. Why reengineer old Cobol or Fortran when there are so many attractive fourth- generation and object-oriented languages on the market? That is why I have chosen to address business issues in this article -- not because the technical problems of transforming code and data structures are not important but because they may be irrelevant if you are not able to make a business case for solving them. There is nothing worse for a technician than to be working on a solution to some problem for years, only to discover that the problem was incorrectly stated from the beginning. I have developed a five- step reengineering planning process, starting with an analysis of the legacy system and ending with contract negotiation. The five major steps are project justification, portfolio analysis, cost estimation, cost-benefit analysis, and contracting.
An OO Database Migrates to the Web
Authors: Maria A. Cobb, Harold Foley, Ruth Wilson, Miyi Chung, Kevin B. Shaw
Venue: IEEE Software (1998)

Traditional databases can be restructured to take advantage of OO methods. Java's advent has enhanced OO's benefits by providing a way to run applications across varying platforms. To take advantage of these trends, the authors first converted a relational database to the OO paradigm, then migrated it to the Web. Here they describe the procedures and technologies they used to accomplish the migration.
Processor Architecture Considerations for Embedded Controller Applications
Authors: Ron Cates
Venue: IEEE Micro (1988)

The ways in which the environment of an embedded controller differs from that of a general-purpose CPU are described. A particular embedded controller application, the network interface is examined. The microprocessor used is the 32-bit VL86C010 Acorn RISC (reduced-instruction-set computer). The features of the network architecture, as they affect the choice of processor, are discussed. The impact of system latency on the choice of hardware is examined.
Electrodeposition of micromagnets of CoPtW(P) alloys
Authors: S. Franz, M. Bestetti, M. Consonni, P. L. Cavallotti
Venue: Microelectronic Engineering (2002)

Well-oriented permanent magnets of CoPtW(P) alloys with the basal plane parallel to the surface and a columnar structure were obtained by electrodeposition. Relatively high saturation moments and coercivities, both in perpendicular and in parallel magnetic field, are obtained at thickness up to 20 µm. Temperature dependence was also investigated, showing a great decrease of the magnetic properties. Chemical post-treatments can strongly influence magnetic properties, decreasing saturation magnetisation and coercivity while increasing squareness ratio.
UltraSparc I: A Four-Issue Processor Supporting Multimedia
Authors: Marc Tremblay, J. Michael O'Connor
Venue: IEEE Micro (1996)

UltraSPARC-I is a general-purpose processor implementing the SPARC V9 64-bit RISC architecture. In addition to supporting this Instruction Set Architecture (ISA), UltraSPARC-I includes over 30 new multimedia instructions (VIS - Visual Instruction Set) that provide the most common operations related to image processing, two- and three-dimensional graphics, video compression/decompression algorithms, etc.The simple in-order execution model implemented on UltraSPARC-I allows a balance between a high clock rate and a relatively wide (four-issue) machine. Microarchitecture features allowing the processor to sustain an execution of four instructions per cycle even in the presence of conditional branches and cache misses are described. The second part of the article focuses on the microarchitecture features that the software can leverage to achieve higher performance, including some of the multimedia features implemented on chip.
Toward a Discipline of Software Engineering
Authors: Anthony I. Wasserman
Venue: IEEE Software (1996)

Despite rapid changes in computing and software development, some fundamental ideas have remained constant. This article describes eight such concepts that together constitute a viable foundation for a software engineering discipline: abstraction, analysis and design methods and notations, user interface prototyping, modularity and architecture, software life cycle and process, reuse, metrics, and automated support.
High-level Language Support for User-defined Reductions
Authors: Steven J. Deitz, Bradford L. Chamberlain, Lawrence Snyder
Venue: The Journal of Supercomputing (2002)

The optimized handling of reductions on parallel supercomputers or clusters of workstations is critical to high performance because reductions are common in scientific codes and a potential source of bottlenecks. Yet in many high-level languages, a mechanism for writing efficient reductions remains surprisingly absent. Further, when such mechanisms do exist, they often do not provide the flexibility a programmer needs to achieve a desirable level of performance. In this paper, we present a new language construct for arbitrary reductions that lets a programmer achieve a level of performance equal to that achievable with the highly flexible, but low-level combination of Fortran and MPI. We have implemented this construct in the ZPL language and evaluate it in the context of the initialization of the NAS MG benchmark. We show a 45 times speedup over the same code written in ZPL without this construct. In addition, performance on a large number of processors surpasses that achieved in the NAS implementation showing that our mechanism provides programmers with the needed flexibility.
Analyzing Multichip Module Testing Strategies
Authors: Magdy S. Abadir, Ashish R. Parikh, Linda Bal, Peter A. Sandborn, Ken Drake
Venue: IEEE Design Test (1994)

Incorporating test and fault diagnosis as critical design requirements is necessary to achieve high-quality, cost-effective multichip systems. However, evaluating where and when to test, and deciding upon the best test method and level, take considerable study. The authors explore the trade-offs between various MCM test and rework strategies, then analyze the impact of cost, yield, and test effectiveness of the final cost and quality. This analysis of the trade-offs associated with test strategies for complex multichip systems and modules clearly indicate that incorporating DFT and BIST with varying degrees at the chip or MCM levels is economically justifiable. These methods result in cost reduction as well as quality improvement, and indicate that the MCM cost could vary by about 10% to 20%, depending on the test strategy used. However, proper determination of where and how to test, and whether to employ DFT and BIST at the IC or MCM levels, require an evaluation of the economics of the various solutions and the payback. This process is highly dependent on the design under consideration and the parameters associated with the available manufacturing environments.
Blueprint for the Ideal Requirements Engineer
Authors: Mark Christensen, Carl Chang
Venue: IEEE Software (1996)

Industry advisers present their vision of the direction of software technology.
The Test of Time
Authors: Ken Sakamura
Venue: IEEE Micro (2002)

We invited Karl E. Grosspietsch from the Fraunhofer Institute of Autonomous Intelligent Systems to organize a special issue on unorthodox computer architectures. This issue presents articles on somewhat unfamiliar topics includingartificial neural networks for ultra-large-scale integration,a parallel neural processor for real-time processing,an intelligent memory architecture for artificial neural networks,a symbolic-learning method based on multiple-valued logic using recon-figurable hardware, anda parallel-processor architecture based on the extension of the cache-only memory architecture to the instruction sequence.
A DSP Controlled resonant active filter for power conditioning in three-phase industrial power systems
Authors: Abdurrahman Ünsal, Annette R. von Jouanne, Virginia L. Stonick
Venue: Signal Processing (2002)

This paper presents a DSP controlled resonant active filter for power conditioning in three-phase industrial or commercial power systems. The active filter is designed to cancel lower-order harmonics generated by nonlinear loads using a series resonant LC tank tuned to a high frequency along with a pulse-width modulated (PWM) rectifier topology. The PWM control of the active filter allows for independent control of lower-order harmonics to efficiently cancel load-generated harmonics for power quality improvement. The active filter control algorithm is simulated in MATLAB and the real-time harmonic cancellation process is implemented on a DSP and verified through experimental results.
Uncertainty Management in Expert Systems
Authors: Keung-Chi Ng, Bruce Abramson
Venue: IEEE Expert: Intelligent Systems and Their Applications (1990)

Basic expert system terminology is reviewed, and several uncertainty management paradigms are surveyed. The focus is on subjective probability theory, Dempster-Shafer theory, and possibility theory, although a number of other methods are mentioned. The benefits and limitations of the various schemes are examined, examples of expert systems within each school are presented, and some relevant open problems are discussed.
Occlusions as a Guide for Planning the Next View
Authors: J. Maver, R. Bajcsy
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1993)

A strategy for acquiring 3-D data of an unknown scene, using range images obtained by a light stripe range finder is addressed. The foci of attention are occluded regions, i.e., only the scene at the borders of the occlusions is modeled to compute the next move. Since the system has knowledge of the sensor geometry, it can resolve the appearance of occlusions by analyzing them. The problem of 3-D data acquisition is divided into two subproblems due to two types of occlusions. An occlusion arises either when the reflected laser light does not reach the camera or when the directed laser light does not reach the scene surface. After taking the range image of a scene, the regions of no data due to the first kind of occlusion are extracted. The missing data are acquired by rotating the sensor system in the scanning plane, which is defined by the first scan. After a complete image of the surface illuminated from the first scanning plane has been built, the regions of missing data due to the second kind of occlusions are located. Then, the directions of the next scanning planes for further 3-D data acquisition are computed.
On the Hicksian Laws of Comparative Statics for the Hicksian Case: the Path-Following Approach Using an Alternative Homotopy
Authors: Takashi Shiomura
Venue: Computational Economics (1998)

The paper discusses an approach to comparative statics in the large by making use of a homotopy continuation method. This is based on the path-following approach presented by the author which is in turn due to the fixed-point algorithm explored by Garcia and Zangwill. We investigate from a global viewpoint the Hicksian laws of comparative statics for the Hicksian case which is a key to the first Hicksian law at least locally, and obtain the first Hicksian law in the large. Global results for the dominant diagonal case and the G_1-Metzlerian case are also obtained.
Image Representation Via a Finite Radon Transform
Authors: F. Matús, J. Flusser
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1993)

A model of finite Radon transforms composed of Radon projections is presented. The model generalizes to finite group projections in the classical Radon transform theory. The Radon projector averages a function on a group over cosets of a subgroup. Reconstruction formulae that were formally similar to the convolved backprojection ones are derived, and an iterative reconstruction technique is found to converge after a finite number of steps. Applying these results to the group Z/sub 2//sup P/, new computationally favorable image representations have been obtained. A numerical study of the transform coding aspects is attached.