ppxscal/embedding_network huggingface dataset:
Computing performance as a function of the speed, quantity, and cost of the processors
Authors: M. L. Barton, G. R. Withers
Venue: Proceedings of the 1989 ACM/IEEE conference on Supercomputing (1989)

Everyone wants more computing power for their applications, and the industry has responded in two ways: first by increasing the speed of single CPU's, and second by deploying multiple processors in parallel. Much controversy exists over how best to balance processor speed against the number of processors employed. Is it better to have a single, very fast and very expensive CPU, thousands of very slow but very cheap CPU's, or is there some optimal mix in between? The value of single processors, measured in floating-point performance per dollar, is relatively easy to assess, but the corresponding value of parallel systems is obscured by the fact that applications are not generally perfectly parallel, with some loss in efficiency occurring due to sequential bottlenecks and communication overhead. Parallel speedup, the ratio of execution time on a single processor to that on p processors, is often used to capture the effect and measure the efficiency of parallel utilization. We argue that this measure of efficiency is not a good measure of parallel performance because it rewards slow processors. Instead we evaluate delivered floating-point performance as a function of the number of processors for either constant aggregate performance of the processors, or constant total cost. From these measures we offer two conclusions: 1) For a given aggregate floating-point performance, actual delivered performance never increases with the number of processors. and 2) For a given cost, delivered performance is maximized by selecting the fastest processor available at a given technology level, and employing as many as the budget allows. These results, which are generally known to parallel researchers, are often overlooked in the marketing announcements promoting &ldquo;massively parallel&rdquo; systems. We motivate this discussion by giving measured performance results from an actual application, and then show the theoretical basis.
Speed and data structures in computer algebra systems
Authors: R. J. Fateman, C. G. Ponder
Venue: ACM SIGSAM Bulletin (1989)

Comparing the speed of computation in algebra systems is a perennial occupation of system designers, algorithm implementors, and, more recently, marketing personnel. At least some people have observed that for many problems, the choice of a system makes much less difference than the approach used to represent the problem. The mapping from mathematics to a data representation and the choice of algorithms can make significant, and separate, contributions to efficiency. Systems which have the flexibility to provide several data structures and algorithms can provide an advantage in this respect. Macsyma [1] is probably the system with the largest selection, currently. On the other hand, Macsyma has not taken advantage of recent advances such as the extensive use of hash-coding incorporated in the University of Waterloo's Maple [2] system. For the one somewhat artificial benchmark we discuss in this paper, it appears that the Maple system does considerably better than any representation in Macsyma by precisely this mechanism.
Performance and Architectural Issues for String Matching
Authors: Merrill E. Iseman, Dennis E. Shasha
Venue: IEEE Transactions on Computers (1990)

The authors introduce special heuristics to the Knuth-Morris-Pratt algorithm to reduce the time and space required to perform the string matching. They compare their hardware-based approach to the software approaches embodied in the Unix system grep and fgrep commands. Simulation results show that the hardware approach can provide a 25-500-fold performance improvement, depending on the complexity of the query, and that it is fast enough, even in the presence of variable-length 'don't cares' to keep up with a 20-million character/second disk. The approach compares favorably to other hardware designs in speed and space. The proposed hardware implementation requires 10 kB of one cycle static memory, 28 single-character comparators, four 16-b adders, and control logic for four finite-state machines with a term-matcher controller. After that, additional hardware produces negligible performance improvements for queries with up to 80 terms, about half of which have variable-length 'don't cares'.
Object lens: a &ldquo;spreadsheet&rdquo; for cooperative work
Authors: Kum-Yew Lai, Thomas W. Malone
Venue: Proceedings of the 1988 ACM conference on Computer-supported cooperative work (1988)

Object Lens allows unsophisticated computer users to create their own cooperative work applications using a set of simple, but powerful, building blocks. By defining and modifying templates for various semistructured objects, users represent many different kinds of information. By creating semiautonomous agents, users specify rules for automatically processing this information in different situations. The combination of these primitives provides a single consistent interface that integrates facilities for object-oriented databases, hypertext, electronic messaging, and rule-based intelligent agents. To illustrate the power of this combined approach, we describe several simple examples of applications (such as task tracking, intelligent message routing, and database retrieval) that we have developed in this framework.
The Task of the Referee
Authors: Alan Jay Smith
Venue: Computer (1990)

Computer researchers have a professional obligation to referee the work of others. This article tells you how to evaluate a paper and write a report using common standards and procedures. It focuses on research papers in applied areas of computer science and engineering, such as systems architecture, hardware, communications, and performance evaluation, but most of the discussion is generally applicable; separate sections consider research proposals and survey and tutorial papers.
On the productivity of recursive list definitions
Authors: Ben A. Sijtsma
Venue: ACM Transactions on Programming Languages and Systems (TOPLAS) (1989)

Several related notions of the productivity are presented for functional languages with lazy evaluation. The notion of productivity captures the idea of computability, of progress of infinite-list programs. If an infinite-list program is productive, then every element of the list can be computed in finite &ldquo;time.&rdquo; These notions are used to study recursive list definitions, that is, lists defined by l where l = fl. Sufficient conditions are given in terms of the function f that either guarantee the productivity of the list or its unproductivity. Furthermore, a calculus is developed that can be used in verifying that lists defined by l where l = f I are productive. The power and the usefulness of our theory are demonstrated by several nontrivial examples. Several observations are given in conclusion.
Views of SDE: automation of engineering and engineering of automation
Authors: W. Stinson
Venue: ACM SIGSOFT Software Engineering Notes (1989)

This paper develops an abstract model of software development and then explores its implications for software development environments (SDEs). It explores the automation of engineering, i.e., what to automate, and the engineering of automation, i.e., how to automate. It explains the automation of engineering by deriving basic automation paradigms from the development model. It explains the engineering of automation in terms of principles which guide the architecture of an SDE.
Designing families of data types using exemplars
Authors: Wilf R. LaLonde
Venue: ACM Transactions on Programming Languages and Systems (TOPLAS) (1989)

Designing data types in isolation is fundamentally different from designing them for integration into communities of data types, especially when inheritance is a fundamental issue. Moreover, we can distinguish between the design of families&mdash;integrated types that are variations of each other&mdash;and more general communities where totally different but cohesive collections of types support specific applications (e.g., a compiler). We are concerned with the design of integrated families of data types as opposed to individual data types; that is, on the issues that arise when the focus is intermediate between the design of individual data types and more general communities of data types. We argue that design at this level is not adequately served by systems providing only class-based inheritance hierarchies and that systems which additionally provide a coupled subtype specification hierarchy are still not adequate. We propose a system that provides an unlimited number of uncoupled specification hi erarchies and illustrate it with three: a subtype hierarchy, a specialization/generalization hierarchy, and a like hierarchy. We also resurrect a relatively unknown Smalltalk design methodology that we call programming-by-exemplars and argue that it is an important addition to a designer's grab bag of techniques. The methodology is used to show that the subtype hierarchy must be decoupled from the inheritance hierarchy, something that other researchers have also suggested. However, we do so in the context of exemplar-based systems to additionally show that they can already support the extensions required without modification and that they lead to a better separation between users and implementers, since classes and exemplars can be related in more flexible ways. We also suggest that class-based systems need the notion of private types if they are to surmount their current limitations. Our points are made in the guise of designing a family of List data types. Among these is a new variety of lists that have never been previously published: prefix-sharing lists. We also argue that there is a need for familial classes to serve as an intermediary between users and the members of a family.
Code scheduling and register allocation in large basic blocks
Authors: J. R. Goodman, W.-C. Hsu
Venue: Proceedings of the 2nd international conference on Supercomputing (1988)

We discuss the issues about the interdependency between code scheduling and register allocation. We present two methods as solutions: (1) an integrated code scheduling technique; and (2) a DAG-driven register allocator. The integrated code scheduling method combines two scheduling techniques&mdash;one to reduce pipeline delays and the other to minimize register usage&mdash;into a single phase. By keeping track of the number of available registers, the scheduler can choose the appropriate scheduling technique to schedule a better code sequence. The DAG-driven register allocator uses a dependency graph to assist in assigning registers; it introduces much less extra dependency than does an ordinary register allocator. For large basic blocks, both approaches were shown to generate more efficient code sequences than conventional techniques in the simulations.
Using feedback to control tree saturation in multistage interconnection networks
Authors: S. L. Scott, G. S. Sohi
Venue: ACM SIGARCH Computer Architecture News (1989)

In this paper, we propose the use of feedback schemes in multiprocessors which use an interconnection network with distributed routing control. We show that by altering system behavior so as to minimize the occurrence of a performance-degrading situation in the network, the overall throughout of the system can be improved. As an example, we have considered the problem of tree saturation caused by hot spots in multistage interconnection networks. Tree saturation degrades the performance of all processors in a system, including those not participating in the hot spot activity. We see that feedback schemes can be used to control tree saturation, reduce degradation to memory requests that are not to the hot memory module and increase overall system bandwidth. As a companion to feedback schemes, damping schemes are also considered. Simulation studies presented in this paper show that feedback schemes can improve overall system performance significantly in many cases.
Cedar Fortran and other Vector and parallel Fortran dialects
Authors: M. D. Guzzi, J. P. Hoeflinger, D. A. Padua, D. H. Lawrie
Venue: Proceedings of the 1988 ACM/IEEE conference on Supercomputing (1988)

The introduction of vector processors and multiprocessors punctuate the most dramatic changes in Fortran and its dialects. The emerging generation of supercomputers utilize both vector processing and multiprocessing simultaneously. The challenge is to provide language constructs and software tools that will allow the programmer to easily exploit the capabilities of the machine. This paper will outline the development of vector and multiprocessor language constructs in Fortran. The significant architectures, their languages, and optimizers will be described. The paper concludes with a description of Cedar Fortran, the language for the Cedar Multiprocessor under development at the University of Illinois, Urbana-Champaign. Cedar is a hierarchical, shared-memory, vector multiprocessor. As such, its language, Cedar Fortran, contains many of the language features that will be described for vector processors and multiprocessors.
Definition and Analysis of Hardware- and Software-Fault-Tolerant Architectures
Authors: Jean-Claude Laprie, Christian Béounes
Venue: Computer (1990)

A structured definition of hardware- and software-fault-tolerant architectures is presented. Software-fault-tolerance methods are discussed, resulting in definitions for soft and solid faults. A soft software fault has a negligible likelihood or recurrence and is recoverable, whereas a solid software fault is recurrent under normal operations or cannot be recovered. A set of hardware- and software-fault-tolerant architectures is presented, and three of them are analyzed and evaluated. Architectures tolerating a single fault and architectures tolerating two consecutive faults are discussed separately. A sidebar addresses the cost issues related to software fault tolerance. The approach taken throughout is as general as possible, dealing with specific classes of faults or techniques only when necessary.
Ada translation tools development: automatic translation of FORTRAN to Ada
Authors: M. Parsian, B. Basdell, Y. Bhayat, I. Caldwell, N. Garland, B. Jubanowsky, J. Robinette
Venue: ACM SIGAda Ada Letters (1988)

The problem addressed is how existent syntactically and semantically correct FORTRAN programs can be translated into Ada programs (library units). We present a system to find one possible form of translation. Our algorithm for translator system can be applied to generate translators from any source high level language into target language (Ada source code).
A random binary tree generator
Authors: H. W. Martin, B. J. Orr
Venue: Proceedings of the 17th conference on ACM Annual Computer Science Conference (1989)

Let B(N) denote the set of all binary trees that have N nodes. A procedure for randomly generating the trees in B(N) such that each tree is equally likely to occur, that is an unbiased random generator, is given which runs in O(N) time, requires very little storage, and uses a system of arithmetic no larger than is required to represent the number U itself. Previous unbiased random binary tree generators, based on inverse rank functions, ran in O(N log N) time and required multiple precision arithmetic capable of handling numbers of the order of magnitude of the cardinality of B(N).
Timing analysis in a logic synthesis environment
Authors: N. Weiner, A. Sangiovanni-Vincentelli
Venue: Proceedings of the 26th ACM/IEEE Design Automation Conference (1989)

A goal of a logic synthesis system is the automatic generation of area optimised designs that meet timing requirements. The design process involves repeated timing analyses followed by appropriate modifications. We present fast new algorithms for system level timing analysis and for the generation of timing constraints to guide the re-design of portions of combinational logic. Our systematic approach correctly models designs that incorporate level sensitive latches controlled by multi-frequency, as well as simple multi-phase, clocks. A new feature is that the minimum number of settling times are evaluated for the nodes of combinational networks with input transitions controlled by different clock signals. The computer program Hummingbird uses the algorithms presented. Hummingbird interfaces with other programs in the Berkeley Synthesis System through the OCT data base. For a digital signal processing chip, comprising 3681 standard cells, timing analysis is performed in 14.87 CPU seconds on a VAX 8800 running the ULTRIX operating system.
CSG-EESI: A New Solid Representation Scheme and a Conversion Expert System
Authors: S. Xie, T. W. Calvert
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1988)

A representation scheme is proposed for describing 3-D mechanical parts and structural bodies which are formed from planes and quadratic faces. Since the method combines features of the constructive solid geometry (CSG) representation and an extension of the enhanced (EESI) spherical image representation (ESI), it is designated the CSG-EESI. In this scheme, the body model is roughly divided into two levels: the higher level corresponds to a restricted CSG tree that contains the structural information describing how the various subparts form the body; the lower level contains the geometric information for those simple subparts and represents them by an extension of enhanced spherical images. The scheme can be used both as the medium between pictorial models and relational models and as an internal model to facilitate the recognition of bodies. An expert system written in C-PROLOG on a VAX 11/750 is presented that converts BR-like models into the CSG-EESI representation is presented.
Report on the Collaborative Technology Developers' Workshop
Authors: M. J. Abel, G. L. Rein
Venue: ACM SIGCHI Bulletin (1989)

The second Conference on Computer-Supported Cooperative Work (CSCW '88) was held September 26--28, 1988, in Portland, Oregon. This was a conference on how groups work and how technology (especially computers) can help them work. The term "CSCW" refers to this new multi--disciplinary field, which draws on the expertise and collaboration of many different specialists, including social scientists, anthropologists, and computer scientists. "Groupware" is another popular word for CSCW technology.
Calibrated deflection system for electron beam testing
Authors: M. Brisegård, M. Lidell, S. Steier, G. Stille
Venue: Microelectronic Engineering (1988)

A method for fast access of an electron beam probe to integrated circuit nodes is presented. Application of the method results in increased capacity for Electron Beam Testers (EBT). The method utilizes a calibrated postlens magnetic deflection unit. This unit can move the electron beam to any location within an area of 6 by 6 mm within 200 microseconds. The precision of the system allows the beam to be positioned well within 4 micron metallic conductors.
On a Constraint Equation for the Estimation of Displacement Rates in Image Sequences
Authors: H.-H. Nagel
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1989)

The commonly used constraint equation Delta g/sup T/u+g/sub t/=0 for the estimation of optical flow can only be justified by assumptions that are, in general, far too restrictive for image sequences of real world scenes. B.G. Schunck (1985, 86) recently argued that a constraint equation for the estimation of what he called image flow has to include a term containing the divergence of this image flow without presenting, however, a stringent derivation based on perspective projection from 3-D scene space. The present author derives a constraint equation based on a combination of perspective projection and notions from differential geometry. In addition, he demonstrates the quantitive effects of taking into account radiometric considerations based on the use of Lambertian reflection properties and isotropic illumination in scene space.
Modeling input processes with Johnson distributions
Authors: D. J. DeBrota, R. S. Dittus, J. J. Swain, S. D. Roberts, J. R. Wilson
Venue: Proceedings of the 21st conference on Winter simulation (1989)

This paper provides an introduction to the Johnson translation system of probability distributions, and it describes methods for using the Johnson system to model input processes in simulation experiments. For situations in which little or no sample information is available, we have developed a visual interactive method to estimate bounded Johnson distributions subjectively; and we have implemented this technique in VESIFIT, a public-domain software package. For fitting all types of Johnson distributions based on sample data, we have implemented several new statistical-estimation methods as well as some standard techniques in FITTR1, another public-domain software package. We present several examples illustrating the use of VISIFIT and FITTR1 for simulation input modeling.
Techniques and experiences capturing requirements for several real-time applications
Authors: L. Zucconi
Venue: ACM SIGSOFT Software Engineering Notes (1989)

This paper discusses techniques used and experiences gained while gathering and documenting the functional requirements for five control systems and one engineering database system. The majority of this work was performed on several projects at Lawrence Livermore National Laboratory over a period of three years.Teams of from one to four engineers gathered requirements for a large laser control system, several separator control and diagnostic systems, a security system, and an engineering database system. These systems required gathering requirements data from physicists, electrical, mechanical and material engineers, and in the case of one security application system, police officers. The paper discusses team structure, the advantages of larger teams and problems with one person teams. It defines the interview, document, feedback and critique cycle used for requirements acquisition.All but one of these systems are operating. The paper concludes with a discussion on the usefulness of the requirements during system development.
Algorithm 666: Chabis: a mathematical software package for locating and evaluating roots of systems of nonlinear equations
Authors: Michael N. Vrahatis
Venue: ACM Transactions on Mathematical Software (TOMS) (1988)

CHABIS is a mathematical software package for the numerical solution of a system of n nonlinear equations in n variables. First, CHABIS locates at least one solution of the system within an n-dimensional polyhedron. Then, it applies a new generalized method of bisection to this n-polyhedron in order to obtain an approximate solution of the system according to a predetermined accuracy. In this paper we briefly describe the user interface to CHABIS and present several details of its implementation, as well as an example of its usage.