ppxscal/embedding_network huggingface dataset:
Time-Optimal Network Queue Control: The Case of Multiple Congested Nodes
Authors: Mahadevan Iyer, Wei Kang Tsai
Venue: Proceedings of the Parallel and Distributed Systems, Tenth International Conference (2004)

The fundamental problem of time-optimalqueue control in packet-switched networks is how toadjust source rates in time after network disturbances sothat the network queue sizes converge to desired values inthe minimum time, while ensuring that always at least onelink remains fully utilized in every flow's path. Thisnonlinear feedback control problem had been solved in aprevious paper [Time-Optimal Network Queue Control: The Case of a Single Congested Node] for a single queue in a single congestednode and the solution proven robust to queue size andbandwidth estimation errors. In this paper, we generalizethat solution to a general network of flows crisscrossingqueues, with link delays being arbitrary.The solution, derived for desired queue sizes of 0, turnsout to be simple: two computationally simple conditions onthe source rate control, viz. QRE-feasibility and maximallyutilizing property are sufficient to ensure time-optimality,regardless of the packet scheduling scheme used inside thenetwork nodes.
Bot Software Spreads, Causes New Worries
Authors: Laurianne McLaughlin
Venue: IEEE Distributed Systems Online (2004)

Bot software sounds a bit like a low-budget horror movie, but itýs quietly making trouble and stealing data right now, using millions of PCs worldwide.
Exploring Virtual Network Selection Algorithms in DSM Cache Coherence Protocols
Authors: Mainak Chaudhuri Mark Heinrich
Venue: IEEE Transactions on Parallel and Distributed Systems (2004)

Distributed shared memory (DSM) multiprocessors typically require disjoint networks for deadlock-free execution of cache coherence protocols. This is normally achieved by implementing virtual networks with the help of virtual channels or virtual lanes multiplexed on a single physical network. To keep the coherence protocol simple, messages are usually assigned to virtual lanes in a predefined static manner based on a cycle-free lane assignment dependence graph. However, this static split of virtual networks (such as request and reply networks) may lead to underutilization of certain virtual networks while saturating the other networks. In this paper, we explore different static and dynamic schemes to select the virtual lanes for outgoing messages and mix the load among them without restricting any particular type of message to be carried only by a particular virtual network. We achieve this by exposing the selection algorithms to the coherence protocol itself, so that it can inject messages into selected virtual lanes based on some local information, and still enjoy deadlock-freedom. Our execution-driven simulation on five applications from the SPLASH-2 suite shows that as the system scales, the virtual network selection algorithms play an important role. For 128-node systems, our dynamic selection algorithm speeds up parallel execution by as much as 22 percent over an optimized baseline system running a modified SGI Origin 2000 protocol. We also explore how network latency, the number of message buffers per virtual lane, and the depth of network interface output queues affect the relative performance of various virtual lane selection algorithms.
Memory Aware HLS and the Implementation of Ageing Vectors
Authors: Gwenole Corre, Eric Senn, Nathalie Julien, Eric Martin
Venue: Proceedings of the Digital System Design, EUROMICRO Systems (2004)

We introduce a new approach to take into account the memory architecture and the memory mapping in behavioral synthesis. We formalize the memory mapping as a set of constraints for the synthesis, and defined a Memory Constraint Graph and an accessibility criterion to be used in the scheduling step. We present a new strategy for implementing signals (ageing vectors). We formalize the maturing process and explain how it may generate memory conflicts over several iterations of the algorithm. The final Compatibility Graph indicates the set of valid mappings for every signal. Several experiments are performed with our HLS tool GAUT. Our scheduling algorithm exhibits a relatively low complexity that permits to tackle complex designs in a reasonable time.
Taming Lambda's for Applications: The OptIPuter System Software
Authors: Andrew A. Chien
Venue: Proceedings of the Parallel and Distributed Systems, Tenth International Conference (2004)

Dense wavelength-division multiplexing (DWDM),dark fiber, and low-cost optical switches provide thetechnological capability for private, high bandwidthcommunication. However, achieving any substantialapplication benefit from use of these resources isdauntingly complex and error prone. These emergingenvironments are often called lambda grids.
Characterization and failure analysis of MEMS: high resolution optical investigation of small out-of-plane movements and fast vibrations
Authors: W. Merlijn van Spengen, R. Puers, R. Mertens, Ingrid De Wolf
Venue: Microsystem Technologies (2004)

A high resolution optical tool is required to investigate the mechanical behavior and failure modes of micro-electromechanical systems (MEMS). We report on the possibilities of a newly developed optical characterization tool for MEMS devices. Both slow movements and fast mechanical vibrations up to 15 MHz can be monitored. The instrument can perform an imaging operation for a complete image at once by employing laser TV holography, which is a large advantage over scanning laser Doppler vibrometers. For vibration measurements, this new, interference based instrument uses a beat frequency between object excitation and reference beam excitation. A normal CCD camera is used to obtain 3D images and movies of periodic mechanical motions of MEMS devices. Excitation can be by means of a PZT, or by using electronic excitation. We show that the instrument is a very useful tool for the characterization and failure analysis of MEMS devices.
Retrieval of Isomorphic Substructures in Crystallographic Databases
Authors: Hans-Joachim Klein
Venue: Proceedings of the 16th International Conference on Scientific and Statistical Database Management (2004)

Local bindings of atoms are often modeled by coordinationpolyhedra with vertices representing ligands, i.e. atomswith strong bonds to a central atom. Neighbouring polyhedramay be linked by vertices, edges, or faces depending onwhether their central atoms share one, two, or more atomsas ligands. Substructures formed by linked polyhedra areof considerable interest for studying crystal structures. Weintroduce a finite graph representation for infinite polyhedralnetworks and show how to build an index for a givenset of model structures such that the retrieval of isomorphicsubstructures is supported. A system has been implementedproviding this functionality on an interactive graphical Webinterface.
Synchroscalar: A Multiple Clock Domain, Power-Aware, Tile-Based Embedded Processor
Authors: John Oliver, Ravishankar Rao, Paul Sultana, Jedidiah Crandall, Erik Czernikowski, Leslie W. Jones IV, Diana Franklin, Venkatesh Akella, Frederic T. Chong
Venue: Proceedings of the 31st annual international symposium on Computer architecture (2004)

We present Synchroscalar, a tile-based architecture forembedded processing that is designed to provide the flexibilityof DSPs while approaching the power efficiency ofASICs. We achieve this goal by providing high parallelismand voltage scaling while minimizing control and communicationcosts. Specifically, Synchroscalar uses columnsof processor tiles organized into statically-assignedfrequency-voltage domains to minimize power consumption.Furthermore, while columns use SIMD control to minimizeoverhead, data-dependent computations can besupported by extremely flexible statically-scheduled communicationbetween columns.We provide a detailed evaluation of Synchroscalar includingSPICE simulation, wire and device models, synthesisof key components, cycle-level simulation, andcompiler- and hand-optimized signal processing applications.We find that the goal of meeting, not exceeding, performancetargets with data-parallel applications leads todesigns that depart significantly from our intuitions derivedfrom general-purpose microprocessor design. Inparticular, synchronous design and substantial global interconnectare desirable in the low-frequency, low-powerdomain. This global interconnect supports parallelizationand reduces processor idle time, which are critical to energyefficient implementations of high bandwidth signalprocessing. Overall, Synchroscalar provides programmabilitywhile achieving power efficiencies within 8-30X ofknown ASIC implementations, which is 10-60X better thanconventional DSPs. In addition, frequency-voltage scalingin Synchroscalar provides between 3-32% power savingsin our application suite.
Edge spinning algorithm for implicit surfaces
Authors: M. Cermak, V. Skala
Venue: Applied Numerical Mathematics (2004)

This paper presents a new fast method for polygonization of implicit surfaces. Our method put emphasis on the shape of triangles generated and on the polygonization speed. The main advantages of the triangulation presented are simplicity and the stable features that can be used for future expansion. The implementation is not complicated and only the standard data structures are used. This algorithm is based on the surface tracking scheme and it is compared with the well-known marching cubes algorithm that is based on the similar principle. The presented algorithm is accelerated by the space subdivision which is an effective technique to speed-up any geometric of this type.
Array organization in parallel memories
Authors: Mayez Al-Mouhamed
Venue: International Journal of Parallel Programming (2004)

The bandwidth mismatch between processor and main memory is one major throughput limiting problem. Although streamed computations have predictable access patterns their references have little temporal locality and are generally too long to cache. A memory and compiler co-optimization aimed at reducing low-level memory accesses using software and hardware locality optimizations is presented. We propose a scalable and predictable parallel memory based on a compiler synthesis of storage schemes for multi-dimensional arrays that are accessed by an arbitrary but known set of data access patterns. Using algebra of non-singular Boolean matrices, we present analysis of conflict-free access to (1) parallel memories, and (2) alignment networks. Finding a multi-pattern storage scheme is one NP-complete problem. An effective compiler heuristic is proposed for finding a storage matrix that minimizes overall memory access time. This applies to arbitrary linear patterns and arbitrary alignment networks. It is shown that the proposed storage scheme finds an optimal storage scheme for parallel (1) FFT, and (2) bitonic sorting. The proposed storage scheme outperforms statically optimized storages in the case of power-of-2 multi-stride access. The case of non power-of-2 strides is also addressed. The performance and scalability of the proposed parallel memory and its predictable access time are presented using numerical and multimedia algorithms. It is shown that a memory utilization above 83% is achieved by our storage scheme for 64 memories, which largely outperforms previous proposals. Our approach provides a tool for matching the storage pattern with the data access patterns needed for embedded systems running streamed computations with predictable data access patterns.
Interactive and Continuous Collision Detection for Avatars in Virtual Environments
Authors: Stephane Redon, Young J. Kim, Ming C. Lin, Dinesh Manocha, Jim Templeman
Venue: Proceedings of the IEEE Virtual Reality 2004 (2004)

We present a fast algorithm for continuous collision detectionbetween a moving avatar and its surrounding virtualenvironment.We model the avatar as an articulated bodyusing line-skeletons with constant offsets and the virtual environmentas a collection of polygonized objects.Given theposition and orientation of the avatar at discrete time steps,we use an arbitrary in-between motion to interpolate thepath for each link between discrete instances.We boundthe swept-space of each link using a swept volume (SV) andcompute a bounding volume hierarchy to cull away linksthat are not in close proximity to the objects in the virtualenvironment.We generate the SV's of the remaining linksand use them to check for possible interferences and estimatethe time of collision between the surface of the SV andthe objects in the virtual environment.Furthermore, we usegraphics hardware to perform collision queries on the dynamicallygenerated swept surfaces.Our overall algorithmrequires no precomputation and is applicable to general articulatedbodies.We have implemented the algorithm ona 2.4 GHz Pentium IV PC with NVIDIA GeForce FX 5800graphics card and applied it to an avatar with 16 links, movingin a virtual environment composed of hundreds of thousandsof polygons.Our prototype system is able to detect allcontacts between the moving avatar and the environment in10-30 milliseconds.
A projection scheme to stability analysis of discrete T-S fuzzy models
Authors: Chih-Peng Huang, Yau-Tarng Juang
Venue: Mathematics and Computers in Simulation (2004)

The paper deals with the stability analysis of the discrete Takagi-Sugeno's (T-S) fuzzy model, which can describe a class of nonlinear systems. Based on the alternating projection method, the useful projection operators are derived firstly. And we thus proposed an efficient analysis algorithm for analyzing the stability. The effectiveness of the proposed method is illustrated by the numerical examples.
Verifying Web Applications Using Bounded Model Checking
Authors: Yao-Wen Huang, Fang Yu, Christian Hang, Chung-Hung Tsai, D. T. Lee, Sy-Yen Kuo
Venue: Proceedings of the 2004 International Conference on Dependable Systems and Networks (2004)

The authors describe the use of bounded modelchecking (BMC) for verifying Web application code.Vulnerable sections of code are patched automaticallywith runtime guards, allowing both verification andassurance to occur without user intervention. Modelchecking techniques are relatively complex compared tothe typestate-based polynomial-time algorithm (TS) weadopted in an earlier paper, but they offer threebenefits-they provide counterexamples, more precisemodels, and sound and complete verification. Comparedto conventional model checking techniques, BMC offers amore practical approach to verifying programscontaining large numbers of variables, but requires fixedprogram diameters to be complete. Formalizing Webapplication vulnerabilities as a secure information flowproblem with fixed diameter allows for BMC applicationwithout drawback. Using BMC-producedcounterexamples, errors that result from propagations ofthe same initial error can be reported as a single grouprather than individually. This offers two distinct benefits.First, together with the counterexamples themselves, theyallow for more descriptive and precise error reports.Second, it allows for automated patching at locationswhere errors are initially introduced rather than atlocations where the propagated errors cause problems.Results from a TS-BMC comparison test using 230 open-sourceWeb applications showed a 41.0% decrease inruntime instrumentations when BMC was used. In the 38vulnerable projects identified by TS, BMC classified theTS-reported 980 individual errors into 578 groups, witheach group requiring a minimal set of patches for repair.
Implicit java array bounds checking on 64-bit architecture
Authors: Chris Bentley, Scott A. Watterson, David K. Lowenthal, Barry Rountree
Venue: Proceedings of the 18th annual international conference on Supercomputing (2004)

Interest in using Java for high-performance parallel computing has increased in recent years. One obstacle that has inhibited Java from widespread acceptance in the scientific community is the language requirement that all array accesses must be checked to ensure they are within bounds. In practice, array bounds checking in scientific applications may increase execution time by more than a factor of 2. Previous research has explored optimizations to statically eliminate bounds checks, but the dynamic nature of many scientific codes makes this difficult or impossible.Our approach is instead to create a new Java implementation that does not generate explicit bounds checks. It instead places arrays inside of Index Confinement Regions (ICRs), which are large, isolated, mostly unmapped virtual memory regions. Any array reference outside of its bounds will cause a protection violation; this provides implicit bounds checking. Our results show that our new Java implementation reduces the overhead of bounds checking from an average of 63% to an average of 9% on our benchmarks.
Incremental rendering of deformable trimmed NURBS surfaces
Authors: Gary K. L. Cheung, Rynson W. H. Lau, Frederick W. B. Li
Venue: Proceedings of the ACM symposium on Virtual reality software and technology (2003)

Trimmed NURBS surfaces are often used to model smooth and complex objects. Unfortunately, most existing hardware graphics accelerators cannot render them directly. Although there are a lot of methods proposed to accelerate the rendering of such surfaces, majority of them are based on tessellation, which is developed primarily for handling non-deforming objects. For an object that may deform in run-time, such as clothing, facial expression, human and animal character, the tessellation process will need to be performed repeatedly while the object is deforming. However, as the tessellation process is very time consuming, interactive display of deforming objects is difficult. This explains why deformable objects are rarely used in virtual reality applications. In this paper, we present a efficient method for incremental rendering of deformable trimmed NURBS surfaces. This method can handle both trimmed surface deformation and trimming curve deformation. Experimental results show that our method performs significantly faster than the method used in OpenGL.
Classes of Discrete Convexity Properties
Authors: Gabriela Cristescu, Liana Lupsa
Venue: Discrete Computational Geometry (2004)

In the general first-level classification of the convexity properties for sets, discrete convexities appear in more classes. A second-level classification identifies more subclasses containing discrete convexity properties, which appear as approximations either of classical convexity or of fuzzy convexity. First, we prove that all these convexity concepts are defined by segmental methods. The type of segmental method involved in the construction of discrete convexity determines the subclass to which it belongs. The subclasses containing the convexity properties that have discrete particular cases are also presented.
A High-level Interconnect Power Model for Design Space Exploration
Authors: Pallav Gupta, Lin Zhong, Niraj K. Jha
Venue: Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design (2003)

In this paper, we present a high-level power model toestimate the power consumption in semi-global and global interconnects.Such interconnects are used for communications between logic modules,clock distribution networks, and power supply rails. The main purposeof our model is to set forward a simple methodology to efficiently obtainfirst-order estimates of interconnect power in early stages of the designprocess. Hence, the objective is to provide designers and/or high-leveldesign automation tools with a way to quickly explore the design spaceand weed out architectures whose interconnect power requirements donot meet the allocated power budget. In addition to switching power,which includes inter-wire coupling, our model also considers power dueto vias and repeaters. Our experimental results show that in comparisonto an accurate low-level model, the error in our method in estimatingtotal switching power is only 6% (while the speedup is three-to-fourorders of magnitude), and an estimate of the numbers of vias (hence, viapower) is within 3% agreement of that obtained for designs synthesizedby commercial tools. Furthermore, we develop a probabilistic segmentlength distribution model for cases in which Rent's rule is inadequate. Byanalyzing the netlists of a set of complex designs, we have been able tovalidate our segment length distribution model. The novelty of this worklies in the introduction of a high-level interconnect modeling methodologyin which it is possible to efficiently compute all the major sources ofpower consumption in interconnects and hence, enable interconnect-aware,high-level design space exploration.
Learning effective ranking functions for newsgroup search
Authors: Wensi Xi, Jesper Lind, Eric Brill
Venue: Proceedings of the 27th annual international ACM SIGIR conference on Research and development in information retrieval (2004)

Web communities are web virtual broadcasting spaces where people can freely discuss anything. While such communities function as discussion boards, they have even greater value as large repositories of archived information. In order to unlock the value of this resource, we need an effective means for searching archived discussion threads. Unfortunately the techniques that have proven successful for searching document collections and the Web are not ideally suited to the task of searching archived community discussions. In this paper, we explore the problem of creating an effective ranking function to predict the most relevant messages to queries in community search. We extract a set of predictive features from the thread trees of newsgroup messages as well as features of message authors and lexical distribution within a message thread. Our final results indicate that when using linear regression with this feature set, our search system achieved a 28.5% performance improvement compared to our baseline system.
Compression of Samplable Sources
Authors: Luca Trevisan, Salil Vadhan, David Zuckerman
Venue: Proceedings of the 19th IEEE Annual Conference on Computational Complexity (2004)

We study the compression of polynomially samplablesources. In particular, we give efficientprefix-free compression and decompression algorithmsfor three classes of such sources (whosesupport is a subset of {0, 1}^n).1. We show how to compress sources X samplableby logspace machines to expectedlength H(X) + O(1).Our next results concern flat sources whose supportis in P.2. If H(X) ¿ k = n - O(log n), we showhow to compress to length k + ¿ ¿ (n - k)for any constant ¦¿ > 0; in quasi-polynomialtime we show how to compress to length k +O(polylog log(n - k)) even if k = n - polylog(n).3. If the support of X is the witness set for a self-reducibleNP relation, then we show how tocompress to expected length H(X) + 4.
Tim Tom
Venue: ACM SIGGRAPH 2003 video review on Electronic theater program on Electronic theater program - Volume 144 (2003)

Two animated characters, Tim and Tom want to meet, but their creator does not readily oblige. A homage to the cartoon film, with touches from the Thaumatrope, the studio Aardman, and the influences of Tex Avery. Copyright held by creator.