ppxscal/embedding_network huggingface dataset:
Practical Verification of Embedded Software
Authors: Jørgen Staunstrup, Henrik Reif Andersen, Henrik Hulgaard, Jørn Lind-Nielsen, Kim G. Larsen, Gerd Behrmann, Kåre Kristoffersen, Arne Skou, Henrik Leerberg, Niels Bo Theilgaard
Venue: Computer (2000)

Advances in processor speed, memory capacities, sensors, and peripherals have enabled the inexpensive fabrication of sophisticated products. They range from simple controllers in applications such as mobile phones and hi-fi equipment to highly complex software in cars and airplanes. Unfortunately, the lack of good design methods and tools is a major bottleneck in the development of these products, particularly those with a short life cycle such as consumer electronics and household appliances.Developing embedded software for large, complicated applications requires models that are both intellectually manageable and physically realizable. Choosing a modeling technique is a compromise between conflicting goals. Models must not only be easy to comprehend and construct, but they also must be practicable and provide platforms for analysis.Using a new verification algorithm called the compositional backward technique, the authors demonstrate that they can exhaustively verify even the largest industrial applications-- comprising more than 1,000 components--in a few minutes on a standard PC.
Issues in the Design of Medical Ontologies Used for Knowledge Sharing
Authors: A. Burgun, G. Botti, P. Le Beux
Venue: Journal of Medical Systems (2001)

Recent work in Medical Informatics is exploring the development and the use of formal ontologies as a way of specifying content-specific agreements for the sharing and reuse of knowledge among several computer systems. We describe the role of ontologies in supporting knowledge sharing activities in medicine Principles for the design of ontologies have been proposed, mainly in other domains: these principles include parsimony, clarity, representation of categories versus terms, and coherence. We analyze how and why these principles can or cannot be applied from case studies from medical systems. Regarding the fact that most of medical concepts are empirical, selected design decisions are discussed. An alternative representation choice consists in mapping principled general core ontologies and domain ontologies.
Performance Analysis of Two Different Algorithms for Ethernet-FDDI Interconnection
Authors: G. Bucci, A. Del Bimbo, S. Santini
Venue: IEEE Transactions on Parallel and Distributed Systems (1994)

Fiber Distributed Data Interface (FDDI) local area networks (LAN's) are used either ashigh-speed links between computers and peripherals, or as backbones for lower-speedLAN's, such as Ethernet and Token Ring. The availability of such a high-speed channel will lead to the implementation of high-performance distributed environments spread over a wider area than that allowed by commonly used LAN's. The performance of suchdistributed environments will strongly depend on that of the interconnecting devices. Inthis paper, two different algorithms for packet filtering are discussed, referring to bridgesinterconnecting Ethernet LAN's to FDDI backbones. Algorithm performance is comparedwith respect to 1) the traffic increase produced on a local Ethernet, and 2) the maximumallowed traffic on remote Ethernets.
Improved Approximations of Crossings in Graph Drawings and VLSI Layout Areas
Authors: Guy Even, Sudipto Guha, Baruch Schieber
Venue: SIAM Journal on Computing (2003)

We give improved approximations for two classical embedding problems: (i) minimizing the number of crossings in a drawing on the plane of a bounded degree graph; and (ii) minimizing the VLSI layout area of a graph of maximum degree four. These improved algorithms can be applied to improve a variety of VLSI layout problems. Our results are as follows. (i) We compute a drawing on the plane of a bounded degree graph in which the sum of the numbers of vertices and crossings is O(log3 n)$ times the optimal minimum sum. This is a logarithmic factor improvement relative to the best known result. (ii) We compute a VLSI layout of a graph of maximum degree four in a square grid whose area is O(log4 n)$ times the minimum layout area. This is an O(log2 n) improvement over the best known long-standing result.
State of the Art in Parallel Search Techniques for Discrete Optimization Problems
Authors: Ananth Grama, Vipin Kumar
Venue: IEEE Transactions on Knowledge and Data Engineering (1999)

Discrete optimization problems arise in a variety of domains, such as VLSI design, transportation, scheduling and management, and design optimization. Very often, these problems are solved using state space search techniques. Due to the high computational requirements and inherent parallel nature of search techniques, there has been a great deal of interest in the development of parallel search methods since the dawn of parallel computing. Significant advances have been made in the use of powerful heuristics and parallel processing to solve large-scale discrete optimization problems. Problem instances that were considered computationally intractable only a few years ago are routinely solved currently on server-class symmetric multi-processors and small workstation clusters. Parallel game-playing programs are challenging the best human minds at games like chess. In this paper, we describe the state of the art in parallel algorithms used for solving discrete optimization problems. We address heuristic and nonheuristic techniques for searching graphs as well as trees, and speedup anomalies in parallel search that are caused by the inherent speculative nature of search techniques.
Open-loop video distribution with support of VCR Functionality
Authors: Ernst W. Biersack, Alain Jean-Marie, Philippe Nain
Venue: Performance Evaluation (2002)

Scalable video distribution schemes have been studied for quite some time. For very popular videos, open-loop broadcast schemes have been devised that partition each video into segments and periodically broadcast each segment on a different channel. Open-loop schemes provide excellent scalability as the number of channels required is independent of the number of clients. However, open-loop schemes typically do not support VCR functions. We will show for open-loop video distribution how, by adjusting the rate at which the segments are transmitted, one can provide VCR functionality. We consider deterministic and probabilistic support of VCR functions: depending on the segment rates chosen, the VCR functions are supported either 100% of the time or with very high probability. For the case of probabilistic support of PLAY and Fast-forward (FF) only, we model the reception process as a semi-Markov accumulation process. We are able to calculate a lower bound on the probability of successfully executing FF actions.
Evolution of the Electronic Design Automation Industry
Authors: Ronald A. Rohrer
Venue: IEEE Design Test (1988)

The author discusses the last 25 years of the evolution of electronic design automation (EDA). He first examines the industry's dynamics and describes how it has coped with the increasing complexity of circuits. He argues that survival in the electronic design automation industry depends on how well it can produce a sequence of properly planned follow-on products and addresses the evolution of the hardware and software platforms on which these products reside.
DAG-Map: Graph-Based FPGA Technology Mapping for Delay Optimization
Authors: Kuang-Chien Chen, Jason Cong, Yuzheng Ding, Andrew B. Kahng, Peter Trajmar
Venue: IEEE Design Test (1992)

A graph-based technology-mapping package for delay optimization in lookup-table-based field programmable gate array (FPGA) designs is presented. The algorithm, DAG-Map, carries out technology mapping and delay optimization on the entire Boolean network, instead of decomposing it into fan-out-free trees. As a preprocessing phase of DAG-Map, a general algorithm called DMIG, which transforms an arbitrary n-node network into a two-input network with only an O(1) factor increase in network depth, is introduced. A matching-based technique that minimizes area without increasing network delay, and is used in the postprocessing phase of DAG-Map is discussed. DAG-Map is compared with previous FPGA mapping algorithms on a set of logic synthesis benchmarks. The experimental results show that, on average, DAG-Map reduces both network delay and the number of look-up tables.
Tensor product multiresolution analysis with error control for compact image representation
Authors: Sergio Amat, Francesc Aràndiga, Albert Cohen, Rosa Donat
Venue: Signal Processing (2002)

A class of multiresolution representations based on nonlinear prediction is studied in the multivariate context based on tensor product strategies. In contrast to standard linear wavelet transforms, these representations cannot be thought of as a change of basis, and the error induced by thresholding or quantizing the coefficients requires a different analysis. We propose specific error control algorithms which ensure a prescribed accuracy in various norms when performing such operations on the coefficients. These algorithms are compared with standard thresholding, for synthetic and real images.
Invariant Fitting of Planar Objects by Primitives
Authors: Klaus Voss, Herbert Suesse
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1997)

The determination of invariant characteristics is an important problem in pattern recognition. Many invariants are known which have been obtained by the method of normalization. In this paper, we introduce a new approach of fitting planar objects by primitives using the method of normalization (for instance: fitting by lines, triangles, rectangles, circles, ellipses, super-quadrics, etc.). Objects and primitives are described by features, for example, by moments. The main advantage is that the normalization process provides us with a canonical frame of the object and the primitive. Therefore, the fit is invariant with respect to the transformation used. By this new method, an analytical fitting of non-analytical objects can be achieved, for example, fitting by polygons. Furthermore, the numerical effort can be reduced drastically by normalizing of the object and the primitive.
Behavior Analysis of Internal Feedback Bridging Faults in CMOS Circuits
Authors: Yukiya Miura, Shuichi Seno
Venue: Journal of Electronic Testing: Theory and Applications (2002)

In this paper we analyze fault behaviors of internal feedback bridging faults. To investigate their behaviors, we use a simple circuit model consisting of 2-input NAND gate and NOT gate. From analysis results, we find that behaviors of internal feedback bridging faults are more complex than those of external feedback bridging faults. We expose that they cause IDDQ-only failure, internal latch and internal oscillation as well as latch and oscillation behavior. These phenomena are caused by the following facts: formation of an electrically conducting feedback loop and connection of the feedback loop with the circuit output depend on input values of the circuit, and the feedback loop is often alive only within the circuit. We also discuss methods for detecting this kind of fault.
Uncertainty Minimization in the Localization of Polyhedral Objects
Authors: V. Caglioti
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1994)

A straightforward method is presented for the determination of the optimal sensor exploration in the localization of a polyhedral object, whose geometry is known. Optimality is intended in the sense of the a posteriori covariance matrix of the object position and orientation parameters. The method consists in decomposing the problem into simpler subproblems, each one relative to a single planar face of the object. It requires reasonable processing time, i.e. comparable with the sensor activation time.
Berger Check Prediction for Array Multipliers and Array Dividers
Authors: J. -C. Lo, S. Thanawastien, T. R. N. Rao
Venue: IEEE Transactions on Computers (1993)

The authors present closed-form check-predicting equations for deriving Berger checks (J.M. Berger, 1961) for array multipliers and array dividers, respectively. Braun's array multipliers and Guild's array dividers are examined. Example check circuits are also presented.
Exploiting Lookahead in Parallel Simulation
Authors: Y. B. Lin, E. D. Lazowska
Venue: IEEE Transactions on Parallel and Distributed Systems (1990)

Lookahead is the ability of a process to predict its future behavior. The feasibility of implicit lookahead for non-FCFS stochastic queuing systems is demonstrated. Several lookahead exploiting techniques are proposed for round-robin (RR) system simulations. An algorithm that generates lookahead in O(1) time is described. Analytical models and experiments are constructed to evaluate these techniques. A lookahead technique for preemptive priority (PP) systems is evaluated using an analytical model. The performance metric for these techniques is the lookahead ratio, which is correlated with other performance measures of more direct interest, such as speedup. The analyses show that using implicit lookahead can significantly improve the lookahead ratios of RR and PP system simulations.
A Hypertext System to Manage Software Life-Cycle Documents
Authors: Pankaj K. Garg, Walt Scacchi
Venue: IEEE Software (1990)

The Documents Integration Facility, an environment based on objects and relationships between objects that was constructed for the development, use, and maintenance of large-scale systems and their life-cycle documents, is presented. DIF helps integrate and manage the documents produced and used throughout the life cycle: requirements specifications, functional specifications, architectural designs (structural specifications), detailed designs, source code, testing information, and user and maintenance manuals. DIF supports information management in large systems where there is much natural-language text. The documentation method used by DIF and DIF's structure are described. How DIF is used is discussed, and the DIF environment is examined. Issues that were encountered in the design of DIF are considered.
Standardization: Art or Discipline?
Authors: Carl F. Cargill
Venue: IEEE Micro (1998)

Standardization - that is, the making of a product or service common across an industry - is one of those uneasy practices which sits on the cusp between marketing and engineering. What was once an engineering discipline is now heavily - and directly - influenced by non-technology issues. This article examines the current state of the practice of standardization, from the organizations to the practitioners to the environment, and draws the conclusion that standardization is neither technical nor a discipline.
Analysis of Testable PLA Designs
Authors: Xi-An Zhu, Melvin A. Breuer
Venue: IEEE Design Test (1988)

A framework is presented for evaluating methods of testing programmable logic arrays (PLAs), and the attributes of 25 test design methodologies are tabulated. PLA testing problems are first examined, and several test-generation algorithms are briefly described. Techniques for designing testable designs are examined, namely, special coding, parity checking, signature analysis, divide and conquer, and fully testable PLAs. The attributes that make a good testable design are then discussed. They fall into four categories: (1) testability characteristics; (2) effect on original design; (3) requirements of the application environment; and (4) design costs, i.e. how difficult it is to implement the technique.
Congestion aware layout driven logic synthesis
Authors: Thomas Kutzschebauch, Leon Stok
Venue: Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design (2001)

In this paper, we present novel algorithms that effectively combine physical layout and early logic synthesis to improve overall design quality. In addition, we employ partitioning and clustering algorithms to achieve faster turn around times.With the increasing complexity of designs, the traditional separation of logic and physical design leads to sub-optimal results as the cost functions employed during logic synthesis do not accurately represent physical design information. While this problem has been addressed extensively, the existing solutions apply only simple synthesis transforms during physical layout and are generally unable to reverse decisions made during logic minimization and technology mapping, that have a major negative impact on circuit structure.In our novel approach, we propose congestion aware algorithms for layout driven decomposition and technology mapping, two of the steps that affect congestion the most during logic synthesis, to effectively decrease wire length and improve congestion. In addition, to improve design turn-around-time and handle large designs, we present an approach in which synthesis partitioning and placement clustering co-exist, reflecting the different characteristics of logical and physical domain.
VIS Speeds New Media Processing
Authors: Marc Tremblay, J. Michael O'Connor, Venkatesh Narayanan, Liang He
Venue: IEEE Micro (1996)

The Visual Instruction Set (VIS), first introduced with the UltraSPARC-I microprocessor, is described from an Instruction Set Architecture (ISA) standpoint. Besides covering the functionality of each instruction individually, we look at a few widely used algorithms that can be sped up significantly (2-7X) by using VIS. The software environment surrounding VIS is also described.
The residually weakly primitive geometries of S5&#x00D7; 2
Authors: Philippe Cara, Dimitri Leemans
Venue: Discrete Mathematics (2002)

We classify all firm and residually connected coset geometries satisfying the intersection property (IP)2, and on which the group S5 × 2 acts flag-transitively and residually weakly primitively. This work was motivated by a study of the Ivanov-Shpectorov coset geometry for the O'Nan sporadic simple group (see Buekenhout, Leemens, J. Combin. Theory Ser. A 85(2) (1999) 148). The importance of having a list of residually weakly primitive coset geometries for S5 × 2 is also shown by Buekenhout et al. (in: A. Pasini et al. (Eds.), Groups and Geometries, Birkhäuser, Basel 1998, pp. 39-54) and Buekenhout and Dony (Bull. Soc. Math. Belg. XLII (1990) 471). We extend the concept of direct sum introduced by Valette in (Simon Stevin 56(3) (1982) 167) to coset geometries and show that all coset geometries are either direct sums of coset geometries of S5 and 2 satisfying the same properties or are extensions of lower rank coset geometries given by a theorem of Leemans' (see Leemons, Master's Thesis, Vol. 1, Université Libre de Bruxelles, 1994.).
Integrating Software Engineering in Introductory Computing Courses
Authors: Grant A. Cheston, Jean-Paul Tremblay
Venue: IEEE Software (2002)

This article describes an introductory course for an undergraduate computing student. This course aims to integrate data structures and software engineering. In addition to requiring students to complete several varied assignments, some involving analysis, modeling, and software design, the coursework has them work in teams on a significant software design project. To help students complete this project, they use a 10-step process to develop an object-oriented software system. The authors discuss the philosophy of giving such a course and the concepts taught.
Numerical Methods for p-Harmonic Flows and Applications to Image Processing
Authors: Luminita A. Vese, Stanley J. Osher
Venue: SIAM Journal on Numerical Analysis (2002)

We propose in this paper an alternative approach for computing p-harmonic maps and flows: instead of solving a constrained minimization problem on SN-1, we solve an unconstrained minimization problem on the entire space of functions. This is possible, using the projection on the sphere of any arbitrary function. Then we show how this formulation can be used in practice, for problems with both isotropic and anisotropic diffusion, with applications to image processing, using a new finite difference scheme.
Complex dynamics and synchronization of a duopoly game with bounded rationality
Authors: H. N. Agiza, A. S. Hegazi, A. A. Elsadany
Venue: Mathematics and Computers in Simulation (2002)

A dynamic Cournot game characterized by players with bounded rationality is modeled by two non-linear difference equations. The stability of the equilibria of the discrete dynamical system is analyzed. As some parameters of the model are varied, the stability of Nash equilibrium is lost and the complex chaotic behavior occurs. Synchronization of two dynamic Cournot duopoly games are considered. In the case of identical players, such dynamical system becomes symmetric, and this implies that synchronized dynamics can be obtained by a simpler one-dimensional model whose dynamics summarizes the common behavior of the two identical players.
Analysis of Processor Allocation in Multiprogrammed, Distributed-Memory Parallel Processing Systems
Authors: S. K. Setia, M. S. Squillante, S. K. Tripathi
Venue: IEEE Transactions on Parallel and Distributed Systems (1994)

A main objective of scheduling independent jobs composed of multiple sequential tasks in shared-memory and distributed-memory multiprocessor computer systems is theassignment of these tasks to processors in a manner that ensures efficient operation ofthe system. Achieving this objective requires the analysis of a fundamental tradeoffbetween maximizing parallel execution, suggesting that the tasks of a job be spreadacross all system processors, and minimizing synchronization and communicationoverheads, suggesting that the job's tasks be executed on a single processor. Theauthors consider a class of scheduling policies that represent the essential aspects ofthis processor allocation tradeoff, and model the system as a distributed fork-joinqueueing system. They derive an approximation for the expected job response time,which includes the important effects of various parallel processing overheads (such astask synchronization and communication) induced by the processor allocation policy.
Adaptive parallel computing on heterogeneous networks with mpC
Authors: Alexey Lastovetsky
Venue: Parallel Computing (2002)

The paper presents a new advanced version of the mpC parallel language. The language was designed specially for programming high-performance parallel computations on heterogeneous networks of computers.The advanced version allows the programmer to define at runtime all the main features of the underlying parallel algorithm, which have an impact on the application execution performance, namely, the total number of participating parallel processes, the total volume of computations to be performed by each of the processes, the total volume of data to be transferred between each pair of the processes, and how exactly the processes interact during the execution of the algorithm. Such an abstraction of parallel algorithm is called a network type in mpC.Given a network type, the programmer can define a network object of this type and describe in details all the computations and communications to be performed on the network object. The mpC programming system uses the information extracted from the network-type definition together with information about the actual performance of the executing network to map the processes of the parallel program to this network in such a way that leads to its better execution time.In addition, the programmer can use a special operator, time of, which predicts the total time of the algorithm execution on the underlying hardware without its real execution. That feature allows the programmer to write such a parallel program that can follow different parallel algorithms to solve the same problem, making choice at runtime depending on the particular executing network and its actual performance.The paper describes both the language model of parallel algorithm and the model of executing parallel environment used by the mpC programming system. It also discusses principles of the implementation of mapping mpC network objects to the computing network.