ppxscal/embedding_network huggingface dataset:
A quadratic time algorithm for the minmax triangulation (extended abstract)
Authors: Herbert Edelsbrunner, Tiow Seng Tan
Venue: Proceedings of the 32nd annual symposium on Foundations of computer science (1991)

It is shown that a triangulation of a set of n points in the plane that minimizes the maximum edge length can be computed in time O(n/sup 2/). The algorithm is reasonably easy to implement and is based on the theorem that there is a triangulation with minmax edge length that contains the relative neighborhood graph of the points as a subgraph. With minor modifications the algorithm works for arbitrary normed metrics.
Socially responsible computing II: first steps on the path to positive contributions
Authors: Ben Shneiderman
Venue: ACM SIGCHI Bulletin (1992)

Now that we are past the initial emotional responses to the LA riots, maybe we can use these tragic events as a stimulus for innovative and constructive efforts. Computing professionals have been active in social causes on an individual basis and in some large projects, but with the growing maturity of our industry we can promote larger initiatives and accept greater responsibility.
Objects with logic
Authors: Mamdouh H. Ibrahim, Fred A. Cummins
Venue: Proceedings of the 1990 ACM annual conference on Cooperation (1990)

This paper describes an approach to the integration of logic and object programming where predicates, logic expressions, and a generalized search protocol that support Prolog-like reasoning are implemented as an integral part of an object-oriented language. This logic programming facility provides 1) domain-based reasoning, 2) functional arguments, 3) support of the abstraction power of object-oriented languages, and 4) matching of complex object patterns, none of which are available in Prolog. The integration does not require logic facts to be local predicates in the environment; instead, facts are represented as objects in the application model. This permits recursive reasoning and backtracking on predicates that are defined on different domains. The design concepts and implementation of this approach are presented and its application is illustrated by an example.
The Heisenberg uncertainty principle and the halting problem
Authors: P. A. Laplante
Venue: ACM SIGACT News (1991)

In this paper it is suggested that the Heisenberg Uncertainty Principle, normally applied to physical systems, can be applied directly to show that the Halting Problem is unsolvable. Although the Heisenberg Uncertainty Principle has appeared in the context of software engineering before [3] it is used in analogy there. As far as the author can determine, this would be the first direct application of the Uncertainty Principle to the solution of a problem in computer science.
A Specificational Approach to High Level Program Monitoring and Measuring
Authors: Yingsha Liao, Donald Cohen
Venue: IEEE Transactions on Software Engineering (1992)

Program monitoring and measuring is the activity of collecting information about the execution characteristics of a program. Although this activity is occasionally supported by special-purpose hardware, it is normally done by adding instrumentation code to the program so that it collects interesting data as it runs. Unfortunately, this alteration is itself a difficult task involving all the complexities of programming. Given some questions to be answered, the programmer must determine what data must be collected, determine where in the program those data can be collected, and add code to the program to collect that data and to process it to produce the desired results. The goal of the work described is to automate the process. A high-level program monitoring and measuring system is presented. The system provides a high-level specification language to let programmers specify what they want to know about their program's execution. It automatically generates an augmented program whose execution produces both the results of the original program and answers to the specified questions.
Augmenting a Window System with Speech Input
Authors: Chris Schmandt, Mark S. Ackerman, Debby Hindus
Venue: Computer (1990)

Some necessary background in speech recognition and window systems is given, with an analysis of how they might be combined. Xspeak, a navigation application, and its operation and a field study of its use are described. With Xspeak, window navigation tasks usually performed with a mouse can be controlled by voice. An improved version, Xspeak II, which incorporates a language for translating spoken commands, is introduced.
Can parallel algorithms enhance serial implementation
Authors: Uzi Vishkin
Venue: ACM SIGACT News (1991)

Consider the serial emulation of a parallel algorithm. The thesis presented in this informal paper is rather broad. It suggests that such a serial emulation has the potential advantage of running on a serial machine faster than a standard serial algorithm for the same problem.The main concrete observation is very simple: just before the serial emulation of a round of the parallel algorithm begins, the whole list of memory addresses needed during this round is readily available; and, we can start fetching these addresses from secondary memories.This enables to prefetch the data that will be needed in the next "time window", perhaps by means of pipelining and have them ready at the fast memories when requested by the CPU. Thereby, utilization of commonly used memory management systems will be theoretically enhanced. Another (considerably less orthodox) implementation approach will result in abandoning locality of references, in favor of a drastically different approach: distribute memory addresses at random over memory modules, as has been proposed in the context of implementing the parallel-random-access machine (PRAM) design space.It is too early to reach conclusions regarding the significance of the thesis of this paper. Serious attempts to follow it up are needed to determine its usefulness. Parts of this paper are intentionally written in an informal way, suppressing issues that will have to be resolved in the context of a concrete implementation. My general intention is to encourage colleagues to: (i) suggest other specific approaches, and (ii) explore opportunities for taking advantage of the fine structure of parallel programs well beyond concrete suggestions made in the paper.The full paper is available as UMIACS TR 91-145, from the Institute for Advanced Computer Studies, University of Maryland, College Park, Maryland 20742--3251.
Performance Evaluation of Scene Registration and Stereo Matching for Artographic Feature Extraction
Authors: Yuan C. Hsieh, David M. McKeown,  Jr., Frederic P. Perlant
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1992)

Three major areas in the development of competent 3-D scene interpretation system are discussed. First, the importance of accurate automatic scene registration and the difficulty in automated extraction and matching of scene reference points are described. Second, the authors describe two stereo matching algorithms, S1, which is an area-based matcher previously used in the SPAM system, and S2, which is a feature-based matching algorithm based on hierarchical waveform matching. Third, the authors introduce several performance evaluation metrics that made it possible to measure the quality of the overall scene recovery, the building disparity estimate, and the quality and sharpness of the building delineations. Such manually generated scene reference models are critical for understanding strengths and weaknesses of various matching algorithms and in the incremental development of improvements to existing algorithms. Experiments were performed on difficult examples of aerial imagery.
A coherent projection approach for direct volume rendering
Authors: Jane Wilhelms, Allen Van Gelder
Venue: ACM SIGGRAPH Computer Graphics (1991)

Direct volume rendering offers the opportunity to visualize all of a three-dimensional sample volume in one image. However, processing such images can be very expensive and good quality high-resolution images are far from interactive. Projection approaches to direct volume rendering process the volume region by region as opposed to ray-casting methods that process it ray by ray. Projection approaches have generated interest because they use coherence to provide greater speed than ray casting and generate the image in a layered, informative fashion. This paper discusses two topics: First, it introduces a projection approach for directly rendering rectilinear, parallel-projected sample volumes that takes advantage of coherence across cells and the identical shape of their projection. Second, it considers the repercussions of various methods of integration in depth and interpolation across the scan plane. Some of these methods take advantage of Gouraud-shading hardware, with advantages in speed but potential disadvantages in image quality.
Highly fault-tolerant sorting circuits
Authors: Tom Leighton, Yuan Ma, C. Greg Plaxton
Venue: Proceedings of the 32nd annual symposium on Foundations of computer science (1991)

The problem of constructing a sorting circuit that will work well even if a constant fraction of its comparators fail at random is addressed. Two types of comparator failure are considered: passive failures, which result in no comparison being made (i.e., the items being compared are output in the same order that they are input), and destructive failures, which result in the items being output in the reverse of the correct order. In either scenario, it is assumed that each comparator is faulty with some constant probability rho , and a circuit is said to be fault-tolerant if it performs some desired function with high probability given that each comparator fails with probability rho . One passive and two destructive circuits are constructed.
A message passing coprocessor for distributed memory multicomputers
Authors: Jiun-Ming Hsu, Prithviraj Banerjee
Venue: Proceedings of the 1990 ACM/IEEE conference on Supercomputing (1990)

This paper presents the architecture, methodology and performance evaluation of a message passing coprocessor (MPC) which can accelerate message communication in a distributed memory multicomputer. The MPC is a microprogrammable processor which off-loads the CPU of the burden of communication and speeds up the software processing by directly executing message passing instructions in microcode. It supports process scheduling, message buffer management, and fast buffer copying. The most unique feature of the MPC is that it performs software caching for expected message destinations and buffers. The MPC works closely with a virtual channel router [1] which is a smart routing controller and supports virtual channels and cached circuits. The software and hardware overhead of communication can be reduced significantly by these two processors. The performance is confirmed by trace driven simulation.
The Influence of the Los Alamos and Livermore National Laboratories on the Development of Supercomputing
Authors: Donald MacKenzie
Venue: IEEE Annals of the History of Computing (1991)

The Los Alamos and Lawrence Livermore National Laboratories have been important sponsors of, and customers for, supercomputers-high-performance scientific computers. The laboratories played an important part in establishing speed of floating-point arithmetic (rather than, say, at logical operations) as the performance criterion defining supercomputing. But their more specific influence on the evolution of computer architecture has been limited by the diversity and classified nature of their central computational tasks, together with the expansion of supercomputer use elsewhere.
Relative scheduling under timing constraints
Authors: David Ku, Gionvanni De Micheli
Venue: Proceedings of the 27th ACM/IEEE Design Automation Conference (1991)

Scheduling techniques are used in high-level synthesis of integrated circuits. Traditional scheduling techniques assume fixed execution delays for the operations. For the synthesis of ASIC designs that interface with external signals and events, operations with unbounded delays, i.e. delays unknown at compile time, must also be considered. We present a relative scheduling technique that supports operations with fixed and unbounded delays. The technique satisfies the timing constraints imposed by the user, which places bounds between the activation of operations. We analyze a novel property called well-posedness of timing constraints that is used to identify consistency of constraints in the presence of unbounded delay operations, and present an approach to relative scheduling that yields a minimum schedule that satisfies the constraints, or detects if no schedule exists, in polynomial time.
Global hardware synthesis from behavioral dataflow descriptions
Authors: Josef Scheichenzuber, Werner Grass, Ulrich Lauther, Sabine März
Venue: Proceedings of the 27th ACM/IEEE Design Automation Conference (1991)

This paper reports on a new bottom-up synthesis technique for general behavioral descriptions. Our technique extends traditional straight-line code synthesis by allowing hierarchical, block-structured dataflow graphs with block-level parallelism. Program path probabilities are taken into account; and both high-level synthesis and design-space exploration are addressed.
A study of control flow and data dependency interface (abstract)
Authors: Narayan C. Debnath
Venue: Proceedings of the 1990 ACM annual conference on Cooperation (1990)

The results described in this paper is motivated by the desire to study the interface between the structure of control flow and data dependencies. The complexity of the control flow and the complexity of the data dependencies are necessarily intertwined. An increase in the complexity of the data dependencies will result from an increase in control flow complexity. A control flow alternation construct can result in an increase in the number of variable definitions that may be referenced. This increase in the number of referable definitions may extend far beyond the range of the alternation construct. In order to study the interface between control structure and data dependencies, a general abstraction describing the static structure of software is developed. The abstraction proposed in this paper is called Generalized Program Graph (GPG) and is a synthesis of the control flow graph and data dependency graph. Various sources of data dependencies in a program and live definitions of variables are discussed. An algorithm for constructing a GPG from a given source program in imperative languages is included. Some results of the analysis of the GPG structures and the interface between control and data dependency complexity are also presented. It appears that the GPG can directly be applied in the studies of software module interconnection complexity. Other important theoretical and practical application of the GPG are discussed. Because the GPG includes both the control flow and data dependency information in one abstraction, it can be used as an implementation model for the development of measurement and analysis tools for empirical research.
Object oriented programming techniques to replace software components on the fly in a running program
Authors: Manfred Stadel
Venue: ACM SIGPLAN Notices (1991)

Many systems, e. g. embedded systems, process control systems, or telecommunication switching systems cannot be stopped running to modify and extend their software. It must be possible to replace software components on the fly by new versions while the program is running. It is shown how object oriented programming techniques can help do design and implement a software system such that its components are dynamically replaceable at run time.
Integrating expert systems with group decision support systems
Authors: Milam W. Aiken, Olivia R. Liu Sheng, Douglas R. Vogel
Venue: ACM Transactions on Information Systems (TOIS) (1991)

Expert systems are powerful tools that serve as adjuncts to decision making and have found wide applicability in a wide variety of areas. Integrating expert systems with group decision support systems has the potential to enhance the quality and effeciency of group communication, negotiation, and collaborative work. This paper examines possible synergies between the two technologies and provides a survey of current partially-integrated systems. Finally, a prototype design of a highly-integrated system is described with directions for further research.
A General Technique for Designing Totally Self-Checking Checker for 1-out-of-N Code with Minimum Gate Delay
Authors: D. L. Tao, C. R. P. Hartmann, P. K. Lala
Venue: IEEE Transactions on Computers (1992)

An efficient technique for designing a totally self-checking checker for 1/n code (n
A parallel object-oriented total architecture: A&ndash;NET
Authors: Takanobu Baba, Tsutomu Yoshinaga, Tohru Iijima, Yoshifumi Iwamoto, Masahiro Hamada, Mitsuru Suzuki
Venue: Proceedings of the 1990 ACM/IEEE conference on Supercomputing (1990)

A-NET is a parallel object-oriented total architecture for highly parallel computation. Starting with a computation model, this paper describes parallel constructs of the designed language, called A-NETL; the A-NETL oriented machine instruction set architecture; the hardware organization of a node processor, which consists of a 40-bit processing element and a router; and a local operating system on each of the node processors. Statistics for the designed language and the machine are derived from experimental results. Keywords: parallel object-oriented, total architecture, multicomputer, processing element, router, parallel operating system
A multi-service storage architecture
Authors: Jean Bacon, Ken Moody, Sue Thomson, Tim Wilson
Venue: ACM SIGOPS Operating Systems Review (1991)

This paper gives an overview of a new Multi Service Storage Architecture (MSSA) which has been designed for a broader range of clients than traditional file servers and in particular for emerging clients such as real-time multimedia applications.The proposed architecture is an open hierarchy of services in which both unstructured and structured data are supported. Any client which requires high performance and a minimal service can use the lowest level directly. A principal-specific capability scheme is used for protection.The paper outlines the designs of the two basic components of the architecture, the Low Level and High Level Storage Services (LLSS and HLSS). The LLSS has a traditional storage service interface, at the byte sequence or subsequence level, and exploits non-volatile memory to achieve high performance. The HLSS provides optional support for structured objects through a flexible but efficient storage type generation scheme together with existence control and concurrency control at any required granularity.We have developed tools for performance evaluation which allow us to monitor the LLSS under artificial load generators and benchmarks as well as local applications. As a side effect we can compare the properties of these loads.We outline how the storage services are being used as a basis for a directory service, a database programming language, an integrated virtual memory system and the representation, storage and retrieval of structured multimedia objects with synchronisation between components.
Data Routing Networks for Systolic/Pipeline Realization of Prime Factor Mapping
Authors: Kar-Lik Wong, Wan-Chi Siu
Venue: IEEE Transactions on Computers (1991)

It is pointed out that transformed data computed by systolic/pipeline processors using the data shuffling network recently proposed by T.K. Troung et al. cannot be unscrambled by simply reversing the cyclic row and cyclic column shufflings. This can be amended by the proposed restoration scheme. In addition, efficient architectures for the data routing networks with low circuit complexities are proposed. These form useful building blocks for very-high-throughput hardware realizations.
MemSpy: analyzing memory system bottlenecks in programs
Authors: Margaret Martonosi, Anoop Gupta, Thomas Anderson
Venue: ACM SIGMETRICS Performance Evaluation Review (1992)

To cope with the increasing difference between processor and main memory speeds, modern computer systems use deep memory hierarchies. In the presence of such hierarchies, the performance attained by an application is largely determined by its memory reference behavior&mdash;if most references hit in the cache, the performance is significantly higher than if most references have to go to main memory. Frequently, it is possible for the programmer to restructure the data or code to achieve better memory reference behavior. Unfortunately, most existing performance debugging tools do not assist the programmer in this component of the overall performance tuning task. This paper describes MemSpy, a prototype tool that helps programmers identify and fix memory bottlenecks in both sequential and parallel programs. A key aspect of MemSpy is that it introduces the notion of data oriented, in addition to code oriented, performance tuning. Thus, for both source level code objects and data objects, MemSpy provides information such as cache miss rates, causes of cache misses, and in multiprocessors, information on cache invalidations and local versus remote memory misses. MemSpy also introduces a concise matrix presentation to allow programmers to view both code and data oriented statistics at the same time. This paper presents design and implementation issues for MemSpy, and gives a detailed case study using MemSpy to tune a parallel sparse matrix application. It shows how MemSpy helps pinpoint memory system bottlenecks, such as poor spatial locality and interference among data structures, and suggests paths for improvement.
A Two-Dimensional, Distributed Logic Architecture
Authors: Mary Jane Irwin, Robert Michael Owens
Venue: IEEE Transactions on Computers (1991)

The authors present a novel, very fine grain associative architecture. This architecture maintains both a high degree of flexibility and fine graininess. This is done by reducing each processor to an associative memory cell. Unlike other associative memory processors, this architecture uses a two-dimensional interconnect and a physically compact memory structure. Arithmetic operations are based on the use of a redundant number system. These features provide a high level of performance. This is particularly true for certain two-dimensional problems which can be solved very efficiently on the proposed architecture.
Higher-Order and Modal Logic as a Framework for Explanation-Based Generalization
Authors: Scott Dietzen, Frank Pfenning
Venue: Machine Learning (1992)

Certain tasks, such as formal program development and theorem proving, fundamentally rely upon the manipulation of higher-order objects such as functions and predicates. Computing tools intended to assist in performing these tasks are at present inadequate in both the amount of &lsquo;knowledge&rsquo; they contain (i.e., the level of support they provide) and in their ability to &lsquo;learn&rsquo; (i.e., their capacity to enhance that support over time). The application of a relevant machine learning technique&mdash;explanation-based generalization (EBG)&mdash;has thus far been limited to first-order problem representations. We extend EBG to generalize higher-order values, thereby enabling its application to higher-order problem encodings.Logic programming provides a uniform framework in which all aspects of explanation-based generalization and learning may be defined and carried out. First-order Horn logics (e.g., Prolog) are not, however, well suited to higher-order applications. Instead, we employ &lambda;Prolog, a higher-order logic programming language, as our basic framework for realizing higher-order EBG. In order to capture the distinction between domain theory and training instance upon which EBG relies, we extend &lambda;Prolog with the necessity operator &squ; of modal logic. We develop a meta-interpreter realizing EBG for the extended language, &lambda;&squ; Prolog, and provide examples of higher-order EBG.