ppxscal/embedding_network huggingface dataset:
Reuse: where to begin and why
Authors: R. Holibaugh, S. Cohen, K. Kang, S. Peterson
Venue: Proceedings of the conference on Tri-Ada '89: Ada technology in context: application, development, and deployment (1989)

The Software Engineering Institute (SEI) is interested in identifying the costs and benefits of software reuse to the mission critical computer resource (MCCR) community. In fulfilling this role, we were faced with the need to investigate reuse without making a large investment. This paper examines where to start a reuse activity by describing our initial view of reuse, our decisions on where to begin, what lessons we learned, and finally, our current view. The reuse life cycle described in our final view gives more insight on how and where to implement reuse. It defines the phases of a reuse life cycle that begin with business planning and shows their relationships. For each phase of the reuse life cycle, we give the goals, the outputs, and an approach for achieving the goals. Each organization that is interested in obtaining the benefits of reuse must evaluate reuse in terms of business goals and objectives. Once this evaluation has been made, the life cycle described in the paper provides one approach to achieving the benefits of reuse.
A parallel multiprocessor machine dedicated to relational and deductive data bases
Authors: R. Gonzalez-Rubio, M. Couprie
Venue: Proceedings of the 11th annual international ACM SIGIR conference on Research and development in information retrieval (1988)

Efficiency in databases is a major requirement. This paper presents some solutions to cope with this problem. One solution is to execute operations in parallel: this is done in the &ldquo;Delta Driven Computer&rdquo; DDC, which is a multiprocessor machine with distributed memory dedicated to relational and deductive databases. In DDC, relations are distributed among the nodes of the machine, and the data are processed asynchronously in each node. To do that in an efficient way, a coprocessor, specialized for relational operations, is also proposed. It is called &mgr;SyC, for &ldquo;microprogrammable Symbolic Coprocessor&rdquo;. This paper is divided into two parts. The first part describes DDC, presenting the architecture, the languages, and an original computational model. The second part describes &mgr;SyC, its architecture, instruction set and the data structures used at the &mgr;SyC level.
Graph based retargetable microcode compilation in the MIMOLA design system
Authors: Lothar Nowak
Venue: ACM SIGMICRO Newsletter (1988)

This paper describes a retargetable compiler, which is able to compile programs into the machine code of a specified hardware (target). The target is described at register-transfer structure level by module specifications and netlists. The program can be defined at several levels of abstraction, spanning the range from algorithmic description e.g. PASCAL) down to RT-level behavioural description. If the program is the complete target's behavioural specification the compiler can be used to verify the structural against this behavioural description.
On Fault-Tolerant Structure, Distributed Fault-Diagnosis, Reconfiguration, and Recovery of the Array Processors
Authors: S. H. Hosseini
Venue: IEEE Transactions on Computers (1989)

A study is made of the design of fault-tolerant array processors. It is shown how hardware redundancy can be used in the existing structures in order to make them capable of withstanding the failure of some of the array links and processors. Distributed fault-tolerance schemes are introduced for the diagnosis of the faulty elements, reconfiguration, and recovery of the array. Fault tolerance is maintained by the cooperation of processors in a decentralized form of control without the participation of any type of hardcore or fault-free central controller such as a host computer. Time redundancy is utilized by assigning the functions of the failed processors to fault-free processors.
A parallel algorithm for the quadratic assignment problem
Authors: P. M. Pardalos, J. V. Crouse
Venue: Proceedings of the 1989 ACM/IEEE conference on Supercomputing (1989)

In this paper we present a parallel branch and bound algorithm for the solution of quadratic assignment problems. The algorithm has been coded in VS/FORTRAN and run on an IBM 3090-400E vector multiprocessor. The algorithm is exact and finds all the solutions. Computational results on a variety of test problems are presented.
Investigation of surface-induced latch-up in VLSI CMOS using the laser probe
Authors: J. Quincke, F. Dielacher, K. Goser
Venue: Microelectronic Engineering (1988)

A technique is introduced for latch-up sensitivity measurements with spatial resolution and a report presented on the examination of a CMOS analog VLSI chip using this method.
The A+ programming language, a different APL
Authors: Jean-Jacques Girardot
Venue: ACM SIGAPL APL Quote Quad (1990)

This paper introduces A+, which is an Array Oriented programming language derived from APL, and explains the motivations for creating such a language. After discussing of some problems of current APL system, like the lack of control structures, the usage of dynamic binding, and the difficulty of handling functions, we present how these problems are solved in A+. The most important feature of A+ is that it uses lexical binding rather than dynamic binding as APL does, which solves some old problems of APL while making it a safer language, and offers a new kind of programming style.
Hamiltonian Cycles in the Shuffle-Exchange Network
Authors: W. Liu, T. H. Hildebrandt, R. Cavin,  III
Venue: IEEE Transactions on Computers (1989)

The usefulness of the shuffle-exchange network in parallel processing applications is well established. The optimal embedding of a shuffle-exchange network of a given size depends on the number of cycles of the shuffle permutation of that size. The cost of one method of adding fault-tolerance through reconfigurability depends upon the number of such cycles, and the manner in which they can be connected to form larger cycles. An exact equation for the number of cycles of a shuffle of size 2/sup W/ is presented. That result is used to demonstrate that it is always possible to form a Hamiltonian cycle on all processors in a shuffle-exchange connected array. From this, it is apparent that there are a large number of ways of sharing spare processors among the members of many cycles. Thus, redundancy can be supplied in any strength, from adding on a spare processor, to adding one for each cycle of the shuffle.
Portable IPC on Vanilla Unix
Authors: M. Rain
Venue: ACM SIGPLAN Notices (1989)

The paper describes an efficient, portable implementation of interprocess communication which does not require modifications to the operating system. The ipc facility described supports communication between arbitrary processes even on systems, such as vanilla Unix V, which normally restrict communication to parent/child or sibling process pairs. Interprocess channels are dynamically allocated, and no system configuration or other static specification is required. The implementation embeds a server registry facility to help clients find the ipc channels for servers. A library of C functions supports the creation, allocation, deallocation and maintenance of ipc channels, the registering, unregistering and searching for servers, and a general packet communication protocol for use between processes using ipc. While described in the context of Unix, the mechanism generalizes to any operating system which supports the 'pipe' or 'core file' concept.
Analytical methods for dynamic simulation of non-penetrating rigid bodies
Authors: D. Baraff
Venue: ACM SIGGRAPH Computer Graphics (1989)

A method for analytically calculating the forces between systems of rigid bodies in resting (non-colliding) contact is presented. The systems of bodies may either be in motion or static equilibrium and adjacent bodies may touch at multiple points. The analytic formulation of the forces between bodies in non-colliding contact can be modified to deal with colliding bodies. Accordingly, an improved method for analytically calculating the forces between systems of rigid bodies in colliding contact is also presented. Both methods can be applied to systems with arbitrary holonomic geometric constraints, such as linked figures. The analytical formulations used treat both holonomic and non-holonomic constraints in a consistent manner.
Multiple vs. wide shared bus multiprocessors
Authors: A. Hopper, A. Jones, D. Lioupis
Venue: ACM SIGARCH Computer Architecture News (1989)

In this paper we compare the simulated performance of a family of multiprocessor architectures based on a global shared memory. The processors are connected to the memory through caches that snoop one or more shared buses in crossbar arrangement. We have simulated a number of configurations in order to assess the relative performance of multiple versus wide bus machines, with varying amounts of prefetch. Four programs, with widely differing characteristics, were run on each configuration. The configurations that gave the best all-round results were multiple narrow buses with 4 words of prefetch.
A Hookup Theorem for Multilevel Security
Authors: Daryl McCullough
Venue: IEEE Transactions on Software Engineering (1990)

A security property for trusted multilevel systems, restrictiveness, is described. It restricts the inferences a user can make about sensitive information. This property is a hookup property, or composable, meaning that a collection of secure restrictive systems when hooked together form a secure restrictive composite system. It is argued that the inference control and composability of restrictiveness make it an attractive choice for a security policy on trusted systems and processes.
High-speed implementations of rule-based systems
Authors: A. Gupta, C. Forgy, A. Newell
Venue: ACM Transactions on Computer Systems (TOCS) (1989)

Rule-based systems are widely used in artificial intelligence for modeling intelligent behavior and building expert systems. Most rule-based programs, however, are extremely computation intensive and run quite slowly. The slow speed of execution has prohibited the use of rule-based systems in domains requiring high performance and real-time response. In this paper we explore various methods for speeding up the execution of rule-based systems. In particular, we examine the role of parallelism in the high-speed execution of rule-based systems and study the architectural issues in the design of computers for rule-based systems. Our results show that contrary to initial expectations, the speed-up that can be obtained from parallelism is quite limited, only about tenfold. The reasons for the small speed-up are: (1) the small number of rules relevant to each change to data memory; (2) the large variation in the processing requirements of relevant rules; and (3) the small number of changes made to data memory between synchronization steps. Furthermore, we observe that to obtain this limited factor of tenfold speed-up, it is necessary to exploit parallelism at a very fine granularity. We propose that a suitable architecture to exploit such fine-grain parallelism is a shared-memory multiprocessor with 32-64 processors. Using such a multiprocessor, it is possible to obtain execution speeds of about 3800 rule-firings/set. This speed is significantly higher than that obtained by other proposed parallel implementations of rule-based systems.
A fast uniform astronomical random number generator
Authors: D. Guinier
Venue: ACM SIGSAC Review (1989)

The present method generates machine-independent uniform random sequences of real numbers in the interval (0.,1.) excluding 1. It uses a set of up to 1024 independent multiplicative congruential generators working with: bull; modulii which are chosen prime numbers whose values have been fixed according to the positive 31-bit positive integer arithmetic available and in the form of 2.P'+1, where P's are also primes. bull; multipliers which are selected from one of their corresponding primitive elements as multipliers to achieve each full cycle independently.The "astronomical" maximum periodicity can be considered as infinite: O (106021); it can be adjusted if required by the user in the sequential version RAN01 or statistically reaching the maximum in the improved "stagger" version DAN01.An "acceptable" composite period is estimated to be O (10189) for a set of only 32 of such independent generators: this fact could find a nice application in the realization of efficient hash-functions in smart cards.An implementation in structured FORTRAN 77 shows very good results in terms of statistical proprieties, velocity and periodicity.
Spreadsheet-based interactive graphics: from prototype to tool
Authors: Nicholas Wilde, Clayton Lewis
Venue: Proceedings of the SIGCHI conference on Human factors in computing systems: Empowering people (1990)

The NoPumpG prototype [7,8] suggested that the spreadsheet model of computation could simplify the creation of some types of interactive graphical application when compared with other approaches. We report here experience in developing an enhanced follow-on system, NoPumpII, and describe three applications developed using it. We conclude that (1) the potential advantages of the spreadsheet model are realized in this application experience, (2) revisions to the prototype design have permitted an increase in the complexity and scale of applications, and (3) there remain limitations in the current design which, if redressed, would further enlarge the scope of application. More generally we conclude that alternative computational models are an important area of exploration for HCI research.
Active memory for text information retrieval
Authors: Y. H. Ng, S. P.V. Barros
Venue: Proceedings of the 11th annual international ACM SIGIR conference on Research and development in information retrieval (1988)

A Symbolic Associative Processor (SAP), capable of supporting parallel Keyword Match and Record Match functions, is proposed to select and streamline textual data for information retrieval. Consequently, high volume text data could be analysed on-the-fly before being channelled to CPU, and thus, cushion the impact of Von Neumann bottleneck commonly experienced in applications requiring high I/O bandwidth. This paper identifies some of the system requirements to support text information retrieval using SAP with the aid of simplified examples.
PCLOS: a critical review
Authors: A. Paepcke
Venue: ACM SIGPLAN Notices (1989)

This paper uses the persistent object system PCLOS to survey some problems and benefits of object persistence. The system is analyzed along several relevant dimensions. PCLOS provides object persistence for an object-oriented language. The insights gained on desirable and detrimental components of the system are presented. The intent is to outline some of the expected and unexpected problems encountered in the construction of support for object persistence.
Hierarchical registers for scientific computers
Authors: J. A. Swensen, Y. N. Patt
Venue: Proceedings of the 2nd international conference on Supercomputing (1988)

Simulations of scientific programs running on traditional scientific computer architectures show that execution with hundreds of registers can be more than twice as fast as execution with only eight registers. In addition, execution with a small number of fast registers and hundreds of slower registers can be as fast as execution with hundreds of fast registers. A hierarchical organization of fast and slow registers is presented, register-allocation strategies are discussed, and a novel, indirect, register-addressing mechanism is described.
Council decision of July 26, 1988
Authors: CORPORATE Council of the European Communities
Venue: Communications of the ACM (1990)

concerning the establishment of a plan of action for setting up an information services market (88/524/EEC)
From a functional point of view: a framework for extensions to APL
Authors: M. Gfeller
Venue: ACM SIGAPL APL Quote Quad (1987)

A preliminary framework for investigating certain extensions to APL is presented. This framework allows classification of some past and future language extensions according to their desirability from a functional point of view. Object classes and syntax are the main themes.
The p-group generation algorithm
Authors: E. A. O'Brien
Venue: Journal of Symbolic Computation (1990)

The theory and implementation of an algorithm used in generating descriptions of p-groups aredescribed. Some applications and details of the performance of the algorithm are provided.
An analytic model for parallel Gaussian elimination on a binary N-Cube architecture
Authors: V. A. F. Almeida, L. W. Dowdy, M. R. Leuze
Venue: Proceedings of the third conference on Hypercube concurrent computers and applications - Volume 2 (1989)

This paper summarizes an analytical technique which predicts the time required to execute a given parallel program, with given data, on a given parallel architecture. For illustration purposes, the particular parallel program chosen is parallel Gaussian elimination and the particular parallel architecture chosen is a binary n-cube. The analytical technique is based upon a product-form queuing network model which is solved using an iterative method. The technique is validated by comparing performance predictions produced by the model against actual hypercube measurements.
Mathematical aspects of various methods for sampling from classical distributions
Authors: U. Dieter
Venue: Proceedings of the 21st conference on Winter simulation (1989)

Simulations were one of the first subjects J.v. Neumann had in mind for applying computers. He recom- mended some methods for generating [0,1)-uniformly distributed random numbers which are out of use today. However, his ideas for sampling from non-uniform distributions are still widely used. Since his 1951-paper is rather short, improvements and generalisations of his ideas have been found in the meantime. They will be discussed in this paper.
Synergistic use of direct manipulation and natural language
Authors: P. R. Cohen, M. Dalrymple, D. B. Moran, F. C. Pereira, J. W. Sullivan
Venue: Proceedings of the SIGCHI conference on Human factors in computing systems: Wings for the mind (1989)

This paper shows how the integration of natural language with direct manipulation produces a multimodal interface that overcomes limitations of these techniques when used separately. Natural language helps direct manipulation in being able to specify objects and actions by description, while direct manipulation enables users to learn which objects and actions are available in the system. Furthermore, graphical rendering and manipulation of context provides a partial solution to difficult problems of natural language anaphora.
JACK: a toolkit for manipulating articulated figures
Authors: Cary B. Phillips, Norman I. Badler
Venue: Proceedings of the 1st annual ACM SIGGRAPH symposium on User Interface Software (1988)

The problem of positioning and manipulating three dimensional articulated figures is often handled by ad hoc techniques which are cumbersome to use. In this paper, we describe a system which provides a consistent and flexible user interface to a complex representation for articulated figures in a 3D environment. Jack is a toolkit of routines for displaying and manipulating complex geometric figures, and it provides a method of interactively manipulating arbitrary homogeneous transformations with a mouse. These transformations may specify the position and orientation of figures within a scene or the joint transformations within the figures themselves. Jack combines this method of 3D input with a flexible and informative screen management facility to provide a user-friendly interface for manipulating three dimensional objects.
Interstitial Redundancy: An Area Efficient Fault Tolerance Scheme for Large Area VLSI Processor Arrays
Authors: A. D. Singh
Venue: IEEE Transactions on Computers (1988)

In the proposed scheme, spare PEs are located at interstitial sites within the array. Each spare can functionally replace any one of the neighboring primary PEs that are connected to it. Because spares are physically close to the PE that they replace, restructured interconnections are short, minimizing performance degradation. This structure can incorporate different levels of redundancy depending on how many of the interstitial sites are used to locate spares, and also how many spares are placed at each site. The author gives a polynomial time algorithm for assigning operational spares to failed primary PEs. He also gives area efficient layouts for such structures, and designs for implementing the switching network needed for reconfiguration. A procedure for deciding the optimum level of redundancy so as to maximize chip area utilization is also shown. The main attractive features of interstitial redundancy are short (fixed length) PE interconnections and high utilization of failure-free PEs. The analysis shows that for a wide range of array sizes and PE survival probabilities, 45-55 percent utilization of failure-free PEs on the chip can be achieved.
Interactive program improvement via EAVE: an expert adviser for vectorization
Authors: P. Bose
Venue: Proceedings of the 2nd international conference on Supercomputing (1988)

An example of a state-of-the-art high-end mainframe is the IBM 3090 VF; its associated compiler, the IBM VS Fortran (version 2) compiler, incorporates some of the latest techniques in automatic vectorization and code optimization. Advances in compiler technology not withstanding, a potential limitation is the &ldquo;knowledge gap&rdquo; which exists between the typical end user and the compiler/machine sub-system. In particular, the user often does not know how to write source code which will result in generation of efficient, high performance object code. In this paper, we address the issue of providing interactive aids for program development and transformation as a means to bridge this knowledge gap. We show how heuristic program changes, guided by the knowledge of a particular compiler-machine pair, help approach achievable peak performance through enhanced vectorization/parallelization. We present our techniques and results in terms of an implemented expert system, called EAVE, which has been designed to help users tune their programs for enhanced performance on the IBM 3090 VF.
Fairness and hyperfairness in multi-party interactions
Authors: Paul C. Attie, Nissim Francez, Orna Grumberg
Venue: Proceedings of the 17th ACM SIGPLAN-SIGACT symposium on Principles of programming languages (1989)

In this paper, a new fairness notion is proposed for languages with multi-party interactions as the sole interprocess synchronization and communication primitive. The main advantage of this fairness notion is the elimination of starvation occurring solely due to race conditions (i.e., ordering of independent actions). Also, this is the first fairness notion for such languages which is fully-adequate with respect to the criteria presented in [AFK88]. The paper defines the notion, proves its properties, and presents examples of its usefulness.
Using models in software engineering
Authors: R. D'ilppolito
Venue: Proceedings of the conference on Tri-Ada '89: Ada technology in context: application, development, and deployment (1989)

The Software Engineering Institute (SEI) has participated in several projects1 in which the focus was on helping contractors make use of good software engineering methods and Ada. During this participation, we have learned several important lessons about the development of software for both large-scale and embedded systems. We have noticed that after a long period of time where the focus on productivity generated searches for new methodologies, tools, and ways to write reusable software, the emphasis has shifted to quality, in recognition of the fact that the new methods and tools were not adequate to address the problems occurring at the design level. We propose that the industry instead concentrate the search for the old methods still in use in the other branches of engineering, and apply those methods to the software problem.