ppxscal/embedding_network huggingface dataset:
Sorting in Mesh Connected Multiprocessors
Authors: P. F. Corbett, I. D. Scherson
Venue: IEEE Transactions on Parallel and Distributed Systems (1992)

A sorting algorithm, dubbed MeshSort, for multidimensional mesh-connected multiprocessors is introduced. Bitonic Sort and ShearSort are shown to be special cases of MeshSort. MeshSort thus provides some insight into the operation of parallel sorting. It requires operations only along orthogonal vectors of processors, simplifying the control of the multiprocessor. This allows MeshSort to be used on any reduced architecture where a multidimensional memory structure is interconnected with a lower dimensional structure of processors. A modified version of MeshSort, called FastMeshSort, is presented. This algorithm applies the same basic principle as MeshSort, and is almost as simple to implement, but achieves much better performance. The modified algorithm is shown to be very efficient for reasonably sized meshes. FastMeshSort is presented as a practical sorting and routing algorithm for real multidimensional mesh-connected multiprocessors. The algorithms can easily be extended to other multiprocessor structures.
Processing Element Design for a Parallel Computer
Authors: Katsuyuki Kaneko, Masaitsu Nakajima, Yasuhiro Kakakura, Junji Nishikawa, Ichiro Okabayashi, Hiroshi Kadota
Venue: IEEE Micro (1990)

A study has been made of how cost-effectiveness due to the improvement of VLSI technology can apply to a scientific computer system without performance loss. The result is a parallel computer, ADENA (Alternating Direction Edition Nexus Array), with a core consisting of four kinds of VLSI chips, two for processor elements (PES) and two for the interprocessor network (plus some memory chips). An overview of ADENA and an analysis of its performance are given. The design considerations for the PEs incorporated in ADENA are discussed. The factors that limit performance in a parallel processing environment are analyzed, and the measures employed to improve these factors at the LSI design level are described. The 42.6 sq cm CMOS PEs reach a peak performance of 20 MFLOPS and a 256-PE ADENA 1.5 GFLOPS has been achieved and 300 to 400 MFLOPS for PDE applications.
High Confidence Visual Recognition of Persons by a Test of Statistical Independence
Authors: J. G. Daugman
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1993)

A method for rapid visual recognition of personal identity is described, based on the failure of a statistical test of independence. The most unique phenotypic feature visible in a person's face is the detailed texture of each eye's iris. The visible texture of a person's iris in a real-time video image is encoded into a compact sequence of multi-scale quadrature 2-D Gabor wavelet coefficients, whose most-significant bits comprise a 256-byte "iris code". Statistical decision theory generates identification decisions from Exclusive-OR comparisons of complete iris codes at the rate of 4000 per second, including calculation of decision confidence levels. The distributions observed empirically in such comparisons imply a theoretical "cross-over" error rate of one in 131000 when a decision criterion is adopted that would equalize the false accept and false reject error rates. In the typical recognition case, given the mean observed degree of iris code agreement, the decision confidence levels correspond formally to a conditional false accept probability of one in about 10/sup 31/.
Constructing Quantitative Models Using Monotone Relationships
Authors: Joseph L. Hellerstein
Venue: IEEE Transactions on Knowledge and Data Engineering (1995)

Constructing quantitative models typically requires characterizing a system in terms of algebraic relationships and then using these relationships to compute quantitative values from numerical data. For real-life systems, such as computer operating systems, an algebraic characterization is often difficult, if not intractable. This paper proposes a statistical approach to constructing quantitative models using monotone relationships. Referred to as nonparametric interpolative-estimation for monotone functions (NIMF), our approach uses monotone relationships to search historical data for bounds that provide a desired level of statistical confidence. NIMF makes no assumption about the algebraic form of the monotone relationship, not even continuity.We present two examples of applying NIMF to computer measurements, and compare NIMF¿s confidence intervals with those of least-squares regression, a traditional technique that requires specifying an algebraic relationship. Our results suggest that when an algebraic characterization is not known with precision, using NIMF with an accurate monotone relationship can produce more accurate confidence intervals than employing least-squares regression with a polynomial approximation to the unknown algebraic relationship.
About Hilbert's integral inequality
Authors: Chang-jian Zhao, Mihály Bencze
Venue: Octogon Mathematical Magazine (2002)

In this paper, we first give a simple proof of Hilbert's integral inequality, ten we obtain a very well generalization.
A router for symmetrical FPGAs based on exact routing density evaluation
Authors: Nak Woong Eum, Taewhan Kim, Chong Min Kyung
Venue: Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design (2001)

This paper presents a new performance and routability driven routing algorithm for symmetrical array based field-programmable gate arrays (FPGAs). A key contribution of our work is to overcome one essential limitation of the previous routing algorithms: inaccurate estimations of routing density which were too general for symmetrical FPGAs. To this end, we derive an exact routing density calculation that is based on a precise analysis of the structure (switch block) of symmetrical FPGAs, and utilize it consistently in global and detailed routings. With an introduction of the proposed accurate routing metrics, we design a new routing algorithm called a cost-effective net-decomposition based routing which is fast, and yet produces remarkable routing results in terms of both routability and path/net delays. We performed an extensive experiment to show the effectiveness of our algorithm based on the proposed cost metrics.
The relationship between citric acid production and the morphology of Aspergillus niger during fermentation
Authors: M. Pazouki, T. Panda
Venue: Iranian Journal of Science and Technology (2002)

Morphological studies have been considered very important in fungal fermentation. Morphological parameters and the type of mycelia present (free mycelia without any branches, branched mycelia and branched mycelia with conidiophore) were measured to correlate citric acid production with the morphology of Aspergillus niger. We observed that morphological parameters and the type of mycelia present varied with substrate concentration. They also depended on the type of substrate (molasses and glucose) used. Maximum citric acid (6.8 kg/m3) was produced when branched mycelia with conidiophore were the most available mycelia present in the broth of molasses containing medium. Citric acid was produced in lesser quantity (1.82 kg/m3) when glucose was used. The addition of methanol doubled citric acid production, increased slightly the percentage of branched mycelia with conidiophore and conditioned the surface of the mycelia.
How Multimedia Workloads Will Change Processor Design
Authors: Keith Diefendorff, Pradeep K. Dubey
Venue: Computer (1997)

Workloads drive architecture design and will change in the next two decades. For high-performance, general-purpose processors, there is a consensus that multimedia will continue to grow in importance. The authors predict these processors will incorporate more media processing capabilities, eventually bringing about the demise of specialized media processors, except perhaps, in embedded applications. These enhanced general-purpose processor capabilities will arise from multimedia applications that require real-time response, continuous-media data types, and significant fine-grained data parallelism.
Deterministic Built-in Pattern Generation for Sequential Circuits
Authors: Vikram Iyengar, Krishnendu Chakrabarty, Brian T. Murray
Venue: Journal of Electronic Testing: Theory and Applications (1999)

We present a new pattern generation approach for deterministic built-in self testing (BIST) of sequential circuits. Our approach is based on precomputed test sequences, and is especially suited to sequential circuits that contain a large number of flip-flops but relatively few controllable primary inputs. Such circuits, often encountered as embedded cores and as filters for digital signal processing, are difficult to test and require long test sequences. We show that statistical encoding of precomputed test sequences can be combined with low-cost pattern decoding to provide deterministic BIST with practical levels of overhead. Optimal Huffman codes and near-optimal Comma codes are especially useful for test set encoding. This approach exploits recent advances in automatic test pattern generation for sequential circuits and, unlike other BIST schemes, does not require access to a gate-level model of the circuit under test. It can be easily automated and integrated with design automation tools. Experimental results for the ISCAS 89 benchmark circuits show that the proposed method provides higher fault coverage than pseudorandom testing with shorter test application time and low to moderate hardware overhead.
Algorithms and Bounds for Shortest Paths and Diameter in Faulty Hypercubes
Authors: S. B. Tien, C. S. Raghavendra
Venue: IEEE Transactions on Parallel and Distributed Systems (1993)

In an n-dimensional hypercube Qn, with the fault set mod F mod >2/sub n-2/, assuming Sand D are not isolated, it is shown that there exists a path of length equal to at mosttheir Hamming distance plus 4. An algorithm with complexity O( mod F mod logn) is given to find such a path. A bound for the diameter of the faulty hypercube Qn-F, when mod F mod >2/sub n-2/, as n+2 is obtained. This improves the previously known bound of n+6 obtained by A.-H. Esfahanian (1989). Worst case scenarios are constructed to show that these bounds for shortest paths and diameter are tight. It is also shown that when mod F mod >2n-2, the diameter bound is reduced to n+1 if every node has at least 2 nonfaulty neighbors and reduced to n if every node has at least 3 nonfaulty neighbors.
A Class of Low Complexity High Concurrence Algorithms
Authors: J. L. Aravena, A. O. Barbir
Venue: IEEE Transactions on Parallel and Distributed Systems (1991)

A nonconventional approach to the analysis of dedicated computing structures in which the number of compute cycles is used as a design parameter to determine families of transformations implementable in the structure is presented. Using this approach, a single architecture can be used to implement a family of transformations with varying degrees of complexity. The transformations generated by a matrix multiplication array are considered in detail. It is shown that, for some real-time applications it becomes possible to incorporate the compute time as a constraint for designs based in optimality criteria. In particular, a least square approximation problem is discussed.
An efficient algorithm for the run-time parallelization of DOACROSS loops
Authors: Ding Kai Chen, Josep Torrellas, Pen Chung Yew
Venue: Proceedings of the 1994 ACM/IEEE conference on Supercomputing (1994)

While automatic parallelization of loops usually relies on compile-time analysis of data dependences, for some loops the data dependences cannot be determined at compile time. An example is loops accessing arrays with subscripted subscripts. To parallelize these loops, it is necessary to perform run-time analysis. In this paper, we present a new algorithm to parallelize these loops at run time. Our scheme handles any type of data dependence in the loop without requiring any special architectural support in the multiprocessor. Furthermore, compared to an older scheme with the same generality, our scheme significantly reduces the amount of processor communication required and increases the overlap among dependent iterations. We evaluate our algorithm with parameterized loops running on the 32-processor Cedar shared-memory multiprocessor. The results show speedups over the serial code of up to 14 with the full overhead of run-time analysis and of up to 27 if part of the analysis is reused across loop invocations. Moreover, the algorithm outperforms the older scheme in nearly all cases, reaching speedups of up to times when the loop has many dependences.
Software Beyond 2001: A Global Vision
Authors: William W. Everett, Mikio Aoyama, Jawed Siddiqi
Venue: IEEE Software (1994)

The worldwide software industry is poised for change well into the next century. How well each developer; researcher, or country fares may depend on how clear its visions of the future are. In this collection of essays, some original thinkers peer into the next century.
Connectionist Password Quality Tester
Authors: Nigel Duffy, Arun Jagota
Venue: IEEE Transactions on Knowledge and Data Engineering (2002)

We present a simple connectionist algorithm for testing the quality of computer passwords. Password quality is evaluated by testing the string against a large dictionary of words stored in a network in distributed form. Numerical simulations demonstrate the effectiveness of this approach. Computer security has always been an issue, more so in recent years due to the global network access. In this correspondence, we present a simple connectionist algorithm for testing the quality of computer passwords. A popular method of evaluating password quality is to test it against a large dictionary of words and near-words. Our algorithm is an approximate realization of this method. The large dictionary of words is stored in the network in distributed form. All stored words are stable; however, spurious memories may develop. Although there is no easy way to determine exactly which nonword strings become spurious, nor even exactly how many spurious memories form, the numerical simulations below reveal that the network works well in distinguishing words and near-words from structure-less strings. Thus, to evaluate a password, one would present it to the network and, if the network labeled it a memory, the password would be considered bad, otherwise good.
Path selection and pattern generation for dynamic timing analysis considering power supply noise effects
Authors: Jing Jia Liou, Angela Krstić, Yi Min Jiang, Kwang Ting Cheng
Venue: Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design (2000)

Noise effects such as power supply and crosstalk can significantly affect the performance of deep submicron designs. These delay effects are highly input pattern dependent. Existing path selection and timing analysis techniques cannot capture the effects of noise on cell/interconnect delays. Therefore, the selected critical paths may not be the longest paths and predicted circuit performance might not reflect the worst-case circuit delay. In this paper, we propose a path selection technique that can consider power supply noise effects on the propagation delays. Next, for the selected critical paths, we propose a pattern generation technique for dynamic timing analysis such that the patterns produce the worst-case power supply noise effects on the delays of these paths. Our experimental results demonstrate the difference in estimated circuit performance for the case when power supply noise effects are considered vs. when these effects are ignored. Thus, they validate the need for considering power supply noise effects on delays during path selection and dynamic timing analysis.
Analyzing and Diagnosing Interconnect Faults in Bus-Structured Systems
Authors: Jun Zhao, Fred J. Meyer, Fabrizio Lombardi
Venue: IEEE Design Test (2002)

Testing multimodule systems presents several challenges, particularly when systems use submicron technology. The authors propose strategies to diagnose interconnect faults in bus-structured systems using several models.
A Knowledge-Based Planning System for Mechanical Assembly Using Robots
Authors: William G. Wee, Kai-Hsiung Chang
Venue: IEEE Expert: Intelligent Systems and Their Applications (1988)

The generation of task-level plans is considered for assembly using robots. A system that uses artificial-intelligence techniques is presented. The system's knowledge types are described, with examples, and its control structure is examined.
Two Auction-Based Protocols for Fair and Fast Resource Assignment in Wireless PCS
Authors: Shu-Yuen Hwang, Tsan-Pin Wang
Venue: Wireless Personal Communications: An International Journal (1999)

The Resource Auction Multiple Access (RAMA) protocol was recently proposed for fast resource assignment in wireless PCS networks. The protocol assigns communication resources to subscribers using a collision resolution method based on subscriber ID&lsquo;s. In each auction cycle, the subscriber with the highest ID will obtain the resource. Thus the RAMA protocol encounters the unfairness problem since subscribers with lower ID&lsquo;s might be delayed forever. In this paper, we propose two modifications to the RAMA protocol to solve the unfairness problem. The first modification forces the RAMA protocol to process requests in bursts, i.e., new requests are not processed until the current burst of requests are all satisfied. The second modification asks the base station to select subscribers randomly instead of the one with the highest ID. We derive mathematical models to compare the performances of proposed and original protocols. Performance results indicate that the modification of random selection is fairer than other protocols in terms of the waiting time distribution.
Accurate Solution to Overdetermined Linear Equations with Errors Using L1 Norm Minimization
Authors: J. Ben Rosen, Haesun Park, John Glick, Lei Zhang
Venue: Computational Optimization and Applications (2000)

It has been known for many years that a robust solution to an overdetermined system of linear equations Ax &ap; b is obtained by minimizing the L1 norm of the residual error. A correct solution x to the linear system can often be obtained in this way, in spite of large errors (outliers) in some elements of the (m &times; n) matrix A and the data vector b. This is in contrast to a least squares solution, where even one large error will typically cause a large error in x. In this paper we give necessary and sufficient conditions that the correct solution is obtained when there are some errors in A and b. Based on the sufficient condition, it is shown that if k rows of [A b] contain large errors, the correct solution is guaranteed if (m &minus; n)/n &ge; 2k/&sigma;, where &sigma; > 0, is a lower bound of singular values related to A. Since m typically represents the number of measurements, this inequality shows how many data points are needed to guarantee a correct solution in the presence of large errors in some of the data. This inequality is, in fact, an upper bound, and computational results are presented, which show that the correct solution will be obtained, with high probability, for much smaller values of m &minus; n.
Using Logical Rings to Solve the Distributed Mutual Exclusion Problem with Fault Tolerance Issues
Authors: Kia Makki, John Dell, Niki Pissinou, W. Melody Moh, Xiaohua Jia
Venue: The Journal of Supercomputing (2000)

In this paper, we investigate distributed mutual exclusion algorithms and delineate the features of a new distributed mutual exclusion algorithm. The basis of the algorithm is the logical ring structure employed in token-based mutual exclusion algorithms. Specifically, there exists dynamic properties of the logical ring that, given certain restrictions regarding message traffic flow, passively give useful information about the location of the token. Effectively, the algorithm demonstrates a type of &ldquo;intelligent routing&rdquo; that identifies useful shortcuts in the routing of the token. The result is a reduction in the total number of messages exchanged prior to the execution of the critical section as compared to the algorithm proposed by Fu and Tzeng &lsqb;3&rsqb;. Furthermore, the algorithm allows for an increased degree of fairness in a lightly loaded system than that allowed by Fu and Tzeng's algorithm. The paper also addresses failure recovery issues.
Implementation-Independent Model of an Instruction Set Architecture in VHDL
Authors: Maximo H. Salinas, Barry W. Johnson, James H. Aylor
Venue: IEEE Design Test (1993)

A methodology using a VHDL (VHSIC hardware description language) to create executable models of computer architectures independent of implementation attributes is described. The authors present such a model of a processor architecture known as the WM as the first step in developing an implementation. Simulations using the model can provide performance measurements such as potential parallelism. The model can also serve as an architectural specification for the computer.
A Hybrid Representation of Vague Collections for Distributed Object Management Systems
Authors: Oliver Haase, Andreas Henrich
Venue: IEEE Transactions on Knowledge and Data Engineering (2000)

An important characteristic of distributed object management systems is that due to network or machine failure, the environment may become partitioned into subenvironments that cannot communicate with each other. In some application scenarios, it is important that the subenvironments remain operable even in this case. In particular, queries should be processed in an appropriate way. To this end, the final and all intermediate results of a query in a distributed object management system must be regarded as potentially vague. In this paper, we propose a hybrid representation for vague sets and vague multisets designed for this application context. The representation consists of an enumerating part, which contains the elements we could access during query processing, and a descriptive part, which describes the relevant elements we could not access. We introduce Propagation Rules which can be used to minimize the vagueness of a query result represented in this hybrid way. The main advantage of our approach is that the descriptive part of the representation can be used to improve the enumerating part during query processing.
Clustering and Classification in Structured Data Domains Using Fuzzy Lattice Neurocomputing (FLN)
Authors: Vassilios Petridis, Vassilis G. Kaburlasos
Venue: IEEE Transactions on Knowledge and Data Engineering (2001)

A connectionist scheme, namely, ¿-Fuzzy Lattice Neurocomputing scheme or ¿-FLN for short, which has been introduced in the literature lately for clustering in a lattice data domain, is employed in this work for computing clusters of directed graphs in a master-graph. New tools are presented and used here, including a convenient inclusion measure function for clustering graphs. A directed graph is treated by ¿-FLN as a single datum in the mathematical lattice of subgraphs stemming from a master-graph. A series of experiments is detailed where the master-graph emanates from a Thesaurus of spoken language synonyms. The words of the Thesaurus are fed to ¿-FLN in order to compute clusters of semantically related words, namely, hyperwords. The arithmetic parameters of ¿-FLN can be adjusted so as to calibrate the total number of hyperwords computed in a specific application. It is demonstrated how the employment of hyperwords implies a reduction, based on the a priori knowledge of semantics contained in the Thesaurus, in the number of features to be used for document classification. In a series of comparative experiments for document classification, it appears that the proposed method favorably improves classification accuracy in problems involving longer documents, whereas performance deteriorates in problems involving short documents.