ppxscal/embedding_network huggingface dataset:
Prediction-Based Dynamic Load-Sharing Heuristics
Authors: K. K. Goswami, M. Devarakonda, R. K. Iyer
Venue: IEEE Transactions on Parallel and Distributed Systems (1993)

Presents dynamic load-sharing heuristics that use predicted resource requirements ofprocesses to manage workloads in a distributed system. A previously developed statisticalpattern-recognition method is employed for resource prediction. Whilenonprediction-based heuristics depend on a rapidly changing system status, the newheuristics depend on slowly changing program resource usage patterns. Furthermore,prediction-based heuristics can be more effective since they use future requirementsrather than just the current system state. Four prediction-based heuristics, twocentralized and two distributed, are presented. Using trace driven simulations, they arecompared against random scheduling and two effective nonprediction based heuristics.Results show that the prediction-based centralized heuristics achieve up to 30% betterresponse times than the nonprediction centralized heuristic, and that theprediction-based distributed heuristics achieve up to 50% improvements relative to theirnonpredictive counterpart.
A Multiscale Method for the Reassembly of Two-Dimensional Fragmented Objects
Authors: Helena Cristina da Gama Leitão, Jorge Stolfi
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (2002)

We describe here an efficient procedure for reassembling unknown two-dimensional objects that have been broken or torn into a large number of irregular fragments¿a problem that often arises in archaeology, art restoration, forensics, and other disciplines. The procedure compares the curvature-encoded fragment outlines, at progressively increasing scales of resolution, using an incremental dynamic programming sequence-matching algorithm. The total cost gets reduced by a factor proportional to the mean number of samples per segment, which makes the method viable for problems of practical size (thousands of fragments). The performance of our method is illustrated with an artificial but realistic example.
Maximal and Near-Maximal Shift Register Sequences: Efficient Event Counters and Easy Discrete Logarithms
Authors: D. W. Clark, Lih-Jyh Weng
Venue: IEEE Transactions on Computers (1994)

A linear feedback shift register, or LFSR, can implement an event counter by shifting whenever an event occurs. A single two-input exclusive-OR gate is often the only additional hardware necessary to allow a shift register to generate, by successive shifts, all of its possible nonzero values. The counting application requires that the number of shifts be recoverable from the LFSR contents so that further processing and analysis may be done. Recovering this number from the shift register value corresponds to a problem from number theory and cryptography known as the discrete logarithm. For some sizes of shift register, the maximal-length LFSR implementation requires more than a single gate, and for some, the discrete logarithm calculation is hard. The paper proposes for such size the use of certain one-gate LFSR's whose sequence lengths are nearly maximal, and which support easy discrete logarithms. These LFSR's have a concise mathematical characterization, and are quite common. The paper concludes by describing an application of these ideas in a computer hardware monitor, and by presenting a table that describes efficient LFSR's of size up to 64 bits.
Efficient Construction of Aliasing-Free Compaction Circuitry
Authors: Ozgur Sinanoglu, Alex Orailoglu
Venue: IEEE Micro (2002)

Parallel testing of cores can reduce soc test times, but the finite number of chip I/Os limits such parallelism. Space and time compaction can maximize parallelism by minimizing the required test bandwidth at the core outputs.
A Nonbinary Neural Network Design
Authors: W. A. Porter, Xiaoyan Zheng
Venue: IEEE Transactions on Computers (1993)

In earlier studies a distributed neural network, referred to as a neuromic array, was introduced. The earlier designs were restricted to binary alphabets. The present study loosens this restriction by demonstrating the design extension to the quartic case. A natural morphism between the quartic valued and binary valued vector spaces is used to establish a design equivalence between the two settings. This correspondence compares the robustness and performance of equivalent binary and quartic designs.
Cached DRAM for ILP Processor Memory Access Latency Reduction
Authors: Zhao Zhang, Zhichun Zhu, Xiaodong Zhang
Venue: IEEE Micro (2001)

Cached DRAM adds a small cache onto a DRAM chip to reduce average DRAM access latency. The authors compare cached DRAM with other advanced dram techniques for reducing memory access latency in instruction-level-parallelism processors.
A Minimalist Approach to VHDL Logic Modeling
Authors: Paul J. Menchini
Venue: IEEE Design Test (1990)

The VHDL Design Exchange Group (VDEG), which consists of VHDL (VHSIC hardware description language) suppliers and users, was formed to promote the identical operation of VHDL models on different tools. One task of VDEG, which is still ongoing, is to develop a consensus logic model and a method for its use. VDEG and the VDEG's work on this task as of September 1989 are described. The definition of portability used by VDEG and the minimalist approach toward a standard multivalue logic type for modeling favored by the group are examined. The use of the model is discussed. VDEG is developing a library of packages to aid in the construction of portable models; the package containing definitions of types of operations is described in some detail. Two mappings are presented to illustrate the assertion that the portable logic model is easy to map to the logic models in existing tools. Future work is outlined.
Why Do So Many Reuse Programs Fail?
Venue: IEEE Software (1994)

Research, forecasts and government studies consistently show that reuse technology has the greatest potential to reduce the cost of software. Some reuse programs have succeeded, achieving anywhere from 30 to 80 percent reuse. Yet other programs have failed to show any clear return. How can such an obvious winner fail? Our experience as promoters and supporters of reuse and as measurers of its effectiveness suggests that two fundamental mistakes contribute to failure. The first mistake is that organizations treat reuse as a technology-acquisition problem instead of a technology-transition problem. Plenty of reuse technology is now mature enough for industrial use (although some problems remain). However, just buying technology usually does not lead to extensive reuse. The second mistake is that organizations fail to approach reuse as a business strategy. Even organizations that recognize reuse as a technology-transition issue may fail to address the business implications of reuse. We consider how the most important obstacles to reuse are economic and cultural not technological.
A Comparative Study of Various Nested Normal Forms
Authors: W. Y. Mok
Venue: IEEE Transactions on Knowledge and Data Engineering (2002)

As object-relational databases (ORDBs) become popular in the industry, it is important for database designers to produce database schemes with good properties in these new kinds of databases. One distinguishing feature of an ORDB is that its tables may not be in first normal form. Hence, ORDBs may contain nested relations along with other collection types. To help the design process of an ORDB, several normal forms for nested relations have recently been defined, and some of them are called nested normal forms. In this paper, we investigate four nested normal forms, which are NNF 20, NNF 21, NNF 23, and NNF 25, with respect to generalizing 4NF and BCNF, reducing redundant data values, and design flexibility. Another major contribution of this paper is that we provide an improved algorithm that generates nested relation schemes in NNF 2 from an $ database scheme, which is the most general type of acyclic database schemes. After presenting the algorithm for NNF 20, the algorithms of all of the four nested normal forms and the nested database schemes that they generate are compared. We discovered that when the given set of MVDs is not conflict-free, NNF 20 is inferior to the other three nested normal forms in reducing redundant data values. However, in all of the other cases considered in this paper, NNF 20 is at least as good as all of the other three nested normal forms.
Direct Gray-Scale Extraction of Features for Character Recognition
Authors: L. Wang, T. Pavlidis
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1993)

A method for feature extraction directly from gray-scale images of scanned documents without the usual step of binarization is presented. This approach eliminates binarization by extracting features directly from gray-scale images. In this method, a digitized gray-scale image is treated as a noisy sampling of the underlying continuous surface and desired features are obtained by extracting and assembling topographic characteristics of this surface. The advantages and effectiveness of the approach are both shown theoretically and demonstrated through preliminary experiments of the proposed method.
Defect-Oriented Sampling of Non-Equally Probable Faults in VLSI Systems
Authors: F. M. Gonçalves, J. P. Teixeira
Venue: Journal of Electronic Testing: Theory and Applications (1999)

The purpose of this paper is to present a novel methodology for Defect-Oriented (DO) fault sampling, and its implementation in a new extraction tool, lobs (\underline Layout \underline Observer). The methodology is based on the statistics theory, and on the application of the concepts of estimation of totals over subpopulations and stratified sampling to the fault sampling problem. The proposed stratified sampling methodology applies to non-equally probable DO faults, exhibiting a wide range of probabilities of occurrence, and leads to confidence intervals similar to the ones obtained with equally probable faults. ISCAS benchmark circuits are laid out and lobs used to ascertain the results, for circuits up to 100,000 MOS transistors, and extracted DO fault lists of 300,000 faults.
Composite k-Arbiters
Authors: Yu-Chen Kuo
Venue: IEEE Transactions on Parallel and Distributed Systems (2001)

The k-Arbiter is a useful concept to solve the distributed h-out-of-k mutual exclusion problem. The distributed h-out-of-k mutual exclusion algorithms, based on the k-arbiter, have the benefits of high fault tolerance and low message cost. However, according to the definition of the k-arbiter, it is required to have a nonempty intersection among any (k+1) quorums in a k-arbiter. Consequently, constructing k-arbiters is difficult. The coterie join operation proposed by Neilsen and Mizuno produces a new and larger coterie by joining known coteries. In this paper, by extending the coterie join operation, we first propose a k-arbiter join operation to construct a new and larger k-arbiter from known k-arbiters for a large system. Then, we derive a necessary and sufficient condition for the k-arbiter join operation to construct a nondominated joined k-arbiter. Moreover, we discuss availability properties of the joined k-arbiters. We observe that, by selecting proper k-arbiters, the joined k-arbiter can provide a higher availability than that of the original input. Finally, we propose a k-arbiter compound operation to construct k-arbiters by using coteries and/or k-coteries. By that way, the problem of constructing k-arbiters can be reduced to the problem of constructing coteries and/or k-coteries.
Trace Processors: Moving to Fourth-Generation Microarchitectures
Authors: James E. Smith, Sriram Vajapeyam
Venue: Computer (1997)

T his article proposes a new architecture called "trace processors," which consist of multiple, distributed on-chip processor cores, each of which simultaneously executes a different trace. All but one core executes the traces speculatively, having used branch prediction to select traces that follow the one executing. (Although this architectural concept is similar to multiscalar processors, described in a sidebar, it does not require explicit compiler support). The authors argue that future processors will rely heavily on replication and hierarchy, and they show how their architecture exploits these concepts.
Determination of an Optimal Retry Time in Multiple-Module Computing Systems
Authors: Chao-Ju Hou, Kang G. Shin
Venue: IEEE Transactions on Computers (1996)

The 'optimal' (in some sense) amount of time used for (or the optimal number of times) retrying an instruction upon detection of an error in a computing system is usually determined under the assumption that the system is composed of a single module, within which all fault activities are confined until some module-replacement action is taken. However, a computing system is usually composed of at least three modules, namely, CPU, memory, and I/O, and the execution of an instruction often requires the cooperation of two or more modules. It is thus more realistic to consider the fault activities in multiple-module systems.In this paper, we first relax the single-module assumption and model the fault activities in a multiple-module system as a Markov process. We apply the randomization method to decompose the continuous-time Markov chain into a discrete-time Markov chain subordinated to a Poisson process. Using this decomposition, we can derive several interesting measures, such as 1) the conditional probability of successful retry given a retry period and the fact that a non-permanent fault has occurred, 2) the mean time-to-system recovery, and 3) the distribution of the time until which all modules in the system enter a fault-free state. All the measures derived are used to determine, along with the parameters characterizing fault activities and costs of recovery techniques, a) whether or not retry should be used as a first-step recovery means upon detection of an error, and b) the best retry period or number of retries that satisfies a given criterion, e.g., a specific probability of successful retry.
Pricing in Agent Economies Using Multi-Agent Q-Learning
Authors: Gerald Tesauro, Jeffrey O. Kephart
Venue: Autonomous Agents and Multi-Agent Systems (2002)

This paper investigates how adaptive software agents may utilize reinforcement learning algorithms such as Q-learning to make economic decisions such as setting prices in a competitive marketplace. For a single adaptive agent facing fixed-strategy opponents, ordinary Q-learning is guaranteed to find the optimal policy. However, for a population of agents each trying to adapt in the presence of other adaptive agents, the problem becomes non-stationary and history dependent, and it is not known whether any global convergence will be obtained, and if so, whether such solutions will be optimal. In this paper, we study simultaneous Q-learning by two competing seller agents in three moderately realistic economic models. This is the simplest case in which interesting multi-agent phenomena can occur, and the state space is small enough so that lookup tables can be used to represent the Q-functions. We find that, despite the lack of theoretical guarantees, simultaneous convergence to self-consistent optimal solutions is obtained in each model, at least for small values of the discount parameter. In some cases, exact or approximate convergence is also found even at large discount parameters. We show how the Q-derived policies increase profitability and damp out or eliminate cyclic price &ldquo;wars&rdquo; compared to simpler policies based on zero lookahead or short-term lookahead. In one of the models (the &ldquo;Shopbot&rdquo; model) where the sellers' profit functions are symmetric, we find that Q-learning can produce either symmetric or broken-symmetry policies, depending on the discount parameter and on initial conditions.
Data-Parallel Programming on MIMD Computers
Authors: P. J. Hatcher, M. J. Quinn, A. J. Lapadula, B. K. Seevers, R. J. Anderson, R. R. Jones
Venue: IEEE Transactions on Parallel and Distributed Systems (1991)

The implementation of two compilers for the data-parallel programming language Dataparallel C is described. One compiler generates code for Intel and nCUBE hypercube multicomputers; the other generates code for Sequent multiprocessors. A suite of Dataparallel C programs has been compiled and executed, and their execution times and speedups on the Intel iPSC/2, the nCUBE 3200 and the Sequent Symmetry are presented.
CPR: curved planar reformation
Authors: Armin Kanitsar, Dominik Fleischmann, Rainer Wegenkittl, Petr Felkel, Meister Eduard Gröller
Venue: Proceedings of the conference on Visualization '02 (2002)

Visualization of tubular structures such as blood vessels is an important topic in medical imaging. One way to display tubular structures for diagnostic purposes is to generate longitudinal cross-sections in order to show their lumen, wall, and surrounding tissue in a curved plane. This process is called Curved Planar Reformation (CPR). We present three different methods to generate CPR images. A tube-phantom was scanned with Computed Tomography (CT) to illustrate the properties of the different CPR methods. Furthermore we introduce enhancements to these methods: thick-CPR, rotating-CPR and multi-path-CPR.
A force-directed macro-cell placer
Authors: Fan Mo, Abdallah Tabbara, Robert K. Brayton
Venue: Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design (2000)

In this paper we present a novel force-directed placement algorithm, which is used to solve macro-cell placement problems. A new wire model replaces the traditional clique model and makes possible early awareness of routing congestion. Issues such as cell orientation, overlap elimination, and pad positioning are also considered. Experiments show satisfactory performance and fast run time.
Smart Antennas with Two-Dimensional Array Configurations for Performance Enhancement of a Joint Detection CDMA Mobile Radio System
Authors: Apostolos Papathanassiou, Ignasi Furió, Josef Johannes Blanz, Paul Walter Baier
Venue: Wireless Personal Communications: An International Journal (1999)

Smart antennas for base stations of cellular mobile radio systems offer the potential of system performance enhancement by taking advantage of the directionally inhomogeneous signal reception at the receiver. In this paper, two-dimensional array configurations employed at the uplink receiver of a joint detection CDMA (JD-CDMA) mobile radio system are investigated. This smart antenna concept can be split up into a novel channel estimator and data detector which incorporate explicitely the information of the direction-of-arrival (DOA) of signals emerging from users assigned to the considered base station. Proceeding from channel models that model the directional inhomogeneity of the mobile radio channel with single DOAs, the link level performance of a JD-CDMA mobile radio system using this smart antenna concept is evaluated for the rural propagation environment. The performance evaluation is based on Monte Carlo simulations of data transmission and average bit error rates versus the average signal to noise ratio per net information bit are presented for different array configurations. Although these results should be considered as upper bounds for the link level performance, they reveal the advantages of implementing two-dimensional array configurations at the uplink receiver of a JD-CDMA mobile radio system.
The random facet simplex algorithm on combinatorial cubes
Authors: Bernd Gärtner
Venue: Random Structures Algorithms (2002)

The RANDOM-FACET algorithm is a randomized variant of the simplex method which is known to solve any linear program with n variables and m constraints using an expected number of pivot steps which is subexponential in both n and m. This is the theoretically fastest simplex algorithm known to date if m ≈ n; it provably beats most of the classical deterministic variants which require exp(Ω(n)) pivot steps in the worst case. RANDOM-FACET has independently been discovered and analyzed ten years ago by Kalai as a variant of the primal simplex method, and by Matousek, Sharir, and Welzl in a dual form. The essential ideas and results connected to RANDOM-FACET Can be presented in a particularly simple and instructive way for the case of linear programs over combinatorial n-cubes. I derive an explicit upper bound of Σℓ=1n 1/ℓ1(??) ≤ exp(2 √n) - 1 on the expected number of pivot steps in this case, using a new technique of "fingerprinting" pivot steps. This bound also holds for generalized linear programs, similar flavors of which have been introduced and studied by several researchers. I then review an interesting class of generalized linear programs, due to Matousek, showing that RANDOM-FACET may indeed require an expected number of exp(Ω(√n)) pivot steps in the worst case. The main new result of the paper is a proof that all actual linear programs in Matousek's class are solved by RANDOM-FACET with an expected polynomial number of O(n2) pivot steps. This proof exploits a combinatorial property of linear programming which has only recently been discovered by Holt and Klee. The result establishes the first scenario in which an algorithm that works for generalized linear programs "recognizes" proper linear programs. Thus, despite Matousek's worst-case result, the question remains open whether RANDOM-FACET (or any other simplex variant) is a polynomial-time algorithm for linear programming. Finally, I briefly discuss extensions of the combinatorial cube results to the general case.
A Distance Measure Tailored to Tailbiting Codes
Authors: M. Handlery, S. Höst, R. Johannesson, V. V. Zyablov
Venue: Problems of Information Transmission (2002)

The error-correcting capability of tailbiting codes generated by convolutional encoders is described. In order to obtain a description beyond what the minimum distance dmin of the tailbiting code implies, the active tailbiting segment distance is introduced. The description of correctable error patterns via active distances leads to an upper bound on the decoding block error probability of tailbiting codes. The necessary length of a tailbiting code so that its minimum distance is equal to the free distance dfree of the convolutional code encoded by the same encoder is easily obtained from the active tailbiting segment distance. This is useful when designing and analyzing concatenated convolutional codes with component codes that are terminated using the tailbiting method. Lower bounds on the active tailbiting segment distance and an upper bound on the ratio between the tailbiting length and memory of the convolutional generator matrix such that dmin equals dfree are derived. Furthermore, affine lower bounds on the active tailbiting segment distance suggest that good tailbiting codes are generated by convolutional encoders with large active-distance slopes.
Case study: visual debugging of cluster hardware
Authors: Patricia Crossno, Rena Haynes
Venue: Proceedings of the conference on Visualization '01 (2001)

This paper presents a novel use of visualization applied to debugging the Cplant&trade; cluster hardware at Sandia National Laboratories. As commodity cluster systems grow in popularity and grow in size, tracking component failures within the hardware will become more and more difficult. We have developed a tool that facilitates visual debugging of errors within the switches and cables connecting the processors. Combining an abstract system model with color-coding for both error and job information enables failing components to be identified.