ppxscal/embedding_network huggingface dataset:
Improving Gil-Werman Algorithm for Running Min and Max Filters
Authors: David Z. Gevorkian, Jaakko T. Astola, Samvel M. Atourian
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1997)

The current best bound on the number of comparison operations needed to compute the running maximum or minimum over a p-element sliding data window is approximately three comparisons per output sample [1], [2], [3], [4]. This bound is probabilistic for the algorithms in [2], [3], [4] and is derived for their complexities on the average for independent, identically distributed (i.i.d.) input signals (uniformly i.i.d., in the case of the algorithm in [2]). The worst-case complexities of these algorithms are O(p). The worst-case complexity C1 = 3 ¿ 4¿/¿p comparisons per output sample for 1D signals is achieved in the Gil-Werman algorithm [1]. In this correspondence we propose a modification of the Gil-Werman algorithm with the same worst-case complexity but with a lower average complexity. A theoretical analysis shows that using the proposed modification the complexities of sliding Max or Min 1D and 2D filters over i.i.d. signals are reduced to C1 = 2.5 ¿ 3.5¿/¿p + 1¿/¿p2 and C2 = 5 ¿ 7¿/¿p + 2¿/¿p2 comparisons per output sample on the average, respectively. Simulations confirm the theoretical results. Moreover, experiments show that even for highly correlated data, namely, for real images the behavior of the algorithm remains the same as for i.i.d. signals.
ANNOD: a navigator of natural-language organized (textual) data
Authors: Robert E. Williamson
Venue: Proceedings of the 8th annual international ACM SIGIR conference on Research and development in information retrieval (1985)

ANNOD is the name of a system developed at the National Library of Medicine (NLM), which implements a set of linguistic and empirical techniques that permit retrieval of natural language information in response to natural language queries. The system is based on Dr. Gerard Salton's SMART [1] document retrieval system and is presently implemented on a mini-computer as part of an Interactive TExt Management System, ITEMS.[2] Actual experience with retrieval of information from NLM's Hepatitis Knowledge Base (HKB), an encyclopedic hierarchical, full-text file, is presented. The techniques used in ANNOD include: automatic stemming of words, common word deletion, thesaurus expansion, a complex empirical matching (ranking) algorithm (similarity measure), and techniques expressly designed to permit rapid response in a mini-computer environment. Preliminary testing demonstrates high efficiency in identifying portions of a text which are relevant to users.
Writing an OLE automation controller in Ada95
Authors: Chad Bremmon
Venue: ACM SIGAda Ada Letters (1997)

Microsoft OLE provides a powerful toolset to the Microsoft WindowsNT/95 developer. We have experienced the development of an OLE Automation Controller in Ada95 and would like to discuss the experience. This paper details the steps necessary to develop an OLE Automation Controller in Ada95.
A simulation model of the FAA'S flight service automation system
Authors: C. R. Spooner, A. Acampora, R. Regner
Venue: Proceedings of the 17th conference on Winter simulation (1985)

The Flight Service Stations of the Federal Aviation Administration are in process of being automated. To study performance, a simulation model has been built. To date, the model has been tentatively calibrated against the first version of the real system, and used to predict performance in a number of situations. The paper outlines the system being modeled, describes the model itself, and discusses some of the issues encountered during modeling. It then describes the calibration of the model, and the experience gained so far in its use. Future plans are outlined.
On the Binary Self-Dual Codes with an Automorphism of Order2
Authors: Stefka Buyuklieva
Venue: Designs, Codes and Cryptography (1997)

Methods to design binary self-dual codes with an automorphism of order two without fixed points are presented. New extremal self-dual [40,20,8], [42,21,8],[44,22,8] and [64,32,12] codes with previously not known weight enumerators are constructed.
Functional Networks
Authors: Enrique Castillo
Venue: Neural Processing Letters (1998)

In this letter we present functional networks. Unlike neural networks, in these networks there are no weightsassociated with the links connecting neurons, and the internal neuron functions are not fixed but learnable. These functions are not arbitrary, but subject to strong constraints to satisfy the compatibility conditions imposed by the existence of multiple links going from the last input layer to the same output units. In fact, writing the values of the output units in different forms, by considering these different links, a system of functional equations is obtained. When this system is solved, the numberof degrees of freedom of these initially multidimensional functions is considerably reduced. One example illustrates the process and shows that multidimensional functions can be reduced to functions with a single argument. To learn the resulting functions, a method based on minimizing a least squares error function is used, which, unlike the functions used in neural networks, has a single minimum.
Knowledge-Based Learning in Exploratory Science: Learning Rules to Predict Rodent Carcinogenicity
Authors: Yongwon Lee, Bruce G. Buchanan, John M. Aronis
Venue: Machine Learning (1998)

In this paper, we report on a multi-year collaboration among computer scientists, toxicologists, chemists, and a statistician, in which the RL induction program was used to assist toxicologists in analyzing relationships among various features of chemical compounds and their carcinogenicity in rodents. Our investigation demonstrated the utility of knowledge-based rule induction in the problem of predicting rodent carcinogenicity and the place of rule induction in the overall process of discovery. Flexibility of the program in accepting different definitions of background knowledge and preferences was considered essential in this exploratory effort. This investigation has made significant contributions not only to predicting carcinogenicity and non-carcinogenicity in rodents, but to understanding how to extend a rule induction program into an exploratory data analysis tool.
Balanced Incomplete Block Designs with Block Size 7
Authors: R. Julian R. Abel, Malcolm Greig
Venue: Designs, Codes and Cryptography (1998)

The object of this paper is the construction of balanced incomplete block designs with k=7. This paper continues the work begun by Hanani, who solved the construction problem for designs with a block size of 7, and with &lambda;=6, 7, 21 and 42. The construction problem is solved here for designs with &lambda; > 2 except for v=253, &lambda;= 4,5 ; also for &lambda;= 2, the number of unconstructed designs is reduced to 9 (1 nonexistent, 8 unknown).
A Unified Approach to Submicron DC MOS Transistor Modelingfor Low-Voltage ICs
Authors: Steve H. Jen, Bing J. Sheu, Yoichi Oshima
Venue: Analog Integrated Circuits and Signal Processing (1997)

A unified single-equation approach for the MOS transistor drain current modeling for energy-efficient submicron MOS circuits is presented. Instead of three sets of separate equations for the triode, saturation, and weak inversion regions, only a continuous expression which is valid to describe the behavior of drain current and the derivatives in all operation regions can be realized by using a combination of hyperbola, sigmoid, and interpolation methods. The model expression can predict accurate results for the current, output conductance, and transconductance with continuous and smooth characteristics. The simulation results agree well with experimental data.
Enterprise enhanced education: an information technology enabled extension of traditional learning environments
Authors: Michael C. Mulder, Doris Lidtke, Gordon E. Stokes
Venue: ACM SIGCSE Bulletin (1997)

For many years there have been complaints from enterprises such as business, industry and government that academia is unable to produce graduates that can function well in the design and implementation of large and complex information and engineering systems. These complaints have been voiced and confirmed once again in recent reports and conference addresses [5],[3]. As a result of discussions on the results of the Mulder NSF report following the report's completion it was suggested that recent advancements in information, communication and computer technologies could enable a new and innovative approach to improving the graduates from our university information specialists programs. This new learning/teaching paradigm involves both the universities and the concerned enterprises. The paper that follows presents some of the reasoning and organizational structure for the suggested cooperative approach enabled by information technology, and information regarding some test sites of cooperative programs involving universities and industry.
Efficient Partitioning of Algorithms for Long Convolutions and their Mapping onto Architectures
Authors: Laurens Bierens, Ed Deprettere
Venue: Journal of VLSI Signal Processing Systems (1998)

We present an efficient approach for the partitioning of algorithms implementing long convolutions. The dependence graph (DG) of a convolution algorithm is locally sequential globally parallel (LSGP) partitioned into smaller, less complex convolution algorithms. The LSGP partitioned DG is mapped onto a signal flow graph (SFG), in which each processor element (PE) performs a small convolution algorithm. The key is then to reduce the complexity of the SFG in two steps: 1. local reduction of complexity: the short Fast Fourier Transform (FFT) is used to perform the small convolution within the PE; and 2. global reduction of complexity: the short FFTs within the PEs are relocated to the global level, where redundant short FFT operations are eliminated. The remaining operation within the PEs is now a simple element-wise multiply-add. After a graph transform, the structure of the SFG kernel is recognized as a set of parallel small convolutions. If we use the short FFT to perform these short convolutions, we come to our final realization of the long convolution algorithm. The computational complexity of this realization is close to the optimum for convolutions, that is, O(N log N). Our approach is thus achieving this N log N &ndash;low without having to implement large-size FFTs. We use, instead, small FFT blocks. The advantage is that small FFT transforms are commercially available, and that they can even be implemented in single-chip VLSI architectures. Our final SFG is three dimensional and can be mapped efficiently onto prototype architectures or dedicated VLSI processors. We demonstrate the procedure in the paper by a design example: the implementation of a prototype convolution architecture that we designed for a real-time radar imaging system.
Transistor sizing issues and tool for multi-threshold CMOS technology
Authors: James Kao, Anantha Chandrakasan, Dimitri Antoniadis
Venue: Proceedings of the 34th annual Design Automation Conference (1997)

Multi-threshold CMOS is an increasingly popular circuitapproach that enables high performance and low power operation.However, no methodologies have been developed to size the highV{t} sleep transistor in an intelligent manner that trades off area andperformance. In fact, many attempts at sizing the sleep transistorwithout close consideration of input vector patterns or internalstructures can lead to large overestimates or large underestimatesin sleep transistor sizing. This paper describes some of the issuesinvolved in sizing transistors for MTCMOS and also introduces avariable breakpoint switch level simulator that can rapidly calculatedelay in MTCMOS circuits as functions of design variablessuch as V{dd}, V{t}, and sleep transistor sizing.
Collaborative learning: a case study for CS1 at Grinnell College and Austin
Authors: Henry M. Walker
Venue: ACM SIGCSE Bulletin (1997)

Since Fall, 1992, the author has used techniques of collaborative learning in his sections of CS1 at both Grinnell College and The University of Texas at Austin. These experiments have been successful by various measures: drop rates are very low, students perform well on tests, student motivation and enthusiasm are very high, and the class covers about 20% more material during the semester. This paper describes the approach that has evolved through several iterations of this course.
Signed Binary Addition Circuitry with Inherent Even Parity Outputs
Authors: M. A. Thornton
Venue: IEEE Transactions on Computers (1997)

A signed binary (SB) addition circuit is presented that always produces an even parity representation of the sum word. The novelty of this design is that no extra check bits are generated or used. The redundancy inherent in a SB representation is further exploited to contain parity information.
Lava: hardware design in Haskell
Authors: Per Bjesse, Koen Claessen, Mary Sheeran, Satnam Singh
Venue: Proceedings of the third ACM SIGPLAN international conference on Functional programming (1998)

Lava is a tool to assist circuit designers in specifying, designing, verifying and implementing hardware. It is a collection of Haskell modules. The system design exploits functional programming language features, such as monads and type classes, to provide multiple interpretations of circuit descriptions. These interpretations implement standard circuit analyses such as simulation, formal verification and the generation of code for the production of real circuits.Lava also uses polymorphism and higher order functions to provide more abstract and general descriptions than are possible in traditional hardware description languages. Two Fast Fourier Transform circuit examples illustrate this.
When Are Group Scheduling Tools Useful?
Authors: Jane N. Mosier, Susan G. Tammaro
Venue: Computer Supported Cooperative Work (1997)

A geographically dispersed department at the MITRE Corporation participated in a field test of groupware tools. This paper documents the results of their use of a group scheduling tool, Meeting Maker Version 1.5. Research in the late 1980s showed that early group scheduling tools were not useful, in part because they only benefited some users and hence critical mass could not be attained. This study was undertaken to determine whether and how far the tools have evolved. Participants said that Meeting Maker made it easy to schedule meetings and maintain their calendars, and 90% wished to continue using it after the study was complete. Problems were noted when not everyone used or had access to the tool, and three generic solutions are discussed: capabilities that allow users to communicate with non-users, capabilities that allow users to stay connected, and lightweight methods of participation.
IDDQ Testing of Bridging Faults in Logic Resources of Reconfigurable Field Programmable Gate Arrays
Authors: Lan Zhao, Duncan M. Hank Walker, Fabrizio Lombardi
Venue: IEEE Transactions on Computers (1998)

This paper presents an IDDQ-based test strategy for detecting bridging faults in the logic resources of reprogrammable Field Programmable Gate Arrays (FPGAs). The proposed approach utilizes the programmability of the Configurable Logic Blocks (CLBs) to achieve 100 percent coverage of IDDQ-testable bridging faults. We use a hieararchical approach for generating tests and configurations. At the chip level, the CLBs are viewed as a homogeneous two-dimensional array. Two configuration strategies are suggested to simultaneously test each CLB. Within each CLB, we test for external bridging faults between the combinational and sequential logic modules (e.g., flip-flops, multiplexers, lookup tables). Finally, we test for internal bridging faults within each module based on their implementation. Since reconfiguration programming time dominates total test time, even with slow IDDQ vectors, we use a bottom-up test generation approach to minimize the number of programming phases first and, then, to minimize the number of test vectors. The Xilinx XC4000 family of SRAM-based FPGAs is used as an example application of the proposed approach. One hundred percent coverage for IDDQ-testable bridging faults is achieved in five programming phases and 16 IDDQ vectors. Since the lookup tables in the CLB can be configured as RAM, the RAM modes are also tested. This requires a further phase, using 48 test vectors and 38 IDDQ measurements.
Fitting Monotone Surfaces to Scattered Data Using C1 Piecewise Cubics
Authors: Lu Han, Larry L. Schumaker
Venue: SIAM Journal on Numerical Analysis (1997)

We derive sufficient conditions on the Bézier net of a Bernstein--Bézier polynomial defined on a triangle in the plane to insure that the corresponding surface is monotone. We then apply these conditions to construct a new algorithm for fitting a monotone surface to gridded data. The method uses C1 cubic splines defined on the triangulation obtained by drawing both diagonals of each subrectangle. In addition, we present an algorithm for the monotone scattered data interpolation problem which is based on a method for creating gridded data from the scattered data. Numerical results for several test examples are presented.
Extending microcode compaction for real architectures
Authors: Mark Harris
Venue: Proceedings of the 20th annual workshop on Microprogramming (1987)

Microcode compaction is an essential component of any high-level language compiler that generates microcode for a horizontal architecture machine. Recent research into both local and global compaction has assumed the use of a simple abstract machine. Although this assumption simplifies the effort considerably, it neglects addressing and timing problems brought on by the uncommon operation of some machines. This paper discusses both local and global compaction in terms of the Burroughs D-machine. The D-machine has peculiar timing and an uncommon jump instruction that do not readily fit into proposed compaction algorithms. Methods for handling these problems are presented. In addition, two popular algorithms for performing compaction, list scheduling and trace scheduling, are explained entirely in terms of the D-machine. This should aid the reader in understanding the problem and evaluating any alternatives.
The spineless tagless G-machine, naturally
Authors: Jon Mountjoy
Venue: ACM SIGPLAN Notices (1999)

The application of natural semantic specifications of lazy evaluation to areas such as usage analysis, formal profiling and abstract machine construction has shown it to be a useful formalism. This paper introduces several variants and extensions of this specification.The first variant is derived from observations of the Spineless Tagless G-machine (STG), used in the Glasgow Haskell compiler. We present a modified natural semantic specification which can be formally manipulated to derive an STG-like machine.The second variant is the development of a natural semantic specification which allows functions to be applied to more than one argument at once. The STG and TIM abstract machines both allow this kind of behaviour, and we illustrate a use of this semantics by again modifying this semantics following observations of the STG machine. The resulting semantics can be used to formally derive the STG machine. This effectively proves the STG machine correct with respect to Launchbury's semantics.En route, we also show that update markers in the STG machine are necessary for termination, and show how well-known abstract machine instructions, such as the squeeze operation, appear quite naturally as optimisations of the derived abstract machine.
Inside the APL2 workspace
Authors: James A. Brown
Venue: Proceedings of the international conference on APL: APL and the future (1986)

With the advent of IBM's APL2 Program Product (5668-899) which includes nested arrays and new internal types of data, the physical layout of the workspace has been redesigned. This paper presents the general workspace layout, gives details on the more important entries in the workspace, and discusses the philosophy behind changes made from VS APL.
ATV: an abstract timing verifier
Authors: David E. Wallace, Carlo H. Séquin
Venue: Proceedings of the 25th ACM/IEEE Design Automation Conference (1988)

We discuss implementation and extensions of the Abstract Timing Verifier proposed in [WaS86], in particular, several new operations and a new algorithm for analyzing critical paths that extend through transparent latches and stretch over multiple machine cycles. By placing events in different reference frames that can be translated relative to one another, the program can be used either to check a design for timing errors when the clock schedule is fixed and known, or to derive spacing constraints between clock edges when only the relative ordering of the clock edges is known. The algorithms are designed to operate on a wide variety of representations of time and delay.
Approximate algorithms for time separation of events
Authors: Supratik Chakraborty, David L. Dill
Venue: Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design (1997)

We describe a polynomial-time approximate algorithm for computing minimum and maximum time separations between all pairs of events in systems specified by acyclic timing constraint graphs. Even for acyclic graphs, the problem is NP-complete. We propose finding an approximate solution by first approximating the non-convex feasible space with a suitable convex ``envelope'', and then solving the problem efficiently in the approximate convex space. Unlike previous works, our algorithm can handle both min and max-type timing constraints in the same system, and has a computational complexity that is polynomial in the number of events. Although the computed separations are conservative in the worst-case, experiments indicate that our results are highly accurate in practice.
Using value prediction to increase the power of speculative execution hardware
Authors: Freddy Gabbay, Avi Mendelson
Venue: ACM Transactions on Computer Systems (TOCS) (1998)

This article presents an experimental and analytical study of value prediction and its impact on speculative execution in superscalar microprocessors. Value prediction is a new paradigm that suggests predicting outcome values of operations (at run-time ) and using these predicted values to trigger the execution of true-data-dependent operations speculatively. As a result, stals to memory locations can be reduced and the amount of instruction-level parallelism can be extended beyond the limits of the program's dataflow graph. This article examines the characteristics of the value prediction concept from two perspectives: (1) the related phenomena that are reflected in the nature of computer programs and (2) the significance of these phenomena to boosting instruction-level parallelism of superscalar microprocessors that support speculative execution. In order to better understand these characteristics, our work combines both analytical and experimental studies.