ppxscal/embedding_network huggingface dataset:
Object Exchange Across Heterogeneous Information Sources
Authors: Yannis Papakonstantinou, Hector Garcia-Molina, Jennifer Widom
Venue: Proceedings of the Eleventh International Conference on Data Engineering (1995)

We address the problem of providing integrated access to diverse and dynamic information sources. We explain how this problem differs from the traditional database integration problem and we focus on one aspect of the information integration problem, namely information exchange. We define an object-based information exchange model and a corresponding query language that we believe are well suited for integration of diverse information sources. We describe how, the model and language have been used to integrate heterogeneous bibliographic information sources. We also describe two general-purpose libraries we have implemented for object exchange between clients and servers.
MORALE. Mission ORiented Architectural Legacy Evolution
Authors: Gregory D. Abowd, Ashok K. Goel, Dean F. Jerding, Michael McCracken, Melody M. Moore, J. William Murdock, Colin Potts, Spencer Rugaber, Linda M. Wills
Venue: Proceedings of the International Conference on Software Maintenance (1997)

Software evolution is the most costly and time-consuming software development activity, yet software engineering research is predominantly concerned with initial development. MORALE is a development method specifically designed for evolving software. It features an inquiry-based approach to eliciting change requirements, a reverse engineering technique for extracting architectural information from existing code, an approach to impact assessment that determines the extent to which the existing system's architectural components can be reused in the evolved version, a reflective approach to actually perform the evolution, and a specific technique for dealing with the difficulties that arise when evolving user interfaces. MORALE is described in the context of making a specific change to an existing system: adding user-configurable viewers to Version 2.4 of the Mosaic Web browser. Issues that arise are discussed, and the Esprit de Corps tool-suite is described.
Satisfiability, Branch-Width and Tseitin Tautologies
Authors: Michael Alekhnovich, Alexander A. Razborov
Venue: Proceedings of the 43rd Symposium on Foundations of Computer Science (2002)

For a CNF_\tau, let wb(\tau ) be the bronch-width of its underlying hypergraph. In this paper we design an algorithm for solving SAT in time n^{0(1)} 2^0 (wb(\tau )). This in particular implies a polynomial algorithm for testing satisfiability on instances with tree-width O(log n).Our algorithm is a modification of the width based automated theorem prover (WBATP) which is a popular (at least on the theoretical level) heuristic for finding resolution refutations of unsatisfiable CNFs. We show that instead of the exhaustive enumerotion of all provable clauses, one can do a better search based on the Robertson-Seymour algorithm forapproximating the bronch-width of a graph. We call the resulting procedure Bronch- Width Based Automated Theorem Prover (BWBATP). As opposed to WBATP, it always produces regular refutations. Perhaps more importantly, the running time of our algorithm is boundedin terms of a clean combinatorial charocteristic that can be efficiently approximated, and that the algorithm also produces, within the same time, a satisfying assignment if \tauhappens to be satisfiable.In the second part of the paper we investigate the behavior of BWBATP on the well-studied class of Tseitin tautologies. We argue that in this case BWBATP is better than WBATP. Namely, we show that its running time on any Tseitin tautology \tau is \left| \tau\right|^{0(1)}\cdot 2^{0(w(\tau 1 - 0)} as opposed to the obvious bound n^{0(1)} 2^0 (wb(\tau ))\left| \tau\right|^{0(1)}\cdot 2^{0(w(\tau 1 - 0)} provided by WBATP.This in particular implies that Resolution is automatizable on those Tseitin tautologies for which we know the relation w(\tau 1 - 0) \leqslant 0(\log S(\tau )). We identify one such subclass and prove partial results toward establishing this relation for larger classes of graphs.
Logic Channels: A Coordination Approach to Distributed Programming
Authors: Manuel Diaz, Bartolomé Rubio, José M. Troya
Venue: Proceedings of the 11th International Symposium on Parallel Processing (1997)

In this paper, we present a new coordination model and a small set of programming notations for distributed programming that can be integrated in very different programming languages (imperative, declarative or object oriented). Both together, allow the development of distributed programs in a compositional way, by assembling different independent pieces of (possibly preexisting and heterogeneous) code. This approach is in the spirit of many other similar proposals as Linda, PCN, CC++, etc., but it allows multiparadigm and multilingual integration and provides a powerful set of concurrent programming techniques, inherited from Concurrent Logic Languages (CLLs), that can be efficiently implemented in distributed systems. The coordination model is based on Logic Channels; these are an evolution of the concept of shared logic variable used in CLLs that, with the same expressive power, can be more efficiently implemented in distributed systems.
Reducing Parallel Overheads Through Dynamic Serialization
Authors: Michael Voss, Rudolf Eigenmann
Venue: Proceedings of the 13th International Symposium on Parallel Processing and the 10th Symposium on Parallel and Distributed Processing (1999)

If parallelism can be successfully exploited in a program, significant reductions in execution time can be achieved. However, if sections of the code are dominated by parallel overheads, the overall program performance can degrade. We propose a framework, based on an inspector-executor model, for identifying loops that are dominated by parallel overheads and dynamically serializing these loops. We implement this framework in the Polaris parallelizing compiler and evaluate two portable methods for classifying loops as profitable or unprofitable. We show that for six benchmark programs from the Perfect Club and SPEC 95 suites, parallel program execution times can be improved by as much as 85% on 16 processors of an Origin 2000.
A Cultural Heritage Forum Celebrating Technological Innovation at Station X
Authors: Trevor Collins, Paul Mulholland
Venue: Proceedings of the 13th International Workshop on Database and Expert Systems Applications (2002)

We aim to encourage and support public participation in heritage through the development of Cultural Heritage Forums, a kind of cultural web portal that enables active participation of communities of interest in a way that complements rather than replaces visits to physicalcultural institutions. The cultural heritage forum described here (Station X) is concerned with promoting an understanding of technology innovation in the areas of computing and cryptography. We propose a number of scenarios concerning how the forum can be designed, drawing on our earlier work in using knowledge modelling and text analysis to support the exploration of digital resources.
Shape Evolution Using Restoration Forces
Authors: Andrea G. Campos Bianchi, Hilary G. E. Hentschel, Luciano da Fontoura Costa
Venue: Proceedings of the 15th Brazilian Symposium on Computer Graphics and Image Processing (2002)

This paper presents a mathematical formulation of neural shape changes. The dynamics of the model for the evolution of the elastic cell membrane is based on a system of coupled springs under the action of internal and external forces, based on the biology of neural development and growth. Although this article presents a simple implementation, improvements can be performed by adding active contours to the formulation, enabling a more complete description.
Non-Parametric Smoothing for Relative Radiometric Correction on Remotely Sensed Data
Authors: Maria Luiza F. Velloso, Flávio J. De Souza
Venue: Proceedings of the 15th Brazilian Symposium on Computer Graphics and Image Processing (2002)

Abstract. Digital change detection methods have been broadly divided into either pre-classification spectral change detection or post-classification change detection. Since all spectral change detection methods are based on pixel-wise operations, or scene-wise plus pixel-wise operations, accuracy in image registration and scene-to-scene radiometric normalization is more critical for these methods than for other methods. A wide range of algorithms has been developed to adjust linear models. This paper proposes an automated radiometric normalization process that automatically extracts the training dataset, and uses a non-parametric smoother to adjust a non-linear mapping in order to minimize the effects of the influences of radiometric differences on image interpretation and classification. In order to investigate how the proposed normalization improves the performance classification, and assess the effectiveness of this technique, we carried out classification experiments on three image sets, and compare their results.
Using System Dynamics Modeling to Manage Projects
Authors: Douglas M. Sycamore, James S. Collofello
Venue: 23rd International Computer Software and Applications Conference (1999)

This paper focuses on improving the planning and tracking abilities of software projects through the utilization of system dynamics modeling. A prototyped software project management tool, which incorporates a system dynamics model of the concurrent incremental development process, was developed and is described in this paper. The tool enables project personnel to plan and track a project in terms of schedule, budget, and quality. It also provides a "what if" capability that enables project personnel to assess the impact of proposed project control actions in terms of schedule, budget, and rework hours. These proposed actions are analyzed utilizing the underlying system dynamics model which evaluates the actions in terms of dependencies and feedback loops among project variables. The concepts discussed in this paper and demonstrated through the prototype tool should be integrated into existing project management tools to increase their power and effectiveness.
A prototype router for the massively parallel computer RWC-1
Authors: T. Yokota, H. Matsuoka, K. Okamoto, H. Hirono, A. Hori, S. Sakai
Venue: Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors (1995)

The RWC-1 is a massively parallel computer based on a multi-threaded architecture. This architecture requires extremely high communication performance with reasonable hardware cost. ln this paper, we first introduce a new class of direct interconnection networks called MDCE (Multidimensional Directed Cycles Ensemble extension). MDCE has many desirable features for RWC-1 including small degree, low latency, and high throughput. MDCE is thus adopted for a RWC-1 network. We have designed an MDCE router and fabricated an experimental VLSI chip. We explain the design details in this paper. The chip employs operating system support features as well as communication functions, and enables advanced resource management, A prototype chip with about 125,000 gates has been fabricated using 0.6-/spl mu/m CMOS gate array technology. Its clock runs at 50 MHz and a transmission rate of 300 M bytes per second per communication port is achieved.
Enhancing extensibility of the design rule checker of an EDA tool by object-oriented modeling
Authors: Amir A. Khwaja
Venue: Proceedings of the 21st International Computer Software and Applications Conference (1997)

Design rule checking systems are an integral part of electronic design automation tools. Rapid advances and continuous change in semiconductor technology requires that these DRC systems also change accordingly. The paper presents the architecture and mechanism of the DRC module of an IC package design tool. Design goals were identified for the module to allow easy addition, removal, and modification of rules and to minimize the effect of changes among others. The object oriented modeling technique facilitates the accomplishment of these goals by supporting concepts such as abstraction, encapsulation, inheritance, and dynamic binding. The paper puts these concepts in perspective within the context of the architecture and mechanism of the DRC module.
Individual Knowledge Management with MailTack
Authors: Marco C. Bettoni, Robert Ottiger, Rolf Todesco, Kurt Zwimpfer
Venue: Proceedings of the 13th International Workshop on Database and Expert Systems Applications (2002)

We present our EU-sponsored research in the domain of individual knowledge management and collaborative learning: the MailTack system. MailTack is a stand-alone software tool that we use to understand and support our behaviour in complex e-mail discussions with the aim ofcontributing to a systematic Individual Knowledge Management and Team Learning. Based on a constructivist understanding of knowing, we have developed MailTack as a tool for Persistent Business Discussions combined with an Individual Knowledge Assessment. By helping the involved individuals in improving the effectiveness and efficiency of their asynchronous conversations we think that MailTack could contribute to make collaborative learning and asynchronous interactions (for cooperating, coaching, tutoring, etc.) more successful and attractive thus facilitating the dynamics of Communities of Practice and more generally of learning communities.
Transformable computers hardware object technology
Authors: John Schewel, Michael Thornburg, Steve Casselman
Venue: Proceedings of the 9th International Symposium on Parallel Processing (1995)

We define transformable computing systems as those machines that use the reconfigurable aspects of field programmable gate arrays (FPGA) to implement an algorithm. Researchers throughout the world have shown that computationally intensive software algorithms can be transposed directly into hardware design for extreme performance gain. The on-the-fly use of digital designs in a reconfigurable computer can easily be utilized from within existing software applications. Hardware objects are converted digital designs called from within a software program. This H.O.T. (Hardware Object Technology) method of programming transformable computers is the subject of this paper.
Web Informetrics: Extending Classical Informetrics to the Web
Authors: Devanshu Dhyani, Sourav S. Bhowmick, Wee Keong Ng
Venue: Proceedings of the 13th International Workshop on Database and Expert Systems Applications (2002)

In this paper, we explored the extension of classical informetric theory to the WWW. From the power law distribution of Webpage degrees, we derived other interesting laws that hold for the Web such as Mandelbrot's law, Leimkuhler's law and Bradford's law. We introduced the theory of information producing processes that serves as a generic framework for studying the interrelationships between these informetric regularities. The theory of informetrics leads to a repertoire of metrics for measuring the scale of concentration that can be applied to the WWW.
Modeling the Technology Impact on the Design of a Two-Level Multicomputer Interconnection Network
Authors: José Cruz-Rivera, D. Scott Wills, Thomas Gaylord, Elias Glytsis
Venue: Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors (1996)

The rapid advance of VLSI and packaging technologies has a significant impact on system architecture. In this paper, an analytical model is used to explore the design space of interconnection networks for a 4,096 node processing system incorporating multi-node chips packaged on a single MCM substrate. Possible designs are evaluated for a two-level interconnect with separate k-ary n-cube networks for intrachip and interchip communication. An analysis of the impact several architectural and technological parameters have on the optimal network implementation (based on average no-load latency) is presented.
Failure Handling for Transaction Hierarchies
Authors: Qiming Chen, Umeshwar Dayal
Venue: Proceedings of the Thirteenth International Conference on Data Engineering (1997)

Previously, failure recovery mechanisms have been developed separately for nested transactions and for transactional workflows specified as "flat" flow graphs. The paper develops unified techniques for complex business processes modeled as cooperative transaction hierarchies. Multiple cooperative transaction hierarchies often have operational dependencies, thus a failure occurring in one transaction hierarchy may need to be transferred to another. The existing transaction models do not support failure handling across transaction hierarchies. The authors introduce the notion of transaction execution history tree which allows one to develop a unified hierarchical failure recovery mechanism applicable to both nested and flat transaction structures. They also develop a cross-hierarchy undo mechanism for determining failure scopes and supporting backward and forward failure recovery over multiple transaction hierarchies. These mechanisms form a structured and unified approach for handling failures in flat transactional workflows, along a transaction hierarchy, and across transaction hierarchies.
Integrating Cognitive Support with CASE-Tools for Design Recovery
Authors: Jens H. Jahnke
Venue: Proceedings of the 1st IEEE International Conference on Cognitive Informatics (2002)

Reverse engineering (RE) activities account for the largest part of current expenses in software maintenance. The RE support provided by existing design tools is limited to simple mappings of idioms in the source code to diagrammatic primitives. Human analysts still have togo through the laborious task of manually detecting patterns and creating higher abstractions. Perhaps the most important challenge in automating RE is to deal with the imperfect knowledge inherently involved in the detection process. Recently, a number of researchershave developed prototypes of design tools with knowledge-based RE capabilities. For several reasons these research prototypes are rarely acceptable for industrial-strength applications. Consequently, innovative technologies often have difficulties reaching their target audience. We try to address this issue by adopting established design tools and extending them with knowledge-based RE functionality. This paper reports on the development of such an extension component and contains a case study that shows the feasibility of this approach.
Benefits of Processor Clustering in Designing Large Parallel Systems: When and How?
Authors: Debashis Basak, Dhabaleswar K. Panda, Mohammad Banikazemi
Venue: Proceedings of the 10th International Parallel Processing Symposium (1996)

Advances in multiprocessor interconnect technology are leading to high performance networks. However, software overheads associated with message passing are limiting the processors to get maximum performance from these networks, leading to under-utilization of network resources. Though processor-clusters are being used in some systems in an ad hoc manner to alleviate this problem, there is no formal analysis in the literature to show when and how processor clusters benefit in designing high performance and scalable systems. In this paper we analyze and solve this problem by considering processor-clustering, messaging overheads, and network performance in an integrated manner. Our analysis establishes the following three design guidelines. Compared to a base system, under high messaging overheads, processor clustering can be used to build a) an equal-sized system with a smaller network or b) a larger system with an equal-sized network. Under low messaging overheads, a combination of processor clustering and wider channels can be used to build a range of larger-sized systems. All these guidelines lead to designing cost-effective and scalable parallel systems while delivering high performance.
Deadlock-Free Fault-tolerant Routing in the Multi-dimensional Crossbar Network and Its Implementation for the Hitachi SR2201
Authors: Yoshiko Yasuda, Hiroaki Fujii, Hideya Akashi, Yasuhiro Inagami, Teruo Tanaka, Junji Nakagoshi, Hideo Wada, Tsutomu Sumimoto
Venue: Proceedings of the 11th International Symposium on Parallel Processing (1997)

We have developed a hardware detour path selection facility for the Hitachi SR2201 parallel computer, which uses a multi-dimensional crossbar as an inter-processor network to ensure operating efficiency and high reliability when a part of the network is faulty. when this hardware facility is used, packets are transmitted to their destination along alternative paths to avoid the fault. However, changing the routing may cause deadlock. This paper describes a deadlock-free fault-tolerant routing scheme that can be used by the detour path selection facility to avoid deadlock, and its implementation for the SR2201.
Features of a Web-Oriented Information System
Authors: Petr Kroha, Dany Loeffler
Venue: Proceedings of the 13th International Workshop on Database and Expert Systems Applications (2002)

In this contribution, some typical features of Web-based information system WEBIS are described. WEBIS collects and updates its data automatically using specified Web-pages,notifies changes of used Web-pages, transforms the obtained data into XML documents, stores them into an XML repository, accepts queries and transforms the found data into information.
Hierarchical tiling for improved superscalar performance
Authors: Larry Carter, Jeanne Ferrante, Susan Flynn Hummel
Venue: Proceedings of the 9th International Symposium on Parallel Processing (1995)

It takes more than a good algorithm to achieve high performance: inner-loop performance and data locality are also important. Tiling is a well-known method for parallelization and for improving data locality. However, tiling has the potential of being even more beneficial. At the finest granularity, it can be used to guide register allocation and instruction scheduling; at the coarsest level, it can help manage magnetic storage media. It also can be useful in overlapping data movement with computation, for instance by prefetching data from archival storage, disks and main memory into cache and registers, or by choreographing data movement between processors. Hierarchical tiling is a framework for applying both known tiling methods and new techniques to an expanded set of uses. It eases the burden on several compiler phases that are traditionally treated separately, such as scalar replacement, register allocation, generation of message passing calls, and storage mapping. By explicitly naming and copying data, it takes control of the mapping of data to memory and of the movement of data between processing elements and up and down the memory hierarchy. This paper focuses on using hierarchical tiling to exploit superscalar pipelined processors. On a simple example, it improves performance by a factor of 3, achieving perfect use of the superscalar processor's pipeline. Hierarchical tiling is presented here as a method of hand-tuning performance; while outside the scope of this paper, the ideas can be incorporated into an automatic preprocessor or optimizing compiler.