ppxscal/embedding_network huggingface dataset:
DSP address optimization using a minimum cost circulation technique
Authors: Catherine Gebotys
Venue: Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design (1997)

This paper presents a new approach to solving the DSP address assignment problem. A minimum cost circulation approach is used to efficiently generate high performance addressing code in polynomial time. Addressing code size improvements of up to 7 times are obtained, accounting for up to 1.6 times improvement in code size and performance of compiler-generated DSP code. Results also show that memory layout has a small effect on code size and performance when optimal addressing is used. This research is important for industry since this value-added technique can improve code size, power dissipation and performance, without increasing cost.
A 10-bit 100 MSamples/s BiCMOS D/A Converter
Authors: Ivan Harald Holger Jørgensen, Svein Anders Tunheim
Venue: Analog Integrated Circuits and Signal Processing (1997)

This paper presents a 10-bit Digital-to-Analogue Converter (DAC) based on the current steering principle. The DAC is processed in a 0.8\mu m BiCMOS process and is designed to operate at a sampling rate of 100i>MSamples/s. The DAC is intended for applications using direct digital synthesis, and focus has been set on reducing dynamic nonlinearities to achieve a high spurious free dynamic range (SFDR) at high generated frequencies. The main part of the DAC consists of a matrix of current cells. Each current cell contains an emitter-coupled logic (ECL) flip-flop, clocked by a global ECL clock to ensure accurate clocking. A bipolar differential pair, with a cascode CMOS current sink, steered by the differential output of the ECL flip-flop, is used in each current cell to steer the current. The DAC operates at 5 V, and has a power consumption of approximately 650m W. The area of the chip-core is 2.2mm\times 2.2mm. The measured integral nonlinearity (INL) and differential nonlinearity (DNL) are both approximately 2 LSB. At a generated frequency of f_g\approx 0.1\cdot f_s(f_s = 100\hbox{\it MSamples}/s) the measured SFDR is 50dB, and at f_g\approx 0.3\cdot f_s the measured SFDR is as high as 43dB. The DAC is operating up to a sampling frequency of approximately 140i>MSamples/s. The DAC uses the hierarchical switching scheme and therefore the dynamic performance is not described well using the conventional glitch energy. A new energy measure that replaces the conventional glitch energy is therefore proposed. This energy measure is especially useful during the design phase.
Trace driven logic synthesis&mdash;application to power minimization
Authors: Luca P. Carloni, Patrick C. McGeer, Alexander Saldanha, Alberto L. Sangiovanni-Vincentelli
Venue: Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design (1997)

A trace driven methodology for logic synthesis and optimization is proposed. Given a logic description of a digital circuit C and an expected trace of input vectors T an implementation of C that optimizes a cost function under application of T is derived. This approach is effective in capturing and utilizing the correlations that exist between input signals on an application specific design. The idea is novel since it propose synthesis and optimization at the logic level where the goal is to optimize the average case rather than the worst case for a chosen cost metric. This paper focuses on the development of algorithms for trace driven optimization to minimize the switching power in multi-level networks. The average net power reduction (internal plus I/O power) obtained on a set of benchmark FSMs is 14%, while the average reduction in internal power is 25%. We also demonstrate that the I/O transition activity provides an upper bound on the power reduction that can be achieved by combinational logic synthesis.
Analysis of a variant hypercube topology
Authors: Nian-Feng Tzeng
Venue: ACM SIGARCH Computer Architecture News (1990)

Each node of a hypercube system, when fabricated, comes with a fixed number of links designed for a maximum sized construction. Very often, there are links left unused at each node in a real system. In this article, we study the hypercube in which extra connections are added between pairs of nodes through otherwise unused links. Those extra connections are made in order to maximize the improvement of the performance measure of interest under various traffic distributions. The resulting hypercube, called the variant hypercube, requires a simple routing algorithm and is guaranteed not to create any traffic-congested point or link. The variant hypercube is found to achieve considerable reduction in diameter, and noticeable improvement in mean internode distance and traffic density. In addition, a variant hypercube is more cost-effective than a regular hypercube and does not suffer from practical implementation difficulty. As a result, it also appears advantageous for hypercube systems with no available unused links to augment each node so as to accommodate an extra link, provided that the building block is not pin limited and is allowed to do so.
On the Complexity of Negation-Limited Boolean Networks
Authors: Robert Beals, Tetsuro Nishino, Keisuke Tanaka
Venue: SIAM Journal on Computing (1998)

A theorem of Markov precisely determines the number r of NEGATION gates necessary and sufficient to compute a system of boolean functions F. For a system of boolean functions on n variables, $r\leq b(n)=\lceil\log_2(n+1)\rceil$. We call a circuit using b(n) NEGATION gates negation-limited. We continue recent investigations into negation-limited circuit complexity, giving both upper and lower bounds.A circuit with inputs x1,..., xn and outputs $\neg x_1, \ldots, \neg x_n$ is called an inverter, for which $r=\lceil\log_2(n+1)\rceil$. Fischer has constructed negation-limited inverters of size O(n2 log n) and depth O(log n). Recently, Tanaka and Nishino have reduced the circuit size to O(n log2 n) at the expense of increasing the depth to log2 n. We construct negation-limited inverters of size O(n log n), with depth only O(log n), and we conjecture that this is optimal. We also improve a technique of Valiant for constructing monotone circuits for slice functions (introduced by Berkowitz).Next, we introduce some lower bound techniques for negation-limited circuits. We provide a 5n+3 log(n+1)-c lower bound for the size of a negation-limited inverter. In addition, we show that for two different restricted classes of circuit, negation-limited inverters require superlinear size.
Uniform versus priority dropping for layered video
Authors: Sandeep Bajaj, Lee Breslau, Scott Shenker
Venue: ACM SIGCOMM Computer Communication Review (1998)

In this paper, we analyze the relative merits of uniform versus priority dropping for the transmission of layered video. We first present our original intuitions about these two approaches, and then investigate the issue more thoroughly through simulations and analysis in which we explicitly model the performance of layered video applications. We compare both their performance characteristics and incentive properties, and find that the performance benefit of priority dropping is smaller than we expected, while uniform dropping has worse incentive properties than we previously believed.
Device reservation in audio/video editing systems
Authors: David P. Anderson
Venue: ACM Transactions on Computer Systems (TOCS) (1997)

What fraction of disks and other shared devices must be reserved to play an audio/video document without dropouts? In general, this question cannot be answered precisely. For documents with complex and irregular structure, such as those arising in audio/video editing, it is difficult even to give a good estimate. We describe three approaches to this problem. The first, based on long-term average properties of segments, is fast but imprecise: it underreserves in some cases and overreserves in others. The second approach models individual disk and network operations. It is precise but slow. The third approach, a hybrid, is both precise and fast.
Analog Universal Active Device: Theory, Design and Applications
Authors: Rafael Cabeza, Alfonso Carlosena
Venue: Analog Integrated Circuits and Signal Processing (1997)

This paper introduces the concept of what we call analog Universal Active Device (UAD), as a step forward from Operational Amplifiers and other recently proposed active devices. The model for such a device is nothing but a two port classically known as Nullor. To obtain practical implementations of the UAD, or Nullor, a unified aproach is proposed. The basis of the approach is the use of a single cell consisting of a voltage and current buffer, also known as negative second-generation Current Conveyor (CCII &ndash;). We obtained the four most simple implementations for the UAD as a paradigm of more complex ones. Non ideal effects of these practical implementations are theoretically analysed, particularly parasitic impedances associated to the interconnections of the CCII &ndash; cells, and then their influence in some simple amplifier stages. It is demonstrated that while any UAD implementation can be used in a given application, its performance is strongly dependent on its implementation. Also, a novel floating structure for a General Impedance Converter (GIC) type impedance, containing two UADs, is suggested. Simulation results are given supporting the ideas presented here.
What is a design automation framework, anyway? (panel)
Authors: Wayne Wolf
Venue: Proceedings of the 25th ACM/IEEE Design Automation Conference (1988)

Over the past decade the number of CAD tools used in the design of a complex electronic system has increased significantly. With this increase has come a nightmare of design data management, tool integration problems, design-flow management, and multiple, inconsistent user interfaces. 'CAD Frameworks' promise to solve many or all of these problems by providing a flexible environment for customizing design flow and user-interface, while managing component versions and using a common data model for many or all tools. But do the existing CAD Frameworks really solve all of these problems or do they only solve the 'easy ones'? Is a single, integrated data model really necessary? Does it even help? What about the role of configuration management? How big do these databases get, anyway? Wouldn't it be better to wait for object-oriented' software technology to solve this problem rather than investing in a framework today? Can third-party tools be added to the framework easily or does the integrator end up writing translators anyway? If a user puts all of their design data into a particular framework, how can they extract it if they want to move to a new framework later? Will there ever be a 'Standard Data Management Interface'? Where do EDIF, VHDL, and other standards fit in? What happens if the existing tools run on a variety of computer types and operating systems? The ACM Portal is published by the Association for Computing Machinery. Copyright © 2010 ACM, Inc. Terms of Usage Privacy Policy Code of Ethics Contact Us Useful downloads: Adobe Acrobat QuickTime Windows Media Player Real Player
Operation scheduling in reconfigurable, multifunction pipelines
Authors: Jack Walicki, John D. Laughlin
Venue: Proceedings of the 20th annual workshop on Microprogramming (1987)

One of the key issues in the efficient use of pipelines is the problem of pipeline scheduling. An overview of the research in pipeline scheduling is presented. The scheduling problem for multifunction, dynamically reconfigurable pipelines is studied from the point of view of retargetable microcode compilation. A modified greedy strategy using the criterion of the earliest completion time tc is presented with an example.
Multi-pads, single layer power net routing in VLSI circuits
Authors: H. Cai
Venue: Proceedings of the 25th ACM/IEEE Design Automation Conference (1988)

An algorithm is presented for obtaining a planar routing of two power nets in building-block layout. In contrast to other works, more than one pad for each of the power nets is allowed. First, conditions are established to guarantee a planar routing. The algorithm consists of three parts, a top-down terminal clustering, a bottom-up topological path routing and a wire width calculation procedure. Because of the hierarchical nature of the algorithm, it is inherently fast.
Alternate structures for public power systems
Authors: Thomas D. Clark,  Jr., William A. Bailey,  Jr.
Venue: Proceedings of the 17th conference on Winter simulation (1985)

The basic structure of interacting public utility systems is addressed in the paper. Several alternative structures dealing with networking and shared resources recently have been proposed. These structures are considered by using a system dynamics model to explore system behavior under various options. Various types of utilities, demand sources, and power types may be addressed using the model.
GPS-based Clock Synchronization in a Mobile, Distributed Real-Time System
Authors: Bernhard Sterzbach
Venue: Real-Time Systems (1997)

In a vehicle tracking system computers aboard moving vehicles determine periodically their geographical position and transmit it to a control center. This paper presents a commercial vehicle tracking system as an example of a distributed real-time system with mobile components and focuses on the issue of clock synchronization. The mobile components of the system obtain highly accurate timing information from the Global Positioning System which is used to synchronize their local clocks to UTC world time. Thus a tight clock synchronization is achieved without imposing additional load on the communication channels of the system.
Probabilistic models for document retrieval: a comparison of perfromance on exterimental and synthetic data bases
Authors: Robert Losee, Abraham Bookstein, Clement T. Yu
Venue: Proceedings of the 9th annual international ACM SIGIR conference on Research and development in information retrieval (1986)

Probabilistic document retrieval systems consistent with the two Poisson independence model outperforms the binary independence model if the terms are distributed as described by the model's assumptions. The Two Poisson Effectiveness Hypothesis suggests that retrieval models based upon the two Poisson model will outperform binary independent models when used on a &ldquo;real-world&rdquo; database, where independence and two Poisson term occurrence distributions fail to hold, because the added information obtained from incorporating term frequency information will more than compensate for the non-Poisson distributions of terms. Searches of the MED1033 database suggest that if terms are not independent and frequencies of term occurrence are not distributed in a two Poisson manner, the binary independence sequential retrieval model outperforms the two Poisson independence retrieval model.
Unsupervised Texture Segmentation in a Deterministic Annealing Framework
Authors: Thomas Hofmann, Jan Puzicha, Joachim M. Buchmann
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1998)

We present a novel optimization framework for unsupervised texture segmentation that relies on statistical tests as a measure of homogeneity. Texture segmentation is formulated as a data clustering problem based on sparse proximity data. Dissimilarities of pairs of textured regions are computed from a multiscale Gabor filter image representation. We discuss and compare a class of clustering objective functions which is systematically derived from invariance principles. As a general optimization framework, we propose deterministic annealing based on a mean-field approximation. The canonical way to derive clustering algorithms within this framework as well as an efficient implementation of mean-field annealing and the closely related Gibbs sampler are presented. We apply both annealing variants to Brodatz-like microtexture mixtures and real-word images.
Efficient Parallel Manipulations of IBB Coded Imageson Meshes with Multiple Broadcasting
Authors: Kuo-Liang Chung
Venue: Journal of Mathematical Imaging and Vision (1997)

The Interpolation-Based Bintree (IBB) is a storage-saving encoding scheme for representing binary images. In this paper, we present efficient parallel algorithms for important manipulations on IBB coded images (also called bincodes). Given a set of bincodes, e.g.,B with size n, the 4-neighbor finding and the diagonal-neighbor finding algorithms onB can be accomplished in O(1) time on ann x n mesh computer with multiple broadcasting (MMB). Given two sets of bincodes, B_1 andB_2 , with size n and m &le; n, respectively, the intersection and union operations for B_1 and B_2 can be performed in O(1) time on an MMB using (n+m)^2 processors. With n^2 processors, the complement operation for B can be performed in O(Log n) time.
Physically Based Adaptive Preconditioning for Early Vision
Authors: Shang-Hong Lai, Baba C. Vemuri
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1997)

Several problems in early vision have been formulated in the past in a regularization framework. These problems, when discretized, lead to large sparse linear systems. In this paper, we present a novel physically based adaptive preconditioning technique which can be used in conjunction with a conjugate gradient algorithm to dramatically improve the speed of convergence for solving the aforementioned linear systems. A preconditioner, based on the membrane spline, or the thin plate spline, or a convex combination of the two, is termed a physically based preconditioner for obvious reasons. The adaptation of the preconditioner to an early vision problem is achieved via the explicit use of the spectral characteristics of the regularization filter in conjunction with the data. This spectral function is used to modulate the frequency characteristics of a chosen wavelet basis, and these modulated values are then used in the construction of our preconditioner. We present the preconditioner construction for three different early vision problems namely, the surface reconstruction, the shape from shading, and the optical flow computation problems. Performance of the preconditioning scheme is demonstrated via experiments on synthetic and real data sets. We note that our preconditioner outperforms other methods of preconditioning for these early vision problems, described in computer vision literature.
AweSim: the integrated simulation system
Authors: A. Alan B. Pritsker, Jean J. O'Reilly
Venue: Proceedings of the 28th conference on Winter simulation (1996)

AweSim is a totally new general-purpose simulation system, released in June of 1996. AweSim takes advantage of the latest in Windows technology to integrate programs and provide componentware. AweSim includes the Visual SLAM simulation language to build network, discrete event, and continuous models. Network models require no programming yet allow user-coded inserts in Visual Basic or C. Discrete event and continuous models can be created using the object-oriented technology of Visual Basic, C or Visual C++ and can be combined with network models. This tutorial will demonstrate the process of using AweSim's componentware and provide examples of user interfaces that allow integration with other Windows applications both directly and through the AweSim database.
Multigrid Methods for Nearly Singular Linear Equations and Eigenvalue Problems
Authors: Zhiqiang Cai, Jan Mandel, Steve McCormick
Venue: SIAM Journal on Numerical Analysis (1997)

The purpose of this paper is to develop a convergence theory for multigrid methods applied to nearly singular linear elliptic partial differential equations of the type produced from a positive definite system by a shift with the identity. One of the important aspects of this theory is that it allows such shifts to vary anywhere in the multigrid scheme, enabling its application to a wider class of eigenproblem solvers. The theory is first applied to a method for computing eigenvalues and eigenvectors that consists of multigrid iterations with zero right-hand side and updating the shift from the Rayleigh quotient before every cycle. It is then applied to the Rayleigh quotient multigrid (RQMG) method, which is a more direct multigrid procedure for solving eigenproblems. Local convergence of the multigrid V-cycle and global convergence for a full multigrid version of both methods is obtained.
Analysis of simulation of output data
Authors: W. David Kelton
Venue: Proceedings of the 17th conference on Winter simulation (1985)

The problem of analysis of simulation output data is motivated and put in the context of related methodological problems. Examples are given to indicate why this problem is important, and why it is difficult.
A new area and shape function estimation technique for VLSI layouts
Authors: Gerhard Zimmerman
Venue: Proceedings of the 25th ACM/IEEE Design Automation Conference (1988)

Area estimation of IC layouts has become an important requirement for early design and top-down chip planning tools. Especially the relation of area and aspect ratio (shape function) is necessary for chip planning. Statistical models have been published with good results for standard cell blocks with near unity aspect ratios. This paper describes a new model for the prediction of shape functions for aspect ratios up to 1:5. The model is based on the shape and connectivity of adjacent cells. It can be used for many different design styles and has been tested for standard cell blocks and for the placement of general cells. Categories: 6, 9
COMFY&mdash;comfortable set of control primitives for machine language programming
Authors: Henry G. Baker
Venue: ACM SIGPLAN Notices (1997)

Structured programming advocates the elimination of the GOTO from the set of primitives for a computer language. Yet at the machine language level, almost all machines offer only the conditional or unconditional branch as the basic control primitive. Vaughan Pratt has suggested using instead pseudo-non-deterministic programming (as well as the COMFY name). We present a new set of machine language control primitives based on Pratt's suggestion which are simpler to implement than if-then-else and do-while and are more flexible at the same time. The machine language implementation of these primitives requires nothing more complicated than a stack; the size of the stack needed (exclusive of programmer-defined subroutine control points) is O(d), where d is the operator depth of the program. This is much less space and machine complexity than would be required for a true backtracking control structure. The user can emulate if-then-else, do-while, repeat-until, etc., with macros using these primitives if he so desires.
Immersed Interface Methods for Stokes Flow with Elastic Boundaries or Surface Tension
Authors: Randall J. LeVeque, Zhilin Li
Venue: SIAM Journal on Scientific Computing (1997)

A second-order accurate interface tracking method for the solution of incompressible Stokes flow problems with moving interfaces on a uniform Cartesian grid is presented. The interface may consist of an elastic boundary immersed in the fluid or an interface between two different fluids. The interface is represented by a cubic spline along which the singularly supported elastic or surface tension force can be computed. The Stokes equations are then discretized using the second-order accurate finite difference methods for elliptic equations with singular sources developed in our previous paper [SIAM J. Numer. Anal., 31(1994), pp. 1019--1044]. The resulting velocities are interpolated to the interface to determine the motion of the interface. An implicit quasi-Newton method is developed that allows reasonable time steps to be used.