ppxscal/embedding_network huggingface dataset:
Color and Sound in Algorithm Animation
Authors: Marc H. Brown, John Hershberger
Venue: Computer (1992)

The techniques developed by M. M. Brown and R. Sedgewick (1985) in using the Balsa algorithm-animation system are reviewed. Techniques that focus on color and sound, areas just opening up in workstation-based interactive algorithm-animation systems, are described. Color is used for encoding the state of data structures, highlighting activity, trying multiple views together, emphasizing patterns, and making an algorithm's history visible in a single static image. Sound is used for reinforcing visuals, conveying patterns, replacing visuals, and signaling exceptional conditions. The techniques are based on work done with the Zeus algorithm-animation system. Six screen dumps from six different algorithm animations that are representative of the was Zeus was used are presented.
Expanding Automotive Electronic Systems
Authors: Gabriel Leen, Donal Heffernan
Venue: Computer (2002)

The past four decades have witnessed an exponential increase in the number and sophistication of electronic systems in vehicles. In 1977, the value of electronics systems and silicon components-such as transistors, microprocessors, and diodes-in motor vehicles averaged $110, while in 2001 it had increased to $1,800. Today, the cost of electronics in luxury vehicles can amount to more than 23 percent of the total manufacturing cost. Analysts estimate that more than 80 percent of all automotive innovation now stems from electronics. Today's high-end vehicles may have more than 4 kilometers of wiring-compared to 45 meters in vehicles manufactured in 1955. Reducing wiring mass through in-vehicle networks will bring an explosion of new functionality and innovation. Our vehicles will become more like PCs, creating the potential for a host of plug-and-play devices. On average, US commuters spend 9 percent of their day in an automobile. Thus, introducing multimedia and telematics to vehicles will increase productivity and provide entertainment for millions. Further, X-by-wire solutions will make computer diagnostics a standard part of mechanics' work and may even create an electronic chauffeur.
Composition of Image Analysis Processes Through Object-Centered Hierarchical Planning
Authors: Leiguang Gong, Casimir A. Kulikowski
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1995)

This paper presents a new approach to the knowledge-based composition of processes for image interpretation and analysis. Its computer implementation in the VISIPLAN (VISIon PLANner) system provides a way of modeling the composition of image analysis processes within a unified, object-centered hierarchical planning framework. The approach has been tested and shown to be flexible in handling a reasonably broad class of multi-modality biomedical image analysis and interpretation problems. It provides a relatively general design or planning framework, within which problem-specific image analysis and recognition processes can be generated more efficiently and effectively. In this way, generality is gained at the design and planning stages, even though the final implementation stage of interpretation processes is almost invariably problem- and domain-specific.
Using Inspection Data for Defect Estimation
Authors: Stefan Biffl
Venue: IEEE Software (2000)

This article pro-poses subjective team estimation models calculated from individual estimates and investigates the accuracy of defect estimation models based on inspection data.
Class-Congruence Property and Two-Phase Routing of Borel Cayley Graphs
Authors: Bruce W. Arden, K. Wendy Tang
Venue: IEEE Transactions on Computers (1995)

Dense, symmetric graphs are useful interconnection models for multicomputer systems. Borel Cayley graphs, the densest degree-4 graphs for a range of diameters [1], are attractive candidates. However, the group-theoretic representation of these graphs makes the development of efficient routing algorithms difficult. In earlier reports, we showed that all degree-4 Borel Cayley graphs have generalized chordal ring (GCR) and chordal ring (CR) representations [2], [3]. In this paper, we present the class-congruence property and use this property to develop the two-phase routing algorithm for Borel Cayley graphs in a special GCR representation. The algorithm requires a small space complexity of O(p+k) for n=p×k nodes. Although suboptimal, the algorithm finds paths with length bounded by 2D, where D is the diameter. Furthermore, our computer implementation of the algorithm on networks with 1,081 and 15,657 nodes shows that the average path length is on the order of the diameter. The performance of the algorithm is compared with that of existing optimal and suboptimal algorithms.
A Systematic Methodology for the Design of High Performance Recursive Digital Filters
Authors: John V. McCanny, Stephen E. McQuillan
Venue: IEEE Transactions on Computers (1995)

A systematic design methodology is described for the rapid derivation of VLSI architectures for implementing high performance recursive digital filters, particularly ones based on most significant digit (msd) first arithmetic. The method has been derived by undertaking theoretical investigations of msd first multiply-accumulate algorithms and by deriving important relationships governing the dependencies between circuit latency, levels of pipelining and the range and number representations of filter operands. The techniques described are general and can be applied to both bit parallel and bit serial circuits, including those based on on-line arithmetic. The method is illustrated by applying it to the design of a number of highly pipelined bit parallel IIR and wave digital filter circuits. It is shown that established architectures, which were previously designed using heuristic techniques, can be derived directly from the equations described.
Composable Semantic Models for Actor Theories
Authors: Carolyn L. Talcott
Venue: Higher-Order and Symbolic Computation (1998)

We are interested in developing a semantic foundation that supports specifying, composing, and reasoning about components of open distributed systems. The actor model provides the basic elements for open distributed computation: encapsulation of state&semi; independent concurrent units of computation&semi; interaction&semi; and dynamic creation and interconnection. In order to provide for composability, and for reasoning about properties at many different levels of abstraction we introduce the notions of actor component, actor component algebra, and actor component algebra morphism. Morphisms from syntactic to semantic algebras give composable semantics.We first illustrate features of the actor model and a variety of component algebras and morphisms through a series of simple examples. We then define three semantic models for actor computation starting with a generalization to open systems of Clinger&lsquo;s event diagram model, and forming two abstractions: interaction diagrams and interaction paths. An algebra is defined on each semantic domain with operations for parallel composition, hiding of internal actors, and renaming, and we show that component algebra laws hold. We use these models to provide semantics for descriptions of actor components based on actor theories and show that the semantics is a component algebra homomorphism.
Software Component Licensing: A Primer
Authors: Andrea Chávez, Catherine Tornabene, Gio Wiederhold
Venue: IEEE Software (1998)

For developers to feel it worthwhile to invest in software components, both licensors and licensees must be fairly compensated for the time and resources invested in making and using such components. The authors suggest that properly framed software licensing agreements provide the vehicle for ensuring such compensation.
Constructing Covering Codes with Given Automorphisms
Authors: Patric R. J. \"Osterg\Aa Rd, William D. Weakley
Venue: Designs, Codes and Cryptography (1999)

Let K(n,r) denote the minimum cardinality of a binary covering code of length n and covering radius r. Constructions of covering codes give upper bounds on K(n,r). It is here shown how computer searches for covering codes can be sped up by requiring that the code has a given (not necessarily full) automorphism group. Tabu search is used to find orbits of words that lead to a covering. In particular, a code D is found which proves K(13,1) \leq 704, a new record. A direct construction of D is given, and its full automorphism group is shown to be the general linear group GL(3,3). It is proved that D is a perfect dominating set (each word not in D is covered by exactly one word in D) and is a counterexample to the recent Uniformity Conjecture of Weichsel.
Parallel Fiber-Optic SCI Links
Authors: David R. Engebretsen, Daniel M. Kuchta, Richard C. Booth, John D. Crow, Wayne G. Nation
Venue: IEEE Micro (1996)

This work was supported by ARPA under contract MDA972-92-C-0075 and by the IBM Corporation. Dave Engebretsen was employed by the IBM Corporation at the time this work was performed.As the drive to include more and more processors and I/O devices in a parallel processor complex continues, box-to-box interconnection links capable of delivering bandwidth comparable to system backplanes is required. Point-to-point links overcome the speed and cost constraints of shared busses; however, copper-based point-to-point links are limited in the distance they can reliably carry high-speed data. At data rates of 500 Mbits/second/line, parallel copper has a practical limit of about 10 meters. Links based on parallel optical fiber can substantially increase the transmission distance and surpass the bandwidth capability of copper. Optical transmitter and receiver modules supporting a 500 MHz, 32-bit wide fiber link, with a peak bandwidth of 2 GBytes/second, have been integrated with a 500 MHz, 18-bit wide SCI-Link module. The parallel fiber optic technology was developed by the Optoelectronics Technology Consortium (OETC) while the high-bandwidth Scalable Coherent Interface-Link (SCI-Link) module was developed by IBM. Laboratory tests have demonstrated operation of a 100-meter link at a speed of 512 MHz.
Distributed Memory Compiler Design For Sparse Problems
Authors: Raja Das, Janet Wu, Joel Saltz, Harry Berryman, Seema Hiranandani
Venue: IEEE Transactions on Computers (1995)

This paper addresses the issue of compiling concurrent loop nests in the presence of complicated array references and irregularly distributed arrays. Arrays accessed within loops may contain accesses that make it impossible to precisely determine the reference pattern at compile time. This paper proposes a run time support mechanism that is used effectively by a compiler to generate efficient code in these situations. The compiler accepts as input a Fortran 77 program enhanced with specifications for distributing data, and outputs a message passing program that runs on the nodes of a distributed memory machine. The runtime support for the compiler consists of a library of primitives designed to support irregular patterns of distributed array accesses and irregularly distributed array partitions. A variety of performance results on the Intel iPSC/860 are presented.
Retraction Approach to CPS Transform
Authors: Jakov Kučan
Venue: Higher-Order and Symbolic Computation (1998)

We study the continuation passing style (CPS) transform and its generalization, the computational transform, in which the notion of computation is generalized from continuation passing to an arbitrary one. To establish a relation between direct style and continuation passing style interpretation of sequential call-by-value programs, we prove the Retraction Theorem which says that a lambda term can be recovered from its CPS form via a &lambda;-definable retraction. The Retraction Theorem is proved in the logic of computational lambda calculus for the simply typable terms.
Some Codes for Correcting and Detecting Unidirectional Byte Errors
Authors: Y. Saitoh, H. Imai
Venue: IEEE Transactions on Computers (1993)

Codes for correcting and detecting unidirectional byte errors are investigated. The relations between distances and the error-correcting and -detecting capabilities of such codes are derived. It is shown that a two-fold unidirectional b-bit-byte error-correcting (2-UbEC) code requires at least three check bytes and that a one-fold unidirectional b-bit-byte error-correcting/2-fold unidirectional b-bit-byte error-detecting (1-UbEC/2-UbED) code requires at least two check bytes. Construction methods for 2-UbEC codes with three check bytes and 1-UbEC/2-UbEd codes with two check bytes are proposed.
Fuzzylot: a novel self-organising fuzzy-neural rule-based pilot system for automated vehicles
Authors: Michel Pasquier, Chai Quek, Mary Toh
Venue: Neural Networks (2001)

This paper presents part of our research work concerned with the realisation of an Intelligent Vehicle and the technologies required for its routing, navigation, and control. An automated driver prototype has been developed using a self-organising fuzzy rule-based system (POPFNN-CRI(S)) to model and subsequently emulate human driving expertise. The ability of fuzzy logic to represent vague information using linguistic variables makes it a powerful tool to develop rule-based control systems when an exact working model is not available, as is the case of any vehicle-driving task. Designing a fuzzy system, however, is a complex endeavour, due to the need to define the variables and their associated fuzzy sets, and determine a suitable rule base. Many efforts have thus been devoted to automating this process, yielding the development of learning and optimisation techniques. One of them is the family of POP-FNNs, or Pseudo-Outer Product Fuzzy Neural Networks (TVR, AARS(S), AARS(NS), CRI, Yager). These generic self-organising neural networks developed at the Intelligent Systems Laboratory (ISL/NTU) are based on formal fuzzy mathematical theory and are able to objectively extract a fuzzy rule base from training data. In this application, a driving simulator has been developed, that integrates a detailed model of the car dynamics, complete with engine characteristics and environmental parameters, and an OpenGL-based 3D-simulation interface coupled with driving wheel and accelerator/ brake pedals. The simulator has been used on various road scenarios to record from a human pilot driving data consisting of steering and speed control actions associated to road features. Specifically, the POPFNN-CRI(S) system is used to cluster the data and extract a fuzzy rule base modelling the human driving behaviour. Finally, the effectiveness of the generated rule base has been validated using the simulator in autopilot mode.
A Comprehensive Performance Evaluation of Crossbar Networks
Authors: H. Y. Youn, C. C. Y. Chen
Venue: IEEE Transactions on Parallel and Distributed Systems (1993)

A comprehensive model for evaluating crossbar networks in which the memory bandwidth and processor acceptance probability are primary measures considered is presented. This analytical model includes all important network control policies, such as the bus arbitration and rejected request handling policies, as well as the home memory concept. Computer simulation validates the correctness of the model. It is confirmed that the home memory and dynamic bus arbitration policy improve the network performance.
Transistor-level timing analysis using embedded simulation
Authors: Pawan Kulshreshtha, Robert Palermo, Mohammad Mortazavi, Cyrus Bamji, Hakan Yalcin
Venue: Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design (2000)

A high accuracy system for transistor-level static timing analysis is presented. Accurate static timing verification requires that individual gate and interconnect delays be accurately calculated. At the sub-micron level, calculating gate and interconnect delays using delay models can result in reduced accuracy. Instead, the proposed method calculates delays through numerical integration using an embedded circuit simulator. It takes into account short circuit current and carefully chooses the set of conditions that results in a tight upper bound of the worst case delay for each gate. Similar repeating transistor configurations of gates in the circuit are automatically identified and a novel interpolation based caching scheme quickly computes gate delays from the delays of similar gates. A tight object code level integration with a commercial high speed transistor-level circuit simulator allows efficient invocation of the simulation.
An Object-Oriented Database System Jasmine: Implementation, Application, and Extension
Authors: Hiroshi Ishikawa, Yasuo Yamane, Yoshio Izumida, Nobuaki Kawato
Venue: IEEE Transactions on Knowledge and Data Engineering (1996)

New applications such as engineering tasks require complex object modeling, integration of database and programming facilities, and extensibility. We have devised an Object-Oriented DBMS called Jasmine for such advanced applications. This paper describes the implementation, application, and extension of Jasmine in detail. First, we focus on the impact of the design of its Object-Oriented model and language on database implementation technology. We describe what part of traditional relational database technology we extend to handle Object-Oriented features such as object identifiers, complex objects, class hierarchies, and methods. We introduce nested relations to efficiently store and access clustered complex objects. We use hash-based methods to efficiently access nonclustered complex objects. We provide user-defined functions directly evaluated on page buffers to efficiently process method invocation. We devise Object-Oriented optimization of queries including class hierarchies, complex objects, and method invocation. We incorporate dedicated object buffering to allow efficient access to objects through object identifiers. Second, we describe nontrivial applications of Jasmine and discuss the validity of Object-Oriented databases. We focus on a constraint management facility, which can be implemented by taking advantage of the extensibility of Jasmine. The facility includes constraint rules, called design goals, for automatic database population required by engineering applications. Third, we describe a view facility for schema integration also needed by engineering applications in distributed environments. We focus on how we extend Jasmine to implement the facility.
Collision Detection of a Moving Polygon in the Presence of Polygonal Obstacles in the Plane
Authors: C. A. Wang
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1994)

This paper presents a new approach for the following collision detection problem in the plane: Let a simple polygon P rotate at a center /spl ogr/ with constant angular velocity /spl omega/ and translate towards a set of polygonal obstacles S with constant velocity /spl nu/. Given P and S as well as their initial positions, and given also the velocities of P, determine whether or not P will collide with any element of S and report the collided elements of S if collisions occurred. An O(mn) worst-case optimal algorithm is proposed to solve this problem, where n is the number of vertices of P and m is the number of vertices of the obstacles in S.
Tools for Business-Process Reengineering
Venue: IEEE Software (1994)

Not every attempt at business process reengineering has been a success. Part of the reason is that traditional modeling and analysis tools are simplistic. Business processes are dynamic and they interact. Static process modeling tools reveal only what happens within a process, what it uses as input, and what it outputs. Business planners also need behavioural modeling which reveals how a business process operates. The author discusses the selection of process engineering tools and their various requirements.
The DSP32C: AT&T's Second Generation Floating Point Digital Signal Processor
Authors: Michael L. Fuccio, Renato N. Gadenz, Craig J. Garen, Joan M. Huser, Benjamin Ng, Steven P. Pekarich, Kreg D. Ulery
Venue: IEEE Micro (1988)

The WEDSP32C high-performance, programmable digital signal processor supports 32-bit floating-point arithmetic and is upwardly compatible with its predecessor, the WEDSP32. Because it is implemented in 0.75- mu m (effective channel length) CMOS technology, the second-generation device achieves high functional density with low power consumption. The DSP32C offers the following features: 25-Mflop operation; 16-Mb/s serial-input and serial-output ports; a 160-bit, parallel I/O port for control and data transfer; interrupt facilities; single-instruction mu -law and A-law data conversions; single-instruction conversions between integers and floating-point data; a byte-addressable, on-chip memory that is extendable off chip; direct memory access to and from internal and external memory via parallel and serial I/O ports; 16 Mbytes of address space; and IEEE Std. 754 floating-point format conversion. The authors describe the DSP32C's instruction set, architecture, and application development tools. The latter includes an assembler, a simulator, an optimizing C compiler, and special-purpose hardware.
A genetic classification error method for speech recognition
Authors: S. Kwong, Q. H. He, K. W. Ku, T. M. Chan, K. F. Man, K. S. Tang
Venue: Signal Processing (2002)

In this paper, we present a genetic approach for training hidden Markov models using minimum classification error (MCE) as the reestimation criteria. This approach is discriminative and proved to be better than other non-discriminative approach such as the maximum likelihood (ML) method. The major problem of using the MCE is to formulate the error rate estimate as a smooth continuous loss function such that the gradient search techniques can be applied to search for the solutions. A genetic approach for this particular classification error method aimed at finding the global solution or better optimal solutions is proposed. Comparing our approach with the ML and MCE approaches, the experimental results showed that it is superior to both the MCE and ML methods.
Development of a Class of Distributed Termination Detection Algorithms
Authors: D. Kumar
Venue: IEEE Transactions on Knowledge and Data Engineering (1992)

Accessing and updating information in a self organizing data structure in a distributed environment requires execution of various distributed algorithms. Design of such algorithms is often facilitated by the use of a distributed termination detection algorithm superimposed on top of another distributed algorithm. The problem of distributed termination detection is considered, and message counting is introduced as an effective technique in designing such algorithms. A class of efficient algorithms, based on the idea of message counting, for this problem is presented. After termination has occurred, it is detected within a small number of message communications. These algorithms do not require the FIFO (first in, first out) property for the communication lines. Assumptions regarding the connectivity of the processes are simple. The algorithms are incrementally developed, i.e. a succession of algorithms leading to the final algorithms is presented.