ppxscal/embedding_network huggingface dataset:
The glass ceiling: in theory women swell ranks of science, but remain invisible at the top
Authors: Natalie Angier
Venue: ACM SIGACT News (1991)

[I]n extensive interviews with women at all stages of their scientific careers and in a broad variety of disciplines, the researchers insisted that in fact some of the difficulties they encountered were peculiar to their trade, and that certain characteristics of the scientific culture were likelier to impede women's progress than to propel it.Among those characteristics is the extreme insularity of science, and the need to be at the center of the rumor mill if one is to hear of vital new results before competitors do ...They also said they were given far fewer chances to present their findings and ideas to powerful audiences of their peers, a key method of winning converts and scientific influence ...[M]any female scientists believe that when conference organizers put together their roster of speakers, deciding who are the most respected elders, or the hottest young turks, women seem to come to mind rarely...Despite the greater opportunities in the lower ranks, women remain poorly represented in the upper echelons...'Women appear invisible to men,' said Dr. Margaret Davis ... 'If you ask men for the names of seminar or symposium speakers, the names you get back are almost invariably male. If you ask women, you get both male and female names.' ...'We've got lots of women on the panel,' [Dr. Darrell S. Rigel] said. But on checking the exact number, he laughed nervously. 'Oh, wait a minute. Only 2 out of 28. Hmm. It never occurred to me. I just don't choose people on the basis of gender. But this does raise my consciousness.'...
A Hardware-Oriented Algorithm for Floating-Point Function Generation
Authors: E. Pearse O'Grady, Baek-Kyu Young
Venue: IEEE Transactions on Computers (1991)

An algorithm is presented for performing accurate, high-speed, floating-point function generation for univariate functions defined at arbitrary breakpoints. Rapid identification of the breakdown interval, which includes the input argument, is shown to be the key operation in the algorithm. A hardware implementation which makes extensive use of read/write memories is used to illustrate the algorithm.
The consortium for lexical research
Venue: Proceedings of the workshop on Speech and Natural Language (1991)

Work in computational linguistics has reached the point where the performance of many natural language processing systems is limited by a "lexical bottleneck". That is, such systems could handle much more text and produce much more impressive application results were it not for the fact that their lexicons are too small.
Interactive multimedia explanation for equipment maintenance and repair
Authors: Kathleen McKeown, Steven Feiner
Venue: Proceedings of the workshop on Speech and Natural Language (1990)

COMET (COordinated Multimedia Explanation Testbed) is an experimental system that generates interactive multimedia explanations of how to operate, maintain, and repair equipment. Our research stresses the dynamic generation of the content and form of all material presented, addressing issues in the generation of text and graphics, and in coordinating text and graphics in an integrated presentation.
Foundations for the study of software architecture
Authors: Dewayne E. Perry, Alexander L. Wolf
Venue: ACM SIGSOFT Software Engineering Notes (1992)

The purpose of this paper is to build the foundation for software architecture. We first develop an intuition for software architecture by appealing to several well-established architectural disciplines. On the basis of this intuition, we present a model of software architecture that consists of three components: elements, form, and rationale. Elements are either processing, data, or connecting elements. Form is defined in terms of the properties of, and the relationships among, the elements --- that is, the constraints on the elements. The rationale provides the underlying basis for the architecture in terms of the system constraints, which most often derive from the system requirements. We discuss the components of the model in the context of both architectures and architectural styles and present an extended example to illustrate some important architecture and style considerations. We conclude by presenting some of the benefits of our approach to software architecture, summarizing our contributions, and relating our approach to other current work.
Monomial orderings and Gröbner bases
Authors: Fritz Schwarz
Venue: ACM SIGSAM Bulletin (1991)

Let there be given a set of monomials in n variables and some order relations between them. The following fundamental problem of monomial ordering is considered. Is it possible to decide whether these ordering relations are consistent and if so to extend them to an admissible ordering for all monomials? The answer is given in terms of the algorithm MACOT which constructs a matrix of so called cotes which establishes the desired ordering relations. The main area of application of this algorithm, i.e. the construction of Gr ouml;bner bases for different orderings and of universal Gr ouml;bner bases is treated in the last section.
A class of prefetch schemes for on-chip data caches
Authors: Anujan Varma, Gunjan Sinha
Venue: ACM SIGARCH Computer Architecture News (1992)

We introduce and evaluate a class of prefetch schemes for on-chip data caches in high-performance RISC processors. These schemes are conservative, initiating a prefetch only when a sequential pattern of references have been observed. Performance results based on traces of five programs in the SPEC suite on an IBM RS/6000 show that these schemes result in a significant reduction in miss ratio without the large increase in memory traffic associated with earlier schemes.
Pattern matching in a digitized image
Authors: Gad M. Landau, Uzi Vishkin
Venue: Proceedings of the third annual ACM-SIAM symposium on Discrete algorithms (1992)

The continuous pattern matching problem is defined. Given are two pictures, each consisting of unicolor regions; one picture is called the scene and the other the pattern. The problem is to find all occurrences of the pattern in the scene. As a step towards efficient algorithmic handling of the continuous pattern matching problem by computers, where discretized representations are involved, we give several algorithms. Our strongest algorithmic result is for a one-dimensional version of the problem, where running time which is linear in the length of a digitized representation is achieved. The definitions of our problems are derived from a &ldquo;digitized-based&rdquo; approach to object recognition problems in computer vision, which is different from a common computer vision approach. The digitized based approach may lead towards further research within the discrete algorithms community on computer vision problems.
The interactive matrix chart
Authors: Shaun Marsh
Venue: ACM SIGCHI Bulletin (1992)

This paper presents a method for mapping a table of quantitative data into a unique graphical presentation, called an interactive matrix chart. Each chart consists of a grid containing graphical marks in each of the cells, and these marks may vary in color, size, shape and other characteristics.The chart may be manipulated through both a simplification and a query mechanism. Simplifying the interactive matrix chart involves rearranging rows and columns of the chart. Querying the interactive matrix chart involves redesigning the individual marks meant to represent the underlying data. By simplifying and querying the interactive matrix chart, different patterns of marks are rendered, and, therefore, different relationships between the data are revealed.
The DASH prototype: implementation and performance
Authors: Daniel Lenoski, James Laudon, Truman Joe, David Nakahira, Luis Stevens, Anoop Gupta, John Hennessy
Venue: Proceedings of the 19th annual international symposium on Computer architecture (1992)

The fundamental premise behind the DASH project is that it is feasible to build large-scale shared-memory multiprocessors with hardware cache coherence. While paper studies and software simulators are useful for understanding many high-level design trade-offs, prototypes are essential to ensure that no critical details are overlooked. A prototype provides convincing evidence of the feasibility of the design allows one to accurately estimate both the hardware and the complexity cost of various features, and provides a platform for studying real workloads. A 16-processor prototype of the DASH multiprocessor has been operational for the last six months. In this paper, the hardware overhead of directory-based cache coherence in the prototype is examined. We also discuss the performance of the system, and the speedups obtained by parallel applications running on the prototype. Using a sophisticated hardware performance monitor, we characterize the effectiveness of coherent caches and the relationship between an application's reference behavior and its speedup.
Comparison of hypercube, hypernet, and symmetric hypernet architectures
Authors: R. P. Kaushal, J. S. Bedi
Venue: ACM SIGARCH Computer Architecture News (1992)

Hypercube has been the most popular topology for developing multiprocessor supercomputers because of its connectivity, regularity, symmetry and algorithmic mapping properties. However, if a hypercube needs to be expanded at some future time, both hardware configuration and communication software of each node has to be altered because its node degree is not constant. Hwang and Ghosh proposed a new interconnection network called hypernet which has a constant node degree and is easily expandable. However, its components count increases unsymmetrically with the increase in size. We propose a new topology called symmetric hypernet which grows symmetrically with the increase in dimension and hierachical level. The nodes in the symmetric net are functionally and physically separated as IO nodes and computation nodes to avoid traffic congestion and message delays. The IO nodes are placed uniformly among the processing nodes. The system can be dynamically partitioned into subsystems, each of which may be dedicated to serve a user's request(s). The system analysis can be done with the help of analytical models to serve a user's request(s). The system analysis can be done with the help of analytical models to determine how different structures would affect system performance.
Performance issues in non-blocking synchronization on shared-memory multiprocessors
Authors: Juan Alemany, Edward W. Felten
Venue: Proceedings of the eleventh annual ACM symposium on Principles of distributed computing (1992)

This paper considers the implementation of non-blocking concurrent objects on shared-memory multiprocessors. Real multiprocessors have properties not present in theoretical models; these properties can be exploited to design non-blocking protocols that are more efficient in practice than those allowed by theoretical models. These new protocols rely on the operating system to take action when a thread of control is delayed during its non-blocking update. We illustrate the effectiveness of this approach by presenting two protocols that address factors hindering the performance of Herlihy's standard non-blocking protocol [Herlihy 90, Herlihy 91a]. These factors are: resources wasted by attempted non-blocking operations that fail, and the cost of data copying. We demonstrate the importance of these factors experimentally, and show how they can be reduced using protocols that rely on operating system support. To reduce the overhead of failing non-blocking operations, our first protocol maintains information about the utilization of the shared object; experiments show that this protocol performs better than the known alternatives. To reduce the cost of data copying, we introduce a second, optimistic protocol that avoids copying, except in the case when a thread of control is delayed during its attempted update.
Integrating perception, language-handling, learning and planning in the CHILDLIKE system
Authors: Ganesh Mani, Leonard Uhr
Venue: ACM SIGART Bulletin (1991)

In this paper, we highlight the importance of the integrated perceive-reason-act-learn loop, which appears to be central to intelligence, and describe a system that we are developing to capture this loop. As a first step, the system learns about simple objects, their qualities, and the words that name them and describe their parts and relations. The visual-linguistic associations formed act as a bias in acquiring further knowledge about actions, which in turn aids the system in satisfying its internal needs (e.g., hunger, thirst, sleep, curiosity). We briefly describe the components of the system and discuss some of the salient properties of the CHILDLIKE integrated architecture.
A Novel Discrete Relaxation Architecture
Authors: Jun Gu, Wei Wang
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1992)

The discrete relaxation algorithm (DRA) is a computational technique that enforces arc consistency (AC) in a constraint satisfaction problem (CSP). The original sequential AC-1 algorithm suffers from O(n/sup 3/m/sup 3/) time complexity, and even the optimal sequential AC-4 algorithm is O(n/sup 2/m/sup 2/) for an n-object and m-label DRA problem. Sample problem runs show that these algorithms are all too slow to meet the need for any useful, real-time CSP applications. A parallel DRA5 algorithm that reaches a lower bound of O(nm) (where the number of processors is polynomial in the problem size) is given. A fine-grained, massively parallel hardware computer architecture has been designed for the DRA5 algorithm. For practical problems, many orders of magnitude of efficiency improvement can be reached on such a hardware architecture.
Knowledge-based evaluation as design support for graphical user interfaces
Authors: Jonas Löwgren, Tommy Nordqvist
Venue: Proceedings of the SIGCHI conference on Human factors in computing systems (1992)

The motivation for our work is that even though user interface guidelines and style guides contain much useful knowledge, they are hard for user interface designers to use. We want to investigate ways of bringing the human factors knowledge closer to the design process, thus making it more accesible to designers. To this end, we present a knowledge-based tool, containing design knowledge drawn from general guideline documents and toolkit-specific style guides, capable of evaluating a user interface design produced in a UIMS. Our assessment shows that part of what the designers consider relevant design knowledge is related to the user's tasks and thus cannot be applied to the static design representation of the UIMS. The final section of the paper discusses ways of using this task-related knowledge.
Abstract data types and high-level synthesis
Authors: Gregory S. Whitcomb, A. Richard Newton
Venue: Proceedings of the 27th ACM/IEEE Design Automation Conference (1991)

Previous data abstraction efforts in software and hardware description have approached abstract data types from a specification and simulation standpoint. This paper addresses the use of abstract data types for high-level synthesis. Data types are extended to support don't care information and new synthesis steps are presented. Results from a number of realistic design examples indicate that the area and delay of logic implementations can be substantially reduced when data abstraction and appropriate synthesis procedures are incorporated into the high-level synthesis process.
Distributed Diagnosis Algorithms for Regular Interconnected Structures
Authors: Arun K. Somani, Vinod K. Agarwal
Venue: IEEE Transactions on Computers (1992)

A distributed diagnosis algorithm to locate faulty processing elements in large-scale regular interconnected structures based on the concepts of system-level diagnosis is developed. This algorithm can either operate in a systolic manner or may be executed on a supervisory processor to locate the faulty processors. The computational complexity of the algorithm is linear when run on a supervisory processor and constant when run in parallel systolic manner. The implementation complexity and diagnosis capability of the algorithm are also analyzed without restricting the fault set size. The probability of correct diagnosis is shown to be very high even in the presence of large fault sets.
A high speed mechanism for short branches
Authors: Bernard K. Gunther
Venue: ACM SIGARCH Computer Architecture News (1990)

A semi-absolute branch instruction supplies the low-order bits of the destination address, or an offset into a frame, while the high-order bits the destination address, or frame number, are derived from the current frame number. The branch mechanism proposed here compares a small number of the most significant bits of a current and destination frame offsets followed by a possible increment or decrement of the current frame number, allowing branches to be effected more rapidly, for a given hardware cost, than by adding an offset to the instruction pointer. The increment can be performed upon branching or prior to it in order to hide the latency of the increment operation. If, for example, the three most significant bits of the frame offsets are compared the overall branch range is reduced to 94% of the range of conventional relative branches. This technique over comes the branch range restriction that occurs when the instruction pointer points to near a frame boundary and the destination address is generated by a simple bit-field substitution.
Goats to sheep: can recognition rate be improved for poor Tangora speaker?
Authors: Catalina M. Denis
Venue: Proceedings of the workshop on Speech and Natural Language (1989)

This paper reports on a study of recognition performance for a group of new users during their first month of experience with the TANGORA system. TANGORA is a 20,000 word, speaker dependent, isolated-word system which transcribes speech input into text in real-time. Twelve users, six males and six females, participated in 21 sessions each, during which they read aloud unrelated sentences selected from a corpus of office correspondence. Their goal was to develop a speaking style which minimized TANGORA's recognition error. Hypotheses were generated about users' speech habits which may have lead to increased recognition error and suggestions were made to them on how to modify their speaking style accordingly. On average, recognition errors decreased by 33% from the first to the fourth week. Some characteristics of successful speakers have been identified.
Performance analysis of coherency control policies through lock retention
Authors: Asit Dan, Philip S. Yu
Venue: Proceedings of the 1992 ACM SIGMOD international conference on Management of data (1992)

Buffer coherency control can be achieved through retaining a lock (shared, exclusive, etc.) on each page in the buffer, even after the requesting transaction has committed. Depending upon the lock mode held for retention and the compatibility of lock modes specified, different retention policies can be devised. In addition to tracking the validity of the buffered data granules, additional capabilities can be provided such as deferred writes to support no-force policy on commit, (node) location identification of valid granules to support remote memory accesses, and shared/exclusive lock retention to reduce the number of global lock requests for concurrency control. However, these can have serious implications not only on the performance but also on the recovery complexity. In this paper, five different integrated coherency policies are considered. We classify these policies into three different categories according to their recovery requirements. A performance study based on analytic models is provided to understand the trade-offs on both maximum throughputs and response times of the policies with a similar level of recovery complexity and the performance gain achievable through increasing the level of recovery complexity.
Solutions Relating Static and Dynamic Machine Code Measurements
Authors: Jack W. Davidson, John R. Rabung, David B. Whalley
Venue: IEEE Transactions on Computers (1992)

In an effort to relate static measurements of machine code instructions and addressing modes to their dynamic counterparts, both types of measurements were made on nine different machines using a large and varied suite of programs. Using classical regression analysis techniques, the relationship between static architecture measurements and dynamic architecture measurements was explored. The statistical analysis showed that many static and dynamic measurements are strongly correlated and that it is possible to use the more easily obtained static measurements to predict dynamic usage of instructions and addressing modes. With few exceptions, the predictions are accurate for most architectural features.
Hierarchical blocking and data flow analysis for numerical linear algebra
Authors: Dingju Chen
Venue: Proceedings of the 1990 ACM/IEEE conference on Supercomputing (1990)

The optimization of BLAS2 and BLAS3 for linear algebra on computers with hierarchical memory systems is discussed. A new blocking strategy called hierarchical blocking and data flow analysis is proposed and its applications are given. Numerical results on IBM RISC System/6000 Model 530 are given.
Undergraduate software engineering laboratories: a progress report from two universities
Authors: James Kiper, Michael J. Lutz, Henry A. Etlinger
Venue: Proceedings of the twenty-third SIGCSE technical symposium on Computer science education (1992)

Recently, both Miami University of Ohio and the Rochester Institute of Technology received NSF grants to develop undergraduate software engineering laboratories. While the general goals of the labs are similar, specific hardware and software selections were driven by differing curricular emphases and educational environments at the two institutions. This paper presents the distinctive characteristics of each school's program, discusses the influence of these features on the selection process, and describes our experiences to date with the resulting labs. The goal is to provide useful information guidance to others considering such facilities.
Visual Knowledge Engineering
Authors: Marc Eisenstadt, John Domingue, Tim Rajan, Enrico Motta
Venue: IEEE Transactions on Software Engineering (1990)

The knowledge engineer is only weakly supported at three critical stages in the knowledge engineering life cycle: (1) knowledge acquisition during which problem conceptualization must largely be tackled with paper and pencil; (2) knowledge encoding, during which it is frequently necessary to be able to navigate across a variety of knowledge representation formalisms; and (3) large-scale debugging, in which the graphical rule traces cannot cope with enormous rule sets involving hundreds or thousands of rules. The research described attempts to provide just such support through complementary visual programming (VP) and program visualization (PV) techniques embedded in a fully implemented software environment called KEATS: the knowledge engineer's assistant. Several novel visual programming and program visualization techniques aimed at knowledge engineers have been developed, which include (1) a hypertext transcript analyzer from which conceptual models can be generated, (2) a direct graph manipulation sketchpad which allows the knowledge engineer to sketch out objects and relations (including control flow and rule dependencies) from which code can be generated, and (3) dependency viewers which allow the knowledge engineer to examine and manipulate temporal and logical rule dependencies at different levels of granularity. How these facilities are incorporated into KEATS and the key themes that emerge from this approach to visual knowledge engineering are discussed.