ppxscal/embedding_network huggingface dataset:
Online BIST for Embedded Systems
Authors: Hussain Al-Asaad, Brian T. Murray, John P. Hayes
Venue: IEEE Design Test (1998)

We survey online testing techniques in embedded systems and evaluate them based on the following parameters: error coverage, error latency, space redundancy, and time redundancy. We then discuss online BIST methods that provide full error coverage, bounded error latency, low space and time redundancy, and impose no redesign constraints on the circuit under test. Finally, we discuss a recently designed commercial microprocessor for critical applications that incorporate most of the methods considered.
Associative processing and processors
Authors: Anargyros Krikelis, Charles C. Weems
Venue: Computer (1994)

Associative memory concerns the concept that one idea may trigger the recall of a different but related idea. Traditional computers, however, rely upon a memory design that stores and retrieves data by its address rather than its content. In such a search, every accessed data word must travel individually between the processing unit and the memory. The simplicity of this retrieval-by-address approach has ensured its success, but has also produced some inherent disadvantages. One is the von Neumann bottleneck, where the memory-access path becomes the limiting factor for system performance. A related disadvantage is the inability to proportionally increase the size of a unit transfer between the memory and the processor as the size of the memory scales up. Associative memory, in contrast, provides a naturally parallel and scalable form of data retrieval for both structured data (e.g. sets, arrays, tables, trees and graphs) and unstructured data (raw text and digitized signals). An associative memory can be easily extended to process the retrieved data in place, thus becoming an associative processor. This extension is merely the capability for writing a value in parallel into selected cells.
Scaling Access to Heterogeneous Data Sources with DISCO
Authors: Anthony Tomasic, Louiqa Raschid, Patrick Valduriez
Venue: IEEE Transactions on Knowledge and Data Engineering (1998)

Accessing many data sources aggravates problems for users of heterogeneous distributed databases. Database administrators must deal with fragile mediators, that is, mediators with schemas and views that must be significantly changed to incorporate a new data source. When implementing translators of queries from mediators to data sources, database implementors must deal with data sources that do not support all the functionality required by mediators. Application programmers must deal with graceless failures for unavailable data sources. Queries simply return failure and no further information when data sources are unavailable for query processing. The Distributed Information Search COmponent (DISCO) addresses these problems. Data modeling techniques manage the connections to data sources, and sources can be added transparently to the users and applications. The interface between mediators and data sources flexibly handles different query languages and different data source functionality. Query rewriting and optimization techniques rewrite queries so they are efficiently evaluated by sources. Query processing and evaluation semantics are developed to process queries over unavailable data sources. In this article, we describe 1) the distributed mediator architecture of DISCO; 2) the data model and its modeling of data source connections; 3) the interface to underlying data sources and the query rewriting process; and 4) query processing semantics. We describe several advantages of our system.
A 4 GHz &Delta;&Sigma; Fractional-N Frequency Synthesizer
Authors: Rami Ahola, Kari Halonen
Venue: Analog Integrated Circuits and Signal Processing (2003)

A 4 GHz &Delta;&Sigma; fractional-N frequency synthesizer for wireless communications applications is implemented in a 0.35 &mu;m BiCMOS process. The synthesizer achieves a close-in phase noise of &minus;66 dBc/Hz. The key building blocks are an ECL multiple-modulus prescaler employing the phase-switching architecture to minimize the power dissipation, a digital third-order MASH &Delta;&Sigma;-modulator that controls the modulus of the prescaler, a very linear phase detector that enables the synthesizer to achieve a low close-in phase noise, and a chargepump providing a constant output current over a large output voltage range. The power dissipation of the synthesizer chip is 27.7 mW from a 2.7 V supply.
Certifying Compilation and Run-Time Code Generation
Authors: Luke Hornof, Trevor Jim
Venue: Higher-Order and Symbolic Computation (1999)

A certifying compiler takes a source language program and produces object code, as well as a &ldquo;certificate&rdquo; that can be used to verify that the object code satisfies desirable properties, such as type safety and memory safety. Certifying compilation helps to increase both compiler robustness and program safety. Compiler robustness is improved since some compiler errors can be caught by checking the object code against the certificate immediately after compilation. Program safety is improved because the object code and certificate alone are sufficient to establish safety: even if the object code and certificate are produced on an unknown machine by an unknown compiler and sent over an untrusted network, safe execution is guaranteed as long as the code and certificate pass the verifier.Existing work in certifying compilation has addressed statically generated code. In this paper, we extend this to code generated at run time. Our goal is to combine certifying compilation with run-time code generation to produce programs that are both fast and verifiably safe. To achieve this goal, we present two new languages with explicit run-time code generation constructs: Cyclone, a type safe dialect of C, and TAL/T, a type safe assembly language. We have designed and implemented a system that translates a safe C program into Cyclone, which is then compiled to TAL/T, and finally assembled into executable object code. This paper focuses on our overall approach and the front end of our system&semi; details about TAL/T will appear in a subsequent paper.
Object-Oriented Databases: Definition and Research Directions
Authors: W. Kim
Venue: IEEE Transactions on Knowledge and Data Engineering (1990)

An object-oriented database is defined and justified on the basis of a small set of central object-oriented concepts. A number of common misconceptions about object-oriented databases are discussed. The results of relevant recent research in object-oriented databases are outlined. Directions for future research in object-oriented databases are provided.
Corrigendum to "Synthetic Traces for Trace-Driven Simulation of Cache Memories"
Authors: D. Thiebaut, J. Wolf, H. Stone
Venue: IEEE Transactions on Computers (1993)

Three errors appearing in the above-tilted paper by D. Thiebaut, J. Wolf, and H. Stone are corrected. They were introduced during the revision process and do not affect the results.
Computational Surface Flattening: A Voxel-Based Approach
Authors: R. Grossmann, N. Kiryati, R. Kimmel
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (2002)

A voxel-based method for flattening a surface in 3D space into 2D while best preserving distances is presented. Triangulation or polyhedral approximation of the voxel data are not required. The problem is divided into two main parts: Voxel-based calculation of the minimal geodesic distances between points on the surface and finding a configuration of points in 2D that has Euclidean distances as close as possible to these distances. The method suggested combines an efficient voxel-based hybrid distance estimation method, that takes the continuity of the underlying surface into account, with classical multidimensional scaling (MDS) for finding the 2D point configuration. The proposed algorithm is efficient, simple, and can be applied to surfaces that are not functions. Experimental results are shown.
Software Products
Venue: IEEE Software (1990)

No abstract available The ACM Portal is published by the Association for Computing Machinery. Copyright © 2010 ACM, Inc. Terms of Usage Privacy Policy Code of Ethics Contact Us Useful downloads: Adobe Acrobat QuickTime Windows Media Player Real Player
Trapezoid Self-Scheduling: A Practical Scheduling Scheme for Parallel Compilers
Authors: T. H. Tzen, L. M. Ni
Venue: IEEE Transactions on Parallel and Distributed Systems (1993)

A practical processor self-scheduling scheme, trapezoid self-scheduling, is proposed for arbitrary parallel nested loops in shared-memory multiprocessors. Generally, loops are the richest source of parallelism in parallel programs. To dynamically allocate loop iterations to processors, one may achieve load balancing among processors at the expense of run-time scheduling overhead. By linearly decreasing the chunk size at run time, the best tradeoff between the scheduling overhead and balanced workload can be obtained in the proposed trapezoid self-scheduling approach. Due to its simplicity and flexibility, this approach can be efficiently implemented in any parallel compiler. The small and predictable number of chores also allow efficient management of memory in a static fashion. The experiments conducted in a 96-node Butterfly GP-1000 clearly show the advantage of the trapezoid self-scheduling over other well-known self-scheduling approaches.
Maximum Consistency of Incomplete Datavia Non-Invasive Imputation
Authors: Günther Gediga, Ivo Düntsch
Venue: Artificial Intelligence Review (2003)

We present an algorithm to impute missing values from given data alone, and analyse its performance. The proposed procedure is based on non-numeric rule based data analysis, and aims to maximise consistency of imputation from known values. In contrast to the prevailing statistical imputation algorithms, it does not make representational assumptions or presupposes other model constraints. Therefore, it is suitable for a wide variety of data &ndash; sets, and can be used as a pre-processing step before resorting to harder numerical methods.
Programming Three Parallel Computers
Authors: Marta Kallstrom, Shreekant S. Thakkar
Venue: IEEE Software (1988)

Three commercial systems are considered from a programmer's point of view. The three are the Intel iPSC, a network of Inmos transputers, and the Sequent Balance. The differences in overhead are examined by implementing a solution to the traveling-salesman problem on all three. The evaluation focuses on three major issues in parallel programming: (1) how execution is divided among processing elements and how it is controlled; (2) how data are shared; and (3) how events are synchronized. The experiences of the authors are presented and some specific as well as general conclusions are drawn.
A Bayesian model selection method with applications
Authors: Xin-Yuan Song, Sik-Yum Lee
Venue: Computational Statistics Data Analysis (2002)

In this paper, we consider Bayesian model selection using the well-known Bayes factor. A method on the basis of path sampling for computing the ratio of two normalizing constants involved in the Bayes factor is proposed. The key idea is to construct a continuous path to link up the competing models, then the Bayes factor can be estimated efficiently by means of grids in [0,1] and observations simulated from the posterior distribution of the parameters. This method is applied to non-nested regression models, mixture models with an unknown number of components, and a general latent variable model with mixed continuous and polytomous variables. Analyses of some real data sets are presented to illustrate the efficiency and flexibility of the method.
The M/sup 3/ Multiprocessor Laboratory
Authors: H. Burkhart, R. Eigenmann, H. Kindlimann, M. Moser, H. Scholian
Venue: IEEE Transactions on Parallel and Distributed Systems (1993)

An integrated programming environment for the M/sup 3/ multiprocessor is discussed.Three tools support the software development cycle of a parallel program, including theprogramming, configuration, and debugging/performance measurement phases.Programmer support for performance analysis has been a primary motivation for thesystem. The sources of performance loss are identified and the ways in which thisinformation is gathered and analyzed are described. As a case study, a fast maze routeralgorithm is used to show the functionality of the different tools. The M/sup 3/environment is compared with other state-of-the-art projects.
Interactive Parallel Programming using the ParaScope Editor
Authors: K. Kennedy, K. S. McKinley, C. W. Tseng
Venue: IEEE Transactions on Parallel and Distributed Systems (1991)

The ParaScope Editor, an intelligent interactive editor for parallel Fortran programs, which is the centerpiece of the ParaScope project, an integrated collection of tools to help scientific programmers implement correct and efficient parallel programs, is discussed. ParaScope Editor reveals to users potential hazards of a proposed parallelization in a program. It provides a variety of powerful interactive program transformations that have been shown useful in converting programs to parallel form. ParaScope Editor supports general user editing through a hybrid text and structure editing facility that incrementally analyzes the modified program for potential hazards. It is shown that ParaScope Editor supports an exploratory programming style in which users get immediate feedback on their various strategies for parallelization.
A Maximum Entropy Approach to Nonmonotonic Reasoning
Authors: M. Goldzsmidt, P. Morris, J. Pearl
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1993)

An approach to nonmonotonic reasoning that combines the principle of infinitesimal probabilities with that of maximum entropy, thus extending the inferential power of the probabilistic interpretation of defaults, is proposed. A precise formalization of the consequences entailed by a conditional knowledge base is provided, the computational machinery necessary for drawing these consequences is developed, and the behavior of the maximum entropy approach is compared to related work in default reasoning. The resulting formalism offers a compromise between two extremes: the cautious approach based on the conditional interpretations of defaults and the bold approach based on minimizing abnormalities.
A toolkit for visualizing biomedical data sets
Authors: Burkhard C. Wünsche
Venue: Proceedings of the 1st international conference on Computer graphics and interactive techniques in Australasia and South East Asia (2003)

Medical data sets now comprise a diverse range of measurements such as tissue densities, sensitivity to magnetization, blood flow velocity, and material strain. The size and complexity of medical data sets makes it increasingly difficult to understand, compare, analyze and communicate the data. Visualization is an attempt to simplify these tasks according to the motto "An image says more than a thousand words". Representing complex material properties, such as strain, as a single image improves the perception of features and pattern in the data, enables the recognition of relationship between different measures and facilitates the navigation through and interaction with complex and disparate sets of data.This paper introduces a toolkit developed for exploring complex biomedical data sets. The contributions of this paper are threefold: we suggest a modular design which facilitates the comparison and exploration of multiple data sets and visualization. We introduce a novel field data structure which allows interactive creation of new fields and we present boolean filters as a universal visualization tool.
A 3D robot simulation for education
Authors: Tim L. Dunn, Aster Wardhani
Venue: Proceedings of the 1st international conference on Computer graphics and interactive techniques in Australasia and South East Asia (2003)

This paper describes the work-in-progress of creating an artificial 3D environment and robot, suitable for educational simulation. A visual 3D vehicle robot, equipped with a monocular camera navigates in a physics based 3D environment, with some artificial intelligence capabilities. Students can interact with the robot, add new objects and set the robot various tasks. This multimedia tool is designed for students with very little experience with robotics, and aims at giving students unlimited access to a relatively sophisticated robotic system, incorporating artificial intelligence, with an extremely low cost compared to using real robot systems. Our current version of the simulation software has been designed to perform three main tasks, play soccer, avoid object, and wander. The simulation is being designed to closely resemble its real-world counterparts, and we hope, will ultimately become a powerful research and development tool.
Trends in Low-Cost, High-Performance Substrate Technology
Authors: David H. Carey
Venue: IEEE Micro (1993)

The trends in high density interconnection (HDI) multichip module (MCM) techniques that have the potential to reduce interconnection cost and production time are described. The implementation in laminated dielectric (MCM-L) technology of a workstation processor core illustrates current substrate technology capabilities. The design, routing, layout and thermal management of the processor core are described. Thin-film deposited dielectric (MCM-D) technology is discussed as a cost-effective method for future interconnection applications.
Axisymmetric wake and jet solutions in decelerating streams
Authors: J. Barker, G. Wilks
Venue: Zeitschrift f&uuml;r Angewandte Mathematik und Physik (ZAMP) (2002)

New solutions of the axisymmetric boundary-layer equations are presented. The solutions are associated with free shear layers within non-uniform streams. Both jet- and wake-like velocity profiles have been found. In the appropriate limit it is demonstrated that the jet-like profiles asymptote to the round jet solution in a quiescent ambient.
Top contacts for vertical double-gate MOSFETs
Authors: J. Moers, St. Trellenkamp, M. Goryll, M. Marso, A. van der Hart, S. Hogg, S. Mantl, P. Kordos, H. Lüth
Venue: Microelectronic Engineering (2002)

As scaling of electronic devices goes on, the issue of short channel effects draws growing attention. Double-gate MOSFETs are known to reduce short channel behaviour effectively [Proc. IEEE 85 (1997) 486] and therefore have gained increasing attention for future CMOS application. Here a vertical layout is discussed, where the current flow is perpendicular to the surface. In an already realised layout [Proc. ESSDERC (2001) 191] the device performance is ruled by the resistance of the top contact. In a revised layout the top contact is implemented directly on top of the transistor. Here the layout and the technology steps to obtain this structure are discussed.
D-optimal designs for sensor and actuator locations
Authors: Rex K. Kincaid, Sharon L. Padula
Venue: Computers and Operations Research (2002)

Active control of noise and vibration is now possible in automobiles, aircraft, and many other devices. Where to place actuators, to control noise and vibration, and sensors, to measure the performance of the actuators, is a central question. Given a truss structure, we seek the k most effective locations to control and/or sense vibrations. A discrete D-optimal design has been proposed as a solution to this location problem. We develop a simple static tabu search and test its performance on an 80 node truss structure built at NASA-Langley Research Center. We show that our tabu search approach dominates the traditional approaches to finding D-optimal designs.
The Raw Microprocessor: A Computational Fabric for Software Circuits and General-Purpose Programs
Authors: Michael Bedford Taylor, Jason Kim, Jason Miller, David Wentzlaff, Fae Ghodrat, Ben Greenwald, Henry Hoffman, Paul Johnson, Jae-Wook Lee, Walter Lee, Albert Ma, Arvind Saraf, Mark Seneski, Nathan Shnidman, Volker Strumpen, Matt Frank, Saman Amarasinghe, Anant Agarwal
Venue: IEEE Micro (2002)

Wire delay is emerging as the natural limiter to microprocessor scalability. A new architectural approach could solve this problem, as well as deliver unprecedented performance, energy efficiency, and cost effectiveness.
Efficient Query Processing for a Subset of Linear Recursive Binary Rules
Authors: K. -C. Guh, C. Yu
Venue: IEEE Transactions on Knowledge and Data Engineering (1994)

We study the complexity of processing a class of rules called simple binary rule sets. The data referenced by the rules are stored in secondary memory. A necessary and sufficient condition that a simple binary rule set can be processed in a single pass of a file containing the base relations is given. Because not all simple binary rule sets can be processed in a single pass, a necessary and sufficient condition that a simple binary rule set can be processed by a constant number of passes is also given.
Genetic Search: Analysis Using Fitness Moments
Authors: M. Srinivas, L. m. Patnaik
Venue: IEEE Transactions on Knowledge and Data Engineering (1996)

Genetic Algorithms are efficient and robust search methods that are being employed in a plethora of applications with extremely large search spaces. The directed search mechanism employed in Genetic Algorithms performs a simultaneous and balanced, exploration of new regions in the search space and exploitation of already discovered regions.This paper introduces the notion of fitness moments for analyzing the working of Genetic Algorithms (GAs). We show that the fitness moments in any generation may be predicted from those of the initial population. Since a knowledge of the fitness moments allows us to estimate the fitness distribution of strings, this approach provides for a method of characterizing the dynamics of GAs. In particular the average fitness and fitness variance of the population in any generation may be predicted.We introduce the technique of fitness-based disruption of solutions for improving the performance of GAs. Using fitness moments, we demonstrate the advantages of using fitness-based disruption. We also present experimental results comparing the performance of a standard GA and GAs (CDGA and AGA) that incorporate the principle of fitness-based disruption. The experimental evidence clearly demonstrates the power of fitness based disruption.
A High-Performance Memory Allocator for Object-Oriented Systems
Authors: J. Morris Chang, Edward F. Gehringer
Venue: IEEE Transactions on Computers (1996)

Object-oriented programming languages tend to allocate and deallocate blocks of memory very frequently. The growing popularity of these languages increases the importance of high-performance memory allocation. For speed and simplicity in memory allocation, the buddy system has been the method of choice for nearly three decades. A software realization incurs the overhead of internal fragmentation and of memory traffic due to splitting and coalescing memory blocks. This paper presents a simple hardware design for buddy-system allocation that takes advantage of the speed of a pure combinational-logic implementation. Two binary trees formed by anding and oring propagate information about the allocation status of blocks and subblocks. They implement a nonbacktracking search for the address of the first free block that is large enough to satisfy a request.Although the buddy system may allocate a block that is much larger than the requested size, the logic that finds a free block can be augmented by a "bit-flipper" to relinquish the unused portion at the end of the block. This effectively eliminates internal fragmentation. Simulation results show that the buddy system modified in this way uses less memory in most, though not all, programs than the unmodified buddy. Hence, the hardware buddy-system allocator is faster and uses memory more efficiently than the standard software approach.