ppxscal/embedding_network huggingface dataset:
System-level simulation of a next generation, multi-sensor concurrent signal processor
Authors: James F. Engler
Venue: Proceedings of the 21st annual symposium on Simulation (1988)

A new generation of processors is now emerging which addresses the modular processing requirements for a wide range of multispectrum applications envisioned for the late-20th/early-21st century. Due to the complexity of interaction among software modules and hardware devices simulation techniques are required to verify that specific configurations support application requirements. This paper demonstrates how simulation results can provide useful information for validation objectives. For this study, a system-level architectural model of one such processor was written in a conventional programming language oriented toward simulation of computer environments.
A dynamic span storing method for hidden surface removal
Authors: J. Zhang
Venue: Proceedings of the 17th conference on ACM Annual Computer Science Conference (1989)

A dynamic span storing method is presented to reduce the large space requirement of the conventional z-buffer algorithm for hidden surface removal, but retain the simplicity to calculate spans of polygons. The method is also applied to the conventional scan-line algorithm using span coherence, resulting in a new scan-line algorithm having a much simpler control in span manipulation. A new polygon filling scheme is also presented for span generation, which handles singularities properly in all cases.
Transaction management in an object-oriented database system
Authors: Jorge F. Garza, Won Kim
Venue: ACM SIGMOD Record (1988)

In this paper, we describe transaction management in ORION, an object-oriented database system. The application environments for which ORION is intended led us to implement the notions of sessions of transactions, and hypothetical transactions (transactions which always abort). The object-oriented data model which ORION implements complicates locking requirements. ORION supports a concurrency control mechanism based on extensions to the current theory of locking, and a transaction recovery mechanism based on conventional logging.
IDS 5000: An integrated diagnostic system for VLSI
Authors: Stefano Concina, Neil Richardson
Venue: Microelectronic Engineering (1988)

This paper describes the implementation of a mouse and window-driven Electron-Beam prober, intended for use by IC designers for debugging VLSI circuits. A worksation enables on-line access to the schematic, physical layout and test data, which is displayed in a format with which the designer is familiar so that little training is necessary to operate the system.
FCP: a summary of performance results
Authors: S. Taylor, R. Shapiro
Venue: Proceedings of the third conference on Hypercube concurrent computers and applications - Volume 2 (1989)

Flat Concurrent Prolog is a simple concurrent programming language which has been used for a variety of non-trivial applications. A compiler based parallel implementation has been completed which operates on an Intel Hypercube. This paper presents a brief summary of performance data from a recent study of the implementation. Three categories of program were studied: parallel applications, uniprocessor benchmarks and communication stereotypes. The latter programs are abstractions of common parallel programming techniques and serve to quantify the cost of communication in the language.
Founding crytpography on oblivious transfer
Authors: Joe Kilian
Venue: Proceedings of the twentieth annual ACM symposium on Theory of computing (1988)

Suppose your netmail is being erratically censored by Captain Yossarian. Whenever you send a message, he censors each bit of the message with probability 1/2, replacing each censored bit by some reserved character. Well versed in such concepts as redundancy, this is no real problem to you. The question is, can it actually be turned around and used to your advantage? We answer this question strongly in the affirmative. We show that this protocol, more commonly known as oblivious transfer, can be used to simulate a more sophisticated protocol, known as oblivious circuit evaluation([Y]). We also show that with such a communication channel, one can have completely noninteractive zero-knowledge proofs of statements in NP. These results do not use any complexity-theoretic assumptions. We can show that they have applications to a variety of models in which oblivious transfer can be done.
A modular technique for the design of efficient distributed leader finding algorithms
Authors: E. Korach, S. Kutten
Venue: ACM Transactions on Programming Languages and Systems (TOPLAS) (1990)

A general, modular technique for designing efficient leader finding algorithms in distributed, asynchronous networks is developed. This technique reduces the problem of efficient leader finding to a simpler problem of efficient serial traversing of the corresponding network. The message complexity of the resulting leader finding algorithms is bounded by [f(n) + n)(log2k + 1) (or (f(m) + n)(log2k + 1)], where n is the number of nodes in the network [m is the number of edges in the network], k is the number of nodes that start the algorithm, and f (n) [f(m)] is the message complexity of traversing the nodes [edges] of the network. The time complexity of these algorithms may be as large as their message complexity. This technique does not require that the FIFO discipline is obeyed by the links. The local memory needed for each node, besides the memory needed for the traversal algorithm, is logarithmic in the maximal identity of a node in the network. This result achieves in a unified way the best known upper bounds on the message complexity of leader finding algorithms for circular, complete, and general networks. It is also shown to be applicable to other classes of networks, and in some cases the message complexity of the resulting algorithms is better by a constant factor than that of previously known algorithms.
Photoemission sampling technique for high-speed integrated-circuit testing
Authors: H. Beha, H. Seitz, A. Blacha, R. Clauberg
Venue: Microelectronic Engineering (1988)

After a short review of the basic principles of time-resolved photoemission and its capabilities as a method for contactless electrical testing of integrated circuits, this paper reports on the progress made toward meeting the requirements for integrated-circuit (IC) testing and diagnostic equipment. The goals of IC testing are to provide high time and voltage resolutions with short testing time, and simultaneously high spatial resolution independent of the circuit technology (Si, GaAs). Here, the emphasis is on the time and voltage resolutions and short testing time. In the photoemission process, these parameters are independent of the spatial resolution in the regime of interest. The investigation is carried out with a pulsed-laser system generating picosecond pulses in the UV range. The measurements presented were performed on photoconductive switches. This allows testing the time resolution of the method by ultra-fast signals, and generating the electric transients to be sampled by the same laser source as the sampling pulse, guaranteeing almost jitter-free operation. The results clearly demonstrate that photoemission sampling is capable of contactless diagnostics and testing of very high-speed circuits with a high-voltage resolution and short testing time.
A benchmark package for sparse matrix computations
Authors: Y. Saad, H. A. G. Wijshoff
Venue: Proceedings of the 2nd international conference on Supercomputing (1988)

We examine the problem of evaluating performance of supercomputer architectures on sparse (matrix) computations and lay out the details of a benchmark package for this problem. Whereas there already exists a number of benchmark packages for scientific computations, such as the Livermore Loops, the Linpack benchmark and the Los Alamos benchmark, none of these deals with the specific nature of sparse computations. Sparse matrix techniques are characterized by the relatively small number of operations per data element and the irregularity of the computation. Both facts may significantly increase the overhead time due to memory traffic. For this reason, the performance evaluation of sparse computations should not only take into account the CPU performance but also the degradation of performance caused by high memory traffic. Furthermore, sparse matrix techniques comprise a variety of different types of basic computations. Taking these considerations into account we propose a benchmark package that consists of several independent modules, each of which has a distinct role.
Multiresolution Feature Extraction and Selection for Texture Segmentation
Authors: M. Unser, M. Eden
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1989)

An approach is described for unsupervised segmentation of textured images. Local texture properties are extracted using local linear transforms that have been optimized for maximal texture discrimination. Local statistics (texture energy measures) are estimated at the output of an equivalent filter bank by means of a nonlinear transformation (absolute value) followed by an iterative Gaussian smoothing algorithm. This procedure generates a multiresolution sequence of feature planes with a half-octave scale progression. A feature reduction technique is then applied to the data and is determined by simultaneously diagonalizing scatter matrices evaluated at two different spatial resolutions. This approach provides a good approximation of R.A. Fisher's (1950) multiple linear discriminants and has the advantage of requiring no a priori knowledge. This feature reduction methods appears to be an improvement on the commonly used Karhunen-Loeve transform and allows efficient texture segmentation based on simple thresholding.
Validating the TAME resource data model
Authors: D. R. Jeffery, V. R. Basili
Venue: Proceedings of the 10th international conference on Software engineering (1988)

This paper presents a conceptual model of software development resource data and validates the model by reference to the published literature on necessary resource data for development support environments. The conceptual model presented here was developed using a top-down strategy. A resource data model is a prerequisite to the development of integrated project support environments which aim to assist in the processes of resource estimation, evaluation and control. The model proposed is a four dimensional view of resources which can be used for resource estimation, utilization, and review. The model is validated by reference to three publications on resource databases, and the implications of the model arising out of these comparisons is discussed.
IGOR: a system for program debugging via reversible execution
Authors: Stuart I. Feldman, Channing B. Brown
Venue: ACM SIGPLAN Notices (1989)

Typical debugging tools are insufficiently powerful to find the most difficult types of program misbehaviors. We have implemented a prototype of a new debugging system, IGOR, which provides a great deal more useful information and offers new abilities that are quite promising. The system runs fast enough to be quite useful while providing many features that are usually available only in an interpreted environment. We describe here some improved facilities (reverse execution, selective searching of execution history, substitution of data and executable parts of the programs) that are needed for serious debugging and are not found in traditional single-thread debugging tools. With a little help from the operating system, we provide these capabilities at reasonable cost without modifying the executable code and running fairly close to full speed. The prototype runs under the DUNE distributed operating system. The current system only supports debugging of single-thread programs. The paper describes planned extensions to make use of extra processors to speed the system and for applying the technique to multi-thread and time dependent executions.
Scheduling time-critical instructions on RISC machines
Authors: Krishna Palem, Barbara Simons
Venue: Proceedings of the 17th ACM SIGPLAN-SIGACT symposium on Principles of programming languages (1989)

An instruction or a set of instructions can be considered time critical if their execution is required to free up a resource. Time critical instructions might be used to make shared resources such as registers more quickly available for reuse; or they might be used for real time computations, portions of which are critical for the operation of some piece of equipment. In this paper we present a polynomial time algorithm for optimally scheduling instructions with or without time critical constraints on RISC machines such as the IBM 801, the Berkeley RISC machine, and the HP Precision Architecture. We also show that in the absence of time critical constraints, the greedy algorithm always produces a schedule for a target machine with multiple identical pipelines that has a length less than twice that of an optimal schedule. The behavior of the greedy algorithm is of interest because, as we show, the instruction scheduling problem becomes NP-hard for arbitrary length pipelines, even when the basic block of code being input consists of only several independent streams of straight-line code, and there are no time-critical constraints. Finally, we present the first correct proofs that the problem becomes NP-hard even for small pipelines, no time-critical constraints, and input of several independent streams of straight-line code if there is only a single register or if there is a bus constraint.
The role of Ada in contemporary interface technology
Authors: S. Boyd
Venue: ACM SIGAda Ada Letters (1989)

This report addresses certain issues relevant to Ada interface technology, and identifies technical and organizational barriers to Ada's effective use as an interface medium. The report provides examples from the SQL Ada area, and the proposed POSIX Ada standard, and presents the argument that the principles which motivate good software design must be applied in the development of workable interface standards.
I didn't even know it was user services
Authors: Marlene R. Pratto, Judy H. Martin
Venue: Proceedings of the 16th annual ACM SIGUCCS Conference on User Services (1988)

We decided to write this paper in the third person since we are merging two co-workers' views of the evolution of User Services.
Electrical debugging of synchronous MOS VLSI circuits exploiting analysis of the intended logic behaviour
Authors: I. Bolsens, W. De Rammelaere, L. Claesen, H. De Man
Venue: Proceedings of the 26th ACM/IEEE Design Automation Conference (1989)

This paper discusses the kernel implementation issues of a new and more formal approach to electrical verification. Rule based analysis of the transistor network is applied to derive the signal flow direction and to identify control and state nodes. Symbolic analysis of Boolean expressions, capturing all aspects of switch level networks, allows to take into account the logical structure of the network and its environment during verification and guarantees more relevant error reports. The application of the proposed strategy on real life examples, demonstrates its usefulness and allows for a realistic evaluation of the tool.
Multi-prover interactive proofs: how to remove intractability assumptions
Authors: Michael Ben-Or, Shafi Goldwasser, Joe Kilian, Avi Wigderson
Venue: Proceedings of the twentieth annual ACM symposium on Theory of computing (1988)

Quite complex cryptographic machinery has been developed based on the assumption that one-way functions exist, yet we know of only a few possible such candidates. It is important at this time to find alternative foundations to the design of secure cryptography. We introduce a new model of generalized interactive proofs as a step in this direction. We prove that all NP languages have perfect zero-knowledge proof-systems in this model, without making any intractability assumptions. The generalized interactive-proof model consists of two computationally unbounded and untrusted provers, rather than one, who jointly agree on a strategy to convince the verifier of the truth of an assertion and then engage in a polynomial number of message exchanges with the verifier in their attempt to do so. To believe the validity of the assertion, the verifier must make sure that the two provers can not communicate with each other during the course of the proof process. Thus, the complexity assumptions made in previous work, have been traded for a physical separation between the two provers. We call this new model the multi-prover interactive-proof model, and examine its properties and applicability to cryptography.
MAC-CUBE, the Macintosh-based hypercube
Authors: A. Ho, G. C. Fox, D. W. Walker, M. Breaden, S. Chen, A. Knutson, S. Kuwamoto, T. Cole
Venue: Proceedings of the third conference on Hypercube concurrent computers and applications: Architecture, software, computer systems, and general issues - Volume 1 (1988)

The MAC-CUBE is a Macintosh-based hypercube. It uses AppleTalk hardware and software as the medium for the nodal connections. At the physical level AppleTalk has a bus topology. Hypercube connectivity is emulated on the AppleTalk local area network while the hypercube communication protocol is integrated in the AppleTalk software. Available for MAC-CUBE is the Crystalline Operating System III (CrOS III.) MAC-CUBE provides a programming environment similar to any other hypercube systems running CrOS III. It allows inexpensive hands-on experience with a concurrent machine. Data can be displayed on graphics monitor and/or stored locally at each node. In addition to the low cost, these capabilities of the Mac-Cube makes it an indispensable instructional and development tool for parallel processing. Some application programs which are taken from the book Solving Problems on Concurrent Processors [Fox 88] have been implemented with graphics enhancement on Mac-Cube. The applications are solving the Mandelbrot set in the complex plane, and solving a 2-dimensional Laplace equation using finite difference.
Perfect Latin squares and parallel array access
Authors: K. Kim, V. K. Prasanna-Kumar
Venue: ACM SIGARCH Computer Architecture News (1989)

A new nonlinear skewing scheme is proposed for parallel array access. We introduce a new Latin square(perfect Latin square) which has several properties useful for parallel array access. A sufficient condition for the existence of perfect Latin squares and a simple construction method for perfect Latin squares are presented. The resulting skewing scheme provides conflict free access to various subsets of an N x N array using N memory modules. When the number of memory modules is an even power of two, address generation is performed in constant time using a simple circuit. This scheme is the first memory scheme that achieves constant time access to rows, columns, diagonals, and N1/2 x N1/2 subarrays of an N x N array using the minimum number of memory modules.
On mechanical quantifier elimination for elementary algebra and geometry
Authors: Dennis S. Arnon, Maurice Mignotte
Venue: Journal of Symbolic Computation (1988)

We give solutions to two problems of elementary algebra and geometry: (1) find conditlons on real numbers p, q, and r; so that the polynomial function f(x) = x^4 + px^2 + q x+ r is nonnegative for all real x and (2) find conditions on real numbers a, b, and c so that the ellipse (x-c)^2q^2+y^2b^2-1=0 lies inside the unit circle y^2 + x^2 - 1 = O. Our solutions are obtained by following the basic outline of the method of quantifier elimination by cylindrical algebraic decomposition (Collins, 1975), but we have developed, and have been considerably aided by, modified vcrsions of certain of its steps. We have found three equally simple but not obviously equivalent solutions for the first problem, illustrating the difficulty of obtaining unique ''simplest'' solutions to quantifier eliminetion problems of elementary algebra and geometry.
On the construction of surfaces interpolating curves. I. A method for handling nonconstant parameter curves
Authors: David R. Ferguson, Thomas A. Grandine
Venue: ACM Transactions on Graphics (TOG) (1990)

In industrial design, the tool of choice for constructing surfaces that interpolate curves is the Boolean sum surface technique. However, if curves do not lie on constant parameter lines, reparametrizations will be needed, and this may introduce derivative discontinuities. A new technique which shows promise in overcoming this problem is described here. The method is based on describing the interpolation problem directly as a system of linear equations rather than as a curve-blending problem. The resulting system of equations is usually underdetermined and can be solved using numerical linear algebra methods without the a priori determination of certain parameters. The &ldquo;free&rdquo; parameters can be used to control the shape of the resulting surface. Two examples of the procedure are given.
Requiring CS1 students to write requirements specifications: a rationale, implementation suggestions, and a case study
Authors: Dale A. Brown
Venue: ACM SIGCSE Bulletin (1988)

This paper offers arguments supporting the concept of requiring written requirements specifications for all programming assignments in the first Computer Science course. The term &ldquo;requirements specifications&rdquo; is used here to refer to a description of the functional interaction of a single computer program with its environment and the non-functional constraints placed on that interaction. The principle thrust of the arguments is that students are best served if they are introduced to program design only as an activity which naturally follows requirements specification. This concept must be reinforced in all classroom examples and by practical student exercises. By requiring the students to create requirements specifications, the instructor encourages them to view the software development effort, from the beginning, as the analysis and solution of a problem rather than as the generation of a computer program. They are similarly encouraged to realize that the valuable end product of the effort is not just a program, but a thorough description of the problem and solution. Guidelines for incorporating the concept into existing CS1 courses are given. They are reinforced by a description of how this has been done in a specific course.
Maintaining the spirit of excitement in growing companies
Authors: A.-M. Garden
Venue: ACM SIGCPR Computer Personnel (1988)

One of the most critical issues facing managers of high tech companies is how to retain the spirit of excitement and energy as the company grows. Interviews with managers of these companies reflected the view that the spirit of excitement and energy which is so palatable in smaller software companies, somehow dissipates in a seemingly inevitable way as the company increases in size. (The notion that "something happens" when a company gets "too big" is a common one.) The question arising from this for managers is how that spirit of excitement or high level of motivation is created in the first place, and how it can be retained. In this commentary, some preliminary findings concerning the excitement levels in different size high tech companies are presented.The findings are based on the questionnaire results of 339 people from 11 high tech software companies; 7 "small" companies with less than 50 employees, 3 "medium" sized companies with between 150-250 employees and 1 "large" company with over 2, 000 employees in total.The average response rate for all companies was 55%. For the small companies it was much higher, at 68%, but in the large company it was 51%. The average age of the sample was 28 years, average years in present company was 2.5 years, 80 were women with 259 men. Most (96%) have at least a Bachelors degree so they represent a highly educated sample.