ppxscal/embedding_network huggingface dataset:
Object orientation in heterogeneous distributed computing systems
Authors: John R. Nicol, C. Thomas Wilkes, Frank A. Manola
Venue: Computer (1993)

The basic properties of object orientation and their application to heterogeneous, autonomous, and distributed system to increase interoperability ar examined. It is argued that object-oriented distributed computing is a natural step forward from client-server systems. To support this claim, the differing levels of object-oriented support already found in commercially available distributed systems-in particular, the distributed computing environment of the open software foundation and the Cronus system of Bolt Beranek, Newman (BBN)-are discussed. Emerging object-oriented systems and standards are described, focusing on the convergence toward a least-common-denominator approach to object-oriented distributed computing embodied by the object management group's common object request broker architecture.
Steady Gap Flows by the Spectral and Mortar Element Method
Authors: D. Weill, M. O. Deville
Venue: Journal of Scientific Computing (2002)

This work aims at observing the effect of the mortar element method applied to a geometry requiring refinement in the vicinity of singularities induced by the presence of sharp corners. We solve the two-dimensional incompressible Navier&ndash;Stokes equations with a spectral element method. Mortar elements allow for local polynomial refinement, since they allow for functional nonconformity. The problem solved is the flow in a channel partially obstructed by an obstacle representing a rectangular blade.
Efficient Sequential Test Generation Based on Logic Simulation
Authors: Shuo Sheng, Michael S. Hsiao
Venue: IEEE Design Test (2002)

A simple and highly efficient logic-simulation-based test generator uses a genetic algorithm to achieve both high fault coverage and short test generation times.
Generalized Mosaicing: Wide Field of View Multispectral Imaging
Authors: Yoav Y. Schechner, Shree K. Nayar
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (2002)

We present an approach to significantly enhance the spectral resolution of imaging systems by generalizing image mosaicing. A filter transmitting spatially varying spectral bands is rigidly attached to a camera. As the system moves, it senses each scene point multiple times, each time in a different spectral band. This is an additional dimension of the generalized mosaic paradigm, which has recently demonstrated yielding high radiometric dynamic range images in a wide field of view, using a spatially varying density filter. The resulting mosaic represents the spectrum at each scene point. The image acquisition is as easy as in traditional image mosaics. We derive an efficient scene sampling rate, and use a registration method that accommodates the spatially varying properties of the filter. Using the data acquired by this method, we demonstrate scene rendering under different simulated illumination spectra. We are also able to infer information about the scene illumination. The approach was tested using a standard 8-bit black/white video camera and a fixed spatially varying spectral (interference) filter.
Decomposing refinement proofs using assume-guarantee reasoning
Authors: Thomas A. Henzinger, Shaz Qadeer, Sriram K. Rajamani
Venue: Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design (2000)

Model-checking algorithms can be used to verify, formally and automatically, if a low-level description of a design conforms with a high-level description. However, for designs with very large state spaces, prior to the application of an algorithm, the refinement-checking task needs to be decomposed into subtasks of manageable complexity. It is natural to decompose the task following the component structure of the design. However, an individual component often does not satisfy its requirements unless the component is put into the right context, which constrains the inputs to the component. Thus, in order to verify each component individually, we need to make assumptions about its inputs, which are provided by the other components of the design. This reasoning is circular: component A is verified under the assumption that context B behaves correctly, and symmetrically, B is verified assuming the correctness of A. The assume-guarantee paradigm provides a systematic theory and methodology for ensuring the soundness of the circular style of postulating and discharging assumptions in component-based reasoning.We give a tutorial introduction to the assume-guarantee paradigm for decomposing refinement-checking tasks. To illustrate the method, we step in detail through the formal verification of a processor pipeline against an instruction set architecture. In this example, the verification of a three-stage pipeline is broken up into three subtasks, one for each stage of the pipeline.
Two-channel adaptive biorthogonal filterbanks via lifting
Authors: Penglang Shui, Zheng Bao, Xianda Zhang, Yuanyan Tang
Venue: Signal Processing (2002)

In the high bit-rate data compression, the filterbanks that match the statistical properties of inputs have been widely researched. For orthonormal uniform filterbanks and biorthogonal filterbanks without order constraints, the design problems have been solved on the whole. However, for biorthogonal FIR filterbanks, an efficient method associated with an algorithm for the design still needs to be developed. In this paper, two-channel adaptive biorthogonal filterbanks via lifting scheme are investigated. Starting from an arbitrary filterbank (orthonormal or biorthogonal), two-channel biorthogonal filterbanks are designed by the adaptive lifting scheme, which is a general form of our previous work. Two adaptive lifting algorithms are developed, namely, the sequential adaptive lifting and the joint adaptive lifting. Further, it is proved that starting from a linear-phase filterbank, the optimal filterbank by the sequential adaptive lifting preserves the linear-phase property. Experimental results show that the subband coding gains can be markedly improved when an appropriate initial filterbank is chosen.
Test Generation for Path Delay Faults Using Binary Decision Diagrams
Authors: Prathima Agrawal, Debashis Bhattacharya, Vishwani D. Agrawal
Venue: IEEE Transactions on Computers (1995)

A new test generation technique for path delay faults in circuits employing scan/hold type flip-flops is presented. Reduced ordered binary decision diagrams (ROBDDs) are used to represent Boolean functions realized by all signals in the circuit, as well as to represent the constraints to be satisfied by the delay fault test. Two faults are considered for each path in the circuit. For each fault, a pair of constraint functions, corresponding to the two time frames that constitute a transition, is evaluated. If the constraint function in the second time frame is non-null, robust - hazard-free - test generation for the delay fault is attempted. A robust test thus generated belongs either to the class of fully transitional path (FTP) tests or to the class of single input transition (SIT) tests. If a robust test cannot be found, the existence of a non-robust test is checked. Boolean algebraic manipulation of the constraint functions guarantees that if neither robust nor non-robust tests exist, the fault is undetectable. In its present form the method is applicable to all circuits that are amenable to analysis using ROBDDs. An implementation of this technique is used to analyze delay fault testability of ISCAS ¿89 benchmark circuits. These results show that the algebraic technique is one to two orders of magnitude faster than previously reported methods based on branch-and-bound algorithms.
Fault Models and Test Procedures for Flash Memory Disturbances
Authors: Mohammad Gh. Mohammad, Kewal K. Saluja, Alex S. Yap
Venue: Journal of Electronic Testing: Theory and Applications (2001)

Disturbances are special type of faults that are unique to flash memories. Causes of the disturbances are defects within the insulating layers of the memory element. These defects result in abnormal behavior of a memory cell under specific conditions. This paper describes characteristics of these defects as well as their manifestation as DC-Programming, DC-Erasure, and Drain Disturbance. We develop fault models to capture the behavior of faulty flash memories. We introduce three different fault models based on the underlying defects in a memory cell. These models are: Simple, Exclusive and General Fault model. Further, we develop test algorithms that detect disturbance faults under each of the fault models. The test algorithms reported in this paper for the simple fault model for each type of disturbance require optimal number of program, read, and flash operations&semi; where as the algorithms for the remaining two fault models require near optimal number of these operations.
Official NetScape Javascript Book 1.2: Programmer's Reference, 1st edition
Authors: Peter Kent, Kent Multer
Venue:  (1997)

:The most complete, concise reference available for JavaScript 1.2, this professional guide covers everything you need to know to write effective scripts - all in an encyclopedic format. Covers all objects, properties, methods, functions, expressions, and statements with reserved words, symbols, color codes, and ISO character sets; describes frames, multiple windows, event handlers, and other popular features; lists all commands alphabetically with extensive cross references including handy jump tables, and a complete, hypertext version of the book on CD-ROM; each entry includes syntax, usage, values, and parameters with examples of how the scripts work; topics address advanced techniques such as animation, security, and interaction with applets and plug-ins; plus a thorough discussion of programming techniques with JavaScript 1.2.
An Iteration Partition Approach for Cache or Local Memory Thrashing on Parallel Processing
Authors: J. Z. Fang, M. Lu
Venue: IEEE Transactions on Computers (1993)

Parallel processing systems with cache or local memory in the memory hierarchies are considered. These systems have a local cache memory in each processor and usually employ a write-invalidate protocol for the cache coherence. In such systems, a problem called 'cache or local memory thrashing' can arise in executions of parallel programs, when the data unnecessarily moves back and forth between the caches or local memories in different processors. An approach to eliminate, or at least to reduce, such movement for nested parallel loops is presented. It is based on relations between array element accesses and enclosed loop indexes in the loops. The relations can be used to assign processors to execute the appropriate iterations for parallel loops in the loop nests with respect to the data in their caches or local memories. An algorithm for calculating the correct iteration of the parallel loop in terms of loop indexes of the previous iterations executed in the processor is presented. This method benefits parallel code with nested loop structures in a wide range of applications. The experimental results show that the technique can achieve speedups up to 2.
Maximum Performance Pipelines With Switchable Reservation Tables
Authors: Yi Chang Tseng, Ahmed El-Amawy
Venue: IEEE Transactions on Computers (1995)

We describe a new technique for achieving maximum performance in pipelines which allows task initiations to follow any arbitrary cycle provided that the average time between initiations is ¿M, where M is the maximum number of reservations of any stage. This is not possible with the existing methods. The idea behind the proposed scheme is to allow different initiations to follow different reservation tables. This contrasts existing methods which require all initiations in a cycle to follow the same reservation table. We describe an algorithm for systematic construction of the reservation tables for different initiations in any cycle whose performance does not exceed the theoretical upper bound on throughput. We formally prove that the algorithm is correct and that it will always succeed in constructing the tables.
The Compute Cluster and Other Parallel Programming Models
Venue: Computer (1993)

The parallel processing requirements of many computer applications, such as machine vision, radar, solar, and signal processing, are reviewed. The major hardware architectural features in optimizing parallel processing performance (interconnect topology, memory locality, and synchronization facilities) are discussed. The various parallel processing models available are also discussed. These include job-level parallelism, data-level parallelism, algorithm-level parallelism, loop-level parallelism, and compute clusters. The ACM Portal is published by the Association for Computing Machinery. Copyright © 2010 ACM, Inc. Terms of Usage Privacy Policy Code of Ethics Contact Us Useful downloads: Adobe Acrobat QuickTime Windows Media Player Real Player
Global optimization of SDH networks: a practical application
Authors: Dirk Beckmann, Jörn Thurow
Venue: International Journal of Network Management (2003)

We describe in this paper how the backbone network of a major German telecommunication company has been globally optimized using the so-called branch-and-bound algorithm. The described optimization approach enables significant reductions of expenses for leased lines compared to manually derived planning results. This gain achieved by the presented optimization approach is also demonstrated by the comparison with a heuristic algorithm which is used for the simulation of a human network planning process.
Local Multichannel Deconvolution
Authors: G. R. Easley, D. F. Walnut
Venue: Journal of Mathematical Imaging and Vision (2003)

We introduce a method to locally restore multiple blurred images that yields an extended boundary of the restored image. In particular, we provide a method for finding solutions that are compactly (finitely) supported to the multichannel deconvolution equation when the impulse responses are also compactly supported distributions. This method allows us to broaden the scope of calculating solutions for any particular type of function beyond what was possible in D.F. Walnut (J. Fourier Anal. Appl., Vol. 4, No. 6, pp. 669&ndash;709, 1998). During reconstruction, noise from the blurred images is added locally in neighborhoods dependent on the support of the restoration filters. Numerical simulations indicate that these filters may highly increase the magnitude of the noise but with a slight regularization of the filters, the results obtained show the effectiveness of this method.
Characteristics of semi- and full discretization of stabilized Galerkin meshfree method
Authors: Yang You, Jiun-Shyan Chen, Thomas E. Voth
Venue: Finite Elements in Analysis and Design (2002)

Stabilized conforming nodal integration (SCNI) has been developed to enhance computational efficiency of Galerkin meshfree methods. This paper employs von Neumann analyses to study the spatial semi-discretization of Galerkin meshfree methods using SCNI. Two model problems were presented with respect to the normalized phase speed and group speed for the wave equation, and normalized diffusivity for the heat equation. Both consistent and lumped mass (capacity) discretizations are considered in the study. The transient properties in the full discretization of the two model problems were also analyzed. The results show superior dispersion behavior in meshfree methods integrated by SCNI compared to the Gauss integration when consistent mass (capacity) matrix is employed in the discretization. For the lumped mass case, SCNI performance is comparable to that of the Gauss integration, but exhibits considerable reduction of computational time.
Where is Computing Headed?
Authors: Ted G. Lewis
Venue: Computer (1994)

Technological change is putting entire industries on the betting line. For computer technologists, these shifts can mean opportunity or disappointment as one technology is replaced by another. Therefore, it is important that we consider economic and technical forces when we plan for the future. By studying predictable technology and asking "what if" questions where developments are less certain, we can envision the state of computing in another 10 years.
In Search of the Wisdom Web
Authors: Ning Zhong, Jiming Liu, Yiy Yao
Venue: Computer (2002)

Web intelligence offers a new direction for scientific research and development, pushing technology toward manipulating the meaning of data and creating a distributed intelligence that can actually get things done. WI explores the fundamental and practical impact that artificial intelligence and advanced information technology will have on the next generation of Web-empowered systems, services, and environments.The Web significantly affects both academic research and everyday life, revolutionizing how we gather, store, process, present, share, and use information. It offers opportunities and challenges in many areas, including business, commerce, finance, and research and development.The next-generation Web will go beyond improved information search and knowledge queries and will help people achieve better ways of living, working, playing, and learning. To fulfill its potential, the intelligent Web's design and development must incorporate knowledge from existing disciplines, such as artificial intelligence and information technology, in a totally new domain.
Using VHDL for High-Level, Mixed-Mode System Simulation
Authors: Mani B. Srivastava, Robert W. Brodersen
Venue: IEEE Design Test (1992)

The application of a very-high-speed integrated circuit hardware description language (VHDL) to the modeling of complex, application-specific systems that employ a mix of digital hardware and software and interact with their environments through continuous-time components is described. A VHDL model simulating package and a SPICE-like low-level package simulating continuous-time subsystems are discussed. To illustrate how the various packages discussed are used in a complete high-level system simulation, a simplified high-level block diagram of a robot control system is presented, and the modeling of the system is described. Specialized VHDL packages model the system's discrete-time portion as a set of concurrent processes communicating via channels with well-defined protocols, and sets of coupled ordinary differential equations model the system's continuous-time blocks.
Adaptive-Size Meshes for Rigid and Nonrigid Shape Analysis and Synthesis
Authors: W. C. Huang, D. B. Goldgof
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1993)

A physically based modeling method that uses adaptive-size meshes to model surfaces of rigid and nonrigid objects is presented. The initial model uses an a priori determined mesh size. However, the mesh size increases or decreases dynamically during surface reconstruction to locate nodes near surface areas of interest (like high curvature points) and to optimize the fitting error. Further, presented with multiple 3-D data frames, the mesh size varies as the data surface undergoes nonrigid motion. This model is used to reconstruct 3-D surfaces, analyze the nonrigid motion, track the corresponding points in nonrigid motion, and create graphic animation and visualization. The method was tested on real range data, on simulated nonrigid motion, and on real data for the left ventricular motion.
Prototyping the M68060 for Concurrent Verification
Authors: Jainendra Kumar
Venue: IEEE Design Test (1997)

Large-scale hardware logic emulation using software-configurable hardware provides a new means to rapidly prototype large designs such as advanced microprocessors, thereby significantly improving pre-tape out verification of complex integrated circuits.The essence of hardware logic emulation is the provision of a hardware prototype of the circuit being designed. Such a hardware prototype can execute both pseudo-random verification vectors and software application programs up to six orders-of-magnitude faster than conventional software logic simulators. Trillions of verification vectors can be run on the emulation prototype for verification in only a few weeks compared to the prior best practice of running only billions of verification vectors in many months. The provision of "virtual silicon" for the Motorola's 68060 superscalar microprocessor before tape out facilitated true concurrent engineering, full functional verification of the design, system (hardware/software) integration and debug, resulting in a substantial reduction in cycle time and time to market. Elimination of several silicon re-spins is a significant distinguishing result of emulation verification. Application of hardware logic emulation requires a sound design methodology with an ability to generate a full-chip gate-level model from the HDL models.Development of emulation library, equivalent emulation models for custom blocks, and modeling design memories were some of the interesting challenges encountered in successfully building a reconfigurable prototype for the M68060 microprocessor. Once the prototype is validated to 'functionally' represent the M68060, it is extensively utilized to verify test cards, testers, perform architectural analysis, run benchmarks, conformance tests, run application software in target systems, verify post-silicon bug fixes, and many more tasks which would normally not be possible before fabricating a silicon using conventional technologies. Emulation verification is rapidly becoming a required verification tool to manage the next wave of design complexity.
Shrimp Project Update: Myrinet Communication
Authors: Cezary Dubnicki, Angelos Bilas, Yuqun Chen, Stefanos N. Damianakis, Kai Li
Venue: IEEE Micro (1998)

In the last year's IEEE Micro special issue on the Hot Interconnects IV Symposium, we discussed our experiences with client-server computing on the Paragon-based Shrimp multicomputer. Since then we implemented the same virtual memory-mapped communication (VMMC) mechanism on the Myrinet-based Shrimp multicomputer (a set of Pentium PCs connected by a Myrinet network). In both cases we achieved protected, user-level, end-to-end performance close to the hardware limits. However, VMMC imposes a copy for high-level connection-oriented communication libraries. Therefore, we extended the VMMC model, and designed and built a new implementation. We call the new model VMMCII. This update reports our latest work with VMMCII on the Myrinet-based Shrimp multicomputer.
Travelling fronts for the KPP equation with spatio-temporal delay
Authors: P. Ashwin, M. V. Bartuccelli, T. J. Bridges, S. A. Gourley
Venue: Zeitschrift f&uuml;r Angewandte Mathematik und Physik (ZAMP) (2002)

We study an integro-differential equation based on the KPP equation with a convolution term which introduces a time-delay in the nonlinearity. Special attention is paid to the question of the existence of travelling wavefront solutions connecting the two uniform steady states and their qualitative form. Motivated by the analogue between steady travelling fronts and heteroclinic orbits of an associated ordinary differential equation, we prove, using a geometric singular perturbation analysis, that steady travelling wavefront solutions persist when the delay is suitably small, for a class of convolution kernels. These travelling fronts are qualitatively similar to the well known KPP wavefront. The effect of finite and large delay is studied numerically and we find that this introduces qualitative changes to the fronts but that the front remains robust. A numerical integration of the initial-value problem confirms the qualitative shape of these fronts and suggests that - even for large delay - they may be temporally stable. Finally we show that in the discrete delay case the non-zero uniform state can be driven unstable. In this case a travelling wavefront can leave in its wake a periodic travelling wave moving with a different speed.