ppxscal/embedding_network huggingface dataset:
Skew-Hadamard Matrices and the Smith Normal Form
Authors: T. S. Michael, W. D. Wallis
Venue: Designs, Codes and Cryptography (1998)

We show that the Smith normal form of every skew-Hadamard matrix of order 4m is diag[1,2,....,2, 2m,....,2m,4m]
Low energy memory and register allocation using network flow
Authors: Catherine H. Gebotys
Venue: Proceedings of the 34th annual Design Automation Conference (1997)

This paper presents for the first time low energy simultaneousmemory and register allocation. A minimum cost network flowapproach is used to efficiently solve for minimum energy dissipationsolutions in polynomial time. Results show that estimatedenergy improvements of 1.4 to 2.5 times over previous researchare obtained. This research is important for industry since energydissipation is minimized without requiring an increase in cost.
Hardness Results for Learning First-Order Representations and Programming by Demonstration
Authors: William W. Cohen
Venue: Machine Learning (1998)

Learning from &ldquo;structured examples&rdquo; is necessary in a number of settings, including inductive logic programming. Here we analyze a simple learning problem in which examples have non-trivial structure: specifically, a learning problem in which concepts are strings over a fixed alphabet, examples are deterministic finite automata (DFAs), and a string represents the set of all DFAs that accept it. We show that solving this &ldquo;dual&rdquo; DFA learning problem is hard, under cryptographic assumptions. This result implies the hardness of several other more natural learning problems, including learning the description logic Classic from subconcepts, and learning arity-two &ldquo;determinate&rdquo; function-free Prolog clauses from ground clauses. The result also implies the hardness of two formal problems related to the area of &ldquo;programming by demonstration&rdquo;: learning straightline programs over a fixed operator set from input-output pairs, and learning straightline programs from input-output pairs and &ldquo;partial traces&rdquo;.
Using after action review systems for exercise planning and control
Authors: John A. Hixson
Venue: Proceedings of the 28th conference on Winter simulation (1996)

After Action Review Systems-the training assessment component of simulation training exercises-provide vital feedback to the military training audience. This paper describes how AARSs serve another essential training function-exercise planning and control-by supplying archived data, in a variety of formats, arrays, and sequences, that can be used to develop plans and monitor exercise progress. This claim is based on Logicon's nine years of experience developing and using an AARS to support the United States Army Battle Command Training Program. The ACM Portal is published by the Association for Computing Machinery. Copyright © 2010 ACM, Inc. Terms of Usage Privacy Policy Code of Ethics Contact Us Useful downloads: Adobe Acrobat QuickTime Windows Media Player Real Player
MANUPLAN: a precursor to simulation for complex manufacturing systems
Authors: Rajan Suri, Gregory W. Diehl
Venue: Proceedings of the 17th conference on Winter simulation (1985)

MANUPLAN is a tool for designing and analyzing manufacturing systems. In the early stages of manufacturing systems planning, it offers an efficient alternative to simulation modelling. MANUPLAN is based on a state-of-the-art analytical model. It is practical and easy to use, being simpler and quicker than simulations model. In a typical case, a system design that would have taken several weeks to evaluate using simulation was evaluated in under two days with MANUPLAN. Inputs to MANUPLAN are the basic system design data: information on part routing, equipment capacities and reliabilities, and production requirements. Outputs from MANUPLAN include part flow times, work-in-process levels, equipment utilizations, and production rates achieved. Each run by MANUPLAN takes only a few seconds. By changing the system design data, manufacturing designers can quickly understand the trade-offs between inventory levels, production requirements, flow times, and equipment reliabilities, for their system.
A Unifying Theoretical Background for Some Bdd-based Data Structures
Authors: Christoph Meinel, Anna Slobodová
Venue: Formal Methods in System Design (1997)

In the paper, we propose a general concept (denoted by TBDD) for Boolean functions manipulation that is based on cube transformations. The basic idea is to manipulate a Boolean function by converting it by means of a cube transformation into a function that can be efficiently represented and manipulated in terms of ordered binary decision diagrams (OBDDs). We show that the new concept unifies several BDD&ndash;based data structures considerably, and simplifies their manipulation to work with the simple and well&ndash;understood data struture of OBDDs. This is especially important for practical applications.Further, to give an example of how TBDDs open new ways in the search for efficient data structures for Boolean functions, we discuss the data structure of typed kFBDDs.
Implementation of 5-point/9-point multi-level methods on hypercube architectures
Authors: Victor Eijkhout
Venue: Proceedings of the 4th international conference on Supercomputing (1990)

Computational complexity of implementing 5/9-point multi-level methods on hypercube architectures is considered. The embedding of the nested red/black structures of these methods is described, and an analysis is made of data distances involved.
Optimal Algorithmic Complexity of Fuzzy ART
Authors: T. Burwick, F. Joublin
Venue: Neural Processing Letters (1998)

We discuss implementations of the Adaptive Resonance Theory (ART) on a serial machine. The standard formulation of ART, which was inspired by recurrent brain structures, corresponds to a recursive algorithm. This induces an algorithmic complexity of order O(N^2)+O(MN) in worst and average case, N being the number of categories, and M the input dimension. It is possible, however, to formulate ART in a non-recursive algorithm such that the complexity is of order O(MN) only.
Bounding the Size of Planar Intertwines
Authors: Arvind Gupta, Russell Impagliazzo
Venue: SIAM Journal on Discrete Mathematics (1997)

The proof of Wagner's conjecture by Robertson and Seymour gives a finite description of any family of graphs which is closed under the minor ordering. This description is a finite set of minimal graphs not in the family; these graphs are called the obstructions of the family. Since the intersection and union of two minor closed graph families is again a minor closed graph family, an interesting question regards computing the obstructions of the new family given the obstructions for the original two families. It is easy to compute the obstructions of the intersection, but nontrivial to compute those of the union. In this paper, we show that if the original families are planar then the planar obstructions of the union are no larger than nO(n2), where n is the size of the largest obstruction of the original families.
Generating efficient virtual worlds for visualization using partial evaluation and dynamic compilation
Authors: Clifford Beshers, Steven Feiner
Venue: ACM SIGPLAN Notices (1997)

We argue that runtime program transformation, partial evaluation, and dynamic compilation are essential tools for automated generation of flexible, highly interactive graphical interfaces. In particular, these techniques help bridge the gap between a high-level, functional description and an efficient implementation. To support our claim, we describe our application of these techniques to a functional implementation of n-Vision, a real-time visualization system that represents multivariate relations as nested 3D interactors, and to Auto Visual, a rule-based system that designs n-Vision visualizations from high-level task specifications. n-Vision visualizations are specified using a simple functional language. These programs are transformed into a cached dataflow graph. A partial evaluator is used on particular computation-intensive function applications, and the results are compiled to native code. The functional representation simplifies generation of correct code, and the program transformations ensure good performance. We demonstrate why these transformations improve performance and why they cannot be done at compile time.
Preprototyping SIMD coprocessors using virtual machine emulation and trace compilation
Authors: Martin C. Herbordt, Owais Kidwai, Charles C. Weems
Venue: Proceedings of the 1997 ACM SIGMETRICS international conference on Measurement and modeling of computer systems (1997)

The use of massively parallel SIMD array architectures is proliferating in the area of domain specific coprocessors. Even so, they have undergone few systematic empirical studies. The underlying problems include the size of the architecture space, the lack of portability of the test programs, and the inherent complexity of simulating up to hundreds of thousands of processing elements. We address the computational cost problem with a novel approach to trace-based simulation. Code is run on an abstract virtual machine to generate a coarse-grained trace, which is then refined through a series of transformations (a process we call trace compilation) wherein greater resolution is obtained with respect to the details of the target machine. We have found this technique to be one to two orders of magnitude faster than instruction-level simulation while still retaining much of the accuracy of the model. Furthermore, abstract machine traces must be regenerated for only a small fraction of the possible parameter combinations. Using virtual machine emulation and trace compilation also addresses program portability by allowing the user to code in a single data parallel language with a single compiler, regardless of the target architecture. This technique has already been used to generate significant results with respect to SIMD array architectures, a sample of which are presented here.
Embedded system synthesis by timing constraints solving
Authors: Krzysztof Kuchcinski
Venue: Proceedings of the 10th international symposium on System synthesis (1997)

This paper presents an approach to embedded system synthesis which minimizes a system cost while implementing given timing requirements. The embedded system is represented by a set of finite domain constraints defining different requirements on processes timing, system resources and interprocess communication. The assignment of processes to processors and interprocess communications to buses as well as their scheduling are then defined as an optimization problem. A prototype system, based on constraint solving techniques, has been implemented in CHIP 5, the constraint logic programming system. Experimental results show that this approach can be efficiently used to define different system constraints and generate optimized system implementations.
So many algorithms. So little time
Authors: Garrison W. Greenwood
Venue: ACM SIGSOFT Software Engineering Notes (1997)

This paper discusses the futility in answering questions about convergence and performance in algorithms used to solve optimization problems. Not only are these answers difficult to obtain, they are often times meaningless.
ACE: a decision tool for restaurant managers
Authors: Todd C. Whyte, Darrell W. Starks
Venue: Proceedings of the 28th conference on Winter simulation (1996)

A simulation based decision support tool called ACE has been developed for Pepsico Restaurants International (PRI) allowing restaurant managers to quickly and accurately analyze a given restaurant, ACE gives the restaurant manager a tool to evaluate the customer point of contact within a given restaurant. This simulation based tool uses Arena for the model and Lotus 123 for the interface. PRI has installed this tool in two of the six international regions and will by early 1997 have it in all of the international regions.
Asymptotically Efficient Adaptive Choice of Control Laws inControlled Markov Chains
Authors: Todd L. Graves, Tze Leung Lai
Venue: SIAM Journal on Control and Optimization (1997)

We consider a controlled Markov chain on a general state space whose transition probabilities are parameterized by an unknown parameter belonging to a compact metric space. There is a one-step reward associated with each pair of control and the following state of the process. Given a finite set of stationary control laws, under each of which the Markov chain is uniformly recurrent, an optimal control law is this set is one that maximizes the long-run average reward. In ignorance of the parameter value, we construct an adaptive control rule which uses the optimal control law(s) at a relative frequency of 1 - O(n-1 log n) and show that this relative frequency gives an asymptotically optimal balance between the control objective and the amount of information needed to learn about the unknown parameter. The basic idea underlying this construction is to introduce suitable "uncertainty adjustments" via sequential testing theory into the certainty-equivalence rule, thus resolving the apparent dilemma between control and information.
Standardized Time Series LP-Norm Variance Estimators for Simulations
Authors: Gamze Tokol, David Goldsman, Daniel H. Ockerman, James J. Swain
Venue: Management Science (1998)

This paper studies a class of estimators for the variance parameter of a stationary stochastic process. The estimators are based on Lp norms of standardized time series, and they generalize previously studied estimators due to Schruben. We show that the new estimators have some desirable properties: they are asymptotically unbiased and have low asymptotic variance. We also illustrate empirically the performance of the Lp-norm estimators on various stochastic processes.
The MENTOR workbench for enterprise-wide workflow management
Authors: Dirk Wodtke, Jeanine Weissenfels, Gerhard Weikum, Angelika Kotz Dittrich, Peter Muth
Venue: ACM SIGMOD Record (1997)

MENTOR (&ldquo;Middleware for Enterprise-Wide Workflow Management&rdquo;) is a joint project of the University of the Saarland, the Union Bank of Switzerland, and ETH Zurich [1, 2, 3]. The focus of the project is on enterprise-wide workflow management. Workflows in this category may span multiple organizational units each unit having its own workflow server, involve a variety of heterogeneous information systems, and require many thousands of clients to interact with the workflow management system (WFMS). The project aims to develop a scalable and highly available environment for the execution and monitoring of workflows, seamlessly integrated with a specification and verification environment. For the specification of workflows, MENTOR utilizes the formalism of state and activity charts. The mathematical rigor of the specification method establishes a basis for both correctness reasoning and for partitioning of a large workflow into a number of subworkflows according to the organizational responsibilities of the enterprise. For the distributed execution of the partitioned workflow specification, MENTOR relies mostly on standard middleware components and adds own components only where the standard components fall short of functionality or scalability. In particular, the run-time environment is based on a TP monitor and a CORBA implementation.
Introduction to the WITNESS visual interactive simulator and OLEII automation
Authors: W. Bruce Thompson
Venue: Proceedings of the 28th conference on Winter simulation (1996)

The paper describes AT&T Istel's WITNESS Visual Interactive simulator. Benefits of using WITNESS are described and illustrated by explaining the steps required to build any WITNESS model. OLEII Automation as it pertains to WITNESS is also introduced.
On Parabolic and Elliptic Spectral Dichotomy
Authors: A. N. Malyshev, M. Sadkane
Venue: SIAM Journal on Matrix Analysis and Applications (1997)

We discuss two spectral dichotomy techniques: one for computing an invariant subspace of a nonsymmetric matrix associated with the eigenvalues inside and outside a given parabola; another one for computing a right deflating subspace of a regular matrix pencil associated with the eigenvalues inside and outside a given ellipse. The techniques use matrices of twice the order of the original matrices on which the spectral dichotomy by the unit circle and by the imaginary axis apply efficiently. We prove the equivalence between the condition number of the original problems and that of the transformed ones.
A Theory for Total Exchange in Multidimensional Interconnection Networks
Authors: Vassilios V. Dimakopoulos, Nikitas J. Dimopoulos
Venue: IEEE Transactions on Parallel and Distributed Systems (1998)

Total exchange (or multiscattering) is one of the important collective communication problems in multiprocessor interconnection networks. It involves the dissemination of distinct messages from every node to every other node. We present a novel theory for solving the problem in any multidimensional (cartesian product) network. These networks have been adopted as cost-effective interconnection structures for distributed-memory multiprocessors. We construct a general algorithm for single-port networks and provide conditions under which it behaves optimally. It is seen that many of the popular topologies, including hypercubes, k-ary n-cubes, and general tori satisfy these conditions. The algorithm is also extended to homogeneous networks with 2k dimensions and with multiport capabilities. Optimality conditions are also given for this model. In the course of our analysis, we also derive a formula for the average distance of nodes in multidimensional networks; it can be used to obtain almost closed-form results for many interesting networks.
Design-For-Test in a Multiple Substrate Multichip Module
Authors: Joel A. Jorgenson, Russell J. Wagner
Venue: Journal of Electronic Testing: Theory and Applications (1997)

This paper highlights the development and effectiveness of a multichip module (MCM) Design-For-Testability methodology for an application intended for use in a fully electronic active matrix LCD flight instrument. MCM test issues discussed include Design-For-Testability, substrate test, Known-Good Die (KGD) and module level test.The design incorporates IEEE 1149.1 and Built-In-Self-Test features. Bare die pretest is accomplished with a Ball Grid Array (BGA) chip carrier approach.The hardware consists of a mature digital design comprised of application specific and industry standard integrated circuits.
A graphical hardware design language
Authors: Paul J. Drongowski, Jwahar R. Bami, Ranganathan Ramaswamy, Sundar Iyengar, Tsu-Hua Wang
Venue: Proceedings of the 25th ACM/IEEE Design Automation Conference (1988)

Gdl is a graphical hardware design language that separates design decisions into three interrelated, but distinct domains: behavioral, structural and physical. Specific language features are provided to represent a design in each of these domains. This report describes the process model for Gdl. Functional behavior is separated into distinct activities called &ldquo;processes&rdquo; (autonomous control centers.) The computations performed by a process are specified in its behavior graph. Processes may communicate with each other through ports where the channel between two ports may be an abstract logical link or may be a physical bus. Provisions are made for synchronization. The paper concludes with an evaluation of Gdl and suggestions for future research.
The efficiency of inverted index and cluster searches
Authors: Ellen M. Voorhees
Venue: Proceedings of the 9th annual international ACM SIGIR conference on Research and development in information retrieval (1986)

The processing time and disk space requirements of an inverted index and top-down cluster search are compared. The cluster search is shown to use both more time and more disk space, mostly due to the large number of cluster centroids needed by the search. When shorter centroids are used, the efficiency of the cluster search improves, but the inverted index search remains more efficient.
Ada and the Navy next generation computer resources operating system interface standard
Authors: Dan Juttelstad, Rich Bergman
Venue: Proceedings of the conference on TRI-ADA '90 (1990)

This paper provides an overview of Next Generation Computer Resources (NGCR) program and, in particular, the Operating Systems Standards Working Group (OSSWG) and its present status in defining a standard Operating System Interface (OSIF). This brief background is followed by an outline of the technical issues addressed by the OSSWG with respect to system characteristics, application domains, system OSIF requirements, and details of the Ada interface requirements for the Navy's future real-time systems. In conclusion a projected concept of the OSIF standard utilization is provided.
Decomposition of timed decision tables and its use in presynthesis optimizations
Authors: Jian Li, Rajesh K. Gupta
Venue: Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design (1997)

Presynthesis optimizations transform a behavioral HDL description into an optimized HDL description that results in improved synthesis results. We introduce the decomposition of timed decision tables (TDT), a tabular model of system behavior. The TDT decomposition is based on the kernel extraction algorithm. By experimenting using named benchmarks, we demonstrate how TDT decomposition can be used in presynthesis optimizations.
Listing all Minimal Separators of a Graph
Authors: T. Kloks, D. Kratsch
Venue: SIAM Journal on Computing (1998)

An efficient algorithm listing all minimal vertex separators of an undirected graph is given. The algorithm needs polynomial time per separator that is found.
An Optimal Algorithm for Scanning All Spanning Trees of Undirected Graphs
Authors: Akiyoshi Shioura, Akihisa Tamura, Takeaki Uno
Venue: SIAM Journal on Computing (1997)

Let G be an undirected graph with V vertices and E edges. Many algorithms have been developed for enumerating all spanning trees in G. Most of the early algorithms use a technique called "backtracking." Recently, several algorithms using a different technique have been proposed by Kapoor and Ramesh (1992), Matsui (1993), and Shioura and Tamura (1993). They find a new spanning tree by exchanging one edge of a current one. This technique has the merit of enabling us to compress the whole output of all spanning trees by outputting only relative changes of edges. Kapoor and Ramesh first proposed an O(N + V + E)-time algorithm by adopting such a "compact" output, where N is the number of spanning trees. Another algorithm with the same time complexity was constructed by Shioura and Tamura. These are optimal in the sense of time complexity but not in terms of space complexity because they take O(VE) space. We refine Shioura and Tamura's algorithm and decrease the space complexity from O(VE) to O(V + E) while preserving the time complexity. Therefore, our algorithm is optimal in the sense of both time and space complexities.