ppxscal/embedding_network huggingface dataset:
Robust Estimation of Rotation Angles from Image Sequences Usingthe Annealing M-Estimator
Authors: Stan Z. Li, Han Wang, William Y. C. Soh
Venue: Journal of Mathematical Imaging and Vision (1998)

A robust method is presented for computing rotation angles of image sequences from a set of corresponding points containing outliers. Assuming known rotation axis, a least-squares (LS) solution are derived to compute the rotation angle from a clean data set of point correspondences. Since clean data is not guaranteed, we introduce a robust solution, based on the M-estimator, to deal with outliers. Then we present an enhanced robust algorithm, called the annealing M-estimator (AM-estimator), for reliable robust estimation. The AM-estimator has several attractive advantages over the traditional M-estimator: By definition, the AM-estimator involves neither scale estimator nor free parameters and hence avoids instabilities therein. Algorithmically, it uses a deterministic annealing technique to approximate the global solution regardless of the initialization. Experimental results are presented to compare the performance of the LS, M- and AM-estimators for the angle estimation. Experiments show that in the presence of outliers, the M-estimator outperforms the LS estimator and the AM-estimator outperforms the M-estimator.
Replicated Process Allocation for Load Distribution in Fault-Tolerant Multicomputers
Authors: Jong Kim, Heejo Lee, Sunggu Lee
Venue: IEEE Transactions on Computers (1997)

In this paper, we consider a load-balancing process allocation method for fault-tolerant multicomputer systems that balances the load before as well as after faults start to degrade the performance of the system. In order to be able to tolerate a single fault, each process (primary process) is duplicated (i.e., has a backup process). The backup process executes on a different processor from the primary, checkpointing the primary process and recovering the process if the primary process fails. In this paper, we formalize the problem of load-balancing process allocation and propose a new process allocation method and analyze the performance of the proposed method. Simulations are used to compare the proposed method with a process allocation method that does not take into account the different load characteristics of the primary and backup processes. While both methods perform well before the occurrence of a fault, only the proposed method maintains a balanced load after the occurrence of such a fault.
Latin Hypercube Sampling Monte Carlo Estimation of AverageQuality Index for Integrated Circuits
Authors: Mansour Keramat, Richard Kielbasa
Venue: Analog Integrated Circuits and Signal Processing (1997)

The Monte Carlo method exhibits generality and insensitivity to the number of stochastic variables, but is expensive for accurate Average Quality Measure (AQI) or Parametric Yield estimation of MOS VLSI circuits. In this contribution a new method of variance reduction technique, viz. the Latin Hypercube Sampling (LHS) method is presented which improves the efficiency of AQI estimation in integrated circuits especially for MOS digital circuits. This method is similar to the Primitive Monte Carlo (PMC) method except in samples generation step where the Latin Hypercube Sampling method is used. This sampling method is very simple and does not involve any further simulations. Moreover, it has a smaller variance with respect to the PMC estimator. Encouraging results have thus far been obtained. A 3-dimensional quadratic function, a high pass filter, and a CMOS delay circuit examples are included to demonstrate the efficiency of this technique.
On Using Real-Time Static Locking Protocols for DistributedReal-Time Databases
Authors: Kam-Yiu Lam, Sheung-Lun Hung, Sang H. Son
Venue: Real-Time Systems (1997)

The use of Static Two Phase Locking Protocols (S2PL) for concurrency control in real-time database systems (RTDBS) has received little attention in the past. Actually, real-time S2PL (RT-S2PL) protocols do possess some desirable features making them suitable for RTDBS, especially for distributed real-time database systems (DRTDBS) in which remote locking is required and distributed deadlock is possible. In this paper, different RT-S2PL protocols are proposed. They differ in their methods of reducing the blocking time of higher priority transactions. Their performance is studied and compared with a real-time dynamic two phase locking protocol (RT-D2PL), called Hybrid Two Phase Locking (Hb2PL). The impact of different system and workload parameters, such as mean inter-arrival time of transactions, number of remote lock requests of a transaction, communication overhead for sending messages, and database size on their performance have been examined. The performance results indicate that the RT-S2PL protocols are suitable for DRTDBS in which the proportion of local locks of a transaction is small and the communication overhead for locking is high.
Mask verification on the connection machine
Authors: Erik C. Carlson, Rob A. Rutenbar
Venue: Proceedings of the 25th ACM/IEEE Design Automation Conference (1988)

Parallel mask verification algorithms have been developed for the Connection Machine, a massively parallel processor with up to 64K processors. We discuss the design and implementation of algorithms for several essential primitives: generation of completely-intersected mask data, mask-to-mask Boolean operations, labeling of connected regions, and identification of width and spacing violations. Performance results from experiments on a 16K-processor machine are presented. Speedups between 40 and 240 over a VAX 11/785 have been measured.
CAD tool needs for system designers
Venue: Proceedings of the 25th ACM/IEEE Design Automation Conference (1988)

Most CAD research to date has focused on a narrow class of topics - design rule checking, placement and routing, simulation, etc. This research has lead to high-quality tools for a limited set of tasks. Other steps in the design of a major electronic system, such as exploring alternate architectures, managing multiple representations of a constantly changing design, and maintaining project time schedules remain largely unsupported by today's CAD systems. These tasks remain labor-intensive, tedious, and error prone. This panel brings together experienced system designers to hear their views on what tasks require better support, and what kinds of tools might assist these tasks. It is hoped that this panel will provide inspiration for new research areas in CAD.
Computational geometry column 33
Authors: Joseph O'Rourke
Venue: ACM SIGACT News (1998)

Several recent SIGGRAPH papers on surface simplification are described.
Functional design for testability of control-dominated architectures
Authors: F. Fummi, U. Rovati, D. Sciuto
Venue: ACM Transactions on Design Automation of Electronic Systems (TODAES) (1997)

Control-dominated architectures are usually described in a hardware description language (HDL) by means of interacting FSMs. A VHDL or Verilog specification can be translated into an interacting FSM (IFSM) representation as described here. The IFSM model allows us to approach the testable synthesis problem at the level of each FSM. The functionality is modified by the addition of transparency to data flow. The complete testability of the IFSM implementation is thus achieved by connecting fully testable implementations of each modified FSM. In this way, test sequences separately generated for each FSM are directly applied to the IFSM to achieve complete fault coverage. The addition of test functionality to each FSM description, and its simultaneous synthesis with the FSM functionality, produces a lower area overhead than that necessary for the application of a partial-scan technique. Moreover, the test generation problem is highly simplified since it is reduced to the test generation for each separate FSM.
A threshold of ln n for approximating set cover
Authors: Uriel Feige
Venue: Journal of the ACM (JACM) (1998)

Given a collection F of subsets of S = {1,&hellip;,n}, set cover is the problem of selecting as few as possible subsets from F such that their union covers S,, and max k-cover is the problem of selecting k subsets from F such that their union has maximum cardinality. Both these problems are NP-hard. We prove that (1 - o(1)) ln n is a threshold below which set cover cannot be approximated efficiently, unless NP has slightly superpolynomial time algorithms. This closes the gap (up to low-order terms) between the ratio of approximation achievable by the greedy alogorithm (which is (1 - o(1)) ln n), and provious results of Lund and Yanakakis, that showed hardness of approximation within a ratio of log2 n/2&sime;0.72 ln n. For max k-cover, we show an approximation threshold of (1 - 1/e)(up to low-order terms), under assumption that P&ne;NP .
Fundamentals of MCM Testing and Design-for-Testability
Authors: Yervant Zorian
Venue: Journal of Electronic Testing: Theory and Applications (1997)

Products motivated by performance-driven and/or density-driven goals often use Multi-Chip Module (MCM) technology, even though it still faces several challenging problems that need to be resolved before it becomes a widely adopted technology. Among its most challenging problems is achieving acceptable MCM assembly yields while meeting quality requirements. This problem can be significantly reduced by adopting adequate MCM test strategies: to guarantee the quality of incoming bare (unpackaged) dies prior to module assembly; to ensure the structural integrity and performance of assembled modules; and to help isolate the defective parts and apply the repair process.This paper describes today&lsquo;s MCM test problems and presents the corresponding test and design-for-testability (DFT) strategies used for bare dies, substrates, and assembled MCMs.
Finite-Dimensional Filters. Part II: Invariance Group Techniques
Authors: M. Cohende Lara
Venue: SIAM Journal on Control and Optimization (1997)

This two-part paper deals with necessary or sufficient conditions for the existence of finite-dimensional filters. In the first part, we set the problem and proposed a construction of finite-dimensional filters by the Wei--Norman technique. In this second part, we show how geometric-methods offer another approach that is more powerful, as we shall see. The invariance group of a parabolic equation is introduced and its action on initial data enhanced. This is applied to the problem of finite-dimensional realization of bilinear stochastic PDEs and further simplified by the introduction of a Riemannian framework. We end by an analysis of partially observed systems having finite-dimensional filters, with emphasis on the case of systems with correlated noise.
Linear Codes with Non-Uniform Error Correction Capability
Authors: Margaret Ann Bernard, Bhu Dev Sharma
Venue: Designs, Codes and Cryptography (1997)

This paper introduces a class of linear codes which are non-uniform error correcting, i.e. they have the capability of correcting different errors in different code words. A technique for specifying error characteristics in terms of algebraic inequalities, rather than the traditional spheres of radius e, is used. A construction is given for deriving these codes from known linear block codes. This is accomplished by a new method called parity sectioned reduction. In this method, the parity check matrix of a uniform error correcting linear code is reduced by dropping some rows and columns and the error range inequalities are modified.
Normal Rational Curves Over Prime Fields
Authors: L. Storme
Venue: Designs, Codes and Cryptography (1997)

It is shown that in the projective spaces PG(n,p),p prime, 2 \leq n \leq p-2, the normal rational curves are the only (p+1)-arcs fixed by a projective group G isomorphic to PSL(2,p).
Network Competition and the Timing of Commercials
Authors: Fangruo Chen, Yu-Sheng Zheng, Gil S. Epstein
Venue: Management Science (1998)

In a market with a small number of networks, the timing of the commercial breaks is a very important factor in determining the number of viewers facing a channel. Using a theoretical model and statistical analysis with empirical data from the four networks in the United States, we analyze the equilibrium achieved in this network monopolistic competition. Among other things, it is shown theoretically and empirically that in equilibrium all networks broadcast commercial breaks at the same time. As the ability to coordinate is not always possible, it is shown that, as the program progresses, the level of coordination decreases.
Layout driven re-synthesis for low power consumption LSIs
Authors: Masako Murofushi, Takashi Ishioka, Masami Murakata, Takashi Mitsuhashi
Venue: Proceedings of the 34th annual Design Automation Conference (1997)

A new technology re-mapping method named LDR (LayoutDriven Re-synthesis), which is applied after placement, is proposed.LDR executes re-mapping and re-placement simultaneouslyin order to minimize power consumption with placementinformation.High switching activity nets are concealed insidethe re-mapped cells or are shortened by re-placement in LDR.To estimate power consumption, LDR uses static power estimatorfor combinational circuits.LDR also calculates wirecapacitances accurately based on placement information toevaluate power.Experimental results show that 20% powerreduction compared with original circuits is performed by proposed method.
Bounds for the Componentwise Distance to the Nearest Singular Matrix
Authors: S. M. Rump
Venue: SIAM Journal on Matrix Analysis and Applications (1997)

The normwise distance of a matrix $A$ to the nearest singular matrix is well known to be equal to $\|A\|/{\rm cond}(A)$ for norms subordinate to a vector norm. However, there is no hope for finding a similar formula or even a simple algorithm for computing the componentwise distance to the nearest singular matrix for general matrices. This is because Poljak and Rohn [Math. Control Signals Systems, 6 (1993), pp. 1--9] showed that this is an NP-hard problem.Denote the minimum Bauer--Skeel condition number achievable by column scaling by $\kappa$. Demmel [SIAM J. Matrix Anal. Appl., 13 (1992), pp. 10--19] showed that $\kappa^{-1}$ is a lower bound for the com- ponentwise distance to the nearest singular matrix. In our paper we prove that $2.4 \cdot n^{1.7} \cdot \kappa^{-1}$ is an upper bound. This extends and proves a conjecture by Demmel and Higham (in the cited paper by Demmel). We give an explicit set of examples showing that such an upper bound cannot be better than $n \cdot \kappa^{-1}$. Asymptotically, we show that $n^{1+ \ln 2+\varepsilon} \cdot \kappa^{-1}$ is a valid upper bound.
A behaviorally-based methodology for modeling system specifications
Authors: Sigal Mathalone
Venue: ACM SIGSOFT Software Engineering Notes (1997)

The Behaviorally-Based Methodology (BBM), a methodology for modeling behaviorally-complex system requirements specifications, is introduced in this paper. The BBM provides guidelines for a Behaviorally-Based decomposition beginning at the first stage of system development, while placing the emphasis on system behavior and providing notations to represent this behavior. In Behaviorally-Based system modeling, all active services and system behavior at each instant are presented in one place (the relevant system state). Hence, problem domain information is more easily carried through the analysis phase allowing for a clear separation between system analysis and system design. In addition, inconsistencies in describing system behavior can be avoided more easily; where such problems occur they are detected and resolved with greater facility.The BBM is compared to more functional approaches, such as Hatley and Pirbhai's approach [1], highlighting the BBM's advantages. An experiment conducted in a graduate software engineering class is described. The experiment has shown that system modeling performance was significantly improved, in both accuracy and speed, when following the BBM. These design benefits of the BBM are then discussed and illustrated.
A Parallel Interior Point Method and Its Application to Facility Location Problems
Authors: Amal De Silva, David Abramson
Venue: Computational Optimization and Applications (1998)

We present a parallel interior point algorithm to solve block structured linear programs. This algorithm can solve block diagonal linear programs with both side constraints (common rows) and side variables (common columns). The performance of the algorithm is investigated on uncapacitated, capacitated and stochastic facility location problems. The facility location problems are formulated as mixed integer linear programs. Each subproblem of the branch and bound phase of the MIP is solved using the parallel interior point method. We compare the total time taken by the parallel interior point method with the simplex method to solve the complete problems, as well as the various costs of reoptimisation of the non-root nodes of the branch and bound. Computational results on two parallel computers (Fujitsu AP1000 and IBM SP2) are also presented in this paper.
Boolean Circuits, Tensor Ranks, and Communication Complexity
Authors: Pavel Pudlák, Vojtech Rödl, Jirí Sgall
Venue: SIAM Journal on Computing (1997)

We investigate two methods for proving lower bounds on the size of small-depth circuits, namely the approaches based on multiparty communication games and algebraic characterizations extending the concepts of the tensor rank and rigidity of matrices. Our methods are combinatorial, but we think that our main contribution concerns the algebraic concepts used in this area (tensor ranks and rigidity). Our main results are following.(i) An $o(n)$-bit protocol for a communication game for computing shifts, which also gives an upper bound of $o(n^2)$ on the contact rank of the tensor of multiplication of polynomials; this disproves some earlier conjectures. A related probabilistic construction gives an $o(n)$ upper bound for computing all permutations and an $O(n\log\log n)$ upper bound on the communication complexity of pointer jumping with permutations. (ii) A lower bound on certain restricted circuits of depth 2 which are related to the problem of proving a superlinear lower bound on the size of logarithmic-depth circuits; this bound has interpretations both as a lower bound on the rigidity of the tensor of multiplication of polynomials and as a lower bound on the communication needed to compute the shift function in a restricted model. (iii) An upper bound on Boolean circuits of depth 2 for computing shifts and, more generally, all permutations; this shows that such circuits are more efficient than the model based on sending bits along vertex-disjoint paths.
Design and evaluation of a DRAM-based shared memory ATM switch
Authors: Tzi-cker Chiueh, Srinidhi Varadarajan
Venue: Proceedings of the 1997 ACM SIGMETRICS international conference on Measurement and modeling of computer systems (1997)

Beluga is a single-chip switch architecture specifically targeted at local area ATM networks, and it features three architectural innovations. First, an interconnection hierarchy composed of multiple switching fabrics is built into the chip to provide both low-latency cell transfer when the traffic is light and low cell drop rate under heavy load. Secondly, to improve silicon efficiency, Beluga is based on shared memory architecture, and the buffers are implemented using DRAM rather than SRAM technology. Heavy interleaving and selective invalidation are used to address long latency and periodic refreshing problems, respectively. Thirdly, Beluga supports multicast with minimal physical bit replication. It also separates support for unicast and multicast cells to optimize for the common case, where multicast cells occur infrequently. This paper describes the design details of Beluga and the results of a comprehensive simulation study to quantify the performance impact of each of its architectural features. The most important result from this research is that DRAM-based buffer implementation significantly reduces the cell-drop rate during heavy while exhibiting almost identical cell latency to SRAM-based implementation during light load. Therefore, we believe DRAM makes an attractive alternative for switch buffer implementation, especially for single-chip architecture such as Beluga.
Genetic algorithms: APL2 implementation and a real life application
Authors: Alexander O. Skomorokhov
Venue: ACM SIGAPL APL Quote Quad (1996)

This paper describes an application oriented approach to the genetic-algorithm technique. The software is implemented in APL2 and exploits availability of user defined operators and separation of general purpose and problem specific code. The paper presents results of applying genetic algorithms to solve real life problems of simulation and predicting input order streams for a large consulting and service company. In an extended version of the paper, implementation of a GUI interface to genetic algorithm software in APL2 for OS/2 is described.
Distribution of Marcaine in an in vitro model of the subarachnoid space conforming to actual spinal column geometries
Authors: Dirk S. De Wachter, Pascal R. Verdonck, Ronny F. Verhoeven
Venue: Technology and Health Care (1997)

To study factors influencing the distribution of local anaesthetics in the subarachnoid space, an in vitro model is constructed which takes into account the natural curvature of the spinal column and the volume occupation of spinal cord and nerve fibres to resemble the in vivo situation. Three Marcaine &reg; solutions of different baricity (1003, 1008, 1030 kg/m^3) are injected with a 22 G, a 27 G Quincke point needle and a 18 G multiport catheter into three models of non-pathological spinal columns with injection flow speeds of 0.6, 0.2 or 0.1 ml/s. Methylene blue is added for visual and qualitative assessment of drug distribution. Baricity is the main actor in the spreading of the drug solution. For all other variables, no significant difference is found after ten minutes, though the initial distribution may differ according to the geometry used. A hypobaric solution yields a remarked difference between fast and slower injections. The position of the catheter should be controlled.
An application of L systems to local microcode synthesis
Authors: F. Mavaddat, M. Mahmood, M. H. M. Cheng
Venue: Proceedings of the 23rd annual workshop and symposium on Microprogramming and microarchitecture (1990)

In this paper we present a formal language model of register-transfer (RT) design, and apply the model to local microcode synthesis. We transform an RT design's data-path to a DTOL system&mdash;a parallel formal grammar&mdash;and formulate the design of the control part as a parsing problem of the corresponding DTOL language. The initial specification is based on the proposed SDC model of register-transfer design. We discuss the necessary steps for transforming a legal SDC-based data-path to its equivalent DTOL system. We then propose an efficient, goal-oriented, search algorithm to parse a behavioral specification, and use this method to generate the microcode for the corresponding control part. We close by presenting two examples, using a benchmark data-path.
Compiling: a high-level introduction using Scheme
Authors: Christopher T. Haynes
Venue: ACM SIGCSE Bulletin (1997)

Traditional compilation courses use formal methods for parsing, but treat the more important semantic aspects informally. We present a one semester course in which compiler development is reduced to a number of transformation steps, each of which is formally specified, easily tested, and clearly motivated by semantic considerations. The source language is substantial (essentially the host language of the compiler) and the target is a popular RISC architecture.