ppxscal/embedding_network huggingface dataset:
A Fuzzy Problem of Multiparametric Choice of Optimal Solutions
Authors: I. V. Sergienko, I. N. Parasyuk, M. F. Kaspshitskaya
Venue: Cybernetics and Systems Analysis (2003)

The problem of optimal choice of a set of parameters is considered in fuzzy formulation. The so-called S-functions (or bell-shaped functions) are used for interpretation of fuzziness. A method of defuzzification of linguistic variables is proposed. Some results on stability are given.
The Conundrum of Distributed Computing
Authors: Alfred Z. Spector
Venue: Proceedings of the 23rd International Conference on Distributed Computing Systems (2003)

We have been engineering distributed computingarchitectures according to roughly the same formulasfor quite a number of years; yet each time, the endresult has had greater complexity. Modern distributedcomputing architectures have an enormous number ofprotocols, layers, configuration parameters, APIs, etc.While we seem to be proceeding in the right directionin functionality, the growth in complexity is perplexingand has the potential to slow progress in research andin commercial use. I'll discuss this topic and proposeareas of research that are relevant to resolving theissue.
Quality of Electronic Design: From Architectural Level to Test Coverage
Authors: O. P. Dias, J. Semião, M. B. Santos, I. M. Teixeira, J. P. Teixeira
Venue: Proceedings of the 1st International Symposium on Quality of Electronic Design (2000)

The purpose of this paper is to present a design methodology that complements existing methodologies by addressing the upper and the lower extremes of the design flow. The aim of the methodology is to increase design and product quality. At system level, emphasis is given to architecture generation, reconfiguration and quality assessment. Quality metrics and criteria, focused on design and test issues, are used for the purpose. At physical level, a Defect-Oriented Test (DOT) approach and test reuse is the basis of the methodology to estimate test effectiveness, or Defects Coverage. Tools, that implemented the methodology, are presented. Results are shown for a public domain PIC processor, used as a SOC embedded core.
LVis - Digital Library Visualizer
Venue: Proceedings of the International Conference on Information Visualisation (2000)

LVis is a joint project aiming at the 2-D and 3-D visualization of search results derived from user queries of digital library collections. This paper gives an overview of the intent of the project, the data mining techniques applied, the visualization metaphors used, and the usability studies planned and undertaken to date.
Grammar-based compression of interpreted code
Authors: William S. Evans, Christopher W. Fraser
Venue: Communications of the ACM (2003)

Automatically designing and implementing compact interpretable bytecodes.
Execution of TILCO Temporal Logic Specifications
Authors: Pierfrancesco Bellini, Andrea Giotti, Paolo Nesi
Venue: Proceedings of the Eighth International Conference on Engineering of Complex Computer Systems (2002)

Temporal logics are able to describe temporal constraintsamongst events and actions, as invariance, precedence,periodicity, repeated occurrences, liveness andsafety conditions. They are typically used to verify propertiesin the requirements analysis, in order to describe highlevel system behaviour and for test case generation. In somecases, temporal logics are used for the specification of realtime systems and for their execution. In this paper, a modeland algorithm to execute specifications in TILCO first ordertemporal logic are presented. To this end, the TILCO specificationsare translated into a model which can be directlyexecuted by a specific inferential engine. An example is alsopresented.Index terms: formal specification language, first orderlogic, temporal interval logic, real-time systems, temporaloperators.
On Realization of Fault-Tolerant Fuzzy Controllers
Authors: Naotake Kamiura, Masashi Tomita, Teijiro Isokawa, Nobuyuki Matsui
Venue: Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW) (2000)

In this paper, we propose concurrent compensation for fuzzy controllers. The concurrent fault location is executed by observing each sum of two degrees of adjacent membership functions. Instead of the faulty degree in the antecedent part, we employ either zero or degree of next membership function to the faulty one at the easily calculated abscissa. To compensate the faults in the consequent part, we shift several fuzzy variables, and infer with the membership functions representing the variables after shifts. The amount of shifting the variables is determined systematically. Experimental results show that our method is valid for any non-redundant single stuck-at fault both in each of antecedent parts and in the consequent part.
Metric-Based Analysis of Context-Free Grammars
Authors: James F. Power, Brian A. Malloy
Venue: Proceedings of the 8th International Workshop on Program Comprehension (2000)

Recent advances in software engineering have produced a variety of well-established approaches, formalisms and techniques to facilitate the construction of large-scale applications. Developers interested in the construction of robust, extensible software that is easy to maintain should expect to deploy a range of these techniques, as appropriate to the task.In this paper, we provide a foundation for the application of established software metrics to the measurement of context-free grammars. The usual application of software metrics is to program code; we provide a mapping that allows these metrics to be applied to grammars. This allows us to interpret six software engineering metrics in a grammatical context, including McCabe's complexity metric and Fenton's impurity metric.We have designed and implemented a tool to automatically compute the six metrics; as a case study, we use these six metrics to measure some of the properties of grammars for the Oberon, ISO C, ISO C++ and Java programming languages. We believe that the techniques that we have developed can be applied to estimating the difficulty of designing, implementing, testing and maintaining parsers for large grammars.
Enhancing Write I/O Performance of Disk Array RM2 Tolerating Double Disk Failures
Authors: Young Jin Nam, Dae-Woong Kim, Tae-Young Choe, Chanik Park
Venue: Proceedings of the 2002 International Conference on Parallel Processing (2002)

With a large number of internal disks and the rapid growth of disk capacity, storage systems become more susceptible to double disk failures. Thus, the need for such reliable storage systems as RAID6 is expected to gain in importance. However, RAID6 architectures such as RM2, P+Q, EVEN-ODD, and DATUM traditionally suffer from a low write I/O performance caused by updating two distinctive parity data associated with user data. To over-comesuch a low write I/O performance, we propose an enhanced RM2 architecture which combines RM2, one of the well-known RAID6 architectures, with a Lazy Parity Update (LPU) technique. Extensive performance evaluations reveal that the write I/O performance of the proposed architecture is about two times higher than that of RM2 under various I/O workloads with little degradation in reliability.
A Distributed Path Algorithm and Its Correctness Proof
Authors: David D. Wright, Fred B. Schneider
Venue:  (1983)

A distributed program is developed to allow a process in a network to determine a path from itself to any other process, assuming that the topology of the entire network is not known to any process and that each process knows only the names of the processes to which it is directly connected. The solution, written in CSP, is proved correct and deadlock-free.
Logical Processes in Humans and Computers: Theory and Research in Psychology and Artificial Intelligence
Authors: Morton Wagman
Venue:  (2003)

:This volume presents a criticial anaylysis of current theory and research in the psychological and computational sciences diected toward an elucidation of logical processes and structures ranging from the domain of human reasoning heuristics to the domain of systemic scientific reasoning. The ACM Portal is published by the Association for Computing Machinery. Copyright © 2010 ACM, Inc. Terms of Usage Privacy Policy Code of Ethics Contact Us Useful downloads: Adobe Acrobat QuickTime Windows Media Player Real Player
An Efficient and Fast Parallel Connected Component Algorithm
Authors: Robert Wagner, Yijie Han
Venue:  (1986)

A parallel algorithm for computing the connected components of undirected graphs is presented. Shared memory computation models are assumed. For a graph of $e$ edges and $n$ nodes, the time complexity of the algorithm is $0( \frac {e} {p} + \frac {n~logn} {p} + log ^ 2 n)$ with $p$ processors. This algorithm allows concurrent read but not concurrent write. The algorithm can be further refined to yield time complexity $0 ( \frac {H(e,n,p)} {p} + \frac {n~logn} {p~ log 2 \lceil \frac {n} {p} \rceil} + log ^ 2 n)$, where $H(e,n,p)$ is very close to $0(e)$. These results show that linear speedup can be obtained for up to $p \leq \frac {e} {log ^ 2 n} $ processors when $e \geq n~logn$. Even with very sparse graphs $e \geq n~ log ^ {(*)}n$, where $log ^ {(1)}n = logn$, $log ^ {(i)} n = log(log ^ {(i-1)} n )$ and $log ^ {(*)} n = log ^ {(i)} n$ for some $i$, linear speedup can still be achieved with up to $p \leq n ^ \epsilon $ processors, $0 \leq \epsilon > 1$. Our results can be further improved if a more efficient integer sorting algorithm is available.
Analog Design with Verilog-A
Authors: Ira Miller, Dan FitzPatrick, Ramana Aisola
Venue: Proceedings of the 1997 IEEE International Verilog HDL Conference (IVC '97) (1997)

Verilog-A is a language to describe analog behavior. It is an extension to the IEEE 1364 Verilog Hardware Description Language (HDL) specification. A complete definition of the Verilog-A hardware description language, as proposed by the Analog Technical Subcommittee of Open Verilog International (OVI), can be found in the Verilog-A Language Reference Manual (LRM). An LRM to describe mixed signal, Verilog-AMS, is in development and will be available in 1997. Several Verilog-A prototype simulators are now in development and three are currently available from commercial CAD tool providers. This paper contains information about Verilog-A, the motivation to develop it, some thoughts on model development, and an example of a Verilog-A module.
Establishing a framework for comparative analysis of genome sequences
Authors: A. K. Bansal
Venue: Proceedings of the First International Symposium on Intelligence in Neural and Biological Systems (INBS'95) (1995)

This paper describes a framework and a high level language tool for comparative analysis of genome sequence alignment. The framework integrates the information derived from multiple sequence alignment and phylogeny to derive new properties about homologous sequences. Multiple sequence alignments are treated as an abstract data type. Abstract operations have been described to manipulate a multiple sequence alignment, and to derive mutation related information from a phylogenetic tree by superimposing parsimony. The framework has been applied to derive constrained columns which exhibit evolutionary pressure to preserve a common property in a column despite mutation. A Prolog tool based on the the framework has been implemented and demonstrated on alignments containing 3000 sequences and 3904 columns.
Combined Floorplanning and Partitioning Heuristics for Mixed Standard Cell and Macro Block Layout
Authors: Jitendra Apte, Gershon Kedem
Venue:  (1990)

Efficient heuristic algorithms for the layout of large gate level netlists using standard cells, gate arrays and sea-of-gates are now available. Also available are techniques for module generation of large regular layout structures like memory. We look at the problem of combining these two layout styles. The aim of our work is to be able to automatically generate area efficient layouts for netlists containing a mixture of a large number (10,000 or more) of small gates (standard cells) and a few (10 to 20) large macro blocks. These macro blocks may be laid out by hand or generated by module generators. We call this the layout automation (LA) problem. We present here an efficient heuristic algorithm for solving the LA problem. The algorithm employs a combined floorplanning, a partioning and global routing strategy. We illustrate two important costs that need to be minimized simultaneously in order to obtain good layouts. They are the white space cost and the wiring cost. Our algorithm effectively minimizes these by covering up the white space in floorplans using the standard cells as a ``filling''''. Our models are general enough to accommodate gate arrays, sea-of-gates or other layout methodologies instead of standard cells.
On a Global Optimization Problem in the Study of Information Discrepancy
Authors: Weiwu Fang
Venue:  (1997)

A nonlinear function has been introduced for indexing the disagreement degree of a group of judgment matrices (in FW, 1994). It has many good properties and may be applied in decision making and information process. In this paper, we will discuss a global optimization problem concerned with the global maximum of this function which is constrained on some sets of matrices. Because the size of matrix groups in the problem is arbitrary and the number of local maximum solutions increases exponentially, numerical methods are not suitable and formalized results are desired for the problem. By an approach somewhat similar to the branch and bounded method, we have obtained some formulae on global maximums, a sufficient and necessary condition of the function''s taking the maximums, and its some maximum solution sets.
The Sliding Window Protocol Revisited
Authors: Jan L. A. Van de Snepscheut
Venue:  (1991)

We give a correctness proof of the sliding window protocol. Both safety and liveness properties are addressed. We show how faulty channels can be represented as nondeterministic programs. The correctness proof is given as a sequence of correctness-preserving transformations of a sequential program that satisfies the original specification, with the exception that it does not have any faulty channels. We work as long as possible with a sequential program, although the transformation steps are guided by the aim of going to a distributed program. The final transformation steps consist in distributing the actions of the sequential program over a number of processes.
A Framework for Developing Reactive Information Agents with Heterogeneous Communication Capabilities
Authors: Dimitris Vyzovitis, Keith L. Clark
Venue: Proceedings of the Fifth International Symposium on Autonomous Decentralized Systems (2001)

In this paper we present a generic framework for developing complex distributed applications in open information environments, using reactive agents as basic building blocks. We address agent architecture and collaboration issues by introducing a minimal agent architecture, the Reactive Information Agent, and adopting a flexible asynchronous communication infrastructure, the Inter-Agent Communication Model. Finally, we present an implementation of the framework which allows agent designers to rapidly develop multi-agent systems based on simple heterogeneous computational elements, which are mobile, adaptive, reflective, and dynamically reconfigurable during the system lifetime.
Moderate Deviations for Queues in Critical Loading
Authors: Anatolii A. Puhalskii
Venue:  (1998)

We establish logarithmic asymptotics of moderate deviations for the processes of queue length and waiting times in single server queues and open queueing networks in critical loading. Our results complement earlier heavy-traffic approximation results.
Modeling Adaptive Organizations
Authors: Rémy Foisel, Vincent Chevrier, Jean-Paul Haton
Venue: Proceedings of the 3rd International Conference on Multi Agent Systems (1998)

We present in this paper a model based on the notion of interaction to build adaptive organizations. Interaction models are used to provide an initial organizational structure to the system. Local assessment capacities are added to make agents adapt the structure according to their requirements. This model is used to build a multi-agent system with global coherent behavior through the use of organizational structure and with abilities to make the system adapt its structure when it is not locally convenient.
Proving termination of logic programs with delay declarations
Authors: Elena Marchiori, Frank J.M. Teusink
Venue:  (1996)

In this paper we propose a method for proving termination of logic programs with delay declarations. The method is based on the notion of recurrent logic program, which is used to prove programs terminating wrt an arbitrary selection rule. Most importantly, we use the notion of bound query (as proposed by M. Bezem) in the definition of cover, a new notion which forms the kernel of our approach. We introduce the class of delay recurrent programs and prove that programs in this class terminate for all local delay selection rules, provided that the delay conditions imply boundedness. The corresponding method can be also used to transform a logic program into a terminating logic program with delay declarations.
Run-Time Adaptation for Grid Environments
Authors: Ammar H. Alhusaini, C. S. Raghavendra, Viktor K. Prasanna
Venue: Proceedings of the 10th Heterogeneous Computing Workshop â"" HCW 2001 (Workshop 1) - Volume 2 (2001)

In this paper, we study a general mapping problem where a set of independent tasks compete for the shared resources of a Grid environment. Tasks have resource co-allocationrequirements. Each task requires multiple and different resources to be allocated simultaneously. At run-time, a task may release its allocated resources during its execution and before its completion time. Our objective is to minimize the overall schedule length of all submitted tasks while satisfying all resource sharing constraints among them. We develop a two-phase mapping approach for solving this problem. The first phase of our approach is off-line planning phase where a schedule plan, which gives a scheduling order and resource assignments of tasks, is generated at compile-time. The second phase is run-time adaptationphase. The goal of the second phase is to improve the performance of the schedule plan by adapting to run-time changes such as the early release of resources and the variationin computation and communication costs. Adaptation may involve changing the scheduling order and resource assignments of the original schedule plan. Our experimental results demonstrate the effectiveness of our approach compared to a baseline algorithm that performs no adaptation at run-time and to a dynamic algorithm that performs no planning at compile-time. Our two-phase mapping approach outperforms both algorithms by up to 20% with respect to the overall schedule length.
A Unified Model for Performance and Reliability of Fault-Tolerant/Multi-Mode Systems
Authors: G V Kulkarni, Nicola,  V, S K Trivedi
Venue:  (1984)

This paper unifies different models and relates different performance and reliability measures that have been proposed for the analysis of fault-tolerant computer systems. We model the changes in the structure of the system due to different events (such as degradation, failure or repair) as a continuous time Markov chain. In particular we consider the execution of a job on such a computer system where a service rate (or a reward rate) is associated with each structure-state. We allow different types of service-preemption interactions due to changes in the structure-state of the system. We derive the distribution of the completion time of a given job. Although the developed techniques are suitable for the analysis of complex systems, we demonstrate their use through a simple switching server example.
Build Your Own PC Home Entertainment System, 1 edition
Authors: Brian Underdahl
Venue:  (2003)

:Create a PC-based center that delivers endless excitement and entertainment to your home. Choose the appropriate case, motherboard, processor, and memory to make your entertainment system sing, then select the operating system and additional software that will best enhance your PC performance. Inside, you'll find fully illustrated instructions on putting everything together, including operating and troubleshooting tips. From TV tuner and video card options to amplification recommendations, Build Your Own PC Home Entertainment System delivers a complete guide to the parts and accessories you'll need to build your dream home entertainment system.
Coordination of heterogeneous distributed cooperative constraint solving
Authors: Farhad Arbab, Eric B.G. Monfroy
Venue:  (1998)

In this paper we argue for an alternative way of designing cooperative constraint solver systems using a control-oriented coordination language. The idea is to take advantage of the coordination features of Manifold for improving the constraint solver collaboration language of Bali. We demonstrate the validity of our ideas by presenting the advantages of such a realization and its (practical as well as conceptual) improvements of constraint solving. We are convinced that cooperative constraint solving is intrinsically linked to coordination, and that coordination languages, and Manifold in particular, open new horizons for systems like Bali.
The Fast Fourier Transform on Hypercube Parallel Computers
Authors: Clare Y Chu
Venue:  (1987)

The Fast Fourier Transform appears frequently in scientific computing. Therefore it is desirable to implement it efficiently on parallel computers. In this thesis, we investigate several different aspects of parallel Fast Fourier Transform implementation techniques for distributed-memory message-passing systems such as hypercube multiprocessors. We describe various Fast Fourier Transform algorithms using a matrix notation. An error analysis is presented that considers the effect of different methods used in the computation of the Fourier Transform coefficients as well as accumulated roundoff. New implementations of one and two-dimensional Fast Fourier Transforms are presented along with comparisons with existing methods. New algorithms for symmetric transforms are also developed and the results show excellent speedup when implemented on the Intel iPSC hypercube. The ACM Portal is published by the Association for Computing Machinery. Copyright © 2010 ACM, Inc. Terms of Usage Privacy Policy Code of Ethics Contact Us Useful downloads: Adobe Acrobat QuickTime Windows Media Player Real Player
Design of ESD Protection Device Using Statistical Methods
Authors: H. Kawashima
Venue: Proceedings of the 3rd International Symposium on Quality Electronic Design (2002)

This article describes ESD protection device design to minimize its area Ap while maintaining the breakdown voltage VESD. Hypothesis tests were performed to find the applied serge condition and to select control factors for the design-of-experiments (DOE). Also, TCAD was used to estimate VESD. An optimum device structure, where salicide block was employed, was found using statistical methods and TCAD.
Effects of Checkpointing and Queueing on Program Performance
Authors: G V Kulkarni, F V Nicola, S K Trivedi
Venue:  (1987)

Checkpointing is a well-known procedure to reduce the execution time of programs in the presence of failures. If a failure occurs, the work done on the program since the last checkpoint is lost and therefore must be repeated in order to continue the correct execution of the program. A new model is developed for the analysis of the distribution of the program execution time. The questions of whether checkpointing is beneficial and the optimal checkpointing rate are addressed. A queueing analysis is performed to obtain the distribution of the response time of a program in a queueing environment.