ppxscal/embedding_network huggingface dataset:
An APL rule-based system architecture for image interpretation strategies
Authors: P. Bottoni, M. Protti, P. Mussio
Venue: Proceedings of the international conference on APL '91 (1991)

APL is both a language of choice for image processing and image description tasks, and a language for artificial intelligence applications, typically expert systems. The paper presents the architecture of an APL rule-based system for realizing description synthesis strategies i.e., sequences of actions which allow the evaluation and interpretation of the properties of structures detected in an image. Descriptions of images are stored in a data structure which is formally presented in APL2 syntax. Describing an image often requires that reflective actions be taken i.e., actions in which the system examines the state of the computation and its internal state to select the next action to be executed. It is shown how APL provides all the features needed to implement a reflective mechanism through the use of metarules of the same format as rules.
Tolerating data access latency with register preloading
Authors: William Y. Chen, Scott A. Mahlke, Wen-mei W. Hwu, Tokuzo Kiyohara, Pohua P. Chang
Venue: Proceedings of the 6th international conference on Supercomputing (1992)

By exploiting fine grain parallelism, superscalar processors can potentially increase the performance of future supercomputers. However, supercomputers typically have a long access delay to their first level memory which can severely restrict the performance of superscalar processors. Compilers attempt to move load instructions far enough ahead to hide this latency. However, conventional movement of load instructions is limited by data dependence analysis. This paper introduces a simple hardware scheme, referred to as preload register update, to allow the compiler to move load instructions even in the presence of inconclusive data dependence analysis results. Preload register update keeps the load destination registers coherent when load instructions are moved past store instructions that reference the same location. With this addition, superscalar processors can more effectively tolerate longer data access latencies.
Call and connection management: making desktop conferencing systems a real service
Authors: S. R. Ahuja, J. R. Ensor
Venue: ACM SIGCOMM Computer Communication Review (1992)

This is an extended abstract of a paper presented to Multimedia '92. A demonstration ISDN based multipoint multimedia conferencing system is described, together with a proposed protocol architecture for such applications.
SRI's experience with the ATIS evaluation
Authors: Robert Moore, Douglas Appelt, John Bear, Mary Dalrymple, Douglas Moran
Venue: Proceedings of the workshop on Speech and Natural Language (1990)

SRI International participated in the June 1990 Air Travel Information System (ATIS) natural-language evaluation. This report briefly describes the system that SRI used in the evaluation, analyzes SRI's results, and makes some recommendations for changes in the database structure and data collection system to be used for future ATIS evaluations.
Fast Givens goes slow in MATLAB
Authors: Alan Genz, Zongli Lin, Charles Jones, Dali Luo, Thorsten Prenzel
Venue: ACM SIGNUM Newsletter (1991)

Numerical results show that a straightforward implementation in MATLAB of an algorithm for the Fast Givens QR Factorization of an m x n matrix takes more time than an implementation of an algorithm that uses ordinary Givens transformations. Results of timing experiments for various operations in MATLAB are reported and models are constructed to explain why the standard theoretical analysis based on flop counts does not account for the actual times for the algorithms.
Efficient, high-performance algorithms for N-Best search
Authors: Richard Schwartz, Steve Austin
Venue: Proceedings of the workshop on Speech and Natural Language (1990)

We present two efficient search algorithms for real-time spoken language systems. The first called the Word-Dependent N-Best algorithm is an improved algorithm for finding the top <i>N</i> sentence hypotheses. The new algorithm is shown to perform as well as the Exact Sentence-Dependent algorithm presented previously but with an order of magnitude less computation. The second algorithm is a fast match scheme for continuous speech recognition called the Forward-Backward Search. This algorithm, which is directly motivated by the Baum-Welch Forward-Backward training algorithm, has been shown to reduce the computation of a time-synchronous beam search by a factor of 40 with no additional search errors.
An object-oriented specification and its generation for compiler
Authors: Pei-Chi Wu, Feng-Jian Wang, Kai-Ru Young
Venue: Proceedings of the 1992 ACM annual conference on Communications (1992)

In this paper, an object-oriented approach to compiler specification is presented. The syntax symbols are treated as templates which instantiate nodes of parse trees to perform semantics analysis. The compiler generating techniques, specifically for this approach, are also presented in brief.
Efficient implementation of a BDD package
Authors: Karl S. Brace, Richard L. Rudell, Randal E. Bryant
Venue: Proceedings of the 27th ACM/IEEE Design Automation Conference (1991)

Efficient manipulation of Boolean functions is an important component of many computer-aided design tasks. This paper describes a package for manipulating Boolean functions based on the reduced, ordered, binary decision diagram (ROBDD) representation. The package is based on an efficient implementation of the if-then-else (ITE) operator. A hash table is used to maintain a strong canonical form in the ROBDD, and memory use is improved by merging the hash table and the ROBDD into a hybrid data structure. A memory function for the recursive ITE algorithm is implemented using a hash-based cache to decrease memory use. Memory function efficiency is improved by using rules that detect when equivalent functions are computed. The usefulness of the package is enhanced by an automatic and low-cost scheme for recycling memory. Experimental results are given to demonstrate why various implementation trade-offs were made. These results indicate that the package described here is significantly faster and more memory-efficient than other ROBDD implementations described in the literature.
Extending compound assignments for C++
Authors: T. B. Dinesh
Venue: ACM SIGPLAN OOPS Messenger (1992)

Compound assignments have been created with efficiency, for handling a subset of things that simple assignments can do. This gain in efficiency is due to the interpretation of the compound assignment as a message that modifies self (&ldquo;this&rdquo;). However, C++ does not extend the same interpretation of compound assignments to user defined types. In this paper, we illustrate how the notion of compound assignments is natural in C++, how it can be implemented and indicate that the resulting gain in efficiency is akin to the gain in efficiency obtained by optimizing C compilers that translate complex expressions to simple ones that use compound assignments.
The Analysis of the Faulty Behavior of Synchronous Neural Networks
Authors: Lee A. Belfore,  II, Barry W. Johnson
Venue: IEEE Transactions on Computers (1991)

A means for analyzing the faulty behavior of neural networks is presented. Using an analogy between statistical physics and neural networks, a method for assessing the performance of a synchronous neural network model in the presence of faults is developed. Analytical predictions are computed using the statistical physics analogy and compared with the simulated behavior for two neuron models. An example of the analytical technique applied to an autoassociative memory is described.
PYRROS: static task scheduling and code generation for message passing multiprocessors
Authors: Tao Yang, Apostolos Gerasoulis
Venue: Proceedings of the 6th international conference on Supercomputing (1992)

We describe a parallel programming tool for scheduling static task graphs and generating the appropriate target code for message passing MIMD architectures. The computational complexity of the system is almost linear to the size of the task graph and preliminary experiments show performance comparable to the &ldquo;best&rdquo; hand-written programs.
A Partially Supervised Learning Algorithm for Linearly Separable Systems
Authors: S. J. Wan, S. K. M. Wong
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1992)

An important aspect of human learning is the ability to select effective samples to learn and utilize the experience to infer the outcomes of new events. This type of learning is characterized as partially supervised learning. A learning algorithm of this type is suggested for linearly separable systems. The algorithm selects a subset S from a finite set X of linearly separable vectors to construct a linear classifier that can correctly classify all the vectors in X. The sample set S is chosen without any prior knowledge of how the vectors in X-S are classified. The computational complexity of the algorithm is analyzed, and the lower bound on the size of the sample set is established.
MediaView: a general multimedia digital publication system
Authors: Richard L. Phillips
Venue: Communications of the ACM (1991)

MediaView is a multimedia digital publication system that was designed to be flexible and free from restrictions. It was also designed to take maximum advantage of the media-rich hardware and software capabilities of the NeXT [5] computer, especially the features of the NeXTdimension [17] subsystem. Rather than emphasize the work that is almost always paired with multimedia, presentation, MediaView emphasizes communication. The system does not tacitly impose the &ldquo;publisher's&rdquo; agenda on the reader, but structure and sequencing can be overlaid if appropriate. The result is a very general system&mdash;free of artificial structure and inconvenient metaphors.
HILITES: the information service for the world HCI community
Authors: Brian Shackel, James L. Alty, Peter Reid
Venue: ACM SIGCHI Bulletin (1992)

The Hci Information and LITerature Enquiry Service (HILITES) has been developed from two initiatives over the years, one being a series of research projects and the other a service development on a commercial basis. In this paper the user's needs for information services are discussed, and the developments leading to HILITES are reviewed. The facilities provided by HILITES are outlined, including the on-line database containing over 25,000 items of literature available for on-line search, the weekly accessions list and request service, the copy and/or loan service of hard copies to subscribers, and related special services. The latest development (November 1991) has been the release of the HILITES database on CD-ROM.
A short introduction to the ABC language
Authors: Steven Pemberton
Venue: ACM SIGPLAN Notices (1991)

This article gives a quick overview of the programming language ABC and its implementations, and gives a few examples of ABC programs, plus details of where you can find more information.
Automatic Synthesis of SARA Design Models from System Requirements
Authors: Kar-Wing Edward Lor, Daniel M. Berry
Venue: IEEE Transactions on Software Engineering (1991)

In this research in design automation, two views are employed as the requirements of a system-namely, the functional requirements and the operations concept. A requirement analyst uses data flow diagrams and system verification diagrams (SVDs) to represent the functional requirements and the operations concept, respectively. System Architect's Apprentice (SARA) is an environment-supported method for designing hardware and software systems. A knowledge-based system, called the design assistant, was built to help the system designer to transform requirements stated in one particular collection of design languages. The SVD requirement specification features and the SARA design models are reviewed. The knowledge-based tool for synthesizing a particular domain of SARA design from the requirements is described, and an example is given to illustrate this synthesis process. This example shows the rules used and how they are applied. An evaluation of the approach is given.
Fairness in processor scheduling in time sharing systems
Authors: S. Haldar, D. K. Subramanian
Venue: ACM SIGOPS Operating Systems Review (1991)

Loosely, fairness is the assurance of granting each request, from a set of requests, within a predetermined bounded time even though the request scheduling primitives are unfair or random. The fairness property has been studied, in solutions to the mutual exclusion problem, from theoretical point of view. Many fair solutions to the mutual exclusion problem have been proposed in recent years. This paper presents one illustration to show how the concepts of fairness could be incorporated in processor scheduling in time sharing systems. First, it looks at some shortcomings associated with the round robin scheduler used in the time sharing systems, and then presents a fair version of the round robin scheduler.
Efficient periodic execution of Ada tasks
Authors: Thomas J. Quiggle
Venue: Proceedings of the fourth international workshop on Real-time Ada issues (1990)

The Ada language has been faulted for not providing an efficient and reliable mechanism to support periodic execution of tasks. Formulations that rely on delay statements in each periodic task or on user-supplied dispatcher tasks are unreliable or inefficient. This paper presents a simple model based on periodic pseudo-interrupts. This model can be efficiently implemented within the confines of the 1983 Ada language standard.
Could it have been predicted?
Authors: Maurice V. Wilkes
Venue: Communications of the ACM (1991)

As everyone knows, the computer industry is passing through a period of great change. I was speaking recently to a senior executive in one of the large companies vigorously working to meet the developing situation. The question he posed was: &ldquo;Could it have been predicted?&rdquo;
Performing data flow analysis in parallel
Authors: Yong-fong Lee, Thomas J. Marlowe, Barbara G. Ryder
Venue: Proceedings of the 1990 ACM/IEEE conference on Supercomputing (1990)

We have designed a family of parallel data flow analysis algorithms for execution on a message-passing MIMD architecture, based on general-purpose, hybrid data flow analysis algorithms [22]. We have exploited the natural task partitioning of the hybrid algorithms and have explored a static mapping-dynamic scheduling strategy. Alternative mapping-scheduling choices and refinements of the flow graph condensation utilized are discussed. Our parallel hybrid algorithm family is illustrated on the Reaching Definitions problem, although parallel algorithms also exist for many interprocedural (e.g., Aliasing) and intraprocedural (e.g., Available Expressions) problems [20].
Expressiveness and complexity of restricted languages for complex objects
Authors: Stéphane Grumbach, Victor Vianu
Venue: Proceedings of the third international workshop on Database programming languages : bulk types persistent data: bulk types persistent data (1992)

Several means of bounding the complexity of queries in various languages for complex objects are considered. For calculus-based languages, we propose a notion of safety of queries wrt a complexity class, which limits the ranges of variables to domains computable from the input database with the specified complexity. We provide a syntactic notion of range restrictedness which is a counterpart to safety. Other means to bound complexity include using fixpoint operators to provide tractable recursion, and limiting the arity and set height of higher-order types. We consider several calculus-based and deductive languages with the above restrictions, and compare their expressive power.
Improved parallel integer sorting without concurrent writing
Authors: Susanne Albers, Torben Hagerup
Venue: Proceedings of the third annual ACM-SIAM symposium on Discrete algorithms (1992)

We show that n integers in the range 1..n can be stably sorted on an EREW PRAM using O((log n)1/2) time, O(n(log n)1/2(log log n)1/2) operations and O(n) space. In addition, we are able to stably sort n integers in the range 1..n on a deterministic CREW PRAM in O((log n)3/2) time with O(n(log n)1/2) operations and O(n) space and to stably sort n arbitrary integers on a randomized CREW PRAM within the same complexity bounds with high probability. In each case our algorithm is closer to optimality than all previous algorithms for the stated problem in the stated model, and our third result matches the operation count of the best known sequential algorithm. We also show that m integers in the range 1..m can be sorted in O((log n)2) time with O(n) operations on an EREW PRAM using a nonstandard word length of O(log n log log n log m) bits, thereby greatly improving the upper bound on the word length necessary to sort integers with a linear time-processor product, even sequentially. Our algorithms were inspired by, and in one case directly use, the fusion trees recently introduced by Fredman and Willard.
Asynchronous shared memory parallel computation (preliminary version)
Authors: Naomi Nishimura
Venue: ACM SIGARCH Computer Architecture News (1991)

The contributions of this paper are twofold. First, we outline criteria by which any model of asynchronous shared memory parallel computation can be judged. Previous models are considered with respect to these factors. Next, we introduce a new model, and show that this model fulfils all the listed requirements. We also analyze in our model the complexity of several fundamental parallel algorithms.
Benchmark Characterization
Authors: Thomas M. Conte, Wen-mei W. Hwu
Venue: Computer (1991)

An abstract system of benchmark characteristics that makes it possible, in the beginning of the design stage, to design with benchmark performance in mind is presented. The benchmark characteristics for a set of commonly used benchmarks are then shown. The benchmark set used includes some benchmarks from the Systems Performance Evaluation Cooperative. The SPEC programs are industry-standard applications that use specific inputs. Processor, memory-system, and operating-system characteristics are addressed.
MTOOL: a method for detecting memory bottlenecks
Authors: Aaron Goldberg, John Hennessy
Venue: ACM SIGMETRICS Performance Evaluation Review (1991)

This paper presents a new, relatively inexpensive method for detecting regions (e.g. loops and procedures) in a program where the memory hierarchy is performing poorly. By observing where actual measured execution time differs from the time predicted given a perfect memory system, we can isolate memory bottlenecks. MTOOL, an implementation of the approach aimed at applications programs running on MIPS-chip based workstations is described and results for some of the Perfect Club and SPEC benchmarks are summarized.
Fast Image Labeling Using Local Operators on Mesh-Connected Computers
Authors: Hussein M. Alnuweiri, V. K. Prasanna Kumar
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1991)

A new parallel algorithm is proposed for fat image labeling using local operators on image pixels. The algorithm can be implemented on an n*n mesh-connected computer such that, for any integer k in the range (1, log (2n)), the algorithm requires Theta (kn/sup 1/k/) bits of local memory per processor and takes Theta (kn) time. Bit-serial processors and communication links can be used without affecting the asymptotic time complexity of the algorithm. The time complexity of the algorithm has very small leading constant factors, which makes it superior to previous mesh computer labeling algorithms for most practical image sizes (e.g. up to 4096*4096 images). Furthermore, the algorithm is based on using stacks that can be realized using very fast shift registers within each processing element.
Architecture of an Array Processor Using a Nonlinear Skewing Scheme
Authors: De-Lei Lee
Venue: IEEE Transactions on Computers (1992)

The problem of constructing an array processor with N processing elements, N memories, and an interconnection network which provides conflict-free access and alignment of various N-vectors including rows, columns, diagonals, contiguous blocks, and distributed blocks of N*N arrays, where N is any even power of two, is discussed. The use of linear skewing schemes offers no solution to this problem. The solution developed makes use of a nonlinear skewing scheme. The solution leads to a simple, efficient array processor architecture. In particular, the memory organization requires O(log N) gates to generate memory addresses for any of the N-vectors simultaneously in O(1) time. The interconnection structure is able to accomplish data alignment for any of the N-vectors with a single pass through a network of O(N log N) gates. As the system uses the minimum number of memories, it allows both processing elements and memories to achieve the highest utilization possible.
Parsing the voyager domain using pearl
Authors: David M. Magerman, Mitchell P. Marcus
Venue: Proceedings of the workshop on Speech and Natural Language (1991)

This paper describes a natural language parsing algorithm for unrestricted text which uses a probability-based scoring function to select the "best," parse of a sentence according to a given grammar. The parser, <i>P</i>earl, is a time-asynchronous bottom-up chart parser with Earley-type top-down prediction which pursues the highest-scoring theory in the chart, where the score of a theory represents the extent to which the context of the sentence predicts that interpretation. This parser differs from previous attempts at stochastic parsers in that it uses a richer form of conditional probabilities based on context to predict likelihood. <i>P</i>earl also provides a framework for incorporating the results of previous work in part-of-speech assignment, unknown word models, and other probabilistic models of linguistic features into one parsing tool, interleaving these techniques instead of using the traditional pipeline architecture. In tests performed on the Voyager direction-finding domain, <i>P</i>earl has been successful at resolving part-of-speech ambiguity, determining categories for unknown words, and selecting correct parses first using a very loosely fitting covering grammar.
Automated generation of code using backtracking parsers for attribute grammars
Authors: Wolfgang Keller
Venue: ACM SIGPLAN Notices (1991)

Code generation with the Graham Glanville scheme can be improved, using backtracking parsers for attribute grammars. This eliminates semantic and syntactic blocking during code selection and guarantees the cheapest code possible, if desired. Multipass translation allows the use of nontrivial register allocation strategies. The code generator generator system BECC is a LALR(1) based backtracking parser generator for a derivate of S-attributed grammars which provides several interpreters that differ in their abilities and performance.
Semantic correctness of structural editing
Authors: Tadeusz Gruźlewski, Zbigniew Weiss
Venue: ACM SIGPLAN Notices (1991)

Typical structural editor provides for syntax correctness of an edited text. In this paper some problems are discussed that arise when the semantic analysis is to be included in the tasks of a structural editor. The solution to these problems, already implemented in Modelang editor, is presented. It is based on the concept of multistage editing operations and application of default values. Several examples are given to show how the editor should deal with basic Pascal constructs in order to preserve full semantic accuracy. Additionally, two solutions are proposed to the problem of name maintenance within the structural editor. Structural editing versus conditional compilation is also considered.