ppxscal/embedding_network huggingface dataset:
The Complex Representation of Algebraic Curves and Its Simple Exploitation for Pose Estimation and Invariant Recognition
Authors: Jean-Philippe Tarel, David B. Cooper
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (2000)

New representations are introduced for handling 2D algebraic curves (implicit polynomial curves) of arbitrary degree in the scope of computer vision applications. These representations permit fast, accurate pose-independent shape recognition under Euclidean transformations with a complete set of invariants, and fast accurate pose-estimation based on all the polynomial coefficients. The latter is accomplished by a new centering of a polynomial based on its coefficients, followed by rotation estimation by decomposing polynomial coefficient space into a union of orthogonal subspaces for which rotations within two-dimensional subspaces or identity transformations within one-dimensional subspaces result from rotations in $x,y$ measured-data space. Angles of these rotations in the two-dimensional coefficient subspaces are proportional to each other and are integer multiples of the rotation angle in the $x,y$ data space. By recasting this approach in terms of a complex variable, i.e., $x+iy=z$, and complex polynomial-coefficients, further conceptual and computational simplification results. Application to shape-based indexing into databases is presented to illustrate the usefulness and the robustness of the complex representation of algebraic curves.
A methodology for verifying memory access protocols in behavioral synthesis
Authors: Gernot Koch, Taewhan Kim, Reiner Genevriere
Venue: Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design (2000)

Memory is one of the most important components to be optimized in the several phases of the synthesis process. In behavioral synthesis, a memory is viewed as an abstract construct which hides the detail implementations of the memory. Consequently, for a vendor's memory, behavioral synthesis should create a clean model of the memory wrapper which abstracts the properties of the memory that are required to interface to the rest of the circuit. However, this wrapping process invariably demands the verification problem of the memory access protocols in order to be safely used in behavioral synthesis environment. In this paper, we propose a systematic methodology of verifying the correctness of the memory wrapper. Specifically, we analyze the complexity of the problem, and derive an effective solution which is not only practically efficient but also highly reliable. For designers who use memories as design components in behavioral synthesis, automating our solution shortens the verification time significantly in contrast of simulating memory accesses in the context of full design, which is a quite complex and time-consuming process, especially for designs with many memory access operations.
An interactive multimedia learning environment for VLSI built with COSMOS
Authors: Marios C. Angelides, Harry W. Agius
Venue: Computers Education (2002)

This paper presents Bigger Bits, an interactive multimedia learning environment that teaches students about VLSI within the context of computer electronics. The system was built with COSMOS (Content Oriented semantic Modelling Overlay Scheme), which is a modelling scheme that we developed for enabling the semantic content of multimedia to be used within interactive systems.
Using Interceptors to Enhance CORBA
Authors: Priya Narasimhan, Louise E. Moser, P. m. Melliar-Smith
Venue: Computer (1999)

The integration of distributed computing and the object model leads to distributed object computing, in which objects rather than processes are distributed across multiple computers. A well-established standard for distributed object computing is the Common Object Request Broker Architecture (CORBA). Previously, you would have had to create-- and enable the application to use-- the components that provide such additional capabilities. Using these components requires specialized knowledge and understanding of problems outside the application domain. With the advent of interceptors--non-application components that can alter application behavior--you can enhance CORBA applications at runtime with components whose operation is transparent to both the application and the CORBA framework, modifying application behavior without modifying the application or the CORBA framework.
Is This a Pattern?
Authors: Tiffany Winn, Paul Calder
Venue: IEEE Software (2002)

In the current climate, pattern is an often misused buzzword. However, there is no clear definition of patternness, perhaps because patterns do not lend themselves to prescriptive, formal definitions. The authors propose a set of characteristics that can be used as a test for patternness. Each characteristic in their test describes an essential aspect of a design pattern. Recognizing these characteristics will help software designers understand, use, and write better patterns.
Choice number of some complete multi-partite graphs
Authors: Hikoe Enomoto, Kyoji Ohba, Katsuhiro Ota, Junko Sakamoto
Venue: Discrete Mathematics (2002)

One of the authors has conjectured that every graph G with 2χ(G) + 1 or fewer vertices is χ(G)-choosable. Motivated by this, we investigate the choice numbers of some complete k-partite graphs of order slightly larger than 2k, and settle the conjecture for some special cases. We also present several complete multi-partite graphs whose choice numbers are not equal to their chromatic numbers.
Automated separation of touching grains in digital images of thin sections
Authors: E. H. van den Berg, A. G. C. A. Meesters, J. A. M. Kenter, W. Schlager
Venue: Computers Geosciences (2002)

The determination of textural properties of granular material with image analysis is generally troubled by the fact that touching grain sections merge into single features. Without separation of these touching grain sections, the textural properties derived from the images contain substantial bias. Existing methods for separating touching grains, like erosion-dilation cycles or watershed segmentation, are time-consuming and/or alter the textural properties of the grain sections analyzed. An alternative computer algorithm is presented to separate touching grain sections in binary images of granular material. The algorithm detects characteristic sharp contact wedges in the outline of touching grain sections and creates an intersection after checking if the angle of the contact wedge is smaller than a user-defined threshold value. The performance of the new algorithm is compared to that of the watershed segmentation method. The resulting grain-size distributions after applying automated separation techniques, were verified with the size distribution obtained with a laboratory laser particle sizer. The algorithm shows improved preservation of size and shape characteristics of the granular material over the watershed segmentation method.
Using Open Source for a Profitable Startup
Authors: David A. E. Wall
Venue: Computer (2001)

When money's scarce, open source software can help your new business launch without breaking your budget.
Deriving a Fault Architecture to Guide Testing
Authors: C. Stringfellow, A. Andrews
Venue: Software Quality Control (2002)

Defect analysis of software components can be used to guide testing, with the goal of focusing on parts of the software that were fault-prone in earlier releases or earlier life cycle phases, such as development. We replicate a study that adapted a reverse architecting technique using defect reports to derive fault architectures. A fault architecture determines and visualizes components that are fault-prone in their relationships with other components, as well as those that are locally fault-prone. Our case study uses defect data from three releases of a large medical record system to identify relationships among system components, based on whether they are involved in the same defect report.We investigate measures that assess the fault-proneness of components and component relationships. Component relationships are used to derive a fault architecture. The resulting fault architecture indicates what the most fault-prone relationships are in a release. We also apply the technique in a new way. Not only do we derive fault architectures for each release, we derive fault architectures for the development, system test and post release phases within each release. Comparing across releases, makes it possible to see whether some components are repeatedly in fault-prone relationships. Comparing across phases, makes it possible to see whether development fault architectures can be used to identify those parts of the software that need to be tested more. We validate our predictions using system test data from the same release. We also use the development and system test fault architectures to identify fault-prone components after release, and validate our predictions using post release data.
Metatools for Knowledge Acquisition
Authors: Henrik Eriksson, Mark Musen
Venue: IEEE Software (1993)

Four prototype metatools, Protege, Dots, Dash, and Spark, which researchers are using to experiment with the automatic generation of knowledge-acquisition tools, are discussed. Protege and Dots are stand-alone metatools; Dash and Spark are subsystems. Dash is part of Protege II, a design environment for knowledge-based systems. Spark is part of the Spark, Burn, and Firefighter framework for the design of application systems. The two stand-alone tools, their environments, and their subsystems are compared. Protege demonstrates how one can instantiate knowledge-acquisition tools from a description of a problem-solving method. Dots, on the other hand, lets one design knowledge-acquisition tools for many applications. Spark, Burn, and Firefighter are similar to Protege II in that they emphasize developing problem-solving methods from reusable components, although Spark, Burn and Firefighter associate a knowledge-acquisition tool with each method in the library. Protege II uses Dash to generate knowledge-acquisition tools from domain ontologies.
In-Cell Frequency Reuse for Broadband Indoor Wireless Systems Using Sectored Antennas
Authors: Aleandro S. Macedo, Elvino S. Sousa
Venue: Wireless Personal Communications: An International Journal (1999)

This paper proposes a hybrid Space-Time Division Multiple Access (S-TDMA) for broadband indoor wireless systems using sectored antennas. It is shown that portables which are located in different sectors of the indoor microcell may be able to reuse the same frequency and the same time slot. However this requires careful scheduling of packet transmissions in order to avoid transmitting packets that would jam each other during the same time slot. It is proposed that the scheduling be performed by the base station, i.e., a central control architecture. If the number of channels (simultaneous transmissions) is larger than two, the optimum scheduling algorithm, the one that maximizes the number of packets transmitted per frame, is in the NP-Complete class of problems and so can not be solved in real time. Therefore a sub-optimum algorithm named the First Fit Algorithm (FFA) is proposed for frame scheduling and its performance is investigated through measurement results obtained in some typical indoor environments. Computer simulations based on the measured data showed that the FFA can provide a large capacity gain. For example, for a minimum acceptable signal-to- interference ratio of 10 dB and for a sectorization level ten (using ten sectors in the base station) the FFA can multiply the capacity by 3.6 in a typical open indoor location. This means that on average, 3.6 packets can be transmitted per time slot while using the same radio frequency.
Test Strategy for the PowerPC 750 Microprocessor
Authors: Carol Pyron, Javier Prado, James Golab
Venue: IEEE Design Test (1998)

Time to market demands for the PowerPC 750 microprocessor require new test strategy approaches to improving the product test quality, reliability, and debug process. The total time to market includes not just the design cycle time to the initial tapeout, but also the productization time. Strong debug support and silicon verification are key to reducing the time to market. A test suite with high test effectiveness must be prepared before initial parts are available to minimize debug efforts on defective silicon. The implementation of the design for test and debug features also must be balanced with requirements for processor performance. The PowerPC 750 test strategy includes enhanced or new design for test features and improved test generation and debug processes
Object Programming for CAD
Authors: Wayne Wolf
Venue: IEEE Design Test (1991)

The use of object-oriented programming to simplify the design and implementation of CAD systems is discussed. The three features common to all languages that support object-oriented programming data abstraction, inheritance, and runtime-function determination are examined. Examples are given to illustrate the advantages of object-oriented methods. How to build an embryonic CAD framework and when to use an object-oriented language are addressed. Object-oriented databases are defined.
Power: A First-Class Architectural Design Constraint
Authors: Trevor Mudge
Venue: Computer (2001)

With Internet use growing exponentially and information technology consuming about 8 percent of power in the US, limiting power consumption presents a critical computing issue. If the IT component continues to grow exponentially without check, it will soon require more power than all other uses combined. Concurrent with the rapid growth in power consumption, an alarming growth in the chip die's power density has been noted. For example, despite process and circuit improvements, the Alpha model 21364's power density has reached approximately 30 watts per square centimeter-- three times that of a typical hot plate. Obviously, trading high power for high performance cannot continue. Reducing power consumption will require adding architectural improvements to process and circuit improvements. Thus, elevating power to a first-class constraint must be a priority early in the design stage when architectural tradeoffs are made as designers perform cycle-accurate simulation.
Graph-based quantum logic circuits and their realization by novel GaAs multiple quantum wire branch switches utilizing Schottky wrap gates
Authors: Miki Yumoto, Seiya Kasai, Hideki Hasegawa
Venue: Microelectronic Engineering (2002)

A novel approach for quantum logic circuits is described. In this approach, graph-based circuits are directly constructed on nanowire networks and controlled by multiple quantum wire branch switches. Potential advantages of the approach are briefly discussed. A novel GaAs branch switch using a nano-scale Schottky wrap gates (WPGs) on etched AlGaAs/GaAs nanowire was fabricated and its basic control characteristics were investigated. WPG realizes tight gate control of quantum transport near wire pinch off and shows clear conductance quantization at low temperatures. Simple circuits for BDD path switching and AND logic function were then fabricated, and they showed correct operation at low temperature. They could be operated at room temperature by increasing power consumption.
Improving the Reliability and Safety of Automotive Electronics
Authors: Enrico Zanoni, Paolo Pavan
Venue: IEEE Micro (1993)

The activities of the European Prometheus project's PRO-CHIP research groups, which have studied the problem of improving automotive electronic reliability while respecting the specifications of low-cost, high-volume production, light weight, compactness, and short time-to-market imposed by the automotive industry, are reviewed. The reliability problems most frequently encountered by electronic devices for automotive applications, including failure mechanisms due to the package or to the assembling technology, different kinds of electrical overstress, electrostatic discharge, electromagnetic interference, breakdown and burnout of power devices, and failure mechanisms accelerated by high temperatures and high current densities, and the procedures the manufacturers use to evaluate and improve the reliability of their products are discussed.
Does Size Really Matter&mdash;Using a Decision Tree Approach for Comparison of Three Different Databases from the Medical Field of Acute Appendicitis
Authors: Milan Zorman, Hans-Peter Eich, Bruno Stiglic, Christian Ohmann, Mitja Lenic
Venue: Journal of Medical Systems (2002)

Decision trees have been successfully used for years in many medical decision making applications. Transparent representation of acquired knowledge and fast algorithms made decision trees one of the most often used symbolic machine learning approaches. This paper concentrates on the problem of separating acute appendicitis, which is a special problem of acute abdominal pain, from other diseases that cause acute abdominal pain by use of an decision tree approach. Early and accurate diagnosing of acute appendicitis is still a difficult and challenging problem in everyday clinical routine. An important factor in the error rate is poor discrimination between acute appendicitis and other diseases that cause acute abdominal pain. This error rate is still high, despite considerable improvements in history-taking and clinical examination, computer-aided decision-support, and special investigation such as ultrasound. We investigated three databases of different size with ca ses of acute abdominal pain to complete this task as successful as possible. The results show that the size of the database does not necessary directly influence the success of the decision tree built on it. Surprisingly we got the best results from the decision trees built on the smallest and the biggest database, where the database with medium size (relative to the other two) was not so successful. Despite this we were able to produce decision tree classifiers that were capable of producing correct decisions on test data sets with accuracy up to 84%, sensitivity to acute appendicitis up to 90%, and specificity up to 80% on the same test set.
The Complex Bootstrap Algorithm for Blind Separation of QAM Multiuser CDMA Signals
Authors: Y. Bar-Ness, N. J. M. Van Waes
Venue: Wireless Personal Communications: An International Journal (2000)

The bootstrap separator for multiuser signals is principally composed of cancelers, each one using the output of the other cancelers to facilitate control of its adaptive weight. In fact, such a structure performs as a &rsquo;&rsquo;signal separator&lsquo;&lsquo; rather than an interference canceler. Since for its separation there is no need for a reference signal (as in LMS cancelers), it is sometimes justifiably called a &rsquo;&rsquo;Blind Separator&lsquo;&lsquo;. However, for its operation the bootstrap separator requires a signal distinguisher termed &rsquo;&rsquo;discriminator&lsquo;&lsquo;. The algorithm was used in the past in applications such as dually polarized satellite communications and microwave terrestrial links. It was particularly reported for multiuser CDMA signal separating, with the signum function as discriminator. Especially for QAM signals, complex presentation is important. Therefore, we will concentrate in this report on what we call the &rsquo;&rsquo;Complex Bootstrap Algorithm&lsquo;&lsquo;. It is an extension to the previously reported bootstrap structure of [5]. We will examine its performance and emphasize the hardware saving in its implementation, and the ease of using it in simulation.
A Pairwise Substitutional Fault Tolerance Technique for the Cube-Connected Cycles Architecture
Authors: N. F. Tzeng, P. J. Chuang
Venue: IEEE Transactions on Parallel and Distributed Systems (1994)

With all of the salient features of hypercubes, the cube-connected cycles (CCC)structure is an attractive parallel computation network suited for very large scaleintegration (VLSI) implementation because of its layout regularity. Unfortunately, theclassical CCC structure tends to suffer from considerable performance degradation in thepresence of faults. The authors deal with a fault-tolerant CCC structure obtained byincorporating a spare PE in each cycle and by adding extra links among PE's to realizedimensional substitutes for failed PE's in the immediate lower dimension. A unique feature of this design lies in that a faulty PE and its laterally connected PE are always replaced at the same time by their immediate vertical successor pair, achieving pairwise substitution to elegantly maintain the rigid full CCC structure after faulty PE's arise. The proposed structure improves reliability substantially without incurring large overhead in layout area. This design is compared with earlier fault-tolerant CCC designs in terms of normalized reliability, which takes area overhead into account. An extension to this fault-tolerant structure is also discussed.
Data Consistency in Intermittently Connected Distributed Systems
Authors: Evaggelia Pitoura, Bharat Bhargava
Venue: IEEE Transactions on Knowledge and Data Engineering (1999)

Mobile computing introduces a new form of distributed computation in which communication is most often intermittent, low-bandwidth, or expensive, thus providing only weak connectivity. In this paper, we present a replication scheme tailored for such environments. Bounded inconsistency is defined by allowing controlled deviation among copies located at weakly connected sites. A dual database interface is proposed that in addition to read and write operations with the usual semantics supports weak read and write operations. In contrast to the usual read and write operations that read consistent values and perform permanent updates, weak operations access only local and potentially inconsistent copies and perform updates that are only conditionally committed. Exploiting weak operations supports disconnected operation since mobile clients can employ them to continue to operate even while disconnected. The extended database interface coupled with bounded inconsistency offers a flexible mechanism for adapting replica consistency to the networking conditions by appropriately balancing the use of weak and normal operations. Adjusting the degree of divergence among copies provides additional support for adaptivity. We present transaction-oriented correctness criteria for the proposed schemes, introduce corresponding serializability-based methods, and outline protocols for their implementation. Then, some practical examples of their applicability are provided. The performance of the scheme is evaluated for a range of networking conditions and varying percentages of weak transactions by using an analytical model developed for this purpose.
A Single-Chip Multiprocessor
Authors: Lance Hammond, Basem A. Nayfeh, Kunle Olukotun
Venue: Computer (1997)

These Stanford University researchers present the case for billion-transistor processor architectures that will consist of chip multiprocessors (CMPs): multiple (four to 16) simple, fast processors on one chip. In their proposal, each processor is tightly coupled to a small, fast, level-one cache, and all processors share a larger level-two cache. The processors may collaborate on a parallel job or run independent tasks (as in the SMT proposal). The CMP architecture lends itself to simpler design, faster validation, cleaner functional partitioning, and higher theoretical peak performance. However for this architecture to realize its performance potential, either programmers or compilers will have to make code explicitly parallel. Old ISAs will be incompatible with this architecture (although they could run slowly on one of the small processors).