ppxscal/embedding_network huggingface dataset:
A Topos over an Ontology as a Model of Experts Intuition
Authors: Alexander Voinov
Venue: Proceedings of the 2002 IEEE International Conference on Artificial Intelligence Systems (ICAIS'02) (2002)

A formal representation of an expert's world model is described, which covers not only the domain ontology, but also the relationships of similarity between its entities. Similarities are formally treated in the framework of pretopological, topological and metric spaces, where an actually achievable grade of metricity of similarity relationships is determined experimentally. An automated inference under uncertainty in the proposed model is based on the internal logic of a (pre)sheaf, where the base category is the formal domain ontology (a "field of knowledge"), which ordinary skeleton of entities and relationships is embedded into a (pre)topological structure, formed by the subjectively significant, for the expert, "regions of evidence", where the decision process is "intuitively obvious" and formalized with the lattice of conceptual similarities of the corresponding local neighbourhoods in his/her world model.
Logic for Static Hazard Detection of Multiple-Valued Logic Circuits with Tsum, Min, and Literals
Authors: Noboru Tkagi, Kyoichi Nakashima
Venue: Proceedings of the 32nd International Symposium on Multiple-Valued Logic (2002)

Multiple-valued logic circuits are often implementedby the current mode CMOS technology, or sometimesthe voltage mode technology. Even if multiple-valuedlogic circuits are realized by either one of thetwo technologies, the signal propagation delay will causehazards pluses, which are undesirable short pulses incircuits. This paper will focus on static hazards inmultiple-valued logic circuits. The paper is supposedto have a device technology such as the current modeCMOS technology, because the way of information signalstransition is very important to introduce a logicalmodel for hazards detection of multiple-valued logic circuits.We will show some of the mathematical proper-tiesof functions on the logical model introduced by thepaper. Multiple-valued logic circuits are supposed to beconstructed by the truncated sum, the minimum, andthe literal gates.
A Learning Algorithm for Structured Character Pattern Representation Ysed in On-Line Recognition of Handwritten Japanese Characters
Authors: A. Kitadai, M. Nakagawa
Venue: Proceedings of the Eighth International Workshop on Frontiers in Handwriting Recognition (IWFHR'02) (2002)

This paper describes a prototype learning algorithm for structured character pattern representation with common subpatterns shared among multiple character templates for on-line recognition of handwritten Japanese characters. Although prototype learning algorithms have been proved useful for an unstructured set of features, they have not been presented for structured or hierarchical pattern representation. In this paper, we present cost-free parallel translation without rotation of subpatterns that negates their locationdistributions and normalization that reflects feature distributions in raw patterns to the subpattern prototypes, and then show that a prototype learning algorithm can be applied to the structured character pattern representation with significant effect.
Generating Test Cases for GUI Responsibilities Using Complete Interaction Sequences
Authors: Lee White, Husain Almezen
Venue: Proceedings of the 11th International Symposium on Software Reliability Engineering (2000)

Testing Graphical User Interfaces (GUI) is a difficult problem because the GUI possesses a large number of states to be tested; the input space is extremely large due to different permutations of inputs and events, which affect the GUI, and complex GUI dependencies, which may exist. There has been little systematic study of this problem yielding a resulting strategy, which is effective and scalable. The proposed method concentrates upon user sequences of GUI objects and selections, which collaborate, called complete interaction sequences (CIS) that produce a desired response for the user. A systematic method to test these CIS utilizes a finite-state model to generate tests. Identifying components of the CIS that can be tested separately can substantially reduce the required tests. Since consideration is given to defects totally within each CIS, and the components reduce required testing further, this approach is scalable. An empirical investigation of this method shows that substantial reduction in tests can still detect the defects in the GUI. Future research will prioritize testing related to the CIS testing for maximum benefit if testing time is limited.
Functional decomposition of MVL functions using multi-valued decision diagrams
Authors: C. Files, R. Drechsler, M. A. Perkowski
Venue: Proceedings of the 27th International Symposium on Multiple-Valued Logic (1997)

In this paper, the minimization of incompletely specified multi-valued functions using functional decomposition is discussed. From the aspect of machine learning, learning samples can be implemented as minterms in multi-valued logic. The representation, can then be decomposed into smaller blocks, resulting in a reduced problem complexity. This gives induced descriptions through structuring, or feature extraction, of a learning problem. Our approach to the decomposition is based on expressing a multi-valued function (learning problem) in terms of a multi-valued decision diagram that allows the use of Don't Cares. The inclusion of Don't Cares is the emphasis for this paper since multi-valued benchmarks are characterized as having many Don't Cares.
Jade: a distributed software prototyping environment
Authors: Ian H. Witten, Graham M. Birtwistle, John Cleary, David R. Hill, Danny Levinson, Greg Lomow, Radford Neal, Murray Peterson, Brian W. Unger, Brian Wyvill
Venue: ACM SIGOPS Operating Systems Review (1983)

The Jade research project is aimed at building an environment which comfortably supports the design, construction, and testing of distributed computer systems. This note is an informal project description which delimits the scope of the work and identifies the research problems which are tackled. Some design issues are discussed, and progress to date is described.
No Free Lunch for Early Stopping
Authors: Zehra Cataltepe, Yaser S. Abu-Mostafa, Malik Magdon-Ismail
Venue:  (1998)

We show that, with a uniform prior on hypothesis functions having the same training error, early stopping at some fixed training error above the training error minimum results in an increase in the expected generalization error. We also show that regularization methods are equivalent to early stopping with certain non-uniform prior on the early stopping solutions.
Multilevel Data Structures Models and Performance
Authors: Abha Moitra, S. S Iyengar, F. Bastani, I. Yen
Venue:  (1985)

We advocate a stepwise method of deriving high performance implementation of a set of operations. This method is based on the ability to organize the data into a multilevel data structure so as to provide an efficient implementation of all the operations. Typically, for such data organization the performance may deteriorate over a period of time and that can be corrected by reorganizing the data. This data reorganization is done by the introduction of maintenance processes. For a particular example we consider the multilevel data organization and the different models of maintenance processes possible. We sketch a correctness proof for the implementation we develop. Performance behaviour for the different models are derived and we also present some simulation studies of the performance.
Efficient Global Object Space Support for Distributed JVM on Cluster
Authors: Weijian Fang, Cho-Li Wang, Francis C. M. Lau
Venue: Proceedings of the 2002 International Conference on Parallel Processing (2002)

We present the design of a global object space in a distributed Java Virtual Machine that supports parallel execution of a multi-threaded Java program on a cluster of computers. The global object space virtualizes a single Java object heap across machine boundaries to facilitate transparent object accesses. Based on the object connectivity information that is available at runtime, the object reachable from threads at different nodes, named as distributed-shared object, are detected. With the detection of distributed-shared objects, we can alleviate overheads in maintaining the memory consistency within the global object space. Several runtime optimization methods have been incorporated in the global object space design, including an object home migration method that reallocates the home of a distributed-shared object, synchronized method migration that allows the remote execution of a synchronized method at the home node of its synchronized object, and object pushing that uses the object connectivity information to improve access locality.
Parallel Simulation of the Ising Model
Authors: T. MacFarland, G. T. Barkema
Venue:  (1994)

(The following contains mathematical formula and symbols that may become distorted in ASCII text.) New methods for parallelizing Ising model simulations are presented. A parallel single-spin Metropolis algorithm has been implemented with a speedup of 27 on 50 processors of the KSR-1 parallel computer. Our parallel Swendsen-Wang algorithm obtains a speedup of 3.2 on 9 processors of the same computer. Both of these simulations were carried out on 200x200 lattices. The parallel Local Cluster algorithm has been implemented with an almost linear speedup. We also discuss ongoing research using the parallel Local Cluster algorithm.
On Some Classes of Fuzzy Information Granularity and Their Representations
Authors: Yutaka Hata, Masao Mukaidono
Venue: Proceedings of the Twenty Ninth IEEE International Symposium on Multiple-Valued Logic (1999)

This paper describes some classes of fuzzy information granularity and their representation methods. Fuzzy information granularity introduced by Zadeh is that "granularity relates to clumpiness of structure, while granulation refers to partitioning an object into a collection of granules, with a granule being a clump of objects(points) drawn together by indistinguishability, similarity, proximity, or functionality." In this paper we show three classes of granularity structures, which are called Kleene class, Lukasiewicz class and probabilisticlike class. Their meaning and representation methods are discussed. Their examples are also demonstrated. This paper would be a basis to research on the representation of fuzzy information granularity.
Assurance Technology for Coexisting Test and Operation Subsystems and Its Application to Train Control System
Authors: Masayuki Matsumoto
Venue: Proceedings of the The Sixth International Symposium on Autonomous Decentralized Systems (ISADS'03) (2003)

The conventional ground-based train control on-board computer system for keeping a fixed distance between trains cannot provide high-density train operation. Then an autonomous decentralized train control on-board computer system is proposed, in which each train has autonomy to detect its position and its speed, to communicate this information between a train ahead of it and itself, and to judge its speed for safety and punctuality. To realize these real-time on-board computers and their network system, train operation cannot be stopped during their step-by-step construction and testing while both conventional and new systems have to coexist. The autonomous on-line expansion and test technology is proposed where each train has autonomy to select and to receive data based on its content and to judge its normal or test operation. In the process of replacing the conventional system with the new one, two assurance technologies are proposed, where networks based on the content code communication are integrated to coexist with their different data and they are separated butconnected through a gate way. These technologies are evaluated with respect to the total system operation. These technologies are shown to be effective on an experimental railway, and are now being applied on the Keihin Tohoku Line in the Tokyo metropolitan area.
Time-Shift Scheduling: Fair Scheduling of Flows in High Speed Networks
Authors: Jorge A. Cobb, Mohamed G. Gouda, Amal El Nahas
Venue: Proceedings of the 1996 International Conference on Network Protocols (ICNP '96) (1996)

We present a scheduling protocol, called Time-Shift scheduling, to forward data packets from multiple input flows to a single output channel. Each input flow is guaranteed a predetermined forwarding rate and an upper bound on packet delay. The protocol is an improvement over existing protocols because it satisfies the properties of low delay, fairness, and efficiency, while existing protocols fail to satisfy at least one of these properties. In Time-Shift scheduling, each flow is assigned an increasing timestamp, and the packet chosen for transmission is taken from the flow with the least timestamp. The protocol features the novel technique of time shifting, in which the scheduler's real-time clock is adjusted to prevent flow timestamps from increasing faster than the real-time clock. This bounds the difference between any pair of flow timestamps, thus ensuring the fair scheduling of flows.
AutoCAD 2004 for Interior Design and Space Planning
Authors: Beverly L. Kirkpatrick, James M. Kirkpatrick
Venue:  (2003)

:Teaching users how to make architectural drawings using a computer and the AutoCAD 2004 program, this easy-to-understand manual employs the prompt-response format in beginning exercises of all chapters to allow users to learn commands in a drawing situation and, then moves to an outline form in later exercises so they can apply the commands on their own. Applying all the new features of AutoCAD Release 2004e.g. redesigned AutoCAD Design Center, modeless dialog boxes, new gradient hatchings for rendering two-dimensional drawings, 3dOrbit, solidedit and new Publish command for plotting large drawing sets without user interaction autotracking, the volume provides support information, and tips and articles throughout for a completely current examination of the system. The volume details preparing to draw with AutoCAD, two-dimensional AutoCAD, isometric drawing and gradient hatch rendering, creating presentations and creating a web page using AutoCAD, using raster images and grips, three-dimensional AutoCAD, and solid modeling. For Interior Designers, Interior Decorators, Architects, Interior Architects.
Efficient Hierarchical Approach to Test Generation for Digital Systems
Authors: Raimund Ubar, Jaan Raik
Venue: Proceedings of the 1st International Symposium on Quality of Electronic Design (2000)

A new hierarchical approach to test generation for digital systems is proposed. Three levels of modeling are exploited: high-level Decision Diagrams (DD) for module test planning and system constraints generating, low-level Boolean differential equations for fault constraints generating, and medium-level Binary DDs for local test pattern generation for modules under the derived set of constraints. The proposed method of generating fault constraints the first time allows to handle faults which increase the number of states in sequential circuits.Combining the high-level efficiency of solving complex deterministic search problems and medium-level accuracy of fault "transportation" analysis with low-level exact fault activation allows to reach high efficiency in test generation, and high test quality on the other hand. Experimental results compared to the known test generators are provided for demonstrating the high efficiency of test generation achieved by the proposed approach.
Randić structure of a graph
Authors: Juan Rada, Carlos Uzcátegui
Venue: Discrete Applied Mathematics (2003)

Let g be a collection of graphs with n vertices. We present a simple description of [G]χ = {H ∈ g : χ(H) = χ(G)} where χ denotes the Randic´ index. We associate to G a Q-linear map ρ : Qm → Qk (for some integers k, m depending on g) such that the kernel of ρ contains the necessary information to describe [G]χ in terms of linear equations. These results provide precise tools for analyzing the behavior of χ on a collection of graphs.
O(log^2 n) Time Efficient Parallel Factorization of Dense, Sparse Separable, and Banded Matrices
Authors: John H. Reif
Venue:  (1994)

Known polylog parallel algorithms for the solution of linear systems and related problems require computation of the characteristic polynomial or related forms, which are known to be highly unstable in practice. However, matrix factorizations of various types, bypassing computation of the characteristic polynomial, are used extensively in sequential numerical computations and are essential in many applications. This paper gives new parallel methods for various exact factorizations of several classes of matrices. We assume the input matrices are n x n with either interger entries of size > 2^n^0(1) or rational - entries expressible as a ratio of integers of size > 2^n^0(1). - We make no other assumption on the input. We assume the arithmetic PRAM model of parallel computation. Our main result is a reduction of the known parallel time bounds for these factorizations from O(log^3 n) to O(log^2 n). Our results are work efficient; we match the best known work bounds of parallel algorithms with polylog time bounds and are within a log n factor of the work bounds for the best known sequential algorithms for the same problems. The exact factorizations we compute for symmetric positive definite matrices includes: recursive factorization sequences and trees. LU factorizations, QR factorizations, and reduction into upper Hessenberg form. The classes of matrices for which we can efficiently compute these factorizations include: 1. dense matrices, in time O(log^2 n) with processor bound P(n) (the number of processors needed to multiply two n x n matrices in O(log n) time). 2. block diagonal matrices, in time O(log^2 b) with P(b)n/b processors, 3. sparse matrices which are s(n)-separable (recursive factorizations only), in time O(log^2 n) with P(s(n)) processors where s(n) is of the form n^g for 0 > g > 1, and 4. banded matrices, in parallel time O((log n)log b) with P(b)n/b processors. Our factorizations also provide us simillarly efficient algorithms for exact computation (given arbitrary rational matrices that need not be symmetric positive definite) of the following: solution of the corresponding linear systems, the determinant, the inverse. Thus our results provide the first known efficient parallel algorithms for exact solution of these matrix problems, that avoids computation of the characteristic polynomial or related forms. Instead we use a construction which modifies the input matrix, which many initially have arbitrary condition, so as to have condition nearly 1, and then applies a multilevel, pipelined Newton iteration, followed by a similar multilevel, pipelined Hensel Lifting.
Rate Distortion Optimizations for Motion Estimation in Low-Bitrate Video Coding
Authors: T D Hoang, M P Long, Scott J Vitter
Venue:  (1995)

We present and compare methods for choosing motion vectors for motion-compensated video coding. Our primary focus is on videophone and videoconferencing applications, where very low bit rates are necessary, where motion is usually limited, and where frames must be coded in the order they are generated. We provide evidence, using established benchmark videos typical of these applications, that choosing motion vectors explicitly to minimize rate, subject to implicit constraints on distortion, yields better rate-distortion tradeoffs than minimizing notions of prediction error. Minimizing a linear combination of rate and distortion results in further rate-distortion improvements. Using a heuristic function of the prediction error and the motion vector codelength results in compression performance comparable to the more computationally intensive coders while running much faster. We incorporate these ideas into coders that operate within the $p \times 64$ standard.
Program Comprehension Experiences with GXL; Comprehension for Comprehension
Authors: Claire Knight, Malcolm Munro
Venue: Proceedings of the 10th International Workshop on Program Comprehension (2002)

Tools are vital to support the various activities that form the many tasks that are part of the program comprehension process. In order that these tools are used and useful it is necessary that they support the activities of the user. This support must complement the work methods and activities of the user and not hinder them. Whilst features of good tools have been identified tool builders do not always adhere them to. It is important to consider whether needs have changed, and if those desirable properties need augmenting or revising. From experience of maintaining and enhancing an existing program comprehension tool for the purposes of participating in a re-engineering activity many lessons on tool support have been learned.
Simulations of TCP Congestion Control Mechanism Model with Large Buffer Size
Authors: Ying Xu, Wenjun Wu
Venue: Proceedings of the 2001 International Conference on Computer Networks and Mobile Computing (ICCNMC'01) (2001)

Transmission Control Protocol(TCP) is the main protocol of the transport layer in today's Internet. Many works have studied the performance of TCP and researcher are trying to analytically characterizing the throughput of TCP's congestion control mechanism. In this paper, we summarize the works and present the simulation result with large buffer size and give an qualitative analysis of the result. Our conclusion is that the RTT is not increased by linear , but by quadric when the buffer size of the bottleneck is large enough. Our goal is to estimate the average queue length of the buffer size and develop a TCP model based on RTT and the average queue length.
Implementing and Exploiting Static Speculation on Multiple Instruction Issue Processors
Authors: Mayan Moudgill
Venue:  (1994)

Trends in processor architecture and design suggest that static speculation will become a candidate for implementation on future high-performance processors. In this dissertation, we shall examine issues related to the implementation and exploitation of static speculation. There are four primary results: 1) Precise Exceptions: Prior work in static speculation has not examined the interaction between exception handling and speculative instructions in any great detail. We investigate this interaction, exhibiting certain problematic subtleties that arise, and show how they can be overcome. 2) Speculative Tagging: Earlier proposals for implementing speculative instructions tended to have several drawbacks, including restricted applicability. We introduce speculative tagging, a new, more general, mechanism for specifying static speculation, and show it is possible to optimize exception recovery through this mechanism. 3) Whole-DAG Scheduling: Recently, there has been some work on scheduling regions of acyclic code larger than a basic block so as to take advantage of static speculation. We describe another such algorithm, known as whole-DAG scheduling, that contains innovations that make it more flexible, and allow it to use better heuristics. 4) Dynamic Speculation: The work on static speculation and exceptions suggested an alternative approach to implementing dynamic speculation. This approach results in simpler hardware than prior schemes, and is consequently cheaper to implement and potentially has a lesser impact on cycle-time. Additionally, we report results of experimental studies measuring the effectiveness of whole-DAG scheduling. In it, we show, among other things, that our scheduling technique can result in near-optimal schedules, and that the selection heuristics we adopt are superior to those used in earlier algorithms.