ppxscal/embedding_network huggingface dataset:
Automatic Generation of Microarchitecture Simulators
Authors: Soner Önder, Rajiv Gupta
Venue: Proceedings of the 1998 International Conference on Computer Languages (1998)

In this paper we describe the UPFAST system that automatically generates a cycle level simulator, an assembler and a disassembler from a microarchitecture specification written in a domain specific language called the Architecture Description Language (ADL). Using the UPFAST system it is easy to retarget a simulator for an existing architecture to a modified architecture since one has to simply modify the input specification and the new simulator is generated automatically. UPFAST also allows porting of simulators to different platforms with minimal effort. We have been able to develop three simulators ranging from simple pipelined processors to complicated out-of-order issue processors over a short period of three months. While the specifications of the architectures varied from 5000 to 6000 lines of ADL code, the sizes of automatically generated software varied from 20,000 to 30,000 lines of C++ code. The automatically generated simulators are less than 2 times slower than hand coded simulators for similar architectures.
Abstract Deducibility and Domain Theory
Authors: Vladimir Y Sazonov, Dmitri I. Sviridenko
Venue:  (1996)

According to the thesis ``computability = deducibility'''' [D.Scott, LNCS 140] there are investigated intensional aspects of domain theory as mathematical theory of computability. A logistic system is any pair of sets , where R \subseteq Conf(A) := Powerset(A) x (A union {#}), # \notin A. The intended interpretation: A is a set of sentences, R is a rule of inference, and # is a contradiction sign. As usually, R induces a relation |-_R \subseteq Conf(A) of (reflexive) deductive inference and also the classes Cl() \subseteq Powerset(A) of the closed sets under |-_R and Th() \subseteq Cl() of consistent closed sets (theories) partially ordered by the inclusion relation. The followimg more general notion of deducibility ||-_R, which may be non-reflexive, playes an important role. Let G ||-_R f iff there exists a (well-founded) tree of inference G ||-_R f which contains at least one configuration in R (i.e. is non-trivial). By imposing, if necessary, on deducibility notion suitable finitarity conditions (and others) it is possible to characterise rather naturally, from the point of view of the abovementioned thesis, various classes of domains, e.g. classes of all complete lattices with a base, conditionally complete partially ordered sets with a base, complete f_0-spaces (defined in [Ju.L.Ershov, Algebra and Logic, 11, N4], the same as Scott''s algebraic domains; cf. also [D.Scott, LNCS 140] where only finitary reflexive deducibility is considered), Ershov''s complete A_0-spaces [Algebra and Logic, 12, N4] = Scott''s continuous domains, and Scott''s continuous lattices. For example, Th() is an (arbitrary) complete A_0-space under \subseteq if for some R \subseteq Conf(A) there holds (1) G/f \in R =< G is finite, (i.e. R is finitary), (2) G ||-_R f =< G^ ||-_R f, where G^ := union {g^ : g \in G and g^ := {h : g ||-_R h}, and (3) G |- f G ||-_R f^ and $G |- # G ||-_R #. The goal of this paper is just to give an English extended version of the above text published only in Russian [V.Yu.Sazonov and D.I.Sviridenko, Abstract Deducibility and Domain Theory, Seventh All Union Conference on Mathematical Logic, Abstracts, Novosibitsk, 1984, p. 158] in connection with a related recent paper [R.Hoofman, Continuous Information Systems, Information and Computation 105, 42--71 (1993)]. It contains also an Appendix to this Abstract (written by the first author) with additional details, proofs and some comparisons with Hoofman''s approach.
Discrete Mathematics
Authors: Laszlo Lovasz, Jozsef Pelikan, Katalin L. Vesztergombi
Venue:  (2003)

:This book is aimed at undergraduate mathematics and computer science students interested in developing a feeling for what mathematics is all about, where mathematics can be helpful, and what kinds of questions mathematicians work on. The authors discuss a number of selected results and methods of discrete mathematics, mostly from the areas of combinatorics and graph theory, with a little number theory, probability, and combinatorial geometry. Wherever possible, the authors use proofs and problem solving to help students understand the solutions to problems. In addition, there are numerous examples, figures, and exercises spread throughout the book.
Geometric properties of subclasses of starlike functions
Authors: Adam Lecko, Agnieszka Wiśniowska
Venue: Journal of Computational and Applied Mathematics (2003)

We present some geometric characterization of the class k-SJ consisting of the so-called k-starlike functions.
A Bandwidth-Efficient Implementation of Mesh with Multiple Broadcasting
Authors: Jong Hyuk Choi, Bong Wan Kim, Kyu Ho Park, Kwang-Il Park
Venue: Proceedings of the 1999 International Conference on Parallel Processing (1999)

This paper presents a mesh with virtual buses as the bandwidth-efficient implementation of the mesh with multiple broadcasting on which many computational problems can be solved with reduced time complexity. The new system provides a low latency and high bandwidth communication mechanism without the disadvantage of the dual network approach: the possible bandwidth waste. The virtual buses are built using those communication links of the base point-to-point mesh network only upon request. Even if bus requests are not made, the full network bandwidth is harnessed by the point-to-point communication. On the contrary, the bandwidth assigned to the conventional real buses will be wasted when there is little bus request.This paper introduces a wormhole router design equipped with the virtual bus functions, describes the connections among these routers, and presents various virtual bus transactions. We prove the effectiveness of the virtual bus by showing that a representative semigroup computation can be solved very efficiently on it: a vector maxima finding is accelerated by 2.66 times in the experiment. We also explore the network characteristics by the distribution-driven simulation of the system. These evaluations convinced us that the mesh with virtual buses is a promising approach to low latency and high bandwidth communication which has applications in many parallel computations such as in parallel simulations, computer graphics, real time systems, and many others.
On Valid and Invalid Methodologies for Experimentala Evaluations of EBL
Authors: Alberto M. Segre, Charles P. Elkan, Alex Russell
Venue:  (1990)

A number of experimental evaluations of explanation-based learning (EBL) have appeared in the literature on machine learning. Closer examination of experimental methodologies used in the past reveals certain methodological flaws that call into question the conclusions drawn from these experiments. This paper illustrates some of the more common methodological problems, proposes a novel experimental framework for future empirical studies of EBL, and presents an example of an experiment performed within this new framework.
Using White Space for Automated Document Structuring
Authors: Daniela Rus, Kristen Summers
Venue:  (1994)

We present and analyze efficient algorithms for the automated recognition and interpretation of layout structures in electronic documents. The key idea is to use the patterns in the distribution of white space in a document to recognize and interpret its components. The recognition algorithm divides the document into a hierarchy of logical elements; the interpretation algorithms classify these divisions as base-text, tables, indented lists, polygonal drawings, and graphs. We present experimental data and discuss an information access application. Our methodology allows the automatic markup of documents\footnote{For instance in the SGML format} and the creation of multi-level indices and browsing tools for electronic libraries.
Table-Top Spatially-Augmented Reality: Bringing Physical Models to Life with Projected Imagery
Authors: Ramesh Raskar, Greg Welch, Wei-Chao Chen
Venue: Proceedings of the 2nd IEEE and ACM International Workshop on Augmented Reality (1999)

Despite the availability of high-quality graphics systems, architects and designers still build scaled physical models of buildings and products. These physical models have many advantages, however they are typically static in structure and surface characteristics. They are inherently lifeless. In contrast, high-quality graphics systems are tremendously flexible, allowing viewers to see alternative structures, facades, textures, cut-away views, and even dynamic effects such as changing lighting, moving automobiles, people, etc.We introduce a combination of these approaches that builds on our previously-published projector-based Spatially-Augmented Reality techniques. The basic idea is to aim multiple ceiling-mounted light projectors inward to graphically augment table-top scaled physical models of buildings or products. This approach promises to provide very compelling hybrid visualizations that afford the benefits of both traditional physical models, and modern computer graphics, effectively "bringing to life" table-top physical models.
Wearable Performance
Authors: Flavia Sparacino, Alex Pentland, Glorianna Davenport
Venue: Proceedings of the 1st IEEE International Symposium on Wearable Computers (1997)

Wearable computers offer the street performer powerful tools with which to create innovative experiences for the audience. As wearable technology moves computation from the desktop onto the user's body, it provides an invitation to free performance from the indoor stage, bringing a new adaptive richness to the mobile world of street theater. We find it therefore compelling to explore several application contexts in which wearable technology enhances, extends and creates new examples of street performance. In this paper we offer a taxonomy of different genres of street performance and we describe how the wearable computer transforms, augments and enriches the traditional form in an original and witty manner.
Hypercube Communication Performance
Authors: C. L. McCreary, M. E. McArdle, J. D. McCreary
Venue:  (1991)

Performance information is essential to the design of efficient parallel programs. Whether the programmer has total control over determining the parallel execution of processes or whether some automatic means are used to parallelize serial or parallel code, the cost of the overhead due to parallelization must be known. This is especially important in systems where the costs of such mechanisms are high. In distributed systems, message passing is the primary means of communication between parallel processes, and message passing tends to be quite expensive. Users of such systems wrestle with a variety of questions related to performance issues. How is the data to be distributed among the processors? What grain size (amount of code executed serially on a processor) is required for efficient processing? How should the processes be assigned to the system nodes? Approximate answers to these questions can be given only if the performance characteristics of the system are known. This paper presents a step towards the development of a performance model for two distributed memory multiprocessor systems, the Intel iPSC/2 and iPSC/860 hypercubes. From actual timing measurements, we developed formulas to estimate the communication costs on the four possibilities for message passing among multiple processors: a single sender to a single receiver, single sender to multiple receivers, multiple senders to a single receiver, and multiple senders to multiple receivers. A practical method for synchronizing timing measurements among independently clocked processing nodes was developed to do this analysis.
Integration/Evaluation of a HCI Prototyping Environment
Authors: Loretta A. Moore
Venue:  (1994)

Components of a Human Computer Interface (HCI) prototyping environment have been integrated and evaluated. This environment will be valuable in developing and refining HCI standards and evaluating program/project interface development, especially the International Space Station Alpha''s on-board displays for payload operations. This environment, which allows for rapid prototyping and evaluation of graphical interfaces, includes four components: (1) a HCI format development tool, (2) a test and evaluation simulator development tool, (3) a dynamic, interactive interface between the HCI prototype and simulator, and (4) an embedded evaluation capability to evaluate the adequacy of a HCI based on a user''s performance. The objective of the research was to determine whether or not the functional components could be integrated and could provide the needed functionality for a rapid prototyping environment. In order to evaluate the rapid prototyping environment two prototypes were developed. The system chosen for initial evaluation was an automobile. Following the automobile prototype development, the Hopkins Ultraviolet Telescope (HUT), a Spacelab/Space Station payload, prototype was developed. This report will discuss the architecture of the environment, the prototypes developed within it, and results of an evaluation of the environment based on usability, functionality, and performance.
How Many Pixels to Watermark?
Authors: R. Chandramouli, Nasir Memon
Venue: Proceedings of the The International Conference on Information Technology: Coding and Computing (ITCC'00) (2000)

Watermark design and detection have been studied as two separate problems so far. However, we show that, if the watermarking algorithm is based on the watermark detection method, then significant gains can be achieved. With a watermark detector based on a sequential hypothesis test rather than a fixed sample size test, the number of watermark pixels can be reduced almost by a factor of two for small detection error probabilities. This is because, the sequential hypothesis test requires less (average) number of pixels to detect the presence/absence of a watermark compared to a fixed sample size detector. The savings in the number of pixels to be watermarked results in an increased immunity to host signal attacks such as cropping. Degradation in the signal quality due to redundant watermarking is also minimized. Further, applications such as DVD require minimal amount of watermarking. The computational efficiency of the proposed watermark detector can also be exploited to efficiently search for watermarks in large image databases.
Safe Database Queries with External Functions
Authors: Hong-Cheu Liu, Jeffrey X. Yu
Venue: Proceedings of the 1999 International Symposium on Database Engineering & Applications (1999)

We consider the theory of database queries with functions on the complex value data model. The notion of a syntactic criteria, called `embedded allowed', for queries which guarantee embedded domain independence, is generalized for this model. We show that all embedded allowed calculus (or fix-point) queries are external function domain independent and continuous. We also develop an algorithm for translating embedded allowed queries into equivalent algebraic expressions as a basis for evaluating safe queries in all calculus-based query classes. In the second part of this paper, we compare the expressive power of various complex value query languages extended with functions and their certain restricted versions. If we assume polynomial time (space) complexity of external functions and type usage by the database, such as density, then strongly embedded allowed inflationary (partial) fix-point queries express precisely QPTIME (QPSPACE). Finally, we show the relationship between properties such as embedded domain independence, finiteness and embedded allowed in various calculus-based query languages.
Using ISO 9000 to Elicit Business Rules
Authors: Luiz Marcio Cysneiros, T. Diana L. v. A. de Macedo-Soares, Julio Cesar Sampaio do Prado Leite
Venue: Proceedings of the 4th IEEE International Symposium and Forum on Software Engineering Standards (1999)

Business rules have been largely used in database modeling and more recently in the field of information technology, but rarely in requirements engineering. This article will focus on business rules as prescribed procedures that should be followed to achieve the business's goals. The ISO 9000 documentation includes policies, procedures and instructions to assure the final product's conformance with ISO 9000 requirements. Partly for this reason, it is contended here that ISO 9000 standards and associated documents can be of a great help for business rules elicitation. The authors' main contribution is to propose a conceptual model for not only eliciting business rules, but also integrating them into a software requirements baseline model. This proposal uses ISO 9000 characteristics and integrates them with the idea of natural language-based requirements descriptions.
Application of an advanced evolutionary strategy for the automatic design of modular steel structures
Authors: C. Ebenau, J. Rottschaefer, G. Thierauf
Venue: Proceedings of the sixth conference on Computational structures technology (2002)

Modular three-dimensional steel frames, like steel pallet racks or shelving assemblies and scaffoldings are prefabricated structures with slender elements and dominating compressive forces. The analysis includes different nonlinearities and the optimization variables are often mixed-discrete or topological.The optimization of these systems requires the most advanced solution techniques but also a systematic preprocessing, a sophisticated nonlinear structural analysis and an automated handling of stress- and displacement-constraints as well as further side-constraints resulting from the underlying codes of practice. The objective of the optimization is the minimization of cost. In this contribution a (µ +1)- evolutionary strategy (ES) in combination with an adaptive penalty function and a special selection scheme is presented to solve this optimization problem.Two examples from literature are solved and the results are compared. The examples show the reliability and robustness of the presented method.
An Architecture for Self-Healing Digital Systems
Authors: P. K. Lala, B. Kiran Kumar
Venue: Proceedings of the Proceedings of The Eighth IEEE International On-Line Testing Workshop (IOLTW'02) (2002)

The use of very deep submicron technology makes VLSI-based digital systems more susceptible to transient or soft errors, and thus compromises their reliability. This paper proposes an architecture inspired by the human immune system that allows tolerance ofsuch errors.
Dynamic bandwidth allocation for real-time VBR video traffic in ATM networks
Authors: Hon-Wai Chu, D. H. K. Tsang
Venue: Proceedings of the 6th International Conference on Computer Communications and Networks (1997)

We study the problem of dynamic bandwidth allocation for an ATM multiplexer loaded with real-rime VBR video traffic. The proposed mechanism adjusts the allocated bandwidth at regular intervals based on measured QoS. Instead of actual measurement of small cell loss ratios, we combine a virtual output buffer method with a regression method to shorten the time interval required for estimating the required bandwidth to support the specified QoS by prediction. Using numerical examples, we show that our proposed dynamic bandwidth allocation scheme is more efficient than the optimum static bandwidth allocation scheme. Our measurement-based scheme offers several advantages: (1) it removes the dependence on accurate traffic parameters to be declared by users; (2) it can be applied to a wide variety of traffic sources; (3) it adapts quickly to the variations of traffic with small measurement intervals, and (4) the complexity of the algorithm is small.
One-transistor-cell 4-valued universal-literal CAM for cellular logic image processing
Authors: T. Hanyu, M. Arakaki, M. Kameyama
Venue: Proceedings of the 27th International Symposium on Multiple-Valued Logic (1997)

A non-volatile 4-valued content-addressable memory (CAM) is proposed for fully parallel template-matching operations in real-time cellular logic image processing with fixed templates. A universal literal in each CAM cell is used to compare a 4-valued input pixel with a 4-valued template pattern. Any CAM cell functions are performed by a pair of a simple threshold operation and a logic-value conversion which is shared by CAM cells in the same column of a CAM cellular array. Moreover, the use of a single floating-gate MOS transistor makes it possible to implement a universal-literal circuit together with a 4-valued storage element. As a result, a high-density 4-valued universal-literal CAM, with a single transistor cell is designed by using a multi-layer interconnection technology. Its performance is much superior to that of conventional CAM-based implementations under the same dynamic power dissipation.
Floating-Point Arithmetic and Program Correctness Proofs
Authors: John E. Holm
Venue:  (1980)

This thesis develops tight upper and lower bounds on the relative error in various schemes for performing floating-point arithmetic, proposes axioms for characterizing the significant properties embodied by these schemes, and gives examples to illustrate how these axioms may be used to reason about the correctness of floating-point programs. Three addition schemes are considered: (1) chopped addition, (2) addition with both pre and post-adjustment rounding, and (3) addition with pre-adjustment chopping and post-adjustment rounding. Schemes for performing both rounded and chopped multiplication and division are also considered. Our tight bounds are consistent with the commonly held opinion that a binary base minimizes the maximum relative errors in floating-point arithmetic. Also, these bounds show that one guard digit is optimal for minimizing the maximum relative errors in chopped addition. The bounds derived for each of the addition schemes considered are as tight as possible. One guard digit and two guard bits are shown to be sufficient to round the result of an exact addition to the nearest floating-point number. We show how this scheme can be implemented using a single post-adjustment shift, no rounding overflow, and (for certain implementations) requiring no more time than an addition that chops instead of rounds. Two approaches are considered for axiomatizing floating-point arithmetic. In one approach, a set of floating-point numbers is associated with each floating-point expression, and the assignment statement is modeled as a nondeterministic selector of one of the members in the set. In the alternative approach, the floating-point operations are modeled in terms of two cropping functions whose significant properties are characterized by a small set of axioms. In both cases, the axioms characterizing floating-point arithmetic are used with Dijkstra''s weakest pre-condition calculus to provide an axiomatic framework for reasoning about floating-point programs. Finally, the commom practice of modelling the floating-point operations by a single function that chops or rounds the result of the corresponding exact operation is shown to be invalid for many implementations of floating-point arithmetic.
Randomized Adaptive Routing Based on Mobile Agents
Authors: Marc Bui, Ajoy K. Datta, Olivier Flauzac, Dai Tho Nguyen
Venue: Proceedings of the 1999 International Symposium on Parallel Architectures, Algorithms and Networks (1999)

Mobile agent has been shown to be a convenient, efficient, and robust approach to designing distributed protocols. This paper introduces an adaptive, mobile-agents-based routing algorithm. While performing a random walk through the network, mobile agents sense changes in network state, and trigger the computation of updated values for the routing tables. The randomized moving strategy exerts a negligible and balanced impact on the network resources, both in terms of bandwidth and computation. The memory requirement is very moderate. The correctness of the protocol is proven and its complexity is analyzed.