ppxscal/embedding_network huggingface dataset:
Context-sensitive detection and correction of homonym errors in Japanese texts (poster session)
Authors: Hideya Iwasaki Kumiko Tanaka-Ishii, Kei Tateno, Masato Takeichi
Venue: Proceedings of the fifth international workshop on on Information retrieval with Asian languages (2000)

In Japanese and Chinese, the use of kanji characters has produced words with many homonyms. Thus, the correct `spelling' (kanji) for a word can depend on its context. Computer text entry systems provide a mechanism for users to choose between possible spellings, but mistakes are relatively common. We propose a new context-sensitive algorithm to correct this kind of spelling error. The algorithm detects errors in input text and suggests alternative spellings to the user. Our experimental results have shown maximally about 98% of accuracy rate.
Production and employment of Ph.D.'s in computer science&mdash;1977 and 1978
Authors: Orrin E. Taulbee, S. D. Conte
Venue: Communications of the ACM (1979)

This brief report summarizes the results of the third and fourth annual surveys on the production and employment of Ph.D.'s in computer science. Responses were solicited from department chairmen, and aggregated for presentation. Results of the previous surveys were reported in [1] and [2]. Tabular results of the two latest surveys are presented in Tables I-VII. Numbered years in the tables refer to calendar years. Comparisons are made with corresponding data from previous years, and discussion is limited to comments on changes and trends.
A simple user-oriented compiler source language for programming automatic test equipment
Authors: Benson H. Scheff
Venue: Communications of the ACM (1966)

For the nonprogrammer, difficulty in using a language increases rapidly with the number of nonproblem-oriented conventions. A simple language, even if inelegant, which considers the user's background as part of the problem may be more effective than a source language containing subtle and more powerful capabilities. The language described in this paper is used to write computer programs which test electronic equipment. Because this testing process contains few complex ideas, there is little need for the elegance and redundancy of a highly syntax-oriented language. A simple and direct language will suffice for the problem. The eventual users of this language are military depot personnel who cannot be expected to have computer programming skill or significant programming training. For this nonprogramming-oriented user, it was essential to create a language using familiar engineering statements; programming-oriented conventions would have unnecessarily complicated his task.
From coarse to fine skin and face detection
Authors: Hichem Sahbi, Nozha Boujemaa
Venue: Proceedings of the eighth ACM international conference on Multimedia (2000)

A method for fine skin and face detection is described that starts from a coarse color segmentation. Some regions represents parts of human skin and are selection by minimizing an error between the color distribution of each region and the output of a compression decompression neural network, which learns skin color distribution for several populations of different ethnicity. This ANN is used to find a collection of skin regions, which is used in a second learning step to provide parameters for a Gaussian mixture model. A finer classification is performed using a Bayesian framework and makes the skin and face detection invariant to scale and lighting conditions. Finally, a face shape based model is used to decide whether a skin region is a face or not.
Easily Testable Multiple-Valued Logic Circuits Derived from Reed-Muller Circuits
Authors: E. V. Dubrova, J. C. Muzio
Venue: IEEE Transactions on Computers (2000)

In 1972, Reddy showed that the binary circuits realizing Reed-Muller canonical form are easily testable. In this paper, we extend Reddy's result to multiple-valued logic circuits, employing more than two discrete levels of signal. The electronic fabrication of such circuits became feasible due to the recent advances in integrated circuit technology. We show that, in the multiple-valued case, several new phenomena occur which allow us to asymptotically reduce the upper bound on the number of tests required for fault detection, but make the generation of tests harder.
Rankin-Cohen Brackets and Invariant Theory
Authors: Y. Choie, B. Mourrain, P. Solé
Venue: Journal of Algebraic Combinatorics: An International Journal (2001)

Using maps due to Ozeki and Brou&eacute;-Enguehard between graded spaces of invariants for certain finite groups and the algebra of modular forms of even weight we equip these invariants spaces with a differential operator which gives them the structure of a Rankin-Cohen algebra. A direct interpretation of the Rankin-Cohen bracket in terms of transvectant for the group i>SL(2, C) is given.
Concept of Nanometric High Density Charge Coupled Devices
Authors: K. Mutamba, A. Sigurdardo´ttir, H. L. Hartnagel
Venue: Analog Integrated Circuits and Signal Processing (2000)

We present a concept of novel ultra-small charge transfer devices based on III-V quantum heterostructures. The device function is based on the possibility of a lateral carrier transmission between low-dimensional structures. The latter can be obtained using material or geometrical confinement. The principal carrier transfer mechanisms are tunneling and thermionic emission with applied voltage. These properties can be used in planar integrated systems to perform storage and logic functions with a high integration density and efficiency. Charge Coupled Device matrix with a density of up to 1000 storage units per \mu\hbox {m}^2 can be obtained. The reduction of the quantum well size to zero dimensional structures will lead to a further increase of the integration density up to the Tbit region.
Multidimensional binary search trees used for associative searching
Authors: Jon Louis Bentley
Venue: Communications of the ACM (1975)

This paper develops the multidimensional binary search tree (or k-d tree, where k is the dimensionality of the search space) as a data structure for storage of information to be retrieved by associative searches. The k-d tree is defined and examples are given. It is shown to be quite efficient in its storage requirements. A significant advantage of this structure is that a single data structure can handle many types of queries very efficiently. Various utility algorithms are developed; their proven average running times in an n record file are: insertion, O(log n); deletion of the root, O(n(k-1)/k); deletion of a random node, O(log n); and optimization (guarantees logarithmic performance of searches), O(n log n). Search algorithms are given for partial match queries with t keys specified [proven maximum running time of O(n(k-t)/k)] and for nearest neighbor queries [empirically observed average running time of O(log n).] These performances far surpass the best currently known algorithms for these tasks. An algorithm is presented to handle any general intersection query. The main focus of this paper is theoretical. It is felt, however, that k-d trees could be quite useful in many applications, and examples of potential uses are given.
Estimation of the defective IDDQ caused by shorts in deep-submicron CMOS ICs
Authors: R. Rodríguez-Montanés, J. Figueras
Venue: Proceedings of the conference on Design, automation and test in Europe (1998)

The defective IDDQ in deep-submicron full complementary MOS circuits with shorts is estimated. High performance and also low power scenarios are considered. The technology scaling, including geometry reductions of the transistor dimensions, power supply voltage reduction, carrier mobility degradation and velocity saturation, is modeled. By means of the characterization of the saturation current of a simple MOSFET, a lower bound of IDDQ defective consumption versus Leff is found. Quiescent current consumption lower bound for shorts intragate, and shorts intergate affecting at least one logic node is evaluated. The methodology is used to estimate the IDDQ distribution, for a given input vector, of defective circuits. This IDDQ estimation allows the determination of the threshold value to be used for the faulty/fault-free circuit classification
A Specification Refinement Methodology for Power Efficient Partitioning of Data-Dominated Algorithms Within Performance Constraints
Authors: K. Masselos, K. Danckaert, F. Catthoor, N. Zervas, C. E. Goutis, H. De Man
Venue: Journal of VLSI Signal Processing Systems (2000)

A specification refinement methodology for the power efficient partitioning of real-time data-dominated algorithms is presented. The main idea of the proposed methodology is the reorganization with respect to data transfer and storage of the initial description of the target algorithm before conventional partitioning. This is achieved through the application of data transfer and storage optimizing high-level code transformations to the initial description of the target algorithm. These transformations basically align the data production and consumption between the different procedures of the initial specification thus reducing the memory size requirements of the system's realizations especially those in the interfaces between different processors. In this way the data transfer and storage related power consumption which forms an important part of the total power budget of a data dominated system is significantly reduced. Performance issues are explicitly taken into account during the application of the data transfer and storage high-level transformations. The proposed methodology can be applied both in a parallel (programmable) processor context and also in heterogeneous hardware-software architectures. The proposed methodology can be also used for the power efficient implementation of data dominated algorithms on architectures based on programmable cores and application specific memory hierarchies. Experimental results from real life applications prove the impact of the proposed methodology.
A multicast-based protocol for IP mobility support
Authors: Ahmed Helmy
Venue: Proceedings of NGC 2000 on Networked group communication (2000)

Several architectures have been recently proposed to support IP mobility. Most studies, however, show that current protocols, in general, fall short from satisfying the performance requirements for audio applications. In this study, we propose a multicast-based protocol to reduce latency and packet loss during handoff and provide the base for IP mobility support. We use extensive simulation to evaluate our protocol's performance over a variety of real and generated topologies, and we compare it to several other mobility protocols, especially the Mobile IP protocols. We take handoff delay estimates and routing efficiency as metrics for our comparisons. We take a route analysis (as opposed to packet analysis) approach in our study, and we apply it in the context of wide-area networks. Our simulation results show significant improvement for our proposed protocol. On average, basic Mobile IP consumes almost twice as much network bandwidth, and experiences more than twice as much end-to-end and handoff delays, as does our proposed protocol. In addition, average handoff delay estimates for our protocol prove to be less than that for other protocols in this study, even with route optimization. We further propose an extension to Mobile IP to support our protocol with minimal modification.
A prototype chip of multicontext FPGA with DRAM for virtual hardware
Authors: Daisuke Kawakami, Yuichro Shibata, Hideharu Amano
Venue: Proceedings of the 2001 Asia and South Pacific Design Automation Conference (2001)

DRAM-type multicontext FPGA is hopeful for Virtual Hardware. Since it is possible to implement a large number of contexts in a single chip. However, it has been reported only a few examples because of the difficulty of mixed process of DRAM and logic. Here we try to implement a prototype multi-context FPGA with DRAM for Virtual Hardware.
Numerically Invariant Signature Curves
Authors: Mireille Boutin
Venue: International Journal of Computer Vision (2000)

Corrected versions of the numerically invariant expressions for the affine and Euclidean signature of a planar curve introduced by Calabi et al. in (Int. J. Comput. Vision, 26: 107&ndash;135, 1998) are presented. The new formulas are valid for fine but otherwise arbitrary partitions of the curve. We also give numerically invariant expressions for the four differential invariants parameterizing the three dimensional version of the Euclidean signature curve, namely the curvature, the torsion and their derivatives with respect to arc length.
Towards knowledge-based digital libraries
Authors: Ling Feng, Marfred A. Jeusfeld, Jeroen Hoppenbrouwers
Venue: ACM SIGMOD Record (2001)

From the standpoint of satisfying human's information needs, the current digital library (DL) systems suffer from the following two shortcomings: (i) inadequate high-level cognition support; (ii) inadequate knowledge sharing facilities. In this article, we introduce a two-layered digital library architecture to support different levels of human cognitive acts. The model moves beyond simple information searching and browsing across multiple repositories, to inquiry of knowledge about the contents of digital libraries. To address users' high- order cognitive requests, we propose an information space consisting of a knowledge subspace and a document subspace. We extend the traditional indexing and searching schema of digital libraries from keyword-based to knowledge-based by adding knowledge to the documents into the DL information space. The distinguished features of such enhanced DL systems in comparison with the traditional knowledge-based systems are also discussed.
Optimizing binary trees grown with a sorting algorithm
Authors: W. A. Martin, D. N. Ness
Venue: Communications of the ACM (1972)

Items can be retrieved from binary trees grown with a form of the Algorithm Quicksort in an average time proportional to log n, where n is the number of items in the tree. The binary trees grown by this algorithm sometimes have some branches longer than others; therefore, it is possible to reduce the average retrieval time by restructuring the tree to make the branches as uniform in length as possible. An algorithm to do this is presented. The use of this algorithm is discussed, and it is compared with another which restructures the tree after each new item is added.
Programming Techniques: An algorithm for the probability of the union of a large number of events
Authors: G. D. Miller
Venue: Communications of the ACM (1968)

An algorithm is presented which efficiently evaluates the probability for the union of n independent and not mutually exclusive events. The problem is that of evaluating the sums of the products of all possible combinations of n variables in minimum time and storage space.
The predictive analyzer and a path elimination technique
Authors: Susumu Kuno
Venue: Communications of the ACM (1965)

Some of the characteristic features of a predictive analyzer, a system of syntactic analysis now operational at Harvard on an IBM 7094, are delineated. The advantages and disadvantages of the system are discussed in comparison to those of an immediate constituent analyzer, developed at the RAND Corporation with Robinson's English grammar. In addition, a new technique is described for repetitive path elimination for a predictive analyzer, which can now claim efficiency both in processing time and core storage requirement.
LR and LL parsing: some new points of view
Authors: Wim Pijls
Venue: ACM SIGCSE Bulletin (2000)

The two best known parsing algorithms are LR and LL parsing respectively. These algorithms are explained extensively in the vast literature on compiler construction and formal language theory. In almost any textbook, LR and LL are regarded as two distinct methods. In this paper we will show that there exists a clear relationship between those methods, putting them into one framework. To our experience, such a framework is very useful from a didactic point of view. Moreover, the relationship between LR and LL provides a deeper insight into each separate method.
Rethinking Deep-Submicron Circuit Design
Authors: Dennis Sylvester, Kurt Keutzer
Venue: Computer (1999)

Several independent sources forecast that in deep-submicron (DSM) process geometries, 80 percent or more of the delays of critical paths will be directly linked to interconnect. This forecast is supported by the significant timing-closure problems that are arising in current high-performance IC designs. Based on this, both industry and academia sense the need for a significant over-haul of current synthesis and physical-design methodologies. In the emerging design scenario, traditional design flows will no longer be viable for any size of module or block of gates. Deep-submicron effects-particularly those relating to interconnects-have thus been billed as potential roadblocks to the continuation of Moore's law. Some effects, like the rising resistance-capacitance (RC) delay of on-chip wiring, noise considerations, reliability concerns, and increased power dissipation, manifest themselves in both the devices (transistors) and the interconnect, though not in ways previously anticipated. The authors consider the effects of both devices and interconnect. Their analysis shows that interconnect delay actually decreases for DSM processes in a modular design approach. The physical explanations of these DSM effects shed insight into this and other potential impacts on future high-performance ASIC designs.
FIASCO&mdash;An Open-Source Fractal Image and Sequence Codec
Authors: Ullrich Hafner
Venue: Linux Journal (2001)

FIASCO provides state-of-the-art image and video compression.
Variable length tree structures having minimum average search time
Authors: Yale N. Patt
Venue: Communications of the ACM (1969)

Sussenguth suggests in a paper (1963) that a file should be organized as a doubly-chained tree structure if it is necessary both to search and to update frequently. Such a structure provides a compromise between the fast search/slow update characteristics of binary searching and the slow search/fast update characteristics of serial searching. His method, however, contains the limiting restriction that all terminal nodes lie on the same level of the tree. This paper considers the effect of relaxing this restriction. First, trees which have the property that a priori the filial set of each node is well defined are studied. It is proved that coding the nodes within each filial set with respect to the number of terminal nodes reachable from each is necessary and sufficient to guarantee minimum average search time. Then the more general case (that is, where the entire structure of the tree is changeable) is treated. A procedure is developed for constructing a tree with a minimum average search time. A simple closed expression for this minimum average search time is obtained as a function of the number of terminal nodes. The storage capacity required to implement the doubly-chained tree structure on a digital computer is also determined. Finally, the total cost of the structure, using Sussenguth's cost criterion, is computed. It is shown that significant improvements in both the average search time and the total cost can be obtained by relaxing Sussenguth's restriction that all terminal nodes lie on the same level of the tree.
A comprehensive look at system level model
Authors: Ken Rose
Venue: Proceedings of the 2001 international workshop on System-level interconnect prediction (2001)

We review system level modeling from our perspective of developing RIPE, the Rensselaer Interconnect-dominated Performance Estimator. RIPE was developed to predict microprocessor performance (clock frequency and power distribution) on the basis of generally available or preliminary estimates of system, technology, and interconnect parameters. Cycle time estimation is the key to determining clock frequency. RIPE 3.0 gave good agreement (10 to 15 % error) with a range of microprocessor architectures. Subsequently, RIPE was extended to determine wiring strategies from performance requirements. This required a detailed wiring distribution and modification of our cycle time model. RIPE 4.0 was calibrated against Intel Pentium II and III processors where the wiring strategy was known. RIPE 4.0 still gave comparable agreement for the same range of processor architectures. The RIPE model incorporates several features that are closely related to processor performance. These include BEOL yield, signal integrity, electromigration, cache performance, and the effects of repeaters and interconnect inductance. Recently, we have developed accurate linear RC models for MOSFETs that allow better projections of the extent to which interconnects will dominate system performance.
Content-Based Image Retrieval at the End of the Early Years
Authors: Arnold W. M. Smeulders, Marcel Worring, Simone Santini, Amarnath Gupta, Ramesh Jain
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (2000)

The paper presents a review of 200 references in content-based image retrieval. The paper starts with discussing the working conditions of content-based retrieval: patterns of use, types of pictures, the role of semantics, and the sensory gap. Subsequent sections discuss computational steps for image retrieval systems. Step one of the review is image processing for retrieval sorted by color, texture, and local geometry. Features for retrieval are discussed next, sorted by: accumulative and global features, salient points, object and shape features, signs, and structural combinations thereof. Similarity of pictures and objects in pictures is reviewed for each of the feature types, in close connection to the types and means of feedback the user of the systems is capable of giving by interaction. We briefly discuss aspects of system engineering: databases, system architecture, and evaluation. In the concluding section, we present our view on: the driving force of the field, the heritage from computer vision, the influence on computer vision, the role of similarity and of interaction, the need for databases, the problem of evaluation, and the role of the semantic gap.
Open artificial intelligence - one course for all
Authors: Matthew Merzbacher
Venue: ACM SIGCSE Bulletin (2001)

Upper-division courses contain some of the most attractive topics in computer science, such as artificial intelligence (AI). Unfortunately, layers of prerequisites restrict AI to advanced computer science students and a separate course for non-majors is not always curricularly feasible. Instead, upper-division AI can be taught in a way that has no prerequisites while retaining the rigor of an upper-division course. This paper includes the syllabus for such an "open AI" course and discusses experiences, positive and negative, with it.
Proposal for an UNCOL
Authors: Melvin E. Conway
Venue: Communications of the ACM (1958)

This discussion contains a proposal for a universal computer-oriented language (UNCOL) to be used as a common path between the problem-oriented language (POL) and the machine language (ML) in compatible automatic programming systems. (See Ref. 1.)
Explicit query formulation with visual keywords
Authors: Joo-Hwee Lim
Venue: Proceedings of the eighth ACM international conference on Multimedia (2000)

This paper presents a novel framework called visual keywords for indexing and retrieving digital images. Visual keywords are flexible and intuitive visual prototypes with semantics. A new query method based on visual constraints allows direct and explicit content specification. Last but not least, we have developed a digital album prototype to demonstrate query and retrieval based on visual keywords.