ppxscal/embedding_network huggingface dataset:
A Modified Chi2 Algorithm for Discretization
Authors: F. E. H. Tay, L. Shen
Venue: IEEE Transactions on Knowledge and Data Engineering (2002)

Since the ChiMerge algorithm was first proposed by Kerber in 1992, it has become a widely used and discussed discretization method. The Chi2 algorithm is a modification to the ChiMerge method. It automates the discretization process by introducing an inconsistency rate as the stopping criterion and it automatically selects the significance value. In addition, it adds a finer phase aimed at feature selection to broaden the applications of the ChiMerge algorithm. However, the Chi2 algorithm does not consider the inaccuracy inherent in ChiMerge's merging criterion. The user-defined inconsistency rate also brings about inaccuracy to the discretization process. These two drawbacks are first discussed in this paper and modifications to overcome them are then proposed. By comparison, results with original Chi2 algorithm using C4.5, the modified Chi2 algorithm, performs better than the original Chi2 algorithm. It becomes a completely automatic discretization method.
A reduced formula for the precise number of (0, 1)-matrices in A (R, S)
Authors: Blanca Rosa Pérez-Salvador, Sergio de-los-Cobos-Silva, Miguel Angel Gutiérrez-Ándrade, Adolfo Torres-Chazaro
Venue: Discrete Mathematics (2002)

A formula that calculates the number of n × m matrices in A(R, S) was presented by Wang (Sci. sinica Ser. A 1 (1988) 1). This formula has 2n - 2n variables. Later, in 1998, a reduced formula was proposed by Wang and Zhang, in which the number of involved variables was reduced to only 2n-1 - n. The reduction in the number of variables is important, but it continues being of order 2n. In this paper a new reduced formula is presented. This formula contains only (n - 2)(n - 1)/2 variables, that is, of order n2.
Odd Even Shifts in SIMD Hypercubes
Authors: S. Ranka, S. Sahni
Venue: IEEE Transactions on Parallel and Distributed Systems (1990)

A linear-time algorithm is developed to perform all odd (even) length circular shifts of data in an SIMD (single-instruction-stream, multiple-data-stream) hypercube. As an application, the algorithm is used to obtain an O(M/sup 2/+log N) time and O(1) memory per processor algorithm to compute the two-dimensional convolution of an N*N image and an M*M template on an N/sup 2/ processor SIMD hypercube. This improves the previous best complexity of O(M/sup 2/ log M+log N).
Reinforcement Learning Agents
Authors: C. Ribeiro
Venue: Artificial Intelligence Review (2002)

Reinforcement Learning (RL) is learning through direct experimentation. It does not assume the existence of a teacher that provides examples upon which learning of a task takes place. Instead, in RL experience is the only teacher. With historical roots on the study of biological conditioned reflexes, RL attracts the interest of Engineers and Computer Scientists because of its theoretical relevance and potential applications in fields as diverse as Operational Research and Intelligent Robotics.Computationally, RL is intended to operate in a learning environment composed by two subjects: the learner and a dynamic process. At successive time steps, the learner makes an observation of the process state, selects an action and applies it back to the process. Its goal is to find out an action policy that controls the behavior of the dynamic process, guided by signals (reinforcements) that indicate how badly or well it has been performing the required task. These signals are usually associated to a dramatic condition &ndash; e.g., accomplishment of a subtask (reward) or complete failure (punishment), and the learner tries to optimize its behavior by using a performance measure (a function of the received reinforcements). The crucial point is that in order to do that, the learner must evaluate the conditions (associations between observed states and chosen actions) that led to rewards or punishments.Starting from basic concepts, this tutorial presents the many flavors of RL algorithms, develops the corresponding mathematical tools, assess their practical limitations and discusses alternatives that have been proposed for applying RL to realistic tasks.
A generic approach to the static analysis of concurrent programs with procedures
Authors: Ahmed Bouajjani, Javier Esparza, Tayssir Touili
Venue: ACM SIGPLAN Notices (2003)

We present a generic aproach to the static analysis of concurrent programs with procedures. We model programs as communicating pushdown systems. It is known that typical dataflow problems for this model are undecidable, because the emptiness problem for the intersection of context-free languages, which is undecidable, can be reduced to them. In this paper we propose an algebraic framework for defining abstractions (upper approximations) of context-free languages. We consider two classes of abstractions: finite-chain abstractions, which are abstractions whose domains do not contain any infinite chains, and commutative abstractions corresponding to classes of languages that contain a word if and only if they contain all its permutations. We show how to compute such approximations by combining automata theoretic techniques with algorithms for solving systems of polynomial inequations in Kleene algebras.
Extreme Programming from a CMM Perspective
Authors: Mark C. Paulk
Venue: IEEE Software (2001)

Extreme Programming has been advocated recently as an appropriate programming method for the high-speed, volatile world of Internet and Web software development. The author reviews XP from the perspective of the Capability Maturity Model for Software, gives overviews of both approaches, and critiques XP from a SW-CMM perspective.He concludes that lightweight methodologies such as XP advocate many good engineering practices and that both perspectives have something to offer the other.
A New Hierarchical Disk Architecture
Authors: Yiming Hu, Qing Yang
Venue: IEEE Micro (1998)

Large RAM caches are generally used to speed up disk accesses. Such caches more effectively improve read performance than write performance, since write requests must be frequently written into disks to protect them from data loss or damage due to system failures. While Non-volatile RAM (NVRAM) caches can be used to improve write performance, large NVRAM caches are too expensive for many applications. This paper presents a new disk cache architecture called DCD, Disk Caching Disks. DCD takes the advantage of large data transfer sizes and uses inexpensive disk space to provide a high-performance, low-cost and reliable caching solution.
Real-World Board Test Effectiveness
Authors: Ed O. Schlotzhauer
Venue: IEEE Design Test (1988)

In-circuit testing is commonly thought to be inefficient for a high level of quality control, and unable to match the high yields of functional testing. A quantitative study of 34,296 boards that represented the testing of 6,671,038 components reveals that in-circuit testing can produce high yields -96.9% in this case. The author looks at this study.
Interdomain Multicast Solutions Guide
Authors: Brian Adams, Tina Fox, Ed Cheng, Andy Kessler, Mark Manzanares, Bryan McLaughlin, Kevin Tran, Jim Rushton
Venue:  (2002)

:A complete interdomain multicast deployment guideConcise design and application information details how to integrate specific IOS(R) feature functionality within an existing network environmentReaders will learn from Cisco(R)-tested and -proven solutions and configuration examplesCommand reference and configuration material serves as a valuable reference toolDemand for IP multicast services to extend applications across Internet service provider (ISP) network boundaries to a wider audience is growing. To meet this need, sophisticated protocols such as Protocol Independent Multicast sparse mode (PIM-SM), Multiprotocol Border Gateway Protocol (MBGP), and Multicast Source Discovery Protocol (MSDP) are available in Cisco IOS software that provide solutions for successfully implementing native interdomain multicast service. Interdomain Multicast Solutions Guide describes how these protocols were used in a tested environment to support interdomain multicast services.The book begins with a technology description that defines IP multicast and summarizes various methods of deploying multicast services. From there, readers are presented two distinct Interdomain Multicast solutions. These two solutions feature complete design and implementation information. The appendix includes a command summary that describes all the Cisco IOS commands discussed in the book. By combining solutions-based ISDs with Cisco IOS configuration and command reference material, Interdomain Multicast Solutions Guide provides customers with a complete Interdomain Multicast deployment guide.
On Uniform Global Error Bounds for Convex Inequalities
Authors: H. Hu
Venue: Journal of Global Optimization (2003)

This paper studies the existence of a uniform global error bound when a convex inequality g &le; 0, where g is a closed proper convex function, is perturbed. The perturbation neighborhoods are defined by small arbitrary perturbations of the epigraph of its conjugate function. Under certain conditions, it is shown that for sufficiently small arbitrary perturbations the perturbed system is solvable and there exists a uniform global error bound if and only if g satisfies the Slater condition and the solution set is bounded or its recession function satisfies the Slater condition. The results are used to derive lower bounds on the distance to ill-posedness.
Optimum Power Assignment for Maximum Throughput in CDMA Personal Communication Systems with Integrated Voice/Data Traffic
Authors: Qiang Shen, Witold A. Krzymien
Venue: Wireless Personal Communications: An International Journal (1998)

A CDMA personal communication system with integrated voice/data traffic is considered, in which the link error performance is controlled according to the voice error rate requirement, and the acceptable data traffic error rate is ensured by ARQ. Optimum power assignment (or allocation) between voice and data users is investigated to maximize the total system throughput. A graphical method (the tangent method) is described to obtain this optimum power allocation. The maximum throughput is expressed as a function of other system parameters. The tangent method is further used to measure the impact of transmission quality on the maximum data throughput. Numerical results and a design example are given for a power controlled wideband IS-95 type wireless personal communication system.
CALiBeR: a software pipelining algorithm for clustered embedded VLIW processors
Authors: Cagdas Akturan, Margarida F. Jacome
Venue: Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design (2001)

In this paper we describe a software pipelining framework, CALiBeR (Cluster Aware Load Balancing Retiming Algorithm), suitable for compilers targeting clustered embedded VLIW processors. CALiBeR can be effectively used by embedded system designers to explore different code optimization alternatives, i.e., can assist the generation of high-quality customized retiming solutions for desired program memory size and throughput requirements, while minimizing register pressure. An extensive set of experimental results is presented, considering several representative benchmark loop kernels and a wide variety of clustered datapath configurations, demonstrating that our algorithm compares favorably with one of the best state-of-the-art algorithms, achieving up to 50% improvement in performance and up to 47% improvement in register requirements.
Embedding path designs in 4-cycle systems
Authors: Gaetano Quattrocchi
Venue: Discrete Mathematics (2002)

Let (W,C) be an m-cycle system of order n and let Ω ⊆ W, |Ω| = υ ≤ n. We say that a path design (Ω, P) of order υ and block size s (2 ≤ s ≤ m - 1) is embedded in (W,C) if for every p ∈ P there is an m-cycle c = (a1,a2, .... ,am) ∈ C such that: (1) p = [ak,ak+1,....,ak+s-1] for some k ∈ {1,2 ...,m} (i.e. the (s - 1)-path p occurs in the m-cycle c); and (2) ak-1,ak+s ∈ Ω. Note that in (1) and (2) all the indices are reduced to the range {1,...,m} (mod m). For each n ≡ 1(mod8) and for each s ∈ {2,3}, the spectrum of all the integers υ such that there is a handcuffed design of order υ and block size s embedded in a 4-cycle system of order n is determined in Milici and Quattrocchi (Discrete Math. 208/209 (1999) 443-449). In this paper, we want to complete the case m = 4 by determining the set of all the integers υ such that there is a path design of order υ and block size 3 embedded in a 4-cycle system of order n.
Improving the performance of DSM systems via compiler involvement
Authors: Ravi Mirchandaney, Seema Hiranandani, Ajay Sethi
Venue: Proceedings of the 1994 ACM/IEEE conference on Supercomputing (1994)

Distributed shared memory (DSM) systems provide an illusion of shared memory on distributed memory systems such as workstation networks and some parallel computers such as the Cray T3D and Convex SPP-1. This illusion is provided either by enhancements to hardware, software, or a combination thereof. On these systems, users can write programs using a shared memory style of programming instead of message passing which is tedious and error prone. Our experience with one such system, TreadMarks, has shown that a large class of applications does not perform well on these systems. TreadMarks is a software distributed shared memory system designed by Rice University researchers to run on networks of workstations and massively parallel computers. Due to the distributed nature of the memory system, shared memory synchronization primitives such as locks and barriers often cause significant amounts of communication.We have provided a set of powerful primitives that will alleviate the problems with locks and barriers on such systems. We have designed two sets of primitives, the first set maintains coherence and is easy to use by a programmer, the second set does not maintain coherence and is best used by a compiler. These primitives require that the underlying DSM be enhanced. We have implemented some of our primitives on the TreadMarks DSM system and obtained reasonable performance improvements on application kernels from molecular dynamics and numerical analysis. Furthermore, we have identified key compiler optimizations that use the non-coherent primitives to reduce synchronization overhead and improve the performance of DSM systems.
Activity patterns in health care: identifying building blocks for the CPR
Authors: Nathalie Habing, Jan Dietz, Berti Zwetsloot-Schonk
Venue: ACM SIGGROUP Bulletin (2001)

Concerning the development and adoption of the computer-based patient record (CPR), an unsolved problem is still the approach that should be taken to construct a highly configurable, generic CPR. The first step in finding such an approach, is the identification of generic activity patterns. These are considered to be helpful in the identification of components. We identified twelve generic activity patterns in the interaction between a patient and a care-cluster.
A Visualization Tool for Y2K
Authors: Stephen G. Eick
Venue: Computer (1998)

To facilitate Y2K conversions, Bell Laboratories has developed a Y2K visualization tool. The input to the tool is the output of commercially available Cobol parsing tools that identify lines potentially affected by Y2K. While these tools are extremely useful, their output is daunting. Presenting this output visually increases assessment productivity by as much as 80 percent. Visualization also improves conversion quality by suggesting more-informed and efficient repair strategies. This visualization tool is based on the idea that no one view is sufficient to answer important questions concerning Y2K. It therefore provides a suite of tightly coupled, linked views. Each view is engineered for a particular task, is interactive, and is used for both display and analysis. Linking between views causes interactive operations to propagate instantly in each view. The authors report that the results to date have been promising. In one case, the time required for assessment and conversion strategy development dropped from three weeks to three days.
Plane graphs with Eulerian Petrie walks
Authors: Arjana Zitnik
Venue: Discrete Mathematics (2002)

A Petrie walk in a plane graph G is obtained by walking on edges of G, alternatingly selecting as next edge the left edge and the right edge of the current edge in the rotation of edges around the common vertex. We give a characterization of 4-valent plane graphs with Eulerian Petrie walks, which gives rise to a simple algorithm for constructing such graphs. This algorithm is then used to answer the question whether or not there exist 4-valent plane graphs with Eulerian Petrie walks and faces of prescribed sizes.
Streaming-Media Knowledge Discovery
Authors: Jan Pieper, Savitha Srinivasan, Byron Dom
Venue: Computer (2001)

The Multimedia Knowledge Discovery group at IBM Almaden Research Center explores technologies that help locate streaming media on the Web, build effective indexing and classification tools for streaming media, and develop compelling streaming-media applications. The authors' ongoing work, motivated by the Web's role as an ever-increasing information source and knowledge repository, focuses on locating, analyzing, and indexing Web-based streaming media.Frequently, knowledge management applications and information portals synthesize unstructured text information from the Web, intranets, and partner sites. Given this context, the authors routinely crawl a statistically significant number of Web pages, detect those that contain streaming-media links, crawl the media links to extract associated metadata, then use the crawl data to build a resource list for Web media. They have used these crawl data findings to build a media indexing application that uses content-based indexing methods.Searching multiple live-broadcast channels with the indexing application lets users locate relevant multimedia resources on the Web. Providing on-demand access to these media reduces the time spent consuming nonrelevant information from a streaming-media channel.Work on indexing video archives inspires several directions for future research. For example, existing genre-classification and topic-detection methods require processing and analyzing large parts of a document, which presents a greater challenge when performed on live streams. Scalability plays an important role in deploying such systems, given the amount of computation required for simultaneous processing of multiple live streams. Fortunately, rapid progress in hardware and networking will enable deployment of such systems soon.
How to Speed Development with Group Sessions
Venue: IEEE Software (1990)

No abstract available
Optimization of Machine Descriptions for Efficient Use
Authors: John C. Gyllenhaal, Wen-Mei W. Hwu, B. Ramakrishna Rau
Venue: International Journal of Parallel Programming (1998)

A machine description facility allows compiler writers to specify machine execution constraints to the optimization and scheduling phases of an instructionlevel parallelism (ILP) optimizing compiler. The machine description (MDES) facility should support quick development and easy maintenance of machine execution constraint descriptions by compiler writers. However, the facility should also allow compact representation and efficient usage of the MDES during compilation. This paper advocates a model that allows compiler writers to develop the MDES in a high-level language, which is then translated into a low-level representation for efficient use by the compiler. The discrepancy between the requirements of the high-level language and the low-level representation is reconciled with a collection of transformations that derive efficient lowlevel representations from the easy-to-understand high-level descriptions. In order to support these transformations, a novel approach to representing machine execution constraints has been developed. Detailed and precise descriptions of the execution constraints for the HP PA7100, Intel Pentium, SUN SuperSPARC, and AMD-K5 processors, as well as two hypothetical wider-issue processor configurations, are analyzed to show the advantage of using this new representation. The results show that performing these transformations and utilizing the new representation allow easy-to-maintain detailed descriptions written in high-level languages to be efficiently used by ILP-optimizing compilers.
A mean-field model for multiple TCP connections through a buffer implementing RED
Authors: F. Baccelli, D. R. McDonald, J. Reynier
Venue: Performance Evaluation (2002)

Active queue management schemes like RED (random early detection) have been suggested when multiple TCP sessions are multiplexed through a bottleneck buffer. The idea is to detect congestion before the buffer overflows and packets are lost. When the queue length reaches a certain threshold RED schemes drop/mark incoming packets with a probability that increases as the queue size increases. The objectives are an equitable distribution of packet loss, reduced delay and delay variation and improved network utilization.Here we model multiple connections maintained in the congestion avoidance regime by the RED mechanism. The window sizes of each TCP session evolve like independent dynamical systems coupled by the queue length at the buffer. We introduce a mean-field approximation to one such RED system as the number of flows tends to infinity. The deterministic limiting system is described by a transport equation. The numerical solution of the limiting system is found to provide a good description of the evolution of the distribution of the window sizes, the average queue size, the average loss rate per connection and the total throughput. TCP with RED or tail-drop may exhibit limit cycles and this causes unnecessary packet delay variation and variable loss rates. The root cause of these limit cycles is the hysteresis due to the round trip time delay in reacting to a packet loss.
Performance evaluation: integrating techniques and tools into environments and frameworks
Authors: Diane T. Rover
Venue: Proceedings of the 1994 ACM/IEEE conference on Supercomputing (1994)

The techniques and tools that have been developed for the performance evaluation of parallel and distributed computing systems are manifold. This is appealing, since no single technique or tool will be sufficient. However, there is a lack of integration of tools in the form of environments and frameworks, which hinders the development of well-defined methodologies for obtaining optimal performance and answering users' performance questions. This roundtable considers the issues surrounding tool integration and interoperability. Perhaps the dominant issue is whether this area is mature enough for prescribed frameworks to be successfully implemented and consistently adhered to: should the focus be on making sure each tool works, or can it shift to making sure tools can work together? The participants will address the advantages and disadvantages, practicalities, recent history, and future of tool integration in high-performance computing.
An Ultra Small Individual Recognition Security Chip
Authors: Kazuo Takaragi, Mitsuo Usami, Ryo Imura, Rei Itsuki, Tsuneo Satoh
Venue: IEEE Micro (2001)

The manufacture and distribution of goods requires good quality and inventory control. The RFID-enabled µ-chip's small size and low cost make it suitable for attachment to paper media and small products, aiding counterfeit prevention and product tracking in market environments.