ppxscal/embedding_network huggingface dataset:
Towards the Correctness and Consistency of Update Semantics in Semantic Database Schema
Authors: Joan Peckham, Fred Maryanski, Steven A. Demurjian
Venue: IEEE Transactions on Knowledge and Data Engineering (1996)

This paper discusses a paradigm and prototype system for the design-time expression, checking, and automatic implementation of the semantics of database updates. Here, enforcement rules are viewed as the implementation of constraints and are specified, checked for consistency, and then finally mapped to object-oriented code during database design. A classification of enforcement rule types is provided as a basis for these design activities, and the general strategy for specification, analysis, and implementation of these rules within a semantic modeling paradigm is discussed. SORAC (semantic, objects, relationships, and constraints), a prototype database design system at the University of Rhode Island, is also described.
Continuations Revisited
Authors: Christopher P. Wadsworth
Venue: Higher-Order and Symbolic Computation (2000)

To introduce the republication of his joint 1974 paper with Christopher Strachey, &ldquo;Continuations: A Mathematical Semantics for Handling Full Jumps&rdquo;, the author recalls earlier unsuccessful struggles which culminated eventually in the almost instantaneous insight for their discovery of continuations in 1970.
Fitting multiplicative models by robust alternating regressions
Authors: C. Croux, P. Filzmoser, G. Pison, P. J. Rousseeuw
Venue: Statistics and Computing (2003)

In this paper a robust approach for fitting multiplicative models is presented. Focus is on the factor analysis model, where we will estimate factor loadings and scores by a robust alternating regression algorithm. The approach is highly robust, and also works well when there are more variables than observations. The technique yields a robust biplot, depicting the interaction structure between individuals and variables. This biplot is not predetermined by outliers, which can be retrieved from the residual plot. Also provided is an accompanying robust R2-plot to determine the appropriate number of factors. The approach is illustrated by real and artificial examples and compared with factor analysis based on robust covariance matrix estimators. The same estimation technique can fit models with both additive and multiplicative effects (FANOVA models) to two-way tables, thereby extending the median polish technique.
Exploiting Value Locality to Exceed the Dataflow Limit
Authors: Mikko H. Lipasti, John Paul Shen
Venue: International Journal of Parallel Programming (1998)

The serialization constraints imposed by true data dependences have always been regarded as an absolute dataflow limit on the parallel execution of serial programs. This paper describes value prediction, a new technique that allows data dependent instructions to issue and execute in parallel without violating program semantics. This technique exploits value locality, or the likelihood of the recurrence of a previously-seen value within a storage location inside a computer system. Value prediction consists of predicting entire 32- and 64-bit register values based on previously-seen values. We find that values loaded from memory or generated by ALU instructions are frequently predictable. Furthermore, we show that simple microarchitectural enhancements to a modern microprocessor implementation based on the PowerPC 620 that enable value prediction can effectively exploit value locality to collapse true dependences, reduce average memory and result latencies, and provide average performance gains of 3%-23% by exceeding the dataflow limit.
Area Time Trade-Offs in Micro-Grain VLSI Array Architectures
Authors: R. Singh Bajwa, R. M. Owens, M. J. Irwin
Venue: IEEE Transactions on Computers (1994)

We study the relative performance of three different massively parallel fine-grain, VLSI, control-flow architectures. The processor architectures being considered are: an associative memory architecture, a Mux-based SIMD architecture and a modification of the Mux-based architecture using RAMs making it suitable for systolic MIMD/MISD computation. All three architectures are organized as two-dimensional, near-neighbor mesh connected, array of processors. All three are very similar in their construction, and in their control and data-flow requirements. The custom hardware for all three architectures was built using the same technology. We compare and contrast the performance of these three VLSI architectures for a select set of applications. To evaluate the computational power of the three architectures we use the area time product, AT, as the metric. The three designs are known to perform well in their niche applications and we find that for non-niche applications all three designs are comparable in power to within a small constant factor. The performance of the Mux-based SIMD architecture is better in general than the other two in terms of speed though the associative architecture is found to out-perform the SIMD architecture for certain numeric applications like the FFT and matrix multiplication in the AT sense.
Testing Finite-State Machines: State Identification and Verification
Authors: D. Lee, M. Yannakakis
Venue: IEEE Transactions on Computers (1994)

We study the complexity of two fundamental problems in the testing of finite-state machines. 1) Distinguishing sequences (state identification). We show that it is PSPACE-complete to determine whether a finite-state machine has a preset distinguishing sequence. There are machines that have distinguishing sequences, but only of exponential length. We give a polynomial time algorithm that determines whether a finite-state machine has an adaptive distinguishing sequence. (The previous classical algorithms take exponential time.) Furthermore, if there is an adaptive distinguishing sequence, then we give an efficient algorithm that constructs such a sequence of length at most n(n/spl minus/1)/2 (which is the best possible), where n is the number of states. 2) Unique input output sequences (state verification). It is PSPACE-complete to determine whether a state of a machine has a unique input output sequence. There are machines whose states have unique input output sequences but only of exponential length.
TetFusion: an algorithm for rapid tetrahedral mesh simplification
Authors: Prashant Chopra, Joerg Meyer
Venue: Proceedings of the conference on Visualization '02 (2002)

This paper introduces an algorithm for rapid progressive simplification of tetrahedral meshes: TetFusion. We describe how a simple geometry decimation operation steers a rapid and controlled progressive simplification of tetrahedral meshes, while also taking care of complex mesh-inconsistency problems. The algorithm features a high decimation ratio per step, and inherently discourages any cases of self-intersection of boundary, element-boundary intersection at concave boundary-regions, and negative volume tetrahedra (flipping). We achieved rigorous reduction ratios of up to 98% for meshes consisting of 827,904 elements in less than 2 minutes, progressing through a series of level-of-details (LoDs) of the mesh in a controlled manner. We describe how the approach supports a balanced re-distribution of space between tetrahedral elements, and explain some useful control parameters that make it faster and more intuitive than 'edge collapse'-based decimation methods for volumetric meshes [3, 19, 21, 22]. Finally, we discuss how this approach can be employed for rapid LoD prototyping of large time-varying datasets as an aid to interactive visualization.
Software-Based Replication for Fault Tolerance
Authors: Rachid Guerraoui, André Schiper
Venue: Computer (1997)

Developers of early distributed systems took a simplistic approach to providing fault tolerance: They just used another copy of the same hardware as a backup. Later, others developed replication software to work on off-the-shelf hardware. Since neither of these methods is especially economical, a logical course is to take it one step further and eliminate the extra hardware altogether. Fully software-based replication relies on sophisticated techniques to keep track of server communications and ensure the consistency of information across several server replicas. How do you know that each server shares the same view of the data or program semantics? What happens if a server replica crashes? How do you make sure that a system processes invocations in the correct order? These are all problems that a replication technique has to handle. The authors describe two fundamental techniques, primary-backup and active replication, and illustrate how they handle these problems. At this point, both have advantages and disadvantages that depend on the application. The authors also propose that group communication provides a sufficient framework for implementing software-based replication. The concept of static and dynamic groups proves useful in thinking about how to implement replication techniques. Replication techniques can also use total-order and view-synchronous multicast primitives from group communication.
Practical Applications of Statistical Process Control
Authors: Edward F. Weller
Venue: IEEE Software (2000)

Applying quantitative methods and statistical process control to software development projects can provide a positive cost-benefit return. The author used quantitative analysis of inspection and test data to assess product quality during testing and to predict post-ship product quality for a major software release.
A system for synthesizing optimized FPGA hardware from MATLAB
Authors: Malay Haldar, Anshuman Nayak, Alok Choudhary, Prith Banerjee
Venue: Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design (2001)

Efficient high level design tools that can map behavioral descriptions to FPGA architectures are one of the key requirements to fully leverage FPGA for high throughput computations and meet time-to-market pressures. We present a compiler that takes as input algorithms described in MATLAB and generates RTL VHDL. The RTL VHDL then can be mapped to FPGAs using existing commercial tools. The input application is mapped to multiple FPGAs by parallelizing the application and embedding communication and synchronization primitives automatically. Our compiler infers the minimum number of bits required to represent the variable through a precision analysis framework. The compiler can leverage optimized IP cores to enhance the hardware generated. The compiler also exploits parallelism in the input algorithm by pipelining in the presence of resource constraints. We demonstrate the utility of the compiler by synthesizing hardware for a couple of signal/image processing algorithms and comparing them with manually designed hardware.
Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST
Authors: Hua-Guo Liang, Sybille Hellebrand, Hans-Joachim Wunderlich
Venue: Journal of Electronic Testing: Theory and Applications (2002)

In this paper a novel architecture for scan-based mixed mode BIST is presented. To reduce the storage requirements for the deterministic patterns it relies on a two-dimensional compression scheme, which combines the advantages of known vertical and horizontal compression techniques. To reduce both the number of patterns to be stored and the number of bits to be stored for each pattern, deterministic test cubes are encoded as seeds of an LFSR (horizontal compression), and the seeds are again compressed into seeds of a folding counter sequence (vertical compression). The proposed BIST architecture is fully compatible with standard scan design, simple and flexible, so that sharing between several logic cores is possible. Experimental results show that the proposed scheme requires less test data storage than previously published approaches providing the same flexibility and scan compatibility.
A scalable high-performance environment for fluid flow analysis on unstructured grids
Authors: Deb Banerjee, Thomas Tysinger, Wayne Smith
Venue: Proceedings of the 1994 ACM/IEEE conference on Supercomputing (1994)

This paper describes an integrated environment for the analysis and solution of fluid flow problems, and contains a Computational Fluid Dynamics (CFD) solver and visualization system as its major components. The flow solver is capable of solving the Navier-Stokes equations about complex geometries through the use of unstructured, solution adaptable, grids. Unlike post-processing visualization environments, the visualization system is designed to work in a co-processing mode with the CFD application. This significantly reduces data storage and data movement requirements for visualization and also allows the user to interactively steer the application. The solver and visualization system have been implemented on massively parallel computers, multiple processor workstations, and workstation clusters. The user can run the flow simulation on a remote compute server and interactively observe results and control the simulation from a desktop workstation. The system provides Scheme, a high-level interpreted language, for extending and customizing the environment from the text user-interface. Timings on an MPP and workstation cluster are presented to demonstrate the solver's scalability, and a case study of the flow over an F-18 aircraft is included to illustrate how the environment is used on a real-world problem.
Energy-aware design of embedded memories: A survey of technologies, architectures, and optimization techniques
Authors: Luca Benini, Alberto Macii, Massimo Poncino
Venue: ACM Transactions on Embedded Computing Systems (TECS) (2003)

Embedded systems are often designed under stringent energy consumption budgets, to limit heat generation and battery size. Since memory systems consume a significant amount of energy to store and to forward data, it is then imperative to balance power consumption and performance in memory system design. Contemporary system design focuses on the trade-off between performance and energy consumption in processing and storage units, as well as in their interconnections. Although memory design is as important as processor design in achieving the desired design objectives, the former topic has received less attention than the latter in the literature. This article centers on one of the most outstanding problems in chip design for embedded applications. It guides the reader through different memory technologies and architectures, and it reviews the most successful strategies for optimizing them in the power/performance plane.
A Comparison of Mizar and Isar
Authors: Markus Wenzel, Freek Wiedijk
Venue: Journal of Automated Reasoning (2003)

The mathematical proof checker Mizar by Andrzej Trybulec uses a proof input language that is much more readable than the input languages of most other proof assistants. This system also differs in many other respects from most current systems. John Harrison has shown that one can have a Mizar mode on top of a tactical prover, allowing one to combine a mathematical proof language with other styles of proof checking. Currently the only fully developed Mizar mode in this style is the Isar proof language for the Isabelle theorem prover. In fact the Isar language has become the official input language to the Isabelle system, even though many users still use its low-level tactical part only. In this paper we compare Mizar and Isar. A small example, Euclid's proof of the existence of infinitely many primes, is shown in both systems. We also include slightly higher-level views of formal proof sketches. Moreover, a list of differences between Mizar and Isar is presented, highlighting the strengths of both systems from the perspective of end-users. Finally, we point out some key differences of the internal mechanisms of structured proof processing in either system.
The Knowledge Acquisition and Representation Language, KARL
Authors: Dieter Fensel, Jürgen Angele, Rudi Studer
Venue: IEEE Transactions on Knowledge and Data Engineering (1998)

The Knowledge Acquisition and Representation Language (KARL) combines a description of a knowledge-based system at the conceptual level (a so-called model of expertise) with a description at a formal and executable level. Thus, KARL allows the precise and unique specification of the functionality of a knowledge-based system independent of any implementation details. A KARL model of expertise contains the description of domain knowledge, inference knowledge, and procedural control knowledge. For capturing these different types of knowledge, KARL provides corresponding modeling primitives based on Frame-Logic and Dynamic Logic. A declarative semantics for a complete KARL model of expertise is given by a combination of these two types of logic. In addition, an operational definition of this semantics, which relies on a fixpoint approach, is given. This operational semantics defines the basis for the implementation of the KARL interpreter, which includes appropriate algorithms for efficiently executing KARL specifications. This enables the evaluation of KARL specifications by means of testing.
Systems Programming in Java
Authors: Stuart Ritchie
Venue: IEEE Micro (1997)

The Java programming language has been widely accepted as a general-purpose language for developing portable applications, toolkits, and applets. With so much activity in industry and academia in these user-level areas, is it surprising that Java is also an equally capable systems-programming language? This article describes our experiences at JavaSoft of using Java as a systems-level programming language during the development of JavaOS. I discuss our motivations for using Java and show code examples to demonstrate various system-level primitives, including an Ethernet device driver.
Multiprocessors Should Support Simple Memory-Consistency Models
Authors: Mark D. Hill
Venue: Computer (1998)

In the future, many computers will contain multiple processors, in part because the marginal cost of adding a few additional processors is so low that only minimal performance gain is needed to make the additional processors cost-effective. Intel, for example, now makes cards containing four Pentium Pro processors that can easily be incorporated into a system. Multiple-processor cards like Intel's will help multiprocessing spread from servers to the desktop. But how will these multiprocessors be programmed? The evolution of the programming model is already under way. One important function of the programming model is to describe how memory operates. For a multiprocessor, a reasonable model is sequential consistency (SC), which makes a multiprocessor behave like a multitasking uni-processor. Nevertheless, many commercial multiprocessors support more relaxed memory models. The author argues that multiprocessors should support SC because--with speculative execution-- relaxed models do not provide sufficient additional performance to justify exposing their complexity to the authors of low-level software.
TCP Switching: Exposing Circuits to IP
Authors: Pablo Molinero-Fernández, Nick McKeown
Venue: IEEE Micro (2002)

A simple technique could eliminate choke points on the Internet. TCP switching-which integrates circuit switching benefits in the packet-switched Internet-demonstrates the possibilities.
Interleaving a Join Sequence with Semijoins in Distributed Query Processing
Authors: M. S. Chen, P. S. Yu
Venue: IEEE Transactions on Parallel and Distributed Systems (1992)

The problem of combining join and semijoin reducers for distributed query processing is studied. An approach based on interleaving a join sequence with beneficial semijoins is proposed. A join sequence is mapped into a join sequence tree first. The join sequence tree provides an efficient way to identify for each semijoin its correlated semijoins as well as its reducible relations under the join sequence. In light of these properties, an algorithm for determining an effective sequence of join and semijoin reducers is developed. Examples are given to illustrate the results. They show the advantage of using a combination of joins and semijoins as reducers for distributed query processing.
Validating Voice Communication Requirements Using Lightweight Formal Methods
Authors: Johann Hörl, Bernhard K. Aichernig
Venue: IEEE Software (2000)

To show that lightweight approaches can facilitate the technological transfer of formal development methods, the authors report on their experiences using VDM++ to specify a safety-critical air traffic control voice communication system. Their approach raised both the quality of the informal system specification as well as the efficiency of the system test suites they used.
A Data Mining Approach to Characterizing Medical Code Usage Patterns
Authors: William E. Spangler, Jerrold H. May, David P. Strum, Luis G. Vargas
Venue: Journal of Medical Systems (2002)

This research describes a synthetic data mining approach to identifying diagnostic (ICD-9) and procedure (CPT) code usage patterns in two U.S. hospitals, with the goal of determining the adequacy and effectiveness of the current coding classification systems. We combine relative frequency measurements with measures of industry concentration borrowed from industrial economics in order to (1) ascertain the extent to which physicians utilize the available codes in classifying patients and (2) discover the factors that impinge on code usage. Our results partition the domain into areas for which the coding systems perform well and those areas for which the systems perform relatively poorly. The goal is to use this approach to understand how coding systems are used and to highlight areas for targeted improvement of the current coding systems.
Hierarchical interconnect circuit models
Authors: Michael Beattie, Satrajit Gupta, Lawrence Pileggi
Venue: Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design (2000)

The increasing size of integrated systems combined with deep submicron physical modeling details creates an explosion in RLC interconnect modeling complexity of unmanageable proportions. Interconnect extraction tools employ hierarchy to manage complexity, but this hierarchy is discarded via eliminating far away coupling terms when the equivalent RLC circuits are formed. The increasing dominance of capacitance coupling along with the emergence of on-chip inductance, however, makes the composite effect of far-away couplings increasingly evident. Even if newly enforced design rules and practices will ultimately obviate the need for modeling these couplings for design verification, some approximation of the "exact" solution is required to validate these rules. This paper proposes an efficient hierarchical equivalent circuit representation of interconnect parasitics that utilizes the efficient hierarchical long-distance modeling already existing within extractors. Results from a prototype simulator based on these hierarchical models demonstrates the simulation inaccuracy incurred when the far-away coupling terms are ignored. Such a form of interconnect modeling may provide the key to hierarchical modeling of electro-magnetic interactions between large components on future gigascale systems.
Classification and Compilation of Linear Recursive Queries in Deductive Databases
Authors: C. Youn, H. -J. Kim, L. J. Henschen, J. Han
Venue: IEEE Transactions on Knowledge and Data Engineering (1992)

The authors present a graph model which is powerful in classifying and compiling linear recursive formulas in deductive databases. The graph model consists of two kinds of graphs: I-graph and resolution graph. Essential properties of a recursive formula can be extracted from its I-graph, and the compiled formula and the query evaluation plan of the recursive formulas can be determined from its resolution graph. It is demonstrated that based on the graph model all the linear recursive formulas can be classified into a taxonomy of classes and each class shares common characteristics in query compilation and query processing. The compiled formulas and the corresponding query evaluation plans can be derived based on the study of the compilation of each class.