ppxscal/embedding_network huggingface dataset:
Design Considerations for a General-Purpose Microprocessor
Authors: Benjamin Maytal, Dan Biran, Sorin Iacobovici, Jonathan Levy, Donald B. Alpert, Sidi Yom Tov
Venue: Computer (1989)

The authors examine the performance, cost, and schedule tradeoffs made for the NS 32532, a 32-bit general-purpose microprocessor. Among its features are a 30-MHz clock frequency, three on-chip caches, a four-stage pipeline, and dedicated mechanisms for multiprocessing support. The authors describe the design constraints set by the VLSI processing and packaging technologies. They address the issue of market requirements by examining the software and hardware considerations for the microprocessor's target applications. After describing the functional partitioning choices, including the means for supporting a memory hierarchy and floating-point operations, they present the NS32532's microarchitecture. They then examine the microprocessor's system interface, the memory reference transactions, and the instruction-flow and data-flow monitoring mechanisms. Finally, the authors present an overview of the methodology adopted to accomplish the design within a strict schedule while achieving full functionality and meeting cost and performance goals.
Message pattern specifications: a new technique for handling errors in parallel object oriented systems
Authors: Jan A. Purchase, Russel L. Winder
Venue: ACM SIGPLAN Notices (1990)

As object oriented techniques enable the fabrication of ever more sophisticated systems, the need grows for a mechanism to ensure the consistent and 'correct' behaviour of each object at run-time. We describe a new, in-source specification mechanism, Message Pattern Specifications (MPS), to directly satisfy this need in a succinct, orthogonal and disciplined manner. Targeted for use in parallel object oriented systems, MPS allows programmers to enunciate the 'legal' patterns of run-time behaviour in which their objects may engage. Furthermore, it supports the definition of methods for object recovery or graceful failure in case these specifications are violated during execution.
Multiple-transform pipelines for image coding
Authors: A. Antola
Venue: Proceedings of the 2nd international conference on Supercomputing (1988)

Pipelined VLSI/WSI architectures supporting image coding transforms are defined and evaluated in the paper. The structures proposed in the paper have been derived by considering a common algorithmic kernel of the set of examined transforms. The possibility of reducing the computations to a common algorithmic version allows definition of flexible structures characterized by a &ldquo;basic&rdquo; pipeline - performing the common kernel of computation - and by transform-dependent input and output stages. Three different pipelines have been defined and figures of merit, such as silicon area occupation and throughput, have been evaluated for architectures comparisons.
Requirements analysis for Ada compilers
Authors: Peter J. L. Wallis, Brian A. Wichmann
Venue: Communications of the ACM (1984)

A Guide to the Selection and Specification of Ada Compilers was recently produced by the Portability Working Group of Ada-Europe. Most of the points addressed are applicable criteria for evaluation of any language compiler.
Automatic discovery of parallelism: a tool and an experiment (extended abstract)
Authors: Michael Burke, Ron Cytron, Jeanne Ferrante, Wilson Hsieh, Vivek Sarkar, David Shields
Venue: Proceedings of the ACM/SIGPLAN conference on Parallel programming: experience with applications, languages and systems (1988)

This paper reports preliminary results from applying advanced techniques to the parallelization of sequential programs. Such techniques include interprocedural analysis and the identification of nested parallelism. These techniques have been proposed for exploiting the greater concurrency offered by multiprocessors as compared with vector architectures. The effectiveness of these techniques as applied to some popular numerical Fortran programs is examined. Although extrapolation is difficult, these preliminary results are encouraging indicators of the success of these techniques.
Fault-Tolerant Array Processors Using Single-Track Switches
Authors: S.-Y. Kung, S.-N. Jean, C.-W. Chang
Venue: IEEE Transactions on Computers (1989)

An array grid model based on single-track switches is proposed. A reconfigurability theorem is developed to provide the theoretical footing for novel reconfiguration algorithms for the fabrication-time and run-time processing. For fabrication-time yield enhancement, the problem of finding a feasible reconfiguration using global control can be reformulated as a maximum independent set problem. An existing algorithm in graph theory is adopted to solve this problem. The simulations conducted indicate that the algorithm is computationally very efficient; therefore, it may also be applicable to certain run-time fault tolerance. In real-time fault tolerance, the propagation time of data/control signals between the host computer incurred in the global control is often prohibitively long; therefore, only distributed processing is feasible. Based on the same reconfigurability theorem, a distributive reconfiguration algorithm is developed for (asynchronous) array processors.
Interprocedural side-effect analysis in linear time
Authors: K. D. Cooper, K. Kennedy
Venue: Proceedings of the ACM SIGPLAN 1988 conference on Programming Language design and Implementation (1988)

We present a new method for solving Banning's alias-free flow-insensitive side-effect analysis problem. The algorithm employs a new data structure, called the binding multi-graph, along with depth-first search to achieve a running time that is linear in the size of the call multi-graph of the program. This method can be extended to produce fast algorithms for data-flow problems with more complex lattice structures.
Inversion in finite fields using logarithmic depth
Authors: Joachim von zur Gathen
Venue: Journal of Symbolic Computation (1990)

Litow & Davida (1988) show that inverses in large finite fields of small characteristicp, say p=2, can be computed by Boolean circuits of (order-optimal) logarithmic depth. We note that their numerical approach can also be implemented purely algebraically, and that the resulting much simpler algorithm yields, also for large p, both arithmetic and Boolean reductions of inversion in F"p"n to inversion in F"p.
Performance Analysis of Mass Storage Service Alternatives for Distributed Systems
Authors: K. K. Ramakrishnan, Joel S. Emer
Venue: IEEE Transactions on Software Engineering (1989)

The authors consider the performance of alternative mass-storage services for a client-server-style distributed system. Some qualitative arguments are presented on the ramifications of implementations of mass-storage services at various levels of the storagesemantics hierarchy. The authors concentrate, in particular, on contrasting disk and file services. The functionalities of disk and file services are distinguished by their primitive operations: individual disk-block access for the disk service, and individual file-block access for the file service. This difference results in different partitionings of the computation between the client and server, as well as different network communication requirements. To understand the ramifications of such differences between the services, the authors present performance estimates for basic disk and file services. Performance estimates for several design alternatives are presented.
Hypercube performance for 2-D seismic finite-difference modeling
Authors: L. J. Baker
Venue: Proceedings of the third conference on Hypercube concurrent computers and applications - Volume 2 (1989)

Wave-equation seismic modeling in two space dimensions is computationally intensive, often requiring hours of supercomputer CPU time to run typical geological models with 500 &times; 500 grids and 100 sources. This paper analyzes the performance of ACOUS2D, an explicit 4th-order finite-difference program, on Intel's 16-processor vector hypercube computer. The conversion of the sequential version of ACOUS2D to run on hypercube was straightforward, but time-consuming. The key consideration for optimal efficiency is load balancing. On a fairly typical geologic model, the 16-processor Intel vector hypercube computer ran ACOUS2D at 1/3 the speed of a Cray-1S.
A fast algorithm for code movement optimisation
Authors: D. M. Dhamdhere
Venue: ACM SIGPLAN Notices (1988)

Code optimisation algorithms using bi-directional data flow dependencies have become increasingly important in recent years. The use of these algorithms faces two difficulties in practice: (a) Low profitabilities, and (b) high solution costs. This paper develops a new approach to the use of bi-directional dependencies using the concept of edge placement. This is shown to yield higher profitabilities of optimisation. An efficient solution method for such algorithms is also developed. The complexity of this method is shown to be bounded by O(e) operations, where e is the number of edges in the program flow graph. Ths is comparable to the complexity of uni-directional flow algorithms commonly used in optimisation.
Computer condensation of modular representations
Authors: A. J. E. Ryba
Venue: Journal of Symbolic Computation (1990)

Condensation replaces an explicit matrix representation of a group by a related but much smaller representation of a Hecke algebra. We give a general account of condensation and show how condensation is used to obtain the structure of large matrix representations. We include a detailed description of a new implementation of condensation. As an example of condensation, we work through the stages of the computation of the 2-modular character table of G"2(3).
Amoeba: A Distributed Operating System for the 1990s
Authors: Sape J. Mullender, Guido van Rossum, Andrew S. Tanenbaum, Robbert van Renesse, Hans van Staveren
Venue: Computer (1990)

A description is given of the Amoeba distributed operating system, which appears to users as a centralized system but has the speed, fault tolerance, security safeguards, and flexibility required for the 1990s. The Amoeba software is based on objects. Objects are managed by server processes and named using capabilities chosen randomly from a sparse name space. Amoeba has a unique, fast file system split into two parts: the bullet service stores immutable files contiguously on the disk; the directory service gives capabilities symbolic names and handles replication and atomicity, eliminating the need for a separate transaction management system. To bridge the gap with existing systems, Amoeba has a Unix emulation facility consisting of a library of Unix system call routines that make calls to the various Amoeba server processes.
Simulation with MIC-SIM and MIC-SIM VIEW
Authors: D. E. Strack
Venue: Proceedings of the 21st conference on Winter simulation (1989)

MIC-SIM is a general purpose, discrete-event simulation system for use on IBM compatible microcomputers. It was developed as part of a doctoral dissertation in 1980 using Radio Shack computers. Microcomputers were new then and the only simulation languages available required either a mainframe or mini-computer. The MIC-SIM system was changed to work on IBM microcomputers soon after their introduction. The first version used a node and branch basis for representing simulation models. MIC-SIM was later changed to an activity based simulation system in order to improve ease of learning and to incorporate more powerful modeling constructs. This paper discusses the basic features of MIC-SIM and presents an overview on some of the modeling features of MIC-SIM.
The role of supercomputers in higher education
Authors: Larry Neal, John Connolly, Doyle D. Knight, David Matthews-Morgan
Venue: ACM SIGCSE Bulletin (1988)

Advanced technology and networks have made the extra computational power of supercomputers affordable and accessible to researchers even at small universities. This panel will discuss how these important research tools can best be utilized in today's higher education environment.
Efficient Parallel Convex Hull Algorithms
Authors: R. Miller, Q. F. Stout
Venue: IEEE Transactions on Computers (1988)

Parallel algorithms are presented to identify (i.e. detect and enumerate) the extreme points of the convex hull of a set of planar points using a hypercube, pyramid, tree, mesh-of-trees, mesh with reconfigurable bus, exclusive-read-exclusive-write parallel random-access machine (EREW PRAM), and modified AKS network. It is shown that the problem of identifying the convex hull for a set of planar points given arbitrarily, cannot be solved faster than sorting.
Initial experiences with a pattern-oriented parallel debugger
Authors: Alfred A. Hough, Janice E. Cuny
Venue: ACM SIGPLAN Notices (1989)

Highly parallel programs are often best understood in terms of logical patterns of inter process communication. In order to debug such programs, the user must determine the extent to which the intended patterns occur during execution. To facilitate this, we have designed and implemented a pattern-oriented debugger in which abstract, user-defined communication events can be described and animated. We report here on our initial experiences with its use.
Design of a concurrent computer for solving systems of linear equations
Authors: K. Jainandunsing, E. F. Deprettere
Venue: ACM SIGARCH Computer Architecture News (1988)

In this paper we describe the design of a systolic array of Householder processor elements, which is dedicated to the solution of large (dense) systems of linear equations. The array is capable of executing two different algorithms. One for the solution of general, non-singular systems and one for the solution of symmetric, positive definite systems. The array is designed systematically and such that its dimensions are independent of the size of the problem.
VHDL synthesis using structured modeling
Authors: J. S. Lis, D. D. Gajski
Venue: Proceedings of the 26th ACM/IEEE Design Automation Conference (1989)

This paper describes the use of VHDL in a behavioral synthesis system. A structured modeling methodology is presented which suggests standard practices for writing VHDL descriptions which span a variety of design models. The VHDL Synthesis System (VSS) processes each of these input descriptions and produces a structural description of generic components.
A hierarchical solution for application level store-and-forward deadlock prevention
Authors: B. J. Brachman, S. T. Chanson
Venue: ACM SIGCOMM Computer Communication Review (1989)

Application level message transfer systems, primarily used to transport electronic mail, have several unique characteristics that make using existing methods of dealing with deadlock impractical. The special requirements for the efficient transport of application level messages are discussed and a description of a hierarchical scheme that meets these requirements is given. For networks consisting of interconnected clusters of computers, the structured buffer pool technique can be combined with other deadlock-free message transport schemes to form a network-wide, deadlock-free message transport facility. A properly chosen hierarchical system has the advantages of the individual schemes while lessening the impact of their disadvantages. The hierarchical scheme is also applicable to packet-switched and datagram-based networks.
Enlarging the scope of SQA
Authors: P. H. Loy
Venue: ACM SIGSOFT Software Engineering Notes (1989)

The concept of software quality assurance (SQA) is rapidly evolving, and reflects a growing awareness of the critical importance of this field. However, our view of what SQA is all about needs to focus more on the interrelated aspects of integration and scope. In terms of integration, SQA must become an integral part of every task in the development process, rather than being a parallel function embodied in a separate organizational department. With respect to scope, SQA must encompass areas that are often seen as marginal to software quality. In particular, the areas of business policy, metrics, peopleware, technology transfer, and technical leadership must be addressed.
Dynamic RAM for on-chip instruction caches
Authors: Jordi Cortadella, Teodor Jové
Venue: ACM SIGARCH Computer Architecture News (1988)

On-chip memories are commonly used to reduce the external communication bandwidth of current microprocessors. Implementations with static RAM allow simple synchronization structures. The use of dynamic RAM results in an important area saving but complicates the processor control due to the refresh requirements. In this paper, a simple design approach, based on the use of dynamic RAM, is introduced for implementing on-chip instruction caches without complicating the processor control.
On the correctness of representing extended entity-relationship structures in the relational model
Authors: Victor M. Markowitz, Arie Shoshani
Venue: Proceedings of the 1989 ACM SIGMOD international conference on Management of data (1989)

Although the relational representation of Entity-Relationship (ER) structures gained extensive coverage, scarce attention has been paid to the issue of correctness for such representations. Several mappings have been proposed for the representation of both ER and extended ER (EER) structures by relational schemas. The informal nature of most of these proposals, however, does not allow a precise evaluation of their correctness, nor a comparison of the various mappings. We propose a canonical relational representation for EER structures and prove its correctness. We claim that a relational schema represents correctly an EER structure if it has equivalent information-capacity with the corresponding canonical representation. The second problem addressed by this paper is the normalization of relational schemas that represent EER structures. We examine the conditions required by this process and show that ignoring these conditions leads to erroneous analyses and inappropriate design decisions. We show that, under these conditions, the canonical relational representation of any (unrestricted) EER structure has an (information-capacity) equivalent Boyce-Codd Normal Form schema.
Artificial intelligence approaches in space power systems automation at Marshall space flight center
Authors: David J. Weeks
Venue: Proceedings of the 1st international conference on Industrial and engineering applications of artificial intelligence and expert systems - Volume 1 (1988)

Advancements in the field of artificial intelligence (AI) made during this decade have forever changed the way we look at automating spacecraft subsystems including the electrical power system. This paper will discuss various applications of AI to spacecraft electrical power systems. Such discussion will include an overview of various completed, on-going, and planned knowledge-based system activities. These applications include NICBES (Nickel-Cadmium Battery Expert System which is interfaced with the Hubble Space Telescope electrical power system test bed); the SSES (power system loads scheduler); the three cooperating AI systems in the Space Station Module Power Management and Distribution system test bed; and I-DARE, the intelligent data reduction expert. The progress, as well as the issues raised by, of each of these projects will be addressed.
Unification in a combination of arbitrary disjoint equational theories
Authors: Manfred Schmidt-Schauβ
Venue: Journal of Symbolic Computation (1989)

The unification problem in a disjoint combination of equational theories, E"1+...+E"n, is reduced to a combination of two kinds of problems in the E"j's: the pure unification, problem with free (Uninterpreted) constants and the constant-elimination problem. The constant-elimination problem is to find, given terms t"i, 1@?i@?m and free constants c"i, 1@?i@?m, all substitutions @s such that for all i with 1@?i@?m, @st"i is equal to some t'"i that does not contain c"i. The soundness and completeness of the method shows, that a disjoint combination of theories is finitary, provided every theory is finitary and constant-elimination problems in every theory are finitary solvable. In particular, any combination of finitary unifying regular theories, of Boolean rings, of Abelian groups or of theories with terminating basic narrowing, is of unification-type finitary. As a special case, unification in a combination of a free Boolean ring with free function symbols is decidable and finitary; the same holds for Abelian groups. This paper extends the known results on unification in a combination of regular and collapse-free theories in two aspects: i) Arbitrary theories are admissable. ii) The described general procedure can be used for enumerating a complete set of unifiers, even if some unification procedure for a paticular theory produces an infinite complete set of unifiers. It is demonstrated that unifiability of unification problems is decidable in the general case E"1+...+E"n if for every i@?{1,...,n}, there is a method to decide unification problems in a combination of E"i with free function symbols.
Evaluating the performance of four snooping cache coherency protocols
Authors: S. J. Eggers, R. H. Katz
Venue: ACM SIGARCH Computer Architecture News (1989)

Write-invalidate and write-broadcast coherency protocols have been criticized for being unable to achieve good bus performance across all cache configurations. In particular, write-invalidate performance can suffer as block size increases; and large cache sizes will hurt write-broadcast. Read-broadcast and competitive snooping extensions to the protocols have been proposed to solve each problem. Our results indicate that the benefits of the extensions are limited. Read-broadcast reduces the number of invalidation misses, but at a high cost in processor lockout from the cache. The net effect can be an increase in total execution cycles. Competitive snooping benefits only those programs with high per-processor locality of reference to shared data. For programs characterized by inter-processor contention for shared addresses, competitive snooping can degrade performance by causing a slight increase in bus utilization and total execution time.
Evaluation of Quantization Error in Computer Vision
Authors: B. Kamgar-Parsi
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1989)

Due to the important role that digitization error plays in the field of computer vision, a careful analysis of its impact on the computational approaches used in the field is necessary. The authors develop the mathematical tools for the computation of the average (or expected) error due to quantization. They can be used in estimating the actual error occurring in the implementation of a method. Also derived is the analytic expression for the probability density of error distribution of a function of an arbitrarily large number of independently quantized variables. The probability that the error of the function will be within a given range can thus be obtained accurately. The tools developed can be used in the analysis of the applicability of a given algorithm.
Comparative performance of circuit-switched networks based on blocking probability
Authors: C. Hein
Venue: Proceedings of the 1989 ACM/IEEE conference on Supercomputing (1989)

A class of dynamic parallel processor interconnection networks, called circuit-switched networks, are composed of layers of small crossbar elements. Although such networks provide full connectivity, they are often called blocking networks, since contentions for network links sometimes block message pathways. The results from a study are reported in which the goal was to determine the effect of variations in a network's topology to aid in the selection of more optimal architectures. Three approaches were used in the study to determine the relative blocking performance of networks based on topology. Several popular topologies were analyzed by these approaches with respect to availability and probability of blocking. A discussion of the results provides insight into the design of networks containing large numbers of computer nodes by showing why some types of topologies produce more efficient networks than do others.