ppxscal/embedding_network huggingface dataset:
Fuzzy graph based metamodeling
Authors: Klaus-Peter Huber, Michael R. Berthold, Helena Szczerbicka
Venue: Proceedings of the 28th conference on Winter simulation (1996)

Analysis of simulation models has gained considerable interest in the past. However, their complexity still remains a considerable drawback in practical applications. One promising concept is the building of auxiliary models (metamodels) for different analysis goals. We present an efficient algorithm that constructs a metamodel only from simulation data, so no a priori knowledge has to be included. It will be shown that the resulting system approximates real valued functions with an adjustable precision. In addition the data can contain fuzzy patterns or values with a corresponding confidence-interval. This is especially well suited for simulation data due to its stochastic character. The metamodel is represented in form of a Fuzzy Graph which allows the analyst to directly extract easy to interpret if-then-rules. Application of this method to a real world token bus model is shown in detail.
Structuring graphical paradigms in TkGofer
Authors: Koen Claessen, Ton Vullinghs, Erik Meijer
Venue: Proceedings of the second ACM SIGPLAN international conference on Functional programming (1997)

In this paper we describe the implementation of several graphical programming paradigms (Model View Controller, Fudgets, and Functional Animations) using the GUI library TkGofer. This library relies on a combination of monads and multiple-parameter type classes to provide an abstract, type safe interface to Tcl/Tk. We show how choosing the right abstractions makes the given implementations surprisingly concise and easy to understand.
Event sensitive state saving in time warp parallel discrete event simulations
Authors: Sven Sköld, Robert Rönngren
Venue: Proceedings of the 28th conference on Winter simulation (1996)

In this paper we present event sensitive state saving as a novel idea for sparse state saving in Time Warp synchronized parallel discrete event simulations. This state saving model is aimed at efficient simulation of models where the execution time or granularity for different types or classes of events typically has a large variance. The event sensitive state saving mechanism is sensitive to which class of event the previously executed event belongs, and decide when to save simulation state based on this information. We present an analytical analysis and compare this new state saving model with the performance of an existing adaptive state saving model as well as the traditional Time Warp state saving model with fixed state saving interval.
The Minimum Eigenvalue of a Symmetric Positive-Definite Toeplitz Matrix and Rational Hermitian Interpolation
Authors: Wolfgang Mackens, Heinrich Voss
Venue: SIAM Journal on Matrix Analysis and Applications (1997)

A novel method for computing the minimal eigenvalue of a symmetric positive-definite Toeplitz matrix is presented. Similar to the algorithm of Cybenko and Van Loan, it is a combination of bisection and a root finding method. Both phases of the method are accelerated considerably by rational Hermitian interpolation of the secular equation. For randomly generated test problems of dimension 800 the average number of linear systems which must be solved to determine the smallest eigenvalue is 6.6, which reduces the computational cost of the method of Cybenko and Van Loan to approximately 35%. The method includes a rigorous error bound.
A run time support system for multiprocessor machines
Authors: M. A. Tsoukarellas, T. S. Papatheodorou
Venue: Proceedings of the 4th international conference on Supercomputing (1990)

We report on the design and development of a Run Time Support System (RTS) which overcomes known disadvantages of other existing systems. The RTS is independent of the configuration - if the system is reconfigured there is no need to change user's processes. It supports both synchronous and asynchronous communication. A system based on the same design philosophy with this RTS is actually implemented for messages of arbitrary length in the prototype of the PADMAVATI machine, being developed within ESPRIT Project 1219 (967). Experiments were conducted in this environment and performance measurements were obtained and are reported here.
Determining the Order of Processor Transactions in StaticallyScheduled Multiprocessors
Authors: S. Sriram, Edward A. Lee
Venue: Journal of VLSI Signal Processing Systems (1997)

This paper addresses embedded multiprocessor implementation of iterative, real-time applications, such as digital signal and image processing, that are specified as dataflow graphs. Scheduling dataflow graphs on multiple processors involves assigning tasks to processors (processor assignment), ordering the execution of tasks within each processor (task ordering), and determining when each task must commence execution. We consider three scheduling strategies: fully-static, self-timed and ordered transactions, all of which perform the assignment and ordering steps at compile time. Run time costs are small for the fully-static strategy; however it is not robust with respect to changes or uncertainty in task execution times. The self-timed approach is tolerant of variations in task execution times, but pays the penalty of high run time costs, because processors need to explicitly synchronize whenever they communicate. The ordered transactions approach lies between the fully-static and self-timed strategies; in this approach the order in which processors communicate is determined at compile time and enforced at run time. The ordered transactions strategy retains some of the flexibility of self-timed schedules and at the same time has lower run time costs than the self-timed approach.In this paper we determine an order of processor transactions that is nearly optimal given information about task execution times at compile time, and for a given processor assignment and task ordering. The criterion for optimality is the average throughput achieved by the schedule. Our main result is that it is possible to choose a transaction order such that the resulting ordered transactions schedule incurs no performance penalty compared to the more flexible self-timed strategy, even when the higher run time costs implied by the self-timed strategy are ignored.
Initial results on the performance and cost of vector microprocessors
Authors: Corinna G. Lee, Derek J. DeVries
Venue: Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture (1997)

Increasingly wider superscalar processors are experiencing diminishing performance returns while requiring larger portions of die area dedicated to control rather than datapath. As an alternative to using these processors to exploit parallelism effectively, we are investigating the viability of using single-chip vector microprocessors. This paper presents some initial results of our investigation where we compare the performance and cost of vector microprocessors to that of aggressive, out-of-order super- scalar microprocessors.On the performance side, we show that vector processors are able to execute a highly parallel, integer-based application 1.5- 7.3 times faster than superscalar processors can by exploiting parallelism more effectively. This ability stems from the use of vector instructions. Vector instructions exploit parallelism across loop iterations by implicitly re-scheduling operations and temporally localizing the parallelism. Vector instructions also reduce instruction bandwidth by more than an order of magnitude because they express an abundance of parallelism in a compact encoding.On the cost side we show that, to achieve these performance gains, highly parallel, integer-based vector microprocessors are no more costly to implement than existing in-order and out-of- order superscalar microprocessors. One reason for this is that the organization of a vector register file provides tremendous bandwidth without incurring a large area penalty. A second reason is that the control logic for issuing vector instructions is relatively simple.Both the performance gains and cost savings are possible because vector processors rely on a vectorizing compiler, rather than hardware, to detect parallelism and to express it in a compact form to the hardware. These initial results suggest that transferring this functionality to the compiler offers a tremendous performance/cost benefit.
Multiscale, Statistical Anomaly Detection Analysis andAlgorithms for Linearized Inverse Scattering Problems
Authors: Eric L. Miller, Alan S. Willsky
Venue: Multidimensional Systems and Signal Processing (1997)

In this paper we explore the utility of multiscale and statistical techniques for detecting and characterizing the structure of localized anomalies in a medium based upon observations of scattered energy obtained at the boundaries of the region of interest. Wavelet transform techniques are used to provide an efficient and physically meaningful method for modeling the non-anomalous structure of the medium under investigation. We employ decision-theoretic methods both to analyze a variety of difficulties associated with the anomaly detection problem and as the basis for an algorithm to perform anomaly detection and estimation. These methods allow for a quantitative evaluation of the manner in which the performance of the algorithms is impacted by the amplitudes, spatial sizes, and positions of anomalous areas in the overall region of interest. Given the insight provided by this work, we formulate and analyze an algorithm for determining the number, location, and magnitudes associated with a set of anomaly structures. This approach is based upon the use of a Generalized, M-ary Likelihood Ratio Test to successively subdivide the region as a means of localizing anomalous areas in both space and scale. Examples of our multiscale inversion algorithm are presented using the Born approximation of an electrical conductivity problem formulated so as to illustrate many of the features associated with similar detection problems arising in fields such as geophysical prospecting, ultrasonic imaging, and medical imaging.
Business process simulation
Authors: Kerim Tumay
Venue: Proceedings of the 28th conference on Winter simulation (1996)

This introductory tutorial provides an overview of business process simulation and how it works. Descriptions of modeling elements and model performance measures are presented. Classification of business processes is followed by unique modeling, simulation procedure and analysis considerations. Types of business process simulation tools are discussed. Finally, a purchasing process simulation exercise is presented to illustrate the power and suitability of simulation for analyzing a business process.
The novel algorithm for determining the reachability in acyclic Petri nets
Authors: A. E. Kostin
Venue: ACM SIGACT News (1997)

A novel algorithm for determining the reachability of a marking in acyclic Petri nets is proposed. For this algorithm, a Petri net is represented in the matrix form, with a given pair of initial and target markings. The algorithm is based on the creation of a temporal ordering relation for transition firings and on using this relation for determining the shortest sequence of transition firings transforming the initial marking into the target one. By solving the fundamental equation of the Petri net, the algorithm determines initially whether the target marking is reachable from the given initial marking, and, in case it is, produces the shortest sequence of transition firings which transforms the initial marking into the target one.
New standards for educational technology relevant to multiple ACM SIGs
Authors: Roy Rada, James Schoening
Venue: ACM SIGNUM Newsletter (1997)

Standards are relevant to every ACM SIG. The new JavaScript standardization effort from the European Computer Manufacturers Association would be particularly relevant to SIG Software Engineering. Managing Multimedia information Structures from the European Workshop for Open Systems would be particularly relevant to SIG Multimedia. The new ISO 14000 standards for environmental quality management systems might concern SIG Management Information Systems. One of the latest standardization efforts is for educational technology, and to our knowledge only one formal Standards Development Organization, namely the Institute of Electrical and Electronic Engineers (IEEE), is directly addressing educational technology standards.
Memory management for Prolog with tabling
Authors: Bart Demoen, Konstantinos Sagonas
Venue: Proceedings of the 1st international symposium on Memory management (1998)

Tabling can be implemented in a (WAM-based) Prolog system by means of SLG-WAM: consumers suspend and their state is preserved by freezing the execution stacks. XSB is a system that currently implements tabling based on the SLG-WAM. The memory model is quite complex and attempts to understand the notion of usefulness of data in XSB well enough to build a precise garbage collector have failed in the past. CAT is a recent alternative to SLG-WAM: it suspends consumers by copying parts of the execution stacks. The memory model is simpler and the design of a more precise garbage collector became feasible. CAT also provided the necessary insights in the usefulness of data in the context of the SLG-WAM. This paper describes the memory management of tabled logic programming systems, whether based on the SLG-WAM or on CAT. Since CAT can perform arbitrarily worse than SLG-WAM space-wise, a minor garbage collection on creation of the CAT areas is proposed as a remedy; its effectiveness is discussed.
Data-Parallel Sparse Factorization
Authors: John M. Conroy, Steven G. Kratzer, Robert F. Lucas, Aaron E. Naiman
Venue: SIAM Journal on Scientific Computing (1998)

Sparse matrix factorization is a computational bottleneck in many scientific and engineering problems. This paper examines the problem of factoring large sparse matrices on data-parallel computers. A multifrontal approach is presented in which only the fine-grain concurrency found within the elimination of each supernode is exploited. Throughput approaching that of large dense matrix factorizations is demonstrated on two data-parallel systems, the MasPar MP-2 and the Thinking Machines CM-5.
Design and Analysis of a CMOS Switched-Current Sigma-DeltaModulator Using Multi Level Simulations
Authors: Ping Zhu, Hannu Tenhunen
Venue: Analog Integrated Circuits and Signal Processing (1998)

This paper presents the design of a 3.3V CMOS switched-current (SI) second-order sigma-delta modulator for A/D converters intended for radio front-end applications. The effects of non-ideal behaviours of the building blocks on the total performance of a SI double-integrator sigma-delta modulator (DISDM) were analysed and simulated by means of multi level (SpectreHDL-level, transistor-level) and mixed level simulations. The implementation of a SI DISDM concerning the practical issues is discussed. A second-generation cascode SI integrator was optimized to meet the desired speed and to diminish the non-ideal errors. The SI DISDM can operate at the sampling rate of 80MHz and over based on the parasitic-extracted transistor-level simulations.
Optimizing computations in a transposed direct form realization of floating-point LTI-FIR systems
Authors: N. Sankarayya, K. Roy, D. Bhattacharya
Venue: Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design (1997)

The inherent computational redundancy in discrete-time LTI-FIR system response computations in Digital Signal Processing have been exploited in a variety of ways to minimize the computational complexity. We present an improved algorithm-level computational optimization that uses sorted recursive differences between coefficients representing the system transfer function with a Floating-Point number representation to extract maximum benefits from this redundancy. It can be applied to any LTI-FIR system and there is no deterioration in accuracy compared to directly using the coefficients. The results for several practical FIR systems show that there is a significant reduction in the computational complexity, hence power consumed, using this technique.
A Self-Testing Nonincreasing Order Checker
Authors: D. L. Tao
Venue: IEEE Transactions on Computers (1997)

In this paper, we design a new class of self-testing checkers, self-testing nonincreasing order checkers, for the first time. The self-testing nonincreasing order checker is a critical component to design concurrent checking VLSI sorters because it is capable of checking whether an arbitrary long sequence of numbers has been sorted, as well as testing itself during normal system operation.
Topological Reconstruction of a Smooth Manifold-Solid from Its OccludingContour
Authors: Lance R. Williams
Venue: International Journal of Computer Vision (1997)

This paper describes a simple construction for building a combinatorial model of a smooth manifold-solid from a labeled-figure representing its occluding contour. The motivation is twofold. First, deriving the combinatorial model is an essential intermediate step in the visual reconstruction of solid-shape from image contours. A description of solid-shape consists of a metric and a topological component. Both are necessary: the metric component specifies how the topological component is embedded in three-dimensional space. The paneling construction described in this paper is a procedure for generating the topological component from a labeled-figure representing the occluding contour. Second, the existence of this construction establishes the sufficiency of a labeling scheme for line-drawings of smooth solid-objects originally proposed by Huffman (1971). By sufficiency, it is meant that every set of closed plane-curves satisfying this labeling scheme is shown to correspond to a generic view of a manifold-solid. Together with the Whitney theorem (Whitney, 1955), this confirms that Huffman&lsquo;s labeling scheme correctly distinguishes possible from impossible smooth solid-objects.
Scalable Global and Local Hashing Strategies for Duplicate Pruning in Parallel A* Graph Search
Authors: Nihar R. Mahapatra, Shantanu Dutt
Venue: IEEE Transactions on Parallel and Distributed Systems (1997)

For many applications of the A* algorithm, the state space is a graph rather than a tree. The implication of this for parallel A* algorithms is that different processors may perform significant duplicated work if interprocessor duplicates are not pruned. In this paper, we consider the problem of duplicate pruning in parallel A* graph-search algorithms implemented on distributed-memory machines. A commonly used method for duplicate pruning uses a hash function to associate with each distinct node of the search space a particular processor to which duplicate nodes arising in different processors are transmitted and thereby pruned. This approach has two major drawbacks. First, load balance is determined solely by the hash function. Second, node transmissions for duplicate pruning are global; this can lead to hot spots and slower message delivery. To overcome these problems, we propose two different duplicate pruning strategies: 1) To achieve good load balance, we decouple the task of duplicate pruning from load balancing, by using a hash function for the former and a load balancing scheme for the latter. 2) A novel search-space partitioning scheme that allocates disjoint parts of the search space to disjoint subcubes in a hypercube (or disjoint processor groups in the target architecture), so that duplicate pruning is achieved with only intrasubcube or adjacent intersubcube communication. Thus message latency and hot-spot probability are greatly reduced. The above duplicate pruning schemes were implemented on an nCUBE2 hypercube multicomputer to solve the Traveling Salesman Problem (TSP). For uniformly distributed intercity costs, our strategies yield a speedup improvement of 13 to 35 percent on 1,024-processors over previous methods that do not prune any duplicates, and 13 to 25 percent over the previous hashing-only scheme. For normally distributed data the corresponding figures are 135 percent and 10 to 155 percent. Finally, we analyze the scalability of our parallel A* algorithms on k-ary n-cube networks in terms of the isoefficiency metric, and show that they have isoefficiency lower and upper bounds of ¿(P log P) and ¿(Pkn2), respectively.
Cost-optimal parallel B-spline interpolations
Authors: Kuo-Liang Chung, Ferng-Ching Lin, Wen-Chin Chen
Venue: ACM SIGARCH Computer Architecture News (1990)

We show how to transform the B-spline curve and surface fitting problems into suffix computations of continued fractions. Then a parallel substitution scheme is introduced to compute the suffix values on a newly proposed mesh-of-unshuffle network. The derived parallel algorithm allows the curve interpolation through n points to be solved in O(logn) time using &THgr;(n/log n processors and allows the surface interpolation through m &times; n points to be solved in O(log m log n) time using &THgr;(mn/(log m log n)) processors. Both interpolation algorithms are cost-optimal for their respective problems. Besides, the surface fitting problem can be even faster solved in O(log m + log n) time if &THgr;(mn) processors are used in the network.
An Extensible System for Source Code Analysis
Authors: Gerardo Canfora, Aniello Cimitile, Ugo de Carlini, Andrea de Lucia
Venue: IEEE Transactions on Software Engineering (1998)

Constructing code analyzers may be costly and error prone if inadequate technologies and tools are used. If they are written in a conventional programming language, for instance, several thousand lines of code may be required even for relatively simple analyses. One way of facilitating the development of code analyzers is to define a very high-level domain-oriented language and implement an application generator that creates the analyzers from the specification of the analyses they are intended to perform. This paper presents a system for developing code analyzers that uses a database to store both a no-loss fine-grained intermediate representation and the results of the analyses. The system uses an algebraic representation, called F(p), as the user-visible intermediate representation. Analyzers are specified in a declarative language, called $F(p)-\ell,$ which enables an analysis to be specified in the form of a traversal of an algebraic expression, with access to, and storage of, the database information the algebraic expression indices. A foreign language interface allows the analyzers to be embedded in C programs. This is useful for implementing the user interface of an analyzer, for example, or to facilitate interoperation of the generated analyzers with pre-existing tools. The paper evaluates the strengths and limitations of the proposed system, and compares it to other related approaches.
A testbed for parallel simulation performance prediction
Authors: Alois Ferscha, James Johnson
Venue: Proceedings of the 28th conference on Winter simulation (1996)

The overwhelming complexity of influencing factors determining the performance of parallel simulation executions demands a performance oriented development of logical process simulators. This paper presents an incremental code development process that supports early performance predictions of Time Warp protocols and several of its optimizations. A set of tools, N-MAP, for performance prediction and visualization has been developed, representing a testbed for a detailed sensitivity analysis of the various Time Warp execution parameters. As an example, the effects of various performance factors like the event structure underlying the simulation task, the average LVT progression per simulation step, the commitment rate, state saving overhead, etc. are demonstrated. We show how the scenario management features provided by the N-MAP tool can be efficiently utilized to predict performance sensitivities. For the particular example, the Time Warp protocol, though highly involved, N-MAP was able to predict the per formance sensitivity that was measured from the full implementation executing on the Meiko CS-2.