ppxscal/embedding_network huggingface dataset:
Synchronizing large VLSI processor arrays
Authors: Allan L. Fisher, H. T. Kung
Venue: ACM SIGARCH Computer Architecture News (1983)

Highly parallel VLSI computing structures consist of many processing elements operating simultaneously. In order for such processing elements to communicate among themselves, some provision must be made for synchronization of data transfer. The simplest means of synchronization is the use of a global clock. Unfortunately, large clocked systems can be difficult to implement because of the inevitable problem of clock skews and delays, which can be especially acute in VLSI systems as feature sizes shrink. For the near term, good engineering and technology improvements can be expected to maintain the feasibility of clocking in such systems; however, clock distribution problems crop up in any technology as systems grow. An alternative means of enforcing necessary synchronization is the use of self-timed, asynchronous schemes, at the cost of increased design complexity and hardware cost. Realizing that different circumstances call for different synchronization methods, this paper provides a spectrum of synchronization models; based on the assumptions made for each model, theoretical lower bounds on clock skew are derived, and appropriate or best-possible synchronization schemes for large processor arrays are proposed. One set of models is based on assumptions that allow the use of a pipelined clocking scheme, where more than one clock event is propagated at a time. In this case, it is shown that even assuming that physical variations along clock lines can produce skews between wires of the same length, any one-dimensional processor array can be correctly synchronized by a global pipelined clock while enjoying desirable properties such as modularity, expandability and robustness. This result cannot be extended to two-dimensional arrays, however&mdash;the paper shows that under this assumption, it is impossible to run a clock such that the maximum clock skew between two communicating cells will be bounded by a constant as systems grow. For such cases or where pipelined clocking is unworkable, a synchronization scheme incorporating both clocked and &ldquo;asynchronous&rdquo; elements is proposed.
Calibrating the simulation model of the IBM system/360 time sharing system
Authors: P. E. Barker, H. K. Watson
Venue: Proceedings of the third conference on Applications of simulation (1969)

A GPSS/360 model was developed to support the IBM System/360 Time Sharing System (TSS/360) design and evaluation effort. The model was validated by conventional desk-checking procedures and by an extensive measurement effort involving a hardware monitor (SPAR), a software monitor (SIPE), and miscellaneous data-reduction programs. Calibration results obtained with TSS/360 are described, as are some of the benefits derived from the model.
CASS: Computer aided schematic system
Authors: Hedayat Markus Bayegan
Venue: Proceedings of the 14th Design Automation Conference (1977)

Our interactive system for computer aided editing of schematics (CASS) is described here. The system may be used alone as well as a part of an integrated data-base oriented design environment. In isolated operation, a number of utility programs provide for the use of schematic data in succeeding design phases. As part of an integrated system this schematic data may be stored in, and retrieved from, the data-base directly. Some general aspects of the data-base will be described. Particular attention should be devoted to the very "natural" and powerful user's interface of CASS, utilizing the menu technique on a storage display device, while minimizing the use of kayboard. In order to increase the applicability of the system an intelligent graphic terminal, based on a microcomputer, is under implementation. The configuration of this terminal will be outlined and some of its fundamental design aspects will be described.
EDP documentation &mdash; &ldquo;human communications software&rdquo; in the computer age (Presentation Abstract)
Authors: J. Jose Cortez
Venue: Proceedings of the ACM 1980 annual conference (1980)

Until recent years, much of the electronic data processing community demonstrated little or no acknowledge of the importance documentation should have in systems development and operations efforts. At the crux of this attitude was the belief that in the design, coding, and implementation of new EDP systems, there were more pressing problems to solve than to be concerned with documentation. Documentation was, and still is, frequently looked upon by EDP professionals as an ill-defined, undesirable chore that could be put off until all other problems related to the system were &ldquo;under control&rdquo;; not realizing that a major factor for the problems encountered was the inadequacy or non-existence of documentation. Once the subject was addressed, documentation usually took on the form of a program-level manuscript, since program maintenance was considered to be the critical area that documentation should support.
Logic design automation of MOS combinational networks with fan-in, fan-out constraints
Authors: Yacoub M. El-ziq
Venue: Proceedings of the 15th Design Automation Conference (1978)

With the increasing complexity of current digital systems, many aspects have to be considered in the Logic design of these systems. Among them are the pin limitations, interconnections, power dissipation, testability, and fan-in, fan-out constraints. Since MOS (metal oxide semiconductor) is playing a major role in large scale integration (LSI), the problem of synthesis of MOS switching networks with large number of variables is very important. The main advantage of MOS over other forms of integrated circuits is the possibility of obtaining higher chip logic density. Long propagation delay limits MOS to low speed applications, however, speed can be improved by using advanced types of MOS as VMOS, DMOS and HMOS. An efficient algorithm for computer-aided synthesis of MOS combinational logic networks was presented in the 1977 Design Automation Conference. That algorithm considered some of the aspects need to be considered in the logic design process. These were pin limitations, interconnections, and testability. In this paper we present a new algorithm which incorporates, in addition to the aspects considered above, the fan-in, fan-out constraints. Designing digital systems with fan-in, fan-out constraints is vital for achieving proper operation of these systems - specifically speed and noise margin. A step-by-step description as well as a detailed synthesis example are given. Some of the steps of this algorithm were programmed in FORTRAN V on a SPERRY UNIVACTM 1108 computer. The effects of this kind of design on the network performance and testability are discussed. Finally, some future research problems in this area are presented.
Nonserial dynamic programming is optimal
Authors: Arnie Rosenthal
Venue: Proceedings of the ninth annual ACM symposium on Theory of computing (1977)

We show that nonserial dynamic programming is optimal among one class of algorithms for an important class of discrete optimization problems. We consider discrete, multivariate, optimization problems in which the objective function is given as a sum of terms. Each term is a function of only a subset of the variables. We first consider a class of optimization algorithms which eliminate suboptimal solutions by comparing the objective function on &ldquo;comparable&rdquo; partial solutions. A large, natural subclass of comparison algorithms in which the subproblems considered are either nested or nonadjacent (i.e., noninteracting) is then defined. It is shown that a variable-elimination procedure, nonserial dynamic programming, is optimal in an extremely strong sense among all algorithms in the subclass. The results' strong implications for choosing deterministic, adaptive, and nondeterministic algorithms for the optimization problem, for defining a complexity measure for a pattern of interactions, and for describing general classes of decomposition procedures are discussed. Several possible extensions and unsolved problems are mentioned.
A heuristic procedure for ordering MOS arrays
Authors: H. Yoshizawa, H. Kawanishi, K. Kani
Venue: Proceedings of the 12th Design Automation Conference (1975)

For automated layout of one-dimensional MOS gates arrays, a heuristic procedure, determining the optimal ordering of gates to minimize the chip area, is presented.
An asymmetric stream communication system
Authors: Andrew P. Black
Venue: Proceedings of the ninth ACM symposium on Operating systems principles (1983)

Input and output are often viewed as complementary operations, and it is certainly true that the direction of data flow during input is the reverse of that during output. However, in a conventional operating system, the direction of control flow is the same for both input and output: the program plays the active role, while the operating system transput primitives are always passive. Thus there are four primitive transput operations, not two: the corresponding pairs are passive input and active output, and active input and passive output. This paper explores the implications of this idea in the context of an object oriented operating system. This work is supported in part by the National Science Foundation under Grant No. MCS-8004111. Computing equipment and technical support are provided in part under a cooperative research agreement with Digital Equipment Corporation.
Automatic Digital Encoding System, II (ADES II)
Authors: E. K. Blum
Venue: Proceedings of the 1956 11th ACM national meeting (1956)

At the September 1955 Annual Meeting of A.C.M., the author presented a paper which described Automatic Digital Encoding System I, (ADES I), a system of automatic translation of mathematical formulas into computer programs. The present paper describes ADES II, a significant extension of that system. ADES I excluded problems which involved double recursion. This type of recursion is provided for in ADES II, as well as a special type of triple recursion. ADES II also contains new features for improving the efficiency of the computer program.
Microprogramming and its relationship to emulation and technology
Authors: Samuel H. Fuller, Victor R. Lesser, C. Gordon Bell, Charles Kaman
Venue: Conference record of the 7th annual workshop on Microprogramming (1974)

This paper is a survey of the development and future trends in microprogramming. We show how the structure of microprogrammed processors has been shaped primarily by two factors: the state of (semiconductor) technology and the task of emulation. The other main theme of this article is that it is a fruitless exercise to try to characterize and understand microprogramming in terms of how it differs from 'regular' programming. The right approach to understanding microprogramming is to recognize that it is primarily applied to the task of emulation (interpretation). Through this approach the evolution of microprogramming, independent of a particular technology and type of instruction set being emulated, is reviewed and future trends indicated.
An on line program for non-numerical algebra
Authors: Knut Korsvold
Venue: Proceedings of the first ACM symposium on Symbolic and algebraic manipulation (1966)

The paper describes a program for on line manipulation and simplification of non-numerical algebra. The program is written in LISP 1,5 for use under the time-sharing system of the Q-32 computer at System Development Corporation in Santa Monica, California. The structure of the program makes the program easy to be expanded, and the user is allowed fairly extensive control over the course of the program. Intermediate results can be printed at will, and changes to the simplification rules can be done rather easily at several stages of the program. The program has been written and debugged from a remote Teletype consol at Stanford University.
Event list management - a tutorial
Authors: James O. Henriksen
Venue: Proceedings of the 15th conference on Winter Simulation - Volume 2 (1983)

Proper management of the event list is critically important for achieving execution efficiency in discrete event modelling of computer, telecommunication, and other frequently occurring classes of systems. For such systems, use of a poor event list algorithm can result in horrendous inefficiency. Conversely, replacement of a poor algorithm with a good algorithm can reduce execution times tremendously. For example, in models of telecommunication systems, total run times can easily differ by as much as 5:1, depending on choice of event list algorithm. Many papers have been written about event list algorithms. Unfortunately, the variance in quality of what has been written closely parallels the variance in performance of the algorithms themselves: everything from scholarly works to utter nonsense has been published. Among the persistent myths of simulation is the &ldquo;fact&rdquo; that major simulation languages fail to make use of advanced event list algorithms. This is patently false. GPSS/H (Henriksen Crain 1983) has used an improved algorithm (Henriksen 1977) since 1977, and SLAM (Pritsker 1979) has used an improved algorithm (a variant of the GPSS/H algorithm) since the advent of SLAM II in 1981. Before proceeding, we briefly summarize the sections which follow. Section 1 defines what is meant by the phrase &ldquo;event list algorithm.&rdquo; Section 2 presents a hypothetical example, to illustrate the spectacular failure of a naive event list algorithm. Section 3 describes a simple alternative algorithm which is effective when applied to the example of Section 2, but lacks generality. Section 4 presents criteria for evaluating event list algorithms. Section 5 describes some alternative general-purpose algorithms which have been devised, and reviews a number of written works about event list algorithms. Section 6 presents a detailed description of the algorithm used in GPSS/H (Henriksen 1977). Finally, Section 7, offers conclusions.
A computer architecture for system performance monitoring
Authors: E. L. Burke
Venue: Proceedings of the 1973 ACM SIGME symposium (1973)

Many computer systems are sufficiently complex that it is not possible to predict or understand all of the interactions among system components. Performance monitoring is a technique for measuring system performance and recording the internal states of the system in response to various events. Current monitors employ hardware and/or software techniques. This report presents a methodology for designing a performance monitor which is integrated into the system architecture. A new technique for implementing a monitor is described which uses microprogramming to provide a flexible and efficient interface between the monitor and the system.
Educational pathways to computing careers in health care: Education for leadership in the health computing profession
Authors: Karen A. Duncan
Venue: Proceedings of the ACM '81 conference (1981)

The health care industry in the United States is a &dollar;220 Billion a year industry (about 10% of the Gross National Product), with information handling accounting for about 30% of the health care dollar. Although computing could play a major role in facilitating health care information flow to reduce costs and improve the quality of care, the health care industry lags behind most other major U.S. industries in its utilization of information technology. A significant factor in this under- utilization is believed by many to be the scarcity of adequately trained health computing professionals who can design and develop appropriate uses for the technology. The health computing profession's development and its ability to attract bright and creative young professionals, in turn, has been hampered by the poorly specified and diverse career paths, the lack of a well organized peer structure for information exchange, and unspecified goals for the education of health computing professionals. While problems such as these are typical of any emerging profession, the need for educational goals is a problem that must be addressed formally.
Recursion induction applied to generalized flowcharts
Authors: Donald M. Kaplan
Venue: Proceedings of the 1969 24th national conference (1969)

Recursion induction here is a rule of inference for proving flowchart programs equivalent. If a flowchart A is equivalent to another B(A), and if the so-called closed form of B, namely C, halts whenever B(A) does, then A is equivalent to C. It is shown that this rule can be extended to apply to a very general class of flowcharts. A formal theory of flowcharts is introduced that permits proofs of the premises of this extended rule to be carried out, and a derivation using recursion induction is illustrated. As a further example, two flowcharts are introduced that are each equivalent to a two-tape, one-way automaton. A derivation using recursion induction is presented that proves the flowcharts, and hence the automata as well, equivalent.
Signal delay in RC tree networks
Authors: Paul Penfield,  Jr., Jorge Rubinstein
Venue: Proceedings of the 18th Design Automation Conference (1981)

In MOS integrated circuits, signals may propagate between stages with fanout. The MOS interconnect may be modeled by an RC tree. Exact calculation of signal delay through such networks is difficult. However, upper and lower bounds for delay that are computationally simple are presented here. The results can be used (1) to bound the delay, given the signal threshold; or (2) to bound the signal voltage, given a delay time; or (3) to certify that a circuit is &ldquo;fast enough&rdquo;, given both the maximum delay and the voltage threshold.
Smoothly shaded renderings of polyhedral objects on raster displays
Authors: Tom Duff
Venue: Proceedings of the 6th annual conference on Computer graphics and interactive techniques (1979)

The appearance of raster-scan renderings of polyhedral approximations to curved surfaces can be enhanced greatly by shading them in a manner that varies smoothly across each polygon and which matches the correct shade at each vertex. Henri Gouraud and Bui Tuong-Phong have previously described two methods of computing such shading functions. While the computations in Gouraud's method are quite quick to perform, the renderings produced often exhibit pronounced Mach bands, and animated sequences tend to have annoying fluctuations in intensity. Phong's method tries to cure these problems, but is much more expensive computationally. We will show a new, faster method of computing Phong shading, and discuss the relationship of this method to Gouraud shading. We will also exhibit representatives of a class of surfaces for which Phong shading surprisingly produces worse Mach bands than Gouraud shading.
Traversing binary tree structures with shift register memories (Recent Results)
Authors: W. E. Kluge
Venue: Proceedings of the 3rd annual symposium on Computer architecture (1976)

The paper proposes a tree-structured shift register memory in which traversals of binary data tress in pre-or end-order are performed as sequences of two non-cyclic data permutations which move the data tree relative to a unique access port that is located in the root node of the memory tree. These two permutations, denoted A and B, emulate elementary traversal steps. Permutations A correspond to traversals between nodes of an even tree level and the next higher odd level, permutations B correspond to traversals between nodes of an odd tree level and the next higher even level. Traveling from a node to its left successor requires one permutation, traveling to its right successor requires two identical permutations in succession. Three identical permutations in succession perform a counter-clockwise cyclic traversal within a subtree which comprises a (root) node, its left successor node and its right successor node; i.e. subsequences AAA and BBB yield identity. Accordingly, if the conventional address assignment of trees applies, then the permutation (traversal) sequence that is effective on the memory corresponds to the address of the node that is actually being visited. Starting to the right of the most significant '1' bit in the address code and proceeding in the order from left to right, a '0' corresponds to one permutation and a '1' corresponds to two identical permutations; the permutation is A if the bit position is even, and B if the bit position is odd. Thus, the state of permutation may be identified by the address code. The permutation sequence that traverses the data tree is generated from single control bits, associated with every node of the data tree, which distinguish between branch nodes and leaf nodes. Whenever a branch node is being visited, then the permutation to be executed next changes with respect to the preceding permutation. Whenever a leaf node is being visited, the next permutation remains the same as the previous one.
Measuring productive computational work
Authors: Marvin Talbott
Venue: Proceedings of the 1976 annual conference (1976)

The measurement of computational work in computer systems traditionally relied heavily on indicators of hardware. Unfortunately, these indicators have a low correlation to the user's perception of useful work. This paper defines computations in terms of fundamental bit logical manipulations and shows the user's &ldquo;useful computational work&rdquo; can be quantized from a job specification in FORTRAN source statements. The method can be automated yielding a specific quantity of work for a given method FORTRAN program with specified data. The resulting measure of work can be used to obtain ranges of computational power for any system on which the benchmarks are executed.
Application diagnostic aids in APL/700
Authors: James L. Ryan, Harvey W. Bingham
Venue: Proceedings of the eighth international conference on APL (1976)

Diagnostic aids in Burroughs APL/700 include system functions for setting, resetting and querying Trace, Stop, and Monitor conditions on lines of user-defined functions. Trace and Stop have similar effects to those available in other APL systems. Trace also returns type and shape information. Monitor gives the dynamic number of executions of individual lines and the computer time consumed therein. The benefit from monitoring to APL applications typically averages 30% to 50% reduction in processing time, since the most costly lines can be easily identified for potential algorithm tuning.
Decision procedures and expressiveness in the temporal logic of branching time
Authors: E. Allen Emerson, Joseph Y. Halpern
Venue: Proceedings of the fourteenth annual ACM symposium on Theory of computing (1982)

In this paper we consider the Computation Tree Logic (CTL) proposed in [CE] which extends the Unified Branching Time Logic (UB) of [BMP] by adding an until operator. We establish that CTL has the small property by showing that any satisfiable CTL formulae is satisfiable in a small finite model obtained from a small -&-ldquo;pseudo-model-&-rdquo; resulting from the Fischer Ladner quotient construction. We then give an exponential time algorithm for deciding satisfiability in CTL, and extend the axiomatization of UB given in [BMP] to a complete axiomatization for CTL. Lastly, we study the relative expressive power of a family of temporal logics obtained by extending or restricting the syntax of UB and CTL.