ppxscal/embedding_network huggingface dataset:
A parallel pattern mixed-level fault simulator
Authors: Tyh-Song Hwang, Chung Len Lee, Wen Zen Shen, Ching Ping Wu
Venue: Proceedings of the 27th ACM/IEEE Design Automation Conference (1991)

This paper describes a parallel pattern mixed level, i.e. switch-level and gate-level, fault simulator. The switch-level allows the simulator to treat faults at the transistor level while the gate level simulation conserves the simulation speed and the parallel pattern strategy further enhances the simulation speed for more than one order of magnitude.
DSNS (dynamically-hazard-resolved statically-code-scheduled, nonuniform superscalar): yet another superscalar processor architecture
Authors: Morihiro Kuga, Kazuaki Murakami, Shinji Tomita
Venue: ACM SIGARCH Computer Architecture News (1991)

A new superscalar processor architecture, called DSNS (Dynamically-hazard-resolved, Statically-code-scheduled, Nonuniform Superscalar), is proposed and discussed. DSNS has the following major architectural features.1. Dynamically-hazard-resolved superscalar: DSNS is object-code compatible with respect to the degree of superscalar. Pipeline interlock hardware should be provided for detecting and resolving hazards at run time.2. Statically-cade-scheduled superscalar: The performance of DSNS could not be scalable with respect to the degree of superscalar. Compilers must be responsible for scheduling instructions to reduce the pipeline stalls for a particular degree of superscalar.3. Nonuniform superscalar: Although nonuniform superscalar potentially suffers instruction-class conflicts, it can be more cost-effective than uniform superscalar. Again compilers must take care that the class conflicts do not increase structural hazards.4. Static memory disambiguation: The DSNS architecture provides three types of LOAD/STORE instructions; strongly ordered, weakly ordered, and unordered. Memory disambiguation at compile time is responsible for marking each LOAD/STORE instruction. At run time, processors need not detect nor resolve data hazards for every type; they just perform memory accesses inorder for strongly or weakly ordered instructions, and arbitrarily for unordered.5. Static branch prediction with branch-target buffer: Branch instructions predicted as taken by compilers are stored in the branch target buffer. Hardware never guesses the outcomes of branch instructions.6. Early branch resolution with advanced conditioning: Advanced conditioning allows branch decisions to precede further the corresponding branches. It reduces the branch delay and results in resolving branches early in the pipeline.7. Conditional mode execution with dual register files: Dual register file facilitates maintaining the precise machine state that otherwise might be violated by speculative execution such as conditional mode.8. Weakly precise interrupts: The DSNS architecture defines interrupts as being somewhat imprecise but restartable with the help of interrupt handlers. The definition alleviates hardware constraints for ensuring precise interrupts strongly.This paper also presents an implementation of the DSNS architecture. The DSNS processor prototype under development is a four-stage pipelined processor of superscalar-degree four. The instruction pipelines, especially the branch pipeline, are discussed in detail.
On the chronometry and metrology of computer network timescales and their application to the network time protocol
Authors: David L. Mills
Venue: ACM SIGCOMM Computer Communication Review (1991)

This paper summarizes issues in computer network timekeeping with respect to the Network Time Protocol, which is used to synchronize time in many of the hosts and gateways of the Internet. It describes the methods used to coordinate and disseminate international time services and how they are incorporated into NTP time servers. It discusses the hazards on reckoning NTP dates with the conventional civil calendar and a standard method for numbering the days. Finally, the paper describes the NTP timescale, its mapping to conventional civil time and date and its interpretation of leap seconds.
Replication in the harp file system
Authors: Barbara Liskov, Sanjay Ghemawat, Robert Gruber, Paul Johnson, Liuba Shrira
Venue: ACM SIGOPS Operating Systems Review (1991)

This paper describes the design and implementation of the Harp file system. Harp is a replicated Unix file system accessible via the VFS interface. It provides highly available and reliable storage for files and guarantees that file operations are executed atomically in spite of concurrency and failures. It uses a novel variation of the primary copy replication technique that provides good performance because it allows us to trade disk accesses for network communication. Harp is intended to be used within a file service in a distributed network; in our current implementation, it is accessed via NFS. Preliminary performance results indicate that Harp provides equal or better response time and system capacity than an unreplicated implementation of NFS that uses Unix files directly.
A visit to a very small database: lessons from managing the review of papers submitted for CHI'91
Authors: John Rieman, Susan Davies, Jonathan Roberts
Venue: Proceedings of the SIGCHI conference on Human factors in computing systems (1992)

Many of the principles that guide user-interface design for commercial systems do not scale down to simple applications developed on personal computers. These &ldquo;very small systems&rdquo; are typicaly designed within a high-level application such as a database or a spreadsheet. The entire development process may take no more than a few days. In this restricted context, iterative design and usability testing are unaffordable luxuries, while detailed task analysis and early focus on users fail because the task and users will not coalesce until the system is in place. We describe our experiences with developing and using a very small sytem. We present suggestions for successful design in similar situations.
Syntactic and semantic knowledge in the DELPHI unification grammar
Authors: R. Bobrow, Robert Ingria, David Stallard
Venue: Proceedings of the workshop on Speech and Natural Language (1990)

This paper presents recent natural language work on HARC, the BBN Spoken Language System. The HARC system incorporates the Byblos system [6] as its speech recognition component and the natural language system Delphi, which consists of a bottom-up parser paired with an integrated syntax/semantics unification grammar, a discourse module, and a database question-answering backend. The paper focuses on the syntactic and semantic analyses made in the grammar.
On the approximation of maximum satisfiability
Authors: Mihalis Yannakakis
Venue: Proceedings of the third annual ACM-SIAM symposium on Discrete algorithms (1992)

We present a 3/4 polynomial time approximation algorithm for the Maximum Satisfiability problem: Given a set of clauses, find a truth assignment that satisfies the maximum number of clauses. The algorithm applies to the weighted case as well, and involves nontrival application of network flow techniques.
ISI
Authors: William C. Mann, Eduard H. Hovy
Venue: Proceedings of the workshop on Speech and Natural Language (1989)

The Penman Project at USC/ISI has been conducting research in natural language processing since 1978. It presently consists of six technical staff, organized into three principal efforts. The first two are funded by DARPA: - Natural language generation (Penman)
A parallel algorithmic version of the Local Lemma
Authors: Noga Alon
Venue: Proceedings of the 32nd annual symposium on Foundations of computer science (1991)

The Lovasz local lemma (1975) is a tool that enables one to show that certain events hold with positive, though very small probability. It often yields existence proofs of results without supplying any efficient way of solving the corresponding algorithmic problems. J. Beck has recently found a method for converting some of these existence proofs into efficient algorithmic procedures, at the cost of losing a little in the estimates, but his method does not seem to be parallelizable. His technique is modified to achieve an algorithmic version that can be parallelized, thus providing deterministic NC/sup 1/ algorithms for various interesting algorithmic search problems.
On Synthesizing Optimal Family of Linear Systolic Arrays for Matrix Multiplication
Authors: V. K. Prasanna Kumar, Yu-Chen Tsai
Venue: IEEE Transactions on Computers (1991)

The authors describe a family of linear systolic arrays for matrix multiplication exhibiting a tradeoff between local storage and the number of processing elements (PEs). The design consists of processors hooked into a linear array with each processor having storage s, 1>or=s>or=n, for n*n matrix multiplication, where the number of processors equals n times the least integer ¿n/s. The input matrices are fed as two speed data streams using fast and slow channels to satisfy the dependencies in the usual matrix multiplication algorithm. While a family of linear arrays have been synthesized for this problem, this technique leads to simpler designs with fewer number of processors and improved delay from input to output. All these designs use the optimal number of processors for local storage in the range 1>or=s>or=n. The data flow is unidirectional, which makes the designs implementable on fault wafer scale integration models.
Computer-assisted microanalysis of parallel programs
Authors: Timothy J. Hickey, Jacques Cohen, Hirofumi Hotta, Thierry PetitJean
Venue: ACM Transactions on Programming Languages and Systems (TOPLAS) (1992)

This paper consists of two parts: the first provides the theoretical foundations for analyzing parallel programs and illustrates how the theory can be applied to estimate the execution time of a class of parallel programs being executed on a MIMD computer. The second part describes a program analysis system, based on the theoretical model, which allows a user to interactively analyze the results of executing (or simulating the execution) of such parallel programs. Several examples illustrating the use of the tool are presented. A novel contribution is the separation (both at the conceptual and the implementation levels) of the machine-independent and the machine-dependent parts of the analysis. This separation enables the users of the system to establish speed-up curves for machines having varying characteristics.
The design of a spoken language interface
Authors: Jean-Michel Lunati, Alexander I. Rudnicky
Venue: Proceedings of the workshop on Speech and Natural Language (1990)

Fast and accurate speech recognition systems systems bring with them the possibility of designing effective voice driven applications. Efforts to this date have involved the construction of monolithic systems, necessitating repetition of effort as each new system is implemented. In this paper, we describe an initial implementation of a general spoken language interface, the Carnegie Mellon Spoken Language Shell (CM-SLS) which provides voice interface services to a variable number of applications running on the same computer. We also present a system built using CM-SLS, the Office Manager, which provides the user with voice access to facilities such as an appointment calendar, a personal database, and voice mail.
Real-time integration
Authors: H. K. Hodge
Venue: ACM SIGSMALL/PC Notes (1991)

That sounds somewhat redundant, doesn't it? What it means will become clear in the course of this narrative.
Statistical Resistance to Detection (Digital Circuits Testing)
Authors: A. Boneh, J. Savir
Venue: IEEE Transactions on Computers (1992)

Discusses the problem of estimating the sum of the detection probabilities of the yet unobserved faults during a random pattern test of a given digital circuit. The authors describe a statistical method for this purpose. The method requires keeping track of each fault until it is detected for the second time, and thus the simulation cost is about twice the cost of a similar simulation which abandons faults after their first detect. The benefits of having an estimate of the sum of these detection probabilities are twofold: (1) it provides a good stopping rule whenever 100% fault coverage is infeasible (which is often the case), and (2) it provides an estimate of the required effort to detect the next fault. The results of tests performed on some circuits are presented.
Optimized Feature Extraction and the Bayes Decision in Feed-Forward Classifier Networks
Authors: David Lowe, Andrew R. Webb
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1991)

The problem of multiclass pattern classification using adaptive layered networks is addressed. A special class of networks, i.e., feed-forward networks with a linear final layer, that perform generalized linear discriminant analysis is discussed, This class is sufficiently generic to encompass the behavior of arbitrary feed-forward nonlinear networks. Training the network consists of a least-square approach which combines a generalized inverse computation to solve for the final layer weights, together with a nonlinear optimization scheme to solve for parameters of the nonlinearities. A general analytic form for the feature extraction criterion is derived, and it is interpreted for specific forms of target coding and error weighting. An important aspect of the approach is to exhibit how a priori information regarding nonuniform class membership, uneven distribution between train and test sets, and misclassification costs may be exploited in a regularized manner in the training phase of networks.
On some classes of Petri nets (abstract)
Authors: Kunwarjit S. Bagga, Frank W. Owens
Venue: Proceedings of the 1990 ACM annual conference on Cooperation (1990)

Petri nets are used as models of asynchronous concurrent systems. The underlying structure of a Petri net is a bipartite digraph. Many properties of Petri nets and the systems they model can be described in graph theoretic terms. These include the notions of deadlocks and traps. In this paper we consider these properties by restricting attention to some special classes of Petri nets including simple, complete, and free-choice Petri nets.
A Markov Random Field Model-Based Approach to Image Interpretation
Authors: James W. Modestino, Jun Zhang
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1992)

An image is segmented into a collection of disjoint regions that form the nodes of an adjacency graph, and image interpretation is achieved through assigning object labels (or interpretations) to the segmented regions (or nodes) using domain knowledge, extracted feature measurements, and spatial relationships between the various regions. The interpretation labels are modeled as a Markov random field (MRF) on the corresponding adjacency graph, and the image interpretation problem is then formulated as a maximum a posteriori (MAP) estimation rule, given domain knowledge and region-based measurements. Simulated annealing is used to find this best realization or optimal MAP interpretation. This approach also provides a systematic method for organizing and representing domain knowledge through appropriate design of the clique functions describing the Gibbs distribution representing the pdf of the underlying MRF. A general methodology is provided for the design of the clique functions. Results of image interpretation experiments on synthetic and real-world images are described.
Solving two-state logic problems with Boolean arrays: an approach unique to APL
Authors: Kenneth Fordyce, Manuel Alfonseca, James Brown, Gerald Sullivan
Venue: ACM SIGAPL APL Quote Quad (1992)

Many great advances in science and mathematics were preceded by notational improvements. While a given algorithm can be implemented in any general purpose programming language, discovery of algorithms is heavily influenced by the notation used to investigate them. It is often conjectured that APL notation leads to unique solutions. In logic problems the values for variables are often limited to two states or options: yes/no, true/false, on/off, guilt/innocence, etc. This paper provides one example of how APL provides a unique solution to such problems.
Proposal of selection method test pictures in HDTV subjective quality assessments
Authors: Takeshi Tachi, Satoru Iai, Nobuhiko Kitawaki
Venue: ACM SIGCOMM Computer Communication Review (1992)

This paper describes definitive and systematic rules for selecting HDTV still test pictures to be used for properly assessing high-quality factors.We extracted three elementary psychological factors: "vividness," "comfortableness" and "sharpness," dominating the impression of HDTV still pictures, by using `Semantic Differential Method.' And HVC-signal characteristics, in Munsell color space, correlating closely with these factors were defined as selection guidelines of pictures symbolizing high-quality TV.
Allen Newell dies, age 65
Authors: Jill Fain Lehman, Paul Rosenbloom
Venue: ACM SIGART Bulletin (1992)

Dr. Oscar Garcia joined the IRIS staff on September 1, 1992, as Program Director for the Interactive Systems Program, while he is on leave from the George Washington University. The previous program director, Dr. Johnson Hestenes, returns to Drexel University to resume his professiorial duties.
Reliability Modeling: An Overview for System Designers
Authors: Andrew L. Reibman, Malathi Veeraraghavan
Venue: Computer (1991)

The role of reliability models in system design is examined. Methods for predicting system reliability are discussed, covering the choice of metric for analysis, creating the system reliability model, and refining the model. A case study is presented to illustrate reliability modeling.
Surface Identification Using the Dichromatic Reflection Model
Authors: Shoji Tominaga
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1991)

The author describes a method based on the dichromatic reflection model for identifying object surfaces. The surface spectral reflectance function of an inhomogeneous object is described as the sum of a constant interface (specular) reflectance and a body (diffuse) reflectance under all illumination geometries. The interface component is used to estimate the spectral power distribution of the illuminant without using a reference white standard, whereas the body component is used as the principal indication of the surface identity. The body reflectance function of each surface is recovered. A method to classify the observed reflectances is developed, and an algorithm to estimate a body reflectance function, unique to each surface, from the classified reflectances is proposed. The author shows the reliability of the surface classification method and the accuracy of estimated body reflectance function.
An object-oriented VHDL design environment
Authors: Moon Jung Chung, Sangchul Kim
Venue: Proceedings of the 27th ACM/IEEE Design Automation Conference (1991)

This paper presents a System-level Design Environment(SDE) for VHDL. The object-oriented approach is used for modeling the VHDL entities, design constraints and even design patterns. We suggest the data model and its internal schema, which is suitable for the VHDL semantics. SDE allows a designer to reconfigure the designed schematic by binding its generic components to technology-specific ones. It is effectively used for version control. SDE verifies the design by dynamically checking the constraints. The standard VHDL is extended in order to represent the constraints properly.
Integer forward differencing of cubic polynomials: analysis and algorithms
Authors: R. Victor Klassen
Venue: ACM Transactions on Graphics (TOG) (1991)

Two incremental cubic interpolation algorithms are derived and analysed. Each is based on a known linear interpolation algorithm and modified for third order forward differencing. The tradeoff between overflow avoidance and loss of precision has made forward differencing a method which, although known to be fast, can be difficult to implement. It is shown that there is one particular family of curves which represents the worst case, in the sense that if a member of this family can be accurately drawn without overflow, then any curve which fits in the bounding box of that curve can be. From this the limitations in terms of step count and screen resolution are found for each of the two algorithms.
Classification in Noisy Environments Using a Distance Measure Between Structural Symbolic Descriptions
Authors: Floriana Esposito, Donato Malerba, Giovanni Semeraro
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1992)

A definition of distance measure between structural descriptions that is based on a probabilistic interpretation of the matching predicate is proposed. It aims at coping with the problem of classification when noise causes both local and structural deformations. The distance measure is defined according to a top-down evaluation scheme: distance between disjunctions of conjuncts, conjunctions, and literals. At the lowest level, the similarity between a feature value in the pattern model (G) and the corresponding value in the observation (Ex) is defined as the probability of observing a greater distortion. The classification problem is approached by means of a multilayered framework in which the cases of single perfect match, no perfect match, and multiple perfect match are treated differently. A plausible solution for the problem of completing the attribute and structure spaces, based on the probabilistic approach, is also given. A comparison with other related works and an application in the domain of layout-based document recognition are presented.
Arithmetic Spectrum Applied to Fault Detection for Combinational Networks
Authors: Klaus D. Heidtmann
Venue: IEEE Transactions on Computers (1991)

A method for the derivation of fault signatures for the detection of faults in single-output combinational networks is described. The approach uses the arithmetic spectrum instead of the Rademacher-Walsh spectrum. It is a form of data compression that serves to reduce the volume of the response data at test time. The price which is paid for the reduction in the storage requirements is that some of the knowledge of exact fault location is lost. The derived signatures are short and easily tested using very simple test equipment. The test circuitry could be included on the chip since the overhead involved is comparatively small. The test procedure requires a high-speed counter cycling at maximum speed through selected subsets of all input combinations. Hence, the network under test is exercised at speed, and a number of dynamic errors that are not testable by means of conventional test-set approaches will be detected.
A Note on t-EC/d-UED Codes
Authors: D. L. Tao, C. R. P. Hartmann, P. K. Lala
Venue: IEEE Transactions on Computers (1991)

Recently D.J. Lin and B. Bose, (1988) proposed a class of t error correcting and d unidirectional error detecting codes (t-EC/d-UED codes) where d
Introducing users to network resources
Venue: ACM SIGUCCS Newsletter (1992)

You need to inform your users about network resources, but you don't want to reinvent the wheel and develop your own training materials from scratch! Here are some already-developed materials that could help you as well as your users.