ppxscal/embedding_network huggingface dataset:
Geometric Invariant Shape Representations Using Morphological Multiscale Analysis
Authors: L. Alvarez, A.-P. Blanc, L. Mazorra, F. Santana
Venue: Journal of Mathematical Imaging and Vision (2003)

In this paper, we present a new geometric invariant shape representation using morphological multiscale analysis. The geometric invariant is based on the area and perimeter evolution of the shape under the action of a morphological multiscale analysis. First, we present some theoretical results on the perimeter and area evolution across the scales of a shape. In the case of similarity transformations, the proposed geometric invariant is based on a scale-normalized evolution of the isoperimetric ratio of the shape. In the case of general affine geometric transformations the proposed geometric invariant is based on a scale-normalized evolution of the area. We present some numerical experiments to evaluate the performance of the proposed models. We present an application of this technique to the problem of shape classification on a real shape database and we study the well-posedness of the proposed models in the framework of viscosity solution theory.
Localizing Multiple Faults in a Protocol Implementation
Authors: Yoshiaki Kakuda, Hideki Yukitomo, Shinji Kusumoto, Tohru Kikuno
Venue: IEEE Design Test (1995)

A protocol is a set of rules which govern events such as transmission and reception of messages. Conformance testing of protocols is performed by observing events from the outside. Thus, faults must be localized only by observing such events. This paper proposes a protocol test sequence generation technique under two conditions. The characteristics of this technique are to generate test sequences based on protocol specifications and interim test results, and to find locations of multiple faults in protocol implementations. Although the length of the test sequence generated by the proposed technique is a little longer than the one generated by the previous techniques, the class of protocols to which the proposed technique can be applied is larger than that to which the previous techniques can be applied. Finally, the proposed technique is evaluated by simulation experiments with respect to the protocol class to which the proposed technique can be applied and the length of the test sequence which is generated by the proposed technique.
Analysis of Asynchronous Binary Arbitration on Digital Transmission-Line Busses
Authors: S. Kipnis
Venue: IEEE Transactions on Computers (1994)

A common misconception is that asynchronous binary arbitration settles in at most four units of bus-propagation delay, irrelevant of the number of arbitration bus lines. The author disproves this conjecture by presenting an arrangement of modules on m bus lines, for which binary arbitration requires /spl lsqb/m/2/spl rsqb/ units of bus-propagation delay to settle. He also proves that for any arrangement of modules on m bus lines, binary arbitration settles in at most /spl lsqb/m/2/spl rsqb/+2 units of bus-propagation delay.
Matchings and Hadwiger's conjecture
Authors: Andrei Kotlov
Venue: Discrete Mathematics (2002)

Assuming that a graph G on n vertices is a minimal counterexample to Hadwiger's Conjecture χ(G) ≤ η(G), we apply the Edmonds-Gallai Structure Theorem to its complement, H, to find that H has a matching of size ⌊n/2⌋. Hence Magyar Tud. Acad. Mat. Kutató Int. Közl. 8 (1963) 373: χ(G) ≤ ⌈n/2⌉. Further, H is homeomorphic to a three-connected graph, and is of tree width at least four. The same holds for a minimal counterexample G to Colin de Verdière's Conjecture µ(G) + 1 ≥ χ(G).
Screening Financial Innovations: An Expert System Approach
Authors: Sudha Ram, Sundaresan Ram
Venue: IEEE Expert: Intelligent Systems and Their Applications (1990)

An expert system, called Innovator, that helps a financial-service organization (FSO) evaluate new products it does not currently offer is described. Innovator was implemented using a rule-based expert system shell called Expert System Environment. The authors examine why FSOs need expert systems for screening financial innovations. The knowledge-representation and implementation details, and the system validation process are described. Innovator's benefits and continuing research are discussed.
VLSI architectures of the 1-D and 2-D discrete wavelet transforms for JPEG 2000
Authors: Sung Bum Pan, Rae-Hong Park
Venue: Signal Processing (2002)

This paper proposes efficient VLSI architectures for computation of the one-dimensional (1-D) and two-dimensional (2-D) discrete wavelet transforms (DWTs) for joint photographic experts group 2000. The proposed 1-D DWT architecture computes the wavelet lowpass and highpass output sequences using the lowpass filter architecture alone, whereas the conventional architectures compute the lowpass and highpass output sequences using both lowpass and highpass filter architectures. The proposed architecture is effectively applied to computation of the Daubechies 4-tap wavelet transform using the relationships between the Daubechies wavelet filter coefficients. The proposed architecture does not need memory and control units whereas conventional architectures need a complex control unit, memory unit, and so on. The two proposed VLSI architectures for the 2-D DWT are constructed based on block-based computation. Each M × N (N × M) block DWT is performed along the row and column directions simultaneously, where M and N denote the number of filter taps and the number of columns (rows), respectively, thus the required extra processing units of the proposed architectures are much smaller than those of the conventional architectures.
Process Deviations and Spot Defects: Two Aspects of Test and Test Development for Mixed-Signal Circuits
Authors: Carsten Wegener, Michael Peter Kennedy, Bernd Straube
Venue: Journal of Electronic Testing: Theory and Applications (2001)

By their nature, mixed-signal circuits have to be tested for both structural integrity and parametric performance. For the example of data converters we review test pattern selection strategies geared towards structural and performance testing. We introduce a novel test pattern selection strategy that merges both objectives, and by that we achieve a significant reduction in the size of the set of test patterns applied on the production line.
A Boolean Neural Network Approach for the Traveling Salesman Problem
Authors: S. Bhide, N. John, M. R. Kabuka
Venue: IEEE Transactions on Computers (1993)

It is shown that the Boolean-neural network can be used to solve NP-complete problems. The problem under consideration is the traveling salesman problem. The Boolean neural network has been modified to include the iterative procedure for solving combinatorial optimization problems. An architecture that utilizes this modified Boolean neural network (MBNN) is proposed for solving this problem. The simulation results have been found to be comparable to the simulated annealing algorithm (SAA), which is used as a test base. The MBNN implementation involves low hardware complexity, good noise immunity, and fast circuitry. This is very important in real-time systems and commercial job scheduling applications.
Traceability Process for Large OO Projects
Authors: Jean-Pierre Corriveau
Venue: Computer (1996)

Object-oriented software development has become popular, but scaling it up for large projects has been a problem. With large OO projects, late integration problems are a particular concern. They can cause schedule slippage and other difficulties. I developed a process called Traceability for OO Quality Engineering, or TOOQE, to minimize such problems. TOOQE emphasizes traceability and the integration of development and testing to achieve quality and maintainability. TOOQE features an iterative design process that lets developers correct mistakes and learn more about the problem they are trying to solve as they go along. Each iteration includes requirements capture, analysis, design, coding, and testing. In other words, each is a mini-life cycle. TOOQE's approach is also incremental. This lets each iteration build on its predecessor and eliminates the need to retest functionality at each iteration. Integration does not occur late in the process in TOOQE but instead occurs at each iteration. Moreover, integration entails immediate testing of the integrated artifacts, thus providing early and continuous feedback. For object-oriented analysis and design, you use three views of the system. The expression of each view requires at least one model, so OOA and OOD lead to the production of several models.
Future trends in software evolution metrics
Authors: Tom Mens, Serge Demeyer
Venue: Proceedings of the 4th International Workshop on Principles of Software Evolution (2001)

Since the famous statement "What is not measurable make measurable" of Galileo Galilei (1564 - 1642) it has been a major goal in science to quantify observations as a way to understand and control the underlying causes. With the growing awareness that evolution is a key aspect of software, an increasing number of computer scientists is investigating how metrics can be applied to evolving software artifacts. This paper provides a classification of the various approaches that use metrics to analyse, understand, control and improve the software evolution process, and identifies topics that require further research. As such, we expect that this paper will stimulate this emerging research area.
Visualization and Debugging in a Heterogeneous Environment
Authors: Adam Beguelin, Jack Dongarra, Al Geist, Vaidy Sunderam
Venue: Computer (1993)

The authors' experiences with visualization and debugging of parallel virtual machine (PVM) applications and two of the tools they have devised to facilitate these tasks are described. One of the tools is a graphical monitoring package called Xab that can visually display PVM activities inside an application running across a network. The other is a graphical programming environment called Hence, which helps the user write, compile, execute, and trace heterogeneous distributed programs. The authors discuss their early work, the present research, and the future directions of these experimental projects.
Optically Interconnected Multicomputers Using Inverted-Graph Topologies
Authors: Roger D. Chamberlain, Robert R. Krchnavek
Venue: IEEE Micro (1995)

Optical technology has made significant contributions to the state-of-the-art for long distance communications, including high reliability, low interference, security benefits, and (most important) very high bandwidth. However, the technology has yet to be successfully exploited in the domain of tightly-coupled multicomputer systems. To successfully exploit the benefits of optical technology in a tightly-coupled multicomputer, the architectural design must reflect both the advantages of optics and the limitations of optics. This article describes a class of such architectures, based upon inverted graph topologies. We consider the physical construction of these systems, demonstrating the relevant technological components necessary to manufacture a working system. We then consider two example topologies (an inverted hypercube and an inverted mesh), illustrating their properties, including processor labeling, topological embeddings, and message routing algorithms.
Cascading Content-Addressable Memories
Authors: Tim Moors, Antonio Cantoni
Venue: IEEE Micro (1992)

The various methods of connecting multiple content-addressable memory (CAM) devices to form a memory system of larger dimensions are surveyed. They include daisy-chaining CAMs to increase the number of elements and possibly using carry-lookahead logic to increase the cascade. To increase the data size, one can replicate the labels in distinct CAMs, use the data storage available in a primary CAM to index a secondary CAM/RAM (read-only memory), or reduce redundancy in labels. To increase the label size, one can use an element cascade with or without a shift register, a master-slave cascade, or a trie cascade. One of the methods examined for increasing the label size is a new trie cascade approach.
Joint Software Research Between Industry and Academia
Authors: Carl K. Chang, George B. Trubow
Venue: IEEE Software (1990)

A model for industry-sponsored academic software research tha helps the sponsor gain tangible results quickly but respects the university's research mission is presented. Central to the model is joint effort to achieve a win-win situation for all participants. The key is the relationship between the university's principal investigator and the company's visiting scholar. The principal investigator initiates research contracts and is responsible for research results but, because he or she is an academic, may not have an industrial perspective. The company dispatches a technical representative, called the visiting scholar, to participate directly in the daily research. A research structure, relations with the sponsoring company, issues regarding environmental compatibility and funding amount and duration, and a reporting structure are all spelled out in the model. Legal recommendations are made with respect to confidentiality, copyrights and patents, export controls, and other issues. Other considerations that arise when writing a research contract are discussed.
R: a data analysis and statistical programming environment-an emerging tool for the geosciences
Authors: E. C. Grunsky
Venue: Computers Geosciences (2002)

A statistical computation, programming and graphics language is available at no cost under the GNU Public Licence. This programming environment is available in source code and binary code forms and is supported for a number of operating systems. The R language is similar to the S language and is a package that allows users to apply methods of data analysis, statistics and graphical rendering of results in an interactive windows-based environment. The R language is supported by a large development and user's group. Additional data analysis and statistical libraries have been contributed by many users and can be obtained from the Comprehensive R Archive Network (CRAN).
Errata: Comments on 'Knowledge Representation Using Fuzzy Petri Nets'
Authors: Sheng-Ke Yu
Venue: IEEE Transactions on Knowledge and Data Engineering (1995)

This paper points out a serious mistake in Dr. Chen, Dr. Ke and Dr. Chang¿s paper.
A Limited-Global-Information-Based Multicasting Scheme for Faulty Hypercubes
Authors: Kejun Yao, Jie Wu
Venue: IEEE Transactions on Computers (1995)

We study the multicast problem in hypercubes with faulty nodes. We assume that each node has limited global information of fault distribution, which is captured by the safety level associated with the node. Basically, the safety level is an approximate measure of the distribution of faulty nodes in the neighborhood. We first propose a safety-level-based multicasting scheme which guarantees time optimality. We then present a variant of this scheme that reduces the number of traffic steps. Finally, an address-sum-based multicasting scheme is studied which utilizes both the distribution of destination nodes and the safety level of neighboring nodes. Simulation results show that the traffic generated in both schemes is very close to optimal. Time optimality is guaranteed when the source is safe and at most two additional time steps are required when the source is unsafe in an n-dimensional cube (denoted as n-cube) with up to n¿ 1 node faults.
Latency-guided on-chip bus network design
Authors: Milenko Drinic, Darko Kirovski, Seapahn Meguerdichian, Miodrag Potkonjak
Venue: Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design (2000)

Deep submicron technology scaling has two major ramifications on the design process. First, reduced feature size significantly increases wire delay, thus resulting in critical paths being dominated by global interconnect rather than gate delays. Second, ultra high level of integration mandates design of systems-on-chip that encompass numerous intra-synchronous blocks with decreased functional granularity and increased communication demands. To address these issues we have developed an on-chip bus network design methodology and corresponding set of tools which, for the first time, close the synthesis loop between system and physical design. The approach has three components: a communication profiler, a bus network designer, and a fast approximate floorplanner. The communication profiler collects run-time information about the traffic between system cores. The bus network design component optimizes the bus network structure by coordinating information from the other two components. The floorplanner aims at creating a feasible floorplan and to communicate information about the most constrained parts of the network.
The Starburst Active Database Rule System
Authors: Jennifer Widom
Venue: IEEE Transactions on Knowledge and Data Engineering (1996)

This paper describes our development of the Starburst Rule System, an active database rules facility integrated into the Starburst extensible relational database system at the IBM Almaden Research Center. The Starburst rule language is based on arbitrary database state transitions rather than tuple- or statement-level changes, yielding a clear and flexible execution semantics. The rule system has been implemented completely. Its rapid implementation was facilitated by the extensibility features of Starburst, and rule management and rule processing are integrated into all aspects of database processing.
Neural networks-based scheme for system failure detection and diagnosis
Authors: Y. M. Chen, M. L. Lee
Venue: Mathematics and Computers in Simulation (2002)

In this paper, the neural networks of fault tolerant control scheme in flight control is presented. The scheme can be broken up into three steps: fault detection, diagnosis, and accommodation. Particularly emphasis is placed on fault detection and diagnosis employing neural networks in this paper. The testing of the scheme is illustrated through F-16 aircraft model for an actuator failure.
Dynamic Scan: Driving Down the Cost of Test
Authors: Samitha Samaranayake, Nodari Sitchinava, Rohit Kapur, Minesh B. Amin, Thomas W. Williams
Venue: Computer (2002)

Two factors primarily drive the soaringcost of semiconductor test: thenumber of test patterns applied toeach chip and the time it takes to runeach pattern. Typical semiconductortesting for each chip involves a set of1,000 to 5,000 test patterns. These testsare applied through scan chains thatoperate at about 25 MHz. Depending onthe size of the scan chains on the chip, aset of test patterns can take a few secondsto execute per chip.It's easy to see that even a smalldecrease in either the number of patternsor the time to execute them can quicklyadd up to big savings across millions offabricated chips. This potential savingsforms the basis for dynamic scan, a newapproach to the well-established scan testmethodology.The authors' initial studies indicate thatdynamic scan could easily reduce the timespent applying test patterns by 40 percent.A more theoretical analysis shows apotential savings of as much as 80 percent.
An ASIC Chip Set for Parallel Fuzzy Database Mining
Authors: Alberto Ferrari, Antonella Bellettini, Roberto Guerrieri, Giorgio Baccarani
Venue: IEEE Micro (1996)

This paper describes the design and implementation of an application-specific digital architecture aimed at performing the mining of fuzzy databases, a task whose computational weight is very high. The system described here is an array-processor architecture in which the database is split into several units that apply the same operations to different data stored in local memories at the same time. A chip set implementing the architecture has been built using a semicustom approach and it is fully functional. The sustained memory bandwidth of a system featuring 16 units is 5,120 Mbits/s and provides a speedup of 500 times over the software algorithm running on a Sun Sparc2 workstation.
On Group Communication Support in CORBA
Authors: Shivakant Mishra, Lan Fei, Xiao Lin, Guming Xing
Venue: IEEE Transactions on Parallel and Distributed Systems (2001)

Current group communication services have mostly been implemented on a homogeneous, distributed computing environment. This limits their applicability because most modern distributed computing environment are heterogeneous in nature. This paper describes the design, implementation, and performance evaluation of a CORBA group communication service. Using CORBA to implement a group communication service enables that group communication service to operate in a heterogeneous, distributed computing environment. To evaluate the effect of CORBA on the performance of a group communication service, this paper provides a detailed comparison of the performance measured from three implementations of an atomic broadcast protocol and a group membership protocol. Two of these implementations use CORBA, while the third uses UDP sockets for interprocess communication. The main conclusion is that heterogeneity can be achieved in group communication services by implementing them using CORBA, but there is a substantial performance cost. This performance cost can be reduced to a certain extent by carefully choosing a design and tuning various protocol parameters such as buffer sizes and timer values.
The Ant System Applied to the Quadratic Assignment Problem
Authors: Vittorio Maniezzo, Alberto Colorni
Venue: IEEE Transactions on Knowledge and Data Engineering (1999)

In recent years, there has been growing interest in algorithms inspired by the observation of natural phenomena to define computational procedures that can solve complex problems. In this article, we describe a distributed heuristic algorithm that was inspired by the observation of the behavior of ant colonies, and we propose its use for the Quadratic Assignment Problem. The results obtained in solving several classical instances of the problem are compared with those obtained from other evolutionary heuristics to evaluate the quality of the proposed system.
Constructing Communication Subgraphs and Deriving an Optimal Synchronization Interval for Distributed Virtual Environment Systems
Authors: John C. S. Lui
Venue: IEEE Transactions on Knowledge and Data Engineering (2001)

In this paper, we consider problems of constructing a communication subgraph and deriving an optimal synchronization interval for a distributed virtual environment system (DVE). In general, a DVE system is a distributed system which allows many clients who are located in different parts of the network to concurrently explore and interact with each other under a high resolution, 3D, graphical virtual environment. Each client in a DVE system is represented by an avatar in the virtual environment, and each avatar can move and interact freely in the virtual environment. There are many challenging issues in designing a cost-effective DVE system. In this work, we address two important design issues, namely: 1) how to construct a communication subgraph which can efficiently carry traffic generated by all clients in a DVE system, and 2) how to guarantee that each participating client has the same consistent view of the virtual world. In other words, if there is an action taken by an avatar or if there is any change in the state of an object in the virtual world, every participating client will be able to view the change. To provide this consistent view, a DVE system needs to perform synchronization actions periodically. We present several algorithms for constructing a communication subgraph. In the subgraph construction, we try to reduce the consumption of network bandwidth resources or reduce the maximum delay between any two clients in a DVE system. Based on a given communication subgraph, we then derive the optimal synchronization interval so as to guarantee the view consistency among all participating clients. The derivation of the optimal synchronization interval is based on the theory of Markov chains and the fundamental matrix.