ppxscal/embedding_network huggingface dataset:
Application of IBM 1620 EDP methods to the calculation of the formulation constants of complex ions
Authors: A. C. Andrews, John Hassler, Frank DeCou
Venue: Communications of the ACM (1963)

In the course of our work on the physical chemistry of histamine and related compounds, we have done extensive work involving potentiometric titration of systems of chelates of these ligands with various metallic ions, negative ions, and small molecules. The resulting data is used to calculate the stability constants in solution (1, 2, 3, 4). The mathematical calculations for a single titration require two to four hours when done on a desk calculator, even when the operator is experienced. This is a serious disadvantage of the technique. The more accurate methods of successive approximations and of simultaneous equations [2] are so time consuming that their routine use is impractical without the aid of a high speed computer.
Quality assessment for drainage networks and watershed boundaries extraction from a digital elevation model (DEM)
Authors: Julie Charleux-Demargne, Christian Puech
Venue: Proceedings of the 8th ACM international symposium on Advances in geographic information systems (2000)

The use of DEMs in hydrology requires new quality control criteria for drainage analysis. This paper presents an operational and quantitative method of controlling the quality of drainage networks and watershed boundaries extracted from a grid DEM with the D8 flow routing approach. This method enables us to quantify the grid bias induced by the D8 algorithm on the extracted objects and to optimize a DEM-reengineering technique.
Interconnect implications of growth-based structural models for VLSI circuits
Authors: Chung-Kuan Cheng, Andrew B. Kahng, Bao Liu
Venue: Proceedings of the 2001 international workshop on System-level interconnect prediction (2001)

Power-law scaling phenomena that govern VLSI circuits have for several decades formed the foundation of VLSI interconnect estimation. This research investigates possible alternative power-law phenomena in VLSI circuits. In particular, we develop newrandom growthmodels and assess their implications for VLSI interconnect structure. We assess our models' predictions forfanout,crossing edge, andterminalscaling using test data from 21 industry standard-cell designs with up to 283K cells. Our work demonstrates the possibility of non-Rent based, yet equally plausible and well-fitting, structural models for VLSI circuits and their interconnections.
Equivalence between AND/OR graphs and context-free grammars
Authors: Patrick A. V. Hall
Venue: Communications of the ACM (1973)

Recent research in artificial intelligence has led to AND/OR graphs as a model of problem decomposition (Nilsson [3]; Simon and Lee [4]). However, AND/OR graphs of a restricted type are equivalent to context-free grammars. This can be set-up formally (the beginnings of a formalism of AND/OR graphs is contained in [4]), but the formalism is so obvious that a brief discussion and example suffice.
Parallel Sorting with Limited Bandwidth
Authors: Micah Adler, John W. Byers, Richard M. Karp
Venue: SIAM Journal on Computing (2000)

We study the problem of sorting on a parallel computer with limited communication bandwidth. By using the PRAM(m) model, where p processors communicate through a globally shared memory which can service m requests per unit time, we focus on the trade-off between the amount of local computation and the amount of interprocessor communication required for parallel sorting algorithms. Our main result is a lower bound of $\Omega(\frac{n \log m}{m \log n})$ on the time required to sort n numbers on the exclusive-read and queued-read variants of the PRAM(m). We also show that Leighton's Columnsort can be used to give an asymptotically matching upper bound in the case where m grows as a fractional power of n. The bounds are of a surprising form in that they have little dependence on the parameter p. This implies that attempting to distribute the workload across more processors while holding the problem size and the size of the shared memory fixed will not improve the optimal running time of sorting in this model. We also show that both the lower and the upper bounds can be adapted to bridging models that address the issue of limited communication bandwidth: the LogP model and the bulk-synchronous parallel (BSP) model. The lower bounds provide further convincing evidence that efficient parallel algorithms for sorting rely strongly on high communication bandwidth.
Computing Functions of a Shared Secret
Authors: Amos Beimel, Mike Burmester, Yvo Desmedt, Eyal Kushilevitz
Venue: SIAM Journal on Discrete Mathematics (2000)

In this work we introduce and study threshold (t-out-of-n) secret sharing schemes for families of functions ${\cal F}$. Such schemes allow any set of at least t parties to compute privately the value f(s) of a (previously distributed) secret s, for any $f\in {\cal F}$. Smaller sets of players get no more information about the secret than what follows from the value f(s). The goal is to make the shares as short as possible. Results are obtained for two different settings: we study the case when the evaluation is done on a broadcast channel without interaction, and we examine what can be gained by allowing evaluations to be done interactively via private channels.
A Note on Maxflow-Mincut and Homomorphic Equivalence in Matroids
Authors: Winfried Hochstättler, Jaroslav Nešetřil
Venue: Journal of Algebraic Combinatorics: An International Journal (2000)

Graph homomorphisms are used to study good characterizations for coloring problems i>Trans. Amer. Math. Soc. 384 (1996), 1281&ndash;1297&semi; i>Discrete Math. 22 (1978), 287&ndash;300). Particularly, the following concept arises in this context: A pair of graphs (i>A, i>B) is called a i>homomorphism duality if for any graph i>G either there exists a homomorphism &sigma; : i>A &rarr; i>G or there exists a homomorphism &tau; : i>G &rarr; i>B but not both. In this paper we show that maxflow-mincut duality for matroids can be put into this framework using strong maps as homomorphisms. More precisely, we show that, if i>Ci>k denotes the circuit of length i>k + 1, the pairs (i>Ci>k, i>Ci>k + 1) are the only homomorphism dualities in the class of duals of matroids with the strong integer maxflow-mincut property (i>Jour. Comb. Theor. Ser.B 23 (1977), 189&ndash;222). Furthermore, we prove that for general matroids there is only a trivial homomorphism duality.
Skeletonization of Three-Dimensional Object Using Generalized Potential Field
Authors: Jen-Hi Chuang, Chi-Hao Tsai, Min-Chi Ko
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (2000)

The medial axis transform (MAT) is a skeletal representation of an object which has been shown to be useful in interrogation, animation, finite element mesh generation, path planning, and feature recognition. In this paper, the potential-based skeletonization approach for 2D MAT [1], which identifies object skeleton as potential valleys using a Newtonian potential model in place of the distance function, is generalized to three dimensions. The generalized potential functions given in [2], which decay faster with distance than the Newtonian potential, is used for the 3D case. The efficiency of the proposed approach results from the fact that these functions and their gradients can be obtained in closed forms for polyhedral surfaces. According to the simulation results, the skeletons obtained with the proposed approach are closely related to the corresponding MAT skeletons. While the medial axis (surface) is 2D in general for a 3D object, the potential valleys, being one-dimensional, form a more realistic skeleton. Other desirable attributes of the algorithm include stability against perturbations of the object boundary, the flexibility to obtain partial skeleton directly, and low time complexity.
Optimal Policies for n-Dimensional Singular Stochastic Control Problems Part I: The Skorokhod Problem
Authors: Lukasz Kruk
Venue: SIAM Journal on Control and Optimization (2000)

An n-dimensional Brownian motion is controlled by adding a process of locally bounded variation to it so as to minimize an expected infinite-horizon discounted cost. We show, by direct probabilistic techniques, that the optimal control is a solution of a (generalized) Skorokhod problem.
ESP: a system utilization benchmark
Authors: Adrian T. Wong, Leonid Oliker, William T. C. Kramer, Teresa L. Kaltz, David H. Bailey
Venue: Proceedings of the 2000 ACM/IEEE conference on Supercomputing (CDROM) (2000)

This article describes a new benchmark, called the Effective System Performance (ESP) test, which is designed to measure system-level performance, including such factors as job scheduling efficiency, handling of large jobs and shutdown-reboot times. In particular, this test can be used to study the effects of various scheduling policies and parameters. We present here some results that we have obtained so far on the Cray T3E and IBM SP systems, together with insights obtained from simulations.
Performance analysis of session oriented data communications for mobile computing in cellular systems
Authors: Yunsang Park, Stephen S. Rappaport
Venue: Wireless Networks (2000)

Future cellular communication systems must seamlessly support services for a wide range of user needs, including voice, data, video and multi&dash;media. It is envisioned that mobile users may do much computer processing in an off&dash;line mode but must occasionally connect to a network in order to exchange data and&sol;or files. For this purpose a communication session is initiated. During the session the user has access to network resources, although this access may be shared with others. Owing to the mobile environment, the user&apos;s connection to the network during a session may be severed. Since the mobile user can act semi&dash;autonomously, such disconnections can be transparent. That is, the mobile user can continue to function in an off&dash;line mode while the system will begin transparent automatic reconnection attempts to reestablish a link to the network. Only after a fixed &lpr;given&rpar; number of such attempts to reconnect have failed, is the session deemed to have failed. The issue is complicated by the hostile mobile radio environment and by user mobility. We consider session&dash;oriented communications and develop a tractable analytical model for traffic performance based on multi&dash;dimensional birth&ndash;death processes. The approach allows consideration of various platform types, such as pedestrians, automobiles, and buses, which may have very different mobility characteristics. Performance characteristics, such as: blocking, forced session termination, carried traffic, the average time per suspension, and the average number of suspensions per session, are calculated.
Interconnect prediction for programmable logic devices
Authors: Michael Hutton
Venue: Proceedings of the 2001 international workshop on System-level interconnect prediction (2001)

Classical interconnect prediction would seem to be a perfect fit for the design of programmable logic architectures (PLDs). Yet theoretical models such as those based on Rent's Rule are usually only used for rough estimates in the early stages of an architecture development. In practice, empirical methods (evaluation via many test designs) dominate the evaluation of fitting and performance for PLD architectures.The primary reasons for this gap between theory and practice are that the models are difficult to extend to fixed architectures with hierarchy and heterogeneous resources and that many of the cost metrics are different between gate-arrays and PLDs.In this paper and the accompanying talk I will survey some of the issues with line-count estimation for the design of PLDs. I will point out some of the inherent differences between the way interconnect is used in PLDs and gate arrays which lead to new opportunities in the development of the theory. Some previous results will show how interconnect is typically researched in the PLD community. For an idealized PLD architecture, I will attempt to define a simple line-count estimation model using the classical theory and compare it to results in practice. I will also present some empirical and anecdotal data useful for understanding the issues and pitfalls involved in architecture evaluation.The primary goal of this work is to motivate new directions in the theory of interconnect prediction and interconnect prediction specifically for PLDs.
Publish your Excel grade book on the Web
Authors: Torben Lorenzen
Venue: ACM SIGCSE Bulletin (2000)

I have created an Excel spreadsheet to use as my course grade book. I will begin with an overview of such a sample grade book that I use in a course, teaching students about Microsoft Office. I will then tell you how I use the grade book, the equations that make it work, how to download it from the web, and finally how to modify it.
When will the analog design flow catch up with digital methodology? (panel session)
Authors: Georges Gielen, Mar Hershenson, Ken Kundert, Philippe Magarshack, Akira Matsuzawa, Ronald A. Rohrer, Ping Yang
Venue: Proceedings of the 38th annual Design Automation Conference (2001)

Despite the fact that more and more electronic design is comprised of analog and mixed signal content, the design flows and methodologies in this area are lagging behind the pace of innovation in digital design. For sure, analog designers are in shorter supply, but this only makes the need for improvements and efficiency that much greater. Only of late have we seen production-worth attempts at functions such as analog synthesis and optimization reach the market. What is needed in today's analog design flow? What are the key technologies that are missing? How does the existing &ldquo;food chain&rdquo; need to work together to drive greater efficiencies?A distinguished panel of suppliers and users assemble to discuss, analyze and predict.
Low power techniques for address encoding and memory allocation
Authors: Wei-Chung Cheng, Massoud Pedram
Venue: Proceedings of the 2001 Asia and South Pacific Design Automation Conference (2001)

This paper presents encoding techniques to optimize the switching activity on a multiplexed DRAM address bus. The DRAM switching activity can be classified either as external (between two consecutive addresses) or internal (between the row and column addresses of the same address). To eliminate the external switching activity for sequential access, we propose an optimal encoding, Pyramid code, for conventional DRAM mode as well as Burst Pyramid code for burst mode DRAM. To minimize the internal switching activity, we propose Scattered Paging for both random and sequential access patterns by exploiting the built-in virtual memory mechanism, which is commonly present on modern processors.
Separating a Superclass of Comb Inequalities in Planar Graphs
Authors: Adam N. Letchford
Venue: Mathematics of Operations Research (2000)

Many classes of valid and facet-inducing inequalities are known for the family of polytopes associated with theSymmetric Travelling Salesman Problem (STSP), includingsubtour elimination, 2-matching andcomb inequalities. For a given class of inequalities, anexact separation algorithm is a procedure which, given an LP relaxation vectorx*, finds one or more inequalities in the class which are violated byx*, or proves that none exist. Such algorithms are at the core of the highly successfulbranch-and-cut algorithms for the STSP. However, whereas polynomial time exact separation algorithms are known for subtour elimination and 2-matching inequalities, the complexity of comb separation is unknown.Apartial answer to the comb problem is provided in this paper. We define ageneralization of comb inequalities and show that the associated separation problem can be solved efficiently when the subgraph induced by the edges withx*e>0 is planar. The separation algorithm runs in O( n3) time, wheren is the number of vertices in the graph.
Structure of a LISP system using two-level storage
Authors: Daniel G. Bobrow, Daniel L. Murphy
Venue: Communications of the ACM (1967)

In an ideal list-processing system there would be enough core memory to contain all the data and programs. Described in this paper are a number of techniques that have been used to build a LISP system utilizing a drum for its principal storage medium, with a surprisingly low time penalty for use of this slow storage device. The techniques include careful segmentation of system programs, allocation of virtual memory to allow address arithmetic for type determination, and a special algorithm for building reasonably linearized lists. A scheme for binding variables is described which is good in this environment and allows for complete compatibility between compiled and interpreted programs with no special declarations.
Fast field solvers for thermal and electrostatic analysis
Authors: V. Székely, M. Rencz
Venue: Proceedings of the conference on Design, automation and test in Europe (1998)

Two different field solver tools have been developed in order to facilitate fast thermal and electro-static simulation of microsystem elements. The MS-THERMANAL program is capable for the fast steady state and dynamic simulation of suspended multilayered microsystem structures. The 2D-SUNRED program is the first version of a general field solver based on an original method, the successive node reduction. SUNRED offers a very fast and accurate substitute of FEM programs for the solution of the Poisson equation. Steady state and dynamic simulation examples demonstrate the wide usability of the novel tool.
Statistical Learning Theory: A Primer
Authors: Theodoros Evgeniou, Massimiliano Pontil, Tomaso Poggio
Venue: International Journal of Computer Vision (2000)

In this paper we first overview the main concepts of Statistical Learning Theory, a framework in which learning from examples can be studied in a principled way. We then briefly discuss well known as well as emerging learning techniques such as Regularization Networks and Support Vector Machines which can be justified in term of the same induction principle.
Obtaining Fault Tolerant Multilayer Perceptrons Using an Explicit Regularization
Authors: Jose L. Bernier, J. Ortega, I. Rojas, E. Ros, A. Prieto
Venue: Neural Processing Letters (2000)

When the learning algorithm is applied to a MLP structure, different solutions for the weight values can be obtained if the parameters of the applied rule or the initial conditions are changed. Those solutions can present similar performance with respect to learning, but they differ in other aspects, in particular, fault tolerance against weight perturbations. In this paper, a backpropagation algorithm that maximizes fault tolerance is proposed. The algorithm presented explicitly adds a new term to the backpropagation learning rule related to the mean square error degradation in the presence of weight deviations in order to minimize this degradation. The results obtained demonstrate the efficiency of the learning rule proposed here in comparison with other algorithm.
Further survey of punched card codes
Authors: H. McG. Ross
Venue: Communications of the ACM (1961)

The valuable &ldquo;Survey of Punched Card Codes&rdquo; prepared by Smith and Williams (Comm. ACM 3, Dec. 1960, 638) unfortunately omits the card codes of European equipment, other than IBM. These are presented in the table on page 181. This information has been extracted from a Ferranti publication, &ldquo;Collected Information on Punched Card Codes&rdquo; (List CS 266) and has been set out in much the same way as the table by Smith and Williams. The ACM Portal is published by the Association for Computing Machinery. Copyright © 2010 ACM, Inc. Terms of Usage Privacy Policy Code of Ethics Contact Us Useful downloads: Adobe Acrobat QuickTime Windows Media Player Real Player
Win32 system services: the heart of Windows 98 and Windows 2000
Authors: Marshall Brain, Ron Reeves
Venue: Microsoft Technologies Series (2000)

The Win32 best-seller, fully updated for Windows 2000 and Windows 98! Master every key Win32 system service Processes, threads, synchronization, and much more Includes extensive coverage of network programming CD-ROM: Hundreds of proven code examples! The #1 guide to Win32 system services, totally updated! Includes hundreds of proven code examples - in the book and on CD-ROM Comprehensive coverage of RPCs and other network programming topics Processes, threads, and synchronization - in depth Expert techniques for effective large-scale development Leveraging Windows 2000's security capabilitiesGet up-to-speed on the Win32 API, fast!The #1 best-seller - now completely updated!For years, Marshall Brain's Win32 System Services has been the world's #1 resource for Windows developers seeking to master Win32 services in real-world application development. Now, this worldwide bestseller has been fully updated to reflect the latest Win32 enhancements in Windows 2000 and Windows 98!Each self-contained chapter covers a different API service: Win32 files, directory and drive structure, processes and threads, synchronization mechanisms, network communications, Remote Procedure Calls, security, consoles, communications ports, accessing system information, using DLLs to modularize programs, and much more.You'll find practical guidance on when to use each service, today's best techniques for integrating services into complex, enterprise-class applications, and extensive proven code examples. Whether you're an experienced Windows developer seeking to deepen your system programming skills, or you're porting applications from other environments, Win32 System Services - The Heart of Windows 98 and Windows 2000, Third Edition will be your most valuable resource.About the CD-ROMThe accompanying CD-ROM contains all the source code presented in the book.
Interconnect complexity-aware FPGA placement using Rent's rule
Authors: G. Parthasarathy, M. Marek-Sadowska, Arindam Mukherjee, Amit Singh
Venue: Proceedings of the 2001 international workshop on System-level interconnect prediction (2001)

Field Programmable Gate Arrays (FPGAs) have gained in commercial acceptance because they offer instant manufacturing turnaround and low costs. However, FPGAs are constantly hard pressed to keep up with the requirements of the more complex and larger scale circuits which are being targeted for them. Routability of a circuit depends on the FPGA architecture, the placement, and the interconnection complexity of the circuit to be placed and routed. This paper explores the use of Rent's rule as a complexity metric for improving the placement of circuits on a target FPGA architecture, such that routing resource utilization is improved. A new simulated annealing based placement algorithm is presented and experimental results are presented to illustrate the validity of the approach for certain example circuits and the ISCAS benchmarks.
Object-based collective communication in Java
Authors: Arnold Nelisse, Thilo Kielmann, Henri E. Bal, Jason Maassen
Venue: Proceedings of the 2001 joint ACM-ISCOPE conference on Java Grande (2001)

CCJ is a communication library that adds MPI-like collective operations to Java. Rather than trying to adhere to the precise MPI syntax, CCJ aims at a clean integration of collective communication into Java's object-oriented framework. For example, CCJ uses thread groups to support Java's multithreading model and it allows any data structure (not just arrays) to be communicated. CCJ is implemented entirely in Java, on top of RMI, so it can be used with any Java virtual machine. The paper discusses three parallel Java applications that use collective communication. It compares the performance (on top of a Myrinet cluster) of CCJ, RMI and mpiJava versions of these applications, and also compares the code complexity of the CCJ and RMI versions. The results show that the CCJ versions are significantly simpler than the RMI versions and obtain a good performance.