ppxscal/embedding_network huggingface dataset:
A Hierarchical Taxonomic System for Computer Architectures
Authors: Subrata Dasgupta
Venue: Computer (1990)

A novel hierarchical architectural taxonomic system that appears to possess the desirable characteristics of a good taxonomic scheme is presented. The author focuses on the endoarchitecture, i.e. the logical structure, control and behavior of the integrated system of hardware components. The starting point for this system is D.B. Skillicorn's scheme (see ibid., vol.21, no.11, p.46-57, 1988). However, the system both extends and departs from Skillicorn's scheme, using formulas inspired by chemical notation to classify computer architectures in a way that provides both predictive power and explanatory capabilities.
An architecture of a dataflow single chip processor
Authors: S. Sakai, y. Yamaguchi, K. Hiraki, Y. Kodama, T. Yuba
Venue: ACM SIGARCH Computer Architecture News (1989)

A highly parallel (more than a thousand) dataflow machine EM-4 is now under development. The EM-4 design principle is to construct a high performance computer using a compact architecture by overcoming several defects of dataflow machines. Constructing the EM-4, it is essential to fabricate a processing element (PE) on a single chip for reducing operation speed, system size, design complexity and cost. In the EM-4, the PE , called EMC-R, has been specially designed using a 50,000-gate gate array chip. This paper focuses on an architecture of the EMC-R. The distinctive features of it are: a strongly connected arc dataflow model; a direct matching scheme; a RISC-based design; a deadlock-free on-chip packet switch; and an integration of a packet-based circular pipeline and a register-based advanced control pipeline. These features are intensively examined, and the instruction set architecture and the configuration architecture which exploit them are described.
Compiling rules from constraint satisfaction problem solving
Authors: S. Subramanian, E. c. Freuder
Venue: Issue 108 (April 1989) (1989)

We have been developing a learning system for automating the acquisition of problem solving knowledge. The basic technique used is the compilation of rules from observation of problem solving behavior. Our approach is novel in attempting to compile rules from the observation of constraint-based, relaxation-based problem solving.
The Maximum and Minimum Selector SELRAM and its Application for Developing Fast Sorting Machines
Authors: A. Kapralski
Venue: IEEE Transactions on Computers (1989)

The construction of a fast maximum or minimum selecting device called SELRAM is presented. Its basic component is the MAX device, an iterative circuit whose component is a parallel bit selector (PBS). There are two types of MAX device: TMAX, which is iterated in time and uses one PBS, and SMAX, which is iterated in space and uses m PBSs. If TMAX is a component of SELRAM, then m clock periods are required for selecting a maximum, and if SMAX is a component, only one clock period of O(mn) time is needed. Another component of SELRAM is the SFO (selecting the first one) block, which can be performed in many ways, giving different propagation delays and requiring different numbers of internal connections. The construction of SELRAM makes it possible to sort a given file of records in O(mn) time, and the constant for this estimation depends on the amount of hardware used but is generally very low. VLSI technology is very convenient for manufacturing SELRAM chips.
Description for a Tool Specifying and Prototyping Concurrent Programs
Authors: N. De Francesco, G. Vaglini
Venue: IEEE Transactions on Software Engineering (1988)

A specification language is introduced, able to define the behavior of concurrent programs. The language is particularly devoted to describing distributed applications, mainly with respect to scheduling problems. For this purpose, the language allows visibility of the past history of a computation and such history may be explicitly used to derive the choices on the future behavior of the computation itself and to define the values exchanged at each communication. A behavior is a partial order on events (communications) accomplished by processes, while the values of the communications are specified by a functional language. The most noticeable characteristic of specifications written in this language is the capability to be easily translated into executable concurrent programs (written into a CSP-like concurrent language), so obtaining an early prototype for these programs. An algorithm is described to accomplish the translation. An environment is provided to support static semantics checks on specifications, while dynamic testing and debugging are accomplished using interactive tools of the concurrent language environment.
Simulation of simplicity: a technique to cope with degenerate cases in geometric algorithms
Authors: H. Edelsbrunner, E. P. Mücke
Venue: Proceedings of the fourth annual symposium on Computational geometry (1988)

This paper describes a general purpose programming technique, called the Simulation of Simplicity, which can be used to cope with degenerate input data for geometric algorithms. It relieves the programmer from the task to provide a consistent treatment for every single special case that can occur. The programs that use the technique tend to be considerably smaller and more robust than those obtained without using it. We believe that this technique will become a standard tool in writing geometric software.
Towards Banishing the Cut from Prolog
Authors: Saumya K. Debray, David S. Warren
Venue: IEEE Transactions on Software Engineering (1990)

Logic programs can often be inefficient. The usual solution to this problem has been to return some control to the user in the form of impure language features like cut. The authors argue that it is not necessary to resort to such impure features for efficiency. This point is illustrated by considering how most of the common uses of cut can be eliminated from Prolog source programs, relying on static analysis to generate them at compile time. Three common situations where the cut is used are considered. Static analysis techniques are given to detect such situations, and applicable program transformations are described. Two language constructs, firstof and oneof, for situations involving don't-care nondeterminism, are suggested. These constructs have better declarative readings than the cut and extend better to parallel evaluation strategies. Together, these proposals result in a system where users need rely much less on cuts for efficiency, thereby promoting a purer programming style without sacrificing efficiency.
The second generation FPS T series: an enhanced parallel vector supercomputer
Authors: R. J. Fazzari, J. D. Lynch
Venue: Proceedings of the third conference on Hypercube concurrent computers and applications: Architecture, software, computer systems, and general issues - Volume 1 (1988)

The FPS T Series is a parallel vector supercomputer incorporating up to 16,384 compute nodes into a network based on the binary n-cube interconnect. The compute node has been enhanced to improve floating-point scalar and vector performance, and to increase memory size and internode communication bandwidth. The control processor contains a microcomputer with a peak of 10 MIPS, a floating-point unit with a peak of 1.5 MFLOPS for 64-bit operands, four communication links which provide a combined peak of 9.2 MBytes/s for bidirectional data transfers, and 256 KBytes of program memory. The five-ported data memory is composed of four MBytes of DRAM and four 4-KByte vector registers for fast access by the vector processor. The vector processor consists of a floating-point ALU and a floating-point multiplier/divider, which together can perform 32- and 64-bit arithmetic at 19 MFLOPS. This paper describes the architecture and capabilities of the second generation FPS T Series.
Direct connect emulation and the project life cycle
Authors: M. W. Hitchens, T. K. Ryan
Venue: Proceedings of the 21st conference on Winter simulation (1989)

Simulation modeling is viewed as an evolving process. Initial models are broad-based and are used to answer concept questions. These answers lead to system decisions which allow construction of more detailed models. These models are used to answer more detailed system questions, giving rise to still more representative models. These more detailed needs begin to bridge the gap between system design and design implementation. Direct connect emulation extends the use of simulation modeling into the actual startup and operational phases of the system. Emulation is defined as an intermediate stage of simulation where the model represents the "as specified" mechanical plant and equipment. At this point it contains sufficient detail to accurately test the control logic by direct connection to the controller. Verification and maintenance monitoring is defined as the final stage of simulation modeling where the model represents the "as built" mechanical plant and equipment.
Concurrent object-oriented real-times systems research
Authors: D. Kafura
Venue: ACM SIGPLAN Notices (1989)

This research investigates how to build real-time systems using a concurrent object-oriented programming language based on the actor model [Agha86]. The close parallels between the characteristics of concurrent object oriented languages and real-time systems motivates this investigation. Successful use of the actor model in closely related problem domains [Bake78, Barr87, Atha87, Yone87, Dela88] also suggests that this a fruitful line of inquiry. The research is composed of three interrelated projects: bull; designing a concurrent object-oriented programming language, named ACT++, for real-time system applications. bull; using ACT++ in representative real-time applications. bull; constructing a distributed real-time kernel, named REACT, to support the execution of ACT++ applications.The language and the kernel are distinctive because they (1) use fine-medium grained concurrency, termed ultralight processes, (2) support the combination of inheritance with the actor model of computation, and (3) are based on automatic, distributed, incremental real-time garbage collection of concurrent objects - removing error-prone management concerns from developers and unifying process (time) and memory management. An extended "white paper" describing these projects is available from the author on request.
Continuations may be unreasonable
Authors: Albert Meyer, Jon G. Riecke
Venue: Proceedings of the 1988 ACM conference on LISP and functional programming (1988)

We show that two lambda calculus terms can be observationally congruent (i.e., agree in all contexts) but their continuation-passing transforms may not be. We also show that two terms may be congruent in all untyped contexts but fail to be congruent in a calculus with call/cc operators. Hence, familiar reasoning about functional terms may be unsound if the terms use continuations explicitly or access them implicitly through new operators. We then examine one method of connecting terms with their continuized form, extending the work of Meyer and Wand [8].
Automatic vectorization of character string manipulation and relational operations in Pascal
Authors: T. Tsuda, Y. Kunieda, P. Atipas
Venue: Proceedings of the 1989 ACM/IEEE conference on Supercomputing (1989)

In our paper of Supercomputing '88, an overview of V-Pascal, an automatic vectorizing compiler for Pascal, was presented with focus on its Version 1. In that paper, as one of those higher functions to be added to Version 2 V-Pascal, vector-mode execution of nonnummeric operations such as relational database operations and nonnumeric data manipulations was considered. This paper describes the actual results we have obtained. These results are important in that a new vista has been opened up for vector supercomputers which are originally designed solely for high-speed manipulations of scientific numerical data. More concretely, the compiler V-Pascal has acquired the ability to automatically vectorize Pascal programs that compare/assign massive data of character strings and those programs which prescribe time-consuming relational operations such as 'join' and others for relational database manipulation. Timing results demonstrate that these nonnumeric operations are performed in the regime of vector performance.
Biological versus computer viruses
Authors: D. Guinier
Venue: ACM SIGSAC Review (1989)

To understand biological viruses, some notions of the fundamental knowledge of the structure of DNA, the genetic code, the biosynthesis of proteins, the transcription, replication and transfer processes,... are presented so as to give an idea as to how the genetic information is decrypted by biological mechanisms and consequently, how viruses work.A computer "virus" can be defined as a piece of code with a self-reproducing mechanism riding on other programs which cannot exist by itself. In contrast, a worm can exist independently. A computer "virus" can be considered as another category of computer user, the problem of protection against such a "virus" can be reduced to the problem of protection against users.The choice of the term Self-Reproducing Program (SRP) appears to be unambiguous in comparison to the word "virus". After having created the computer in 1948, John Von Neumann said in 1949 that it must be possible to imagine logical or mechanical engines that would be able to be self-reproducing. We propose that "good" SRP's should be useful for the automatic maintenance of software, by infection of old versions by the most recent version in the form of such an SRP.Protection is possible by a better understanding of computer systems and their mechanisms of exchange of data and processes. Such a study is presented for the DOS which should be protected by a watchdog system and suggests the need for a real-time analysis on the most vulnerable points. Security models including Cryptography should offer preventive solutions and "vaccines", the treatment of minor troubles...while prevention requires a better understanding of men and their ambiguities.The idea that there is a need for a better knowledge of SRP's, Worms, Trojan horses...justifies a call for the constitution of a special database concerning them.
Use of change coordination in an information-rich design environment
Authors: M. Winslett, D. Knapp, K. Hall, G. Wiederhold
Venue: Proceedings of the 26th ACM/IEEE Design Automation Conference (1989)

The growing complexity of VLSI designs has led to a partitioning of design responsibilities among different engineers, with the result that engineers work in parallel on different aspects of the design. With this division of responsibilities comes the need for automatic means of coordinating changes made by different engineers, and automatic means of administrating design policies laid down by management. In this paper we show how an information-rich design environment, incorporating (1) detailed knowledge of the design, (2) explicit representation of management's policies, and (3) special software units called change coordinators, can be used to automate the functions of change coordination and policy administration.
Sequential Fault Occurrence and Reconfiguration in System Level Diagnosis
Authors: Arun K. Somani
Venue: IEEE Transactions on Computers (1990)

In a classical system-level diagnosis model, a complex multiprocessor system is characterized to be uniquely diagnosable under the presence of any arbitrary fault set of size up to t. Fault occurrence, however, is usually a sequential process in real-life systems, i.e. multiple faults occur one after another. Any faulty location is immediately diagnosed and the system is reconfigured before any further fault occurs. Systems which are designed under the assumption of sequential fault occurrences and reconfiguration are discussed and their test interconnection assignment for unique diagnosability is characterized. A theorem is developed for sequential k/t-diagnosability, where the system is allowed to have up to t faults but not more than k of them occur at a time. For most practical cases, k has a value of 1. The t-diagnosability theorem is then a special case of this theorem for k=Kt. The results of this theorem are more useful in the design practical systems where the system is reconfigured after every fault is detected and located, and they do not have to satisfy the constraints n
DAME: a rule based designer of microprocessor based systems
Authors: N. J. Dimopoulos, K. F. Li, E. G. Manning
Venue: Proceedings of the 2nd international conference on Industrial and engineering applications of artificial intelligence and expert systems - Volume 1 (1989)

In this work, we present the overall structure of DAME, which is an expert system capable of configuring and designing customized microprocessor based systems from original specifications.DAME [3, 4], is organized as a hierarchy of design levels, each one of which refines the design provided by the previous level, by following established practices in the field of hardware design.In this work, we shall present the general structure of DAME as well as our approach in modelling the behavior of the various signals associated with the components used for the design of microprocessor based systems.
Extracting schematic-like information from CMOS circuit net-lists
Authors: W.-J. Lue, L. P. McNamee
Venue: Proceedings of the 26th ACM/IEEE Design Automation Conference (1989)

A global circuit structure is established from the circuit net-list based on knowledge about CMOS circuits. This approach first partitions the circuit network and then assigns signal flow directions accordingly. The information obtained is absent in the net-list but explicitly present in schematic diagrams. Such interpretation of a circuit network can provide extra heuristics to assist in various CMOS circuit design tasks.
The Cutplane: a tool for interactive solid modeling
Authors: Laurence Edwards, William Kessler, Larry Leifer
Venue: ACM SIGCHI Bulletin (1988)

Today, most solid modeling systems are used only in the final stages of design, where iterations are driven by analysis rather than creative exploration of alternative solutions. These systems have complex interfaces, slow response, and do not provide a convenient way of specifying a three dimensional position using a two dimensional display screen. As such they are not viable alternatives to visualization methods traditionally used in early design.This paper presents a geometric modeling system which incorporates a new concept for intuitively and unambiguously specifying and manipulating points or features in three dimensional space. The central concept, the Cutplane, consists of a plane that moves through space under control of a mouse or similar input device. The intersection of the plane and any object is highlighted, and only this highlighted section can be selected for manipulation. Selection is accomplished with a crosshair that is constrained to remain within the plane, so that the relationship between the crosshair and the feature of interest is immediately evident. Although the idea of a section view is not new, previously it has been used as a way to reveal hidden structure, not as a means of manipulating objects or indicating spatial position, as is proposed here.
C2MP: a cache-coherent, distributed memory multiprocessor-system
Authors: D. E. Marquardt, H. S. Alkhatib
Venue: Proceedings of the 1989 ACM/IEEE conference on Supercomputing (1989)

Current research into the problems of cache coherency in multiprocessor (MP) systems, has primarily focused on bus based memory interconnection networks (M-ICN) and the use of various types of &ldquo;snooping&rdquo; cache coherency protocols. Bus bandwidth limitations can be alleviated through the use of wider bandwidth general interconnection structures, such as a crossbar switch. However, if private caches are used, the cache coherency problem becomes multiply compounded. Little work has been done to address this problem. A new distributed shared-memory multiprocessor system with private caches and for use with general memory interconnection networks (M-ICNs) is presented. A new distributed cache coherency-controller ($-K) unit is employed to manage coherency invalidation/updating over a dedicated bus based coherency interconnection network (C-ICN). This allows for cache-to-cache coherency updating to reduce the M-ICN traffic to only that of instruction/data transactions. This architecture incorporates a unique hierarchical, preemptive cache coherency protocol, simple enough to be implemented in hardware. A feasible implementation of a fully asynchronous crossbar switch is also presented as a possible general memory interconnection network (M-ICN).
PARLOG and its Applications
Authors: K. L. Clark
Venue: IEEE Transactions on Software Engineering (1988)

The key concepts of the parallel logic programming language PARLOG are introduced by comparing the language with Prolog. Some familiarity with Prolog and with the concepts of logic programming is assumed. Two major application areas of PARLOG, systems programming and object-oriented programming, are illustrated. Other applications are briefly surveyed.
ECCS and LIPS: two languages for OSI systems specification and verification
Authors: V. Carchiolo, A. Di Stefano, A. Faro, G. Pappalardo
Venue: ACM Transactions on Programming Languages and Systems (TOPLAS) (1989)

An issue of current interest in the Open Systems Interconnection (OSI) field is the choice of a language well suited to specification and verification. For this purpose, two languages based on Milner's communication calculi are proposed, respectively intended for the specification of asynchronous and synchronous OSI systems. A formal verification method, relying upon the algebraic foundations of the two languages, is introduced and illustrated by means of examples based on nontrivial protocols and services.
The Wisconsin multicube: a new large-scale cache-coherent multiprocessor
Authors: J. R. Goodman, P. J. Woest
Venue: ACM SIGARCH Computer Architecture News (1988)

The Wisconsin Multicube, is a large-scale, shared-memory multiprocessor architecture that employs a snooping cache protocol over a grid of buses. Each processor has a conventional (SRAM) cache optimized to minimize memory latency and a large (DRAM) snooping cache optimized to reduce bus traffic and to maintain consistency. The large snooping cache should guarantee that nearly all the traffic on the buses will be generated by I/O and accesses to shared data. The programmer's view of the system is like a multi -- a set of processors having access to a common shared memory with no notion of geographical locality. Thus writing software, including the operating system, should be a straightforward extension of those techniques being developed for multis. The interconnection topology allows for a cache-coherent protocol for which most bus requests can be satisfied with no more than twice the number of bus operations required of a single-bus multi. The total symmetry guarantees that there are no topology-induced bottlenecks. The total bus bandwidth grows in proportion to the product of the number of processors and the average path length. The proposed architecture is an example of a new class of interconnection topologies -- the Multicube -- which consists of N =nk processors, where each processor is connected to k buses and each bus is connected to n processors. The hypercube is a special case where n=2. The Wisconsin Multicube is a two-dimensional Multicube (k=2), where n scales to about 32, resulting in a proposed system of over 1,000 processors.