ppxscal/embedding_network huggingface dataset:
Providing Automated Support for the GQM Measurement Process
Authors: Luigi Lavazza
Venue: IEEE Software (2000)

Measurement is a key factor for managing and improving software development. This article illustrates the automation of the most expensive phases of a Goal Question Metrics measurement process. In particular, the author describes a tool for the definition, collection, analysis, and feedback of measures, and the techniques to interface this tool with a configuration management system and metrics tools. These techniques have been employed in a measurement program carried out in an industrial setting.
Advanced Fault Collapsing (Logic Circuits Testing)
Authors: Antonio Lloy
Venue: IEEE Design Test (1992)

The partitioning of faults into equivalence classes so that only one representative fault per class must be explicitly considered in fault simulation and test generation, called fault collapsing, is addressed. Two types of equivalence, which are relevant to the work reported, are summarized. New theorems on fault equivalence and dominance, forming the basis of an algorithm that collapses all the structurally equivalent faults in a circuit, plus many of the functionally equivalent faults, are presented. Application of the algorithm to a set of benchmark circuits establishes that identification of functionally equivalent faults is feasible, and that, in some cases, they are a large fraction of the faults in a circuit. The collapsing algorithm applies not only to combinational designs but to synchronous sequential circuits as well.
An Integrated Framework for the Design and Optimization of SOC Test Solutions
Authors: Erik Larsson, Zebo Peng
Venue: Journal of Electronic Testing: Theory and Applications (2002)

We propose an integrated framework for the design of SOC test solutions, which includes a set of algorithms for early design space exploration as well as extensive optimization for the final solution. The framework deals with test scheduling, test access mechanism design, test sets selection, and test resource placement. Our approach minimizes the test application time and the cost of the test access mechanism while considering constraints on tests and power consumption. The main feature of our approach is that it provides an integrated design environment to treat several different tasks at the same time, which were traditionally dealt with as separate problems. We have made an implementation of the proposed heuristic used for the early design space exploration and an implementation based on Simulated Annealing for the extensive optimization. Experiments on several benchmarks and industrial designs show the usefulness and efficiency of our approach.
Scanning probe microscope analysis of microstructures in optically variable devices
Authors: Patrick W. Leech, Brett A. Sexton, Russell J. Marnock
Venue: Microelectronic Engineering (2002)

The fine-scale features of optically variable devices (OVDs) fabricated in resist by electron beam lithography have been examined using scanning probe microscopy (SPM). These features have included patterns of gratings, micro-text and geometrical images. Scanning probe microscopy has provided information on the groove angle, depth of profile and spatial frequency of the features as determined by the details of processing of the image. The OVD patterns formed in EBR-9 and X-AR-P 7400 resists exhibited a more rounded profile with a lower side-wall angle than in ZEP-7000 and PMMA resists.
Improving Subjective Estimates Using Paired Comparisons
Authors: Eduardo Miranda
Venue: IEEE Software (2001)

Despite the existence of structured methods for software sizing and effort estimation, the so-called "expert" approach seems to be the prevalent way to produce estimates in the software industry. The paired-comparisons method offers a more accurate and precise alternative to "guesstimating."
On Wafer-Packing Problems
Authors: D. H. C. Du, Ichiang Lin, K. C. Chang
Venue: IEEE Transactions on Computers (1993)

Wafer packing is a process of combining multiple chip designs on the same wafer such that the fabrication cost can be shared by several designs and hence reduced. This technique is widely used for designs that require a small number of dies or chips. It is essential to have computer algorithms to decide how to allocate designs to wafers in order to reduce the total fabrication cost. Based on different wafer fabrication techniques, two versions of the wafer packing problem are formulated. The authors study different variations for each version. They present algorithms to find optimal solutions for these variations which are polynomial-time solvable. They also present heuristic algorithms for those proven to be NP-hard. The effectiveness of the proposed algorithms is demonstrated by experimental results.
Development of an ASIC Set for Signal Processing
Authors: Parimal A. Patel, Hemal N. Kothari, James F. Robb
Venue: IEEE Micro (1992)

An approach to signal acquisition, digitization, and processing of low-frequency physiological signals is discussed. The approach uses a chip attached to a transducer through a digital wire placed at the sensing point. The wire transmits digital information instead of an analog signal to an application-specific integrated circuit (ASIC) signal processor. This digital wire/Visp chip set produces a noise-immune signal processing system usable in a variety of biosignal processing needs. The concept is demonstrated using the Visually Evoked Potential (VEP) measurement system.
The combined gated-exhaustive vacation system in discrete time
Authors: Dieter Fiems, Stijn De Vuyst, Herwig Bruneel
Venue: Performance Evaluation (2002)

We consider a discrete-time gated vacation system. The available buffer space is divided into two subsequent queues separated by a gate and new customers arrive either before or after this gate. Whenever all customers after the gate are served, the server takes a vacation. After each vacation, the gate opens which causes all waiting customers to move to the buffer space after the gate. The model under investigation allows to capture performance of a.o. the exhaustive and the gated queueing systems with multiple or single vacations. Using a probability generating functions approach, we obtain expressions for performance measures such as moments of system contents at various epochs in equilibrium and of customer delay. We conclude with a numerical example.
Response Time Analysis of Parallel Computer and Storage Systems
Authors: Elizabeth Varki
Venue: IEEE Transactions on Parallel and Distributed Systems (2001)

Fork-join structures have gained increased importance in recent years as a means of modeling parallelism in computer and storage systems. The basic fork-join model is one in which a job arriving at a parallel system splits into K independent tasks that are assigned to K unique, homogeneous servers. In this paper, a simple response time approximation is derived for parallel systems with exponential service time distributions. The approximation holds for networks modeling several devices, both parallel and nonparallel. (In the case of closed networks containing a stand-alone parallel system, a mean response time bound is derived.) In addition, the response time approximation is extended to cover the more realistic case wherein a job splits into an arbitrary number of tasks upon arrival at a parallel system. Simulation results for closed networks with stand-alone parallel subsystems and exponential service time distributions indicate that the response time approximation is, on average, within 3 percent of the seeded response times. Similarly, simulation results with nonexponential distributions also indicate that the response time approximation is close to the seeded values. Potential applications of our results include the modeling of data placement in disk arrays and the execution of parallel programs in multiprocessor and distributed systems.
Effects of a Ta interlayer on the Titanium Silicide reaction: C40 Formation and scalability of the TiSi2 process
Authors: F. La Via, S. Privitera, F. Mammoliti, M. G. Grimaldi
Venue: Microelectronic Engineering (2002)

When a Ta layer is deposited at the Si-Ti interface a new phase has been detected, i.e., the TiSi2 C40. The C40-C54 transformation kinetics and the film morphology are consistent with an increase of the nucleation density with respect to the C49-C54 transition. The activation energies for the nucleation rate (4.2±0.3 eV) and the growth velocity (4.0±0.4 eV) have been obtained from the in situ sheet resistance and the transmission electron microscopy results. These results show that the process with a Ta layer at the Ti-Si interface has a greater scalability with respect to the standard TiSi2 process.
Fuzzy linear transformations on vector spaces and fuzzy vector spaces
Authors: W.B. Vasantha Kandasamy
Venue: Octogon Mathematical Magazine (2002)

In this paper we introduce the new concept of fuzzy linear transformation of vector spaces and fuzzy vector spaces; study them and obtain some interesting results about them. For vector spaces in general refer [1].
Memory Management for User-Level Network Interfaces
Authors: Matt Welsh, Anindya Basu, Xun Wilson Huang, Thorsten von Eicken
Venue: IEEE Micro (1998)

With user-level network interfaces applications can access the network directly without operating system intervention on every send and receive. Messages are transferred to and from user-space by the network interface while observing the traditional protection boundaries between processes. First generation user-level network interfaces limit this message transfer to a per-process region of permanently-pinned physical memory to allow safe DMA. This approach is inflexible and does not scale to a large number of processes. A new memory management extension to the U-Net user-level network architecture allows messages to be transferred directly to and from any part of an application's address space. This is achieved by integrating a translation look-aside buffer into the network interface and coordinating its operation with the operating system's virtual memory subsystem. Two implementations demonstrate that existing commodity hardware and commercial operating systems can efficiently support the architecture.
Part-Whole Relationship Categories and Their Application in Object-Oriented Analysis
Authors: Renate Motschnig-Pitrik, Jens Kaasbøll
Venue: IEEE Transactions on Knowledge and Data Engineering (1999)

Part decomposition and, conversely, the construction of composite objects out of individual parts have long been recognized as ubiquitous and essential mechanisms involving abstraction. This applies, in particular, in areas such as CAD, manufacturing, software development, and computer graphics. Although the part-of relationship is distinguished in object-oriented modeling techniques, it ranks far behind the concept of generalization/specialization and a rigorous definition of its semantics is still missing. In this paper, we first show in which ways a shift in emphasis on the part-of relationship leads to analysis and design models that are easier to understand and to maintain. We then investigate the properties of part-of relationships in order to define their semantics. This is achieved by means of a categorization of part-of relationships and by associating semantic constraints with individual categories. We further suggest a precise and, compared with existing techniques, less redundant specification of constraints accompanying part-of categories based on the degree of exclusiveness and dependence of parts on composite objects. Although the approach appears generally applicable, the object-oriented Unified Modeling Language (UML) is used to present our findings. Several examples demonstrate the applicability of the categories introduced.
1-D Direct phase retrieval
Authors: Adrian Burian, Pauli Kuosmanen, Corneliu Rusu
Venue: Signal Processing (2002)

The problem of reconstructing a one-dimensional signal from only the magnitude of its Fourier transform is known as the phase retrieval problem. This problem emerges when the phase of a signal is apparently lost or impractical to measure. In this paper, we introduce new solutions that compute the phase by directly using the magnitudes of the samples in nepers. These solutions use relationships between the phase and the gain differences, or gain samples. From the obtained minimum phase solution, the non-minimum phase solutions are derived. The advantages consist in simplicity and stability. We compare our solutions by using some numerical examples. The performances under noisy conditions for the two approaches are also considered.
Combining Belief Networks and Neural Networks for Scene Segmentation
Authors: X. Feng, C. K. I. Williams, S. N. Felderhof
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (2002)

We are concerned with the problem of image segmentation, in which each pixel is assigned to one of a predefined finite number of labels. In Bayesian image analysis, this requires fusing together local predictions for the class labels with a prior model of label images. Following the work of, we consider the use of tree-structured belief networks (TSBNs) as prior models. The parameters in the TSBN are trained using a maximum-likelihood objective function with the EM algorithm and the resulting model is evaluated by calculating how efficiently it codes label images. A number of authors have used Gaussian mixture models to connect the label field to the image data. In this paper, we compare this approach to the scaled-likelihood method of where local predictions of pixel classification from neural networks are fused with the TSBN prior. Our results show a higher performance is obtained with the neural networks. We evaluate the classification results obtained and emphasize not only the maximum a posteriori segmentation, but also the uncertainty, as evidenced e.g., by the pixelwise posterior marginal entropies. We also investigate the use of conditional maximum-likelihood training for the TSBN and find that this gives rise to improved classification performance over the ML-trained TSBN.
CPS Translations and Applications: The Cube and Beyond
Authors: Gilles Barthe, John Hatcliff, Morten Heine B. Sørensen
Venue: Higher-Order and Symbolic Computation (1999)

Continuation passing style (CPS) translations of typed &lambda;-calculi have numerous applications. However, the range of these applications has been confined by the fact that CPS translations are known for non-dependent type systems only, thus excluding well-known systems like the calculus of constructions (CC) and the logical frameworks (LF). This paper presents techniques for CPS translating systems with dependent types, with an emphasis on pure type-theoretical applications.In the first part of the paper we review several lines of work in which the need for CPS translations of dependent type systems has arisen, and discuss the difficulties involved with CPS translating such systems. One way of overcoming these difficulties is to work with so-called domain-free type systems. Thus, instead of Barendregt&lsquo;s &lambda;-cube we shall consider the domain-free &lambda;-cube, and instead of traditional pure type systems, we shall consider domain-free pure type systems.We therefore begin the second part by reviewing the domain-free &lambda;-cube, which includes domain-free versions of CC and LF, and then present CPS translations for all the systems of the domain-free &lambda;-cube. We also introduce Direct Style (DS) (i.e., inverse CPS) translations for all the systems of the domain-free &lambda;-cube; such DS translations, which have been used in a number of applications, were previously formulated for untyped and simply-typed languages only.In the third part we review domain-free pure type systems and generalize the CPS translations of the domain-free &lambda;-cube to a large class of domain-free pure type systems which includes most of the systems that appear in the literature, including those of the domain-free &lambda;-cube. Many translations that appear in the literature arise as special cases of ours.In the fourth part of the paper we present two approaches to CPS translations of traditional pure type systems. The first, indirect, technique lifts the CPS translation of domain-free pure type systems to the analogous class of traditional pure type systems by using results that relate derivations in domain-free and traditional pure type systems. The second, direct, approach translates derivations, requiring a certain order on derivations to be well-founded. Both techniques yield translations for most of the systems that appear in the literature, including those of Barendregt&lsquo;s &lambda;-cube.
Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors
Authors: David M. Brooks, Pradip Bose, Stanley E. Schuster, Hans Jacobson, Prabhakar N. Kudva, Alper Buyuktosunoglu, John-David Wellman, Victor Zyuban, Manish Gupta, Peter W. Cook
Venue: IEEE Micro (2000)

Power dissipation limits have emerged as a major constraint in the design of microprocessors. This is true not only at the low end, where cost and battery life are the primary drivers, but also now at the midrange and high-end system (server) level. Thus, the ability to estimate power consumption at the high level, during the early-stage definition and trade-off studies is a key new methodology enhancement sought by design and performance architects. We first review the fundamentals in terms of power estimation and power-performance trade-offs at the microarchitecture level. We then discuss the opportunities of saving power that can be exposed via microarchitecture-level modeling. In particular, the potential savings that can be effected through straightforward clock-gating techniques is cited as an example. We also describe some future ideas and trends in power-efficient processor design. Examples of how microarchitectural observations can be used toward power-saving circuit design optimizations are described. The design and modeling challenges are in the context of work in progress within IBM Research. This research is in support of future, high-end processor development within IBM.
Automatic Text Categorization and Its Application to Text Retrieval
Authors: Wai Lam, Miguel Ruiz, Padmini Srinivasan
Venue: IEEE Transactions on Knowledge and Data Engineering (1999)

We develop an automatic text categorization approach and investigate its application to text retrieval. The categorization approach is derived from a combination of a learning paradigm known as instance-based learning and an advanced document retrieval technique known as retrieval feedback. We demonstrate the effectiveness of our categorization approach using two real-world document collections from the MEDLINE database. Next, we investigate the application of automatic categorization to text retrieval. Our experiments clearly indicate that automatic categorization improves the retrieval performance compared with no categorization. We also demonstrate that the retrieval performance using automatic categorization achieves the same retrieval quality as the performance using manual categorization. Furthermore, detailed analysis of the retrieval performance on each individual test query is provided.
Remote Device Command and Resource Sharing over the Internet: A New Approach Based on a Distributed Layered Architecture
Authors: Francisco José Monaco, Adilson Gonzaga
Venue: IEEE Transactions on Computers (2002)

In addition to the remote access and computer-augmented functionality brought about by the earliest modalities of distance operation, technical advances in the form of telematics have opened up a whole new range of applications, one of which, resource sharing, deserves special attention. Nonetheless, while distance operations through computer networks, and particularly over the Internet, have attracted a great deal of attention in recent years, there is still a noticeable lack of important acquisitions regarding the systemic treatment of essential issues in this field. This paper presents an overview of the current trends in this emerging interdisciplinary area and briefly comments on the fundaments of telematics-supported distance operation. A case study is used to report on an experience involving methodological investigations in this area.
Estimating Size and Effort in Fourth-Generation Development
Authors: June Verner, Graham Tate
Venue: IEEE Software (1988)

The authors report on the building of an information system for a correspondence school with both many students and many types of students, for which they recommended a fourth-generation-language approach. Because they were sceptical about the massive productivity gains claimed for fourth-generation-language development, and because they did not know exactly where the savings would be, they collected data on the effort expended in the various states of system development. The school needed early schedule and effort estimates to make adequate staff assignments. The authors describe the development approach, discuss the estimation methods used, and present and analyze the results.
Experimental Models for Validating Technology
Authors: Marvin V. Zelkowitz, Dolores R. Wallace
Venue: Computer (1998)

Experimentation helps determine the effectiveness of proposed theories and methods. But computer science has not developed a concise taxonomy of methods that could be used to demonstrate the validity of new software development techniques. Partly as a result of this, the state of experimentation in software engineering is poor. In this article, the authors describe the four general approaches to experimentation and the important aspects of data collection. They propose a taxonomy for software engineering experimentation that describes 12 different experimental approaches. To underscore the need for experimentation, the authors also analyze 612 papers in software engineering published in 1985, 1990, and 1995. They classified each paper according to the data collection method used to validate the claims in the paper. They found that about a third of the papers had no experimental validation, and many authors used sloppy terminology to describe their validation method. The software engineering community, the authors conclude, can do a better job reporting its results. This, in turn, will help industry select the right new technology to implement.
Input Feature Selection by Mutual Information Based on Parzen Window
Authors: Nojun Kwak, Chong-Ho Choi
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (2002)

Mutual information is a good indicator of relevance between variables, and have been used as a measure in several feature selection algorithms. However, calculating the mutual information is difficult, and the performance of a feature selection algorithm depends on the accuracy of the mutual information. In this paper, we propose a new method of calculating mutual information between input and class variables based on the Parzen window, and we apply this to a feature selection algorithm for classification problems.
Bounding Signal Probabilities for Testability Measurement Using Conditional Syndromes
Authors: R. Kapur, M. R. Mercer
Venue: IEEE Transactions on Computers (1992)

An algorithm for bounding the random pattern testability of individual faults in a circuit is proposed. Auxiliary gates for bounding the testability are constructed, converting the problem into one of determining the signal probability at the output of the auxiliary gate. The results presented are in terms of lower bounds of the testabilities of faults. The bounds generated by the algorithm can be used by designers to identify pseudorandom pattern resistant faults, to enable them to modify the circuit structure to make the faults easy to detect, and, hence, to increase the fault coverage.