ppxscal/embedding_network huggingface dataset:
Electroless Co(Mo,P) films for Cu interconnect application
Authors: Y. Shacham-Diamand, A. Zylberman, N. Petrov, Y. Sverdlov
Venue: Microelectronic Engineering (2002)

Thin cobalt-molybdenum-phosphorous, Co(Mo,P), films, prepared by electroless deposition, have been studied for barrier and capping layers for copper metallization for ULSI applications. The solutions and the deposition conditions for the preparation of Co(Mo,P) on various seed layers are presented. The material properties of Cu layers with Co(Mo,P) barrier and capping layers, annealed at temperatures up to 350°C, were studied by Auger electron spectroscopy (AES) and X-ray photo-emission spectroscopy (XPS). Measuring the resistance of the samples versus time allowed us to study the kinetics of the thin film oxidation. Composition profiling showed that if there is copper diffusion onto either the top capping layer or the bottom barrier layer, it was below the AES system detection level (∼0.1%). We conclude that the novel Co(Mo,P) can be used as a barrier against copper diffusion and as an oxidation protection layer.
A Test-Pattern-Generation Algorithm for Sequential Circuits
Authors: Elisabeth Auth, Michael H. Schulz
Venue: IEEE Design Test (1991)

A deterministic test-pattern-generation algorithm for synchronous sequential circuits is presented. The algorithm, called Essential, takes advantage of a procedure for learning global implications. It uses static and dynamic dominance relationships among signals, the concept of the potential propagation path, and intelligent heuristics to guide and accelerate the decision-making process for deterministic automatic test pattern generation (ATPG). Essential is based on the well-known method of reverse time processing, but it applies forward processing within time frames to avoid disadvantageous a priori determination of a path to be sensitized or of a primary output to which the fault effects must be propagated. It is designed to exploit fully the sophisticated techniques used for combinational circuits in the Socrates ATPG system. Experimental results for sequential ATPG obtained with Essential (implemented in C on a Sequent Symmetry computer) are reported.
Content-Based Indexing of Multimedia Databases
Authors: Jian-Kang Wu
Venue: IEEE Transactions on Knowledge and Data Engineering (1997)

Content-based retrieval of multimedia database calls for content-based indexing techniques. Different from conventional databases, where data items are represented by a set of attributes of elementary data types, multimedia objects in multimedia databases are represented by a collection of features; similarity of object contents depends on context and frame of reference; and features of objects are characterized by multimodal feature measures. These lead to great challenges for content-based indexing. On the other hand, there are special requirements on content-based indexing: To support visual browsing, similarity retrieval, and fuzzy retrieval, nodes of the index should represent certain meaningful categories. That is to say that certain semantics must be added when performing indexing. ContIndex, the context-based indexing technique presented in this paper, is proposed to meet these challenges and special requirements. The indexing tree is formally defined by adapting a classification-tree concept. Horizontal links among nodes in the same level enhance the flexibility of the index. A special neural-network model, called Learning based on Experiences and Perspectives (LEP), has been developed to create node categories by fusing multimodal feature measures. It brings into the index the capability of self-organizing nodes with respect to certain context and frames of reference. An icon image is generated for each intermediate node to facilitate visual browsing. Algorithms have been developed to support multimedia object archival and retrieval using ContIndex. ContIndex has been successfully applied to two applications: A facial image retrieval system, CAFIIR, and a trademark archival and registration system, STAR.
Arithmetic Unit Design for Neural Accelerators: Cost Performance Issues
Authors: S. r. Jones, K. m. Sammut
Venue: IEEE Transactions on Computers (1995)

Arithmetic unit design is a key issue when supporting the computational requirements of neural networks. However, there is little quantitative evidence from the study of existing neural accelerators to help choose between arithmetic constructs. This paper presents an assessment of the cost-performance trade-offs between arithmetic constructs for linear neural accelerators.
A conjecture of Berge about linear hypergraphs and Steiner systemsS (2,4,v)
Authors: Lucia Gionfriddo
Venue: Discrete Mathematics (2002)

A famous conjecture of Berge about linear hypergraphs is studied. It is proved that all nearly resolvable Steiner systems S(2, 4, υ) and all almost nearly resolvable S(2, 4, υ) verify this conjecture.
A Fuzzy Reasoning Database Question Answering System
Authors: S. Vassiliadis, G. Triantafyllos, W. Kobrosly
Venue: IEEE Transactions on Knowledge and Data Engineering (1994)

Describes a question-answering system based on fuzzy logic. The proposed system provides the capability to assess whether a database contains information pertinent to a subject of interest by evaluating each comment in the database via a fuzzy evaluator that attributes a fuzzy membership value indicating its relationship to the subject. An assessment is provided for the database as a whole regarding its pertinence to the subject of interest, and consequently comments that are considered irrelevant to the subject may be discarded. The system has been developed for the examination of databases that were created during the development of the IBM 4381 computer systems, for bookkeeping purposes, to assess whether such databases contain information pertinent to the functional changes that occurred during the development cycle. The system, however, can be applied with minimal changes to a variety of circumstances, provided that the fundamental assumptions for the development of the membership functions are respected in the new application. Its applicability, without modifications, assuming the same subject of interest, is granted for databases comprising similar characteristics to that of the original database for which the system has been developed.
A Programmable BIST Core for Embedded DRAM
Authors: Chih-Tsun Huang, Jing-Reng Huang, Chi-Feng Wu, Cheng-Wen Wu, Tsin-Yuan Chang
Venue: IEEE Design Test (1999)

With the advent of deep-submicron VLSI technology, ASIC vendors are turning toward the single-chip system solution which integrates cores from various sources. Memory is one of the most universal cores-almost all system chips contain some type of embedded memory. Embedded SRAM's have been widely used, since by merging memory with logic, data bandwidth can be increased and hardware cost can be reduced. Now, with multimillion-gate designs that are pad-limited, we can see why embedded DRAM is also becoming an attractive core to them. With the clear trend that embedded DRAM will play an important role in the IC market over the next few years, their testing is becoming an industry-wide concern. Built-in self-test (BIST) is widely considered to be the best way for functional testing of embedded DRAM's. In this paper, we propose a programmable embedded DRAM BIST scheme which supports various test modes using a simple controller. An EDO DRAM is used as an example to delineate our BIST design and implementation. A novel memory fault simulator also has been implemented and used to analyze the fault coverage of the test algorithms for our BIST design. Our analysis shows that, with the March C- algorithm, the BIST overhead is less than 1.3% for a 1Mb DRAM, and it drops to below 0.3% for a 16Mb DRAM. Also, since the proposed BIST design is programmable, it can easily be applied to other DRAM types.
Discovery of the Maximum Principle
Authors: R. V. Gamkrelidze
Venue: Journal of Dynamical and Control Systems (1999)

A short history of the discovery of the maximum principle in optimal control theory by L. S. Pontryagin and his associates is presented.
Programming a Hypercube Multicomputer
Authors: Sanjay Ranka, Youngju Won, Sartaj Sahni
Venue: IEEE Software (1988)

The issues encountered by programmers are explored. A brief overview of parallel architectures is followed by an example problem of image-template matching. The programming consideration for this problem are discussed.
MDARTS: A Multiprocessor Database Architecture for Hard Real-Time Systems
Authors: Victor B. Lortz, Kang G. Shin, Jinho Kim
Venue: IEEE Transactions on Knowledge and Data Engineering (2000)

Complex real-time systems need databases to support concurrent data access and provide well-defined interfaces between software modules. However, conventional database systems and prior real-time database systems do not provide the performance or predictability needed by high-speed, hard real-time applications. To address this need, we have designed, implemented, and evaluated an object-oriented database system called MDARTS (Multiprocessor Database Architecture for Real-Time Systems). MDARTS avoids the client-server overhead of most prior real-time database systems and object-oriented, real-time systems by moving transaction execution into application tasks. By eliminating these sources of overhead and focusing on basic data management services for control systems (data sharing, serializable transactions, and multiprocessor support), our MDARTS prototype provides hard real-time transaction times approximately three orders of magnitude faster than prior real-time database systems. MDARTS ensures bounded locking delay by disabling preemption when a transaction is waiting for a lock and, hence, allows for the estimation of worst-case transaction execution times. Another contribution of MDARTS is that it supports explicit declarations of real-time requirements and semantic constraints within application code. The MDARTS library examines these declarations at application initialization time and attempts to construct objects that are compatible with the requirements. Besides local shared-memory transactions with hard real-time response time guarantees, MDARTS also supports remote transactions that use remote procedure calls for data access with less stringent timing constraints. Our MDARTS prototype is implemented in C++ and it runs on VME-based multiprocessors and Sun workstations.
Adolescent Girls' Use of the Internet for Health Information: Issues Beyond Access
Authors: Nicola J. Gray, Jonathan D. Klein, Judith A. Cantrill, Peter R. Noyce
Venue: Journal of Medical Systems (2002)

Whilst the &ldquo;digital divide&rdquo; in access to Internet technology has rightly concerned commentators on health inequalities, there are issues beyond physical access that must be tackled if adolescents and adults are to optimize the benefits of this developing medium. Emerging themes from an exploratory qualitative study of adolescents' use of the Internet for information about health and medicines describe four major challenges. Access issues persist if there are insufficient school computers that are unable to cope with increasing Web site sophistication. Software on school-based machines preventing exposure to material that is deemed to be unsuitable may also prohibit access to educational sites about sexual health and drug misuse. Strategies to manage the volume of available information are needed. The interplay of active and passive information seeking challenges whether the Internet can be truly useful during acute illnessepisodes. This exploration with future health service users highlights important questions for further study.
On Harmonic Weight Enumerators of Binary Codes
Authors: Christine Bachoc
Venue: Designs, Codes and Cryptography (1999)

We define some new polynomials associated to a linear binary code and a harmonic function of degree k. The case k=0 is the usual weight enumerator of the code. When divided by (xy)^k, they satisfy a MacWilliams type equality. When applied to certain harmonic functions constructed from Hahn polynomials, they can compute some information on the intersection numbers of the code. As an application, we classify the extremal even formally self-dual codes of length 12.
Performance Simulation of an Alpha Microprocessor
Authors: Matt Reilly, John Edmondson
Venue: Computer (1998)

If there ever was a time when the architecture of a high-performance micro-processor could spring completely formed from the mind of a single engineer, that time has passed. Modern microprocessor architectures are the result of invention and progressive refinement by a team. Producing a finished microprocessor takes the effort of many engineers in many disciplines, but the first step requires that an architecture team sketch out the organization of a chip. The teams that designed Digital's Alpha processors are guided in large part by an executable performance model. In this article, the authors describe the performance model that guides a current Alpha processor design project. The model allows the designers to conduct architectural explorations over a large range of processor organizations. In the process, they arrived at a chip organization that met Digital's design goal of building a better/ faster/cheaper microprocessor.
Logos: A Constraint-Directed Reasoning Shell for Operations Management
Authors: (Alex) Chao-Chiang Meng, Michael Sullivan
Venue: IEEE Expert: Intelligent Systems and Their Applications (1991)

A description is given of the Logos reasoning shell, an expert system that performs reactive scheduling, i.e. reschedules operations in the context of new information. Logos' constraint system supports the use of temporal constraints as well as the need to add and retract constraints incrementally. Logos' problem-solving approach is discussed and constraint-based reasoning and dynamic modeling, both of which are used by Logos, are examined. Some current applications are described.
Fault-Tolerant Wormhole Routing in Meshes without Virtual Channels
Authors: Christopher J. Glass, Lionel M. Ni
Venue: IEEE Transactions on Parallel and Distributed Systems (1996)

Previous methods of making wormhole-routed meshes fault tolerant have been based on adding virtual channels to the networks. This paper proposes an alternative method, one based on the turn model for designing wormhole routing algorithms. The turn model produces routing algorithms that are deadlock free, very adaptive, minimal or nonminimal, and livelock free for direct networks¿whether or not they contain virtual channels. This paper illustrates how to modify the routing algorithms produced by the turn model to handle dynamic faults. The paper first describes how to modify the negative-first routing algorithm, which the turn model produces for n-dimensional meshes without virtual channels, to make it one-fault tolerant. Simulations of the one-fault-tolerant routing algorithm and other minimal and nonminimal routing algorithms in a two-dimensional mesh indicate that misrouting increases communication latencies significantly at high throughputs. The conclusion is that misrouting should be used only for increasing the degree of fault tolerance, never for just increasing adaptiveness. Finally, the paper describes how to modify the negative-first routing algorithm to make it (n¿ 1)-fault tolerant for n-dimensional meshes without virtual channels.
Two Fast and High-Associativity Cache Schemes
Authors: Chenxi Zhang, Xiaodong Zhang, Yong Yan
Venue: IEEE Micro (1997)

A traditional implementation of the set-associative cache has the disadvantage of longer access cycle times than that of a direct-mapped cache. Several methods have been proposed for implementing associativity in non-traditional ways. However, most of them have only achieved an associativity of two. The others with higher associativity still present longer access cycle times or suffer from larger average access times. In this paper, we first systematically address implementation issues of associativity and evaluate existing implementation methods. We then propose two schemes for implementing higher associativity: the Sequential Multi-Column Cache, which is an extension of the Column Associative Cache, and the Parallel Multi-Column Cache. In order to achieve the same access cycle time as that of a direct-mapped cache, data memory in the cache is organized into one bank in both schemes. We use the multiple MRU block technique to increase the first hit ratio, thus reducing the average access time. While the Parallel Multi-Column Cache performs the tag checking in parallel, the Sequential Multi-Column Cache sequentially searches through places in a set, and uses index information to filter out unnecessary probes. In the case of an associativity of 4, they both achieve the low miss rate of a 4-way set-associative cache. Our simulation results using ATUM traces show that both schemes can effectively reduce the average access time. They have average improvements of 9.8% and 10.8% in average access time over a direct-mapped cache, respectively, for a cache size of 4K bytes and a miss penalty of 20 cycles, in which case the average improvement of the Column Associative Cache is only 4.3%. The improvement of the Sequential Multi-Column Cache in average access time reaches 22.4% when the associativity is 8 and the miss penalty increases to 100 cycles. The two schemes are effective for both small and large caches (1K bytes to 128K bytes).
Real-World Design Diversity: A Case Study on Cost
Authors: Karama Kanoun
Venue: IEEE Software (2001)

Developers sometimes use design diversity- producing two or more units, or variants, aimed at delivering the same services through separate designs and realizations-to check the dynamic behavior of their software during execution. Some say it's a waste of resources that might be better spent on the original design. This author describes a case study that analyzed work hours spent on variant design in an industrial development environment over a seven-year period. The results show that the costs did not double by developing a second variant.
An Inherently Parallel Method for Heuristic Problem-Solving: Part I-General Framework
Authors: Ira Pramanick, Jon G. Kuhl
Venue: IEEE Transactions on Parallel and Distributed Systems (1995)

The class of NP-hard problems contains many problems of considerable practical importance. The complexity of these problems is so overwhelming that exhaustive search of the solution space is not possible even using massively parallel search techniques, particularly for problems of super-exponential complexity such as flow-shop and job-shop scheduling. This two-part paper discusses a novel, inherently parallel heuristic solution technique. Part I presents this technique, known as Parallel Dynamic Interaction (PDI), as a general solution framework that is applicable to a number of computationally intractable problems, and gives details of its general methodology.From a parallel processing standpoint, PDI is interesting because it is inherently based upon the dynamic interplay between simultaneously executing subproblems. As such, PDI has no direct serial analog, and is not directly amenable to conventional parallel processing speedup analysis. This may provide an indication that parallel processing can offer opportunities beyond simply speeding up the solution of sequentially specified algorithms. From a practical problem-solving perspective, PDI shows promise as a method capable of generating high quality solutions to exponentially and super-exponentially hard problems. For large problems, PDI is often able to find a near-optimal solution many orders of magnitude faster than the time taken for a conventional parallel branch-and-bound search to find a solution of comparable quality. The successful application of PDI to three NP-hard problems is described in Part II of this paper.
PixelFlex: a reconfigurable multi-projector display system
Authors: Ruigang Yang, David Gotz, Justin Hensley, Herman Towles, Michael S. Brown
Venue: Proceedings of the conference on Visualization '01 (2001)

This paper presents PixelFlex --- a spatially reconfigurable multi-projector display system. The PixelFlex system is composed of ceiling-mounted projectors, each with computer-controlled pan, tilt, zoom and focus; and a camera for closed-loop calibration. Working collectively, these controllable projectors function as a single logical display capable of being easily modified into a variety of spatial formats of differing pixel density, size and shape. New layouts are automatically calibrated within minutes to generate the accurate warping and blending functions needed to produce seamless imagery across planar display surfaces, thus giving the user the flexibility to quickly create, save and restore multiple screen configurations.Overall, PixelFlex provides a new level of automatic reconfigurability and usage, departing from the static, one-size-fits-all design of traditional large format displays. As a front-projection system, PixelFlex can be installed in most environments with space constraints and requires little or no post-installation mechanical maintenance because of the closed-loop calibration.
Visualizing and Analyzing Software Infrastructures
Authors: Adam Buchsbaum, Yih-Farn Chen, Huale Huang, Eleftherios Koutsofios, John Mocenigo, Anne Rogers, Michael Jankowsky, Spiros Mancoridis
Venue: IEEE Software (2001)

Operations in today's large corporations are usually supported by complex software infrastructures that involve hundreds or thousands of software systems.Companies frequently need to redesign their software infrastructures in response to marketplace changes in the. This article describes the Enterprise Navigator, a system that lets architects visualize system interconnections of selected products and services by making database queries on the Web. Moreover, analysis tools are provided for the architects to examine dominating information flows, perform clustering analysis to find substructures, and study the structural evolution of particular business processes or functions. The system has been used extensively on AT&T's System Profile Database. The article also includes a case study to show how an architect can use Enterprise Navigator to perform various visualization and analysis tasks.
Creating Domain Specific Metadata for Scientific Data and Knowledge Bases
Authors: J. Diederich, J. Milton
Venue: IEEE Transactions on Knowledge and Data Engineering (1991)

The authors examine a particular type of domain-based metadata for which a complete ready-made conceptual framework is not and probably cannot be directly supported in predefined data models of knowledge-based representation paradigms. The data or knowledge base designer thus has the burden of sometimes working outside a familiar and otherwise appropriate model. The authors discuss issues arising in formulating certain domain-based metadata extensions and provide guidelines for developing them. These results derive from a continuing effort to create a knowledge base to support research on biological organisms. The added semantics are used to support a more flexible and reliable system for identification.
G-Log: A Graph-Based Query Language
Authors: Jan Paredaens, Peter Peelman, Letizia Tanca
Venue: IEEE Transactions on Knowledge and Data Engineering (1995)

In this paper we introduce G-Log, a declarative query language based on graphs, which combines the expressive power of logic, the modeling power of complex objects with identity and the representation power of graphs. G-Log is a nondeterministic complete query language, and thus allows the expression of a large variety of queries. We compare G-Log to well-known deductive database languages, and find that it is the only nondeterministic and computationally complete language that does not suffer from the copy-elimination problem. G-Log may be used in a totally declarative way, as well as in a ¿more procedural¿ way. Thus, it provides an intuitive, flexible graph-based formalism for nonexpert database users.