ppxscal/embedding_network huggingface dataset:
DMLoader: a Scalable MPI Task Loader on Dawning Supercomputers
Authors: Bibo Tu, Taoying Liu, Dan Meng
Venue: Proceedings of the High Performance Computing and Grid in Asia Pacific Region, Seventh International Conference (2004)

Dawning MPI Loader, a software tool called DMLoader, is used to load DMPI tasks on Dawning Supercomputers (a cluster of SMP nodes). DMPI (Dawning Message Passing Interface) is derived from MPICH, while their difference is that DMPI tasks communicate by BCL (Basic Communication Library) or GM over the Myrinet network, rather than TCP/IP over Ethernet. In this paper, we present the design and implementation of DMLoader software, with emphasis on task management and system scalability issues. The results of performance evaluation are also given.
Some simple advantages of reasoning in intuitionistic neutrosophic logic
Authors: Charles Ashbacher
Venue: Smarandache Notions Journal (2004)

The traditional form of reasoning in logic and automated reasoning is severely limited in that it cannot be used to represent many circumstances. In this paper, we demonstrate two simple examples of the superiority of intuitionistic neutrosophic logic in representing the data of the real world.
Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations
Authors: Aseem Agarwal, David Blaauw, Vladimir Zolotov
Venue: Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design (2003)

Process variations have become a critical issue in performanceverification of high-performance designs. We present a new, statisticaltiming analysis method that accounts for inter- and intra-dieprocess variations and their spatial correlations. Since statisticaltiming analysis has an exponential run time complexity, we proposea method whereby a statistical bound on the probability distributionfunction of the exact circuit delay is computed with linear run time.First, we develop a model for representing inter- and intra-die variationsand their spatial correlations. Using this model, we thenshow how gate delays and arrival times can be represented as a sumof components, such that the correlation information betweenarrival times and gate delays is preserved. We then show howarrival times are propagated and merged in the circuit to obtain anarrival time distribution that is an upper bound on the distributionof the exact circuit delay. We prove the correctness of the bound andalso show how the bound can be improved by propagating multiplearrival times. The proposed algorithms were implemented andtested on a set of benchmark circuits under several process variationscenarios. The results were compared with Monte Carlo simulationand show an accuracy of 3.32% on average over all test cases.
Energy-aware video streaming with QoS control for portable computing devices
Authors: Morihiko Tamai, Tao Sun, Keiichi Yasumoto, Naoki Shibata, Minoru Ito
Venue: Proceedings of the 14th international workshop on Network and operating systems support for digital audio and video (2004)

We propose an energy-aware video streaming system for portable computing devices, in which the video can be played back for the specified duration within the remaining battery amount. To save power, we introduce techniques (i) to reduce playback quality of a video at an intermediate proxy and (ii) to shorten working time of the network I/F card using periodic bulk transfer of the video data on the wireless LAN. To enable playback for the specified duration, we have developed a power consumption model for portable devices using parameters on playback quality, playback duration, battery amount, and so on. We have also developed an algorithm to assign different playback quality among multiple video segments based on the user's preference.within the battery amount. Our experiments using PDAs and laptop PCs on 802.11b WLAN show that our system achieves less than 6 prediction error in playback duration while adapting playback quality among video segments.
A Flexibility Approach to Planning an Intranet in Support of Knowledge Work
Authors: Jan Aidemark
Venue: Proceedings of the Database and Expert Systems Applications, 15th International Workshop (2004)

The aim of the paper is to investigate how a strategic flexibility approach can be used for the planning of information systems as support for knowledge work, i.e. knowledge management systems (KMS). The result of a case study of an intranet project is presented, discussing systems that cover the perspectives of strategic flexibility and illustrating the application of the concept. A concluding discussion argues for this approach to knowledge management as a key activity in balancing change and stability in the organization.
Efficient Byzantine-Tolerant Erasure-Coded Storage
Authors: Garth R. Goodson, Jay J. Wylie, Gregory R. Ganger, Michael K. Reiter
Venue: Proceedings of the 2004 International Conference on Dependable Systems and Networks (2004)

This paper describes a decentralized consistency protocolfor survivable storage that exploits local data versioningwithin each storage-node. Such versioning enables the protocolto efficiently provide linearizability and wait-freedomof read and write operations to erasure-coded data in asynchronousenvironments with Byzantine failures of clientsand servers. By exploiting versioning storage-nodes, theprotocol shifts most work to clients and allows highly optimisticoperation: reads occur in a single round-trip unlessclients observe concurrency or write failures. Measurementsof a storage system prototype using this protocolshow that it scales well with the number of failures tolerated,and its performance compares favorably with an efficientimplementation of Byzantine-tolerant state machine replication.
The Value of a University-based Content Provider: A Case Study of SunnyNet
Authors: Feng-Jyh Lin, Kunhuang Huarng
Venue: Proceedings of the E-Commerce Technology for Dynamic E-Business, IEEE International Conference (2004)

In view of the sheer growth of electronic commerce, users and organizations rushed online to exchange information and conduct commerce. There are full of data, information, and knowledge which can be accessed on the internet. The learning is not restricted to the physical classroom. Students can explore the knowledge from the online data source. As a consequence, many universities have focused on the training of information literacy. This paper introduces a university-based content provider to demonstrate the work of resource-based learning. This is done through a detailed examination of the structure of the organization, the personnel, and the training process. We focus on the concept of designing and maintaining a self-organizing and self-learning student group.
A Variational Complex for Difference Equations
Authors: Peter E. Hydon, Elizabeth L. Mansfield
Venue: Foundations of Computational Mathematics (2004)

An analogue of the Poincar&#x00e9; lemma for exact forms on a lattice is stated and proved. Using this result as a starting-point, a variational complex for difference equations is constructed and is proved to be locally exact. The proof uses homotopy maps, which enable one to calculate Lagrangians for discrete Euler&#x2013;Lagrange systems. Furthermore, such maps lead to a systematic technique for deriving conservation laws of a given system of difference equations (whether or not it is an Euler&#x2013;Lagrange system).
CASSE: A System-Level Modeling and Design-Space Exploration Tool for Multiprocessor Systems-on-Chip
Authors: Victor Reyes, Tomas Bautista, Gustavo Marrero, Pedro P. Carballo, Wido Kruijtzer
Venue: Proceedings of the Digital System Design, EUROMICRO Systems (2004)

As SoC complexity grows new methodologies and tools for system design and time-effective design space exploration are required. In this paper we introduce a tool called CASSE, what stands for CAmellia System-on-chip Simulation Environment. CASSE is a fast, flexible, and modular SystemC-based simulation environment which aims to be useful for design-space exploration and system-level design at different abstraction levels. The tool uses transaction-level modeling techniques for fast simulations and easy architectural modeling, and bridge the gap to system implementation by a progressive refinement approach. CASSE is being used in the European IST-2001-34410 CAMELLIA project, which focuses on the mapping of innovative smart imaging applications onto an existing video encoding architecture.
Debugging "level": step-wise debugging
Authors: Dick Hamlet
Venue: Proceedings of the symposium on High-level debugging (1983)

Debugging techniques originated with low-level programming languages, where the memory dump and interactive word-by-word examination of memory were the primary tools. "High-level" debugging is often no more than low-level techniques adapted to high-level languages. For example, to examine the execution of an operational specification one state at a time by setting breakpoints, is superior to doing the same thing to a machine-language program, but only because the language level has improved; the debugging remains primitive. This paper attempts a radical definition of debugging level, and illustrates it with a technique for ordering the execution of concurrent processes in a way that follows their design structure. Division of a program into a collection of cooperating processes is a means of controlling the complexity of each process. However, in execution the program--development structure is ignored, with the result that the advantages of decomposition are lost. What the designer has divided and conquered, the debugger sees as an overwhelming monolith. The technique proposed here causes the focus of execution to follow the design structure, in a way that does not require detailed user direction.
A new method for fabrication nano-porous aluminum grating array
Authors: Y. Li, Y. Kanamori, K. Hane
Venue: Microsystem Technologies (2004)

The fabrication technique of highly ordered anodic porous alumina membrane by anodization of Al and the obtained membrane as a mask to the fabrication of 100 nm period antireflection grating hole are described. The two-step anodizing process improves the quality of the nanohole because the periodic seeds are generated by the first anodization. Antireflection grating structures are fabricated by using ordered anodic porous alumina mask and etched by SF6 fast atom beam on silicon wafer. The reflectivity of the antireflection grating structures is measured and compared with that of the calculated value and the polished silicon surface.
The application of error-sensitive testing strategies to debugging
Authors: Lori A. Clarke, Debra J. Richardson
Venue: ACM SIGSOFT Software Engineering Notes (1983)

Program errors can be considered from two perspectives -- cause and effect. The goal of program testing is to detect errors by discovering their effects, while the goal of debugging is to search for the associated cause. In this paper, we explore ways in which some of the results of testing research can be applied to the debugging process. In particular, computation testing and domain testing, which are two error-sensitive test data selection strategies, are described. Ways in which these selection strategies can be used as debugging aids are then discussed.
Session Introduction: Wireless Sensor Networks
Authors: Utz Roedig
Venue: Proceedings of the 30th EUROMICRO Conference (2004)

The goal of this special session is to present and discuss current problems on the various communication layers.
Finding and defining the generators of genus-n objects for constructing topological and cut graphs
Authors: D. Steiner, A. Fischer
Venue: The Visual Computer: International Journal of Computer Graphics (2004)

The topology of an object is commonly represented through a topological graph or a cut graph (polygonal scheme). Over the past few years, many studies have focused on extracting the topological and cut graphs of complex freeform objects that are represented by meshes. For an object with genus-n, the topological graph has n cycles, while the cut graph contains 2n cycles. These loops, however, do not always explicitly represent the holes in the objects. That is, a cycle in the graph can be a cycle around a solid (meridian), a cycle around a hole (longitude), or almost any combination of the two. The task of classifying the cycles (generators) as cycles around holes (longitude) and cycles around solids (meridians) on the mesh is not straightforward. Every closed orientable 2-manifold with genus-n can be seen as a collection of n toruses stitched together, so that each hole in the object can be referred to as a torus with two generators. This paper proposes a method that extracts the generators from which the longitudes and the meridians are found. The topological graph is defined by the longitudes and by a spanning tree constructed between them. The cut graph is constructed using the same concept. The advantage of the proposed method over other methods is that each loop in the topological graph explicitly represents a hole in the object.
Using Structured P2P Overlay Networks to Build Content Sensitive Communities
Authors: Paul Stacey, Damon Berry, Eugene Coyle
Venue: Proceedings of the Parallel and Distributed Systems, Tenth International Conference (2004)

This paper details a proposed peer-to-peer system,which allows a user to join communities of other like-mindedusers in order to exchange files. Utilising therouting capabilities of Pastry, the proposed systemincludes an indexing service, which will facilitate thecreation of virtual rendezvous points for users withsimilar interests (manifested by shared keywords). Userswill be described by the content they store. By usingVector Space Modelling techniques users can be groupedtogether to form content sensitive communities. Thesystem is built to serve as the basis for a distributedarchive of research papers.The system is designed to improve the efficiency of filesearches over current p2p file sharing applications.Search requests result in a comprehensive set of relevantdocuments being returned as searching will be based onsemantic meaning rather than literal matching.
Effect and model of gate Oxide breakdown on CMOS inverters
Authors: R. Rodríguez, J. H. Stathis, B. P. Linder
Venue: Microelectronic Engineering (2004)

The effect of oxide breakdown (BD) on the performance of CMOS inverters has been investigated and modeled. The results show that the inverter performance can be affected by the breakdown in a different way depending on the stress polarity applied to the inverter input. In all the cases, the oxide breakdown conduction has been modeled as gate-to-diffusion leakage with a power law formula of the type I = KVp which was previously found to describe the breakdown in capacitor structures. This seems to indicate that the breakdown physics at oxide level is the same as at circuit level.
A Open Model to Define Adaptive Educational Hypermedia Systems Based on Learning Technology Specifications
Authors: Adriana Berlanga, Francisco Garcia
Venue: Proceedings of the Database and Expert Systems Applications, 15th International Workshop (2004)

This paper outlines an ongoing research focus on the definition of an open model to authoring adaptive educational hypermedia systems. The goal is to make it possible to design adaptive environments for any knowledge field, educational level, instructional design or learning style as well as giving the teachers the possibility of creating their own adaptive rules. Moreover, standardized metadata, namely IMS, is used to define the semantic of the elements and guarantee their reusability and interoperability.
Data Mining: How Research Meets Practical Development?
Authors: Xindong Wu, S. Yu, Gregory Piatetsky-Shapiro, Nick Cercone, Y. Lin, Ramamohanarao Kotagiri, W. Wah
Venue: Knowledge and Information Systems (2003)

At the 2001 IEEE International Conference on Data Mining in San Jose, California, on November 29 to December 2, 2001, there was a panel discussion on how data mining research meets practical development. One of the motivations for organizing the panel discussion was to provide useful advice for industrial people to explore their directions in data mining development. Based on the panel discussion, this paper presents the views and arguments from the panel members, the Conference Chair and the Program Committee Co-Chairs. These people as a group have both academic and industrial experiences in different data mining related areas such as databases, machine learning, and neural networks. We will answer questions such as (1) how far data mining is from practical development, (2) how data mining research differs from practical development, and (3) what are the most promising areas in data mining for practical development.
Unified Commerce Server Architecture for Large Number of Enterprise Stores
Authors: Trieu C. Chieu, Florian Pinel, Jih-Shyr Yih
Venue: Proceedings of the IEEE International Conference on E-Commerce Technology (2004)

To serve a large number of enterprise customers, enterprise supplier needs to set up many custom B2B stores, each personalized with special promotions and dedicated contracts. The custom store needs to empower business buyers to shop in the following fashions: 1) Buyers visit the custom store, make direct decisions on product selection, based on entitled pricing, and check out orders; 2) Buyers use their own company's procurement software, perform catalog shopping on one or more remote custom stores, return an order quote locally for approval, and subsequently send approved orders to supplier for fulfillment; 3) Buyers shop with own company's procurement software, using catalog pre-loaded with product and pricing information extracted from supplier's custom stores, and then place purchase orders. This paper describes a practical implementation experience, on how these shopping paradigms can be accommodated effectively and efficiently using a unified commerce server architecture. It is explained, how one master catalog subsystem can be personalized to accommodate B2B Direct catalog shopping, B2B procurement with remote catalog punchout, B2B procurement with local catalog, and entitled catalog extraction. A detailed discussion on how to build the commerce server in a 2-tier architecture is illustrated by the handling of various different punchout protocols in one common implementation. The study also reports on the issues and efficiency considerations by different approaches for real-time entitled pricing lookup vs. batch pricing extraction operation.
Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance
Authors: Rakesh Kumar, Dean M. Tullsen, Parthasarathy Ranganathan, Norman P. Jouppi, Keith I. Farkas
Venue: Proceedings of the 31st annual international symposium on Computer architecture (2004)

A single-ISA heterogeneous multi-core architecture is achip multiprocessor composed of cores of varying size, performance,and complexity. This paper demonstrates that thisarchitecture can provide significantly higher performance inthe same area than a conventional chip multiprocessor. It doesso by matching the various jobs of a diverse workload to thevarious cores. This type of architecture covers a spectrum ofworkloads particularly well, providing high single-thread performancewhen thread parallelism is low, and high throughputwhen thread parallelism is high.This paper examines two such architectures in detail,demonstrating dynamic core assignment policies that providesignificant performance gains over naive assignment, andeven outperform the best static assignment. It examines policiesfor heterogeneous architectures both with and withoutmultithreading cores. One heterogeneous architecture we examineoutperforms the comparable-area homogeneous architectureby up to 63%, and our best core assignment strategyachieves up to 31% speedup over a naive policy.
Rapid design exploration of safety-critical distributed automotive applications via virtual integration platforms
Authors: Paolo Giusto, Thilo Demmeler
Venue: Journal of Systems and Software (2004)

Modern automotive applications such as Drive-by-Wire are implemented over distributed architectures where electronic control units (ECU's) communicate via broadcast buses. In this paper, we present the concept of virtual integration platform for automotive applications. The platform provides the basis for early analysis and validation of distributed applications, therefore enhancing the current model based development process techniques that are applied to one ECU at a time. The virtual prototype includes both functional and performance (time) models of the application software, scheduling policies, and the bus communication protocols. As a result, since design errors can be found earlier in the design process before the different sub-systems are integrated in the car, savings in both production and development costs can be achieved. The virtual integration platform concept is supported by an integrated IP-based tool environment for authoring, integration, and validation. First, a model of the distributed application is built by composing models of HW and SW components. The models can be either authored or imported from different tools. Functional simulation of the overall distributed control algorithm can be carried out first. Then, the mapping phase can take place: subfunctions of the control algorithm are mapped to architectural resources (CPUs), and zero-time communication links between the sub-functions are mapped to bus protocol delay models. Changing mappings, parameters such as task priorities, and bus schedule enables the exploration of alternative implementations. The validation is carried out by simulating the resulted virtual prototype of the distributed control algorithm running on the ECU network. The design environment shortens design turn-around time by supporting (semi)-automatic configuration of the architecture model (e.g. frame packaging, redundancy level, communication matrix, bus and RTOS scheduling, etc.).
CAS-DSM: a compiler assisted software distributed shared memory
Authors: N. P. Manoj, K. V. Manjunath, R. Govindarajan
Venue: International Journal of Parallel Programming (2004)

Traditional software Distributed Shared Memory (DSM) systems rely on the virtual memory management mechanisms to detect accesses to shared memory locations and maintain their consistency. The resulting involvement of the OS (kernel) and the associated overhead which is significant, can be avoided by careful compile time analysis and code instrumentation. In this paper, we propose such a Compiler Assisted Software support approach (CAS-DSM). In the CAS-DSM implementation, the involvement of the OS kernel is avoided by instrumenting the application code at the source level. The overhead caused by the execution of the instrumented code is reduced through several aggressive compile time optimizations. Finally, we also address the issue of reducing certain overheads in polling-based implementation of receiving asynchronous messages. We used SUIF, a public domain compiler tool, to implement compile time analysis, instrumentation and optimizations. We modified CVM, a publicly available software DSM to support the instrumentation inserted by the compiler. Detailed performance evaluation of CAS-DSM is reported using a set of Splash/Splash2 parallel application benchmarks on a distributed memory IBM SP-2 machine. CAS-DSM achieved moderate to good performance improvements for most of the applications compared to the original CVM implementation. Reducing the overheads in polling-based implementation improves the performance of CAS-DSM significantly resulting in an overall improvement of 12-52% over the original CVM implementation.