ppxscal/embedding_network huggingface dataset:
Exhaustive and Near-Exhaustive Memory Testing Techniques and theirBIST Implementations
Authors: Debaleena Das, Mark Karpovsky
Venue: Journal of Electronic Testing: Theory and Applications (1997)

In this work we investigate the problem of detection and location of single and unlinked multiple k-coupling faults in n &times; 1 random-access memories (RAMs). This fault model covers all crosstalks between any k cells in n &times; 1 RAMs. The problem of memory testing has been reduced to the problem of the generation of (n,k-1)-exhaustive backgrounds. We have obtained practical test lengths, for a memory size around 1 M, for detecting up to 6-couplings by exhaustive tests and up to 9-couplings by near-exhaustive tests. The best known test algorithms up to now provide for the detection of 5-couplings only in a 1 M memory, using exhaustive tests. Beyond these parameters, test lengths were impractical. Furthermore, our method for generation of (n,k-1)-exhaustive backgrounds yields short test lengths giving rise to considerably shorter testing times than the present most efficient tests for large n and for k greater than 3. Our test lengths are 50% shorter than other methods for the case of detecting up to 5-couplings in a 1 Mbit RAM. The systematic nature of both our tests enables us to use a built-in self-test (BIST) scheme, for RAMs, with low hardware overhead. For a 1Mbit memory, the BIST area overhead for the detection of 5-couplings is less than 1% for SRAM and 6.8% for a DRAM. For the detection of 9-couplings with 99% or higher probability, the BIST area overhead is less than 0.2% for SRAM and 1.5% for DRAM.
On-line publication of CS laboratories
Authors: Deborah L. Knox
Venue: ACM SIGCSE Bulletin (1997)

Many computer science educators are actively developing laboratory materials in support of their courses because the lab activities provide a rich learning environment. Some instructors are hesitant to pursue this type of pedagogy because of the time commitment required or because of a lack of materials to use as a starting point. This paper describes the development of a repository of computer science laboratories to encourage development and use of labs.The project described is an on-line repository, a database developed for the WEB using HTML forms to help tailor user requests for information. The backbone of the repository is currently CGI scripts written in PERL. The features of the prototype include lab submission, searching by keyword or topic, and an annotation capability for each lab.We also describe the plans for a SIGCSE sponsored peer reviewed on-line repository of lab materials which will create a recognized avenue for the dissemination of labs. The peer review process will help insure a level of quality, and grant developers recognition for their scholarly work in support of teaching.
Measuring Software Dependability by Robustness Benchmarking
Authors: Arup Mukherjee, Daniel P. Siewiorek
Venue: IEEE Transactions on Software Engineering (1997)

Inability to identify weaknesses or to quantify advancements in software system robustness frequently hinders the development of robust software systems. Efforts have been made to develop benchmarks of software robustness to address this problem, but they all suffer from significant shortcomings. This paper presents the various features that are desirable in a benchmark of system robustness, and evaluates some existing benchmarks according to these features. A new hierarchically structured approach to building robustness benchmarks, which overcomes many deficiencies of past efforts, is also presented. This approach has been applied to building a hierarchically structured benchmark that tests part of the Unix file and virtual memory systems. The resultant benchmark has successfully been used to identify new response class structures that were not detected in a similar situation by other less organized techniques.
The Model Checker SPIN
Authors: Gerard J. Holzmann
Venue: IEEE Transactions on Software Engineering (1997)

SPIN is an efficient verification system for models of distributed software systems. It has been used to detect design errors in applications ranging from high-level descriptions of distributed algorithms to detailed code for controlling telephone exchanges. This paper gives an overview of the design and structure of the verifier, reviews its theoretical foundation, and gives an overview of significant practical applications.
Co-emulation and debugging of HW/SW-systems
Authors: Gernot Koch, Udo Kebschull, Wolfgang Rosenstiel
Venue: Proceedings of the 10th international symposium on System synthesis (1997)

In this paper we present a method that allows to observe and control the emulation of communicating systems consisting of hardware and software parts. The approach provides the ability to set breakpoints in either technology without breaking the protocol or loosing data. Systems may contain several software and hardware processes. Each process runs in a separate debugger while the presented approach provides the necessary synchronization between the processes that precludes loss of data at the communication interfaces due to breakpoints. Therefore it allows to continue the operation after a breakpoint which is essential for interactive debugging.
Division-and-Accumulation over GF(2m)
Authors: M. A. Hasan
Venue: IEEE Transactions on Computers (1997)

The Galois field division is a complex arithmetic operation. The corresponding division-and-accumulation (DAA) is not only complex but also a time consuming operation. In this article, the DAA over GF(2m) is considered, and a simple scheme for its sequential operation is presented. A multiple stream DAA structure is developed which supports pipeline operations and yields an increased throughput with only a modest increase in the hardware. As an application, the use of the sequential DAA algorithm is shown for the high speed encoding of Reed-Solomon codes.
Computation of Singularities in Large Nonlinear Systems
Authors: W. Govaerts
Venue: SIAM Journal on Numerical Analysis (1997)

A general approach is proposed for the numerical computation of one-parameter singularities in the sense of Golubitsky and Schaeffer [Singularities and Groups in Bifurcation Theory, Vol. I, Springer-Verlag, Berlin, 1985]. The singularities of codimension three or less are organized in a new way. Our scheme is close to the numerics and in some cases gives explicit expressions for the defining equations (obtained inductively) where no such expressions were previously available. The numerical computation by the Lyapunov--Schmidt reduction summarizes work by many authors during the last 20 years, treating all cases in a unified way. A numerical example is provided where singularities with codimension up to three are detected and computed in a parameterized boundary value problem.
An Efficient Implementation of the Nonsymmetric Lanczos Algorithm
Authors: David Day
Venue: SIAM Journal on Matrix Analysis and Applications (1997)

Lanczos vectors computed in finite precision arithmetic by the three-term recurrence tend to lose their mutual biorthogonality. One either accepts this loss and takes more steps or re-biorthogonalizes the Lanczos vectors at each step. For the symmetric case, there is a compromise approach. This compromise, known as maintaining semiorthogonality, minimizes the cost of reorthogonalization. This paper extends the compromise to the two-sided Lanczos algorithm and justifies the new algorithm.The compromise is called maintaining semiduality. An advantage of maintaining semiduality is that the computed tridiagonal is a perturbation of a matrix that is exactly similar to the appropriate projection of the given matrix onto the computed subspaces. Another benefit is that the simple two-sided Gram--Schmidt procedure is a viable way to correct for loss of duality.A numerical experiment is included in which our Lanczos code is significantly more efficient than Arnoldi's method.
Prediction caches for superscalar processors
Authors: James E. Bennett, Michael J. Flynn
Venue: Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture (1997)

Processor cycle times are currently much faster than memory cycle times, and this gap continues to increase. Adding a high speed cache memory allows the processor to run at full speed, as long as the data it needs is present in the cache. However, memory latency still affects performance in the case of a cache miss. Prediction caches use a history of recent cache misses to predict future misses and to reduce the overall cache miss rate. This paper describes several prediction caches, and introduces a new kind of prediction cache, which combines the features of prefetching and victim caching. This new cache is shown to be more effective at reducing miss rate and improving performance than existing prediction caches.
A functional approach to type constraints of generic definitions
Authors: Myung Ho Kim
Venue: ACM SIGPLAN Notices (1997)

This paper addresses a frequently encountered problem related to type constraints in many contemporary strongly typed object-oriented languages. The problem is that type parameters are often more strongly constrained than is actually needed. As a consequence, reusability of the whole generic definition is limited even when those constraints are only for a portion of the operations it provides. A useful programming idiom to remedy this problem is proposed. It mitigates the problem by moving some of type constraints from the generic definitions to the clients. The only tool required to aid the idiom is the functional parameter.
Unified power control, error correction coding and scheduling for a CDMA downlink system
Authors: Yuming Lu, Robert Brodersen
Venue: Wireless Networks (1997)

Transmitting multimedia data over a CDMA channel presents a new set of challenges. Sometimes, data demands will exceed the system capacity, in which case the system must make the most efficient use of its limited resources. The resources we consider are: fixed bandwidth available for each user and the transmit power budget for each cell. In this paper, we present our approach for unifying power control, variable forward error correction (VFEC), and scheduling for a downlink system by allocating the system resources. Our objective is to maximize the overall system satisfaction, which we call &ldquo;system utility&rdquo;. This objective is achieved by applying a distributed algorithm which divides the overall optimization problem into a hierarchy of three levels (system, cell and user). At each level, the system performs independent and parallel optimizations; the critical information is then passed to the higher level for further optimization. Finally, an iterative and distributed algorithm is applied at the system level to achieve the overall system optimization.
More practical bounded-skew clock routing
Authors: Andrew B. Kahng, C.-W. Albert Tsao
Venue: Proceedings of the 34th annual Design Automation Conference (1997)

Academic clock routing research results has often hadlimited impact on industry practice, since such practical considerationsas hierarchical buffering, rise-time and overshoot constraints,obstacle- and legal location-checking, varying layer parasitics andcongestion, and even the underlying design flow are often ignored.This paper explores directions in which traditional formulationscan be extended so that the resulting algorithms are more usefulin production design environments. Specifically, the following issuesare addressed: (i) clock routing for varying layer parasiticswith nonzero via parasitics; (ii) obstacle-avoidance clock routing;(iii) a new topology design rule for prescribed-delay clock routing;and (iv) predictive modeling of the clock routing itself. Wedevelop new theoretical analyses and heuristics, and present experimentalresults that validate our new approaches.
A proposal for a recursive object-oriented life-cycle
Authors: Kevin E. Carlin, Dino R. Russo, Brad Balfour
Venue: Proceedings of the conference on TRI-ADA '90 (1990)

This paper describes the recursive object oriented life-cycle which has been developed in conjunction with the authors' Object Oriented Development (OOD) methods. The basic goals that a life-cycle must satisfy are described and the recursive life-cycle are mapped back to them. A description of how this life-cycle may be implemented within the framework of existing standards such as DOD-STD-2167A is also included. This paper also summarizes the authors' experience with using this life-cycle (or elements thereof) on various projects over the last six years. Approaches to meeting the issues of formal project management within the recursive framework will also be discussed.
An Interior-Point Method for Approximate Positive Semidefinite Completions
Authors: Charles R. Johnson, Brenda Kroschel, Henry Wolkowicz
Venue: Computational Optimization and Applications (1998)

Given a nonnegative, symmetric matrix of weights, H, we study the problem of finding an Hermitian, positive semidefinite matrix which is closest to a given Hermitian matrix, A, with respect to the weighting H. This extends the notion of exact matrix completion problems in that, H_ij=0 corresponds to the element A_ij being unspecified (free), while H_ij large in absolute value corresponds to the element A_ij being approximately specified (fixed).We present optimality conditions, duality theory, and two primal-dual interior-point algorithms. Because of sparsity considerations, the dual-step-first algorithm is more efficient for a large number of free elements, while the primal-step-first algorithm is more efficient for a large number of fixed elements.Included are numerical tests that illustrate the efficiency and robustness of the algorithms
Pearl: a CMOS timing analyzer
Authors: James J. Cherry
Venue: Proceedings of the 25th ACM/IEEE Design Automation Conference (1988)

Pearl is a timing analyzer that has been used to verify both full custom VLSI and gate array designs. Rather than verify that a design meets a given clock timing, Pearl automatically determines the minimum error free clock period and duty cycles. Delay equations compiled for the circuit facilitate fast incremental analysis when false paths are blocked or transistor sizes are changed while optimizing the circuit. Pearl is one component of a large, tightly integrated set of design tools. This allows it to report delay paths graphically in the schematic editor, greatly improving interpretation of results over simple textual reports. Because it can handle networks that mix transistors and functional models it is able to accurately analyze circuits in which switch level timing models fail. We also describe transistor signal flow direction rules for CMOS circuits used to eliminate false paths.
A &ldquo;Microscopic&rdquo; Study of Minimum Entropy Search in Learning Decomposable Markov Networks
Authors: Y. Xiang, S. K. M. Wong, N. Cercone
Venue: Machine Learning (1997)

Several scoring metrics are used in different search procedures for learning probabilistic networks. We study the properties of cross entropy in learning a decomposable Markov network. Though entropy and related scoring metrics were widely used, its &ldquo;microscopic&rdquo; properties and asymptotic behavior in a search have not been analyzed. We present such a &ldquo;microscopic&rdquo; study of a minimum entropy search algorithm, and show that it learns an I-map of the domain model when the data size is large.Search procedures that modify a network structure one link at a time have been commonly used for efficiency. Our study indicates that a class of domain models cannot be learned by such procedures. This suggests that prior knowledge about the problem domain together with a multi-link search strategy would provide an effective way to uncover many domain models.
Computer User Support degree program: an alternative to computer programming
Authors: Fred Beisse
Venue: 3C ON-LINE (1997)

In a previous 3C ONLINE article, "Degree Program Planned in Computer User Support" [1], a new two-year professional/technical degree program was described which would train students for the computer user support job market. The Computer User Support (CUS) degree was launched at Lane Community College during the 1995-96 year, and we will graduate our first class of approximately 26 students in June, 1997.
A Mediator for Approximate Consistency: Supporting &ldquo;GoodEnough&rdquo; Materialized Views
Authors: Len Seligman, Larry Kerschberg
Venue: Journal of Intelligent Information Systems (1997)

This paper addresses the needs of application designers who would like to tell an automated assistant the following: &ldquo;Here is a query that defines a view I want to materialize within my application. I need this view to remain approximately consistent with the state of the data sources from which the view is derived, in accordance with declaratively specified staleness predicates. When the view becomes stale, follow the refresh strategy I specify (e.g., eager, lazy, hybrid). You must do this in heterogeneous environments containing both active and passive data sources&rdquo;. This paper describes an architecture that realizes this vision. The approach supports materialized, object-based views, called quasi-views , defined over shared databases. Quasi-views are refreshed according to the consistency conditions and refresh strategies specified declaratively by application designers. These conditions allow for the deviation of quasi-views from their database counterparts according to well-defined and monitored approximate consistency predicates. A layer of software called a Mediator\ for\ Approximate\ Consistency automatically generates the database objects necessary to enforce these consistency conditions, shielding the application developer from the implementation details of consistency maintenance. In addition, it does this for both active and passive (e.g., legacy) data sources.This paper formalizes quasi-views, presents a declarative quasi-view specification language, and describes an architecture and implementation of a Mediator for Approximate Consistency.
Implementing a Probabilistic Clock Synchronization Algorithm
Authors: Gianluigi Alari, Augusto Ciuffoletti
Venue: Real-Time Systems (1997)

In this paper we present a new probabilistic clock synchronization algorithm, its prototype implementation and experimental results. The algorithm follows the client-server programming paradigm and is designed to work in a departmental environment with few servers and a number of clients connected through an arbitrary network topology. At the core of the algorithm is a remote clock reading method that mitigates the negative effects of message delay uncertainty. The implementation proves the effectiveness of this approach and corroborates the theoretical speculations.
The filter cache: an energy efficient memory structure
Authors: Johnson Kin, Munish Gupta, William H. Mangione-Smith
Venue: Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture (1997)

Most modern microprocessors employ one or two levels of on-chip caches in order to improve performance. These caches are typically implemented with static RAM cells and often occupy a large portion of the chip area. Not surprisingly, these caches often consume a significant amount of power. In many applications, such as portable devices, low power is more important than performance. We propose to trade performance for power consumption by filtering cache references through an unusually small L1 cache. An L2 cache, which is similar in size and structure to a typical L1 cache, is positioned behind the filter cache and serves to reduce the performance loss. Experimental results across a wide range of embedded applications show that the filter cache results in improved memory system energy efficiency. For example, a direct mapped 256-byte filter cache achieves a 58% power reduction while reducing performance by 21%, corresponding to a 51% reduction in the energy-delay product over conventional design.
Validation of trace-driven simulation models: regression analysis revisited
Authors: Jack P. C. Kleijnen, Bert Bettonvil, Willem J. H. Van Groenendaal
Venue: Proceedings of the 28th conference on Winter simulation (1996)

For the validation of trace-driven simulation models this paper recommends a simple statistical test that uses elementary regression analysis in a novel way. This test concerns a (joint) null-hypothesis: the outputs of the simulated and the real systems have the same means and the same variances. Technically, the differences between simulated and real outputs are regressed on their sums, and the resulting slope and intercept are tested to be zero. This paper further proves that it is wrong to use a naive test that regresses the simulation outputs on the real outcomes, and hypothesizes that the resulting regression line gives a 45 /spl deg/ line through the origin. The new and the old tests are investigated in Monte Carlo experiments with inventory systems. The conclusion is that the new test has the correct type I error probability, whereas the old test (falsely) rejects a valid simulation model substantially more often than the nominal alpha level. The power of the new test increases, as the simulation model deviates more from the real system.
Rapid Prototyping of Application-SpecificSignal Processors (RASSP) In-Progress Report
Authors: James E. Saultz
Venue: Journal of VLSI Signal Processing Systems (1997)

The goal of the DARPA/Tri-Service-sponsored Rapid Prototyping of Application-Specific Signal Processors (RASSP) program is to reduce the cost and time to develop and manufacture signal processors by at least a factor of four. Lockheed Martin Advanced Technology Laboratories&lsquo; (ATL) approach to reaching this goal is based on three thrusts: methodology, model-year architecture, and infrastructure (enterprise). The Advanced Technology Laboratories&lsquo; RASSP team&mdash;composed of an alliance of companies&mdash;implemented the first baseline RASSP system, which advances today&lsquo;s state-of-the-art by a factor of >2X. The Advanced Technology Laboratories&lsquo; RASSP team used the methodology and tools to demonstrate cost and design-cycle improvements on the benchmark virtual proto-type, and developed a hardware/software system that demonstrated first-pass success. Additional developments underway will provide further benefits and will demonstrate 4X improvements in cost and time to market. This paper updates the team&lsquo;s progress halfway through the program, and highlights the impact of using the RASSP concepts on the design of a SAR processor, a Navy standard processor upgrade, and a CNI application.
Modeling the &ldquo;multipolicy machine&rdquo;
Authors: D. Elliott Bell
Venue: Proceedings of the 1994 workshop on New security paradigms (1994)

A method of treating several unspecified policies is presented. Precise notions of policy combination, policy conflict, conflict resolution, and policy precedence are introduced. Necessary and sufficient conditions for policies to be combined without conflict are established.
Quantitative Evaluation of Register Pressure on Software Pipelined Loops
Authors: Josep Llosa, Eduard Ayguadé, Mateo Valero
Venue: International Journal of Parallel Programming (1998)

Software Pipelining is a loop scheduling technique that extracts loop parallelism by overlapping the execution of several consecutive iterations. One of the drawbacks of software pipelining is its high register requirements, which increase with the number of functional units and their degree of pipelining. This paper analyzes the register requirements of software pipelined loops. It also evaluates the effects on performance of the addition of spill code. Spill code is needed when the number of registers required by the software pipelined loop is larger than the number of registers of the target machine. This spill code increases memory traffic and can reduce performance. Finally, compilers can apply transformations in order to reduce the number of memory accesses and increase functional unit utilization. The paper also evaluates the negative effect on register requirements that some of these transformations might produce on loops.