ppxscal/embedding_network huggingface dataset:
Proceedings of the 4th ACM international workshop on Wireless mobile multimedia
Venue: International Workshop on Wireless Mobile Multimedia (2001)

It is with great pleasure that we welcome you to the historical city of Rome, Italy and to the Fourth Annual International Workshop on Wireless Mobile Multimedia - WoWMoM '01We believe that this will be the best WoWMoM thus far. We base our assertion on this year's program, which we are very proud of. The program consists of 11 technical papers and presentations, broken up into three sessions. The papers contain research results on a variety of problems being faced by deployers and users of wireless technology world-wide.We are able to put together a strong program because of the excellent response we received to our call for papers. We received a total of 48 papers from some of the top research institutes from around the world. Statistically speaking, we received the largest number of papers inWoWMoM's history, 33% more papers than last year. 65% of the papers were from academia and 35% from industry. 47% of the papers were from the United States and Canada and 53% from Europe and Asia. These numbers reflect the fact that WoWMoM is truly an international event and that the area of wireless mobile multimedia is still growing. WoWMoM's success can be attributed to its International Program Committee (PC) whose members are some of the strongest active researchers in the field of wireless multimedia, and who represent our global community remarkably. This year's Program Committee had to work under severe time constraints but they came through with flying colors. All in all we generated a total of 144 reviews, with each committee member contributing over 17 reviews in less than 4 weeks. The process we employed for selecting the final set of papers was rigorous. Once all the reviews were in, we ranked order the papers using different criterions, (for example, overall recommendation, originality of the ideas, product of these two criterion etc.) and then looked at the resulting lists to identify the better papers. We then went through the reviews of each of the papers, reading reviewer comments while keeping in mind the confidence they had placed on their reviews, and looking at the relevance of the paper to WoWMoM. We marked papers with disparate reviews and asked the PC members to resolve their differences and come up with a unanimous recommendation. We discussed over 75% of the papers and following this came up with our list of recommendations. The PC reviewed these recommendations one more time and subsequently the final program was announced. Owing to the fact that WoWMoM is a one-day workshop and the quality of the papers was paramount to us, we selected less than 25% of the submissions. We feel that the result of all this effort is that we can bring to you a fairly high-quality program, which we hope you will enjoy and benefit from.
A Unified Tool for Fuzzy/Neural Network Systems
Authors: Alfredo Sanz
Venue: IEEE Micro (1997)

This work present a new tools for the developing complex systems which use fuzzy logic and neural networks technology. We propose a model, named IDEA, to build complex control systems from a biological origin. This model builds of block ANS linked by objects named Vinculos. I define also a high level description language. This tool eases the process of developing of this systems the final implementation by a software simulation or by a specific electronic circuit.
A Non-Two-Phase Locking Protocol for Global Concurrency Control in Distributed Heterogeneous Database Systems
Authors: K. Vidyasankar
Venue: IEEE Transactions on Knowledge and Data Engineering (1991)

A concurrency control method is proposed for global transactions in a distributed heterogeneous database system. This method is applicable when the database sites are interconnected in a rooted tree fashion. It guarantees deadlock freedom in addition to serializability. A general architecture of a heterogeneous system is given. The global transaction manager (GTM) decomposes the global transactions initiated at a site and the subtransactions received from other sites into smaller subtransactions, some of which are sent to the GTMs of the other sites, and those remaining, called g-local transactions, are to be executed by the local transaction manager (LTM) at that site. A concurrency control mechanism ensures serializability among: the local transactions (including the g-local transactions of the global ones) at each site, the global transactions and the global and local transactions together.
Broadcast Encryption's Bright Future
Authors: Jeffrey Lotspiech, Stefan Nusser, Florian Pestoni
Venue: Computer (2002)

Broadcast encryption was designed to answer the question--Can two devices, previously unknown to each other, agree upon a key if they only have a one-way communication path? They can, and the one-way nature of this communication gives the technology its name. Recent advances in broadcast encryption threaten to unseat public key encryption's use in certain applications. To commercialize the technology for media content protection, IBM, Intel, Matsushita, and Toshiba developed the Content Protection for Recordable Media technology. Devices that use CPRM have already been marketed, including digitalaudio players and video recorders, and some flash-memory music players. The authors' work focuses on various aspects of content protection, which they consider to be the ideal application for broadcast encryption.
Binary Extended Perfect Codes of Length 16 by the Generalized Concatenated Construction
Authors: V. A. Zinoviev, D. V. Zinoviev
Venue: Problems of Information Transmission (2002)

We enumerate binary extended nonlinear perfect codes of length 16 obtained by the generalized concatenated construction (GC-construction). There are 15 different types of such codes. They are defined by pairs of MDS codes Ai: (4, 2, 64)4. For every pair, we give the number of nonequivalent codes of this type. In total, there are 285 nonequivalent binary extended nonlinear perfect codes of length 16 obtained by the GC-construction, including the Hamming (i.e., linear) code. Thus, we obtain all binary extended perfect codes of length 16 and rank 13. Their total number is equal to 272.
Error Correcting Codes Over Z/sub 2(m/) for Algorithm-Based Fault Tolerance
Authors: G. L. Feng, T. R. N. Rao, M. S. Kolluru
Venue: IEEE Transactions on Computers (1994)

Algorithm-based fault tolerance is a scheme of low-cost error protection in real-time digital signal processing environments and other computation-intensive tasks. In this paper, a new method for encoding data is proposed and, furthermore, two kinds of error-correcting codes over Z/sub 2(m/), which can be used with fixed-point arithmetic in practical algorithm-based fault tolerant systems, are introduced.
Optimal and Load Balanced Mapping of Parallel Priority Queues in Hypercubes
Authors: Sajal K. Das, M. Cristina Pinotti, Falguni Sarkar
Venue: IEEE Transactions on Parallel and Distributed Systems (1996)

In this paper, we efficiently map a priority queue on the hypercube architecture in a load balanced manner, with no additional communication overhead, and present optimal parallel algorithms for performing insert and deletemin operations. Two implementations for such operations are proposed on the single-port hypercube model. In a b-bandwidth, n-item priority queue in which every node contains b items in sorted order, the first implementation achieves optimal speed-up of $O({\rm min}\{{\rm log}\,\,n,{\textstyle{{b\,\,{\rm log}\,\,n} \over {{\rm log}\,\,b\,\,+\,\,{\rm log}\,{\rm log}\,\,n}}}\})$ for inserting b presorted items or deleting b smallest items, where $b = O(n^{{1 \mathord{\left/ {\vphantom {1 c}} \right. \kern-\nulldelimiterspace} c}})$ with c > 1. In particular, single insertion and deletion operations are cost-optimal and require $O({\textstyle{{{\rm log}\,n} \over p}} + {\rm log} \,\, p)$ time using $O({\textstyle{{{\rm log}^{}\,\,n} \over {{\rm log}\,{\rm log}\,\,n}}})$ processors.The second implementation is more scalable since it uses a larger number of processors, and attains a "nearly" optimal speed-up on the single hypercube. Namely, the insertion of log n presorted items or the deletion of the log n smallest items is accomplished in O(log log n2)time using $O({\textstyle{{{\rm log}^2\,\,n} \over {{\rm log}\,{\rm log}\,\,n}}})$ processors. Finally, on the slightly more powerful pipelined hypercube model, the second implementation performs log n operations in O(log log n) time using $O({\textstyle{{{\rm log}^2\,\,n} \over {{\rm log}\,{\rm log}\,\,n}}})$ processors, thus achieving an optimal speed-up. To the best of our knowledge, our algorithms are the first implementations of b-bandwidth distributed priority queues, which are load balanced and yet guarantee optimal speed-ups.
A Multiclass Priority-Based Slotted-Ring LAN and its Analysis
Authors: S. Mukherjee, S. K. Tripathi, D. Ghosal
Venue: IEEE Transactions on Computers (1993)

A protocol for a slotted-ring local area network to handle two classes of jobs in which one class has preemptive priority over the other is presented. The detailed response time distribution analysis for different classes of jobs is given. It is shown that the modeling and analysis can be extended to multiclass jobs.
Hardware-Software Cosynthesis for Microcontrollers
Authors: Rolf Ernst, Jorg Henkel, Thomas Benner
Venue: IEEE Design Test (1993)

The authors present a software-oriented approach to hardware-software partitioning which avoids restrictions on the software semantics as well as an iterative partitioning process based on hardware extraction controlled by a cost function. This process is used in Cosyma, an experimental cosynthesis system for embedded controllers. As an example, the extraction of coprocessors for loops is demonstrated. Results are presented for several benchmark designs.
SPEC CPU2000: Measuring CPU Performance in the New Millennium
Authors: John L. Henning
Venue: Computer (2000)

As computers and software have become more powerful, it seems almost human nature to want the biggest and fastest toy you can afford. But how do you know if your toy is tops? Even if your application never does any I/O, it's not just the speed of the CPU that dictates performance. Cache, main memory, and compilers also play a role. Software applications also have differing performance requirements. So whom do you trust to provide this information?The Standard Performance Evaluation Corporation (SPEC) is a nonprofit consortium whose members include hardware vendors, software vendors, universities, customers, and consultants. SPEC's mission is to develop technically credible and objective component- and system-level benchmarks for multiple operating systems and environments, including high-performance numeric computing, Web servers, and graphical subsystems.On 30 June 2000, SPEC retired the CPU95 benchmark suite. Its replacement is CPU2000, a new CPU benchmark suite with 19 applications that have never before been in a SPEC CPU suite. This article discusses how SPEC developed this benchmark suite and what the benchmarks do
Efficient Parallel Processing of Image Contours
Authors: L. T. Chen, L. S. Davis, C. P. Kruskal
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1993)

Describes two parallel algorithms for ranking the pixels on a curve in O (log N) time using either an EREW or CREW PRAM model. The algorithms accomplish this with N processors for a square root N* square root N image. After applying such an algorithm to an image, it is possible to move the pixels from a curve into processors having consecutive addresses. This is important because one can subsequently apply many algorithms to the curve (such as piecewise linear approximation algorithms or point in polygon tests) using segmented scan operations (i.e. parallel prefix operations). Scan operations can be executed in logarithmic time on many interconnection networks, such as hypercube, tree, butterfly, and shuffle exchange machines as well as on the EREW PRAM. The algorithms were implemented on the hypercube structured Connection Machine, and various performance tests were conducted.
A new proof of Melnikov's conjecture on the edge-face coloring of plane graphs
Authors: Weifan Wang, Ko-Wei Lih
Venue: Discrete Mathematics (2002)

In 1975, Melnikov conjectured that the edges and faces of each plane graph G may be colored with Δ(G)+3 colors so that any two adjacent or incident elements receive different colors, where Δ(G) is the maximum degree of G. Two similar, yet independent, proofs of this conjecture have been published recently by Waller (J. Combin. Theory Ser. B 69 (1997) 219) and Sanders and Zhao (Combinatorica 17 (1997) 441). Both proofs made use of the Four-Color Theorem. This paper presents a new proof of Melnikov's conjecture independent of the Four-Color Theorem.
A Defined Process For Project Postmortem Review
Authors: Bonnie Collier, Tom DeMarco, Peter Fearey
Venue: IEEE Software (1996)

Conventional wisdom in the software industry decrees that it's good practice to conduct a postmortem study at the end of each project. Some would even suggest that this is not just a useful undertaking, but one of the fundamental principles of successful software development. The rationale authors most often cite for postmortem analysis is that only by analyzing our shortcomings can we learn to do better.We must begin by cataloguing such failures and learning from their patterns. The success of the postmortem-or of any learning process-demands a context that makes organizational learning possible. Participants are empowered when they know that each issue raised during the postmortem process must be added to the risk database and evaluated methodically on each subsequent project.
Reflections on the Nature of Multi-Agent Coordination and Its Implications for an Agent Architecture
Authors: Victor R. Lesser
Venue: Autonomous Agents and Multi-Agent Systems (1998)

The development of enabling infrastructure for the next generation of multi-agent systems consisting of large numbers of agents and operating in open environments is one of the key challenges for the multi-agent community.Current infrastructure support does not materially assist in the development of sophisticated agent coordination strategies. It is the need for and the development of such a high-level support structure that will be the focus of this paper. A domain-independent (generic) agent architecture is proposed that wraps around an agent's problem-solving component in order to make problem solving responsive to real-time constraints, available network resources, and the need to coordinate&mdash;both in the large and small&mdash;with problem-solving activities of other agents. This architecture contains five components, local agent scheduling, multi-agent coordination, organizational design, detection and diagnosis, and on-line learning, that are designed to interact so that a range of different situation-specific coordination strategies can be implemented and adapted as the situation evolves. The presentation of this architecture is followed by a more detailed discussion on the interaction among these components and the research questions that need to be answered to understand the appropriateness of this architecture for the next generation of multi-agent systems.
Systematic Design of Pipelined Recursive Filters
Authors: M. Lapointe, H. T. Huynh, P. Fortier
Venue: IEEE Transactions on Computers (1993)

Systematic design of pipelined recursive filters is presented. The procedure is based on a multiplication algorithm which generates the result with most significant digit first. Since the latency of such a multiplier is low, a reduced number of pipelining delays may be introduced in the reduction loop, resulting in a high sampling rate. The implementation obtained exhibits minimum hardware and ensures minimum latency. It is shown that its flexibility allows, on one hand, the ability to choose freely the number system radix and, on the other hand, the interleaving of two multiplier arrays into one. This is illustrated by the realization of a second-order all-pole filter, operating in a radix-4 representation and using only one array to perform two multiplications. In this way, long interconnections are avoided and denser and more regular layout is achieved. It turns out that the design procedure can also be applied successfully to various types of realization where multiplications are required.
Efficient program tracing
Venue: Computer (1993)

A program trace lists the addresses of instructions executed and data referenced during a program's execution. Earlier approaches to collecting program traces, including abstract execution and optimal control tracing, are reviewed. Two tracing systems based on these techniques are presented. Results collected when using the later systems on several programs show significant reductions in the cost of collecting traces. Reduction in trace file sizes are also significant.
An adjustment algorithm for optimal run orders in design of experiments
Authors: Lieven Tack, Martina Vandebroek
Venue: Computational Statistics Data Analysis (2002)

Using a systematic run order can be the proper way to conduct an experiment when a temporal trend is present. The construction of run orders that are optimally balanced for time trend effects is based on maximization of the information on the parameters of interest whereas the parameters of the postulated time trend are treated as nuisance parameters. An adjustment algorithm to improve the efficiency of the run orders obtained from a search over a predefined set of candidate points is presented. This is done by repeatedly moving the design points or the time points of the candidate list a small amount along their axes as long as an improvement in the efficiency is obtained. It is illustrated that the adjustment algorithm involves substantial increases in the efficiency of the run orders. The use of the adjustment algorithm in addition to a search over a coarse grid of candidate points is especially recommended in situations where the computation time has to be kept within reasonable limits.
Scheduling Data-Flow Graphs via Retiming and Unfolding
Authors: Liang-Fang Chao, Edwin Hsing-Mean Sha
Venue: IEEE Transactions on Parallel and Distributed Systems (1997)

Loop scheduling is an important problem in parallel processing. The retiming technique reorganizes an iteration; the unfolding technique schedules several iterations together. We combine these two techniques to obtain a static schedule with a reduced average computation time per iteration. We first prove that the order of retiming and unfolding is immaterial for scheduling a data-flow graph (DFG). From this nice property, we present a polynomial-time algorithm on the original DFG, before unfolding, to find the minimum-rate static schedule for a given unfolding factor. For the case of a unit-time DFG, efficient checking and retiming algorithms are presented.
Emergence of Orienting Behavior in Ecological Neural Networks
Authors: Paolo Bartolomeo, Luigi Pagliarini, Domenico Parisi
Venue: Neural Processing Letters (2002)

We investigated the emergence of orienting behavior in artificial organisms that evolved following a genetic algorithm. These organisms live in a simulated environment containing food and danger elements and reproduce selectively based on the capacity of each individual to eat food while avoiding danger. When the amount of computational resources (number of hidden units) is adequate to the difficulty of the perceptual discrimination between food and danger, peripheral vision is sufficient to trigger stimulus identification. When the resources are scarce, the central portion of the sensory surface becomes a &lsquo;fovea&rsquo;, and the presence of a stimulus in peripheral vision triggers an orienting movement (foveation), before the organism can decide whether to eat or to avoid the object. Thus, orienting movements, as well as the segregation of processing resources into a high-definition fovea and a poor-definition periphery, may originate from a disproportion between complex perceptual tasks and (relatively) scarce computational resources.
A Survey of Languages for Specifying Dynamics: A Knowledge Engineering Perspective
Authors: Pascal van Eck, Joeri Engelfriet, Dieter Fensel, Frank van Harmelen, Yde Venema, Mark Willems
Venue: IEEE Transactions on Knowledge and Data Engineering (2001)

During the last years, a number of formal specification languages for knowledge-based systems has been developed. Characteristics for knowledge-based systems are a complex knowledge base and an inference engine which uses this knowledge to solve a given problem. Specification languages for knowledge-based systems have to cover both aspects. They have to provide the means to specify a complex and large amount of knowledge and they have to provide the means to specify the dynamic reasoning behavior of a knowledge-based system. This paper focuses on the second aspect. For this purpose, we survey existing approaches for specifying dynamic behavior in related areas of research. In fact, we have taken approaches for the specification of information systems (Language for Conceptual Modeling and Troll), approaches for the specification of database updates and logic programming (Transaction Logic and Dynamic Database Logic) and the generic specification framework of Abstract State Machines.
Optimal Secondary Storage Access Sequence for Performing Relational Join
Authors: F. Fotouhi, S. Pramanik
Venue: IEEE Transactions on Knowledge and Data Engineering (1989)

Two graph models are developed to determine the minimum required buffer size for achieving the theoretical lower bound on the number of disk accesses for performing relational joins. Here, the lower bound implies only one disk access per joining block or page. The first graph model is based on the block connectivity of the joining relations. Using this model, the problem of determining an ordered list of joining blocks that requires the smallest buffer is considered. It is shown that this problem as well as the problem of computing the least upper bound on the buffer size is NP-hard. The second graph model represents the page connectivity of the joining relations. It is shown that the problem of computing the least upper bound on the buffer size for the page connectivity model is also NP-hard. Heuristic procedures are presented for the page connectivity model and it is shown that the sequence obtained using the heuristics requires a near-optimal buffer size The authors also show the performance improvement of the proposed heuristics over the hybrid-has join algorithm for a wide range of join factors.
Rotator Graphs: An Efficient Topology for Point-to-Point Multiprocessor Networks
Authors: P. F. Corbett
Venue: IEEE Transactions on Parallel and Distributed Systems (1992)

Rotator graphs, a set of directed permutation graphs, are proposed as an alternative to star and pancake graphs. Rotator graphs are defined in a way similar to the recently proposed Faber-Moore graphs. They have smaller diameter, n-1 in a graph with n factorial vertices, than either the star or pancake graphs or the k-ary n-cubes. A simple optimal routing algorithm is presented for rotator graphs. The n-rotator graphs are defined as a subset of all rotator graphs. The distribution of distances of vertices in the n-rotator graphs is presented, and the average distance between vertices is found. The n-rotator graphs are shown to be optimally fault tolerant and maximally one-step fault diagnosable. The n-rotator graphs are shown to be Hamiltonian, and an algorithm for finding a Hamiltonian circuit in the graphs is given.