ppxscal/embedding_network huggingface dataset:
MIP Models and BB Strategies in Brachytherapy Treatment Optimization
Authors: Robert R. Meyer, Warren D. D'Souza, Michael C. Ferris, Bruce R. Thomadsen
Venue: Journal of Global Optimization (2003)

Brachytherapy (brachy being derived from a Greek word meaning short) is the treatment by means of radioactive sources that are placed at short distances from the target cells. This form of therapy is becoming common in the treatment of early stage prostate cancer, the most common cancer and the second leading cause of cancer deaths among American males. We consider the use of mixed-integer programming (MIP) models and branch-and-bound (BB) methods to optimize the placement within the prostate of the radioactive ``seeds'' used in this procedure. Several different optimization models are considered along with a number of branchand- bound strategies. With appropriate combinations of modelling and solution strategies, nearoptimal seed placements can be generated for each two-dimensional ultrasound section of the prostate in less than five minutes on a 333-MHz workstation. The original three-dimensional problem can then be solved by considering an appropriately interrelated sequence of these two-dimensional problems.
A Cutting Plane Method for Solving Quasimonotone Variational Inequalities
Authors: P. Marcotte, D. L. Zhu
Venue: Computational Optimization and Applications (2001)

We present an iterative algorithm for solving variational inequalities under the weakest monotonicity condition proposed so far. The method relies on a new cutting plane and on analytic centers.
Deferred Correction in Space and Time
Authors: Bertil Gustafsson, Lina Hemmingsson-Frändén
Venue: Journal of Scientific Computing (2002)

High order implicit methods are constructed for the solution of first order hyperbolic systems of PDE. The methods are based on the deferred correction principle in both space and time, and require only p/2 stages at each timestep for achieving accuracy of order p. Furthermore, they are suitable for applying domain decomposition techniques for implementation on parallel computers.
On the Calculation of Fractal Features from Images
Authors: S. S. Chen, J. M. Keller, R. M. Crownover
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1993)

Fractal geometry is becoming increasingly more important in the study of image characteristics. There are numerous methods available to estimate parameters from images of fractal surfaces. A very general technique to calculate numerous fractal features involves the estimation of the mass density function by box counting. The authors analyze the box-counting method, establish a lower bound for the box size, and indicate how algorithms can be improved to give better estimates of fractal features of images. This provides a theoretical basis for a heuristic approach used by C.A. Pickover and A.L. Khorasani (1986).
A Practical Architecture for Reliable Quantum Computers
Authors: Mark Oskin, Frederic T. Chong, Isaac L. Chuang
Venue: Computer (2002)

Quantum computers offer the prospect of computation that scales exponentially with data size. Unfortunately, a single bit error can corrupt an exponential amount of data. Quantum mechanics can seem more suited to science fiction than system engineering, yet small quantum devices of 5 to 7 bits have been built in the laboratory, 100-bit devices are on the drawing table now, and emerging quantum technologies promise even greater scalability. Empirical studies of practical quantum architectures are just beginning to appear in the literature. Elementary architectural concepts are still lacking: How do we provide quantum storage, data paths, classical control circuits, parallelism, and system integration? And, crucially, how can we design architectures to reduce error-correction overhead? The authors describe a proposed architecture that uses code teleportation, quantum memory refresh units, dynamic compilation of quantum programs, and scalable error correction to achieve system- level efficiencies. They assert that their work indicates the underlying technology's reliability is crucial; practical architectures will require quantum technologies with error rates between 10 ?6 and 10 ?9 .
Learning and Feature Selection in Stereo Matching
Authors: M. S. Lew, T. S. Huang, K. Wong
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1994)

We present a novel stereo matching algorithm which integrates learning, feature selection, and surface reconstruction. First, a new instance based learning (IBL) algorithm is used to generate an approximation to the optimal feature set for matching. In addition, the importance of two separate kinds of knowledge, image dependent knowledge and image independent knowledge, is discussed. Second, we develop an adaptive method for refining the feature set. This adaptive method analyzes the feature error to locate areas of the image that would lead to false matches. Then these areas are used to guide the search through feature space towards maximizing the class separation distance between the correct match and the false matches. Third, we introduce a self-diagnostic method for determining when apriori knowledge is necessary for finding the correct match. If the a priori knowledge is necessary then we use a surface reconstruction model to discriminate between match possibilities. Our algorithm is comprehensively tested against fixed feature set algorithms and against a traditional pyramid algorithm. Finally, we present and discuss extensive empirical results of our algorithm based on a large set of real images.
Challenges to Combining General-Purpose and Multimedia Processors
Authors: Thomas M. Conte, Pradeep K. Dubey, Matthew D. Jennings, Ruby B. Lee, Alex Peleg, Salliah Rathnam, Mike Schlansker, Peter Song, Andrew Wolfe
Venue: Computer (1997)

Multimedia workloads have always held an important role in embedded applications, but now they are becoming increasingly common in general-purpose computing as well. Over the past three years, the major vendors of general-purpose processors (GPPs) have announced extensions to their instruction set architectures that supposedly enhance the performance of multimedia workloads. Merging new multimedia instructions with existing GPPs poses several challenges. Also, some doubt remains as to whether multimedia extensions are a real development or just a competition-induced fad in the GPP industry. If it is indeed a development, how must current processor microarchitectures change in reaction? Multimedia extensions are here to stay, but compiler designers, language designers, and microarchitects face large, difficult problems. The ultimate solution will depend on collaboration between universities and industry-a successful combination familiar to most processor designers.
Beyond broadcast
Authors: Kevin Livingston, Mark Dredze, Kristian Hammond, Larry Birnbaum
Venue: Proceedings of the 8th international conference on Intelligent user interfaces (2003)

The work presented in this paper takes a novel approach to the task of providing information to viewers of broadcast news. Instead of considering the broadcast news as the end product, this work uses it as a starting point to dynamically build an information space for the user to explore. This information space is designed to satisfy the users information needs, by containing more breadth, depth, and points of view than the original broadcast story. The architecture and current implementation are discussed, and preliminary results from the analysis of some its components are presented
A Neural Network Accelerator for Image Analysis
Authors: Eric Cosatto, Hans Peter Graf
Venue: IEEE Micro (1995)

We describe an image analysis system developed around two NET32K neural network processors. This single-board system scans simultaneously 64 templates of size 16x16 pixels over bilevel images. For each template it produces a feature map, marking where in the image a match has been found. The system processes over 20 images of size 512x512 pixels in one second. Two analog neural network chips are at the heart of the system, computing over 100 billion multiply-accumulates per second. By coding simple generic shapes, such as strokes, corners, and end-lines into the templates, the resulting feature maps describe the image's content with a set of building blocks. From this representation a quick and robust analysis of the image's content is possible, even if the images are complex and noisy. The system is used for such tasks as locating address blocks on mail pieces and analyzing the layout of checks.
A Game-Theoretic Approach to Integration of Modules
Authors: H. I. Bozma, J. S. Duncan
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1994)

This paper offers a new approach to integration of modules in an intelligent sensor system. Such a system requires that a set of modules-each doing a smaller portion of the overall task-be integrated within a unifying framework. From the perspective of computational systems, this problem holds a considerable interest because it is characterized by a set of coexisting mathematical objectives that need to be optimized simultaneously. In this sense, the design considerations necessitate the introduction of problem solving with multiple objectives. This paper explores these issues in the instance when each module is associated with a mathematical objective that is a function of the outputs of other modules. The integration problem is formulated and what is required of a good solution is presented. This examination interprets the decentralized mediation of conflicting subgoals as promoting a N-player game amongst the modules to be integrated and proposes a game-theoretic integration framework. We model the interaction among the modules as a noncooperative game and argue that this strategy leads to a framework in which the solutions correspond to a compromise decision. The application of this framework in image analysis motivates the hope that a framework such as game-theoretic integration will facilitate the development of general design principles for "modular" systems.
JPernLite: Extensible Transaction Services for the WWW
Authors: Jingshuang Yang, Gail E. Kaiser
Venue: IEEE Transactions on Knowledge and Data Engineering (1999)

Concurrency control is one of the key problems in design and implementation of collaborative systems such as hypertext/hypermedia systems, CAD/CAM systems, and software development environments. Most existing systems store data in specialized databases with built-in concurrency control policies, usually implemented via locking. It is desirable to construct such collaborative systems on top of the World Wide Web, but most Web servers do not support even conventional transactions, let alone distributed (multi-Website) transactions or flexible concurrency control mechanisms oriented toward teamwork¿such as event notification, shared locks, and fine granularity locks. We present a transaction server that operates independently of Web servers or the collaborative systems, to fill the concurrency control gap. By default, the transaction server enforces the conventional atomic transaction model, where sets of operations are performed in an all-or-nothing fashion and isolated from concurrent users. The server can be tailored dynamically to apply more sophisticated concurrency control policies appropriate for collaboration. The transaction server also supports applications employing information resources other than Web servers, such as legacy databases, CORBA objects, and other hypermedia systems. Our implementation permits a wide range of system architecture styles.
Online and Offline BIST in IP-Core Design
Authors: Alfredo Benso, Silvia Chiusano, Giorgio Di Natale, Paolo Prinetto, Monica Lobetti Bondoni
Venue: IEEE Design Test (2001)

This article presents an online and offline built-in self-test architecture implemented as an SRAM intellectual-property core for telecommunication applications. The architecture combines fault-latency reduction, code-based fault detection, and architecture-based fault avoidance to meet reliability constraints.
An Optimizer for Hardware Synthesis
Authors: J. Bhasker, Huan-Chih Lee
Venue: IEEE Design Test (1990)

A description is given of a process-graph analyzer, i.e. a program that optimizes an algorithmic hardware description while endeavoring to attain maximum speed with the minimum commitment to resources. The analyzer is part of the V-Synth system. The four major subsystems of the analyzer-the decomposer, the optimizer, the control-state generator, and the translator-are discussed. Because both its input and output are in VHDL, VHDL itself is discussed. Preliminary test results for the analyzer are presented.
Implementing the Double Bootstrap
Authors: B. D. McCullough, H. D. Vinod
Venue: Computational Economics (1998)

The single bootstrap already is popular in economics, though the double bootstrap has better convergence properties. We discuss the theory and implementation of the double bootstrap, both with and without the pivotal transformation, and give detailed examples of each. One example is a nonlinear double bootstrap of a Cobb-Douglas production function, and explains the use of Gauss-Newton Regressions as a device to decrease computational time. Another example is double bootstrapping elasticities from a translog production function.
E-Kernel: An Embedding Kernel on the IBM Victor V256 Multiprocessor for Program Mapping and Network Reconfiguration
Authors: E. Ma, D. G. Shea
Venue: IEEE Transactions on Parallel and Distributed Systems (1994)

We present the design of E-kernel, an embedding kernel on the Victor V256message-passing partitionable multiprocessor, developed for the support of programmapping and network reconfiguration. E-kernel supports the embedding of a new network topology onto Victor's 2D mesh and also the embedding of a task graph onto the 2D mesh network or the reconfigured network. In the current implementation, the reconfigured network can be a line or an even-size ring, and the task graphs meshes or tori of a variety of dimensions and shapes or graphs with similar topologies. For application programs having these task graph topologies and that are designed according to the communication model of E-kernel, they can be run without any change on partitions connected by the 2D mesh, line, or ring. Further, E-kernel attempts the communication optimization of these programs on the different networks automatically, thus making both the network topology and the communication optimization attempt completely transparent to the application programs. Many of the embeddings used in E-kernel are optimal or asymptotically optimal (with respect to minimum dilation cost). Theimplementation of E-kernel translated some of the many theoretical results in graphembeddings into practical tools for program mapping and network reconfiguration in aparallel system. E-kernel is functional on Victor V256. Measurements of E-kernel'sperformance on V256 are also included.
A Parallel Algorithm for Computing Fourier Transforms on the Star Graph
Authors: P. Fragopoulou, S. G. Akl
Venue: IEEE Transactions on Parallel and Distributed Systems (1994)

The n-star graph, denoted by S/sub n/, is one of the graph networks that have beenrecently proposed as attractive alternatives to the n-cube topology for interconnectingprocessors in parallel computers. We present a parallel algorithm for the computation ofthe Fourier transform on the star graph. The algorithm requires O(n/sup 2/) multiply-addsteps for an input sequence of n! elements, and is hence cost-optimal with respect tothe sequential algorithm on which it is based. This is believed to be the first algorithm,and the only one to date, for the computation of the Fourier transform on the star graph.
A 3D shape matching framework
Authors: Ee Chien Chang, Zhiyong Huang, Mohan S. Kankanhalli, Rong Xu
Venue: Proceedings of the 1st international conference on Computer graphics and interactive techniques in Australasia and South East Asia (2003)

The research of 3D shape matching starts to get more attention recently. In this short paper, we present a 3D shape matching framework. First, we give a general definition of similarity value of two objects. Then, an algorithm is proposed consisting of Principal Component Analysis (PCA), voxelization, and iterative coarse-to-fine aligning of two objects using multi-resolution volume representation. This process will align two objects to have the maximum overlap. Then, we can compute the similarity value for shape matching. The experiment results show the effectiveness of our framework.
Real-Time Atomic Multicast Algorithms Implemented on a Shared Memory Multiprocessor
Authors: P. D. V. Van Der Stok, A. H. T. Janssen-Raemaekers
Venue: Real-Time Systems (2003)

Processes are distributed over processors that share directly accessible memory. Processes exchange messages via memory. Algorithms are specified which satisfy the atomic multicast requirements under two fault hypotheses: (1) fail-stop memory and fail stop processes and (2) fail-stop memory and processes with timing failures. It is shown that the algorithms can be applied under different scheduling conditions: (1) hard real-time (HRT) applications composed of periodically scheduled tasks and (2) HRT applications with tasks scheduled according to a static off-line calculated schedule. The performance measurements on an implementation of two algorithms are presented.
COPLINK: managing law enforcement data and knowledge
Authors: Hsinchun Chen, Daniel Zeng, Homa Atabakhsh, Wojciech Wyzga, Jenny Schroeder
Venue: Communications of the ACM (2003)

In response to the September 11 terrorist attacks, major government efforts to modernize federal law enforcement authorities' intelligence collection and processing capabilities have been initiated. At the state and local levels, crime and police report data is rapidly migrating from paper records to automated records management systems in recent years, making them increasingly accessible.
An Experience Report on the Personal Software Process
Authors: Jagadish Kamatar, Will Hayes
Venue: IEEE Software (2000)

This article reports on the first author's experiences using the Personal Software Process for several years in the context of two industrial projects. This firsthand account covers training, initial use, and subsequent adoption of PSP techniques, including analysis of defect data and the corrective actions taken.
Algorithms and Average Time Bounds of Sorting on a Mesh-Connected Computer
Authors: Q. P. Gu, J. Gu
Venue: IEEE Transactions on Parallel and Distributed Systems (1994)

We give three new parallel sorting algorithms on a mesh-connected computer withwraparound connections (i.e. a torus). These three algorithms, with the minimum queuesize of 1, sort n/sup 2/ random input data items into a blocked snakelike row major order,a row major order, and a snakelike row major order, in 1.5n+o(n), 2n+o(n), and 2n+o(n)average steps, respectively. These results improve the previous results of 2n+o(n),2.5n+o(n), and 2.5n+o(n), respectively. In addition, we prove that the distance bound non a torus is an average-time lower bound independent of indexing schemes of sortingrandom input data items on it.
A model and methodologies for the location problem with logistical components
Authors: Siddhartha S. Syam
Venue: Computers and Operations Research (2002)

This paper significantly extends traditional facility location models by introducing several logistical cost components such as holding, ordering, and transportation costs in a multi-commodity, multilocation framework. Since location and logistical costs are highly inter-related, the paper provides an integrated model, and seeks to minimize total physical distribution costs by simultaneously determining optimal locations, flows, shipment compositions, and shipment cycle times. Two sophisticated heuristic methodologies, based on Lagrangian relaxation and simulated annealing, respectively, are provided and compared in an extensive computational experiment.
Predicting Where Faults Can Hide from Testing
Authors: Jeffrey Voas, Larry Morrel, Keith Miller
Venue: IEEE Software (1991)

Sensitivity analysis, which estimates the probability that a program location can hide a failure-causing fault, is addressed. The concept of sensitivity is discussed, and a fault/failure model that accounts for fault location is presented. Sensitivity analysis requires that every location be analyzed for three properties: the probability of execution occurring, the probability of infection occurring, and the probability of propagation occurring. One type of analysis is required to handle each part of the fault/failure model. Each of these analyses is examined, and the interpretation of the resulting three sets of probability estimates for each location is discussed. The relationship of the approach to testability is considered.
Writing development of Arab and Jewish students using cooperative learning (CL) and computer-mediated communication (CMC)
Authors: Rachel Hertz-Lazarowitz, Irit Bar-Natan
Venue: Computers Education (2002)

Writing has become central in today's schools as a measure for academic success. In this study 599 5th- and 6th-grade students, 210 Jews and 389 Arabs (310 boys and 289 girls), studied in three learning environments: cooperative learning (CL), computer-mediated communication (CMC), and the combination of CMC and CL. The students reported on their perception of and attitudes to writing. Their teachers evaluated their students as writers, and scored their portfolio writing outcomes. Measures included (1) students' perceptions of writing (SPWC), a 38-item self-report measure on writing apprehension, efficacy, self-regulation, and writing with computer derived from the study of writing; Alpha coefficient 0.90; (2) teachers' assessments of their students as writers (6 items);(3) portfolio evaluation. All students answered the SPWC twice in a pre-post test design in their first language (Arabic or Hebrew), and teachers gave their evaluation at the end of the year. Repeated measure of Manova was used for students' data and Anova for teachers' data. Findings using Multivariate repeated measures showed those students in CMC-CL scored higher on all measures. Teachers' evaluation was similar for CMC and the combined learning environment. Arab students were similar to Jewish students on some of the measures. Surprisingly, no differences were found for gender. The findings indicate that the power of peer interaction in cooperative learning with CMC was greater than each learning environment by itself. The quality implementation of these two (computer and peers) is the key element for students' writing development.
Intelligent Critic System for Architectural Design
Authors: Hon Wai Chun, Edmund Ming-Kit Lai
Venue: IEEE Transactions on Knowledge and Data Engineering (1997)

This paper describes an intelligent computer-aided architectural design system (ICAAD) called ICADS. ICADS encapsulates different types of design knowledge into independent "critic" modules. Each "critic" module possesses expertise in evaluating an architect's work in different areas of architectural design and can offer expert advice when needed. This research focuses on the representation of spatial information encoded in architectural floor plans and the representation of expert design knowledge. Described in this paper is our research in designing and developing two particular "critic" modules. The first module, FPDX, checks a residential apartment floor plan, verifies that the plan meets a set of government regulations, and offers suggestions for floor plan changes if regulations are not met. The second module, IDX, analyzes room and furniture layout according to a set of interior design guidelines and offers ideas on how furniture should be moved if the placement does not follow good design principles.