ppxscal/embedding_network huggingface dataset:
A framework for testing safety and effective computability of extended datalog
Authors: Ravi Krishnamurthy, Raghu Ramakrishnan, Oded Shmueli
Venue: Proceedings of the 1988 ACM SIGMOD international conference on Management of data (1988)

This paper presents a methodology for testing a general logic program containing function symbols and built-in predicates for safety and effective computability. Safety is the property that the set of answers for a given query is finite. A related issues is whether the evaluation strategy can effectively compute all answers and terminate. We consider these problems under the assumption that queries are evaluated using a bottom-up fixpoint computation. We also approximate the use of function symbols by considering Datalog programs with infinite base relations over which finiteness constraints and monotonicity constraints are considered. One of the main results of this paper is a recursive algorithm, check_clique, to test the safety and effective computability of predicates in arbitrarily complex cliques. This algorithm takes certain procedures as parameters, and its applicability can be strengthened by making these procedures more sophisticated. We specify the properties required of these procedures precisely, and present a formal proof of correctness for algorithm check_clique. This work provides a framework for testing safety and effective computability of recursive programs, and is based on a clique by clique analysis. The results reported here form the basis of the safety testing for the LDL language, being implemented at MCC.
Debugging of heterogeneous parallel systems
Authors: Alessandro Forin
Venue: ACM SIGPLAN Notices (1989)

The Agora system supports the development of heterogeneous parallel programs, e.g. programs written in multiple languages and running on heterogeneous machines. Agora has been used since September 1986 in a large distributed system [1]: Two versions of the application have been demonstrated in one year, contrary to the expectation of two years per one version. The simplicity in debugging is one of the reasons of the productivity speedup gained. This simplicity is due both to the deeper understanding that the debugger has of parallel systems, and to a novel feature: the ability to replay the execution of parallel systems built with Agora. A user is able to exactly repeat for any number of times and at a slower pace an execution that failed. This makes it easy to identify time-dependent errors, which are peculiar to parallel and distributed systems. The debugger can also be customized to support user defined synchronization primitives, which are built on top of the system provided ones. The Agora debugger tackles three set of problems that no parallel debugger in the past has simultaneously addressed: dealing with programming-in-the-large, multiple processes in different languages, and multiple machine architectures.
Practical performance of Bloom filters and parallel free-text searching
Authors: M. V. Ramakrishna
Venue: Communications of the ACM (1989)

Bloom filter technique of hashing finds several applications, such as in efficient maintenance of differential files, space efficient storage of dictionaries, and parallel free-text searching. The performance of hash transformations with reference to the filter error rate is the focus of this article.
Differential fault simulation - a fast method using minimal memory
Authors: W.-T. Cheng, M.-L. Yu
Venue: Proceedings of the 26th ACM/IEEE Design Automation Conference (1989)

A new, fast fault simulator called differential fault simulator, DSIM, for sequential circuits is described. Unlike the concurrent fault simulation, DSIM simulates each machine by simulating its machine differences from the other machine just simulated instead of simulating its input differences from the previous status of the same machine. In this manner, DSIM simulates each machine (good or bad) separately for every test vector. Therefore, DSIM dramatically reduces the dynamic memory requirement and the overhead in the memory management in the concurrent fault simulation. Also unlike the single fault propagation which simulates each bad machine by simulating its machine difference from the good machine, the overhead to restore the good machine status before each bad machine simulation is eliminated in DSIM. Our experiments show that DSIM runs 3-12 times faster than an existing concurrent fault simulator and an experimental single fault propagation simulator. Furthermore, owing to the straightforward operations, DSIM is very easy to implement and maintain. Implementation consists of less than 300 lines of &ldquo;C&rdquo; language statements added to the event-driven true-value simulator in an existing sequential test generation system, STG. Currently DSIM uses a zero-delay timing model, while inclusion of other delay models is under development.
A code optimization package for REDUCE
Authors: J. A. van Hulzen, B. J. Hulshof, B. L. Gates, M. C. van Heerwaarden
Venue: Proceedings of the ACM-SIGSAM 1989 international symposium on Symbolic and algebraic computation (1989)

A survey of the strategy behind and the facilities of a code optimization package for REDUCE are given. We avoid a detailed discussion of the different algorithms and concentrate on the user aspects of the package. Examples of straightforward and more advanced usage are shown.
Simple constant-time consensus protocols in realistic failure models
Authors: Benny Chor, Michael Merritt, David B. Shmoys
Venue: Journal of the ACM (JACM) (1989)

Using simple protocols, it is shown how to achieve consensus in constant expected time, within a variety of fail-stop and omission failure models. Significantly, the strongest models considered are completely asynchronous. All of the results are based on distributively flipping a coin, which is usable by a significant majority of the processors. Finally, a nearly matching lower bound is also given for randomized protocols for consensus.
DORUS: an architecture for dynamic optimal resource utilization systems
Authors: S. Ulug, B. A. Bowen, A. Acheson
Venue: Proceedings of the 2nd international conference on Industrial and engineering applications of artificial intelligence and expert systems - Volume 1 (1989)

A number of problems such as planning, scheduling and system maintenance have in common a dynamic set of resources and the need to optimize the use of these resources. The Dynamic Optimal Resource Utilization System (DORUS) is an architecture suitable for the construction of expert systems for these problem domains. It allows not only for dynamic data but for problem solving strategies which might change according to time or circumstance. A DORUS-based system will respond to a predefined set of events. Events may take the form of some change to the set of resources or the passage of time.When a response to an event is required, an appropriate goal is selected and resources are allocated according to a set of rules and heuristics. The set of rules which is activated is determined by the goal and current circumstances. The system is capable of generating a plan to implement the suggested allocation of resources. Finally, a DORUS-based system allows &ldquo;what if&rdquo; scenarios so that the consequences of unexpected events or alternative strategies can be explored.In this article we describe the DORUS architecture and present as an example an expert system for the reconfiguration management of flight data. Other potential applications are also discussed.
The design philosophy of the DARPA internet protocols
Authors: D. Clark
Venue: Symposium proceedings on Communications architectures and protocols (1988)

The Internet protocol suite, TCP/IP, was first proposed fifteen years ago. It was developed by the Defense Advanced Research Projects Agency (DARPA), and has been used widely in military and commercial systems. While there have been papers and specifications that describe how the protocols work, it is sometimes difficult to deduce from these why the protocol is as it is. For example, the Internet protocol is based on a connectionless or datagram mode of service. The motivation for this has been greatly misunderstood. This paper attempts to capture some of the early reasoning which shaped the Internet protocols.
Random Pattern Testing Versus Deterministic Testing of RAMs
Authors: Rene David, Antoine Fuentes, Bernard Courtois
Venue: IEEE Transactions on Computers (1989)

The number of (random) patterns required for random testing of RAMs (random-access memories), when classical fault models including pattern-sensitive faults are considered is determined. Markov chains are a powerful tool for this purpose. Single faults are considered first, and the influence of different parameters is analyzed. Double faults are then considered and arguments are presented to extend the results to all multiple-coupling faults. Those results are compared to the optimal or best-known number of test patterns required when deterministic testing is considered, for the same fault models.
Hardware Resources: a generalizing view on computer architectures
Authors: Wolfgang Matthes
Venue: ACM SIGARCH Computer Architecture News (1990)

Computer hardware is seen as a collection of resources. Performance, functional capabilities, and quantity of these resources are decisive to overall system performance.Starting from this paradigm, computer architecture design may be handled systematically in the future even by formalized methods.
Message driven computing and its relationship to actors
Authors: T. W. Christopher
Venue: ACM SIGPLAN Notices (1989)

We define Message Driven Computation as a style of computing with two characteristics: 1) Messages, not sequential processes, convey both control and data. Indeed, there are no sequential processes unless they are programmed explicitly in terms of messages. 2) Computation is invoked by the presence of a collection of messages at the same location. MDC may be viewed as a generalization of Actors [AGHA86]. MDC - Message Driven Computing MDC is based on message passing to named locations at which both data storage and computation is performed. Messages are sent to labeled message queues called portals. A locus is a named collection of portals. Messages are not sent or received by processes; rather, a collection of messages at a locus that match a pattern will trigger the execution of a procedure. These pattern-invoked procedures are called behaviors. The execution of a behavior can send further messages. There are two kinds of patterns currently provided for triggering behaviors. 1) A specified number of messages at each of several specified portals at the same locus can trigger a behavior. 2) A message arriving at a specified portal of a locus can trigger a behavior if that locus has no other messages at any of its portals. The contents of the messages are not examined in either pattern match. A locus is named by an arbitrary tuple of information. The first component is required to be a symbol, an internally generated value used somewhat like a pointer. All loci whose names begin with the same symbol are typically considered to be components of the same distributed object. Moreover, a garbage collector can collect all loci whose names cannot be generated again because no active computation has access to their initial symbol. A locus will occupy one node of a multi-computer. The node number may be calculated from the locus name by a user specified formula or by hashing if no other method is specified. A locus is created when a message arrives at it and vanishes when no further messages are present or the garbage collector discovers it can no longer be active. Similarly, portals are created at loci when messages arrive at them. A portal name is constructed out of a locus name and a portal label.
A Prototyping Language for Real-Time Software
Authors: Luqi, V. Berzins, R. T. Yeh
Venue: IEEE Transactions on Software Engineering (1988)

PSDL is a language for describing prototypes of real-time software systems. It is most useful for requirements analysis, feasibility studies, and the design of large embedded systems. PSDL has facilities for recording and enforcing timing constraints, and for modeling the control aspects of real-time systems using nonprocedural control constraints, operator abstractions, and data abstractions. The language has been designed for use with an associated prototyping methodology. PSDL prototypes are executable if supported by a software base containing reusable software components in an underlying programming language (e.g. Ada).
Scrambled storage for parallel memory systems
Authors: D. Lee
Venue: ACM SIGARCH Computer Architecture News (1988)

A scrambled storage scheme is proposed for storing arrays of NXN elements in N = 2n parallel memory modules to allow conflict-free access to various array partitions. It is shown that the scheme allows conflict-free access to rows, columns, square blocks, and distributed blocks of stored arrays. An alternative way of achieving the desired accessibility would use Budnik and Kuck's nonuniform skewed storage [3]; in this case, addressing hardware would require &Ogr;(nX2n) exclusive-or circuits. The proposed scheme has, however, the advantage of simplifying address generation; addressing hardware requires n exclusive-or circuits only. Some of the important questions of scrambling/unscrambling data through a proposed interconnection network are discussed.
The Monarch Parallel Processor Hardware Design
Authors: Randall D. Rettberg, William R. Crowther, Philip P. Carvey, Raymond S. Tomlinson
Venue: Computer (1990)

The Monarch architecture team took advantage of custom VLSI in the design of a shared-memory parallel processor. The simple structure eases the task of programming a massively parallel machine.
A model for concurrency in nested transactions systems
Authors: Catriel Beeri, Philip A. Bernstein, Nathan Goodman
Venue: Journal of the ACM (JACM) (1989)

Today's standard model for database concurrency control, called serializability theory, represents executions of transactions as partial orders of operations. The theory tells when an execution is serializable, that is, when the set of operations of a transaction execute atomically with respect to those of other transactions. It has been used successfully to prove correctness of most database concurrency control algorithms. Its most serious limitation is its inability to represent nested computations conveniently. This paper presents a more general model that permits nested transactions. In this model, transactions may execute subtransactions, giving rise to tree-structured computations. A serializability theory is developed for this model, which can be used to prove the correctness of concurrency control algorithms for nested transactions and for multilevel database systems. The theory is based on an abstract model of computation that allows arbitrary operations, and parallel and even nondeterministic programs. Axioms are presented that express the basic properties that programs that manage or access data need to satisfy. We use these axioms to derive proof techniques. One new technique&mdash;substitution&mdash;shows the equivalence of two executions by substituting one subcomputation by another, usually shallower (i.e., less nested), one. Our proof techniques are illustrated by applying them to several well-known concurrency control problems.
An efficient implemenatation of string pattern matching machines for a finite number of keywords
Authors: J. I. Aoe
Venue: ACM SIGIR Forum (1989)

This paper describes a method of implementing a static transition table of a string pattern matching machine to locate all occurrences of a finite number of keywords in a text string. The scheme combines the fast access of an array representation with the compactness of a list structure. Each transition can be computed from the present data structure in O(1) time and the storage is as small as the list structure. The construction and pattern matching programs associated with the present data structure are provided and the efficiency is evaluated by a empirical results.
Simulated annealing and resource location in computer networks
Authors: G. Anandalingam
Venue: Proceedings of the 21st conference on Winter simulation (1989)

This paper examines the problem of locating resources such as databases, controllers, and data processors on a computer network. The integer programming problem in location variables y and interconnection variables x is solved using two simulated annealing algorithms. Pure simulated annealing for this problem has complexity O(2N2+N). In hybrid simulated annealing (HSA), for fixed y, the problem in x becomes a special case of the transporation problem; the worst case solution for HSA is O(N.2N). In parallel simulated annealing (PSA), a decomposition procedure yields knapsack problems for x when y = 1, and x = 0 when y = 0; this is solved in O(Nk2N). Numerical results show that the computation time taken by the simulated annealing algorithms are comparable to a Lagrangian relaxation procedure, and the solutions are on the average within 8 % of a lower bound.
The effect of high school computer science, gender, and work on success in college computer science
Authors: Harriet G. Taylor, Luegina C. Mounfield
Venue: ACM SIGCSE Bulletin (1989)

Researchers have often linked factors such as mathematics ability and overall academic achievement to success in computer science. In this study, a group of students with common mathematics backgrounds was examined to determine if some other new factors were also involved in success in computer science. In particular, the roles of prior computing experience, work, and sex are discussed. A composite picture of the typical successful student is drawn and the implications for computer science departments are identified.
A homogeneous relational model and query languages for temporal databases
Authors: Shashi K. Gadia
Venue: ACM Transactions on Database Systems (TODS) (1988)

In a temporal database, time values are associated with data item to indicate their periods of validity. We propose a model for temporal databases within the framework of the classical database theory. Our model is realized as a temporal parameterization of static relations. We do not impose any restrictions upon the schemes of temporal relations. The classical concepts of normal forms and dependencies are easily extended to our model, allowing a suitable design for a database scheme. We present a relational algebra and a tuple calculus for our model and prove their equivalence. Our data model is homogeneous in the sense that the periods of validity of all the attributes in a given tuple of a temporal relation are identical. We discuss how to relax the homogeneity requirement to extend the application domain of our approach.
A single cached copy data coherence scheme for multiprocessor systems
Authors: A. Mendelson, D. K. Pradhan, A. D. Singh
Venue: ACM SIGARCH Computer Architecture News (1989)

We present and evaluate a snoopy cache memory protocol, the Single Cache Copy Data Coherence (SCCDC), for multiprocessors that allows only a single cache to hold a given share-d data at any time. The simulations presented here indicate that despite its simplicity, the scheme has the potential for good performance comparable with more complex snoopy cache schemes. We have also shown in related work [8] that the existence of only a single copy of data in cache allows efficient access control to shared data by minimizing the overh-ead caused by critical sections. Thus, with low implementation cost, and the efficient support for important operating system functions, the SCCDC scheme appears attractive for multi-user, multi-thread environments where the actual shared rate is modest, and mostly caused by synchronization mechanisms.
Future trends in electron beam testing
Authors: Eckhard Wolfgang
Venue: Microelectronic Engineering (1988)

Current trends in electron beam testing (EBT) are determined by those prevailing in microelectronics. This paper describes those aspects of microelectronics which have a particularly significant effect on EBT. Future trends in EBT are discussed against this background and on the basis of a description of state-of-the-art EBT systems. In its currently available, basic form, EBT can deal with the next two circuit generations, although interesting scopes still exist for improving the time resolution. A critical view must be taken of integration with computer-aided design (CAD) and computer-aided testing (CAT) where standardized interfaces are lacking.
Shape Description by Time Series
Authors: B. Kartikeyan, A. Sarkar
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1989)

Time series modeling techniques are adapted to represent or describe two-dimensional closed contours. Both linear and nonlinear models are fitted. It is found that to detect small changes in shape nonlinear modeling is necessary, even though linear models may be sufficient to differentiate between shapes which differ widely. A nonlinear model called the noncausal quadratic Volterra model is developed for the purpose. Implementation is illustrated with shapes of aircraft.
Performance evaluation of scientific programs on advanced architecture computers
Authors: D. W. Walker, D. W. Messina, C. F. Baillie
Venue: Proceedings of the third conference on Hypercube concurrent computers and applications: Architecture, software, computer systems, and general issues - Volume 1 (1988)

Recently a number of advanced architecture machines have become commercially available. These new machines promise better cost-performance then traditional computers, and some of them have the potential of competing with current supercomputers, such as the Cray X/MP, in terms of maximum performance. This paper describes an on-going project to evaluate a broad range of advanced architecture computers using a number of complete scientific application programs. The computers to be evaluated include (1) distributed-memory machines such as the NCUBE, INTEL and Caltech/JPL hypercubes, and the MEIKO computing surface, (2) shared-memory, bus architecture machines such as the Sequent Balance and the Alliant, (3) very long instruction word machines such as the Multiflow Trace 7/200 computer, (4) &ldquo;traditional&rdquo; supercomputers such as the Cray X/MP and Cray-2, and (5) SIMD machines such as the Connection Machine. Currently 11 application codes from a number of scientific disciplines have been selected, although it is not intended to run all codes on all machines. Results are presented for two of the codes (QCD and missile tracking), and future work is proposed.
Supporting reference and dirty bits in SPUR's virtual address cache
Authors: D. A. Wood, R. H. Katz
Venue: ACM SIGARCH Computer Architecture News (1989)

Virtual address caches can provide faster access times than physical address caches, because translation is only required on cache misses. However, because we don't check the translation information on each cache access, maintaining reference and dirty bits is more difficult. In this paper we examine the trade-offs in supporting reference and dirty bits in a virtual address cache. We use measurements from a uniprocessor SPUR prototype to evaluate different alternatives. The prototype's built-in performance counters make it easy to determine the frequency of important events and to calculate performance metrics. Our results indicate that dirty bits can be efficiently emulated with protection, and thus require no special hardware support. Although this can lead to excess faults when previously cached blocks are written, these account for only 19% of the total faults, on average. For reference bits, a miss bit approximation, which checks the references bits only on cache misses, leads to more page faults at smaller memory sizes. However, the additional overhead required to maintain true reference bits far exceeds the benefits of a lower fault rate.
The National Applied Mathematics Laboratories of the National Bureau of Standards
Authors: John H. Curtiss
Venue: IEEE Annals of the History of Computing (1989)

This progress report covers the first five years of the existence of the National Applied Mathematics Laboratories.