ppxscal/embedding_network huggingface dataset:
Neural nets and alphabets: introducing students to neural networks
Authors: K. G. Schweller, A. L. Plagman
Venue: ACM SIGCSE Bulletin (1989)

Three student projects involving neural networks are described. The projects include recognizing handwritten letters of the alphabet, determining the orientation of an imaged line, and recognizing particular rooms of a house based on samples of furniture found in the rooms. All projects were run on a back propagation neural network program implemented in Modula-2. A description of the program is presented and a sample module for simulating the behavior of an OR gate is included as an appendix. The program has been successfully used in several Artificial Intelligence classes for classroom demonstrations and carrying out various cognitive science experiments.
On the Detection of Dominant Points on Digital Curves
Authors: C. H. Teh, R. T. Chin
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1989)

A parallel algorithm is presented for detecting dominant points on a digital closed curve. The procedure requires no input parameter and remains reliable even when features of multiple sizes are present on the digital curve. The procedure first determines the region of support for each point based on its local properties, then computes measures of relative significance (e.g. curvature) of each point, and finally detects dominant points by a process of nonmaximum suppression. This procedure leads to the observation that the performance of dominant points detection depends not only on the accuracy of the measure of significance, but also on the precise determination of the region of support. This solves the fundamental problem of scale factor selection encountered in various dominant point detection algorithms. The inherent nature of scale-space filtering in the procedure is addressed, and the performance of the procedure is compared to those of several other dominant point detection algorithms, using a number of examples.
Row replacement algorithms for screen editors
Authors: Eugene W. Meyers, Webb Miller
Venue: ACM Transactions on Programming Languages and Systems (TOPLAS) (1989)

Interactive screen editors repeatedly determine terminal command sequences to update a screen row. Computing an optimal command sequence differs from the traditional sequence comparison problem in that there is a cost for moving the cursor over unedited characters and the cost of an n-character command is not always the cost of n one-character commands. For example, on an ANSI-standard terminal, it takes nine bytes to insert one character, ten to insert two, eleven to insert three, and so on. This paper presents an O(MN) dynamic programming algorithm for row replacement where an n-character command costs &agr;n + &bgr; for constants &agr; and &bgr;. M is the length of the original row and N is the length of its replacement. Also given is an O(Cost &times; (M + N)) &ldquo;greedy&rdquo; algorithm for optimal row replacement. Here Cost is the optimal cost (in bytes) of the replacement, so the algorithm is fast when the require d update is small. Though the algorithm is rather complicated, it is fast enough to be useful in practice.
Realistic compilation by program transformation (detailed summary)
Authors: R. Kelsey, P. Hudak
Venue: Proceedings of the 16th ACM SIGPLAN-SIGACT symposium on Principles of programming languages (1989)

Using concepts from denotational semantics, we have produced a very simple compiler that can be used to compile standard programming languages and produces object code as efficient as that of production compilers. The compiler is based entirely on source-to-source transformations performed on programs that have been translated into an intermediate language resembling the lambda calculus. The output of the compiler, while still in the intermediate language, can be trivially translated into machine code for the target machine. The compilation by transformation strategy is simple: the goal is to remove any dependencies on the intermediate language semantics that the target machine cannot implement directly. Front-ends have been written for Pascal, BASIC, and Scheme and the compiler produces code for the MC68020 microprocessor.
A universal concurrent algorithm for plasma particle-in-cell simulation codes
Authors: P. C. Liewer, V. K. Decyk, J. M. Dawson, G. C. Fox
Venue: Proceedings of the third conference on Hypercube concurrent computers and applications - Volume 2 (1989)

We have developed a new algorithm for implementation of plasma particle-in-cell (PIC) simulation codes on concurrent processors. This algorithm, termed the universal concurrent PIC algorithm (UC-PIC), has been utilized in a one-dimensional electrostatic PIC code on the JPL Mark III Hypercube parallel computer. To decompose the problem using the UC-PIC algorithm, the physical domain of the simulation is divided into sub-domains, equal in number to the number of processors, such that all sub-domains have roughly equal numbers of particles. For problems with non-uniform particle densities, these sub-domains will be of unequal physical size. Each processor is assigned, a sub-domain, with nearest neighbor sub-domains assigned to nearest neighbor processors. Using this algorithm in the Mark III PIC code, the increase in speed in going from 1 to 32 processors for the dominant portion of code (push time, defined below) was 29, yielding a parallel efficiency of 90%. Although implemented on a hypercube concurrent computer, this algorithm should be also be efficient for PIC codes on other parallel architectures and on sequential computers where part of the data resides in external memory.
On the Recognition of Curved Objects
Authors: W. Eric Grimson
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1989)

The problem of determining the identity and pose of occluded objects from noisy data is examined. Previous work has shown that local measurements of the position and surface orientation of small patches of an object's surface may be used in a constrained search process to solve this problem, for the case of rigid polygonal objects using 2-D sensory data, or rigid polyhedral objects using 3-D data. The recognition system is extended to recognize and locate curved objects. The extension is done in two dimensions, and applies to the recognition of 2-D objects from 2-D data, or to the recognition of the 3-D objects in stable positions from 2-D data.
A schema for configuration management
Authors: T. C. Miller
Venue: ACM SIGSOFT Software Engineering Notes (1989)

Sun's Network Software Environment (NSE) provides configuration management services for engineering applications [1] [2] [3]. This paper describes the NSE and the object schema it was based on. It emphasizes the design decisions we made in constructing the system.
The pebble crurching model for load balancing in concurrent hypercube ensembles
Authors: J. Barhen, S. Gulati, S. S. Iyengar
Venue: Proceedings of the third conference on Hypercube concurrent computers and applications: Architecture, software, computer systems, and general issues - Volume 1 (1988)

The successful development of fifth generation systems require enormous computational capability and flexibility necessitating the ability to achieve operational responses in hard real-time through optimal resource utilization. This entails dynamically balancing the computational load among all the processing nodes in the system. We propose a graph-theoretic, receiver-initiated, distributed protocol for dynamic load balancing protocol in large-scale hypercube ensembles. Using attributed hypergraphs as the primary data structure for constraint modeling and dynamic optimization, we consider systems running precedence-constrained heterogeneous tasks. Fault Tolerance is ensured by incorporating an integrity check for the decision nodes and their subsequent reelection if needed. Simulation studies are used to evaluate the performance of the algorithm.
The parallel decomposition and implementation of an integrated circuit global router
Authors: Jonathan Rose
Venue: Proceedings of the ACM/SIGPLAN conference on Parallel programming: experience with applications, languages and systems (1988)

Better quality automatic layout of integrated circuits can be obtained by combining the placement and routing phases so that routing is used as the cost function for placement optimization. Conventional routers are too slow to make this feasible, and so this paper presents a parallel decomposition and implementation of an integrated circuit global router. The LocusRoute router is divided into three orthogonal &ldquo;axes&rdquo; of parallelism: routing several wires at once, routing segments of a wire in parallel, and dividing up the potential routes of a segment among different processors to be evaluated. The implementation of two of these approaches achieve significant speedup - wire-by-wire parallelism attains speedups from 6.9 to 13.6 using sixteen processors, and route-by-route achieves up to 4.6 using eight processors. When combined, these approaches can potentially provide speedups of as much as 55 times.
Process control and scheduling issues for multiprogrammed shared-memory multiprocessors
Authors: A. Tucker, A. Gupta
Venue: Proceedings of the twelfth ACM symposium on Operating systems principles (1989)

Shared-memory multiprocessors are frequently used in a time-sharing style with multiple parallel applications executing at the same time. In such an environment, where the machine load is continuously varying, the question arises of how an application should maximize its performance while being fair to other users of the system. In this paper, we address this issue. We first show that if the number of runnable processes belonging to a parallel application significantly exceeds the effective number of physical processors executing it, its performance can be significantly degraded. We then propose a way of controlling the number of runnable processes associated with an application dynamically, to ensure good performance. The optimal number of runnable processes for each application is determined by a centralized server, and applications dynamically suspend or resume processes in order to match that number. A preliminary implementation of the proposed scheme is now running on the Encore Multimax and we show how it helps improve the performance of several applications. In some cases the improvement is more than a factor of two. We also discuss implications of the proposed scheme for multiprocessor schedulers, and how the scheme should interface with parallel programming languages.
Cost-effective design of application specific VLIW processors using the SCARCE framework
Authors: H. Mulder, R. J. Portier
Venue: ACM SIGMICRO Newsletter (1989)

Increasing the performance of application-specific processors by exploiting application-resident parallelism is often prohibited by costs; especially in the case of low-volume productions. The flexibility of horizontal-microcoded machines allows these costs to be reduced, but the flexibility often reduces efficiency. VLIW is a new and promising concept for the design of low-cost, high-performance parallel computer systems. We suggest that the VLIW concept can also be used as a basis for cost-effective design of application-specific processors which must exploit application-resident parallelism. The SCARCE (SCalable ARChitecture Experiment) framework, an approach for cost-effective design of application-specific processors, provides features which allow the design of retargetable VLIW architectures. However, a retargetable VLIW architecture is only effective if there is a retargetable VLIW compiler. Since a VLIW compiler is an essential part of the VLIW architecture, tradeoffs must be made between the variety of VLIW architectures and the compiler complexity. We suggest that limiting the flexibility of the retargetable VLIW architecture does not necessary reduce the application space. This paper discusses the issues related to the design of a retargetable VLIW processor architecture and compiler within the SCARCE framework.
Relational database behavior: utilizing relational discrete event systems and models
Authors: Z. M. Kedem, A. Tuzhilin
Venue: Proceedings of the eighth ACM SIGACT-SIGMOD-SIGART symposium on Principles of database systems (1989)

Behavior of relational databases is studied within the framework of Relational Discrete Event Systems (RDE-Ses) and Models (RDEMs). Production system and recurrence equation RDEMs are introduced, and their expressive powers are compared. Non-deterministic behavior is defined for both RDEMs and the expressive power of deterministic and non-deterministic production rule programs is also compared. This comparison shows that non-determinism increases expressive power of production systems. A formal concept of a production system interpreter is defined, and several specific interpreters are proposed. One interpreter, called parallel deterministic, is shown to be better than others in many respects, including the conflict resolution module of OPS5.
Performance evaluation of on-chip register and cache organizations
Authors: R. J. Eickenmeyer, J. H. Patel
Venue: ACM SIGARCH Computer Architecture News (1988)

Chip area is a critical resource in the design of VLSI processors. There are many different alternative designs that could fill this chip area. This paper compares several different local memory organizations applicable for single-chip processors. Several cache types&mdash;instruction, data, split, unified, stack, top-of-stack&mdash;are considered. These are compared to multiple register set architectures to which various caches can also be added. The performance metric of interest is effective access time, since a wide variety of register and cache organizations are used. A model for access time and a model for chip area required for each organization form the basis for comparison. Extensive simulations of several register-memory organizations are presented. Address traces from a VAX-11/780 running systems programs were used in the simulation.
Fragmentation considered harmful
Authors: C. A. Kent, J. C. Mogul
Venue: Proceedings of the ACM workshop on Frontiers in computer communications technology (1987)

Internetworks can be built from many different kinds of networks, with varying limits on maximum packet size. Throughput is usually maximized when the largest possible packet is sent; unfortunately, some routes can carry only very small packets. The IP protocol allows a gateway to fragment a packet if it is too large to be transmitted. Fragmentation is at best a necessary evil; it can lead to poor performance or complete communication failure. There are a variety of ways to reduce the likelihood of fragmentation; some can be incorporated into existing IP implementations without changes in protocol specifications. Others require new protocols, or modifications to existing protocols.
An Empirical Analysis of the Lilith Instruction Set
Authors: Robert P. Cook
Venue: IEEE Transactions on Computers (1989)

A static analysis of the instructions used to implement all of the system software on the Lilith computer is described. The results are compared to those of a similar analysis performed on the Mesa instruction set architecture. The data provide a good illustration of how code generation strategies and language usage can affect opcode statistics, even for machines with similar architectures.
Tuning architecture at run-time
Authors: E. Luque, T. Sorribes, A. Ripoll
Venue: ACM SIGMICRO Newsletter (1988)

We describe the structure and operational mode of a coprocessor system which, when incorporated in a microprogrammed syetem to carry out Dynamic Vertical Migration, improves execution speed for any program. The coprocessor includes an interconnection mechanism between the machine code and the instruction set microcode. The interconnections (Intermediate instructions) are created in parallel with machine instruction execution and so do not increase normal execution time. This intermediate code is stored dynamically in coprocessor memory, saving the fetching and decoding phases in subsequent executions, speeding up the execution of repetitive machine code.The coprocessor structure is organized around three basic elements: Interconnection Memory, Interconnection Memory Management Unit and Coprocessor Control Unit. A software simulator has been developed to analyse coprocessor behaviour and a theoretical model has been formulated from the results ot these analyses.
A framework for effective retrieval
Authors: C. T. Yu, W. Meng, S. Park
Venue: ACM Transactions on Database Systems (TODS) (1989)

The aim of an effective retrieval system is to yield high recall and precision (retrieval effectiveness). The nonbinary independence model, which takes into consideration the number of occurrences of terms in documents, is introduced. It is shown to be optimal under the assumption that terms are independent. It is verified by experiments to yield significant improvement over the binary independence model. The nonbinary model is extended to normalized vectors and is applicable to more general queries. Various ways to alleviate the consequences of the term independence assumption are discussed. Estimation of parameters required for the nonbinary independence model is provided, taking into consideration that a term may have different meanings.
The Transduction Method-Design of Logic Networks Based on Permissible Functions
Authors: S. Muroga, Y. Kambayashi, H. C. Lai, J. N. Culliney
Venue: IEEE Transactions on Computers (1989)

Based on the new concept of permissible functions, a heuristic procedure to design logic networks with as few gates as possible, without guaranteeing the minimality of designed networks, is developed. This procedure, which is drastically different from conventional logic-design procedures, is called the transduction method, because an initial network designed by any conventionally known logic-design method is first transformed into a different network configuration and then reduced to a simpler network by calculating permissible functions at the outputs of gates and connections throughout the network.
Reliability Estimation of Fault-Tolerant Systems: Tools and Techniques
Authors: Robert Geist, Kishor S. Trivedi
Venue: Computer (1990)

A comparative evaluation of state-of-the-art tools and techniques for estimating the reliability of fault-tolerant computing systems is presented. The theory of reliability estimation is briefly reviewed. Five current approaches are compared in detail: HARP (hybrid automated reliability predictor), SURE (semi-Markov unreliability range estimator), HEIRESS (hierarchical estimation of interval reliability by skewed sampling), SHARPE (symbolic hierarchical automated reliability and performance evaluator), and SAVE (system availability estimator). Particular attention is given to design limitations imposed by underlying model assumptions, on the one hand, and the efficiency and accuracy of the solution techniques employed, on the other hand.
On accessing object-oriented databases: expressive power, complexity, and restrictions
Authors: Richard Hull, Jianwen Su
Venue: ACM SIGMOD Record (1989)

A formal framework for studying the expressive power and complexity of OODB queries is developed. Three approaches to modeling sets are articulated and compared. The class of regular OODB schemas supports the explicit representation of set-valued types. Using an object-based semantics for sets, the regular schemas correspond to most implemented OODB systems in the literature; a value-based semantics for sets is also introduced. Without restrictions, both of these approaches support the specification of all computable queries. Assuming that the new operator is prohibited, the query language of the regular OODB schemas under the object-based semantics is complete in PSPACE; and under the value-based semantics it has hyper-exponential complexity. The third approach to modeling sets is given by the algebraic OODB model, in which multi-valued attributes rather than set-valued types are supported. method implementations can use operators stemming from the relational algebra, and do not have side-effects. The query language of algebraic OODBs is more powerful than the relational algebra but has complexity bounded by PTIME. The expressive power and complexity of data access for other variations of OODBs are also considered. Finally, a new relational query language, called algebra + pointwise recursion, is introduced. This is equivalent to the algebraic OODB language, and can compute generalized transitive closure.
Threshold Superposition in Morphological Image Analysis Systems
Authors: P. Maragos, R. D. Ziff
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1990)

It is shown that four composite morphological systems, namely morphological edge detection, peak/valley extraction, skeletonization, and shape-size distributions obey a weak linear superposition, called threshold-linear superposition. The output image signal or measurement from each system is shown to be the sum of outputs due to input binary images that result from thresholding the input gray-level image at all levels. These results are generalized to a vector space formulation, e.g. to any finite linear combination of simple morphological systems. Thus many such systems processing gray-level images are reduced to corresponding binary image processing systems, which are easier to analyze and implement.
Multiparty Interactions for Interprocess Communication and Synchronization
Authors: M. Evangelist, N. Francez, S. Katz
Venue: IEEE Transactions on Software Engineering (1989)

The authors consider the essential properties of a multiparty interaction construct which serves as a primitive for interprocess communication and synchronization in distributed programs. It is claimed that more general constructs, which violate the suggested properties, are appropriate for abstraction but should not be seen as a communication primitive, and that both facilities are needed. Several acceptability criteria are posed for multiparty interactions, and various possibilities for constructs satisfying these criteria are presented. These include introducing a novel kind of nondeterminism within the assignments of an interaction, weakening the synchronization among the participants in an interaction, and varying the number of participants in order to provide a high-level treatment of fault tolerance.
Knowledge acquisition in a machine fault diagnosis shell
Authors: M. Krishnamurthi, A. J. Underbrink,  Jr.
Venue: Issue 108 (April 1989) (1989)

The knowledge acquisition tools and techniques discussed in the literature deal primarily with the acquisition of human expertise applied in a particular problem domain. The acquired expertise generally includes both the decision making strategies of the human expert and the descriptions of the application problem. This acquisition process can become quite repetitive and time consuming when developing a number of application expert systems which use similar problem solving expertise but differ only in their application details. In this paper, we address this issue by discussing the details of the knowledge acquisition system we have designed and developed for use in a customized machine fault diagnosis shell. The knowledge acquisition system functions as a module of the diagnosis shell and acquires details of application machinery for which diagnosis expert systems are to be developed. The acquired application specific knowledge is combined in the shell with predefined generalized diagnosis strategies and application diagnosis expert systems are rapidly generated. The designed knowledge acquisition system has been implemented using Lisp on the Symbolic Lisp machine and has been validated by acquiring and verifying the design descriptions of a Cincinnati Milacron 786 robot. In this paper, the issues related to the development of a knowledge acquisition system for a customized problem solving shell, such as the machine fault diagnosis shell, and the details of the implemented knowledge acquisition system are discussed.