ppxscal/embedding_network huggingface dataset:
Compiler Techniques for Managing Data Motion
Authors: John S. Pieper
Venue:  (2001)

Software caching, automatic algorithm blocking, and data overlays are different names for the same problem: compiler management of data movement throughout the memory hierarchy. Modern high-performance architectures often omit hardware support for moving data between levels of the memory hierarchy: iWarp does not include a data cache, and Cray supercomputers do not have virtual memory. These systems have effectively traded a more complicated programming model for performance by replacing a hardware-controlled memory hierarchy with a simple fast memory. The simpler memories have less logic in the ciritical path, so the cycle time of the memories is improved. For programs which fit in the resulting memory, the extra performance is great. Unfortunately, the driving force behind supercomputing today is a class of very large scientific problems, both in terms of computation time and in terms of the amount of data used. Many of the programs do no fit in the memory of the machines available. When architects trade hardware support for data migration to gain performance, control of the memory hierarchy is left to the programmer. Either the program size must be cut down to fit into the machine, or every loop which accesses more data than will fit into memory must be restructured by hand. This thesis describes how a compiler can relieve the programmer of this burden, and automate data motion throughout the memory hierarchy without direct hardware support. This work develops a model of how data is accessed within a nested loop by typical scientific programs. It describes techniques which can be used by compilers faced with the task of managing data motion. The concentration is on nested loops which process large data arrays using linear array subscripts. Because the array subscripts are linear functions of the loop indices and the loop indices form an integer lattice, linear algebra can be applied to solve many compilation problems. The approach is to tile the iteration space of the loop nest. Tiling allows the compiler to improve locality of reference. The tiling basis matrix is chosen from a set of candidate vectors which neatly divide the data set. The execution order of the tiles is selected to maximiza locality between tiles. Finally, the tile sizes are chosen to minimize execution time. The approach has been applied to several common scientific loop nests: matrix-matrix multiplication, QR-decomposition, and LU-decomposition. In addition, an illustrative example from the Livermorre Loop benchmark set is explained. Although more compiler time can be required in some cases, this technique produces better code at no cost for most programs. The ACM Portal is published by the Association for Computing Machinery. Copyright © 2010 ACM, Inc. Terms of Usage Privacy Policy Code of Ethics Contact Us Useful downloads: Adobe Acrobat QuickTime Windows Media Player Real Player
FBSF: a new fast packet switching fabric based-on multistage interconnection network with multiple outlets
Venue: Proceedings of the 1996 International Symposium on Parallel Architectures, Algorithms and Networks (1996)

In this paper, we propose a new ATM switch architecture with output queueing. The proposed switch, FBSF (FAB Banyan Switching Fabrics) can deliver up to 2r packets simultaneously destined for the same outlet in a single time slot. The switch fabrics consists of Batcher sorter, a radix-r double shuffle network, r-packet distributors, two FAB networks, and output buffer modules. The performance of the switch fabric is evaluated by measures of throughput, average queue length, and average waiting time. Numerical results indicate that the switch exhibits very good delay-throughput performance over a wide range of input traffic.
A computational mechanism for parallel problem decomposition during requirements engineering
Authors: N. A. M. Maiden, A. G. Sutcliffe
Venue: Proceedings of the 8th International Workshop on Software Specification and Design (1996)

The earliest phases of requirements engineering capture large amounts of diverse facts about the problem domain. These facts must be structured according to useful decompositions of that problem domain. Existing goal oriented decompositions methods do not address issues specific to such decomposition. The paper outlines a tentative model of parallel problem domain decomposition, and describes a computational mechanism for achieving it. The mechanism accesses a set of problem abstractions produced as part of the ESPRIT III 6353 'NATURE' basic research action.
Fault-tolerant multicast with traffic-balancing in hypercubes
Venue: Proceedings of the 1996 International Symposium on Parallel Architectures, Algorithms and Networks (1996)

Multicast is an important interprocessor communication pattern existing in various parallel application algorithms. This paper proposes a new multicast algorithm for hypercube computers that not only minimizes the number of hops required for delivery of the message and keeps a least possible amount of traffic, but also takes into consideration of balancing traffic among the active processors to maximize the parallelism in communication. Our algorithm has a time complexity of O(nN) for fault-tolerant multicasting in a hypercube of N=2/sup n/ processors containing an arbitrary number of faulty processors.
Geometric Bicriteria Optimal Path Problems
Authors: Christine D Piatko
Venue:  (1995)

A bicriteria optimal path simultaneously satisfies two bounds on two measures of path quality. The complexity of finding such a path depends on the particular choices of path quality. This thesis studies bicriteria path problems in a geometric setting using several pairs of path quality, including: path length measured according to different norms ($L_{p}$ and $L_{q}$); Euclidean length within two or more classes of regions; total turn and Euclidean length; total turn and number of links; and Euclidean length and number of links. For several cases, finding the bicriteria optimal path is shown to be NP-hard. These NP-hard cases include minimizing path length in two different norms, minimizing travel through two regions, and minimizing length and total turn. In the last case, an $O(En^{2}N^{2})$ pseudo-polynomial time algorithm to find an approximate answer is presented. In contrast, when the two measures of path quality are total turn and number of links, an $O(E^{3}n \log^{2} n)$ exact algorithm is given. A main result of this thesis examines minimizing the Euclidean length and number of links of a path. When the geometric setting of this problem is a polygon without holes, this thesis presents an $O(n^{3}k^{3} \log(N k/ \epsilon^{1/k}) )$ algorithm to find a $k$-link path with Euclidean length at most $1+\epsilon$ times the length of the shortest $k$-link path. A faster algorithm for a relaxed case, when the output path is allowed to have $2k$ links, is presented for a polygon with or without holes. Finally, some approximation algorithms are outlined for finding a minimum link path among polyhedral obstacles.
State Equivalences for Rectangular Hybrid Automata
Authors: Thomas A. Henzinger, Peter W. Kopke
Venue:  (1996)

Three natural equivalence relations on the infinite state space of a hybrid automaton are language equivalence, simulation equivalence, and bisimulation equivalence. When one of these equivalence relations has a finite quotient, certain model checking and controller synthesis problems are decidable. When bounds on the number of equivalence classes are obtained, bounds on the running times of model checking and synthesis algorithms follow as corollaries. We characterize the time-abstract versions of these equivalence relations on the state spaces of rectangular hybrid automata (RHA), in which each continuous variable is a clock with bounded drift. These automata are useful for modeling communications protocols with drifting local clocks, and for the conservative approximation of more complex hybrid systems. Of our two main results, one has positive implications for automatic verification, and the other has negative implications. On the positive side, we find that the (finite) language equivalence quotient for RHA is coarser than was previously known by a multiplicative exponential factor. On the negative side, we show that simulation equivalence for RHA is equality (which obviously has an infinite quotient). Our main positive result is established by analyzing a subclass of timed automata, called one-sided timed automata (OSA), for which the language equivalence quotient is coarser than for the class all of timed automata. An exact characterization of language equivalence for OSA requires a distinction between synchronous and asynchronous definitions of (bi)simulation: if time actions are silent, then the induced quotient for OSA is coarser than if time actions are visible.
Efficient Bridging Fault Simulation of Sequential Circuits Based on Multi-Valued Logics
Authors: Ilia Polian, Piet Engelke, Bernd Becker
Venue: Proceedings of the 32nd International Symposium on Multiple-Valued Logic (2002)

We present the concept of a multi-valued logic simulator forbridging faults in sequential circuits. Different models for thehandling of intermediate values in flip-flops on the digital designlevel can be integrated and result in an Expected realisticbehavior area for bridging faults. Several experimental resultsare given to underline properties and advantages of the simulationtechnique.
MCAD/MCSD Visual Basic .Net Windows Applications: Exam 70-306 with Cdrom, 1 edition
Authors: David Panagrosso, Kenneth S. Lind, Lyle A. Bryant
Venue:  (2002)

:The only classroom-based training and self-assessment system! Osborne's MCSD Visual Basic .NET Windows Applications Study Guide provides 100% complete coverage of all objectives for exam 70-306. Based on 300,000+ hours of IT training experience, the book contains hundreds of practice exam questions and hands-on exercises. The CD-ROM features full practice exam software with interactive tutorials and lab simulations, plus an adaptive test engine.
A nonlinear input-output model of intracellular thiamine kinetics
Authors: Bellazzi R
Venue:  (2000)

Critical to structural modelling of the intracellular thiamine kinetics in the intestine tissue is the incomplete knowledge of the intrinsic nonlinearity of the absorption process from plasma to cells as well as the paucity of the available experimental data. The latter cause may be also responsible for the failure of traditional black-box modelling approaches. This paper deals with a novel hybrid modelling framework which builds on the qualitative structural knowledge a good initialization of an approximation scheme of the nonlinear functional relationship between the input-output variables. Such an initialization allows us to efficiently cope with the poor data set and to derive an input-output model of the intracellular thiamine kinetics in the intestine tissue. Although the structural assumptions are relaxed and only a descriptive quantitative knowledge may be derived, the model obtained is robust enough to be used as a simulator. The interpretative potential of the model derived has been tested on diabetic subjects. The ACM Portal is published by the Association for Computing Machinery. Copyright © 2010 ACM, Inc. Terms of Usage Privacy Policy Code of Ethics Contact Us Useful downloads: Adobe Acrobat QuickTime Windows Media Player Real Player
DPL: A Language for Instruction in Concepts Basic to Data Processing and Management Information Systems
Authors: Howard L. Morgan
Venue:  (1968)

NO SUPPLIED
A Numerical Comparative Analysis of Partitioning Heuristics for Scheduling Tak Graphs on Multiprocessors
Authors: A. A. Khan, C. L. McCreary, Y. Gong
Venue:  (1993)

Many algorithms for scheduling DAGs on multiprocessors have been proposed, but there has been little work done to determine their effectiveness. Since multiprocessor scheduling is an NP-hard problem, no exact tractable algorithm exists, and no baseline is available from which to compare the resulting schedules. Furthermore, performance guarantees have been found for only a few simple DAGs. This paper is an attempt to quantify the differences in a few of the heuristics. New classification criteria are defined for the DAGs, and the differences between the heuristics are noted for various criteria. The comparison is made between a graph based method, and two critical path methods. The empirical performance of the three heuristics is compared when they are applied to the randomly generated DAGs.
Delete and insert operations in Voronoi/Delaunay methods and applications
Authors: Mir Abolfazl Mostafavi, Christopher Gold, Maciej Dakowicz
Venue: Computers Geosciences (2003)

This paper presents simple point insertion and deletion operations in Voronoi diagrams and Delaunay triangulations which may be useful for a wide variety of applications, either where interactivity is important, or where local modification of the topology is preferable to global rebuilding. While incremental point insertion has been known for many years, point deletion is relatively unknown. The robustness and efficiency of a new algorithm are described. A variety of potential applications are summarized, and the included computer program may be used as the basis for many new projects.
A New Proposal for RSVP Refreshes
Authors: Lan Wang, Andreas Terzis, Lixia Zhang
Venue: Proceedings of the Seventh Annual International Conference on Network Protocols (1999)

As a soft-state protocol, RSVP specifies that each RSVP node sends periodic control messages to maintain the state for active RSVP sessions. The protocol overhead due to such periodic messages grows linearly with the number of RSVP sessions. One may reduce the overhead by using a longer refresh period, which unfortunately leads to longer delays in re-synchronizing RSVP state.In this paper we introduce a novel ``state-compression'' approach to reducing the overhead of periodic refreshes. Instead of per session refresh messages, an RSVP node sends periodically to each of its neighbor node a Digest message that contains a compressed version of the entire RSVP state shared with that particular neighbor. In order to speed up state synchronization in face of message losses we also enhance RSVP with an acknowledgment mechanism. Our mechanisms achieve a constant message transmission overhead and low delay while retaining the soft-state nature of the RSVP protocol.
Conceptual Level Graph Theoretic Design and Development of Complex Information System
Authors: S. Choudhury, N. Chaki, S. Pramanik, S. Bhattacharya
Venue: Proceedings of the The International Conference on Information Technology: Coding and Computing (ITCC'00) (2000)

This paper introduces a graph-oriented model for conceptual level design of large, complex information systems. This has been shown to be highly effective to the system designer from the perspectives of maintainability and upgradability. Due to the flat structure and the lack of holding multidimensional data, the relational model does not provide a structural approach to the system designer. The other alternative object oriented model offer the structured approach but also not able to describe various intermodular relationships spread over same or different levels within a data model. The graph data model also allows dynamic regrouping of related entities at the designers' level. We have proposed the appropriate data structure and corresponding DDL has also been developed. Test runs on simulated environment further establish its computational efficiency.
Non-negative rational spline interpolation
Authors: M. Z. Hussain, M. Sarfraz, S. Butt
Venue: Proceedings of the IEEE Conference on Information Visualisation (1997)

Scientific visualization is one of the important areas of computer graphics. This paper is concerned with non-negative C/sup 1/-interpolation of non-negative data for visualization proposes. Using the rational cubic spline function of Sarfraz et al. (1997), necessary and sufficient conditions have been derived which ensure the generation of a non-negative curve through given non-negative data. In addition to the pleasant display, the scheme provides extra freedom to the users to play with the shape of the curve to modify it according to their desire. This is done through controlling the default curve within the derived constraints.
A New Look At Multimedia Synchronization in Distributed Environments
Authors: Zhonghua Yang, Chengzheng Sun, Abdul Sattar, Yanyan Yang
Venue: Proceedings of the 1999 International Symposium on Parallel Architectures, Algorithms and Networks (1999)

A multimedia system requires to handle automatically and uniformly the generation, manipulation, presentation, storage, and communication of independent discrete and continuous media data. The synchronization between various kinds of media data is a key issue in an integrated multimedia system, and has drawn a considerable attention. In this paper, we investigate the synchronization problem in distributed multimedia environments and propose a new approach. Based on a globally synchronized clock, we present an isochronous clock-driven protocol for multimedia synchronization in a distributed environment. We show that the isochronous approach is simple, easy to understand, and more importantly, can guarantee the temporal ordering (including causal order and $\Delta$-causal order).We believe that with the new developments in the improved NTP over Internet and very high accuracy of synchronized clocks over ATM and LANs, the clock-based distributed synchronization would provide a promising, yet simple and intuitive, alternative to the existing approaches.
Iterative Symmetry Indices Decomposition for Ternary Logic Synthesis in Three-Dimensional Space
Authors: Anas N. Al-Rabadi
Venue: Proceedings of the 33rd International Symposium on Multiple-Valued Logic (2003)

This paper introduces the implementation ofthe Iterative Symmetry Indices Decomposition(ISID) for the synthesis of ternary three-dimensionallogic circuits. The synthesis of regulartwo-dimensional circuits using ISID has been introducedpreviously, and the synthesis of area-specificcircuits using ISID has been demonstrated.The new method is useful for the synthesis of functionsusing three-dimensional regular logic circuitswhenever volume-specific layout constraints haveto be satisfied.
Working with DVD Studio Pro
Authors: Mike Evangelist
Venue:  (2003)

:This book is the definitive guide on how to unleash the power of DVD Studio Pro to produce exciting, sophisticated DVD projects. It will supplement the user manual by focusing on the challenges that pros face everyday, revealing fast, efficient solutions, and providing workarounds and alternatives to the application's shortcomings. Real-world examples will help readers to learn about the most powerful features of the DVD medium, such as alternate soundtracks, scripting, and variables, and learn how to master the more complex aspects of DVD authoring, such as making disks that work on both wide and standard TVs, subtitling, and multiple angles and replication problems. The companion DVD features sample video and tutorial materials. The ACM Portal is published by the Association for Computing Machinery. Copyright © 2010 ACM, Inc. Terms of Usage Privacy Policy Code of Ethics Contact Us Useful downloads: Adobe Acrobat QuickTime Windows Media Player Real Player
A Tutorial Introduction to Mosaic Pascal
Authors: Johan J. Lukkien, Johan L. A. Van de Snepscheut
Venue:  (1992)

No abstract available.
Measuring HDL-based design productivity: an experimental comparison
Authors: M. Joshi, H. Kim, H. Kobayashi
Venue: Proceedings of the 4th IEEE International Verilog HDL Conference (1995)

Two process models for top-down HDL-based design are developed in order to measure HDL-based design productivity. A sorting algorithm is used as a benchmark to experience various design activities in HDL entry and mixed entry design process models. We measure the effort (time) required for each design activity and analyze the "effort-distribution" over various design activities. We also discuss the resources that are essential to perform each design activity. These experiments the applicability of "effort-distribution analysis" to enhance design productivity in real life design projects.
Automatic, Template-Based Run-Time Specialization: Implementation and Experimental Study
Authors: Francois Noel, Luke Hornof, Charles Consel, Julia L. Lawall
Venue: Proceedings of the 1998 International Conference on Computer Languages (1998)

Specializing programs with respect to run-time values has been shown to drastically improve code performance on realistic programs ranging from operating systems to graphics. Recently, various approaches to specializing code at run-time have been proposed. However, these approaches still suffer from shortcomings that limit their applicability: they are manual, too expensive, or require programs to be written in a dedicated language.We solve these problems by introducing new techniques to implement run-time specialization. The key to our approach is the use of code templates. Templates are automatically generated from ordinary programs and are optimized before run time, allowing high-quality code to be quickly generated at run time.Experimental results obtained on scientific and graphics code indicate that our approach is highly effective. Little run-time overhead is introduced, since code generation primarily consists of copying instructions. Run-time specialized programs run up to 10 times faster, and are nearly as fast as fully optimized programs (80% on average). The combination of low run-time overhead and high code quality enables specialization to be amortized in as few as 3 runs.Although this approach is highly effective, its implementation is relatively simple since it exploits existing partial evaluation and compiler technologies.
Parallel, distributed-memory implementation of sparse-grid methods for three-dimensional fluid-flow computations
Authors: C. T.H. Everaars, Farhad Arbab, Barry Koren
Venue:  (2000)

A workable approach for modernization of existing software into parallel/distributed applications is through coarse-grain restructuring. If, for instance, entire subroutines of legacy code can be plugged into a new structure, the investment required for the re-discovery of the details of what they do can be spared. The resulting renovated software can then take advantage of the improved performance offered by modern parallel/distributed computing environments, without rethinking or rewriting the bulk of their existing code. Our approach is simple and is in fact a cut-and-paste method. First we try to identify and isolate components in the legacy source code (the cut). Second, we glue them together by writing coordinator modules (glue modules) with the help of a coordination language (the paste). We have used Manifold as the glue language. Manifold is a general purpose coordination language developed at CWI (Centrum voor Wiskunde en Informatica) in the Netherlands and is specially designed to express cooperation protocols among components in component based systems. Our point of departure is two different pieces of existing sequential Fortran code from computational fluid dynamics (CFD). The first Fortran source code deals with a standard CFD problem solved with the so-called sparse-grid method and the other solves the same problem but now with the so-called semi-sparse-grid method. Applying our cut-and-paste method to these two programs results in {\em one} generally applicable coordinator module that can restructure both sequential programs into parallel applications (which now run on a shared memory machine) as well as distributed applications (which now run on a cluster of workstations). Before we give the actual restructuring of the two sequential programs, we first test the coordinator module with a simplified ``toy'''' example. We also give some performance results.