ppxscal/embedding_network huggingface dataset:
Learning from information systems failures by using narrative and ante-narrative methods
Authors: Darren Dalcher, Lynette Drevin
Venue: Proceedings of the 2003 annual research conference of the South African institute of computer scientists and information technologists on Enablement through technology (2003)

We see, know and experience information systems development failures in many domains and in many countries. This paper will explore some of the issues related to the study of these failures. Every year, billions of dollars are wasted on failed projects in developed countries. Developing countries can learn from these grim experiences so as not to waste precious resources in repeating similar failures. The paper will emphasise the fact that the study of failures can only take place post-hoc, once a failure has been identified. Preparation is therefore different to normal scientific study where a situation is pre-selected in advance, the precise parameters are identified and decisions are made about the best methods for measuring them accurately and objectively. The literature reveals that researchers and practitioners have been experiencing projects failures for many years. Indeed, acknowledgements of failures go back at least thirty-five years. However, failures are still a prevalent problem. A significant obstacle related to the study of failures is the lack of acknowledged research methods for understanding such complex phenomena. The evidence collected during failure investigations emerges from a variety of sources, perspectives and contexts. Not surprisingly, it often appears to be ambiguous, incoherent and confused. The information collected tends to be rich, messy, contradictory and subjective. Such situations call for a new repertoire of methods to address the unique features of failures. This paper will introduce possible alternative ways of looking at and constructing failure stories. The techniques described below come under the umbrella term <i>forensic analysis</i>. The insights obtained from forensic analysis can be used for internal learning within organisations as well as externally within the discipline, thereby enabling practitioners and developing countries to benefit from the mistakes of others.
Algorithms for large-scale problems in computational biology
Authors: Srinivas Aluru
Venue:  (2002)

Advancements in biological research have enabled researchers to obtain large amounts of data, especially on DNA and protein sequences. Algorithmic inventions to process biological data are necessary to match their increasing size. In this dissertation, we present algorithms for solving large-scale problems in sequence comparison, accessible surface area computation and string search. Comparison of long biological sequences is of interest due to the availability of long DNA sequences such as chromosomes, which may be up to several hundred million base pairs long. Sequence comparison algorithms take time proportional to the product of the input sequences. We considered constant and affine gap penalty functions, full-sequence and subsequence matching, syntenic alignments, and also developed space-saving algorithms. Our algorithms solve all these problems in optimal O mnp time, and O m+np space. Solvent accessible surface area (ASA) is used in determining the energy of protein molecules, and protein folding prediction using molecular dynamics simulation computes ASA repeatedly. Each atom in the protein is modeled as a sphere. Using domain specific knowledge, we show that the number of sphere intersections is O(n), where n is the number of atoms in the protein molecule. For computing sphere intersections, we present a hash-based algorithm that runs in O( n) expected sequential time and a sort-based algorithm that runs in worst-case O(n log n) sequential time. Optimal parallelization of both the algorithms are also presented. Our algorithms are a factor of n faster than currently known algorithms. We also present a Monte Carlo algorithm for computing the solvent accessible surface area, and provide error bounds as a function of the sample size. PATRICIA tree, suffix tree and suffix array are useful data structures for string search because the search time using them is only a function of the length of the pattern, and not the length of the text. We present a fast algorithm to construct PATRICIA trees. Our algorithm can construct a PATRICIA tree in O(n) expected running time and O mlogn worst-case running time, where n is the number of the strings indexed by PATRICIA tree and m is the sum of the length of all the strings. Finally, we present two fast string search algorithms using PATRICIA trees. One algorithm uses linear space and searches pattern p with length |p| in O p time when |p| = O wlog 2S 2 , where w is the number of bits a processor can process in unit time (typically w = 32), and O plog 2Sw time otherwise. The other algorithm uses O( n log2 |p|) space and searches a PATRICIA tree in O(log2 |p|) time when |p| = O wlog 2S .
A thermal management design for system-on-chip circuits and advanced computer systems
Authors: John Choma,  Jr.
Venue:  (2002)

Increases in circuit density and clock speed in modern VLSI designs have brought thermal issues into the spotlight of high-speed integrated circuit design. Local overheating in one spot of a high-density circuit, such as a CPU on high speed mixed-signal circuit, can cause a whole system to crash. Clock synchronization problems, parameter mismatching and other coefficient changes due to temperature gradients generated by uneven heat-up of on-chip circuitry are the major reasons for system failure. The early stage of this project has successfully characterized the local heat-up problem through an analytical model and test chip. The impact of temperature gradients on circuit behavior is also evaluated. Since the outcome of this analysis has proven the importance of this matter, a systematic solution to thermal management has been proposed. Instead of worst-case thermal management used in conventional systems, this design targets nominal power dissipation and requires the system to actively manage its thermal activity, including monitoring thermal activity and reacting to specified conditions through the control of cooling mechanisms, such as an integrated multi-stage fan controller, to ensure operation within specification. Continuing work includes further improvement in the circuit and architecture as well as analyzing and optimizing the performance of this design. The limitations and advantages by using this thermal management design are also assessed to establish guidelines for designing and analyzing modern system-on-chip designs, which are often limited by thermal factors because of inherent power density and sizes. The success of this project offers an opportunity for modern system-on-chip designs to incorporate thermal management techniques to enhance system stability and performance. This design yields intricate control and optimal management with little system overhead and minimum hardware requirements, as well as provides the flexibility to support different management algorithms.
PCI-DMA/CPU Handoff for Increased Effectiveness of Checkpointing Functionalities in CCL
Authors: Andrea Santoro, Francesco Quaglia
Venue: Proceedings of the Seventh IEEE International Symposium on Distributed Simulation and Real-Time Applications (2003)

Checkpointing and Communication Library (CCL) is a recently developed software in support of optimistic parallel discrete event simulation on myrinet clusters. Beyond low latency message delivery functionalities, CCL also offers non-blocking checkpointing functionalities supported by a programmable PCI DMA engine on board of myrinet cards. CCL employs a re-synchronization functionality between PCI DMA activities and CPU activities to maintainthe consistency of checkpointed information (i.e. to prevent the CPU from updating information that still needs to be copied through DMAing). If re-synchronization is invoked before the checkpoint operation is completed, simulation activities carried out by the CPU may be forced to wait for checkpoint completion. Since data copy through the PCI DMA is slower than what achievable with the CPU, in pathological situations a re-synchronization period maylast more than a whole checkpoint operation performed by the CPU, thus nullifying the potential benefit from offloading checkpointing from the CPU. This paper tackles such an issue by presenting the design and implementation of a handoff mechanism of checkpoint operations between PCI DMA and CPU to enhance the effectiveness of checkpointing functionalities offered by CCL. Although a checkpoint operation is initially entrusted to the PCI DMA, whenever re-synchronization forces the simulation application to wait for its completion, the checkpoint operation is dynamically switched to the CPU, namely the fastest available device, since its timely completion has become a performance critical task for the simulation application.
A low power approach to system level pipelined interconnect design
Authors: Vikas Chandra, Anthony Xu, Herman Schmit
Venue: Proceedings of the 2004 international workshop on System level interconnect prediction (2004)

System on Chip interconnects require first-in first-out buffers (FIFOs) to handle different data rates between IP cores. The design of an interconnect channel containing multiple stages of FIFO require making tradeoff between throughput and power consumption. The design variables are the sizes of the FIFOs, their voltages and their clock frequencies. Decreasing the FIFO clock frequencies saves power but it causes the channel performance (throughput) to decrease. In this work, we recover the performance by resizing the FIFOs in the channel. The voltage and clock scaling in the interconnect channel followed by FIFO resizing approach leads to significant power savings. The power savings is a function of system parameters λ (expected data production rate) and μ (expected data consumption rate). We observed a maximum dynamic power savings of 45.8%, 28.9% and 11.3% for min(λ, μ) of 0.2, 0.5 and 0.8 respectively. Our approach of reducing voltage in the interconnect channel will reduce the leakage power as well.
Arts'Codes: Generation of Parallel-Automata Real-Time Systems, using a Unifying Diagrammatic Component Oriented Design Methodology
Authors: A. Teitelbaum, H. G. Medelbaum
Venue: Proceedings of the IEEE International Conference on Software-Science, Technology & Engineering (2003)

We present a new method for real-time embeddedapplications development.The method includes graphicdesign (Codes), and an execution platform based onparallel automata (Arts).The design method and theexecution platform cooperate, so to win clarity in designand robustness in execution.In this paper we place our empasize on the designstage.We introduce new ideas in graphic design tocreate a framework for the developer in order to arrangehis/her thought.The graphic design was influenced byDiagrammatic Reasoning researches, and theirconclusions.The design is component oriented; it is hierarchicallyhomothetic and uses a minimum number of elements inorder to minimize cognitive efforts.It unifies in one sortof diagram, the architectural view and the behavioralview of the system to build.A case study is presented in order to picture themethod, and to compare the Arts'Codes method to otherrelated ones.
Rapid evaluation using multiple choice tests and TeX
Authors: Petr Sojka
Venue: Proceedings of the 8th annual conference on Innovation and technology in computer science education (2003)

This paper describes a framework for effective design, typesetting, use and evaluation of students that uses multiple-choice tests. With this approach, based on a TEX engine, macros and a small program, several hundred customized tests can be typeset, printed and evaluated within several hours, allowing significant savings of educator's time and rapid electronic dissemination of tests results.
Fully discrete random walks for space-time fractional diffusion equations
Authors: Rudolf Gorenflo, Alessandro Vivoli
Venue: Signal Processing (2003)

For space-time fractional diffusion equations a theory of discrete-space discrete-time random walks, analogous to the theory of continuous-time random walks, is presented. The essential assumption is that the probabilities for waiting times and jump-widths behave asymptotically like powers with negative exponents related to the orders of the fractional derivatives. Properly scaled passage to the diffusion limit then leads to the space-time fractional diffusion equation. Illustrating examples are given, numerical results and plots of simulations are displayed.
A Toolkit for Developing Web-based Information Systems: Case Studies
Authors: Thierry Bodhuin, Maria Tortorella
Venue: Proceedings of the 27th Annual International Conference on Computer Software and Applications (2003)

The widespread usage of Internet increases the need of web-basedsoftware applications for diffusing, searching andexchanging information useful to support a large variety ofactivities, such as business exchange, collaborative work,training, etc. The use of Internet allows the enterprises toexperiment new and more efficient organization models throughinnovative elements that simplify the communication among theirdifferent sites. This situation motivates the increasing need ofweb-based applications and calls for a quick development of newtools making easier the interaction with and/or between theenterprises' information systems.This paper briefly introduces an approach for a quickdevelopment of Web-based Information Systems by using atoolkit, named MVCGen, Model/View/Controller Generator. Thename exhibits that the software systems produced are based onthe Model-View-Controller design pattern. The paper presents aset of experiences regarding the automatic generation of Web-basedsoftware systems.
A Parallel Implementation of the LTSn Method for a Radiative Transfer Problem
Authors: Roberto P. Souto, Haroldo F. de Campos Velho, Stephan Stephany, Airam J. Preto, Cynthia F. Segatto, Marco T. Vilhena
Venue: Proceedings of the 15th Symposium on Computer Architecture and High Performance Computing (2003)

A radiative transfer solver that implements the LTSn method was optimized and parallelized using the MPI message passing communication library. Timing and profiling information was obtained for the sequential code in order to identify performance bottlenecks. Performance tests were executed in a distributed memory parallel machine, a multicomputer based on IA-32 architecture. The radiative transfer equation was solved for a cloud test case to evaluate theparallel performance of the LTSnmethod. The LTSn-code include spatial discretization of the domain and Fourier decomposition of the radiances leading to independent azimuthal modes. This yields an independent radiative transfer equation for each mode that can be executed by a different processor in a parallel implementation. Speed-up results show that the parallel implementation is suitable for the used architecture.
Experimenting with a Policy-Based HIDS Based on an Information Flow Control Model
Authors: Jacob Zimmerman, Ludovic Mé, Christophe Bidan
Venue: Proceedings of the 19th Annual Computer Security Applications Conference (2003)

In [1], we proposed a model for policy-based intrusiondetection, based on information flow control.Inthe present paper, we show its applicability and effectivenesson a standard OS.We present results of twoset of experiments, one carried out in a completely controlledenvironment, the other on an operational serverwith real network traffic.Our results results show thatthe model fulfills its goals and serves as a successfulruntime policy-based intrusion detector.
Attitude and management style matter in IT implementation: a study of small business owners
Authors: Elaine R. Winston, Dorothy G. Dologite
Venue: Advanced topics in end user computing (2003)

According to previous studies, a positive attitude towards information technology (IT) among small business owners appears to be a key factor in achieving high quality IT implementations. In an effort to extend this stream of research, case studies were conducted with small business owners. A surprising finding of this study was that high quality IT implementations resulted with owners who had either a positive or a negative attitude towards IT. Another finding was that these owners also all had an entrepreneurial, or shared, management style. By contrast, owners who had an uncertain attitude about IT uniformly practiced a traditional (non-entrepreneurial) management style. This group also uniformly had low quality IT implementations. It is proposed, based on case study data, that small business owners with an uncertain attitude towards IT might experience higher quality IT results in their organizations through practicing a more entrepreneurial, or shared, management style. The study provides insights for both computer specialists and small business owners planning IT implementations.
Compressing MIPS code by multiple operand dependencies
Authors: Kelvin Lin, Chung-Ping Chung, Jean Jyh-Jiun Shann
Venue: ACM Transactions on Embedded Computing Systems (TECS) (2003)

Intuitively, destination registers of some instructions have great possibilities to be used as the source registers of the immediately subsequent instructions. Such destination register/source register pairs have been exploited previously to improve code compression ratio [compression ratio = (Dictionary Size + Encoded Program Size)/Original Program Size]. This paper further examines the exploitation of both register and immediate operand dependencies to improve the compression ratio. A mapping tag is used to flag dependency relationships so that dependent operands can be omitted during compression. The compression ratio is enhanced by both the removal of dependent operands and the sharing of mapping tags between different types of dependencies and between different instructions. Simulation results show that the proposed method results in the best compression ratio achieved so far, giving average compression ratios of 33.8&percnt; for MediaBench benchmarks and 33.6&percnt; for SPEC95 benchmarks, both compiled for a MIPS R2000 processor.
Clock Calibration Faults and their Impact on Quality of High Performance Microprocessors
Authors: C. Metra, T. M. Mak, D. Rossi
Venue: Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (2003)

In this paper we analyze the fault effects of some clock calibration features which are common to today's high performance microprocessors. We will show that induced faults with such schemes may give rise to effects that are not detectable by common manufacturing testing (e.g., scan based). However, these faults could seriously impact the microprocessor correct operation, and result in a decrease of product quality. Similar considerations may apply to different microprocessor calibration features. Considering that there is a wide range of process variations on die, as well as across the process, and that Very Deep Sub-Micron circuits tend to provide higher levels of performance to the circuits, the use of such on-die calibration features will increase in all segments of design. Proper strategies to test these features cannot be ignored.
Highlighting programming language issues using mixed language programming nn Maple and C
Authors: Andrew T. Phillips
Venue: Proceedings of the 35th SIGCSE technical symposium on Computer science education (2004)

Three examples using mixed language programming in Maple and C are provided for the express purpose of highlighting, in a practical way, various issues normally discussed in a traditional programming languages class only as theoretical concepts. The three examples highlight concepts in parameter passing techniques, storage order choices, native machine types and sizes, and the handling of single and multi-dimensional arrays when dealing with legacy code.
Cyber defense: art to science
Authors: O. Sami Saydjari
Venue: Communications of the ACM (2004)

Seeking the knowledge and means to more methodically detect, defend against, and better understand attacks on networked computer resources.
The switching reverse polise algorithm
Authors: Robert W. Witty
Venue: ACM SIGPLAN Notices (1977)

The classical Reverse Polish Algorithm is examined to see why it does not produce optimal evaluation order Reverse Polish. A new algorithm, the Switching Reverse Polish Algorithm, is derived which optimises or improves the evaluation order but retains the simplicity and serial input-output of the classical algorithm. The supermultiply operator is introduced to facilitate strength reduction.
Constraint Based Region Matching for Image Retrieval
Authors: Tao Wang, Yong Rui, Jia-Guang Sun
Venue: International Journal of Computer Vision (2004)

Objects and their spatial relationships are important features for human visual perception. In most existing content-based image retrieval systems, however, only global features extracted from the whole image are used. While they are easy to implement, they have limited power to model semantic-level objects and spatial relationship. To overcome this difficulty, this paper proposes a constraint-based region matching approach to image retrieval. Unlike existing region-based approaches where either individual regions are used or only first-order constraints are modeled, the proposed approach formulates the problem in a probabilistic framework and simultaneously models both first-order region properties and second-order spatial relationships for all the regions in the image. Specifically, in this paper we present a complete system that includes image segmentation, local feature extraction, first- and second-order constraints, and probabilistic region weight estimation. Extensive experiments have been carried out on a large heterogeneous image collection with 17,000 images. The proposed approach achieves significantly better performance than the state-of-the-art approaches.
An iterative method for single and vertically stacked semiconductor quantum dots simulation
Authors: Yiming Li
Venue: Proceedings of the international conference on Computational methods in sciences and engineering (2003)

We present a computational efficient nonlinear iterative method for calculating the electron energy spectra in single and vertically stacked InAs/GaAs semiconductor quantum dots. The problem is formulated with the effective one electronic band Hamiltonian, the energy and position dependent electron effective mass approximation, and the Ben Daniel-Duke boundary conditions. The proposed iterative method converges for all quantum dot simulations. Numerical results show that the electron energy spectra are significantly dependent on the number of coupled layers. For the excited states, the layer dependence effect has been found to be weak than that for the ground state.
Concerning characterizations of boundaries of holomorphic 1-chains within complex surfaces
Authors: Ronald Allen Walker
Venue:  (2003)

Let X be a complex manifold or an analytic variety and let &gamma; be a closed, oriented, C2 real 1-chain in X. We say &gamma; is the boundary of an holomorphic 1-chain within X if there is a holomorphic 1-chain V in X\spt &gamma; such that b[V] = [&gamma;], in the sense of currents, and spt V &Sub; X. We produce a family of new characterizations for boundaries of holomorphic 1-chains within CP2 , related to a previous characterization involving shockwaves. We show that some of these characterizations are computationally accessible and may be tractably tested. By employing birational maps, we further characterize the boundaries of holomorphic 1-chains within C&d4;&times; C&d4; and C&times;C&d4; . By a separate approach, we produce a distinctly new vein of characterizations for boundaries of holomorphic 1-chains within CP2 and C&times;C&d4; .