ppxscal/embedding_network huggingface dataset:
A polynomial time algorithm for obtaining minimum edge ranking on two-connected outerplanar graphs
Authors: Shin-ichi Nakayama, Shigeru Masuyama
Venue: Information Processing Letters (2007)

An edge ranking of a graph G is a labeling r of its edges with positive integers such that every path between two different edges e"u, e"v with the same rank r(e"u)=r(e"v) contains an intermediate edge e"w with rank r(e"w)>r(e"u). An edge ranking of G is minimum if the largest rank k assigned is the smallest among all rankings of G. The edge ranking problem is to find a minimum edge ranking of given graph G. This problem is NP-hard and no polynomial time algorithm for solving it is known for non-trivial classes of graphs other than the class of trees. In this paper, we first show, on a general graph G, a relation between a minimum edge ranking of G and its minimal cuts, which ensures that we can obtain a polynomial time algorithm for obtaining minimum edge ranking of a given graph G if minimal cuts for each subgraph of G can be found in polynomial time and the number of those is polynomial. Based on this relation, we develop a polynomial time algorithm for finding a minimum edge ranking on a 2-connected outerplanar graph.
A Novel Approach to Domino Circuit Synthesis
Authors: Dhiren M. Parmar, M. Sarma, D. Samanta
Venue: Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems (2007)

Dynamic CMOS logic in general and domino logic in particular has a number of advantages to design high speed and low power CMOS circuits. However, the main difficulty with domino logic is that it can implement only non-inverted logic. To implement inverted polarity it is required to duplicate several circuit parts using inverted polarities of inputs and hence increasing area and power dissipation. With static CMOS logic, on the other hand, it is simple to realize gate with both inverted and non-inverted logic unlike dynamic CMOS logic. In this paper, we propose a mixed approach, where it implements both static and dynamic CMOS logic styles in the same circuit eliminating intermediate inverter implementation of domino logic. Simulation results on ISCAS'85 benchmark circuits show that circuits based on our approach have on the average 34 % area and 32 % power improvement compared to circuits with only domino logic and on the average 26 % power and 38 % delay improvement compared to circuits with only static CMOS logic.
Probabilistic simulation of human-machine dialogues
Authors: K. Scheffler
Venue: Proceedings of the Acoustics, Speech, and Signal Processing, 2000. on IEEE International Conference - Volume 02 (2000)

The field of spoken dialogue systems has developed rapidly. However, optimisation, evaluation and rapid development of systems remain problematic. This paper describes a method of producing a probabilistic simulation of mixed initiative dialogue with recognition and understanding errors. Both user behaviour and system errors are modelled using a data-driven approach, and the quality of the simulations are evaluated by comparing them to real human-machine dialogues. The simulation system can be used to perform rapid evaluations of prototype systems, thus aiding the development process. It is also envisaged that it will be used as a tool for automation of dialogue design.
www.cybercareers.org: career education resources for educators and students
Authors: P. Saflund
Venue: Proceedings of the Frontiers in Education Conference, 2001. 31st Annual - Volume 02 (2001)

What are the best tools for introducing students to the wide world of IT? How do you develop and deliver a course or class on IT career education? What resources can students use to take a self-guided tour of the careers in IT? In the presentation, the author introduces the audience to www.cybercareers.org. This career education website features tools and information for both educators and students. On this website, teachers will find lesson plans and ideas for activities. Students can learn how to prepare for a career in the world of IT, what salaries to expect, and how to best match their interests and personalities to careers in IT. The ACM Portal is published by the Association for Computing Machinery. Copyright © 2010 ACM, Inc. Terms of Usage Privacy Policy Code of Ethics Contact Us Useful downloads: Adobe Acrobat QuickTime Windows Media Player Real Player
Algorithms to estimating fractal dimension of textured images
Authors: Wen-Shiung Chen
Venue: Proceedings of the Acoustics, Speech, and Signal Processing, 2001. on IEEE International Conference - Volume 03 (2001)

Two algorithms that can obtain more accurate estimate of the fractal dimension are proposed. One is the shifting DBC (SDBC) algorithm and the other one is the scanning BC (SBC) algorithm. It is theoretically proven that the SDBC algorithm approaches the estimated value closer to the exact fractal dimension than the DBC method. Simulation results show that the proposed algorithms consistently give more satisfactory results on textured images.
Many Sorted Observational Calculi for Multi-Relational Data Mining
Authors: Jan Rauch
Venue: Proceedings of the Sixth IEEE International Conference on Data Mining - Workshops (2006)

Observational calculi approved as a tool for study logical properties of association rules. They are defined by modifications of classical predicate calculi. Many sorted observational calculi are introduced as a modification of classical many sorted predicate calculi. It is argued that such defined calculi are suitable for relational data mining. Results on decidability of these calculi are presented. Further research directions are outlined.
Boosting the role of inductive invariants in model checking
Authors: Gianpiero Cabodi, Sergio Nocco, Stefano Quer
Venue: Proceedings of the conference on Design, automation and test in Europe (2007)

This paper focuses on inductive invariants in unbounded model checking to improve efficiency and scalability. First of all, it introduces optimized techniques to speedup the computation of inductive invariants, considering both equivalences and implications between pairs of nodes in the logic network. Secondly, it presents a very efficient dynamic procedure, based on an incremental SAT approach, to reduce the set of checked invariants. Finally, it shows how to effectively integrate inductive invariant computations with state-of-the-art model checking procedures. Experiments address different property verification aspects, and specifically consider cases where inductive invariants alone are not sufficient for the final proof.
Using polynomial regression for data representation in wireless sensor networks: Research Articles
Authors: Torsha Banerjee, Kaushik R. Chowdhury, Dharma P. Agrawal
Venue: International Journal of Communication Systems (2007)

Unlike conventional sensor networks, wireless sensors are limited in power, have much smaller memory buffers, and possess relatively slower processing speeds. These characteristics necessitate minimum transfer and storage of information in order to prolong the network lifetime. In this paper, we exploit the spatio-temporal nature of sensor data to approximate the current values of the sensors based on readings obtained from neighbouring sensors and itself. We propose a tree based polynomial regression algorithm (TREG), that addresses the problem of data compression in wireless sensor networks. Instead of aggregated data, only the coefficients computed by the regression function, TREG are passed to achieve the following goals: (i) the sink can get attribute values in the regions devoid of sensor nodes, and (ii) readings over any portion of the region can be obtained at one time by querying the root of the tree. As the size of the data packet from each tree node to its parent remains constant, the proposed scheme scales very well with growing network density or increased coverage area. Since physical attributes exhibit a gradual change over time, we propose an iterative scheme, UPDATE&lowbar;COEFF, which obviates the need to perform the regression function repeatedly and uses approximations based on previous readings. Extensive simulations are performed on real world data to demonstrate the effectiveness of the aggregation algorithm, TREG. Results reveal that for a network density of 0.0025, a complete binary tree of depth 4 could provide the absolute error to be less than 6&percnt;. A data compression ratio of about 0.02 is achieved using our proposed algorithm, which is almost independent of the tree depth. In addition, our proposed updating scheme makes the aggregation process faster while maintaining the desired error bounds. Copyright &copy; 2006 John Wiley & Sons, Ltd.
UWIN: UNIX for windows
Authors: David G. Korn
Venue: Proceedings of the USENIX Windows NT Workshop on The USENIX Windows NT Workshop 1997 (1997)

This paper describes an effort of trying to build a UNIX interface layer on top of the Windows NT[1] and Windows 95[2] operating system. The goal was to build an open environment rich enough to be both a good development environment and a suitable execution environment. The result of this effort is a set of libraries, headers, and utilities that we collectively refer to as UWIN. UWIN contains nearly all the X/Open Release 4[3] headers, interfaces, and commands. An earlier paper on porting to Windows NT[4], describes alternative porting strategies and presents some performance results for UWIN. In this paper we discuss some of the design decisions behind UWIN and some of the results so far as well as some of the remaining challenges.
Translating HPSG-style outputs of a robust parser into typed dynamic logic
Authors: Manabu Sato, Daisuke Bekki, Yusuke Miyao, Jun'ichi Tsujii
Venue: Proceedings of the COLING/ACL on Main conference poster sessions (2006)

The present paper proposes a method by which to translate outputs of a robust HPSG parser into semantic representations of Typed Dynamic Logic (TDL), a dynamic plural semantics defined in typed lambda calculus. With its higher-order representations of contexts, TDL analyzes and describes the inherently inter-sentential nature of quantification and anaphora in a strictly lexicalized and compositional manner. The present study shows that the proposed translation method successfully combines robustness and descriptive adequacy of contemporary semantics. The present implementation achieves high coverage, approximately 90%, for the real text of the Penn Treebank corpus.
Refactoring - Does it improve software quality?
Authors: Konstantinos Stroggylos, Diomidis Spinellis
Venue: Proceedings of the 29th International Conference on Software Engineering Workshops (2007)

Software systems undergo modifications, improvements and enhancements to cope with evolving requirements. This maintenance can cause their quality to decrease. Various metrics can be used to evaluate the way the quality is affected. Refactoring is one of the most important and commonly used techniques of transforming a piece of software in order to improve its quality. However, although it would be expected that the increase in quality achieved via refactoring is reflected in the various metrics, measurements on real life systems indicate the opposite. We analyzed source code version control system logs of popular open source software systems to detect changes marked as refactorings and examine how the software metrics are affected by this process, in order to evaluate whether refactoring is effectively used as a means to improve software quality within the open source community.
Shock-peakon and shock-compacton solutions for K(p,q) equation by variational iteration method
Authors: Lixin Tian, Jiuli Yin
Venue: Journal of Computational and Applied Mathematics (2007)

By variational iteration method, we obtain new solitary solutions for non-linear dispersive equations. Particularly, shock-peakon solutions in K(2,2) equation and shock-compacton solutions in K(3,3) equation are found by this simple method. These two types of solutions are new solitary wave solutions which have the shapes of shock solutions and compacton solutions (or peakon solutions).
A new adaptive channel estimator for turbo decoding in Rayleigh fading channels
Authors: Wee-Peng Ang, H.-K. Garg
Venue: Proceedings of the The 8th International Conference on Communication Systems - Volume 01 (2002)

A new adaptive channel estimation filter based on the variable step-size LMS algorithm is shown to perform close to the optimum Wiener filter without assuming a-priori knowledge of the channel fading rate. It is unlike other fixed characteristics filters such as the equal weight moving average and FIR filters designed using the windowing method. Under a non-stationary Rayleigh fading channel where the fading rate varies, the proposed adaptive filter is also able to track the time-varying channel, achieving better performance than the fixed characteristics filters.
PRO: a popularity-based multi-threaded reconstruction optimization for RAID-structured storage systems
Authors: Lei Tian, Dan Feng, Hong Jiang, Ke Zhou, Lingfang Zeng, Jianxi Chen, Zhikun Wang, Zhenlei Song
Venue: Proceedings of the 5th USENIX conference on File and Storage Technologies (2007)

This paper proposes and evaluates a novel dynamic data reconstruction optimization algorithm, called popularity-based multi-threaded reconstruction optimization (PRO), which allows the reconstruction process in a RAID-structured storage system to rebuild the frequently accessed areas prior to rebuilding infrequently accessed areas to exploit access locality. This approach has the salient advantage of simultaneously decreasing reconstruction time and alleviating user and system performance degradation. It can also be easily adopted in various conventional reconstruction approaches. In particular, we optimize the disk-oriented reconstruction (DOR) approach with PRO. The PRO-powered DOR is shown to induce a much earlier onset of response-time improvement and sustain a longer time span of such improvement than the original DOR. Our benchmark studies on read-only web workloads have shown that the PRO-powered DOR algorithm consistently outperforms the original DOR algorithm in the failurerecovery process in terms of user response time, with a 3.6%-23.9% performance improvement and up to 44.7% reconstruction time improvement simultaneously.
Extending Rate Monotonic Analysis with Exact Cost of Preemptions for Hard Real-Time Systems
Authors: Patrick Meumeu Yomsi, Yves Sorel
Venue: Proceedings of the 19th Euromicro Conference on Real-Time Systems (2007)

In this paper we study hard real-time systems composed of independent periodic preemptive tasks where we assume that tasks are scheduled by using Liu & Layland's pioneering model following the Rate Monotonic Analysis (RMA). For such systems, the designer must guarantee that all the deadlines of all the tasks are met, otherwise dramatic consequences occur. Certainly, guaranteeing deadlines is not always achievable because the preemption is approximated when using this analysis, and this approximation may lead to a wrong real-time execution whereas the schedulability analysis concluded that the system was schedulable. To cope with this problem the designer usually allows margins which are difficult to assess, and thus in any case lead to a waste of resources. This paper makes multiple contributions. First, we show that, when considering the cost of the preemption during the analysis, the critical instant does not occur upon simultaneous release of all tasks. Second, we provide a technique which counts the exact number of preemptions of each instance for all the tasks of a given system. Finally, we present an RMA extension which takes into account the exact cost due to preemption in the schedulability analysis rather than an approximation, thus yielding a new and stronger schedulability condition which eliminates the waste of resources since margins are not necessary.
The collective: a cache-based system management architecture
Authors: Ramesh Chandra, Nickolai Zeldovich, Constantine Sapuntzakis, Monica S. Lam
Venue: Proceedings of the 2nd conference on Symposium on Networked Systems Design & Implementation - Volume 2 (2005)

This paper presents the Collective, a system that delivers managed desktops to personal computer (PC) users. System administrators are responsible for the creation and maintenance of the desktop environments, or virtual appliances, which include the operating system and all installed applications. PCs run client software, called the virtual appliance transceiver, that caches and runs the latest copies of appliances locally and continuously backs up changes to user data to a network repository. This model provides the advantages of central management, such as better security and lower cost of management, while leveraging the cost-effectiveness of commodity PCs. With a straightforward design, this model provides a comprehensive suite of important system functions including machine lockdown, system updates, error recovery, backups, and support for mobility. These functions are made available to all desktop environments that run on the x86 architecture, while remaining protected from the environments and their many vulnerabilities. The model is suitable for managing computers on a LAN, WAN with broadband, or even computers occasionally disconnected from the network like a laptop. Users can access their desktops from any Collective client; they can also carry a bootable drive that converts a PC into a client; finally, they can use a remote display client from a browser to access their desktop running on a remote server. We have developed a prototype of the Collective system and have used it for almost a year. We have found the system helpful in simplifying the management of our desktops while imposing little performance overhead.
Policies for dynamic clock scheduling
Authors: Dirk Grunwald, Charles B. Morrey,  III, Philip Levis, Michael Neufeld, Keith I. Farkas
Venue: Proceedings of the 4th conference on Symposium on Operating System Design & Implementation - Volume 4 (2000)

Pocket computers are beginning to emerge that provide sufficient processing capability and memory capacity to run traditional desktop applications and operating systems on them. The increasing demand placed on these systems by software is competing against the continuing trend in the design of low-power microprocessors towards increasing the amount of computation per unit of energy. Consequently, in spite of advances in low-power circuit design, the microprocessor is likely to continue to account for a significant portion of the overall power consumption of pocket computers. This paper investigates clock scaling algorithms on the Itsy, an experimental pocket computer that runs a complete, functional multitasking operating system (a version of Linux 2.0.30). We implemented a number of clock scaling algorithms that are used to adjust the processor speed to reduce the power used by the processor. After testing these algorithms, we conclude that currently proposed algorithms consistently fail to achieve their goal of saving power while not causing user applications to change their interactive behavior.
A Re-configurable FTL (Flash Translation Layer) Architecture for NAND Flash based Applications
Authors: Chanik Park, Wonmoon Cheon, Yangsup Lee, Myoung-Soo Jung, Wonhee Cho, Hanbin Yoon
Venue: Proceedings of the 18th IEEE/IFIP International Workshop on Rapid System Prototyping (2007)

In this paper, we propose a novel FTL (Flash Translation Layer) architecture for NAND flash based applications such as mp3 players, DSCs (Digital still camera) and SSDs (Solid-state disk). Even though the basic function of an FTL is to translate a logical sector address to a physical sector address in flash memory, its efficient algorithms have a significant impact on performance as well as lifetime. After we categorize dominant parameters that affect performance and endurance, we explore the design space of the FTL architecture based on a diverse workload analysis. With our FTL architectural framework, we can decide which configuration of FTL mapping parameters yields the best performance depending on each NAND flash application behavior.
Implementation of a high-quality Dolby Digital decoder using MMX/sup TM/ technology
Authors: J. C. Abel
Venue: Proceedings of the Acoustics, Speech, and Signal Processing, 1999. on 1999 IEEE International Conference - Volume 04 (1999)

Software decoding of Dolby Digital allows it to become a baseline capability on the PC, with greater flexibility than a hardware approach. Intel's MMX/sup TM/ technology provides instructions that can significantly speed up the execution of the Dolby Digital decoder, freeing up the processor to perform other tasks such as video decoding and/or audio enhancement. Intel has worked closely with Dolby Laboratories to define an implementation of Dolby Digital based on MMX technology that has achieved Dolby's certification of quality.
Multi channel HMM
Authors: Dongkin Xu
Venue: Proceedings of the Acoustics, Speech, and Signal Processing, 1996. on Conference Proceedings., 1996 IEEE International Conference - Volume 02 (1996)

In speech recognition, the speech signal is usually represented in multidimensions but the hidden Markov model (HMM) is one-dimensional. A multichannel HMM (MC-HMM) is proposed as a more robust modeling method for multi-channel signals. Weighting among channels can be incorporated into the model in an uniform way, i.e. both model parameters and weighting coefficients can be estimated by the efficient Baum-Welch training procedure. Moreover, it can be shown that weighting among channels is exactly equivalent to relaxing the probability constraints. Therefore, for the weighting, no extra parameter is actually needed, and consequently no extra memory and computational costs are required. The preliminary experiment results on word spotting show that MC-HMM is better than the standard HMM.
Change-out: A System of Systems Approach to COTS Management
Authors: Sally J. F. Baron
Venue: Proceedings of the Sixth International IEEE Conference on Commercial-off-the-Shelf (COTS)-Based Software Systems (2007)

Civilization has slipped into the twenty-first century with electronics touching nearly every part of our lives. Since inception, integrated circuit technology and software have advanced exponentially. Complex systems such as cars, satellites and aircraft can have subsystems with lifespans that wildly differ. Many such products are truly a systems of systems where subsystem change-out is required to keep the unit upto- date. Products that run mostly on electronics are often smaller like telephones and computers. When obsolete they are usually replaced rather than refurbished. But in larger systems like an aircraft or a submarine, subsystem change-out should be considering during planning. In the Department of Defense as well as other organizations, managing such a process is complex. This paper examines such complexity, provides a visual framework for a system of systems and the relevance and importance of change-out in general.