ppxscal/embedding_network huggingface dataset:
A Compared Study of Two Correctness Proofs for the Standardized Algorithm of ABR Conformance
Authors: Béatrice Bérard, Laurent Fribourg, Francis Klay, Jean-François Monin
Venue: Formal Methods in System Design (2003)

The ABR conformance protocol is a real-time program that controls dataflow rates on ATM networks. A crucial part of this protocol is the dynamical computation of the expected rate of data cells. We present here a modelling of the corresponding program with its environment, using the notion of (parametric) timed automata. A fundamental property of the service provided by the protocol to the user is expressed in this framework and proved by two different methods. The first proof relies on inductive invariants, and was originally verified using theorem-proving assistant COQ. The second proof is based on reachability analysis, and was obtained using model-checker HYTECH. We explain and compare these two proofs in the unified framework of timed automata.
The observability of the Fibonacci and the Lucas cubes
Authors: Ernesto Dedó, Damiano Torri, Norma Zagaglia Salvi
Venue: Discrete Mathematics (2002)

The Fibonacci cube Γn is the graph whose vertices are binary strings of length n without two consecutive 1's and two vertices are adjacent when their Hamming distance is exactly 1. If the binary strings do not contain two consecutive 1's nor a 1 in the first and in the last position, we obtain the Lucas cube Ln. We prove that the observability of Γn and Ln is n, where the observability of a graph G is the minimum number of colors to be assigned to the edges of G so that the coloring is proper and the vertices are distinguished by their color sets.
T-Engine: The Open, Real-Time Embedded-Systems Platform
Authors: Ken Sakamura, Noboru Koshizuka
Venue: IEEE Micro (2002)

The growing popularity of real-time embedded systems creates an urgent need for improved performance and expanded functionality. this open architecture helps optimize these systems.
Pseudorandom Testing for Boundary-Scan Design with Built-In Self-Test
Authors: P. Nagvajara, M. G. Karpovsky, L. B. Levitin
Venue: IEEE Design Test (1991)

The design of a pseudorandom pattern generator for a boundary-scan chip with built-in self-test is described. The proposed test-generation procedure, together with a method of connecting the generator outputs and the primary inputs of the chip under test, ensures full pattern coverage. The authors show how to evaluate the choice of generator parameters and initial states when there are more flip-flops in the generator than bits in the test pattern.
A feature-based pencil drawing method
Authors: Nan Li, Zhiong Huang
Venue: Proceedings of the 1st international conference on Computer graphics and interactive techniques in Australasia and South East Asia (2003)

We present a method for generating a pencil drawing from a digital image using the feature geometric attributes obtained by analysis of image moment and texture of each region. Thus, the drawing results represent not only the local region information but also the feature characteristics. It is inspired and devised to correspond to a real pencil drawing process: A painter often divides a scene into regions, observes the distinctive features, and applies the pencil strokes accordingly. We have implemented the method and compared the results with Adobe Photoshop 5.0.
Fast Power Estimation of Large Circuits
Authors: Peter H. Schneider, Ulf Schlichtmann, Bernd Wurth
Venue: IEEE Design Test (1996)

Logic-level circuit optimization for low power requires efficient estimation of the power consumed by the resulting circuit. In CMOS, the power consumption depends on the number of transitions occurring on the signals internal to a circuit. We introduce a new technique to estimate the transition probabilities for internal signals of combinational circuits. This technique uses Markov chains and the concept of reconvergence regions, and is efficiently implemented based on ROBDDs.The temporal dependence of each signal, multiple concurrent transitions and mutual dependence of internal signals are taken into account. Our technique provides an exact computation for small circuits and an approximate estimation for large circuits. Experimental results show the approximate estimation to be fast even for large circuits while only small inaccuracies appear.
A Role Based Model for the Normative Specification of Organized Collective Agency and Agents Interaction
Authors: Olga Pacheco, José Carmo
Venue: Autonomous Agents and Multi-Agent Systems (2003)

In this article we propose a role based model for the specification of organized collective agency, based on the legal concept of artificial person and on the normative perspective of organizational systems. We focus on the analysis of groups of agents (humans or not) that want to act collectively in a (more or less) permanent basis, and in a stable and organized way, as it is the typical case of organizations. We argue that in those cases such groups of agents should give rise to a new agent, that we call of institutionalized agent, with its own identity, whose structure is essentially defined through the characterization of a set of roles and whose behavior is determined by the acts of the agents that play such roles. We also present a deontic and action modal logic that captures the concept of acting in a role and relates it with the deontic notions of obligation, permission and prohibition. This logic is used in the formal specification of institutionalized agents and of societies of agents and in the rigorous analysis of them. We pay particular attention to the interaction between agents through contracts or other normative relations. A high level specification language is also suggested.
Universal Test Interface for Embedded-DRAM Testing
Authors: Shinji Miyano, Katsuhiko Sato, Kenji Numata
Venue: IEEE Design Test (1999)

This paper describes circuitry for facilitating the test of embedded DRAM macro whose configuration can be easily changed (reconfigurable macro). It is difficult to use conventional direct access mode circuitry, because the configuration of embedded DRAMs on a chip is varied for each product, and therefor the test circuitry should be customized for each product. The proposed test circuits implemented in the macro provide a Universal Test Interface regardless of the DRAM configuration and the number of macros on a chip.
Analytical Estimation of Vector Access Performance in Parallel Memory Architectures
Authors: D. T. Harper,  III, Y. Costa
Venue: IEEE Transactions on Computers (1993)

A limiting factor in high-performance vector computers is the rate at which data can be moved to and from memory during vector loads and stores. To increase the bandwidth of vector memory operations, several investigators have proposed the use of noninterleaved storage mappings, also known as storage schemes. A method of analyzing the performance of vector references for the class of storage schemes referred to as XOR schemes is described. The proposed measure of relative performance, the variability of an access, is defined and its computation is outlined. The use of variability as a performance indicator is demonstrated and compared with performance measurements made using simulation. One of the key aspects of the variability measure is its capability to lend insight to the transient behavior of vector accesses.
Extensible Integration Frameworks for Measurement
Venue: IEEE Software (1990)

No abstract available The ACM Portal is published by the Association for Computing Machinery. Copyright © 2010 ACM, Inc. Terms of Usage Privacy Policy Code of Ethics Contact Us Useful downloads: Adobe Acrobat QuickTime Windows Media Player Real Player
EROS: A Principle-Driven Operating System from the Ground Up
Authors: Jonathan S. Shapiro, Norman Hardy
Venue: IEEE Software (2002)

Design principles are one of the most advocated ideas in software construction, but they are rarely systematically applied. They are particularly critical in se-cure, reliable systems. EROS, an operating system built from the ground up, provides formally verifiable security, practical reliability, and high performance. This article describes the primary design principles on which EROS is built, the impact these principles had on the design, the application structure that naturally emerged from the resulting system, and the how this affected the system's security and testability.
New bounds on a hypercube coloring problem
Authors: Hung Quang Ngo, Ding-Zhu Du, Ronald L. Graham
Venue: Information Processing Letters (2002)

In studying the scalability of optical networks, one problem which arises involves coloring the vertices of the n-cube with as few colors as possible such that any two vertices whose Hamming distance is at most k are colored differently. Determining the exact value of χ??(n), the minimum number of colors needed, appears to be a difficult problem. In this note, we improve the known lower and upper bounds of χ??(n) and indicate the connection of this coloring problem to linear codes.
Reverse Engineering and the Computing Profession
Authors: Cristina Cifuentes
Venue: Computer (2001)

Recent actions against reverse engineering threaten to remove this valuable practice from the computing profession's toolkit.
Safety Verification of Ada Programs Using Software Fault Trees
Authors: Nancy G. Leveson, Stephen S. Cha, Timothy J. Shimeall
Venue: IEEE Software (1991)

The software fault-tree analysis technique is explained. It is then extended to allow its use on a more complex language involving such features as concurrency and exception handling. Ada is used as the example language because many safety-critical projects are using or planning to use Ada. It also contains complex, real-time programming facilities found in other languages used in these types of projects. Software fault-tree analysis uses failure-mode templates to generate the fault tree. The templates provided can be used to define the procedures for applying the technique to programs written in most other declarative languages. To explain the use of the templates an example Ada program, for a traffic-light-control system, is analyzed. The cost and practicality of the method and its implications for software reuse are assessed. The application of the safety analysis procedures to requirements modeling and specification languages is considered.
New Model and Algorithms for Leader Election in Synchronous Fiber-Optic Networks
Authors: H. Abu-Amara, V. Gummadi
Venue: IEEE Transactions on Parallel and Distributed Systems (1994)

We improve on I. Cidon, I. Gopal and S. Kutten's leader election algorithm (Proc. 7th ACM Symp. Principles Distrib. Computing, Toronto, Ont., Canada. Aug. 1988) by presenting an algorithm that uses only O(/spl radic/n log D + f) time units to run on synchronous networks of degree f and diameter D, where f/spl ges/3. When f is 2, the algorithm uses only O(log D) time units.
Algorithms for High-Level Synthesis
Authors: Pierre G. Paulin, John P. Knight
Venue: IEEE Design Test (1989)

Synthesis algorithms that offer a technique for scheduling operations and allocating registers and buses in light of both timing constraints and available hardware resources are presented. They enhance current scheduling techniques by using a global priority function that minimizes storage, interconnections, and functional unit cost. Algorithms for allocating registers and buses minimize storage and interconnection costs and take into account the interdependence of both tasks. The algorithms are also applicable to more than one method of synthesis; although first implemented in the HAL system, they have since been integrated into more specialized high-level synthesis systems.
Should Computer Scientists Experiment More?
Authors: Walter F. Tichy
Venue: Computer (1998)

Do computer scientists need to experiment at all? Only if the answer is "yes" does it make sense to ask whether there is enough of it. The author argues that experimentation is central to the scientific process. Only experiments test theories. Only experiments can explore critical factors and bring new phenomena to light, so theories can be formulated and corrected. Without experiments, according to the author, computer science is in danger of drying up and becoming an auxiliary discipline. The current pressure to concentrate on application is the writing on the wall. The author rebuts the eight most common objections computer scientists have to focusing on experimentation: The traditional scientific method isn't applicable. The current level of experimentation is good enough. Experiments cost too much. Demonstrations will suffice. There's too much noise in the way. Progress will slow. Technology changes too fast. You'll never get it published.In contrast, the author argues that experimentation would build a reliable base of knowledge and thus reduce uncertainty about which theories, methods, and tools are adequate; lead to new, useful, and unexpected insights and open whole new areas of investigation; and accelerate progress by quickly eliminating fruitless approaches, erroneous assumptions, and fads. Conversely, when we ignore experimentation and avoid contact with reality, we hamper progress. As computer science leaves adolescence behind, the author advocates the development of its experimental branch.
A Study of 12 Specifications of the Library Problem
Authors: Jeannette M. Wing
Venue: IEEE Software (1988)

The author studies twelve specifications for a seemingly simple database problem and demonstrates many approaches for classifying informally stated problem requirements. She compares the specifications according to how they address problems of the library example to illustrate the imprecision of natural-language specifications and how twelve different approaches to the same set of informal requirements reveal many of the same problems. The comparison suggests which issues should be addressed in refining an informal set of requirements and shows how these issues are resolved in different specification approaches.
On the Complexity of Distributed Query Optimization
Authors: Chihping Wang, Ming-Syan Chen
Venue: IEEE Transactions on Knowledge and Data Engineering (1996)

While a significant amount of research efforts has been reported on developing algorithms, based on joins and semijoins, to tackle distributed query processing, there is relatively little progress made toward exploring the complexity of the problems studied. As a result, proving NP-hardness of or devising polynomial-time algorithms for certain distributed query optimization problems has been elaborated upon by many researchers. However, due to its inherent difficulty, the complexity of the majority of problems on distributed query optimization remains unknown. In this paper we generally characterize the distributed query optimization problems and provide a frame work to explore their complexity. As it will be shown, most distributed query optimization problems can be transformed into an optimization problem comprising a set of binary decisions, termed Sum Product Optimization (SPO) problem. We first prove SPO is NP-hard in light of the NP-completeness of a well-known problem, Knapsack (KNAP). Then, using this result as a basis, we prove that five classes of distributed query optimization problems, which cover the majority of distributed query optimization problems previously studied in the literature, are NP-hard by polynomially reducing SPO to each of them. The detail for each problem transformation is derived. We not only prove the conjecture that many prior studies relied upon, but also provide a frame work for future related studies.
Analysis on Extended Ant Routing Algorithms for Network Routing and Management
Authors: John Sum, Hong Shen, G. Young, Jie Wu, Chi-Sing Leung
Venue: The Journal of Supercomputing (2003)

Advances in mobile agent research have brought in a new method for network routing, ant routing. Recently, we have derived some preliminary results regarding the agent population growth property and the jumping behavior for an ant routing algorithm. The focus was on the expected number of agents in a node. In practice, the number of agents propagating on each network channel is also critical as the network channel bandwidth is limited. In this paper, we first propose two extended ant routing algorithms, and then provide an in-depth analysis on the population growth behavior of the propagating agents for these algorithms, both at nodes (hosts) and on edges (channels) of the network.
Hierarchical Scalable Photonic Architectures for High-Performance Processor Interconnection
Authors: P. W. Dowd, K. Bogineni, K. A. Aly, J. A. Perreault
Venue: IEEE Transactions on Computers (1993)

Introduces two hierarchical optical structures for processor interconnection and compares their performance through analytic models and discrete-event simulation. Both architectures are based on wavelength division multiplexing (WDM) which enables multiple multi-access channels to be realized on a single optical fiber. The objective of the hierarchical architectures is to achieve scalability yet avoid the requirement of multiple wavelength tunable devices per node. Furthermore, both hierarchical architectures are single-hop: a packet remains in the optical form from source to destination and does not require cross dimensional intermediate routing.
Immersive volume visualization of seismic simulations: a case study of techniques invented and lessons learned
Authors: Prashant Chopra, Joerg Meyer, Antonio Fernandez
Venue: Proceedings of the conference on Visualization '02 (2002)

This paper is a documentation of techniques invented, results obtained and lessons learned while creating visualization algorithms to render outputs of large-scale seismic simulations. The objective is the development of techniques for a collaborative simulation and visualization shared between structural engineers, seismologists, and computer scientists. The computer graphics research community has been witnessing a large number of exemplary publications addressing the challenges faced while trying to visualize both large-scale surface and volumetric datasets lately. From a visualization perspective, issues like data preprocessing (simplification, sampling, filtering, etc.); rendering algorithms (surface and volume), and interaction paradigms (large-scale, highly interactive, highly immersive, etc.) have been areas of study. In this light, we outline and describe the milestones achieved in a large-scale simulation and visualization project, which opened the scope for combining existing techniques with new methods, especially in those cases where no existing methods were suitable. We elucidate the data simplification and reorganization schemes that we used, and discuss the problems we encountered and the solutions we found. We describe both desktop (high-end local as well as remote) interfaces and immersive visualization systems that we developed to employ interactive surface and volume rendering algorithms. Finally, we describe the results obtained, challenges that still need to be addressed, and ongoing efforts to meet the challenges of large-scale visualization.
Effective Built-In Self-Test for Booth Multipliers
Authors: Dimitris Gizopoulos, Antonis Paschalis, Yervant Zorian
Venue: IEEE Design Test (1998)

Module generators provided by library vendors supply chip designers with optimized Booth multipliers which are widely used, as embedded cores, in both general purpose datapath structures and specialized Digital Signal Processors. Testing of such multipliers deeply embedded in complex ICs requires the utilization of an effective BIST scheme that can be easily synthesized along with the multiplier by the module generator. The BIST scheme for Booth multipliers, introduced in this paper, completely complies with this requirement. The algorithmic BIST patterns that this scheme generates guarantee a fault coverage higher than 99%. The required Test Pattern Generator consists of a simple fixed-size either binary counter or maximum length LFSR, independent of the size of the multiplier. Accumulator-based compaction is adopted since multipliers and adders co-exist in datapath structures. A new accumulator-based compaction scheme is introduced to provide higher compaction quality than existing approaches. The novel BIST scheme is generic, (i.e. independent of specific gate-level implementations of the multiplier cells and not requiring DFT in the multiplier) and thus it can be adopted by any module generator.
Orientation determination in the 3D reconstruction of icosahedral viruses using a parallel computer
Authors: C. A. Johnson, N. I. Weisenfeld, B. L. Trus, J. F. Conway, R. L. Martino, A. C. Steven
Venue: Proceedings of the 1994 ACM/IEEE conference on Supercomputing (1994)

Three dimensional image reconstruction from cryo-electron micrographs allows the capsid structures of icosahedral viruses to be studied. The most computationally demanding stages of the reconstruction process are those that find and refine the orientations of the virus particles. We have devised and implemented parallel solutions to the problem of determining these orientations. By enabling determination of the orientations of far more particles than previously had been possible, parallel processing methods have contributed to improvements in the quality of recent reconstructions.
Are We Developers Liars or Just Fools?
Authors: Robert N. Charette
Venue: IEEE Software (1995)

Things were good in the old days. Very few people understood software, so those of us who were cognoscenti could get away with murder. We could explain away cost and schedule overruns by blaming ¿complexity.¿ Performance problems were the fault of emerging technology. And if management or customers got angry, what could they do? We were the only show in town.Although nearly everything that defined ¿the old days¿ has changed, Robert Charette argues that many of the old foibles remain. Charette is president of Itabhi Corporation, a high-tech management consultancy, and one of the leading authorities on software, systems, and business risk management. He consults with several national governments and Fortune 100 companies, and he worries about the social and ethical implications of computing. According to Charette, software managers and the people who work for them risk being viewed as liars or fools, a perception that can only harm the software community.¿ Roger Pressman
The Development of ATM Standards and Technology: A Retrospective
Authors: Richard Vickers
Venue: IEEE Micro (1993)

The evolution of the ATM (asynchronous transfer mode) from its inception in early trials through to the current developments is reviewed. Strong emphasis is placed on the role of standards development in the development of the technology, as it is the opinion of the author that ATM could never have reached the status that it has today without the development effort put into the standards over the period between 1986 and 1992. The standards development process has also been a learning process. Technical differences seem to get resolved more quickly with more interaction at informal workshops. The creation of the ATM Forum has taken ATM one step closer to the end user. However, the standards community is aware of a need to improve its process, to develop standards that are less ambiguous and less subject to error, and to ensure interoperability of different networks and different vendor products. The author notes that over the next few years one will see major changes in these areas to improve the product of standards development.