ppxscal/embedding_network huggingface dataset:
Evaluation of a Semiautomatic 3D Fusion Technique Applied to Molecular Imaging and MRI Brain/Frame Volume Data Sets
Authors: R. J. T. Gorniak, E. L. Kramer, G. Q. Maguire,  Jr., M. E. Noz, C. J. Schettino, M. P. Zeleznik
Venue: Journal of Medical Systems (2003)

A generally applicable 3D fusion method was evaluated using molecular imaging and MRI volumetric data sets from 15 brain tumor patients with stereotactic frames attached to their skull. Point pairs, placed on the frame only, were chosen, polynomial warping coefficients were generated to map voxels from one coordinate space to the other. The MRI frame was considered the reference structure and the standard for &ldquo;correct&rdquo; registration. An ANOVA test (p > 0.05) confirmed the point pair choice to be consistent. The 95% confidence interval for the t-test showed the measured distance difference between the registered volumes was within one MRI voxel. A further experiment was conducted to independently evaluate the brain registration based on testing for consistency of randomly selected interior/exterior points. A t-test result (p < 0.05) showed that the consistency (i.e., both interior or both exterior) before and after volume registration were significantly different. This fusion method may be a viable alternative when other methods fail.
Test generation for acyclic sequential circuits with hold registers
Authors: Tomoo Inoue, Debesh Kumar Das, Chiiho Sano, Takahiro Mihara, Hideo Fujiwara
Venue: Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design (2000)

We present a method of test generation for acyclic sequential circuits with hold registers. A complete (100% fault efficiency) test sequence for an acyclic sequential circuit can be obtained by applying a combinational test generator to all the maximal time-expansion models (TEMs) of the circuit. We propose a class of acyclic sequential circuits for which the number of maximal TEMs is one, i.e, the maximum TEM exists. For a circuit in the class, test generation can be performed by using only the maximum TEM.The proposed class of sequential circuits with the maximum TEM properly includes several known classes of acyclic sequential circuits such as balanced structures and acyclic sequential circuits without hold registers for which test generation can be also performed by using a combinational test generator. Therefore, in general, the hardware overhead for partial scan based on the proposed structure is smaller than that based on balanced or acyclic sequential structure without hold registers.
Towards a self-adapting centralized concurrency control algorithm
Authors: Haran Boral, Israel Gold
Venue: Proceedings of the 1984 ACM SIGMOD international conference on Management of data (1984)

We introduce the notion of self-adapting concurrency control algorithms --- concurrency control algorithms that consist of several rw and several ww synchronization techniques, and employ combinations of the techniques in a manner that attains a performance objective. We Consider synchronization techniques that use locking and certification. A general proof method for such algorithms is outlined and applied.
A type system for higher-order modules
Authors: Derek Dreyer, Karl Crary, Robert Harper
Venue: ACM SIGPLAN Notices (2003)

We present a type theory for higher-order modules that accounts for many central issues in module system design, including translucency, applicativity, generativity, and modules as first-class values. Our type system harmonizes design elements from previous work, resulting in a simple, economical account of modular programming. The main unifying principle is the treatment of abstraction mechanisms as computational effects. Our language is the first to provide a complete and practical formalization of all of these critical issues in module system design.
A force-directed maze router
Authors: Fan Mo, Abdallah Tabbara, Robert K. Brayton
Venue: Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design (2001)

A new routing algorithm is presented. It is based on a multiple star net model, force-directed placement and maze searching techniques. The algorithm inherits the power of maze routing in that it is able to route complex layouts with various obstructions. The large memory requirement of the conventional maze algorithm is alleviated through successive net refinement, which constrains the maze searching to small regions. The algorithm shows advantages in routing designs with complicated layout obstructions.
Negotiation on Data Allocation in Multi-Agent Environments
Authors: Rina Azoulay-Schwartz, Sarit Kraus
Venue: Autonomous Agents and Multi-Agent Systems (2002)

In this paper, we consider the problem of data allocation in environments of self-motivated servers, where information servers respond to queries from users. New data items arrive frequently and have to be allocated in the distributed system. The servers have no common interests, and each server is concerned with the exact location of each of the data items. There is also no central controller. We suggest using a negotiation framework which takes into account the passage of time during the negotiation process itself. Using this negotiation mechanism, the servers have simple and stable negotiation strategies that result in efficient agreements without delays. We provide heuristics for finding the details of the strategies which depend on the specific settings of the environment and which cannot be provided to the agents in advance. We demonstrate the quality of the heuristics, using simulations. We consider situations characterized by complete, as well as incomplete, information and prove that our methods yield better results than the static allocation policy currently used for data allocation for servers in distributed systems.
Multiprocessor Fault Diagnosis Under Local Constraints
Authors: A. Das, K. Thulasiraman, V. K. Agarwal, K. B. Lakshmanan
Venue: IEEE Transactions on Computers (1993)

The authors study the fault diagnosis of multiprocessor systems when fault constraints in the local domain of each processor are specified. They use the comparison-based model. A multiprocessor system S is t-in-L diagnosable if, given a syndrome, all faulty processors can be uniquely identified provided there are at most t faulty processors in the local domain L(u/sub i/) union (u/sub i/) of every processor, u/sub i/ in S, where L (u/sub i/) denotes the set of processors adjacent to u/sub i/. Certain basic results that lead to efficient conditions for unique diagnosis of a system when certain fault constraints are satisfied in the local domain of each processor in the system are presented. The t-in-L diagnosability of certain regular interconnected systems is examined under the assumption that less than half of the processors in the system are faulty. Diagnosis algorithms for these systems are presented.
Structural and enumerative properties of the Fibonacci cubes
Authors: Emanuele Munarini, Norma Zagaglia Salvi
Venue: Discrete Mathematics (2002)

The Fibonacci cube represents a new topology for the interconnection of multicomputers. It is a bipartite graph which can be embedded in the Boolean cube. We prove that it is a particular semilattice and determine its structural properties such as the partite sets, the radius, the center, the independence number of vertices. Furthermore, we obtain enumerative properties as a new formula for the Fibonacci numbers.
Progress in Design for Test: A Personal View
Authors: R. G. (Ben) Bennitts
Venue: IEEE Design Test (1994)

The author discusses the history and benefits of design for test. He describes common arguments against it and gives convincing rebuttals to each. In addition, he provides a glimpse into the future of DFT. The problem is that we do not have a measurable parameter that expresses the incremental gain in product quality arising from the addition of some specific DFT technique, compared to its cost of implementation. The author refers to this parameter as the quality improvement factor (Quif), and defines it as the benefit versus the cost of the DFT technique.
Cache Memory Design for Internet Processors
Authors: Tzi-cker Chiueh, Prashant Pradhan
Venue: IEEE Micro (2000)

We evaluate a series of three progressively more aggressive routing-table cache designs and demonstrate that the incorporation of hardware caches into Internet processors, combined with efficient caching algorithms can significantly improve overall packet forwarding performance.
In situ study of strain evolution during thin film Ti/AL(Si,Cu) reaction using synchrotron radiation
Authors: C. Rivero, O. Bostrom, P. Gergaud, O. Thomas, P. Boivin, A. Mazuelas
Venue: Microelectronic Engineering (2002)

Stress development and relaxation are important issues for the reliability of integrated circuits. In this article we report on the stress evolution during solid state reaction, which occurs in Ti/Al bilayers. Whereas the formation of TiAl3 is expected to induce large tensile stress because of a global volume decrease of 6-8%, our in-situ X-ray diffraction measurements during annealing at 465 °C indicate the formation of a compressive compound. Furthermore, an increase in the lattice parameter of Ti is evidenced by X-ray diffraction. A plausible explanation for this expansion is the incorporation of O in solution from a reaction with the underlying SiO2 layer.
Computing the Shortest Network under a Fixed Topology
Authors: Guoliang Xue, K. Thulasiraman
Venue: IEEE Transactions on Computers (2002)

We show that, in any given uniform orientation metric plane, the shortest network interconnecting a given set of points under a fixed topology can be computed by solving a linear programming problem whose size is bounded by a polynomial in the number of terminals and the number of legal orientations. When the given topology is restricted to a Steiner topology, our result implies that the Steiner minimum tree under a given Steiner topology can be computed in polynomial time in any given uniform orientation metric with $\big. \lambda\bigr.$ legal orientations for any fixed integer $\big. \lambda \ge 2\bigr.$. This settles an open problem posed in a recent paper [3].
Efficient canonical form for boolean matching of complex functions in large libraries
Authors: Jovanka Ciric, Carl Sechen
Venue: Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design (2001)

A new algorithm is developed which transforms the truth table or implicant table of a Boolean function into a canonical form under any permutation of inputs. The algorithm is used for Boolean matching for large libraries that contain cells with large numbers of inputs and implicants. The minimum cost canonical form is used as a unique identifier for searching for the cell in the library. The search time is nearly constant if a hash table is used for storing the cells' canonical representations in the library. Experimental results on more than 100,000 gates confirm the validity and feasible run-time of the algorithm.
Compressing polygon mesh geometry with parallelogram prediction
Authors: Martin Isenburg, Pierre Alliez
Venue: Proceedings of the conference on Visualization '02 (2002)

In this paper we present a generalization of the geometry coder by Touma and Gotsman [34] to polygon meshes. We let the polygon information dictate where to apply the parallelogram rule that they use to predict vertex positions. Since polygons tend to be fairly planar and fairly convex, it is beneficial to make predictions within a polygon rather than across polygons. This, for example, avoids poor predictions due to a crease angle between polygons. Up to 90 percent of the vertices can be predicted this way. Our strategy improves geometry compression by 10 to 40 percent depending on (a) how polygonal the mesh is and (b) on the quality (planarity/convexity) of the polygons.
Detection of Dimension Sets in Engineering Drawings
Authors: C. P. Lai, R. Katsuri
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1994)

This correspondence presents a system for detecting dimension sets in engineering drawings that are drawn to ANSI drafting standards. A new rule-based text/graphics separation algorithm and a model-based procedure for detecting arrowheads in any orientation have been developed. Arrowhead tracking and search methods are used to extract leaders, tails, and witness lines from segmented images containing only graphics. Text blocks and feature control frames extracted from the segmented images are than associated with their corresponding leaders to obtain complete dimension sets. Experimental results are presented.
The Lucas property of a number array
Authors: Marko Razpet
Venue: Discrete Mathematics (2002)

For all nonnegative integers i,j let w(i, j|a, b,c) denote the number of all paths in the plane from (0,0) to (i,j) with steps (1,0), (0, 1), (1, 1), and with positive integer weights a, b, c, respectively. The divisibility property of the array w(i, j |a, b, c) is studied. The notation of the Lucas property is introduced.Let p be a prime and let w(i,j|a, b,c) denote the remainders of dividing w(i,j|a, b,c) by p where 0 ≤ w(i, j|a, b,c) < p. The Lucas property of w(i,j|a,b,c) explains the self-similar pattern of w(i,j|a, b, c). The principal clusters of higher orders are generated by the tensor powers of the principal cell containing w(i, j|a, b,c) where 0 ≤ i < p and 0 ≤ j < p.
An Efficient Modular Spare Allocation Scheme and Its Application to Fault Tolerant Binary Hypercubes
Authors: M. S. Alam, R. G. Melhem
Venue: IEEE Transactions on Parallel and Distributed Systems (1991)

Consideration is given to fault tolerant systems that are built from modules called fault tolerant basic blocks (FTBBs), where each module contains some primary nodes and some spare nodes. Full spare utilization is achieved when each spare within an FTBB can replace any other primary or spare node in that FTBB. This, however, may be prohibitively expensive for larger FTBBs. Therefore, it is shown that for a given hardware overhead more reliable systems can be designed using bigger FTBBs without full spare utilization than using smaller FTBBs with full spare utilization. Sufficient conditions for maximizing the reliability of a spare allocation strategy in an FTBB for a given hardware overhead are presented. The proposed spare allocation strategy is applied to two fault tolerant reconfiguration schemes for binary hypercubes. One scheme uses hardware switches to replace a faulty node, and the other scheme uses fault tolerant routing to bypass faulty nodes in the system and deliver messages to the destination node.
Visual-Language System for User Interfaces
Authors: Shi-Kuo Chang, Gennaro Costagliola, Giuliano Pacini, Maurizio Tucci, Genoveffa Tortora, Bing Yu, Jing-sheng Yu
Venue: IEEE Software (1995)

We present an experimental software system to design, specify and interpret customized visual languages for different applications. The system consists of two major subsystems: the visual language compiler and the visual language generator. The experimental system is capable of parsing and interpreting visual sentences, and generating a customized visual language from sample visual sentences. Three parsers are supported: a general visual language parser, a fuzzy visual language parser, and a positional grammar parser. Two approaches of specifying semantics are supported: by semantic routines, or by semantic tables. The experimental system has been implemented on IBM PCs and SUN workstations, and applied to visual queries for information retrieval, and the design of iconic languages for augmentative communication.
Correctness properties in a shared-memory parallel language
Authors: Gilbert Caplain
Venue: Journal of the ACM (JACM) (2002)

We study a property of correctness of programs written in a shared-memory parallel language. This property is a semantic equivalence between the parallel program and its sequential version, that we define. We consider some standard parallel imperative language. Within this language, this correctness property follows from the preservation of data dependences by the control flow and the synchronizations. Our result makes use of the semantics of the sequential version only. Hence, through our result, checking the correctness of some parallel program boils down to verifying properties of some sequential program.
Exploiting Intermediate Sparsity in Computing Derivatives for a Leapfrog Scheme
Authors: Christian H. Bischof, H. Martin Bücker, Po-Ting Wu
Venue: Computational Optimization and Applications (2003)

The leapfrog scheme is a commonly used second-order method for solving differential equations. If Z(t) denotes the state of a system at a particular time step t, this integration scheme computes the state at the next time step as Z(t + 1) &equals; H(Z(t), Z(t &minus; 1), W), where H is the nonlinear timestepping operator and W are parameters that are not time-dependent. In this note, we show how the associativity of the chain rule of differential calculus can be used to expose and exploit intermediate derivative sparsity arising from the typical localized nature of the operator H. We construct a computational harness that capitalizes on this structure while employing automatic differentiation tools to automatically generate the derivative code corresponding to the evaluation of one time step. Experimental results with a 2-D shallow water equations model on IBM RS/6000 and Sun SPARCstations illustrate these issues.
Further notes for a self-study course in block-cipher cryptanalysis
Authors: Raphael Chung-Wei Phan
Venue: Cryptologia (2002)

To every aspiring cryptanalyst, especially those just starting to study cryptanalysis, there is no standard textbook to refer. A year ago, the existing literature on block-cipher cryptanalysis was organized in a self-study course in a way that could help students learn cryptanalysis step by step.[5] Since then, various new cryptanalytic methods have sprung up and have been added to the cryptanalytic literature. This paper attempts to acquaint the student with the new cryptanalytic methods and serve as further notes to the course in block-cipher cryptanalysis.
Hypertext: The Next Maintenance Mountain
Authors: Pearl Brereton, David Budgen, Geoff Hamilton
Venue: Computer (1998)

For many organizations today, maintaining hypertext documents is becoming a burdensome task in its own right. The development process for hypertext documents is also starting to resemble that of software, with increasingly complex analysis of hypertext documents' ability to meet an organization's needs, well-planned design and implementation, and follow-up testing for consistency and effectiveness. Software maintenance is a major problem, and hypertext documents share many of the characteristics of software. Yet according to the authors' review of the summaries of 52 Web development tools, only six contained maintenance related terms or features. The situation is made more critical because Web development has attracted a mixed community of professional and nonprofessional developers. In this article, the authors compare the characteristics of software and hypertext documents. They derive lessons from software development that can be applied to the creation and maintenance of hypertext documents, in terms of structure, reuse, testing, version management, development tools, and development processes.
The Changing Role of Information Technology in Manufacturing
Authors: Krishnamurthy Srinivasan, Sundaresan Jayaraman
Venue: Computer (1999)

Today's manufacturing enterprise, whether it produces consumer goods or weapons systems, must often juggle a range of conflicting demands. Smaller lot sizes, increased product flexibility, higher product quality, decreased delivery time, and smaller profit margins are typical of the ambitious goals in many such organizations. Through it all, the enterprise must consistently aim for the five R's-- produce the right product, with the right quality, in the right quantity, at the right price, and at the right time-- and it must do more than satisfy its customers; it must delight them. Correct and timely information is key to meeting these goals, and information technology-- database management systems, enterprise resource planning systems, and simulation and computer-aided design tools-- has become indispensable to most manufacturing enterprises. Although its role in manufacturing has been more to support processes, IT is evolving to become a catalyst for process and product change. In this case study, an apparel manufacturer used a modeling framework developed by Georgia Tech to implement multiple IT solutions. It was then able to rapidly shift production resources between two separate product lines. IT is at the heart of successful enterprises worldwide, and manufacturing enterprises are no exception. Terry Manufacturing, the case study for this article, successfully implemented its IT strategy, thereby enabling itself to effect a significant transformation in operations and remain in business as a viable and reliable model supplier to both the defense and civilian markets.
Nonnumeric search results on the EM-4 distributed-memory multiprocessor
Authors: Andrew Sohn, Mitsuhisa Sato, Shuichi Sakai, Yuetsu Kodama, Yoshinori Yamaguchi
Venue: Proceedings of the 1994 ACM/IEEE conference on Supercomputing (1994)

Numeric scientific problems have been the main focus of supercomputing as their numerous implementations on various multiprocessors indicate. Nonnumeric problems on the other hand have received very little attention for parallel implementation due to their irregular behaviors and a large amount of resource usage. This report presents our experiences implementing difficult nonnumeric problems on the EM-4 multiprocessor, believing that supercomputers should also be able to effectively execute nonnumeric problems if they are to be considered 'supercomputers.' We selected two typical search problems, the Eight-Puzzle and the Tower-of-Hanoi. Two parallel search techniques are used to implement the search problems, unidirectional and bidirectional heuristic search. A total of eight different programs has been implemented on the EM-4 multiprocessor with realistic problem sizes. Execution results demonstrate that the parallel bidirectional heuristic search can solve the tree depth 20 to 40 of the Eight-Puzzle in an optimal or near optimal number of iterations in less than two seconds, and is highly scalable as it gives over 40-fold speedup for both problems on 80 processors.
Investigating anytime algorithms for future distance warning systems
Authors: K. Sobottka, H. Bunke
Venue: Real-Time Imaging (2002)

Most road-accidents are caused by a driver not paying attention to the traffic situation. This problem can be solved by assistance systems which warn the driver of potential dangers. Recent progress in sensor technology makes range sensors very attractive for automotive applications, but up to now little research has been done into the interpretation of range image sequences in outdoor environments. In this article an overall approach to the analysis of range image sequences for use in future distance warning systems is presented. A method for obstacle detection is described using radial slope evaluation and 3D connected component analysis. For obstacle tracking a new approach based on an anytime algorithm is proposed. This algorithm has an interpretation of the input data, possibly sub-optimal, ready whenever it is stopped and improves the interpretation with additional computing time. The different approaches proposed in this paper have been tested on a data set of 11 range image sequences consisting of 595 frames in total. Experimental results reveal that a reliable interpretation can be obtained in real time.