ppxscal/embedding_network huggingface dataset:
Theory and Applications of Telemedicine
Authors: Nihal Fatma Güler, Elif Derya Übeyli
Venue: Journal of Medical Systems (2002)

In this study, telemedicine and the use of advanced telemedicine technologies are explained. Telemedicine is the use of modern telecommunications and information technologies for the provision of clinical care to individuals at a distance, and transmission of information to provide that care. Telemedicine can be used for decision making, remote sensing, and collaborative arrangements for the real-time management of patients at a distance. The use of telecommunications and information technologies in providing health services is determined. Telemedicine is described as combination of topics from the fields of telecommunication, medicine, and informatics. The medical systems infrastructure consisting of the equipment and processes used to acquire and present clinical information and to store and retrieve data are explained in details. The challenges existing in telemedicine development in different countries are given. Technological, political, and professional barriers in applications of telemedicine are defined. An investigation of telemedicine applications in various fields is presented, and enormous impact of telemedicine systems on the future of medicine is determined.
Comparative Performance Evaluation of Hot Spot Contention Between MIN-Based and Ring-Based Shared-Memory Architectures
Authors: Xiaodong Zhang, Yong Yan, Robert Castañeda
Venue: IEEE Transactions on Parallel and Distributed Systems (1995)

Hot spot contention on a network-based shared-memory architecture occurs when a large number of processors try to access a globally shared variable across the network. While Multistage Interconnection Network (MIN) and Hierarchical Ring (HR) structures are two important bases on which to build large scale shared-memory multiprocessors, the different interconnection networks and cache/memory systems of the two architectures respond very differently to network bottleneck situations. In this paper, we present a comparative performance evaluation of hot spot effects on the MIN-based and HR-based shared-memory architectures. Both nonblocking MIN-based and HR-based architectures are classified, and analytical models are described for understanding network differences and for evaluating hot spot performance on both architectures. The analytical comparisons indicate that HR-based architectures have the potential to handle various contentions caused by hot spots more efficiently than MIN-based architectures. Intensive performance measurements on hot spots have been conducted on the BBN TC2000 (MIN-based) and the KSR1 (HR-based) machines. Performance experiments were also conducted on the practical experience of hot spots with respect to synchronization lock algorithms. The experimental results are consistent with the analytical models, and present practical observations and an evaluation of hot spots on the two types of architectures.
Rivest-Vuillemin conjecture is true for monotone boolean functions with twelve variables
Authors: Sui-Xiang Gao, Ding-Zhu Du, xiao-Dong Hun, Xiaohua Jia
Venue: Discrete Mathematics (2002)

A Boolean function f(x1,x2,...,xn) is elusive if every decision tree computing f must examine all n variables in the worst case. It is a long-standing conjecture that every nontrivial monotone weakly symmetric Boolean function is elusive. In this paper, we prove this conjecture for Boolean functions with twelve variables.
A comparative study of the Benes filtering problem
Authors: A. Farina, D. Benvenuti, B. Ristic
Venue: Signal Processing (2002)

This paper studies a non-linear filter due to Benes for which the optimum solution is known. The paper compares the estimation performance of Benes filter to those of well-known approximate filters: the Extended Kalman, the statistical linearisation and the particle filtering. The performance of all these four filters are also compared to the Cramer-Rao lower bound. Thus, the Benes filter is a yardstick to rank the above-mentioned known techniques in terms of performance and computational cost which solve in an approximate manner the problem solved in an optimum way by Benes. This class of non-linear filtering problem has an interest in application problems like the target tracking.
Point based rendering of non manifold surfaces
Authors: Huw Jones, Ron J. Balsys, Kevin G. Suffernt
Venue: Proceedings of the 1st international conference on Computer graphics and interactive techniques in Australasia and South East Asia (2003)

We present a point based rendering technique that uses iterated function systems to render arbitrary parametric and implicit surfaces with singularities and non manifold features, to the pixel precision of the image. Its advantage over existing point based techniques is the simplicity of its implementation but in this form it is slow. It only requires evaluations of the surface functions and gradients to render shaded images. The technique also allows for hidden surface elimination using a z-buffer and shadow casting using a shadow buffer.
EX5505E: Microsoft Exchange Server 5.5 : Configuring Exchange Components II
Authors: Smartforce
Venue:  (1998)

:General InformationCourse Duration: 5 hoursAudience: System and network administrators; consultants who will configure and implement Exchange Server 5.5; those who will be sitting the Microsoft Certified System Engineer examsPrerequisites: The Completion of all preceding courses in the Microsoft Exchange Server 5.5 curriculum, and an understanding of computers, operating systems, networks, and Windows NTcourseTopics Covered System Attendant and Address Book Views:System Attendant configurationAddress Book Views The Server property pages:The Server property pagesCreating and configuring mailboxes: Creating mailboxesConfiguring a mailbox Custom recipients and distribution lists:Custom recipientsDistribution listsMinimum Requirements to run SmartForce products:486/33 processor or higher8MB of RAMVGA display (256 colors recommended)10-20MB of hard disk spaceDOS version 3.1 or higherWindows version 3.1/Windows 95Supported Network Operating Systems:Novell NetWare 3.1x/4.1xWindows NT 3.51/4.0OS/2 LAN ManagerBanyan VinesCourse Aim To enable the student to configure the System Attendant and Address Book Views, and to create recipientLearning Objectives After taking this course, the student should be ableto:Discuss the functions of the System AttendantDescribe how to configure the System AttendantExplain what an Address Book View is Discuss how to create and manage Address Book ViewsDescribe how to configure the Server property pagesExplain how to create and configure recipientsCourse Incorporates: Test, hands-on exercises The ACM Portal is published by the Association for Computing Machinery. Copyright © 2010 ACM, Inc. Terms of Usage Privacy Policy Code of Ethics Contact Us Useful downloads: Adobe Acrobat QuickTime Windows Media Player Real Player
Development and Application of Expert Systems in Audit Services
Authors: E. L. Denna, J. V. Hansen, R. D. Meservy
Venue: IEEE Transactions on Knowledge and Data Engineering (1991)

The authors evaluate research and development in the design of expert systems for the audit domain, providing an overview of the domain of expert judgment involved in the audit process. A framework used to present and analyze work to date and to guide future efforts is constructed. Methods of knowledge acquisition being used to develop audit applications are examined. The authors address knowledge representation for the audit domain. Most systems developed for auditing are rule-based systems. Currently, however, other representational forms are being tested that may be more appropriate for dealing with audit complexity. Progress being made in expert system validation is considered, and the current state of development and directions for future efforts are briefly discussed.
Multiprocessor Implementation of Digital Filtering Algorithms Using a Parallel Block Processing Method
Authors: W. Sung, S. K. Mitra, B. Jeren
Venue: IEEE Transactions on Parallel and Distributed Systems (1992)

An efficient real-time implementation of digital filtering algorithms using a multiprocessor system in a ring network is investigated. This method is based on a parallel block processing approach, where a continuously supplied input data is divided into blocks, and the blocks are processed concurrently by being assigned to each processor in the system. This approach requires only a simple interconnection network and reduces significantly the number of communications among the processors, making the system easily expandable and highly efficient. In addition, various digital signal processing algorithms can be implemented on the same multiprocessor system. The data dependency of the blocks to be processed concurrently brings on dependency problems between the processors. A systematic scheduling method has been developed by using a precedence graph for the analysis of the dependency relation. Methods for solving the dependency problems between the processors are also investigated. Implementation procedures and results for FIR, recursive, and adaptive filtering algorithms are illustrated.
Continuous generated associative aggregation operators
Authors: T. Calvo, R. Mesiar
Venue: Fuzzy Sets and Systems (2002)

Continuous generated associative aggregation operators are discussed. The only asymmetric solutions are the trivial operators of the projection to the first or the last coordinate, respectively. The only nontrivial convenient aggregation operators are necessarily symmetric and they are either continuous Archimedean t-norms and t-conorms, or generated nullnorms. The latter may combine any nilpotent t-conorm and any t-norm with any prescribed annihilator k ∈ ]0, 1[.
QuadTIN: quadtree based triangulated irregular networks
Authors: Renato Pajarola, Marc Antonijuan, Roberto Lario
Venue: Proceedings of the conference on Visualization '02 (2002)

Interactive visualization of large digital elevation models is of continuing interest in scientific visualization, GIS, and virtual reality applications. Taking advantage of the regular structure of grid digital elevation models, efficient hierarchical multiresolution triangulation and adaptive level-of-detail (LOD) rendering algorithms have been developed for interactive terrain visualization. Despite the higher triangle count, these approaches generally outperform mesh simplification methods that produce irregular triangulated network (TIN) based LOD representations. In this project we combine the advantage of a TIN based mesh simplification preprocess with high-performance quadtree based LOD triangulation and rendering at run-time. This approach, called QuadTIN, generates an efficient quadtree triangulation hierarchy over any irregular point set that may originate from irregular terrain sampling or from reducing oversampling in high-resolution grid digital elevation models.
&epsiv;-Descending Support Vector Machines for Financial Time Series Forecasting
Authors: Francis E. H. Tay, L. J. Cao
Venue: Neural Processing Letters (2002)

This paper proposes a modified version of support vector machines (SVMs), called &epsiv;-descending support vector machines (&epsiv;-DSVMs), to model non-stationary financial time series. The &epsiv;-DSVMs are obtained by incorporating the problem domain knowledge &ndash; non-stationarity of financial time series into SVMs. Unlike the standard SVMs which use a constant tube in all the training data points, the &epsiv;-DSVMs use an adaptive tube to deal with the structure changes in the data. The experiment shows that the &epsiv;-DSVMs generalize better than the standard SVMs in forecasting non-stationary financial time series. Another advantage of this modification is that the &epsiv;-DSVMs converge to fewer support vectors, resulting in a sparser representation of the solution.
Soft News
Venue: IEEE Software (1990)

No abstract available The ACM Portal is published by the Association for Computing Machinery. Copyright © 2010 ACM, Inc. Terms of Usage Privacy Policy Code of Ethics Contact Us Useful downloads: Adobe Acrobat QuickTime Windows Media Player Real Player
Testing Tools
Authors: Mike Lutz
Venue: IEEE Software (1990)

After a brief overview, separate presentations are given on tools that support the testing process in a variety of ways. Some tools simulate the final execution environment as a way of expediting test execution, others automate the development of test plans, and still others collect performance data during execution. The tools address three aspects of the testing process. They provide a controlled environment in which testing can take place as well as test-data control, and some tools actually perform the tests, capturing and organizing the resulting output. The tools covered are: RUTE (Real-Time Unix Text Environment); Xray/DX; TDC (Testing and Debugging Concurrent) Ada; T; Mothra; Specification Analyzer; and Test inc.
Behavioral Simulation of Fractional-N Frequency Synthesizers and Other PLL Circuits
Authors: Michael H. Perrott
Venue: IEEE Design Test (2002)

Two techniques are presented that allow fast and accurate simulation of fractional-N synthesizers. A uniform time step allows implementation of these techniques in various simulationframeworks, such as Verilog, Matlab, and C or C++ programs. The techniques are also applicable to the simulation of other PLL systems, such as clock and data recovery circuits.Fractional-N Frequency Synthersizers provide high-speed frequency sources that can be accurately set with very high resolution--avaluable feature or many communication systems.
Synthesis Steps and Design Models for Codesign
Authors: Tarek Ben Ismail, Ahmed Amine Jerraya
Venue: Computer (1995)

Growing design complexity and an urgent need for early prototypes have become limitations in current electronic systems design. A mature codesign offers advantages to overcome this challenge. Codesign is an emerging approach for the joint development of hardware and software, and is an important part of rapid system prototyping. It includes partitioning, communication synthesis, and virtual prototyping. Starting from a system-level specification, codesign produces a heterogeneous architecture containing software, hardware, and communication modules. The authors provide a detailed description of Cosmos, a methodology and environment for codesign. The design process in this environment includes four refinement steps: system-level specification, system-level partitioning, communication synthesis (including channel binding and channel mapping), and architecture generation (including virtual prototyping and architecture mapping). Architecture generation includes virtual prototyping and architecture mapping (prototyping). Virtual prototyping produces a system model that can be simulated. Architecture mapping produces an architecture that implements (or emulates) the initial specification. The authors provide a comprehensive description of these steps along with the design models used during the codesign process. Combining the Cosmos model with Solar, a design representation for system-level concepts, allows modular design and design reuse of existing subsystems.
Notes on Multiple Input Signature Analysis
Authors: T. Kameda, S. Pilarski, A. Ivanov
Venue: IEEE Transactions on Computers (1993)

Many results regarding the probability of aliasing for multiple-input compactors have been derived under error assumptions that are not very realistic for VLSI circuits. Recently, the value of aliasing probability has been proven to tend to 2/sup -k/, where k is the number of binary memory elements of the linear compactor. This result is based on the assumption that the compactor is characterized by an irreducible polynomial and that the 'no error' vector has a probability different from zero. In these notes, the above result is generalized. More specifically, it is proved that it is valid if any two error vectors, neither of which needs to be the 'no error' vector, have probabilities of occurrence different from zero. To make the error model complete, the situation in which exactly one error vector has a probability different from zero is also considered. For the latter type of error distributions, the test lengths at which aliasing occurs are determined. Simple proofs for the results are provided; they are based on standard linear algebra notions and well-known theorems.
Arithmetic Co-Transformations in the Real and Complex Logarithmic Number Systems
Authors: Mark G. Arnold, Thomas A. Bailey, John R. Cowles, Mark D. Winkel
Venue: IEEE Transactions on Computers (1998)

The real logarithmic number system, which represents a value with a sign bit and a quantized logarithm, can be generalized to create the complex logarithmic number system, which replaces the sign bit with a quantized angle in a log/polar coordinate system. Although multiplication and related operations are easy in both real and complex systems, addition and subtraction are hard, especially when interpolation is used to implement the system. Both real and complex logarithmic arithmetic benefit from the use of co-transformation, which converts an addition or subtraction from a region where interpolation is expensive to a region where it is easier. Two co-transformations that accomplish this goal are introduced. The first is an approximation based on real analysis of the subtraction logarithm. The second is based on simple algebra that applies for both real and complex values and that works for both addition and subtraction.
Lessons Learned in an Industrial Software Lab
Authors: Albert Endres
Venue: IEEE Software (1993)

The author offers a personal account of the issues and challenges that have confronted the software developer over the last few decades. The failures and successes associated with formal methods, the realities of reuse, and the implementation of development process models and goals are discussed.
Runtime Support and Compilation Methods for User-Specified Irregular Data Distributions
Authors: Ravi Ponnusamy, Joel Saltz, Alok Choudhary, Yuan-Shin Hwang, Geoffrey Fox
Venue: IEEE Transactions on Parallel and Distributed Systems (1995)

This paper describes two new ideas by which a High Performance Fortran compiler can deal with irregular computations effectively. The first mechanism invokes a user specified mapping procedure via a set of proposed compiler directives. The directives allow use of program arrays to describe graph connectivity, spatial location of array elements, and computational load. The second mechanism is a conservative method for compiling irregular loops in which dependence arises only due to reduction operations. This mechanism in many cases enables a compiler to recognize that it is possible to reuse previously computed information from inspectors (e.g., communication schedules, loop iteration partitions, and information that associates off-processor data copies with on-processor buffer locations). This paper also presents performance results for these mechanisms from a Fortran 90D compiler implementation.
Key-Dependent S-Boxes and Differential Cryptanalysis
Authors: S. Murphy, M. J. B. Robshaw
Venue: Designs, Codes and Cryptography (2002)

Key-dependent S-boxes gained some prominence in block cipher design when Twofish became an AES finalist. In this paper we make some observations on how the cryptanalyst might work with key-dependent S-boxes, we begin to develop a framework for the differential cryptanalysis of key-dependent S-boxes, and we introduce some basic techniques that were used in an analysis of reduced-round Twofish.
Understanding Integrated Circuits
Authors: Gregory H. Chisholm, Steven T. Eckmann, Christopher M. Lain, Robert L. Veroff
Venue: IEEE Design Test (1999)

Reverse engineering is the inverse of the design process. The design process begins with an abstract description of a target device and, via a succession of refinements, produces a design that can be implemented directly. Reverse engineering, on the other hand, begins with the disassembly of a manufactured device and culminates with an abstract description of the device's functionality. In the case of integrated circuits, the disassembly process consists of obtaining an image of the internal structure of a circuit and extracting a transistor-level netlist from the image. This description is then transformed to successively higher levels of abstraction until a suitably high-level description of the circuit's behavior is obtained.Much has been written about methods for obtaining images ¾ for example, sample preparation via chemical etching and image acquisition via scanning-electron-microscopy ¾ and about extracting information from images ¾ for example, techniques for automated component identification via pattern recognition. There appears, however, to be little written about deriving an understanding of a circuit's behavior from a detailed circuit description. This tutorial describes an approach to one aspect of this problem ¾ deriving a module-level description from a gate-level netlist. The approach includes a number of transformations, based on well understood properties of circuits, and a set of rules (algorithms and heuristics) for applying the transformations in a computationally feasible way.
Microsoft Windows 98 Companion, 1st edition
Authors: Martin Matthews, Microsoft Corporation
Venue:  (1998)

:Microsoft Windows 98 Companion introduces you to Microsoft Windows 98 and shows you how to use it to your best advantage. Starting from the ground up, you'll learn Windows basics such as working with dialog boxes and using the mouse, move on to working with the Active Desktop(TM) and using the file folder structure, and progress to working with Windows 98 on a network. Experience Level: Beginner/ Intermediate
Path Signatures: A Way to Speed Up Recursion in Relational Databases
Authors: Jukka Teuhola
Venue: IEEE Transactions on Knowledge and Data Engineering (1996)

Composite objects often involve recursive relationships, so called bills-of-materials, which are cumbersome to handle in relational database systems. The relationships constitute a directed graph, where the successors of a node represent its components, recursively. Instead of the whole transitive closure (all ancestor-descendant pairs), the task is here to retrieve the descendants of any given node. A simple relational solution is suggested, which packs information of the ancestor path of each node into a fixed-length code, called the signature. The code is nonunique, and its purpose is to define a relatively small superset of the descendants, as well as establish a basis for clustering. It supports effective retrieval of the descendants, in terms of both disk accesses and DBMS calls. The method performs best for tree-structured graphs, where the processing time typically decreases by a factor of more than 10, compared to a simple loop of joins. Also general directed graphs, both acyclic and cyclic, can be processed more effectively. The method is implemented on top of a relational system, but advantages can be gained on other platforms, too.