ppxscal/embedding_network huggingface dataset:
Finite element analysis of bubbly flow around an oscillating square-section cylinder
Authors: Tomomi Uchiyama
Venue: Finite Elements in Analysis and Design (2002)

The bubbly flow around a square-section cylinder, which is forced to oscillate normal to a uniform flow, is simulated by an incompressible two-fluid model. The model is solved by the Arbitrary Lagrangian-Eulerian (ALE) finite element method. The width of the cylinder is 30 mm. A bubbly flow is assumed, and the bubble diameter is set as 1 mm. The volumetric fraction of the gas-phase upstream of the cylinder is 0.05, where the Reynolds number defined by the volumetric velocity of the liquid-phase is 200. With an increment in the cylinder oscillation frequency Sc, the vortex shedding frequency St approaches the Sc value. When the Sc is increased beyond a critical value, the lock-in occurs, in which the vortex shedding is synchronized with the cylinder oscillation. The time-averaged drag coefficient and the root-mean-square of the lift coefficient for the cylinder take their maximum values at the lock-in state. The volumetric fraction of the gas-phase αg is higher in the wake of the cylinder, irrespective of the Sc value. The αg value is lower below the lock-in state and higher in the lock-in state than the value for the stationary cylinder.
Diagnosis by Signature Analysis of Test Responses
Authors: M. G. Karpovsky, L. B. Levitin, F. S. Vainstein
Venue: IEEE Transactions on Computers (1994)

Proposes a new approach for identification of faulty processing elements based on an analysis of the compressed test response of the system. The test response is compressed first in space and then in time, and faulty processing elements are identified by hard decision decoding of the corresponding space-time signature. The approach results in considerable savings in hardware required for diagnostics.
Crouching Error, Hidden Markup
Authors: Neville Holmes
Venue: Computer (2001)

Its lack of a versatile and visible markup language can make using Microsoft Word a nightmare-and reflects poorly on our profession.
A Methodology for Debugging ASIC Prototypes in the Field
Authors: David A. Fechser
Venue: IEEE Design Test (1991)

A step-by-step methodology for debugging and solving wafer sort and final-test prototype failures in application-specific integrated circuits (ASICs) is provided. The uses of schmoo plots, datalogs, and fault analysis are described, and a checklist for investigating problems is given. Most of the work can take place at the remote site, using simulators, schematics, and standard information provided by the test engineer.
Convergence Rates of Nonparametric Filtering Estimates in Autoregression Dynamic Systems
Authors: A. V. Dobrovidov
Venue: Automation and Remote Control (2003)

The Bayes problem of filtration of a random process from observations on an autoregression process with coefficients defined by functions of the useful signal is studied. The main assumption asserts that the conditional observation densities belong to a family of conditional exponential densities with known functions of observations and useful signal, whose distribution is not known in advance. Optimal signal filtering equations and empirical risk estimates are derived. Regularized nonparametric filtering estimates are derived and a theorem on the mean-square convergence and convergence rates of these estimates is formulated.
European Trends in Library Development
Authors: Jean Pierre Moreau, Joseph Borel, Davoud Samani
Venue: IEEE Micro (1992)

The time-to-market and cost constraints of designing VLSI circuits, together with increasing complexity, necessitate a structured design methodology. Such a methodology should be based on an extensive use of libraries of generic components and previously designed macro blocks. An ideal library for modern design strategies that are based on a top-down structured approach is described. The concepts of portability, migratability, and interoperability of libraries are discussed. It is shown that libraries capitalize on knowledge gained over generations of designs, and successful libraries demand a serious effort at standardization.
An analytical parasitic resistance dependent Id-Vd model for planar doped InA1As/InGaAs/InP HEMT using non-linear charge control analysis
Authors: Ritesh Gupta, Abhinav Kranti, S. Haldar, Mridula Gupta, R. S. Gupta
Venue: Microelectronic Engineering (2002)

An analytical parasitic resistance dependent model for the current voltage characteristics for InAlAs/InGaAs/ InP HEMT is proposed. The model uses a new polynomial dependence of sheet carrier concentration on gate voltage to calculate Id-Vd characteristics and has been extended to obtain transconductance, output conductance and cut-off frequency of the device. A maximum cut-off frequency of 83 and 175 GHz was obtained for channel length of 0.25 and 0.1 µm, respectively. Close agreement with published results confirms the validity of our approach.
Efficient Cost Models for Spatial Queries Using R-Trees
Authors: Yannis Theodoridis, Emmanuel Stefanakis, Timos Sellis
Venue: IEEE Transactions on Knowledge and Data Engineering (2000)

Selection and join queries are fundamental operations in Data Base Management Systems (DBMS). Support for nontraditional data, including spatial objects, in an efficient manner is of ongoing interest in database research. Toward this goal, access methods and cost models for spatial queries are necessary tools for spatial query processing and optimization. In this paper, we present analytical models that estimate the cost (in terms of node and disk accesses) of selection and join queries using R-tree-based structures. The proposed formulae need no knowledge of the underlying R-tree structure(s) and are applicable to uniform-like and nonuniform data distributions. In addition, experimental results are presented which show the accuracy of the analytical estimations when compared to actual runs on both synthetic and real data sets.
An Efficient Algorithm for Out-of-Core Matrix Transposition
Authors: J. Suh, V. K. Prasanna
Venue: IEEE Transactions on Computers (2002)

Efficient transposition of Out-of-core matrices has been widely studied. These efforts have focused on reducing the number of I/O operations. However, in state-of-the-art architectures, memory-memory data transfer time and index computation time are also significant components of the overall time. In this paper, we propose an algorithm that considers the index computation time and the I/O time and reduces the overall execution time. Our algorithm reduces the total execution time by reducing the number of I/O operations and eliminating the index computation. In doing so, two techniques are employed: writing the data onto disk in predefined patterns and balancing the number of disk read and write operations. The index computation time, which is an expensive operation involving two divisions and a multiplication, is eliminated by partitioning the memory into read and write buffers. The expensive in-processor permutation is replaced by data collection from the read buffer to the write buffer. Even though this partitioning may increase the number of I/O operations for some cases, it results in an overall reduction in the execution time due to the elimination of the expensive index computation. Our algorithm is analyzed using the well-known Linear Model and the Parallel Disk Model. The experimental results on Sun Enterprise, SGI R12000, and Pentium III show that our algorithm reduces the overall execution time by up to 50 percent compared with the best known algorithms in the literature.
Functionally Testable Path Delay Faults on a Microprocessor
Authors: Wei-Cheng Lai, Angela Krstic, Kwang-Ting (Tim) Cheng
Venue: IEEE Design Test (2000)

We address the problem of testing path delay faults in a microprocessor using instructions. It is observed that a structurally testable path (i.e., a path testable through at-speed scan) in a microprocessor might not be testable by its instructions. This is because no instruction sequence can produce a test sequence which can sensitize the path and capture the fault effect into the destination output/flip-flop at-speed. These paths are called functionally untestable paths. We discuss the impact of delay defects on the functionally untestable paths on the overall circuit performance. Identification of such paths helps determine the achievable path delay fault coverage and reduce the subsequent test generation effort. The experimental results for two microprocessors (Parwan and DLX ) indicate that a significant percentage of structurally testable paths are functionally untestable.
An Empirical Analysis of the IEEE-1394 Serial Bus Protocol
Authors: Dan Steinberg, Yitzhak Birk
Venue: IEEE Micro (2000)

The Statistics Collector and Analyzer records, displays, and analyzes performance measurements from an active IEEE-1394 bus in real time. An empirical analysis using SCA exposes the unique, complex arbitration mechanisms used by IEEE-1394 nodes and their effect on the performance of higher level protocols.
An Efficient Data Dependence Analysis for Parallelizing Compilers
Authors: Z. Li, P. C. Yew, C. Q. Zhu
Venue: IEEE Transactions on Parallel and Distributed Systems (1990)

A novel algorithm, called the lambda test, is presented for an efficient and accurate data dependence analysis of multidimensional array references. It extends the numerical methods to allow all dimensions of array references to be tested simultaneously. Hence, it combines the efficiency and the accuracy of both approaches. This algorithm has been implemented in Parafrase, a Fortran program parallelization restructurer developed at the University of Illinois at Urbana-Champaign. Some experimental results are presented to show its effectiveness.
Dissipation and quantum fluctuations in 2d-array of small Josephson junctions
Authors: Youiti Ootuka, Yamaguchi Takahide, Hisao Miyazaki, Akinobu Kanda
Venue: Microelectronic Engineering (2002)

The transport properties of two-dimensional arrays of small Josephson junctions shunted with ohmic resistors are investigated. The zero-temperature phase diagram shows a phase transition driven by quantum fluctuations and dissipation. The recovery of Josephson-like current by the dissipation is discussed.
Topological Equivalence of Dicritical Holomorphic Vector Fields
Authors: M. I. Camacho, R. M. B. Tome
Venue: Journal of Dynamical and Control Systems (1998)

In this paper we study the topological equivalence between holomorphic vector fields with dicritical isolated singularity and without singularities at the divisor.
TNet: A Reliable System Area Network
Authors: Robert W. Horst
Venue: IEEE Micro (1995)

TNet is a new system area network designed to support current and future needs for reliable, efficient communications among processors and peripherals. It is an extensible hardware/software layer that allows very large configurations by logically and physically isolating the processor busses from the I/O busses. TNet is a wormhole-routed, packet-switched, point-to-point, system area network. The first implementation has full-duplex, byte-serial links with electrical interfaces supporting either backplane connections or inter-cabinet cables. Variable length packets contain up to 64-bytes of data per packet. TNet transactions consist of pairs of request-response packets allowing data to either be pushed or pulled across the network. The network is designed to support many simultaneous, low-latency, DMA transfers for both inter-processor communications and I/O.
Collective Communication in Wormhole-Routed Massively Parallel Computers
Authors: Philip K. McKinley, Yih-jia Tsai, David F. Robinson
Venue: Computer (1995)

The supercomputer market is now dominated by parallel architectures, among which massively parallel computers (MPCs) are an important class of systems. The memory of an MPC is physically distributed among an ensemble of computing nodes that communicate by sending data through a network. Communication operations can be either point-to-point, with one source and one destination, or collective, with more than two participating processes. The design of collective communication operations depends on the MPC's underlying network architecture. While there has been little consensus on some aspects of communication architectures, such as network topology, a good deal of agreement exists regarding the most efficient way to switch messages through the network. Most MPCs use wormhole routing, in which each message is divided into small pieces that are pipelined through the network. Compared with the store-and-forward switching method used in early multicomputers, wormhole routing reduces the effect of path length on communication time. However, in situations where multiple messages exist in the network concurrently, wormhole routing can exacerbate channel contention, which occurs when blocked messages hold some communication channels while waiting for others. Invoking a collective operation, which can involve many messages, poses this situation. In recent years, many projects have addressed the design of efficient collective communication algorithms for wormhole-routed systems. By exploiting the relative distance-insensitivity of wormhole routing, these new algorithms often differ fundamentally from their store-and-forward counterparts. This article examines software and hardware approaches to implementing collective communication operations, illustrating several issues arising in this research area and describing the major classes of algorithms proposed to solve these problems.
An Integrated Multicomponent Synthesis Environment for MCMs
Authors: Ranga Vemuri, Nand Kumar, RaghVutukuruu, Prasad Subba Rao, Praveen Sinha, Ning Ren, Paddy Mamtora, Ram Mandayam, Ram Vemuri, Jayanta Roy
Venue: Computer (1993)

The multicompact synthesis (MSS) integrated design environment for multichip modules (MCMs) is discussed. The MSS environment is centered in VHDL (very-high-speed integrated circuit hardware description language), WAVES (waveform and vector exchange specification), and PDL (performance description language). MSS provides four levels of automated synthesis support all the way from the behavioral level to MCM placement and routing, three levels of simulation support including behavioral, register, and switch levels, and tools for automated test-bench compilation and design validation for all synthesized designs. Three tutorial examples illustrate MSS algorithms and results. The primary example is the Find, which performs a bubble sort followed by binary search. It is used as the running example because it is small. Such small specifications, however, do not require MCMs. Two larger examples, the Move Machine and the Viper Microprocessor, are used to illustrate the results.
A Deterministic Built-In Self-Test Generator Based on Cellular Automata Structures
Authors: Samir Boubezari, Bozena Kaminska
Venue: IEEE Transactions on Computers (1995)

This paper proposes a new approach for designing a cost-effective, on-chip, deterministic, built-in, self-test generator. Given a set of precomputed test vectors (obtained by an ATPG tool) with a predetermined fault coverage, a simple test vector generator (TVG) is synthesized to apply the given test set in a minimal test time. To achieve this objective, cellular automata (CA) structures have been used in which the rule space is not limited to the linear rules commonly used in CA studies recently. Based on some new notations and new formulations of CA properties, two techniques are developed to synthesize such a TVG which is used to generate an ordered/unordered deterministic test vector set. The resulting TVG is very efficient in terms of hardware size and speed performance, and is very regular and testable. Simulation of various benchmark combinational circuits has given good results when compared to alternative solutions.
Bidirectional Deformable Matching with Application to Handwritten Character Extraction
Authors: Kwok-Wai Cheung, Dit-Yan Yeung, Roland T. Chin
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (2002)

To achieve integrated segmentation and recognition in complex scenes, the model-based approach has widely been accepted as a promising paradigm. However, the performance is still far from satisfactory when the target object is highly deformed and the level of outlier contamination is high. In this paper, we first describe two Bayesian frameworks, one for classifying input patterns and another for detecting target patterns in complex scenes using deformable models. Then, we show that the two frameworks are similar to the forward-reverse setting of Hausdorff matching and that their matching and discriminating properties are complementary to each other. By properly combining the two frameworks, we propose a new matching scheme called bidirectional matching. This combined approach inherits the advantages of the two Bayesian frameworks. In particular, we have obtained encouraging empirical results on shape-based pattern extraction, using a subset of the CEDAR handwriting database containing handwritten words of highly varying shape.
The MC68332 Microcontroller
Authors: Joe Jelemensky, Vernon Goler, Brad Burgess, James Eifert, Gary Miller, Les Kohn, Neal Margulis
Venue: IEEE Micro (1989)

The total-system goals, CPU design goals, and modular design approach of the high-performance MC68332 microcontroller are described. The features of the system integration module, queued serial module, and standby RAM are summarized. The CPU and time processor modules are discussed in detail.
Correlation analysis between pattern and non-pattern wafer for characterization of shallow trench isolation-chemical-mechanical polishing (STI-CMP) process
Authors: Sang-Yong Kim, Yong-Jin Seo
Venue: Microelectronic Engineering (2002)

This study is about control of oxide removal amounts on the shallow trench isolation (STI) patterned wafers using removal rate and thickness of blanket (non-patterned) wafers. At first, the removal properties of plasma enhanced tetra-ethyl ortho-silicate (PETEOS) blanket wafers was investigated, and then it was compared with the removal properties and the planarization (step height) as a function of polishing time of the specific STI patterned wafers. We found that there is a relationship between the amount of oxide removal by blanket and patterned wafers. We analyzed this relationship, and the post-CMP thickness of patterned wafers could be controlled by removal rate and removal target thickness of blanket wafers. As the result of correlation analysis, we confirmed that there was the strong correlation between patterned and blanket wafers (correlation factor: 0.7109). So, we could confirm the repeatability as applying to STI CMP process from the linear formula obtained.
A General-Purpose Fuzzy Inference Processor
Authors: Herbert Eichfeld, Martin Klimke, Manfred Menke, Jürgen Nolles, Thomas Künemund
Venue: IEEE Micro (1995)

The SAE 81C99 Fuzzy Inference Processor (FP) exhibits four different operation modes, eight programmable fuzzy algorithms and up to 256 inputs, 64 outputs and 16,384 rules. The chip, fabricated in 1.0 m CMOS technology, can be used as a stand-alone device or as an on-chip module for 8-bit and 16-bit microcontrollers. At 20 MHz crystal frequency, it has a maximum inference speed of 10 million rules/s. Thus, the FP can be applied for even very complex systems and for processes far beyond the millisecond region occuring, e.g., in automotive electronics and pattern recognition.
Definition of a parallel execution model with abstract state machines
Authors: Zsolt Németh
Venue: Acta Cybernetica (2002)

Languages, architectures and execution models are strongly related. A new architectural platform makes necessary to modify the execution model in order to exploit all the advantages of the underlying architecture while preserving its main characteristics. The latter issue requires a careful analysis of the design process. Abstract State Machines offer a powerful method for aiding complex system design. In this paper some aspects of its application are presented by taking the redesign process of a parallel Prolog model as an example.
Multiclass LS-SVMs: Moderated Outputs and Coding-Decoding Schemes
Authors: T. Van Gestel, J. A. K. Suykens, G. Lanckriet, A. Lambrechts, B. De Moor, J. Vandewalle
Venue: Neural Processing Letters (2002)

A common way of solving the multiclass categorization problem is to reformulate the problem into a set of binary classification problems. Discriminative binary classifiers like, e.g., Support Vector Machines (SVMs), directly optimize the decision boundary with respect to a certain cost function. In a pragmatic and computationally simple approach, Least Squares SVMs (LS-SVMs) are inferred by minimizing a related regression least squares cost function. The moderated outputs of the binary classifiers are obtained in a second step within the evidence framework. In this paper, Bayes' rule is repeatedly applied to infer the posterior multiclass probabilities, using the moderated outputs of the binary plug-in classifiers and the prior multiclass probabilities. This Bayesian decoding motivates the use of loss function based decoding instead of Hamming decoding. For SVMs and LS-SVMs with linear kernel, experimental evidence suggests the use of one-versus-one coding. With a Radial Basis Function kernel one-versus-one and error correcting output codes yield the best performances, but simpler codings may still yield satisfactory results.
Hot Chips and Soggy Software
Authors: Stephen C. Johnson
Venue: IEEE Micro (1990)

The author discusses the bottlenecks that impair performance of a computer system and discusses the success of the RISC (reduced-instruction-set computer) approach. He attributes it, at least in part, to the fact that all the seminal work on the RISC chips was carried out in close conjunction with a strong compiler team. He discusses issues that designers of computer systems must consider and examines trends that will affect the optimum design points for future systems. The author then addresses what he refers to as 'soggy software', i.e. the slow pace of progress in software development as compared to hardware, identifying standardization and reuse as necessary components of any solution to the problem.
On Loop Transformations for Generalized Cycle Shrinking
Authors: W. Shang, M. T. O'Keefe, J. A. B. Fortes
Venue: IEEE Transactions on Parallel and Distributed Systems (1994)

This paper describes several loop transformation techniques for extracting parallelism from nested loop structures. Nested loops can then be scheduled to run in parallel so thatexecution time is minimized. One technique is called selective cycle shrinking, and theother is called true dependence cycle shrinking. It is shown how selective shrinking isrelated to linear scheduling of nested loops and how true dependence shrinking is relatedto conflict-free mappings of higher dimensional algorithms into lower dimensionalprocessor arrays. Methods are proposed in this paper to find the selective and truedependence shrinkings with minimum total execution time by applying the techniques offinding optimal linear schedules and optimal and conflict-free mappings proposed by W.Shang and A.B. Fortes.
Itanium Processor Microarchitecture
Authors: Harsh Sharangpani, Ken Arora
Venue: IEEE Micro (2000)

This article describes the microarchitecture of the Itanium(tm) processor, which is the first implementation of the IA-64 instruction set architecture. The processor is optimized to meet a wide range of requirements - high performance on Internet servers and workstations, support for 64bits of addressing, reliability for mission-critical applications, full IA-32 instruction set compatibility in hardware, and scalability across a range of operating systems and platforms