ppxscal/embedding_network huggingface dataset:
Synchronization likelihood: an unbiased measure of generalized synchronization in multivariate data sets
Authors: C. J. Stam, B. W. van Dijk
Venue: Physica D (2002)

The study of complex systems consisting of many interacting subsystems requires the use of analytical tools which can detect statistical dependencies between time series recorded from these subsystems. Typical examples are the electroencephalogram (EEG) and magnetoencephalogram (MEG) which may involve the simultaneous recording of 150 or more time series. Coherency, which is often used to study such data, is only sensitive to linear and symmetric interdependencies and cannot deal with non-stationarity. Recently, several algorithms based upon the concept of generalized synchronization have been introduced to overcome some of the limitations of coherency estimates (e.g. [Physica D 134 (1999) 419; Brain Res. 792 (1998) 24]). However, these methods are biased by the degrees of freedom of the interacting subsystems [Physica D 134 (1999) 419; Physica D 148 (2001) 147]. We propose a novel measure for generalized synchronization in multivariate data sets which avoids this bias and can deal with non-stationary dynamics.
Analysis of 3-D Rotation Fitting
Authors: K. Kanatani
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1994)

Computational techniques for fitting a 3-D rotation to 3-D data are recapitulated in a refined form as minimization over proper rotations, extending three existing methods-the method of singular value decomposition, the method of polar decomposition, and the method of quaternion representation. Then, we describe the problem of 3-D motion estimation in this new light. Finally, we define the covariance matrix of a rotation and analyze the statistical behavior of errors in 3-D rotation fitting.
Reasoning for web document associations and its applications in site map construction
Authors: K. Selçuk Candan, Wen-Syan Li
Venue: Data Knowledge Engineering (2002)

Recently, there is an interest in using associations between Web pages in providing users with pages relevant to what they are currently viewing. We believe that, to enable intelligent decisions, we need to answer the question "for a given set of pages, find out why they are associated". We present a framework for reasoning about Web document associations. We start from the observation that the reasons of the Web page associations are implicitly embedded in the content of the pages as well as the links connecting them. The association reasoning scheme we propose is based on a random walk algorithm. This algorithm can take both link structure and contents into consideration and allows users to specify a focus. We then show how the proposed algorithm, combined with a logical domain identification technique, can be used for Web site summarization and Web site map construction to help users navigate through complex corporate sites. We see that, to achieve this goal, it is essential to recover the Web authors' intentions and superimpose it with the users' retrieval contexts in summarizing Web sites. Therefore, we present a framework, which uses logical neighborhoods, entry pages, and associations of entry pages, in creating context-sensitive summaries and maps of complex Web sites.
Enhancing software reliability with speculative threads
Authors: Jeffrey Oplinger, Monica S. Lam
Venue: ACM SIGPLAN Notices (2002)

This paper advocates the use of a monitor-and-recover programming paradigm to enhance the reliability of software, and proposes an architectural design that allows software and hardware to cooperate in making this paradigm more efficient and easier to program.We propose that programmers write monitoring functions assuming simple sequential execution semantics. Our architecture speeds up the computation by executing the monitoring functions speculatively in parallel with the main computation. For recovery, programmers can define fine-grain transactions whose side effects, including all register modifications and memory writes, can either be committed or aborted under program control. Transactions are implemented efficiently by treating them as speculative threads.Our experimental results suggest that monitored execution is more amenable to parallelization than regular program execution. Code monitoring is sped up by a factor of 1.5 by exploiting single-thread instruction-level parallelism, and by an additional factor of 1.6 using thread-level speculation. This results in an overall improvement of 2.5 times and a sustained 5.4 instructions-per-cycle performance. A monitored execution that used to be 2.5 times slower executes with a degradation of only 12% when compared to the performance on the baseline machine. We also show that the concept of fine-grain transactional programming is useful in catching buffer overrun errors through a number of real-life examples.
Tailoring Cleanroom for Industrial Use
Authors: Robert S. Oshana
Venue: IEEE Software (1998)

In a pilot process improvement program to move from CMM level 3 to level 5, a Raytheon group working on real-time embedded software decided to focus on Cleanroom software engineering technology. The article shares the group's encouraging lessons learned from tailoring Cleanroom to their specific needs. Oshana provides evidence to support their claims of success, but cautions readers who want to employ the same approach to their own organizations because concerns, issues, and barriers do exist.
Analog Nonlinear Function Synthesis
Authors: Olivier Landolt
Venue: IEEE Micro (1996)

Networks of resistors have been identified as interesting devices for analog computation. Since the analytical model of a network of constant resistors is a set of linear equations, such a circuit can be used to solve a large number of linear equations concurrently. Whenever such a resistive embodiment of a computational problem can be found, the resulting circuit is usually very simple, fast and dense compared to CPU-based hardware. Particular problems solved by such networks include simulation of electromagnetic fields, linear image filtering, regularization for image processing, and D/A conversion. Networks of resistors are especially attractive for CMOS integrated circuits, since it has been shown that a circuit obtained by replacing every resistor by a single MOS transistor has exactly the same branch currents as its resistive counterpart.
Virtual Memory: Issues of Implementation
Authors: Bruce Jacob, Trevor Mudge
Venue: Computer (1998)

Virtual memory was developed to automate the movement of program code and data between main memory and secondary storage to give the appearance of a single large store. This technique greatly simplified the programmer's job, particularly when program code and data exceeded the main memory's size. Virtual memory has now become widely used, and most modern processors have hardware to support it.Unfortunately, there has not been much agreement on the form that this support should take. The result of this lack of agreement is that hardware mechanisms are often completely incompatible. Thus, designers and porters of system-level software have two somewhat unattractive choices: They can write software to fit many different architectures or they can insert layers of software to emulate a particular hardware interface. In this article, the authors present the software mechanisms of virtual memory from a hardware perspective and then describe several hardware examples and how they support virtual-memory software. Their focus is to show the diversity of virtual-memory support and, by implication, how this diversity complicates the design and porting of OSs. The authors introduce basic virtual-memory technologies and then compare memory-management designs in three commercial microarchitectures. They show the diversity of virtual-memory support and, by implication, how this diversity can complicate and compromise system operations.
Imagine: Media Processing with Streams
Authors: Brucek Khailany, William J. Dally, Ujval J. Kapasi, Peter Mattson, Jinyung Namkoong, John D. Owens, Brian Towles, Andrew Chang, Scott Rixner
Venue: IEEE Micro (2001)

The power-efficient imagine stream processor achieves performance densities comparable to those of special-purpose embedded processors. Executing programs mapped to streams and kernels, a single imagine processor is expected to have a peak performance of 20 gflops and sustain 18.3 gops on mpeg-2 encoding.
Parallel two level block ILU Preconditioning techniques for solving large sparse linear systems
Authors: Chi Shen, Jun Zhang
Venue: Parallel Computing (2002)

We discuss issues related to domain decomposition and multilevel preconditioning techniques which are often employed for solving large sparse linear systems in parallel computations. We implement a parallel preconditioner for solving general sparse linear systems based on a two level block ILU factorization strategy. We give some new data structures and strategies to construct a local coefficient matrix and a local Schur complement matrix on each processor. The preconditioner constructed is fast and robust for solving certain large sparse matrices. Numerical experiments show that our domain based two level block ILU preconditioners are more robust and more efficient than some published ILU preconditioners based on Schur complement techniques for parallel sparse matrix solutions.
On Trial at the Summer Olympic Games: Smart Cards
Authors: Ware Myers
Venue: Computer (1996)

Smart cards have their genesis in the development of microprocessor and semiconductor memory in the 1970s. Motorola produced a card with a chip--the first smart card--in 1977 for Cartes Bancaires, the French banking association. Since then, Motorola has shipped more than 150 million smart-card microcontrollers, but the market has developed more slowly than some had predicted. The smart-card market has had to wait for advancements in semiconductor hardware, standards, procedures, software, capital, and training. Although 350 million smart cards are in use around the world, few Americans have every used one. The future of the smart card in the US is riding on a high-profile trial at the Olympics. Visa International has teamed up with the three largest banks in the southeastern United States to offer stored-value cards to the four million visitors and residents expected to attend the Olympics in Atlanta this month. Stored-value cards (or cash cards) transfer stored, digital money from the card to merchants' special terminals. Periodically, the merchants transfer the accumulated store to their bank accounts. Smart card technology must be financed; the participants have to raise the necessary capital. Motorola plans to increase its production capacity tenfold, at a cost of billions of dollars, to meet the end-of-century demand for smart cards. This investment must be regained with interest and profit. Almost everyone on earth will eventually have a smart card, but it may take a few decades yet. The governing point is that the rate of growth of smart-card applications depends fundamentally on the rate at which human beings can grow comfortable with the applications, and less on the rate of technical change.
The average-case area of Heilbronn-type triangles
Authors: Tao Jiang, Ming Li, Paul Vitányi
Venue: Random Structures Algorithms (2002)

From among ??? triangles with vertices chosen from n points in the unit square, let T be the one with the smallest area, and let A be the area of T. Heilbronn's triangle problem asks for the maximum value assumed by A over all choices of n points. We consider the average-case: If the n points are chosen independently and at random (with a uniform distribution), then there exist positive constants c and C such that c/n3 < µn < C/n3 for all large enough values of n, where µn is the expectation of A. Moreover, c/n3 < A < C/n3, with probability close to one. Our proof uses the incompressibility method based on Kolmogorov complexity; it actually determines the area of the smallest triangle for an arrangement in "general position."
Direct Rambus Technology: The New Main Memory Standard
Authors: Richard Crisp
Venue: IEEE Micro (1997)

Conventional DRAM architectures have reached their practical upper limit in operating frequency and bus width. Scaling the SDRAM's memory clock from 66MHz to 100MHz operation creates numerous system design issues, but only offers 33% additional peak bandwidth. Direct Rambus(tm) DRAMs (RDRAM(r)) provide 1.6Gigabytes/sec (GB/s) bandwidth from a single DRAM approaching 95% efficiency when subjected to typical multimedia PC main memory workloads. Using a 16-bit data field and a separate 8-bit address and control field, the Direct RDRAM has independent control and scheduling of all row and column resources as well as I/O data. Based on conventional printed circuit board (PCB) and connector technology, Direct RDRAM modules fit seamlessly into the existing mechanical space and airflow environment of the industry standard PC chassis while providing 3x the memory bandwidth of the industry-standard 66MHz SDRAM subsystem. Direct RDRAMs have both high speed and low power operating modes serving the needs of both line-operated and portable products.
Diagnosis and Repair in Multiprocessor Systems
Authors: D. M. Blough, A. Pelc
Venue: IEEE Transactions on Computers (1993)

Diagnosis of multiprocessor systems in which faulty processors can be replaced by spares or repaired is known as sequential diagnosis. A generalization is considered of classical sequential diagnosis, referred to as diagnosis and repair, under a probabilistic model for the faults and test outcomes in a system. It is shown that correct diagnosis and repair of all faulty processors can be achieved with high probability in a large class of systems including, for example, rings, grids, meshes, tori, and hypercubes. These results show, without restrictive assumptions on the behavior of faulty processors, that correct diagnosis can be achieved in these widely used, low-degree systems when a fixed percentage of the processors in the system are faulty.
Shifting Paradigms with the Application Service Provider Model
Authors: Lixin Tao
Venue: Computer (2001)

In the past four decades, several technological breakthroughs have made it feasible to sell computing as a service rather than a product. Supercomputers and clustering technologies have made huge amounts of raw computing power available, while time-sharing operating systems have made computing resources a divisible utility. Personal computers have educated generations of home and office computing users, who now depend on such devices. Meanwhile, the Internet has become the world's largest data and computing-service delivery infrastructure, offering a new platform for net-work-centric computing.Recently, application service providers have begun marketing the ASP model, which uses the Internet or other wide area networks to provide online application services on a rental basis¿commercially delivering computing as a service. For the ASP model to become the computing industry's mainstream paradigm, ASPs must make significant breakthroughs in networking infra-structure, computing technologies, and rental-based cost models and financial services.If it can overcome the challenges facing it, the ASP model will foster a new generation of distributed, component-based computing services.
Virtual Design of Multiengineering Electronics Systems
Authors: Mikko Kerttula, Timo Tokkonen
Venue: Computer (2001)

The authors describe a virtual reality prototyping (VRP) and virtual product design approach that uses a modeling strategy to design, test, and evaluate concepts and products in advance-before creating any physical design models. Their design decisions reflect solutions and practices derived from systems engineering and software engineering research in projects that focused primarily on developing small-sized consumer electronics and telecommunications products such as cellular phones, other personal terminals, set-top boxes, and wrist computers.Close competition has forced companies to focus on tailoring technological products to meet customer preferences in user interface design, usability, and appearance. Often, implementing new features has assumed less importance than creating an optimal product variation for different customer segments in international markets. Modern computer-based systems result from a multidomain development process, and organizing this work requires developers to communicate, cooperate, and coordinate effectively with nonengineering teams. Early linking of product development to other company operations supports this activity.Geographically dispersed development teams must communicate and coordinate effectively. Distance and time differences provide the first obstacles, but businesses also must overcome linguistic and cultural challenges. Extending the use of interactive, functional, and photorealistic 3D product models into other company domains can facilitate effective business practices that cover the entire value chain, from simulated product idea to Web-based customer support of the final product. This wider adoption of the VRP technology and process offers ample scope for further research.
Predicate Caching for Data-Intensive Autonomous Systems
Authors: Nabil N. Kamel
Venue: Computer (1997)

With traditional caching, a system copies data from a slower device to a faster one to improve throughput. With predicate caching, a system applies a predicate to the data on its way from one memory device to another. A predicate, in this context, is any predetermined calculation made by a program. Examples are a numerical integration function, a database SQL query, shortest path calculation in a network, a complex weather calculation, and a sorting program. Predicate caching is especially suited to autonomous systems, such as rule-based systems, expert systems, and autonomous intelligent agents. Some of these systems are data-intensive; that is, they operate against a very large database and respond to numerous, repetitive queries. Predicate caching improves memory utilization and response time of repetitive queries by prestoring partial results in primary memory, which results in minimizing secondary storage access. This article describes the predicate caching technique and, specifically, the page-predicate approach, which is designed to resolve problems of cache partitioning, management, and optimization.
Survival Reliability of Some Double-Loop Networks and Chordal Rings
Authors: Paul E. Wright, Frank K. Hwang
Venue: IEEE Transactions on Computers (1995)

Three of the most well known double-loop networks are the distributed double-loop computer network (DDLCN), the daisy chain, and the braided ring. We compute the exact reliabilities of all three networks. We also extend the results on double-loop networks to directed chordal rings.
CAN for Critical Embedded Automotive Networks
Authors: Lars-Berno Fredriksson
Venue: IEEE Micro (2002)

The controller area network protocol offers flexibility in safety-critical automotive system design. The benefits of using already established specifications will aid automotive system designers in x-by-wire development.
Performance Analysis of Parallelizing Compilers on the Perfect Benchmarks Programs
Authors: W. Blume, R. Eigenmann
Venue: IEEE Transactions on Parallel and Distributed Systems (1992)

The speedups of the Perfect Benchmarks codes that result from automatic parallelizationare reported. The performance gains caused by individual restructuring techniques havealso been measured. Specific reasons for the successes and failures of thetransformations are discussed, and potential improvements that result in measurablybetter program performance are analyzed. The most important findings are that availablerestructurers often cause insignificant performance gains in real programs and that onlyfew restructuring techniques contribute to this gain. However, it can be shown that thereis potential for advancing compiler technology so that many of the most important loopsin these programs can be parallelized.
Resource management in energy-limited, bandwidth-limited, transceiver-limited wireless networks for session-based multicasting
Authors: Jeffrey E. Wieselthier, Gam D. Nguyen, Anthony Ephremides
Venue: Computer Networks: The International Journal of Computer and Telecommunications Networking (2002)

In this paper we consider source-initiated multicast session traffic in an ad hoc wireless network, operating under hard constraints on the available transmission energy as well as on bandwidth and transceiver resources. We describe the similarities and differences between energy-limited and energy-efficient communications, and we illustrate the impact of these overlapping (and sometimes conflicting) considerations on network operation. In energy-limited applications, fundamental objectives include the maximization of a network's useful lifetime and the maximization of traffic that is delivered during this lifetime. We demonstrate how the incorporation of residual energy into the cost metric used for tree construction can provide improved performance based on these criteria.
A Classification of CASE Technology
Authors: Alfonso Fuggetta
Venue: Computer (1993)

A description that provides more precise definitions for terms such as tool, workbench, toolset, and environment is provided. The aim is to provide a reference framework and an initial classification of existing technology as a solid starting point for continuous updating.
Generating triangulations on closed surfaces with minimum degree at least 4
Authors: Atsuhiro Nakamoto, Seiya Negami
Venue: Discrete Mathematics (2002)

We show that every triangulation on a closed surface, except the sphere, with minimum degree at least 4 can be obtained from an irreducible triangulation by two kinds of local deformations, called 4-splitting and addition of an octahedron and that every triangulation on the sphere can be obtained from the octahedron by them.
Automatic Extraction of Functional Parallelism from Ordinary Programs
Authors: M. Girkar, C. D. Polychronopoulos
Venue: IEEE Transactions on Parallel and Distributed Systems (1992)

Presents the hierarchical task graph (HTG) as an intermediate parallel program representation which encapsulates minimal data and control dependences, and which can be used for the extraction and exploitation of functional, or task-level parallelism. The hierarchical nature of the HTG facilitates efficient task-granularity control during codegeneration, and thus applicability to a variety of parallel architectures. The construction of the HTG at a given hierarchy level, the derivation of the execution conditions of tasks which maximizes task-level parallelism, and the optimization of these conditions which results in reducing synchronization overhead imposed by data and control dependences are emphasized. Algorithms for the formation of tasks and their execution conditions based on data and control dependence constraints are presented. The issue ofoptimization of such conditions is discussed, and optimization algorithms are proposed. The HTG is used as the intermediate representation of parallel Fortran and C programs for generating parallel source as well as parallel machine code.
Digital Curvature Flow and Its Application for Skeletonization
Authors: Atsushi Imiya, Masahiko Saito, Ken Tatara, Kiwamu Nakamura
Venue: Journal of Mathematical Imaging and Vision (2003)

In this paper, we define digital curvature flow for planar digital objects. We define the principal normal vectors for points on the digital boundary of a binary planar object. Digital curvature flow is defined as the motion of points on the boundary curve according to principal normal vectors. Therefore, digital curvature flow is a digital version of curvature flow. Furthermore, this transformation could also be considered as discrete curvature flow on isotetic polygons, all edges of which are parallel to the axes of an orthogonal coordinate system.