ppxscal/embedding_network huggingface dataset:
Optimizing Remote Method Invocation in Java
Authors: Tomás Sysala, Jan Janecek
Venue: Proceedings of the 13th International Workshop on Database and Expert Systems Applications (2002)

Communication mechanisms utilized in current middleware technologies have procedural form. The obvious strategy of purely synchronous remote method invocation can result in a bottleneck when applied to a multi-layer application (e.g., when application logic is isolated from data sources). The effect is apparent in Java technologies and challenges to look for a suitable solution.This contribution deals with effectiveness of Java and Java-CORBA remote method invocation. Standard approaches are compared with asynchronous communication support we developed in the frame of the standard Java RMI. Real-time behaviour of different mechanisms (and primarily of asynchronous RMI) has been evaluated on the system developed for middleware testing.
Applying ODP Enterprise Viewpoint Language to Hospital Information System
Authors: Akira Tanaka, Yoshihide Nagase, Yasuo Kiryu, Kanji Nakai
Venue: Proceedings of the 5th IEEE International Conference on Enterprise Distributed Object Computing (2001)

Abstract: INTAP (Interoperability Technology Association for Information Processing, Japan), CBOP (Consortium for Business Object Promotion), MEDIS-DC (Medical Information System Development Center) and JAHIS (Japanese Association of Healthcare Information Systems Industry) have completed the initial phase of the Japanese Healthcare Domain Reference Enterprise Model project. The goal of the project is to define a reference healthcare domain model using ISO/IEC and ITU-T standardized RM-ODP framework. The initial phase focused on modeling the enterprise aspect of hospital information systems in Japan. RM-ODP Enterprise Viewpoint Language and UML were used as the key languages. This paper presents the results of the initial phase of the project, and discusses issues we faced during model development.
A Multi-Attribute Reverse Auction for Outsourcing
Authors: Debasis Mishra, Dharmaraj Veeramani
Venue: Proceedings of the 13th International Workshop on Database and Expert Systems Applications (2002)

In an outsourcing economy, a set of parent-firms want to outsource one component each to one of the suppliers out of a set of suppliers, who each want to supply a maximum of one component. There is a finite set of attributes, each of which can take some finite values, which concern the parent-firms and the suppliers. Parent-firms have valuations for their components and suppliers have costs for supplying the component, both of which depend on the attribute values and are private to the respective parent-firms and suppliers. We propose a reverse auction algorithm for the outsourcing economy. Our reverse auction algorithm achieves nearly efficient allocation and the final prices are also nearly competitive. We investigate strategic behavior of parent-firms and suppliers in our auction.
How to Optimize Residual Communications?
Authors: Michèle Dion, Cyril Randriamaro, Yves Robert
Venue: Proceedings of the 10th International Parallel Processing Symposium (1996)

Minimizing communications when mapping affine loop nests onto distributed memory parallel computers has already drawn a lot of attention. This paper focuses on the next step: as it is generally impossible to obtain a communication-free (or local) mapping, how to optimize the residual communications? We explain how to take advantage of macro-communications such as broadcasts, scatters, gathers or reductions or how to decompose general affine communications into simpler ones that can be performed more efficiently. We finally give a two-step heuristic that summarizes our approach: first minimize the number of nonlocal communications, then optimize residual affine communications using macro-communications or decompositions.
Rectangle Labelling for an Invoice Understanding System
Authors: Francesca Cesarini, Enrico Francesconi, Marco Gori, Simone Marinai, J. Q. Sheng, Giovanni Soda
Venue: Proceedings of the 4th International Conference on Document Analysis and Recognition (1997)

In this paper we present a method for the logical labelling of physical rectangles, extracted from invoices, based on a Conceptual Model which describes, as generally as possible, the invoice universe. This general knowledge is used in the semi-automatic construction of a model for each class of invoices. Once the model is constructed, it can be applied to understand an invoice instance, whose class is univocally identified by its logo. This approach is used to design a flexible system which is able to learn, from a nucleus of general knowledge, a monotonic set of specific knowledge for each class of invoices (Document Models), in terms of physical coordinates for each rectangle and related semantic label.
Process combination to increase event granularity in parallel logic simulation
Authors: Timothy J. McBrayer, Philip A. Wilsey
Venue: Proceedings of the 9th International Symposium on Parallel Processing (1995)

The increasing complexity of digital system designs is motivating a strong desire for higher capacity, faster simulation of logic circuits. While special purpose hardware accelerators show good performance, their high cost and long design times heave inhibited their widespread use. In contrast, the proliferation of reasonably priced symmetric multiprocessors provides an excellent platform upon which to build parallel logic simulators. Unfortunately, attempts to implement parallel simulators to speed logic simulation have meet with limited success. This is largely due to the low event granularity and high communication costs. Furthermore both empirical and analytical studies show that only limited parallelism exists within logic circuits for parallel simulators to exploit. Consequently, a reasonable alternative is to restructure the parallel processes, eliminating some by combining them into single tasks with larger event granularities and less expensive communication costs. This paper presents the constraints and method through which parallel logic gates in a VHDL description can be combined into single processes. Experimentally, we observed significant performance improvements; in some cases, process combination provided a speedup of 2.22 over the original, uncombined description.
A High-Level Abstraction for Graphics Hardware Programming
Authors: Danilo Tuler, Waldemar Celes Filho
Venue: Proceedings of the 15th Brazilian Symposium on Computer Graphics and Image Processing (2002)

Currently available graphics hardware has become programmable. However, this programmability is still offered at a very low abstraction level, usually based on a specialized assembly language, and is difficult to use. To overcome this problem, we present a simple programmable pipeline abstraction. Our proposal is built over the Lua programming language. the application programmer writes a Lua code that, when executed, generates the equivalent assymbly code to be loaded by the hardware. We compare our proposal to other recently published ones or still under construction.
Reengineering Legacy Systems Using Web
Authors: Rakesh Agarwal, Suresh Nayak, Sambit Mishra
Venue: 24th International Computer Software and Applications Conference (2000)

There has been an increasing need to migrate legacy systems to new hardware and software development paradigm because the legacy systems present problems such as high maintenance cost and lack of documentation. All organization must overcome serious challenges if they are to remain competitive in today's fast changing business and technological environment. Legacy system cannot evolve to provide new functionality, they keep on running on obsolete hardware and maintenance is expensive. In this paper we have analyzed the different ways in which a web based solution can be provided for the technological requirement of legacy systems and focuses on the web-based development solutions. This research is implemented using sound software architecture.
Multiscalar Execution along a Single Flow of Control
Authors: Krishna K. Sundararaman, Manoj Franklin
Venue: Proceedings of the international Conference on Parallel Processing (1997)

The multiscalar processing model extracts instruction level parallelism from ordinary programs by splitting the program into smaller, possibly dependent, tasks, and parallelly executing multiple tasks using multiple execution units. Past work had advocated pursuing multiple flows of control in the multiscalar processor. We first illustrate the problems involved in pursuing multiple flows of control. We then discuss a methodology to obtain good performance from multiple tasks extracted from a single line of control. We also present the results of simulation studies that verify the potential of this method. These results, obtained with the SPEC92 benchmarks, show better issue rates when a single line of control is pursued in the multiscalar processor. The primary reason for this improvement is the ability to have better load balancing among the execution units.
Abstract Combinatorial Programs and Efficient Property Testers
Authors: Artur Czumaj, Christian Sohler
Venue: Proceedings of the 43rd Symposium on Foundations of Computer Science (2002)

Property testing is a relaxation of classical decision problems which aims at distinguishing between functions having a predetermined property and functions being far from any function having the property. In this paper we present a novel framework for analyzing property testing algorithms with one-sided error. Our framework is based on a connection of property testing and a new class of problems which we call abstract combinatorial programs. We show that if the problem of testing a property can be reduced to an abstract combinatorial program of small dimension, then the property has an efficient tester. We apply our framework to a variety of classical combinatorial problems. Among others, we present efficient property testing algorithms for geometric clustering problems, for the reversal distance problem, for graph and hypergraph coloring problems. We also prove that, informally, any hereditary graph property can be efficiently tested if and only if it can be reduced to an abstract combinatorial program of small size.Our framework allows us to analyze all our testers in a unified way and the obtained complexity bounds either match or improve the previously known bounds. We believethat our framework will help to better understand the structure of efficiently testable properties.
Handwritten Digits Segmentation Based on Structural Approach
Authors: Luiz E. Soares de Oliveira, Edouard Lethelier, Flávio Bortolozzi, Robert Sabourin
Venue: Proceedings of the 13th Brazilian Symposium on Computer Graphics and Image Processing (2000)

We deal with a new segmentation approach applied to unconstrained handwritten digits. The novelty of the proposed algorithm is based on the combination of two types of structural features in order to provide the best segmentation path between connected entities. This method was developed to be applied in a segmentation-based recognition system. We first present the features used to generate our basic segmentation points, and we define our segmentation paths depending on the encountered configurations with only few heuristic rules. Then, we present a strategy based on graphs in order to manage the segmentation. Finally, we evaluate the output of our segmenter using a integrated classifier with three different combination methods.
Systematic analysis of bounds on power consumption in pipelined and non-pipelined multipliers
Authors: Janardhan H. Satyanarayana, Keshab K. Parhi, Leilei Song, Yun-Nam Chang
Venue: Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors (1996)

The paper presents a systematic theoretical approach for the analysis of bounds on power consumption in Baugh-Wooley, binary tree and Wallace tree multipliers. This is achieved by first developing state transition diagrams (STDs) for the sub circuits making up the multipliers. The STD is comprised of states and edges, with the edges representing a transition (switching activity) from one state to another in the sub circuit. Then, maximum (minimum) energy values associated with the edges constituting the STDs are used to derive the zipper (lower) bound in both non pipelined and p-bit level pipelined multipliers. It is shown that as p is decreased, the upper bound approaches the lower bound. Moreover, based on the theoretical analysis we conclude that the upper bound in a Baugh-Wooley multiplier has a cubic dependence on the word length, while that in a binary tree multiplier has a quadratic dependence on the word length.
An Optimal Multiple Bus Network for Fan-in Algorithms
Authors: Hettihe P. Dharmasena, Ramachandran Vaidyanathan
Venue: Proceedings of the international Conference on Parallel Processing (1997)

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QAME - QoS-Aware Management Environment
Authors: Lisandro Zambenedetti Granville, Liane M. Rockenbach Tarouco
Venue: Proceedings of the 25th International Computer Software and Applications Conference on Invigorating Software Development (2001)

Providing QoS-guaranteed services in current installed networks is an important issue, but only the deploying QoS services is not enough to guarantee their success: QoS management must also be provided. Nowadays, pol-icy-based management addresses this need, but such man-agement is not enough either. Network managers often deal with QoS tasks that cannot be performed using only policy-based management. This paper describes six im-portant QoS management-related tasks (QoS installation, operation maintenance, discovery, monitoring, analysis and visualization) and shows solutions that can help managers proceed with these tasks. Unfortunately, these solutions are independent from each other, leading to a scenario where integration is difficult. To solve this lack of integration, QAME (QoS-Aware Management Environ-ment) has been developed. QAME provides support to allow the execution of the defined QoS tasks in an inte-grated fashion.
Maximum Delivery Time and Hot Spots in ServerNet(tm) Topologies
Authors: Dimiter R. Avresky, Vladimir Shurbanov, Robert W. Horst, William J. Watson, L. Young, Doug Jewett
Venue: Proceedings of the 11th International Symposium on Parallel Processing (1997)

This paper centers on analysis of the performance characteristics of ServerNet topologies, concentrating on the prediction through simulation and statistical analysis of the maximum two-way delivery time, the identification of congested links (hot spots) and tree saturation. ServerNet/sup TM/, developed by Tandem Computers Inc., is a wormhole-routed, packet-switched, point-to-point network, with special attention paid to reducing latency and to assuring reliability. ServerNet uses multiple high-speed, low-cost routers to rapidly switch data directly between data sources and destinations. Our study is based on data generated by a simulation tool. Statistical analysis and inference methods were used to process the samples generated by the simulator and to obtain estimates for the maximum two-way packet delivery time. Link usage statistics were recorded by the simulator for the purpose of performing a detailed investigation of congestion effects and hot spots. Hot spots may cause the occurrence of tree saturation in the network i.e., where an individual tree will become congested (tree saturation) while all other trees are mostly idle, which leads to significant performance degradation.
Multi-Criteria Transaction for E-Commerce Applications
Authors: Peng Li, Jayabharath Goluguri, I-Ling Yen, Ann T. Tai
Venue: Proceedings of the 25th International Computer Software and Applications Conference on Invigorating Software Development (2001)

In this paper, we discuss a multi-criteria transaction model to address problems encountered in large-scale E-commerce transaction processing systems. A multi-criteria transaction (MCT) is a generalized transaction where users can specify their preferences in a request by specifying multiple criteria in the transaction. With each criteria specification, a set of alternate execution paths is included. Thus, an MCT is less likely to fail. Moreover, the MCT model allows easy extraction of criteria from a set of transactions and, hence, optimal decisions can be made to achieve better customer satisfaction. We discuss the design of a MCT processing system and compare the MCT model to conventional transaction processing approaches.
A Performance Model of Speculative Prefetching in Distributed Information Systems
Authors: Nor Jaidi Tuah, Mohan Kumar, Svetha Venkatesh
Venue: Proceedings of the 13th International Symposium on Parallel Processing and the 10th Symposium on Parallel and Distributed Processing (1999)

Previous studies in speculative prefetching focus on building and evaluating access models for the purpose of access prediction. This paper investigates a complementary area which has been largely ignored, that of performance modelling. We use improvement in access time as the performance metric, for which we derive a formula in terms of resource parameters (time available and time required for prefetching) and speculative parameters (probabilities for next access). The performance maximisation problem is expressed as a stretch knapsack problem. We develop an algorithm to maximise the improvement in access time by solving the stretch knapsack problem, using theoretically proven apparatus to reduce the search space. Integration between speculative prefetching and caching is also investigated, albeit under the assumption of equal item sizes.
Introducing the Golden Section to Computer Science
Authors: Natalia López, Manuel Núñez, Ismael Rodríguez, Fernando Rubio
Venue: Proceedings of the 1st IEEE International Conference on Cognitive Informatics (2002)

The golden section appears in the nature showing that this magical number represents the right answer for finding the optimal solution to many covering problems. In this paper, we claim that it can also be quite profitable the using of this number in the context of computer science. This assertion is contrasted by showing how to solve two quite different (classes of) computer science problems on the basis of the golden section. For each problem, an algorithm is given, and its results are compared with those of other methods, showing the advantages of our approach.
Maintaining Spatial Data Sets in Distributed-Memory Machines
Authors: Susanne E. Hambrusch, Ashfaq A. Khokhar
Venue: Proceedings of the 11th International Symposium on Parallel Processing (1997)

We propose a distributed data structure for maintaining spatial data sets on message-passing, distributed memory machines. The data structure is based on orthogonal bisection trees and it captures relevant characteristics of parallel machines. The operations we consider include insertion, deletion, and range queries. We introduce parameters to control how much imbalance is tolerated at each processor and to specify the load to be achieved during balancing. When balancing, we first broadcast point counts of a data-dependent partition of the data. Based on this partition, we propose load balancing methods with different communication and computation requirements. We present initial experimental results for the Cray T3D.
SPAX: A New Parallel Processing System for Commercial Application
Authors: Woo-Jong Hahn, Kee-Wook Rim, Soo-Won Kim
Venue: Proceedings of the 11th International Symposium on Parallel Processing (1997)

A new parallel processing system for commercial applications, called SPAX, is described. SPAX cost-effectively overcomes the SMP limitation by providing scalability of the parallel processing system and application portability of the SMP. We also describe a new system network, called Xcent-Net, which interconnects hundreds of multiprocessor PC boards in SPAX. It is a hierarchical network that provides incremental scalability with minimum re-wiring when the user's requirement is changed. This is based on the low latency crossbar routers on each hierarchy, which consist a router-cloud and provide up to 2.67 Gbytes/sec/router-cloud of bandwidth. We briefly describe the preliminary evaluation result that shows Xcent-Net will not be the bottleneck in the system running a typical commercial application.
A coprocessor for accurate and reliable numerical computations
Authors: Michael J. Schulte, Earl E. Swartzlander,  Jr.
Venue: Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors (1995)

This paper presents the architecture and hardware design of a special-purpose coprocessor that performs variable-precision, interval arithmetic. Variable-precision arithmetic allows the precision of the computation to be specified, based on the problem to be solved and the required accuracy of the results. Interval arithmetic produces two values for each result, such that the true result is guaranteed to be between the two values. The coprocessor gives the programmer the ability to specify the precision of the computation, determine the accuracy of the results, and recompute inaccurate results with higher precision. Direct hardware support for variable-precision, interval arithmetic greatly improves the accuracy and reliability of numerical computations. Execution time estimates indicate that the coprocessor is two to three orders of magnitude faster than an existing software package for variable-precision, interval arithmetic.
A New Paradigm on Fingerprint Classification using Directional Image
Authors: Silvia M. Farani Costa, João Marcelo V. de Oliveira, Francisco Javier Ramirez Fernandez
Venue: Proceedings of the 15th Brazilian Symposium on Computer Graphics and Image Processing (2002)

This work presents a simple method to obtain fingerprint classification via directional map smoothing. The program was developed in C++ language, using statistical techniques. That strategy allows to extract attributes of an image and to increase the quality of the process due reduction of the noise, if compared with the result obtained by mean other method exposed in literature. The experimental results, obtained by this technique, demonstrate that a better directional map is arranged.
A World Without Risks: Let Me Out!
Authors: Jeffrey M. Voas
Venue: The 4th IEEE International Symposium on High-Assurance Systems Engineering (1999)

Life is based on risk. If everything in life worked perfectly, the world would be boring. In fact, we'd probably have to create risks just to stay sane. Risk is a phenomenon that all living things must cope with, manage, and mitigate. The key is not to focus on total risk avoidance, but instead, intelligent risk management. Total risk avoidance is impossible. My position is that software's benefit to society outweighs the risks. Software is the great enabler for a higher "quality of life." Human casualties will inevitably occur as we continue to seek new methods and refine existing methods for high assurance software.
An Object/Segment Oriented Skew-Correction Technique for Document Images
Authors: M. Ben Hadj Ali
Venue: Proceedings of the 4th International Conference on Document Analysis and Recognition (1997)

An innovative new skew correction technique is presented. The method is not pixel oriented as the most classical techniques, but is object/segment oriented. It does not suppose a unique text orientation in the document image and can handle document images including "text" blocks with different orientations. It is very efficient in the sense that only the relevant data/information is rotated: the connected components using their contour descriptions.