ppxscal/embedding_network huggingface dataset:
The type inference and coercion facilities in the scratchpad II interpreter
Authors: R. S. Sutor, R. D. Jenks
Venue: Papers of the Symposium on Interpreters and interpretive techniques (1987)

The Scratchpad II system is an abstract datatype programming language, a compiler for the language, a library of packages of polymorphic functions and parametrized abstract datatypes, and an interpreter that provides sophisticated type inference and coercion facilities. Although originally designed for the implementation of symbolic mathematical algorithms, Scratchpad II is a general purpose programming language. This paper discusses aspects of the implementation of the interpreter and how it attempts to provide a user friendly and relatively weakly typed front end for the strongly typed programming language.
The effect of instruction set complexity on program size and memory performance
Authors: Jack W. Davidson, Richard A. Vaughan
Venue: ACM SIGPLAN Notices (1987)

One potential disadvantage of a machine with a reduced instruction set is that object programs may be substantially larger than those for a machine with a richer, more complex instruction set. The main reason is that a small instruction set will require more instructions to implement the same function. In addition, the tendency of RISC machines to use fixed length instructions with a few instruction formats also increases object program size. It has been conjectured that the resulting larger programs could adversely affect memory performance and bus traffic. In this paper we report the results of a set of experiments to isolate and determine the effect of instruction set complexity on cache memory performance and bus traffic. Three high-level language compilers were constructed for machines with instruction sets of varying degrees of complexity. Using a set of benchmark programs, we evaluated the effect of instruction set complexity had on program size. Five of the programs were used to perform a set of trace-driven simulations to study each machine's cache and bus performance. While we found that the miss ratio is affected by object program size, it appears that this can be corrected by simplying increasing the size of the cache. Our measurements of bus traffic, however, show that even with large caches, machines with simple instruction sets can expect substantially more main memory reads than machines with dense object programs.
Parallel Block Predictor-Corrector Methods for Ode's
Authors: Louis G. Birta, Osman Abou-Rabia
Venue: IEEE Transactions on Computers (1987)

The problem of achieving parallelism in the solution of the ordinary differential equations is investigated in this paper. The study focuses on an examination of block methods as a practical means for conveniently distributing the computational workload over multiple processors. Both previously suggested and newly proposed predictor-corrector formula pairs are presented and analyzed and a variable stepsize procedure is developed. The performance of two particular members of the block predictor-corrector class is evaluated experimentally using a collection of test problems. A multimicroprocessor system architecture which uses a distributed memory to deal with the interprocessor communications problem is described as a feasible hardware realization of the approach.
John Reid reports: X3J3 meeting, February 1987
Authors: John Reid
Venue: ACM SIGPLAN Fortran Forum (1987)

A letter ballot of all X3J3 members was conducted prior to this meeting, asking the question "Do you approve the draft Fortran Revision...enclosed with this ballot for submission to X3 for further processing as an American National Standard?" The result was Yes: 9; Yes with comments, 20; No: 7. Since less than 1/3 voted "no", the ballot passed. Short summaries of the reasons given for each no vote appear in Section 2. It looks of 2 or 3 of these may change to yes votes once all the comments have been processed, but the rest are asking for drastic changes that are quite unacceptable to a majority of the Committee.
VITS-A Vision System for Autonomous Land Vehicle Navigation
Authors: Matthew A. Turk, David G. Morgenthaler Keith D. Gremban, Martin Marra
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1988)

A description is given of VITS (for vision task sequencer), the vision system for the autonomous land vehicle (ALV) Alvin, addressing in particular the task of road-following. The ALV vision system builds symbolic descriptions of road and obstacle boundaries using both video and range sensors. The authors discuss various road segmentation methods for video-based road-following, along with approaches to boundary extraction and transformation of boundaries in the image plane into a vehicle-centered three-dimensional scene model.
The butterfly satellite IMP for the wideband packet satellite network
Authors: W Edmond, S Bumenthal, A Echenique, S Storch, T Calderwood
Venue: Proceedings of the ACM SIGCOMM conference on Communications architectures protocols (1986)

Multiprocessor computer systems have proven effective as high performance switching nodes in packet switched data communications networks. They are well suited to performing the required queuing, routing, and scheduling tasks, and can scale upward to provide higher system throughput when combined with software that exploits the parallelism provided by the hardware. This paper describes the packet switch used in the DARPA Wideband Packet Satellite Network and the Butterfly&trade; Multiprocessor on which it is based.
An experience with a Prolog-based object-oriented language
Authors: Koichi Fukunaga, Shin-ichi Hirose
Venue: ACM SIGPLAN Notices (1986)

This paper presents an experience with a programming language SPOOL which is based on the combination of object-oriented programming and logic programming. This language inherits the capability of knowledge base organization from object-oriented programming and its expressive power from logic programming.The experience of the application of SPOOL to the program annotation system showed that this combination was quite useful to formalize domain knowledge into declarative data types and make them reusable in different contexts. It also showed the need for further study such as better linguistic support to exploit the full power of this combination.
Stability and Distributed Scheduling Algorithms
Authors: John A. Stankovic
Venue: IEEE Transactions on Software Engineering (1985)

Many distributed scheduling algorithms have been developed and reported in the current literature. However, very few of them explicitly treat stability issues. This paper first discusses stability issues for distributed scheduling algorithms in general terms. Two very different distributed scheduling algorithms which contain explicit mechanisms for stability are then presented and evaluated with respect to individual specific stability issues. One of the agorithms is based on stochastic learning automata and the other on bidding. The results indicate how very specific the treatment of stability is to the algorithm and environnent under consideration.
Performance Modeling Based on Real Data: A Case Study
Authors: M. C. Hsueh, R. K. Iyer, K. S. Trivedi
Venue: IEEE Transactions on Computers (1988)

A measurement-based performability model is described that is based on error and resource-usage data collected on a multiprocessor system. A method for identifying the model structure is introduced, and the resulting model is validated against real data. Model development from the collection of raw data to the estimation of the expected reward is described. Both normal behavior and error behavior of the system are characterized. The measured data show that the holding times in key operational and error states are not simple exponentials and that a semi-Markov process is necessary to model the system behavior. A reward function, which is based on the service rate and the error rate in each state, is defined in order to estimate the performability of the system and to depict the cost of different types of errors.
Machine-Independent Virtual Memory Management for Paged Uniprocessor and Multiprocessor Architectures
Authors: Richard Rashid, Avadis Tevanin,  Jr. Michael Young, David Golub, Robert Baron
Venue: IEEE Transactions on Computers (1988)

The authors describe the design, implementation, and evaluation of the Mach virtual-memory management system. The Mach virtual-memory system exhibits architecture independence, multiprocessor and distributed system support, and advanced functionality. The performance of this virtual-memory system is shown to often exceed that of commercially developed memory management systems targeted at specific hardware architectures.
An experimental study of people creating spreadsheets
Authors: Polly S. Brown, John D. Gould
Venue: ACM Transactions on Information Systems (TOIS) (1987)

Nine experienced users of electronic spreadsheets each created three spreadsheets. Although participants were quite confident that their spreadsheets were accurate, 44 percent of the spreadsheets contained user-generated programming errors. With regard to the spreadsheet creation process, we found that experienced spreadsheet users spend a large percentage of their time using the cursor keys, primarily for the purpose of moving the cursor around the spreadsheet. Users did not spend a lot of time planning before launching into spreadsheet creation, nor did they spend much time in a separate, systematic debugging stage. Participants spent 21 percent of their time pausing, presumably reading and/or thinking, prior to the initial keystrokes of spreadsheet creation episodes.
Just-in-time (JIT) production and process cycle time variability
Authors: Menberu Lulu, J. T. Black
Venue: Proceedings of the 20th annual symposium on Simulation (1987)

The effects of process cycle time variability on the performance of a zero inventory simulation model of a Just-In-Time Manufacturing and Production System (JITMPS) is investigated. Process cycle time variability does not adversely affect the performance of a Kanban- linked process structure. However, it does lengthen product cycle time and product throughput time, and lower system utilization on directly linked process structure. Modifying a directly linked process structure to include one accumulator with one unit of float between each individual process eliminates these adverse effects.
The impact of end-user computing on information systems development
Authors: Mary Sumner, Robert Klepper
Venue: ACM SIGCPR Computer Personnel (1986)

In their study of user manager's systems needs, Alloway and Quillard surveyed 529 managers to determine whether current systems supported their information needs. Managers reported that only 44% of the installed base of application systems, most of which were transaction processing systems, were useful. Inquiry systems, which enabled managers to query data bases and to generate reports, and data analysis systems, which provided opportunities for modeling, simulating, and statistical analysis, were overwhelmingly favored by the managers surveyed. However, few of these analysis and inquiry systems existed (Alloway and Quillard, 1983).
Functional Test Generation Based on Unate Function Theory
Authors: Vijay Pitchumani, Satish S. Soman
Venue: IEEE Transactions on Computers (1988)

The generation of a universal test set (UTS) for unate functions is used as a starting point. This test set is complete and minimal for the set of all unateness-preserving faults. However, for functions that are not unate in any variable, the UTS generated by this algorithm is the exhaustive set. An algorithm is presented that computes a good functional test set (GFTS) of reasonable size even for such functions. The algorithm does this by breaking up functions into more unate components, recursively computing GFTS for them, and combining the test sets in an appropriate way. The GFTS generated by the algorithm is compared to random test sets of the same size for gate-level fault coverage in typical implementations.
The Mahler experience: using an intermediate language as the machine description
Authors: David W. Wall, Michael L. Powell
Venue: ACM SIGARCH Computer Architecture News (1987)

Division of a compiler into a front end and a back end that communicate via an intermediate language is a well-known technique. We go farther and use the intermediate language as the official description of a family of machines with simple instruction sets and addressing capabilities, hiding some of the inconvenient details of the real machine from the users and the front end compilers.To do this credibly, we have had to hide not only the existence of the details but also the performance consequences of hiding them. The back end that compiles and links the intermediate language tries to produce code that does not suffer a performance penalty because of the details that were hidden from the front end compiler. To accomplish this, we have used a number of link-time optimizations, including instruction scheduling and interprocedural register allocation, to hide the existence of such idiosyncracies as delayed branches and non-infinite register sets. For the most part we have been sucessful.
An Automatic Wafer Inspection System Using Pipelined Image Processing Techniques
Authors: H. Yoda, Y. Ohuchi, Y. Taniguchi, M. Ejiri
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1988)

An automatic wafer pattern inspection system has been developed that can detect defective patterns 6 mu m or larger in multilayered wafer patterns at a speed 30 times faster than that of a human inspector. The false-alarm rate is less than 0.5 occurrences/chip. This performance is achieved mainly by the use of a special comparison method between two adjacent patterns obtained through a single optical setup, and also by the use of digital design pattern data (CAD data). The main functions of the design pattern data are to specify the inspection area, to designate optimum parameters for inspection, and to separate defective portions into different layers, thereby facilitating the classification of the defects. All image processing is performed in one pass by a high-speed pipeline-structured image processor that can analyze an input image signal at a 7 MHz video rate.
Gracefully Degradable Processor Arrays
Authors: Jose A. B. Fortes, C. S. Raghavendra
Venue: IEEE Transactions on Computers (1985)

A new approach to the design of gracefully degradable processor arrays is discussed. Fault tolerance and graceful degradation are achieved by simultaneously reconfiguring the processor array and the algorithm in execution. Two types of algorithm reconfigurability are considered, namely, row reconfigurability (RR) and row-column reconfigurability (RCR). correspondingly, two array reconfiguration schemes are discussed, i.e., successive row elimination (SRE) and alternate row-column elimination (ARCE). It is shown that the computations of any algorithm executable in a processor array can always be (re) organized so that the resultant algorithm has the RR and/or RCR properties. Upper bounds on the increase in execution time of an algorithm due to reorganization of computations for reconfigurability are derived. Detailed analysis of performance and reliability is done for both SRE and ARCE reconfiguration schemes. These reconfiguration techniques are applicable to any processor array and suitable for VLSI technology.
Separating content from form: A language for formatting on-line documentation and dialog
Authors: Charlie Wiecha, Max Henrion
Venue: Proceedings of the 4th annual international conference on Systems documentation (1986)

Recent research has demonstrated the advantages of separating management of the user interface from the application program. A user interface system should integrate access to on-line help and documentation with other dialog for interacting with the program into a uniform environment. We describe such a user interface management system, called ICE, with emphasis on its facilities for authoring networks of frames containing help information and menus for interacting with the application program. Authors can write help and dialog using a language similar to the SCRIBE document processing system, widely used at CMU and elsewhere. But instead of generating hardcopy documents for different printing devices, ICE produces interactive &ldquo;softcopy&rdquo; documents, consisting of a network of frames combining documentation and interface. In ICE the screen layout of frames and the style of interaction is specified in a format file which is separate from the dialog file that contains the text to appear in the frames. This separation allows the dialog author to write the text without having to worry much about its precise appearance on the screen. The display designer can specify the actual format independently. The same text can be formatted in different ways to make use of different display devices and to allow experimentation with alternative formats and styles of interaction.
A framework for knowledge representation and use in pattern analysis
Authors: F Bergadano, A Giordana
Venue: Proceedings of the ACM SIGART international symposium on Methodologies for intelligent systems (1986)

In this paper a prototype Expert System oriented to signal and pattern analysis is described together with a general methodology based on a hypothesize-and-test strategy similar to the one used by a human expert. This paper focuses on the knowledge base architecture and on its use. In order to make it capable of dealing with noisy patterns, the knowledge description is based on Fuzzy logic and the inference engine is able to reason about the knowledge it uses. The system is being applied to the phonetic analysis of the voice signal in speech recognition, as a case study.
The geometry of semaphore programs
Authors: Scott D. Carson, Paul F. Reynolds,  Jr.
Venue: ACM Transactions on Programming Languages and Systems (TOPLAS) (1987)

Synchronization errors in concurrent programs are notoriously difficult to find and correct. Deadlock, partial deadlock, and unsafeness are conditions that constitute such errors. A model of concurrent semaphore programs based on multidimensional, solid geometry is presented. While previously reported geometric models are restricted to two-process mutual exclusion problems, the model described here applies to a broader class of synchronization problems. The model is shown to be exact for systems composed of an arbitrary, yet fixed number of concurrent processes, each consisting of a straight line sequence of arbitrarily ordered semaphore operations.
Fuzzy functional dependencies and lossless join decomposition of fuzzy relational database systems
Authors: K. V. S. V. N. Raju, Arun K. Majumdar
Venue: ACM Transactions on Database Systems (TODS) (1988)

This paper deals with the application of fuzzy logic in a relational database environment with the objective of capturing more meaning of the data. It is shown that with suitable interpretations for the fuzzy membership functions, a fuzzy relational data model can be used to represent ambiguities in data values as well as impreciseness in the association among them. Relational operators for fuzzy relations have been studied, and applicability of fuzzy logic in capturing integrity constraints has been investigated. By introducing a fuzzy resemblance measure EQUAL for comparing domain values, the definition of classical functional dependency has been generalized to fuzzy functional dependency (ffd). The implication problem of ffds has been examined and a set of sound and complete inference axioms has been proposed. Next, the problem of lossless join decomposition of fuzzy relations for a given set of fuzzy functional dependencies is investigated. It is proved that with a suitable restriction on EQUAL, the design theory of a classical relational database with functional dependencies can be extended to fuzzy relations satisfying fuzzy functional dependencies.
The syntax of APL, an old approach revisited
Authors: Jean Jacques Girardot, Florence Rollin
Venue: Proceedings of the international conference on APL: APL in transition (1987)

Most efforts have been made in the past APL conferences to propose new approaches to the analysis of APL, and introduce new features in the language. However, most of these proposals take very little in account the amount of work that has been made around syntax analysis in the 'main stream' of computer science. The proposed approach, as described in this paper, can therefore be considered as an old work. We first describe the fundamental syntactic devices of APL. Those devices are then arranged as a standard BNF. We can exhibit some properties of the language described, and consequently select from the literature an appropriate technique to perform the syntax analysis of APL expressions. The proposed method uses a push-down automaton. Although the language is shown to be not LR(k), an adaptation of this technique works well using backtracking. The whole process has been modelled in APL. A first application transforms a grammar expressed as a BNF in a set of tables. A second application uses these tables to perform the syntax analysis of APL statements. These last programs have been rewritten in C, integrated in an APL system, and used to test different dialects of APL, such as ISO-APL or APL2. Results show the influence of the cost of syntax analysis in the processing of APL expressions.
A case study in silicon compilation software engineering, HVDEV high voltage device layout generator
Authors: N. J. Elias
Venue: Proceedings of the 24th ACM/IEEE Design Automation Conference (1987)

Philips Laboratories has developed HVDEV, a procedural language layout generator for compiling high voltage MOS device layouts from behavioral specifications. HVDEV is analyzed as a case study in silicon compilation software engineering. The paper formulates a comparative analysis to conventional layout design accounting for software development and maintenance. Critical factors in planning silicon compilation software development are identified.
Impact of organizational maturity on user satisfaction with information systems
Authors: Mo A Mahmood, Jack D Becker
Venue: Proceedings of the twenty-first annual conference on Computer personnel research (1985)

User satisfaction has increasingly played an important role in information systems (IS) organizations' effectiveness. Does an IS organization's ability to design and develop increasingly effective systems depend on its maturity? Does maturity depend on bringing in state-of-the-art technology? Is maturity related to the organizational structure of the Data Processing/Management Information Systems (DP/MIS) Unit? Is maturity related to spending increasing amounts of money on IS organizations? The importance of these questions and their answers to DP/MIS managers and users cannot be overemphasized. The research uses a field study of IS users and managers to answer these questions and other related issues. The study shows a weak but significant overall relationship between user satisfaction variables and maturity criteria defined by Nolan [25]. Further research based on the findings of the study is suggested as a means of improving the degree of relationship between maturity criteria and user satisfaction variables.
Designing large real-time systems with Ada
Authors: Kjell W. Nielsen, Ken Shumate
Venue: Communications of the ACM (1987)

The programming language Ada encourages improved methods for the design of real-time systems.