ppxscal/embedding_network huggingface dataset:
Software metrics: using measurement theory to describe the properties and scales of static software complexity metrics
Authors: H. Zuse, P. Bollmann
Venue: ACM SIGPLAN Notices (1989)

Over the last decade many software metrics have been introduced by researchers and many software tools have been developed using software metrics to measure the "quality" of programs. These metrics for measuring productivity, reliability, maintainability, and complexity, for example, are vital to software development planning and management. In this paper a new approach is presented to describe the properties of the software metrics and their scales using measurement theory. Methods are shown to describe a software complexity metric as an ordinal, an interval or a ratio scale. The use of this concept is shown by application to the Metric of McCabe. These results are very important for selecting appropriate software metrics for software measurement and for developing tools which use software metrics to evaluate the "quality" of software.
Orthogonal version management
Authors: C. Reichenberger
Venue: ACM SIGSOFT Software Engineering Notes (1989)

One part of the &ldquo;Software Configuration Management&rdquo; &mdash; software version control &mdash; is the task of controlling different versions of documents. Most existing version control systems accomplish this task by managing variant and revision trees of single documents. The structure of these trees depends on the chronological evolution of the software project. We call this form of organization &ldquo;intermixed organization&rdquo; of variants and revisions. This paper points out the disadvantages of that organization, introduces a new way of version management - the &ldquo;orthogonal organization&rdquo; - and then compares the two organizations by means of an example.
Issues in Ada Compiler Technology
Authors: Mahadevan Ganapathi, Geoffrey O. Mendal
Venue: Computer (1989)

The key technical issues involved in producing high-quality Ada compilers and related support tools are discussed. These include real-time issues, programming tools and environments, and code optimization. Also addressed are some important problems that compiler designers face, for example, determining which deficiencies of existing Ada systems can be attributed to the language and which are simply hard-to-implement features or unresolved issued in Ada compiler technology.
A high speed transport protocol for datagram/virtual circuit networks
Authors: K. K. Sabnani, A. N. Netravali
Venue: Symposium proceedings on Communications architectures protocols (1989)

We present a design and preliminary analysis of an end-to-end transport protocol that is capable of high throughput consistent with the evolving wideband physical networks based on fiber optic transmission lines and high capacity switches. Unlike the current transport protocols in which changes in control state information are exchanged between the two communicating entities only when some significant event occurs, our protocol exchanges relevant and full state information periodically, routinely and frequently. We show that this results in reducing the complexity of protocol processing by removing many of the procedures required to recover from the inadequacies of the network such as bit-errors, packet loss, out of sequence packets and makes it more amenable to parallel processing. Also, to increase channel utilization in the presence of high speed, long latency networks, and to support datagrams, we propose an efficient implementation of selective repeat method of error control used in our protocol. Thus, we utilize small extra bandwidth to simplify protocol processing; a trade-off that appears proper since electronic speeds for protocol processing are far slower than fiber transmission rates. Our preliminary estimates indicate that 20,000 packets/second can be handled in a completely software implementation on a 10 MIP microprocessor using 8% of its cycles.
Architectural and organizational tradeoffs in the design of the MultiTitan CPU
Authors: N. P. Jouppi
Venue: ACM SIGARCH Computer Architecture News (1989)

This paper describes the architectural and organizational tradeoffs made during the design of the MultiTitan, and provides data supporting the decisions made. These decisions covered the entire space of processor design, from the instruction set and virtual memory architecture through the pipeline and organization of the machine. In particular, some of the tradeoffs involved the use of an on-chip instruction cache with off-chip TLB and floating-point unit, the use of direct-mapped instead of associative caches, the use of 64-bit vs. 32-bit data bus, and the implementation of hardware pipeline interlocks.
Analysis of transaction management performance
Authors: D. Duchamp
Venue: Proceedings of the twelfth ACM symposium on Operating systems principles (1989)

There is currently much interest in incorporating transactions into both operating systems and general-purpose programming languages. This paper provides a detailed examination of the design and performance of the transaction manager of the Camelot system. Camelot is a transaction facility that provides a rich model of transactions intended to support a wide variety of general-purpose applications. The transaction manager's principal function is to execute the protocols that ensure atomicity. The conclusions of this study are: a simple optimization to two-phase commit reduces logging activity of distributed transactions; non-blocking commit is practical for some applications; multithreaded design improves throughput provided that log batching is used; multi-casting reduces the variance of distributed commit protocols in a LAN environment; and the performance of transaction mechanisms such as Camelot depend heavily upon kernel performance.
Edge-Labeling Using Dictionary-Based Relaxation
Authors: E. R. Hancock, J. Kittler
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1990)

An improved application of probabilistic relaxation to edge labeling is presented. The improvement derives from the use of a representation of the edge process that is internally consistent and which utilizes a more complex description of edge structure. The application uses a dictionary to represent permitted labelings of the entire context-conveying neighborhood of each pixel. Details are given of the dictionary approach and the related representation of the edge process. A comparison with other edge-postprocessing strategies is provided.
Primitive Cellular Automata, Threshold Decomposition, and Ranked Order Operations
Authors: H. V. Jagadish, T. Kailath
Venue: IEEE Transactions on Computers (1989)

A connection between ranked filters and primitive cellular automata is discussed. Primitive cellular automata are those whose nodes comprise a single bit of state information. It is shown that these structures can perform ranked order operations on one-dimensional k-level signals by virtue of threshold decomposition. Extensions to the case of multidimensional signals are also possible.
A high performance Prolog processor with multiple function units
Authors: A. Singhal, Y. N. Patt
Venue: ACM SIGARCH Computer Architecture News (1989)

We describe the Parallel Unification Machine (PLUM), a Prolog processor that exploits fine grain parallelism using multiple function units executing in parallel. In most cases the execution of bookkeeping instructions is almost completely overlapped by unification, and the performance of the processor is limited only by the available unification parallelism. We present measurements from a register transfer level simulator of PLUM. These results show that PLUM with 3 Unification Units achieves an average speedup of approximately 3.4 over the Berkeley VLSI-PLM, which is usually regarded as the current highest performance special purpose, pipelined Prolog processor. Measurements that show the effects of multiple Unification Units and memory access time on performance are also presented.
Partially shared views: a scheme for communicating among groups that use different type hierarchies
Authors: Jintae Lee, Thomas W. Malone
Venue: ACM Transactions on Information Systems (TOIS) (1990)

Many computer systems are based on various types of messages, forms, or other objects. When users of such systems need to communicate with people who use different object types, some kind of translation is necessary. In this paper, we explore the space of general solutions to this translation problem and propose a scheme that synthesizes these solutions. After first illustrating the problem in the Object Lens system, we identify two partly conflicting objectives that any translation scheme should satisfy: preservation of meaning and autonomous evolution of group languages. Then we partition the space of possible solutions to this problem in terms of the set theoretic relations between group languages and a common language. This leads to five primary solution classes and we illustrate and evaluate each one. Finally, we describe a composite scheme, called Partially Shared Views, that combines many of the best features of the other schemes. A key insight of the analysis is that partially shared type hierarchies allow &ldquo;foreign&rdquo; object types to be automatically translated into their nearest common &ldquo;ancestor&rdquo; types. The partial interoperability attained in this way makes possible flexible standards from which people can benefit from whatever agreements they do have without having to agree on everything. Even though our examples deal primarily with extensions to the Object Lens system, the analysis also suggests how other kinds of systems, such as EDI applications, might exploit specialization hierarchies of object types to simplify the translation problem.
COOL: kernel support for object-oriented environments
Authors: Sabine Habert, Laurence Mosseri
Venue: Proceedings of the European conference on object-oriented programming on Object-oriented programming systems, languages, and applications (1990)

The Chorus Object-Oriented Layer (COOL) is an extension of the facilities provided by the Chorus distributed operating system with additional functionality for the support of object-oriented environments. This functionality is realized by a layer built on top of the Chorus V3 Nucleus, which extends the Chorus interface with generic functions for object management: creation, deletion, storage, remote invocation and migration. One major goal of this approach was to explore the feasibility of general object management at the kernel level, with support of multiple object models at a higher level. We present the implementation of COOL and a first evaluation of this approach with a C++ environment using the COOL mechanisms.
Expert systems for configuration at Digital: XCON and beyond
Authors: Virginia E. Barker, Dennis E. O'Connor, Judith Bachant, Elliot Soloway
Venue: Communications of the ACM (1989)

Members of Digital Equipment Corporation's team of expert system experts reflect and recount a decade's worth of lessons learned in designing, and building a core of configuration systems
Expert simulation for on-line scheduling
Authors: S. Jain, K. Barber, D. Osterfeld
Venue: Proceedings of the 21st conference on Winter simulation (1989)

In recent years, the automotive industry has realized the importance of speed of new products to market and has mounted efforts for improving it. The Expert System Scheduler (ESS) facilitates these efforts by enabling manufacturing plants to generate viable schedules under increasing constraints and demands for flexibility. The scheduler takes advantage of the Computer Integrated Manufacturing (CIM) environment by utilizing the realtime information from the factory floor for responsive scheduling.The Expert System Scheduler uses heuristics developed by an experienced factory scheduler. It uses simulation concepts and these heuristics to generate schedules. Forward and "backward" simulation are used at different stages of the schedule generation process.The system is used to control parts flow on the factory floor at one automated facility. This highly automated facility is a testbed for implementation of CIM concepts. The scheduler runs on a Texas Instruments (TI) Explorer II computer using software developed inhouse utilizing IntelliCorp's Knowledge Engineering Environment (KEE) shell and the LISP language. The scheduling computer is networked to the factory control computer, which actually controls the plant floor. The TI Explorer II acquires current plant floor information from the factory control system, generates a new schedule and sends it back within a short time. The configuration allows fast response to changes in requirements and plant floor conditions.
A data-flow driven resource allocation in a retargetable microcode compiler
Authors: H. Feuerhahn
Venue: Proceedings of the 21st annual workshop on Microprogramming and microarchitecture (1988)

A method for global resource allocation is described, which minimizes data movements and optimizes the use of resources like special purpose registers and functional units in complicated bus structures. The algorithm can deal with arbitrary flow graphs and hierarchies of nonrecursive procedures. It is based on a thorough data flow analysis of the source program and a description of the target architecture. The method has been implemented in a retargetable compiler with front-ends for the system implementation languages C and CDL2.
Retrieval performance versus disc space utilization on WORM optical discs
Authors: Stavros Christodoulakis, Daniel Alexander Ford
Venue: ACM SIGMOD Record (1989)

Steady progress in the development of optical disc technology over the past decade has brought it to the point where it is beginning to compete directly with magnetic disc technology. WORM optical discs in particular, which permanently register information on the disc surface, have significant advantages over magnetic technology for applications that are mainly archival in nature but require the ability to do frequent on-line insertions. In this paper, we propose a class of access methods that use rewritable storage for the temporary buffering of insertions to data sets stored on WORM optical discs and we examine the relationship between the retrieval performance from WORM optical discs and the utilization of disc storage space when one of these organizations is employed. We describe the performance trade off as one of fast sequential retrieval of the contents of a block versus wasted space owing to data replication. A model of a specific instance of such an organization (a buffered hash file scheme) is described that allows for the specification of retrieval performance objectives. Alternative strategies for managing data replication that allow trade offs between higher consumption rates and better average retrieval performance are also described. We then provide an expected value analysis of the amount of disc space that must be consumed on a WORM disc to meet specified performance limits. The analysis is general enough to allow easy extension to other types of buffered files systems for WORM optical discs.
Act II - Scene I - data integrity
Authors: L. Ohringer
Venue: ACM SIGSAC Review (1989)

The National Institute of Standards and Technology held a Workshop on Data Integrity in January 1989 to try to identify and analyze the properties of computer security that go beyond confidentiality. A strawman position paper, which was written to promote discussion at the Workshop, called this property Integrity. Confusion developed among some of the workshop participants over the characterization and attributes of integrity.
A binary feedback scheme for congestion avoidance in computer networks
Authors: K. K. Ramakrishnan, Raj Jain
Venue: ACM Transactions on Computer Systems (TOCS) (1990)

We propose a scheme for congestion avoidance in networks using a connectionless protocol at the network layer. The scheme uses a minimal amount of feedback from the network to the users, who adjust the amount of traffic allowed into the network. The routers in the network detect congestion and set a congestion-indication bit on packets flowing in the forward direction. The congestion indication is communicated back to the users through the transport-level acknowledgment. The scheme is distributed, adapts to the dynamic state of the network, converges to the optimal operating point, is quite simple to implement, and has low overhead. The scheme maintains fairness in service provided to multiple sources. This paper presents the scheme and the analysis that went into the choice of the various decision mechanisms. We also address the performance of the scheme under transient changes in the network and pathological overload conditions.
Safety of datalog queries over infinite databases
Authors: Y. Sagiv, M. Y. Vardi
Venue: Proceedings of the eighth ACM SIGACT-SIGMOD-SIGART symposium on Principles of database systems (1989)

A query is safe with respect to a set of constraints if for every database that satisfies the constraints the query is guaranteed to yield a finite set of answers. We study here the safety problem for Datalog programs with respect to finiteness constraints. We show that safety can be viewed as a combination of two properties: weak safety, which guarantees the finiteness of intermediate answers, and termination, which guarantees the finiteness of the evaluation. We prove that while weak safety is decidable, termination is not. We then consider monadic programs, i.e., programs in which all intensional predicates are monadic, and show that safety is decidable in polynomial time for monadic programs. While we do not settle the safety problem, we show that a closely related problem, the decision problem for safety with respect to functional dependencies, is undecidable even for monadic programs.
An open-ended data representation model for EU_LISP
Authors: Christian Queinnec, Pierre Cointe
Venue: Proceedings of the 1988 ACM conference on LISP and functional programming (1988)

The goal of this paper is to describe an open-ended type system for Lisp with explicit and full control of bit-level data representations. This description uses a reflective architecture based on a metatype facility. This low-level formalism solves the problem of an harmonious design of a class taxononomy inside a type system. A prototype for this framework has been written in Le-Lisp and is used to build the integrated type and object systems of the EU_LISP proposal.
Mache: no-loss trace compaction
Authors: A. D. Samples
Venue: ACM SIGMETRICS Performance Evaluation Review (1989)

Execution traces can be significantly compressed using their referencing locality. A simple observation leads to a technique capable of compressing execution traces by an order of magnitude; instruction-only traces are compressed by two orders of magnitude. This technique is unlike previously reported trace compression techniques in that it compresses without loss of information and, therefore, does not affect trace-driven simulation time or accuracy.
Invariant Properties of Straight Homogeneous Generalized Cylinders and Their Contours
Authors: J. Ponce, D. Chelberg, W. B. Mann
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1989)

A fundamental group in computer vision is the recovery of three-dimensional shape from image data. While this problem is in general underconstrained, the authors show that it can be simplified in the case where the objects being viewed are generalized cylinders. They consider the class of straight homogeneous generalized cylinders (SHGCs), without any further assumption on the viewing direction or the precise shape of these objects. They present a rigorous mathematical study of the geometry of SHGCs and characterize their Gaussian curvature and occluding contours, and use these results to prove several new invariant properties of the contours of SHGCs. These properties are, in turn, used in two implemented algorithms for recovering SHGC descriptions from image contours. Several examples of segmentation of real images are given. Other applications are also discussed.
Automated diagnosis of analog circuits
Authors: David W. Tong, Kevin C. Zalondek, Christopher H. Jolly
Venue: Proceedings of the 2nd international conference on Industrial and engineering applications of artificial intelligence and expert systems - Volume 1 (1989)

While a number of different approaches have been proposed to automatically troubleshoot electronic systems given schematic information, few are sufficiently powerful to tackle the complexity of analog circuits at the resistor/transistor level. This paper describes work which applies quantitative model-based reasoning techniques to this problem. The circuit schematic is converted into a constraint diagram to which the combination of constraint propagation and dependency tracking are applied to search for inconsistencies and identify the implicated components. Instead of resorting to the propagation of symbols, the technique of aggregate models is used to enhance deductive power but with manageable computation. These ideas have been implemented in the program FIX which diagnoses a given circuit by recognizing inconsistencies among measurements, identifies the set of fault candidates and their posterior probabilities, and suggests the best next measurement. Modeling and inference issues are discussed, and diagnosis of various faults in an example circuit by FIX is described.
Uniformity tests on the GPSS-Fortran pseudorandom number generators
Authors: Gerritt K. Janssens
Venue: ACM SIGSIM Simulation Digest (1988)

A fundamental characteristic of pseudorandom number generators is their uniformity. often in simulation packages the user has to accept the generators provided and has no control on their quality. GPSS-FORTRAN however is a package of FORTRAN-subroutines in which the generators are clearly presented to the user. In this paper we test the 30 generators available, warn the users not to use some of the generators for prespecified sample sizes and create a table containing the best available generators for the same sample sizes.
Parallelization and performance evaluation of circuit simulation on a shared-memory multiprocessor
Authors: P. Sadayappan, V. Visvanathan
Venue: Proceedings of the 2nd international conference on Supercomputing (1988)

Circuit simulation is a widely used but computationally demanding tool for VLSI design. In this paper, the considerations in achieving performance improvement through parallelization on a shared-memory multiprocessor are addressed. The two main components that comprise the computational bulk of circuit simulation, namely, matrix assembly and sparse matrix solution, raise very different issues in their parallelization. Parallelizing matrix assembly involves using a sequence of lock-synchronized parallel loops. A theoretical prediction of the performance of such loops is developed and this prediction is then compared to actual performance on a variety of circuits. Two approaches to parallel sparse matrix solution are contrasted: 1) an efficient implementation of an earlier proposed fine-grained model that captures parallelism at the elemental-operation level, and 2) a newly proposed medium-grained scheme that represents the computation at the row-operation level. A performance-evaluation framework is developed to interpret measured speedup in terms of various relevant factors. While the fine-grained approach achieves somewhat better load-balancing and also slightly lower scheduling overheads due to judicious task-clustering, the medium-grained approach is shown to be consistently superior for large circuit matrices due to lower operand access costs and better vectorization potential. The techniques developed have been incorporated into a prototype parallel implementation of the production circuit simulator ADVICE on the Alliant FX/8 multiprocessor.