ppxscal/embedding_network huggingface dataset:
Error catch and analysis for semiconductor memories using march tests
Authors: Chi Feng Wu, Chih Tsun Huang, Chih Wea Wang, Kuo Liang Cheng, Cheng Wen Wu
Venue: Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design (2000)

We present an error catch and analysis (ECA) system for semiconductor memories. The system consists of a test algorithm generator called TAGS, a fault simulator called RAM-SES, and an error analyzer (ERA). We use TAGS to generate a set of test algorithms of different lengths and diagnostic resolutions for the memory under test, and use RAMSES to generate the March dictionary for each test algorithm. With the March dictionaries, ERA is able to support March algorithms for easy diagnosis of faulty RAMs. Legacy test algorithms also can be reused. When integrated with a RAM tester, our ECA system can generate RAM bitmaps that are similar to the RAM layout. The bitmaps provide detail information about the error locations and faults causing the errors. Based on the information, diagnosis of the RAM chips for yield and reliability improvement can be done more easily.
Understanding and Reducing Web Delays
Authors: Mazen Zari, Hossein Saiedian, Muhammad Naeem
Venue: Computer (2001)

Slow performance costs e-commerce Web sites as much as $4.35 billion annually in lost revenue. Perceived latency-the amount of time between when a user issues a request and receives a response-is a critical issue. Research into improving performance falls into two categories: work on servers and work on networks and protocols. On the server side, previous work has focused on techniques for improving server performance. Such studies show how Web servers behave under a range of loads. These studies often suggest enhancements to application implementations and the operating systems those servers run. On the network side, research has focused on improving network infrastructure performance for Internet applications. Studies focusing on network dynamics have resulted in several enhancements to HTTP, including data compression, persistent connections, and pipelining. These improvements are all part of HTTP 1.1. However, little work has been done on common latency sources that cause the overall delays that frustrate end users. The future of performance improvements lies in developing additional techniques to help implement efficient, scalable, and stable improvements that enhance the end-user experience.
Efficient Aggregation Algorithms for Compressed Data Warehouses
Authors: J. Li, J. Srivastava
Venue: IEEE Transactions on Knowledge and Data Engineering (2002)

Aggregation and cube are important operations for online analytical processing (OLAP). Many efficient algorithms to compute aggregation and cube for relational OLAP have been developed. Some work has been done on efficiently computing cube for multidimensional data warehouses that store data sets in multidimensional arrays rather than in tables. However, to our knowledge, there is nothing to date in the literature describing aggregation algorithms on compressed data warehouses for multidimensional OLAP. This paper presents a set of aggregation algorithms on compressed data warehouses for multidimensional OLAP. These algorithms operate directly on compressed data sets, which are compressed by the mapping-complete compression methods, without the need to first decompress them. The algorithms have different performance behaviors as a function of the data set parameters, sizes of outputs and main memory availability. The algorithms are described and the I/O and CPU cost functions are presented in this paper. A decision procedure to select the most efficient algorithm for a given aggregation request is also proposed. The analysis and experimental results show that the algorithms have better performance on sparse data than the previous aggregation algorithms.
Effectiveness of Parallel Joins
Authors: M. S. Lakshmi, P. S. Yu
Venue: IEEE Transactions on Knowledge and Data Engineering (1990)

The effectiveness of parallel processing of relational join operations is examined. The skew in the distribution of join attribute values and the stochastic nature of the task processing times are identified as the major factors that can affect the effective exploitation of parallelism. Expressions for the execution time of parallel hash join and semijoin are derived and their effectiveness analyzed. When many small processors are used in the parallel architecture, the skew can result in some processors becoming sources of bottleneck while other processors are being underutilized. Even in the absence of skew, the variations in the processing times of the parallel tasks belonging to a query can lead to high task synchronization delay and impact the maximum speedup achievable through parallel execution. For example, when the task processing time on each processor is exponential with the same mean, the speedup is proportional to P/ln(P) where P is the number of processors. Other factors such as memory size, communication bandwidth, etc., can lead to even lower speedup. These are quantified using analytical models.
Designing and Conducting an Empirical Study on Test Management Automation
Authors: Griselda Giraudo, Paolo Tonella
Venue: Empirical Software Engineering (2003)

Test management aims at organizing, documenting and executing test cases, and at generating execution reports. The adoption of a support tool and of a standard process for such activities is expected to improve the current practice. ITALO is a European project devoted to the evaluation of the benefits coming from test management automation. In this paper the experiences collected and the lessons learned during ITALO are summarized. A formal methodology was adopted for the selection of a support tool among those available from the market. A survey of the current practice in component testing was conducted to adapt the existing process model so as to obtain the greatest benefits from automation. An empirical study was then designed to measure the effects that are expected to be produced by the new test process complemented with the introduction of the support tool. Three pilot projects were conducted to measure the benefits obtained from tool usage and process modification. Results are presented and discussed in this paper.
2-factors in dense bipartite graphs
Authors: A. Czygrinow, H. A. Kierstead
Venue: Discrete Mathematics (2002)

An n-ladder is a balanced bipartite graph with vertex sets A = {a,..., an} and B = {b1,..., bn} such that ai ∼ bj iff |i-j| ≤ 1. We use techniques developed recently by Komlós et al. (1997) to show that if G = (U,V,E) is a bipartite graph with |U| = n = |V|, with n sufficiently large, and the minimum degree of G is at least n/2 + 1, then G contains an n-ladder. This answers a question of Wang.
Imbedding Rule Inferencing in Applications
Authors: David W. Franke
Venue: IEEE Expert: Intelligent Systems and Their Applications (1990)

The CAD Inference Engine (CADIE) is discussed. CADIE implements a rule-inferencing capability intended to be embedded in CAD tools. The primary goal is to integrate tightly a rule-based inferencing capability and CAD tools developed in an object-oriented language, specifically C++. CADIE examines tool data directly, thereby avoiding translations and enabling the rule-based problem solver to be integrated into a tool that supports an existing design activity. CADIE accomplishes this access without additional data fields in tool defined data structures. The program achieves integration by making use of features of object-oriented languages that enable the inference engine to remain application independent and that require only minor changes to application code and data structure definitions. The object-oriented design of the inference engine and the interface between the inference engine and tool-defined data structures are described.
A Performance Study of Robust Load Sharing Strategies for Distributed Heterogeneous Web Server Systems
Authors: M. Colajanni, P. S. Yu
Venue: IEEE Transactions on Knowledge and Data Engineering (2002)

Replication of information across multiple servers is becoming a common approach to support popular Web sites. A distributed architecture with some mechanisms to assign client requests to Web servers is more scalable than any centralized or mirrored architecture. In this paper, we consider distributed systems in which the Authoritative Domain Name Server (ADNS) of the Web site takes the request dispatcher role by mapping the URL hostname into the IP address of a visible node, that is, a Web server or a Web cluster interface. This architecture can support local and geographical distribution of the Web servers. However, the ADNS controls only a very small fraction of the requests reaching the Web site because the address mapping is not requested for each client access. Indeed, to reduce Internet traffic, address resolution is cached at various name servers for a time-to-live (TTL) period. This opens an entirely new set of problems that traditional centralized schedulers of parallel/distributed systems do not have to face. The heterogeneity assumption on Web node capacity, which is much more likely in practice, increases the order of complexity of the request assignment problem and severely affects the applicability and performance of the existing load sharing algorithms. We propose new assignment strategies, namely adaptive TTL schemes, which tailor the TTL value for each address mapping instead of using a fixed value for all mapping requests. The adaptive TTL schemes are able to address both the nonuniformity of client requests and the heterogeneous capacity of Web server nodes. Extensive simulations show that the proposed algorithms are very effective in avoiding node overload, even for high levels of heterogeneity and limited ADNS control.
Applying an Agent-Oriented Methodology to the Design of Artificial Organizations: A Case Study in Robotic Soccer
Authors: A. Drogoul, A. Collinot
Venue: Autonomous Agents and Multi-Agent Systems (1998)

The multi-agent paradigm is widely used to provide solutions to a number of organizational problems related to the collective achievement of one or more tasks. All these problems share a common difficulty of design: how to proceed from the global specification of a collective task to the specification of the local behaviors to be provided to the agents? We have defined the Cassiopeia method whose specificity is to articulate the design of a multi-agent system around the notion of organization. This paper reports the use of this method for designing and implementing the organization of a soccer-playing robotic team. We show why we chose this application and how we designed it, and we discuss its interest and inherent difficulties in order to clearly express the needs for a design methodology dedicated to DAI.
Using Control Theory to Achieve Service Level Objectives In Performance Management
Authors: S. Parekh, N. Gandhi, J. Hellerstein, D. Tilbury, T. Jayram, J. Bigus
Venue: Real-Time Systems (2002)

A widely used approach to achieving service level objectives for a software system (e.g., an email server) is to add a controller that manipulates the target system&rsquo;s tuning parameters. We describe a methodology for designing such controllers for software systems that builds on classical control theory. The classical approach proceeds in two steps: system identification and controller design. In system identification, we construct mathematical models of the target system. Traditionally, this has been based on a first-principles approach, using detailed knowledge of the target system. Such models can be complex and difficult to build, validate, use, and maintain. In our methodology, a statistical (ARMA) model is fit to historical measurements of the target being controlled. These models are easier to obtain and use and allow us to apply control-theoretic design techniques to a larger class of systems. When applied to a Lotus Notes groupware server, we obtain model-fits with R^{2} no lower than 75% and as high as 98%. In controller design, an analysis of the models leads to a controller that will achieve the service level objectives. We report on an analysis of a closed-loop system using an integral control law with Lotus Notes as the target. The objective is to maintain a reference queue length. Using root-locus analysis from control theory, we are able to predict the occurrence (or absence) of controller-induced oscillations in the system&rsquo;s response. Such oscillations are undesirable since they increase variability, thereby resulting in a failure to meet the service level objective. We implement this controller for a real Lotus Notes system, and observe a remarkable correspondence between the behavior of the real system and the predictions of the analysis. This indicates that the control theoretic analysis is sufficient to select controller parameters that meet the desired goals, and the need for simulations is reduced.
On Process Migration and Load Balancing in Time Warp
Authors: D. W. Glazer, C. Tropper
Venue: IEEE Transactions on Parallel and Distributed Systems (1993)

A load balancing algorithm for a discrete event simulation executed under Time Warp ispresented. The algorithm rests upon recent developments in active process migration,which permit the use of dynamic strategies. Dynamic load balancing allows forreadjustments when resource requirements vary during simulation. It is also useful wheninitial resource predictions are unknown or incorrect. A simulated multiprocessorenvironment (PARALLEX) was developed in order to evaluate the algorithm. The resultsindicate that substantial performance gains may be realized with the algorithm.
Electrochemical mechanical deposition (ECMD) Technique for semiconductor interconnect applications
Authors: B. M. Basol, C. E. Uzoh, H. Talieh, D. Young, P. Lindquist, T. Wang, M. Cornejo
Venue: Microelectronic Engineering (2002)

A novel electrodeposition technique is described for deposition of conductors on non-planar surfaces of substrates in a planar manner. Electrochemical Mechanical Deposition (ECMD) technique involves simultaneous electrochemical deposition and mechanical polishing of the substrate surface. Copper layers deposited by the ECMD process grow preferentially in cavities on the wafer surface yielding flat profiles and much reduced overburden thickness. ECMD technology's potential to reduce cost of interconnect fabrication and some of its enabling features are discussed in this paper.
Performance Evaluation of a Threshold Policy for Scheduling Readers and Writers
Authors: A. Thomasian, V. F. Nicola
Venue: IEEE Transactions on Computers (1993)

An analysis of a threshold policy for scheduling readers and writers in a multiserver system and a comparison of its performance with the first-come, first-served (FCFS) policy are presented. The threshold fastest emptying (FTE) policy is analyzed in a system with writer arrivals and an infinite backlog of readers using a Markovian model as well as a vacationing server model to yield closed-form expressions for the mean writer response time and the reader throughput. The maximum throughput achieved by the TFE policy is shown to be an increasing function of K, the threshold on the number of writers in the system, which even at K=1 exceeds the maximum throughput achieved by FCFS. In a system with reader and writer arrivals (nonsaturated system), simulation is used to study and compare the mean response time for the FCFS and the TFE policies.
The 68040 Processor. I. Design and Implementation
Authors: Robin W. Edenfield, Michael G. Gallup, William B. Ledbetter,  Jr., Ralph C. McGarity, Eric E. Quintana, Russel A. Reininger
Venue: IEEE Micro (1990)

The design of the 68040, a third-generation, full-32-b microprocessor in the Motorola 68000 family, is presented. The 68040 integrates over 1.2 million transistors on one chip and can execute the complete 68020 microprocessor and 68882 floating-point coprocessor instruction sets. Pipelined integer and floating-point execution units that operate concurrently with separate internal memory controllers and an autonomous bus controller contribute to its high performance level. Physical caches of 4 kB each for instruction and data reside on chip. Separate address-translation caches of 64 entries apiece operate in parallel with the instruction and data caches. This arrangement provides complete memory management in a virtual, demand-paged operating system. The design team explains its total approach and the workings of the integer and floating-point units.
Direct observation of excited states in double quantum dot silicon single electron transistor
Authors: B. H. Choi, S. H. Son, K. H. Cho, S. W. Hwang, D. Ahn, D. H. Kim, J. D. Lee, B. G. Park
Venue: Microelectronic Engineering (2002)

We report, in this paper, the detailed measurements obtained from the double quantum dot silicon single electron transistors. Both the drain current and the differential conductance measurements in large drain voltage regime show small conductance peaks--as many as seven. The differential conductance contour exhibits many small diamond-like features other than main Coulomb blockade diamonds. The extracted quantum energy of the dot is 2.52 meV, which is only six times smaller than the charging energy and the Monte-Carlo simulation results are qualitatively consistent with the measured results.
ECOSystem: managing energy as a first class operating system resource
Authors: Heng Zeng, Carla S. Ellis, Alvin R. Lebeck, Amin Vahdat
Venue: ACM SIGPLAN Notices (2002)

Energy consumption has recently been widely recognized as a major challenge of computer systems design. This paper explores how to support energy as a first-class operating system resource. Energy, because of its global system nature, presents challenges beyond those of conventional resource management. To meet these challenges we propose the Currentcy Model that unifies energy accounting over diverse hardware components and enables fair allocation of available energy among applications. Our particular goal is to extend battery lifetime by limiting the average discharge rate and to share this limited resource among competing task according to user preferences. To demonstrate how our framework supports explicit control over the battery resource we implemented ECOSystem, a modified Linux, that incorporates our currentcy model. Experimental results show that ECOSystem accurately accounts for the energy consumed by asynchronous device operation, can achieve a target battery lifetime, and proportionally shares the limited energy resource among competing tasks.
Component-Based APIs for Versioning and Distributed Applications
Authors: Robert J. Stets, Galen C. Hunt, Michael L. Scott
Venue: Computer (1999)

Operating system application programming interfaces (APIs) are typically monolithic procedural interfaces that address a single machine's requirements. This design limits evolutionary development and complicates application development for distributed systems. Current APIs tend to be large, rigid, and focus on a single host machine. Component-based APIs could solve these problems through strong versioning capabilities and support for distributed applications. Ideally, obsolete API calls should be deleted, and calls with modified semantics (but unmodified parameters and return values) would remain the same. However, since the OS must continue to support legacy applications, obsolete calls cannot be deleted, and new call semantics are best introduced through new calls. In addition, typical OS APIs do not adequately address the needs of distributed applications: They have support for intermachine communication but lack high-level support for accessing remote OS resources. The primary omission is a uniform method for naming remote resources, such as windows, files, and synchronization objects.
Rule Ordering in Bottom-Up Fixpoint Evaluation of Logic Programs
Authors: R. Ramakrishnan, D. Srivastava, S. Sudarshan
Venue: IEEE Transactions on Knowledge and Data Engineering (1994)

Logic programs can be evaluated bottom-up by repeatedly applying all rules, in "iterations", until the fixpoint is reached. However, it is often desirable-and, in some cases, e.g. programs with stratified negation, it is even necessary to guarantee the semantics-to apply the rules in some order. We present two algorithms that apply rules in a specified order without repeating inferences. One of them (GSN) is capable of dealing with a wide range of rule orderings, but with a little more overhead than the well-known seminaive algorithm (which we call BSN). The other (PSN) handles a smaller class of rule orderings, but with no overheads beyond those in BSN. We also demonstrate that by choosing a good ordering, we can reduce the number of rule applications (and thus the number of joins). We present a theoretical analysis of rule orderings and identify orderings that minimize the number of rule applications (for all possible instances of the base relations) with respect to a class of orderings called fair orderings. We also show that though nonfair orderings may do a little better on some data sets, they can do much worse on others. The analysis is supplemented by performance results.
Web Animation with Macromedia Flash 2, 10th edition
Authors: Ken Milburn, Janine Warner
Venue:  (1997)

:In addition to professional animation techniques, you'll also discover Flash 2's versatile features for handling countless other graphics tasks. This extensively illustrated, step-by-step guide shows you how to automate drawing tasks, learn the animation process, harness advanced techniques, create Web-efficient files, and learn from the masters at NBC and Microsoft Network.
The 68040 Processor. 2. Memory Design and Chip
Authors: Robin W. Edenfield, Michael G. Gallup, William B. Ledbetter,  Jr., Ralph C. McGarity, Eric E. Quintana, Russel A. Reininger
Venue: IEEE Micro (1990)

For pt.1 see ibid., February (1990). The memory subsystem, the external bus, chip and board testing, and design-verification methods for the 68040, a third-generation, full-32-bit microprocessor in the Motorola 68000 family, are discussed. The internal caches and memory management are examined at length. The external bus protocol, arbitration, snooping, and timing specifications are addressed. The MOVE16 instruction, which moves a cache line from one address (which may reside in the data cache) to another address outside the cache is described. User testing, based on dedicated test logic that is fully compliant with the IEEE 1149.1 standard, and factory testing, for which the processor employs structured design techniques for random logic and special test modes for embedded arrays, are examined. The use of top-down design and a hierarchical method of design verification is discussed.
Some Results on a SRT Type Division Scheme
Authors: D. M. Mandelbaum
Venue: IEEE Transactions on Computers (1993)

A variation of a division method previously presented by the author (1990) is described. The method is of the SRT type. This present scheme is based upon a system of recursion equations derived from the equation 1/A=Q. Its advantages are presented.
The TX1 32-Bit Microprocessor: Performance Analysis, and Debugging Support
Authors: Misao Miyata, Hidechika Kishigami, Kosei Okamoto, Shigeo Kamiya
Venue: IEEE Micro (1988)

The 32-bit TX1 microprocessor, developed to meet the architectural specification of Japan's TRON (The Real-Time-Operating Nucleus) project, has been given a loosely coupled pipeline structure to meet the demands of high-performance systems. The authors discuss the design architecture of the TX1, provide some performance analysis for the design, and describe the debugging feature provided on the processor. Results for several benchmark programs show that the average performance of the TX1 is over 5 MIPS (million instructions per second).