ppxscal/embedding_network huggingface dataset:
A Distributed Architecture for Cooperative and Adaptative Multimedia Applications
Authors: Philippe Roose, Marc Dalmau, Franck Luthon
Venue: Proceedings of the 26th International Computer Software and Applications Conference on Prolonging Software Life: Development and Redevelopment (2002)

Previously, we developed a method and a distributed platform for the re-engineering of applications by adding cooperation. The goal was to supply a way of communication based on the exchange of events, messages and shared data. Now, we propose to adapt this approach (method and platform) to distributed multimedia applications. These applications present the characteristic to be organized around the communication. So, we can consider them as composed of distributed components which have to collaborate. Because it is heavilyinteractive, such an application needs to adapt itself in real-time to the user and to the environment in which it runs. Our approach consists in breaking down the application into two levels : the first one reflects the users' point of view in terms of functionalities. The second one, reflects the way to achieve these functionalities in terms of quality of service. We propose to organize components into workgroups and subworkgroups corresponding to thistwo levels. The platform manages these groups and makes them evolve in real time. It also ensures the inter-operability of components which cooperate in these groups.
S-Check: a Tool for Tuning Parallel Programs
Authors: Robert Snelick
Venue: Proceedings of the 11th International Symposium on Parallel Processing (1997)

We present a novel tool, called S-Check, for identifying performance bottlenecks in parallel and networked pro-grams. S-Check is a highly-automated sensitivity analysis tool for programs that extends benchmarking and conven-tional profiling. It predicts how refinements in parts of a program are going to affect performance by making local changes in code efficiencies and correlating these against overall program performance. This analysis is a sophisti-cated comparison that catches interactions arising from shared resources or communication links. S-Check's per-formance assessment ranks code segments (bottlenecks) according to their sensitivity to the code efficiency changes. This rank-ordered list serves as a guide for tuning applications. In practice, S-Check code analysis yields faster parallel programs. A case study compares and con-trasts sensitivity analyses of the same program on different architectures and offers solutions for performance improvement. An initial implementation of S-Check runs on Silicon Graphics multiprocessors and IBM SP machines. Particulars of the underlying methodology are only sketched, with main emphasis given to details of the tool S-Check and its use.
A dynamic cache sub-block design to reduce false sharing
Authors: Murali Kadiyala, Laxmi N. Bhuyan
Venue: Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors (1995)

Parallel applications differ from significant bus traffic due to the transfer of shared data. Large block sizes exploit locality and decrease the effective memory access time. It also has a tendency to group data together even though only a part of it is needed by any one processor. This is known as the false sharing problem. This research presents a dynamic sub-block coherence protocol which minimizes false sharing by trying to dynamically locate the point of false reference. Sharing traffic is minimized by maintaining coherence on smaller blocks (sub-blocks) which are truly shared, whereas larger blocks are used as the basic units of transfer. Larger blocks exploit locality while coherence is maintained on sub-blocks which minimize bus traffic due to shared misses. The simulation results indicate that the dynamic sub-block protocol reduces the false sharing misses by 20 to 30 percent over the fixed sub-block scheme.
Performance Analysis of Traffic Control System Based on Stochastic Timed Petri Net Models
Authors: Jiacun Wang, Chun Jin, Yi Deng
Venue: 23rd International Computer Software and Applications Conference (1999)

We present a new modeling method to evaluate the performance indices of traffic control systems where each intersection has two or four phases. The method is based on the stochastic timed Petri net models of isolated intersections. It considers one direction of traffic along a street each time, and the interactions between traffic of different directions are partially approximated by statistical models. By so doing, it dramatically reduces the computing complexity that other Petri net-based methods suffer due to the consideration of detailed interactions among all directions of traffic. An example is presented to show the potential application of the new method.
On Mining General Temporal Association Rules in a Publication Database
Authors: Chang-Hung Lee, Cheng-Ri Lin, Ming-Syan Chen
Venue: Proceedings of the 2001 IEEE International Conference on Data Mining (2001)

In this paper, we explore a new problem of mining general temporal association rules in publication databases. In essence, a publication database is a set of transactions where each transaction T is a set of items of which each item contains an individual exhibition period. The current model of association rule mining is not able to handle the publication database due to the following fundamental problems, i.e., (1) lack of consideration of the exhibition period of each individual item; (2) lack of an equitable support counting basis for each item. To remedy this, we propose an innovative algorithm Progressive-Partition-Miner (abbreviatedly as PPM) to discover general temporal association rules in a publication database. The basic idea ofPPM is to first partition the publication database in light of exhibition periods of items and then progressively accumulate the occurrence count of each candidate 2-itemset based on the intrinsic partitioning characteristics. Algorithm PPM is also designed to employ a filtering threshold in each partition to early prune out those cumulatively infrequent 2-itemsets. Explicitly, the execution time of PPM is, in orders of magnitude, smaller than those required by the schemes which are directly extended from existing methods.
Linear Features Detection in SAR Images for Urban Analysis
Authors: R. C. S. Costa, F. N. S. Medeiros
Venue: Proceedings of the 15th Brazilian Symposium on Computer Graphics and Image Processing (2002)

This work is concerned with extracting straight lines in SAR image areas for application of urban analysis. The methodology combines the Hough transform and the line detectors algorithms proposed in Tupin et al. [2] to extract the main axes in road networks. A real SAR image is used to test the proposed algorithm.
The Partitioned Optical Passive Stars (POPS) topology
Authors: Greg Gravenstreter, Rami G. Melhem, Donald M. Chiarulli, Steven P. Levitan, J. P. Teza
Venue: Proceedings of the 9th International Symposium on Parallel Processing (1995)

This paper presents and analyzes a topological approach to providing multiple data channels using current technologies. The Partitioned Optical Passive Stars (POPS) topology is an all-optical interconnection architecture that uses multiple non-hierarchical couplers. POPS topologies provide powerful configurability for optimization of system complexity, network throughput, power budget, and control overhead. It is shown that high performance and utilization is achieved for random communication patterns. POPS topologies maintain these characteristics even when scaled to large systems.
Concurrent Zero Knowledge with Logarithmic Round-Complexity
Authors: Manoj Prabhakaran, Alon Rosen, Amit Sahai
Venue: Proceedings of the 43rd Symposium on Foundations of Computer Science (2002)

We show that every language in NP has a (black-box) concurrent zero-knowledge proof system using \widetilde0(\log n) rounds of interaction. The number of rounds in our protocol is optimal, in the sense that any language outside BPP requires at least \widetilde\Omega (\log n) rounds of interaction in order to be proved in black-box concurrent zero-knowledge. The zero-knowledge property of our main protocol is proved under the assumption that there exists a collection of claw-free functions. Assuming only the existence of one-way functions, we show the existence of \widetilde0(\log n)-round concurrent zero-knowledge arguments for all languages in NP .
HierarchyScan: A Hierarchical Similarity Search Algorithm for Databases of Long Sequences
Authors: Chung-Sheng Li, Philip S. Yu, Vittorio Castelli
Venue: Proceedings of the Twelfth International Conference on Data Engineering (1996)

We present a hierarchical algorithm, HierarchyScan, that efficiently locates one-dimensional subsequences within a collection of sequences of arbitrary length. The subsequences identified by HierarchyScan match a given template pattern in a scale- and phase-independent fashion. The idea is to perform correlation between the stored sequences and the template in the transformed domain hierarchically. Only those subsequences whose maximum correlation value is higher than a predefined threshold will be selected. The performance of this approach is compared to the sequential scanning and an order-of-magnitude speedup is observed.
2.5n-Step Sorting on n*n Meshes in the Presence of o(sqrt(n)) Worst-Case Faults
Authors: Chi-Hsiang Yeh, Behrooz Parhami, Hua Lee, Emmanouel A. Varvarigos
Venue: Proceedings of the 13th International Symposium on Parallel Processing and the 10th Symposium on Parallel and Distributed Processing (1999)

In this paper, we propose the robust algorithm-configured emulation (RACE) scheme for the design of simple and efficient robust algorithms that can run on faulty mesh-connected computers. We show that 1-1 sorting (1 key per healthy processor) can be performed in 2:5n + o(n) communication steps and 2n + o(n) comparison steps on an n × n mesh with an arbitrary pattern of o(vn) faults. This running time has exactly the same leading constant as the best known algorithms for 1-1 sorting on an n × n fault-free mesh. We also formulate the mesh robustness theorem, which leads to a variety of efficient robust algorithms on faulty meshes.
Nearly Optimal One-To-Many Parallel Routing in Star Networks
Authors: Chi-Chang Chen, Jianer Chen
Venue: Proceedings of the 11th International Symposium on Parallel Processing (1997)

Star networks were proposed recently as an attractive alternative to the well-known hypercube models for interconnection networks. Extensive research has been performed that shows that star networks are as versatile as hypercubes. This paper is an effort in the same direction. Based on the well-known paradigms, we study the one-to-many parallel routing problem on star networks and develop an improved routing algorithm that finds n-1 node-disjoint paths between one node and a set of other n-1 nodes in the n-star network. These parallel paths are proven of minimum length within a small additive constant, and our algorithm has an optimal time complexity. This result significantly improves the previous known algorithms for the problem. Moreover, the algorithm well illustrates an application of the orthogonal partition of star networks, which was observed by the original inventors of the star networks but seems generally overlooked in the subsequent study. We should also point out that similar problems are already studied for hypercubes and have proven useful in designing efficient and fault tolerant routing algorithms on hypercube networks.
Large Standard Cell Libraries and Their Impact on Layout Area and Circuit Performanc
Authors: Bingzhong Guan, Carl Sechen
Venue: Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors (1996)

We present a complete study of layout area and circuit performance as a result of utilizing a large library of standard cells. We built libraries of all possible static CMOS cells having a chain length of up to 7. We refer to a library of all possible cells having a chain length limit of n as sn. Although library s7 has billions of possible cells in it, our technology mapper only selected on the order of 100 of these cells to implement each of the MCNC logic synthesis benchmark circuits. We drew the following conclusions from this study. 1) For three or more layers of metal, using very large libraries (e. g., s7) is optimal in terms of area and delay. 2) For two layers of metal, lim iting the library size to s5, but at least s4, is optimal in terms of area and delay. Given that the number of distinct combinational cells in industrial libraries today never exceeds 200 (and usually considerably fewer) and given that even library s4 has 3503 distinct cells, tremendous area savings (without increase in worst case path delay) are readily available by utilizing much larger cell libraries. Specifically, given that library s3 has 87 distinct cells (current industrial libraries typically have no more than this), we surmise that area savings of about 30% can be achieved by using library s7 for three or more metal layers versus any current indus trial library.
Efficient Execution of Parallel Applications in Multiprogrammed Multiprocessor Systems
Authors: Kelvin K. Yue, David J. Lilja
Venue: Proceedings of the 10th International Parallel Processing Symposium (1996)

Existing techniques for sharing the processing resources in multiprogrammed shared-memory multiprocessors, such as time-sharing, space-sharing, and gang-scheduling, typically sacrifice the performance of individual parallel applications to improve overall system utilization. We present a new processor allocation technique that dynamically adjusts the number of processors an application is allowed to use for the execution of each parallel section of code based on the current system load. This approach exploits the maximum parallelism possible for each application without overloading the system. We implement our scheme on a Silicon Graphics Challenge multiprocessor system and evaluate its performance using applications from the Perfect Club benchmark suite and synthetic benchmarks. Our approach shows significant improvements over traditional time-sharing and gang scheduling. It has performance comparable to, or slightly better than, static space-sharing, but our strategy is more robust since, unlike static space-sharing, it does not require a priori knowledge of the applications' parallelism characteristics.
On Similarity Measures for Cluster Analysis in Clinical Laboratory Examination Databases
Authors: Shoji Hirano, Xiaoguang Sun, Shusaku Tsumoto
Venue: Proceedings of the 26th International Computer Software and Applications Conference on Prolonging Software Life: Development and Redevelopment (2002)

This paper discusses ho the conventional similarity measure orks on the practical medical data set. The similarity measure used as linear combination of the Mahalanobis distance between numerical attributes and the Hamming distance between nominal attributes. We performed clustering experiments on the meningoencephalitis data set using the similarity measure in conjunction with four types of clustering algorithms:single-and complete-linkage agglomerativehierarchical clustering, Ward's method and rough clustering. Usefulness of the similarity measure as evaluated from the following viewpoints: (1) quality of the generated clusters, (2) clinical reasonability of the attributes used to generate the high-quality clusters. The results showed that the best clusters were obtained using Ward's method where the clinically reasonable attributes were selected. It suggests that this similarity measures would be applicable to the medical data sets.
A Software Engineering Cognitive Knowledge Discovery Framework
Authors: Vincent Chiew
Venue: Proceedings of the 1st IEEE International Conference on Cognitive Informatics (2002)

Knowledge discovery has been proven useful in many areas such as marketing, signal processing and strategic military planning. Many approaches have been implemented to increase the discovered knowledge value and knowledge intelligence. This paper suggests one approach by proposing a Cognitive Knowledge Discovery Framework based on Cognitive Informatics. The discussions in this paper draw parallels between Computer Science technologies and Cognitive Science concepts, which involve the correlation between Software Engineering using Decision Tree technique and Cognitive Psychology.
Towards Point-Based Acquisition and Rendering of Large Real-World Environments
Authors: Wagner Toledo Corrêa, Shachar Fleishman, Cláudio T. Silva
Venue: Proceedings of the 15th Brazilian Symposium on Computer Graphics and Image Processing (2002)

Abstract. This paper describes a pipeline for the acquisition and rendering of large real-world environments. In the acquisition phase, we use a laser rangefinder to capture the geometry of an environment, and a digital camera to capture its colors. In the rendering phase, we use a cluster of commodity PCs to render high-resolution images of the environment at interactive frame rates. In this paper, we describe in detail our scanning hardware, the tools we use to minimize the acquisition artifacts in the 3D scans, the procedure to register the scans to each other, and how to map colors from a photograph to a scan. We also present a sequential, out-of-core rendering approach that uses multiple threads to overlap rendering, visibility computation, and disk operations. Finally, we show how to use the sequential rendering approach as a building block for a parallel rendering system that uses a cluster of PCs to drive a high-resolution, multi-projector display wall. Our acquisition approach allows us to capture environments that would be extremely difficult to model by hand, and our rendering approach allows us to use inexpensive PCs, instead of high-end graphics workstations, to visualize those environments at interactive frame rates.
Relaxed Index Consistency for a Client-Server Database
Authors: Vibby Gottemukkala, Edward Omiecinski, Umakishore Ramachandran
Venue: Proceedings of the Twelfth International Conference on Data Engineering (1996)

Client-Server systems cache data in client buffers to deliver good performance. Several efficient protocols have been proposed to maintain the coherence of the cached data. However, none of the protocols distinguish between index pages and data pages. We propose a new coherence protocol, called Relaxed Index Consistency, that exploits the inherent differences in the coherence and concurrency-control (C&CC) requirements for index and data pages. The key idea is to incur a small increase in computation time at the clients to gain a significant reduction in the number of messages exchanged between the clients and the servers. The protocol uses the concurrency control on data pages to maintain coherence of index pages. A performance-conscious implementation of the protocol that makes judicious use of version numbers is proposed. We show, through both qualitative and quantitative analysis, the performance benefits of making the distinction between index pages and data pages for the purposes of C&CC. Our simulation studies show that the Relaxed Index Consistency protocol improves system throughput by as much as 15% to 88%, based on the workload.
A Method for Analog Circuits Visualization
Authors: Bogdan G. Arsintescu
Venue: Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors (1996)

A method for visualization of analog circuit schematic starting from a netlist is described in this paper. The images obtained have a comprehensible form, symmetrical structures and other analog topological patterns being discovered in the circuit netlist. The method is based on two algorithms. The first one, the symmetry algorithm, exploits the possibility to extract topology information from a graph representation of the circuit. The second one performs a grid expansion on a directed graph structure, using the results of the symmetry algorithm. The method has been implemented in the ``A-warD'' program. Test-cases demonstrate the effectiveness of the method.
Parallel algorithms for logic synthesis using the MIS approach
Authors: Kaushik De, John A. Chandy, Sumit Roy, Steven Parkes, Prithviraj Banerjee
Venue: Proceedings of the 9th International Symposium on Parallel Processing (1995)

Combinational logic synthesis is a very important but computationally expensive phase of VLSI system design. Parallel processing offers an attractive solution to reduce this design cycle rime. In this paper we describe ProperMIS, a portable parallel algorithm for logic synthesis based on the MIS multi-level logic synthesis system. As part of this work, we have developed novel parallel algorithms for the different logic transformations of the MIS system. Our algorithm uses art asynchronous message-driven computing model with no synchronizing barriers separating phases of parallel computation. The algorithm is portable across a wide variety of parallel architectures, and is built around a well-defined sequential algorithm interface, so that we can benefit from future expansion of the sequential algorithm. We present results on several MCNC and ISCAS benchmark circuits for a variety of shared memory and distributed processing architectures. Our implementation produces speedups of an average of 4 on 8 processors.
IBM RS/6000 SP Interconnection Network Topologies for Large Systems
Authors: Harish Sethu, Craig B. Stunkel, Robert F. Stucke
Venue: Proceedings of the 1998 International Conference on Parallel Processing (1998)

While the interconnection network topology is one of the most important determinants of the performance of a parallel system, no single topology offers an ideal cost/performance trade-off for all classes of applications in parallel processing. The modular units used in the IBM RS/6000 SP topologies allow the construction of a large variety of topologies including 4-ary fat-tree networks. In our experience, however, cost and cost/performance ratio are often the primary concerns of customers. Therefore, while fat-tree topologies offer excellent performance, they are not always the most attractive choice for customers of large-scale parallel systems. This paper presents the lower-cost RS/6000 SP topologies for large systems designed with fewer switching elements than fat-tree networks, and describes some of the rationale behind the choices made.
An Optimal Disk Allocation Strategy for Partial Match Queries on Non-Uniform Cartesian Product Files
Authors: Sajal K. Das, Maria Cristina Pinotti
Venue: Proceedings of the 13th International Symposium on Parallel Processing and the 10th Symposium on Parallel and Distributed Processing (1999)

The disk allocation problem addresses the issue of how to distribute a file on to several disks to maximize the concurrent disk accesses in response to a partial match query. In the past this problem has been studied for binary as well as for $p$-ary cartesian product files.In this paper, we propose a disk allocation strategy for non-uniform cartesian product files by a coding theoretic approach. Our strictly optimal disk allocation strategies are based on a large and flexible class of maximum distance separable (MDS) codes, namely the redundant residue codes.