ppxscal/embedding_network huggingface dataset:
Research in music and artificial intelligence
Authors: Curtis Roads
Venue: ACM Computing Surveys (CSUR) (1985)

Although the boundaries of artificial intelligence (AI) remain elusive, computers can now perform musical tasks that were formerly associated exclusively with naturally intelligent musicians. After a historical note, this paper sermonizes on the need for AI techniques in four areas of musical research: composition, performance, music theory, and digital sound processing. The next part surveys recent work involving AI and music. The discussion concentrates on applications in the four areas of research just mentioned. The final part examines how AI techniques of planning and learning could be used to expand the knowledge base and enrich the behavior of musically intelligent systems.
Distribution of mathematical software via electronic mail
Authors: Jack J Dongarra, Eric Grosse
Venue: Communications of the ACM (1987)

A large collection of public-domain mathematical software is now available via electronic mail. Messages sent to "netlib&commat;anl-mcs" (on the Arpanet/CSNET) or to "research!netlib" (on the UNIX&reg; network) wake up a server that distributes items from the collection. The one-line message "send index" causes a library catalog to be sent by return mail.
StarLite, a visual simulation package for software prototyping
Authors: Robert P Cook, Rihard J Auletta
Venue: ACM SIGPLAN Notices (1987)

We describe a software prototyping environment implemented on the Lilith computer. By isolating hardware dependencies, the environment supports the development and testing of concurrent and distributed algorithms on a host as well as on the target hardware. A library of generic devices, which includes clocks, disks and EtherNets, is provided to support experimentation. The paper describes how any programming language can be extended to provide such an environment by adding subroutine packages for concurrent programming, simulation, and window management.
A Partitioning Strategy for Nonuniform Problems on Multiprocessors
Authors: M. J. Berger, S. H. Bokhari
Venue: IEEE Transactions on Computers (1987)

We consider the partitioning of a problem on a domain with unequal work estimates in different subdomains in a way that balances the workload across multiple processors. Such a problem arises for example in solving partial differential equations using an adaptive method that places extra grid points in certain subregions of the domain. We use a binary decomposition of the domain to partition it into rectangles requiring equal computational effort. We then study the communication costs of mapping this partitioning onto different multiprocessors: a mesh- connected array, a tree machine, and a hypercube. The communication cost expressions can be used to determine the optimal depth of the above partitioning.
IAI Corporate Software Engineering Training and Education Program
Authors: Jonah Z. Lavi, Moshe I. Ben Porat, Amram Ben-David
Venue: IEEE Transactions on Software Engineering (1987)

Israel Aircraft Industries has developed a comprehensive educational program in software engineering. Goals of the program include: the retraining of college graduates to become software engineers with specializations in one of three application areas (data processing, embedded computer systems, and CAD/CAM systems), and enhancement of the knowledge of currently practicing software engineers. The program is centered around three distinct full-time courses of study having an average duration of 7 months. The training program also includes a large number of short courses and seminars. The company is currently planning an M.Sc. program in embedded computer systems and software engineering in cooperation with one of the universities in Israel.
Supporting concurrency, communication, and synchronization in human-computer interaction&mdash;the Sassafras UIMS
Authors: Ralph D. Hill
Venue: ACM Transactions on Graphics (TOG) (1986)

Sassafras is a prototype User Interface Management System (UIMS) specifically designed to support a wide range of user interface styles. In particular, it supports the implementation of user interfaces where the user is free to manipulate multiple input devices and perform several (possibly related) tasks concurrently. These interfaces can be compactly represented and efficiently implemented without violating any of the rules of well-structured programming. Sassafras also supports elaborate run-time communication and synchronization among the modules that make up the user interface. This is needed to implement user interfaces that have context-sensitive defaults, and it simplifies recovery from semantic errors. Sassafras is based on a new language for specifying the syntax of human-computer dialogues known as Event-Response Language (ERL) and a new run-time structure and communication mechanism for UIMSs known as the Local Event Broadcast Method (LEBM). Both ERL and LEBM are described in detail, and implementation techniques are presented. The effectiveness of Sassafras is demonstrated by describing two interfaces that have been implemented with Sassafras.
Product-Form Solution Techniques for the Performance Analysis of Multiple-Bus Multiprocessor Systems with Nonuniform Memory References
Authors: Giovanni Chiola, Marco Ajmone Marsan, Gianfranco Balbo
Venue: IEEE Transactions on Computers (1988)

Recursive relations are derived for the exact computation of the steady-state probability distribution of some queuing models with passive resources that can be used to analyze the performance of multiple-bus multiprocessor system architectures. The most general case that can be shown to admit a product-form solution is described, and a recursive solution is obtained taking into account, considering different processor access rates, different memory selection probabilities, and a first-come-first-served bus scheduling policy. Several simpler cases allowing easier model solutions are also considered. Numerical evaluations for large computing systems with nonuniform memory references show the usefulness of the results.
Object-oriented concurrent programming ABCL/1
Authors: Akinori Yonezawa, Jean-Pierre Briot, Etsuya Shibayama
Venue: ACM SIGPLAN Notices (1986)

An object-oriented computation model is presented which is designed for modelling and describing a wide variety of concurrent systems. In this model, three types of message passing are incorporated. An overview of a programming language called ABCL/1, whose semantics faithfully reflects this computation model, is also presented. Using ABCL/1, a simple scheme of distributed problem solving is illustrated. Furthermore, we discuss the reply destination mechanism and its applications. A distributed &ldquo;same fringe&rdquo; algorithm is presented as an illustration of both the reply destination mechanism and the future type message passing which is one of the three message passing types in our computation model.
Performance Models of Asynchronous Multitrunk HYPERchannel Networks
Authors: I. Chlamtac, O. Ganz
Venue: IEEE Transactions on Computers (1987)

The HYPERchannel communication network based on one to four trunks, or channels is considered. We develop closed queueing models with dependent servers which characterize the network performance as a function of the number of channels, the channel load, the number of stations and the packet length distribution. For analyzing the network behavior with constant packet length we introduce techniques for representing the actual asynchronous network operation by a tractable "sequential synchronous" model. Throughput and delay measures are in this way obtained for asynchronous systems operating with constant or exponential service times. The developed approach can also be used for obtaining tractable analyses of other asynchronous systems, such as multiprocessors employing multiple-bus interconnection. In the case of HYPERchannel networks, we apply the introduced models for analyzing multi- trunk network behavior and for predicting the number of channels needed to obtain a required packet-delay/trunk-utilization performance. In HYPERchannel networks the observed results are of special significance since they are most pronounced when the number of stations is small, the situation found in the majority of operational networks.
Structured Assembly language in VAX-11 MACRO
Authors: Robert R. Leeper, Karl O. Rehmer
Venue: ACM SIGCSE Bulletin (1986)

For several years, the introductory assembly language course at Indiana-Purdue at Fort Wayne has used &ldquo;structured&rdquo; assembly language on an IBM System 370. A later course makes use of VAX-11 MACRO assembly language on a VAX 11/780. This paper shows how the major constructs for structured programming may be implemented in VAX-11 MACRO. The scheme involves assembly language templates for each of the constructs, a standard labeling scheme, and a commenting method which reflects the structure of the program.
PAMS: an expert system for parameterized module synthesis
Authors: t. Cesear, E. Iodice, C. Tsareff
Venue: Proceedings of the 24th ACM/IEEE Design Automation Conference (1987)

An expert system has been developed which converts a description of transistor connectivity into a parameterized CMOS module. PAMS was designed to augment a standard cell environment by automatically generating special purpose modules parameterized in terms of area, speed, and power dissipation. Allowing parameterization differentiates PAMS from previous expert systems work in this field.
Implementation of a parallel extended Kalman filter using a bit-serial silicon compiler
Authors: P. L. Shaffer
Venue: Proceedings of the 1987 Fall Joint Computer Conference on Exploring technology: today and tomorrow (1987)

Two different architectures to compute the extended Kalman filter have been designed using a bit-serial silicon compiler. For both systems, the Kalman filter is to be used for target tracking, with 9 states, 3 observations, and 3 process noise sources. The first system is a systolic-type architecture. Data matrices are presented by columns and data vectors presented by element, and recursive computations are used to triangularize matrices. The feedback necessary to use recursion limits the throughput of this architecture. For this application, with a 20 MHz clock rate, the throughput is 1736 samples/sec, and the latency (delay from data availability to production of results) is 0.859 msec. This circuit requires about 51 chips of 13 different types. The second system is a pipelined synchronous dataflow architecture. All data values are presented simultaneously, and recursion is not used. Because most of the matrices involved are triangular, block triangular, band, or sparse, the number of elements dealt with is manageable. The throughput of this system is simply the clock rate divided by the word length, or 625000 samples/sec. The circuit requires about 112 chips of 10 different types, and has a latency of 0.842 msec. This system could thus track 526 different targets at 1188 samples/sec each. Thus, by using about twice as many chips and avoiding recursion, the throughput was increased by 360 times.
A programmable interface language for heterogeneous distributed systems
Authors: Joseph R. Falcone
Venue: ACM Transactions on Computer Systems (TOCS) (1987)

The 1980s have witnessed the emergence of a new architecture for computing based on networks of personal computer workstations. The performance requirements of such systems of workstations places a strain on traditional approaches to network architecture. The integration of diverse systems into this environment introduces functional compatibility issues that are not present in homogeneous networks. Effective prescriptions for functional compatibility, therefore, must go beyond the communication paradigms used in present distributed systems, such as remote procedure calls. This paper proposes a distributed system architecture in which communication follows a programming paradigm. In this architecture a programming language provides remote service interfaces for the heterogeneous distributed system environment. This language is a flexible and efficient medium for implementing service function protocols. In essence, clients and servers communicate by programming one another.
Performance of the Expressnet with voice/data traffic
Authors: Timothy A. Gonsalves, Fouad A. Tobagi
Venue: Proceedings of the 1987 ACM SIGMETRICS conference on Measurement and modeling of computer systems (1987)

In the past few years, local area networks have come into widespread use for the interconnection of computers. Together with the trend towards digital transmission in voice telephony, this has spurred interest in integrated voice/data networks. The Expressnet, an implicit-token round-robin scheme using unidirectional busses, achieves high performance even at bandwidths of 100 Mb/s. Other features that make the protocol attractive for voice/data traffic are bounded delays and priorities. The latter is achieved by devoting alternate rounds to one or the other of the two traffic types. By the use of accurate simulation, the performance of the Expressnet with voice/data traffic is characterized. It is shown that the Expressnet satisfies the real-time constraints of voice traffic adequately even at bandwidths of 100 Mb/s. Data traffic is able to effectively utilize bandwidth unused by voice traffic. The trade-offs in the alternating round priority mechanism are quantified. Loss of voice samples under overload is shown to occur regularly in small, frequent clips, subjectively preferable to irregular clips. In a comparison of the Expressnet, the contention-based Ethernet and the round-robin Token Bus protocols, the two round-robin protocols are found to perform better than the Ethernet under heavy load owing to the more deterministic mode of operation. The comparison of the two round-robin protocols highlights the importance of minimizing scheduling overhead at high bandwidths.
Mathematics support for computing degrees: a small college perspective
Authors: Scott Sigman
Venue: Proceedings of the eighteenth SIGCSE technical symposium on Computer science education (1987)

This paper describes a study of the required mathematical support for the computing program at Southwest Baptist University. A list of requisite mathematical concepts identified in four core courses is presented. Additionally, the results of a survey of required mathematics support courses for eighty-four small colleges and universities offering computing programs are presented and contrasted with the concepts identified by the study. The results highlight the need for a freshmen level discrete mathematics course.
On the discrepancy of GFSR pseudorandom numbers
Authors: Shu Tezuka
Venue: Journal of the ACM (JACM) (1987)

A new summation formula based on the orthogonal property of Walsh functions is devised. Using this formula, the k-dimensional discrepancy of the generalized feedback shift register (GFSR) pseudorandom numbers is derived. The relation between the discrepancy and k-distribution of GFSR sequences is also obtained. Finally the definition of optimal GPSR pseudorandom number generators is introduced.
Elimination of intersection anomalies from database schemes
Authors: Catriel Beeri, Michael Kifer
Venue: Journal of the ACM (JACM) (1986)

The desirability of acyclic (conflict-free) schemes is well argued in [8] and [13]. When a scheme is described by multivalued dependencies, acyclicity means that the dependencies do not split each other's left-hand side and do not form intersection anomalies. It is shown that if the second condition fails to hold, the scheme can be amended so that it does hold. The basic step is to add one attribute and some dependencies to resolve one intersection anomaly. This step generates an extension of the given scheme in which the anomaly does not exist. Also, the iterative use of the basic step is analyzed and it is proved that the transformation so defined terminates and removes all intersection anomalies.
Amortized analyses of self-organizing sequential search heuristics
Authors: Jon L. Bentley, Catherine C. McGeoch
Venue: Communications of the ACM (1985)

The performance of sequential search can be enhanced by the use of heuristics that move elements closer to the front of the list as they are found. Previous analyses have characterized the performance of such heuristics probabilistically. In this article, we use amortization to analyze the heuristics in a worst-case sense; the relative merit of the heuristics in this analysis is different in the probabilistic analyses. Experiments show that the behavior of the heuristics on real data is more closely described by the amortized analyses than by the probabilistic analyses.
An editor for revision control
Authors: Christipher W. Fraser, Eugene W. Myers
Venue: ACM Transactions on Programming Languages and Systems (TOPLAS) (1987)

Programming environments support revision control in several guises. Explicitly, revision control software manages the trees of revisions that grow as software is modified. Implicitly, editors retain past versions by automatically saving backup copies and by allowing users to undo commands. This paper describes an editor that offers a uniform solution to these problems by never destroying the old version of the file being edited. It represents files using a generalization of AVL trees called &ldquo;AVL dags,&rdquo; which makes it affordable to automatically retain past versions of files. Automatic retention makes revision maintenance transparent to users. The editor also uses the same command language to edit both text and revision trees.
Statistics for parallelism and abstraction level in digital simulation
Authors: L. Soule, R. Blank
Venue: Proceedings of the 24th ACM/IEEE Design Automation Conference (1987)

This paper presents statistics of several designs at four design abstraction levels - the instruction, behavioral, RTL, and gate levels. The data includes simulation time profiles, maximum speedup and limitations of parallelism, typical model evaluation times, event distributions, element intensities, and component counts for the four abstraction levels. This data is then used to analyze and evaluate several speed-up approaches: mixed-level simulation, parallel software simulators, parallel pipelined hardware accelerators, and decreased time resolution. The results show that element activity is around 0.1 to 0.5% at any particular time point. For the example circuits (3400 gates, 5000 gates, and 150,000 transistors), simulations show that parallelism can obtain speed-ups between 10-30. We found a factor of roughly ten speed-up between each of the abstraction levels.
The costs of personal computing in a complex organization: a comparative study
Authors: Sonia Nayle, Walt Scacchi
Venue: ACM SIGOIS Bulletin (1986)

The widespread adoption of personal computers (PCs) may be attributable to their apparent low purchase and operational costs. However, significant procedural costs arise in fitting a PC application into a work setting. Our investigation of the adoption and use of PCs in several departments of a complex organization reveals a large number of unanticipated costs. These indirect, deferred, and governance costs are chiefly borne by users not responsible for acquiring PCs. These costs represent additional demands for users' time, skill, expertise, and attention as well as money. We find that the distribution of deferred costs determines the viability of PC systems. We also find that the integration of PCs can alter the way people do their jobs. These changes in turn give rise to additional social and political costs within the organization. Subsequently, we find that the true costs of personal computing are typically underestimated and unaccounted.
Enhancing availability in distributed real-time databases
Authors: Kwei-Jay Lin, Ming-Ju Lin
Venue: ACM SIGMOD Record (1988)

One of the issues in distributed databases is to maintain the data consistency when a database is replicated for higher availability. In a real-time database system, availability may be more important than consistency since a result must be produced before a deadline. We propose techniques to increase the availability in a partitioned real-time database. We also suggest that a transaction may execute even when the most up-to-date information is not available or when a serializable execution cannot be guaranteed. As long as data integrity is maintained, serializable execution may not be necessary.
Mapping data flow programs on a VLSI array of processors
Authors: B. Mendelson, G. M. Silberman
Venue: Proceedings of the 14th annual international symposium on Computer architecture (1987)

With the advent of VLSI, relatively large processing arrays may be realized in a single VLSI chip. Such regularly structured arrays take considerably less time to design and test, and fault-tolerance can easily be introduced into them. However, only a few computational algorithms which can effectively use such regular arrays have been developed so far. We present an approach to mapping arbitrary algorithms, expressed as programs in a data flow language, onto a regular array of data-driven processors implemented by a number of VLSI chips. Each chip contains a number of processors, interconnected by a set of regular paths, and connected to processors in other similar chips to form a large array. This array is thus tailored to perform a specific computational task, as an attached processor in a larger system. The data flow program is first translated into a graph representation, the data flow graph, which is then mapped onto a finite but (theoretically) unbounded array of identical processors. Each node in the graph represents an operation which can be performed by an individual processor in the array. Therefore, the mapping operation consists of assigning nodes in the graph to processors in the array, and defining the connections between the processors according to the arcs in the graph. The last step consists of partitioning the unbounded array into a number of segments, to account for the number of processors which fit in a single VLSI chip.
Effective computer education
Authors: David Sachs
Venue: Proceedings of the 15th annual ACM SIGUCCS conference on User Services (1987)

The design of an effective program to provide PC education is an exciting, challenging, complicated, rewarding activity. Such a program offers professional growth and development opportunities to university faculty, new corporate relationships for both the professors and the university, and the opportune moment for exciting explorations into the areas of curriculum development, evaluation methodology, and teaching styles. The design of an effective computer education program can be an important addition to a university's overall educational mandate. Key issues for any successful computer education include curriculum development, instructional design, course development, delivery of instruction, evaluation, and overall project management. This paper provides some guidelines for those who desire to design successful PC computer education. Under the author's direction, over 1,000 days of education have been provided to approximately 7,500 individuals during the past three years. The impact of such a program on the lives of the professors involved and the corporate clients receiving the education, has been enormous.