ppxscal/embedding_network huggingface dataset:
On Episodic Queues
Authors: Qi-Ming He, Marcel F. Neuts
Venue: SIAM Journal on Matrix Analysis and Applications (1997)

For a queueing system with a low traffic intensity, the expected number of customers in the queue is small. However, with a bursty input process, long queues may build up in a short time. In this paper, we study light traffic queueing systems with bursty input processes. We study the distributions of queue lengths, waiting times, busy and active periods, and their corresponding expansions when the traffic intensity is small. Special attention goes to some conditional distributions of queue lengths, waiting times, and system-active periods. The expansions given in this paper provide a potential asymptotic approach to the computation of various descriptors of queueing systems. The coefficients of those expansions reflect some important features of episodic queues. We also report numerical results which give a graphic view of our approximations and of the effect of the burstiness of the input and service processes on the queues.
The APL 90 project: new directions in APL interpreters technology
Authors: Jean-Jacques Girardot
Venue: Proceedings of the international conference on APL: APL and the future (1986)

This paper presents some aspects of a new implementation of APL, the APL 90 system. This implementation includes concepts inherited from LISP, such as the notion of property lists, or the ability to manipulate simply the internal representation of user defined functions or operators. These two features allow a great flexibility both in describing the system and using it. The work presented here is being implemented under UNIX on a SM 90 computer.
Specifying representations of machine instructions
Authors: Norman Ramsey, Mary F. Fernández
Venue: ACM Transactions on Programming Languages and Systems (TOPLAS) (1997)

We present SLED, a specification language for Encoding and Decoding, which describes, abstract, binary, and assembly-language representations of machine instructions. Guided by a SLED specification, the New Jersey Machine-Code Toolkit generates bit-manipulating code for use in applications that process machine code. Programmers can write such applications at an assembly language level of abstraction, and the toolkit enables the applications to recognize and emit the binary representations used by the hardware. SLED is suitable for describing both CISC and RISC machines; we have specified representations of MIPS R3000, SPARC, Alpha, and Intel Pentium instructions, and toolkit users have written specifications for the Power PC and Motorola 68000. The article includes representative excerpts from our SPARC and Pentium specifications. SLED uses four elements; fields and tokens describe parts of instructions; patterns describe binary representations of instructions or group of instructions; and constructors map between the abstract and binary levels. By combining the elements in different ways, SLED supports machine-independent implementations of machine-level concepts like conditional assembly, span-dependent instructions, relocatable addresses, object code, sections, and relocation. SLED specifications can be checked automatically for consistency with existing assemblers. The implementation of the toolkit is largely determined by our representations of patterns and constructors. We use a normal form that facilitates construction of encoders and decoders. The article describes the normal form and its use. The toolkit has been used to help build several applications. We have built a retargetable debugger and a retargetable, optimizing linker. Colleagues have built a dynamic code generator, a decompiler, and an execution-time analyzer. The toolkit generates efficient code; for example, the linker emits binary up to 15% faster than it emits assembly language, making it 1.7-2 times faster to produce an a.out directly than by using the assembler.
An augmented induction for HND computer studies students through an early integrated, inter-disciplinary assignment
Authors: C. Rosen, D. Simper, J. I. Bostock
Venue: ACM SIGCSE Bulletin (1998)

Poor progression rates on the first year of the Higher National Diploma (HND) Computer Studies at the University of Derby have been a significant issue for the department for several years. Problems were attributed to the modular nature of the course and a lack of social skills on the part of the students. The course was modified by introducing a three week programme at the beginning of the course which integrated the Systems Analysis, Introductory Programming and Fundamentals modules. The approach was designed to improve progression rates by breaking down barriers both between students, and between course modules. It also aimed to facilitate the transition from further to higher education by providing a more structured induction and a more closely managed initial experience for the students.
Breakpoint Detection Using Covariance Propagation
Authors: Qiang Ji, Robert M. Haralick
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1998)

This paper presents a novel statistical approach for detecting breakpoints from chain encoded digital arcs. An arc point is declared as a breakpoint if the estimated orientations of the two fitted lines of the two arc segments immediately to the right and left of the arc point are significantly statistically different. The major contributions of this research include developing a method for analytically estimating the covariance matrix of the fitted line parameters and proposing a perturbation model to characterize the perturbation associated with each arc point.
Learning and Updating of Uncertainty in Dirichlet Models
Authors: Enrique Castillo, Ali S. Hadi, Cristina Solares
Venue: Machine Learning (1997)

In this paper we analyze the problem of learning and updating of uncertainty in Dirichlet models, where updating refers to determining the conditional distribution of a single variable when some evidence is known. We first obtain the most general family of prior-posterior distributions which is conjugate to a Dirichlet likelihood and we identify those hyperparameters that are influenced by data values. Next, we describe some methods to assess the prior hyperparameters and we give a numerical method to estimate the Dirichlet parameters in a Bayesian context, based on the posterior mode. We also give formulas for updating uncertainty by determining the conditional probabilities of single variables when the values of other variables are known. A time series approach is presented for dealing with the cases in which samples are not identically distributed, that is, the Dirichlet parameters change from sample to sample. This typically occurs when the population is observed at different times. Finally, two examples are given that illustrate the learning and updating processes and the time series approach.
Parallel simulation by time segmentation: methodology and applications
Authors: Mehdi Hoseyni-Nasab, Sigrún Andradóttir
Venue: Proceedings of the 28th conference on Winter simulation (1996)

In this paper we present a time parallel simulation approach and discuss conditions under which this approach is applicable. Our approach involves distributing the available processors among segments of the time horizon of the simulation. We show that under certain conditions, sample paths of the system generated by a common sequence of potential events will couple (i.e., become identical) with probability one. This property will be exploited to efficiently combine the information collected on different segments of the sample path and generate a complete valid sample path. We show that the expected coupling time of the system (i.e., the amount of time required for all the sample paths of the system to couple) is essential to the efficiency of the approach. We apply our parallel simulation approach to a class of Markovian queueing networks and investigate the efficiency of the method by providing bounds and estimates for the expected coupling times.
A Bist Scheme for Non-Volatile Memories
Authors: Piero Olivo, Marcello Dalpasso
Venue: Journal of Electronic Testing: Theory and Applications (1998)

A new BIST scheme for on-chip testing of non-volatile memories and based on signature analysis is presented. The signature of the whole memory, whose content can be changed selectively by the user, is dynamically self-learned by the memory and it is saved in a dedicated memory location. Either such a signature can be externally compared with the expected one in order to check for the programming operation, or it can be used for comparison purposes when data retention must be self-tested.
Developing critical skills in technical courses (seminar)
Authors: Janet Kourik
Venue: ACM SIGCSE Bulletin (1997)

To succeed in today's computer information systems (CIS) environment, CIS professionals need far more than traditional technical skills. Managers seek technical staff with the ability to communicate effectively and understand an organization's primary mission. Industry would like CIS professionals to have strong backgrounds in a broad variety of skills such as oral and written communication, team work, and an awareness of international issues. Current computer science and information system curricula often do not provide our students with the opportunity to learn these critical skills.By adding a variety of simple activities to existing technical courses we can provide students with valuable opportunities to develop these critical skills. A variety of teaching techniques can re-enforce skills in both arenas at the same time. Some assignments can assist students in understanding the technical material by requiring them to apply advanced critical thinking skills. Active learning can reach students with different learning styles and increase the understanding and retention of technical material. A mixture of activities also provides a variety of forms of assessment which may more accurately reflect students' understanding of the material. As a bonus, these skills will enable our students to continue to thrive in a field fraught with constant change.The seminar will expand on these themes and provide examples and practice developing assignments that can help prepare well-rounded students for success in computer information systems.
Improving the Accuracy of History-Based Branch Prediction
Authors: David R. Kaeli, Philip G. Emma
Venue: IEEE Transactions on Computers (1997)

In this paper, we present mechanisms that improve the accuracy and performance of history-based branch prediction. By studying the characteristics of the decision structures present in high-level languages, two mechanisms are proposed that reduce the number of wrong predictions made by a branch target buffer (BTB). Execution-driven modeling is used to evaluate the improvement in branch prediction accuracy, as well as the reduction in overall program execution.
Procedure based program compression
Authors: Darko Kirovski, Johnson Kin, William H. Mangione-Smith
Venue: Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture (1997)

Cost and power consumption are two of the most important design factors for many embedded systems, particularly consumer devices. Products such as personal digital assistants, pagers with integrated data services and smart phones have fixed performance requirements but unlimited appetites for reduced cost and increased battery life. Program compression is one technique that can be used to attack both of these problems. Compressed programs require less memory, thus reducing the cost of both direct materials and manufacturing. Furthermore, by relying on compressed memory, the total number of memory references is reduced. This reduction saves power by lowering the traffic on high-capacitance buses. This paper discusses a new approach to implementing transparent program compression that requires little or no hardware support. Procedures are compressed individually, and a directory structure is used to bind them together at run-time. Decompressed procedures are explicitly cached in ordinary RAM as complete units, thus resolving references within each procedure. This approach has been evaluated on a set of 25 embedded multimedia and communications applications, and results in an average memory reduction of 40% with a run-time performance overhead of 10%.
Partial Resolution in Branch Target Buffers
Authors: Barry Fagin
Venue: IEEE Transactions on Computers (1997)

Branch target buffers, or BTBs, are small caches for program branching information. Like data caches, addresses are divided into equivalence classes based on their low order bits. Unlike data caches, however, complete resolution of a single address from within an equivalence class is not required for correct execution. Substantial savings are therefore possible by employing partial resolution, using fewer tag bits than necessary to uniquely identify an address. We present the relationship between the number of tag bits in a branch target buffer and prediction accuracy, based on dynamic simulations of the SPECINT92 benchmark suite. For a 512 entry BTB, on average only two tag bits are necessary to obtain 99.9 percent of the accuracy obtainable with a full tag; no more than nine tag bits are required to obtain identical prediction accuracy. This suggests that microprocessors can achieve substantial area savings in their BTB tag stores by employing partial resolution.
Sparse Approximate-Inverse Preconditioners Using Norm-Minimization Techniques
Authors: Nicholas I. M. Gould, Jennifer A. Scott
Venue: SIAM Journal on Scientific Computing (1998)

We investigate the use of sparse approximate-inverse preconditioners for the iterative solution of unsymmetric linear systems of equations. We consider the approximations proposed by Cosgrove, Diaz, and Griewank [Internat. J. Comput. Math., 44 (1992), pp. 91--110] and Huckle and Grote [A New Approach to Parallel Preconditioning with Sparse Approximate Inverses, Tech. report SCCM-94-03, Stanford University, 1994] which are based on norm-minimization techniques. Such methods are of particular interest because of the considerable scope for parallelization. We propose a number of enhancements which may improve their performance. When run in a sequential environment, these methods can perform unfavorably when compared with other techniques. However, they can be successful when other methods fail and simulations indicate that they can be competitive when considered in a parallel environment.
Distributed Multi-Level Recovery in Main-Memory Databases
Authors: Rajeev Rastogi, Philip Bohannon, James Parker, Avi Silberschatz, S. Seshadri, S. Sudarshan
Venue: Distributed and Parallel Databases (1998)

In this paper we present recovery techniques for distributed main-memory databases, specifically for client-server and shared-disk architectures. We present a recovery scheme for client-server architectures which is based on shipping log records to the server, and two recovery schemes for shared-disk architectures&mdash;one based on page shipping, and the other based on broadcasting of the log of updates. The schemes offer different tradeoffs, based on factors such as update rates.Our techniques are extensions to a distributed-memory setting of a centralized recovery scheme for main-memory databases, which has been implemented in the Dal&igrave; main-memory database system. Our centralized as well as distributed-memory recovery schemes have several attractive features&mdash;they support an explicit multi-level recovery abstraction for high concurrency, reduce disk I/O by writing only redo log records to disk during normal processing, and use per-transaction redo and undo logs to reduce contention on the system log. Further, the techniques use a fuzzy checkpointing scheme that writes only dirty pages to disk, yet minimally interferes with normal processing&mdash;all but one of our recovery schemes do not require updaters to even acquire a latch before updating a page. Our log shipping/broadcasting schemes also support concurrent updates to the same page at different sites.
Benchmarking for deadline-driven computing
Authors: Nelson Weiderman, Patrick Donohoe, Ruth Shapiro
Venue: Proceedings of the conference on TRI-ADA '90 (1990)

Hartstone is a series of timing requirements for testing a system's ability to handle hard real-time applications. It is specified as a set of processes with well-defined workloads and timing constraints. The name Hartstone derives from HArd Real Time and the fact that the workloads are based on the well-known Whetstone benchmark. This paper describes the results obtained by running Version 1.0 of the Hartstone benchmark, an Ada implementation of one of the requirements, on a number of compiler/target processor combinations. The characteristics and expected behavior of the benchmark are described, actual results are presented and analyzed, and the lessons learned about the compilers and processors, and the benchmark itself, are discussed. Nothing in this paper should be taken as an endorsement of, or an indictment of, a particular product. Users of Ada technology are encouraged to experiment with the Hartstone benchmark relative to their own particular application requirements.
Fast incremental circuit analysis using extracted hierarchy
Authors: Derek L. Beatty, Randal E. Bryant
Venue: Proceedings of the 25th ACM/IEEE Design Automation Conference (1988)

We present an algorithm for extracting a two-level subnetwork hierarchy from flat netlists and its application to incremental circuit analysis in the COSMOS compiled switch-level simulator. Incremental operation is achieved by using the file system as a large hash table that retains information over many executions of the incremental analyzer. The hierarchy extraction algorithm computes a hash signature for each subnetwork by coloring vertices in a manner similar to wirelist-comparison programs, then identifies duplicates using standard hash-table techniques. Its application decreases the network preprocessing time for COSMOS by nearly an order of magnitude.
The Matrix Sign Function Method and the Computation of Invariant Subspaces
Authors: Ralph Byers, Chunyang He, Volker Mehrmann
Venue: SIAM Journal on Matrix Analysis and Applications (1997)

A perturbation analysis shows that if a numerically stable procedure is used to compute the matrix sign function, then it is competitive with conventional methods for computing invariant subspaces. Stability analysis of the Newton iteration improves an earlier result of Byers and confirms that ill-conditioned iterates may cause numerical instability. Numerical examples demonstrate the theoretical results.
A model of human aiming movements applied to Parkinson's disease
Authors: Roland E. Suri, Carlo Albani, Adolf H. Glattfelder
Venue: Technology and Health Care (1997)

Healthy control subjects and Parkinsonian patients with and without l-DOPA medication were tested in a motor paradigm. The subjects were instructed to aim with the forearm as fast and as accurately as possible to the illuminated target. A quantitative dynamic model for planning and execution of voluntary aiming movements is developed. The proposed 'motor model' reproduces Parkinsonian symptoms and the therapeutic effects of the drug. The proposed model implies that the basal ganglia store movement and limb specific parameters which are necessary for the control of voluntary aiming movements. The model is contrasted against analytic concepts of motor control. Analytic concepts assume that movements are planned in space coordinates and then transformed to neural activities corresponding to the muscle force. In contrast, the neuronal activities simulated in the proposed 'motor model' can not be described by the terms 'planned trajectory', 'muscle force' or similar terms but suggest a more abstract dynamic concept.
Cache behavior of network protocols
Authors: Erich Nahum, David Yates, Jim Kurose, Don Towsley
Venue: Proceedings of the 1997 ACM SIGMETRICS international conference on Measurement and modeling of computer systems (1997)

In this paper we present a performance study of memory reference behavior in network protocol processing, using an Internet-based protocol stack implemented in the x-kernel running in user space on a MIPS R4400-based Silicon Graphics machine. We use the protocols to drive a validated execution-driven architectural simulator of our machine. We characterize the behavior of network protocol processing, deriving statistics such as cache miss rates and percentage of time spent waiting for memory. We also determine how sensitive protocol processing is to the architectural environment, varying factors such as cache size and associativity, and predict performance on future machines.We show that network protocol cache behavior varies widely, with miss rates ranging from 0 to 28 percent, depending on the scenario. We find instruction cache behavior has the greatest effect on protocol latency under most cases, and that cold cache behavior is very different from warm cache behavior. We demonstrate the upper bounds on performance that can be expected by improving memory behavior, and the impact of features such as associativity and larger cache sizes. In particular, we find that TCP is more sensitive to cache behavior than UDP, gaining larger benefits from improved associativity and bigger caches. We predict that network protocols will scale well with CPU speeds in the future.
MILO: a microarchitecture and logic optimizer
Authors: Nels Vander Zanden, Daniel Gajski
Venue: Proceedings of the 25th ACM/IEEE Design Automation Conference (1988)

In this paper we discuss strengths and weaknesses of logic synthesis systems and present a system for microarchitecture and logic optimization. Our system uses a set of algorithms for synthesizing SSI/MSI cells from parameterized microarchitecture components. In addition, it uses rules for optimizing both at the microarchitecture and logic level. The system increases designer productivity and requires less design knowledge and experience from circuit engineers.
Complexity Analysis of a Parallel Lattice Basis Reduction Algorithm
Authors: C. Heckler, L. Thiele
Venue: SIAM Journal on Computing (1998)

Lattice basis reduction is an important problem in geometry of numbers with applications in combinatorial optimization, computer algebra, and cryptography. The well-known sequential LLL algorithm finds a short vector in O(n4 log B) arithmetic operations on integers having binary length O(n log B), where n denotes the dimension of the lattice and B denotes the maximum L2 norm of the initial basis vectors. In this paper a new analysis of the parallel algorithm of Roch and Villard is presented. It is shown that on an n x n mesh it needs O(n2 log B) arithmetic operations on integers having binary length O(n log B). This improves the previous analysis and shows that an asymptotical speedup of n2 is possible using n2 processors.
Generalizations of Ky Fan's Dominance Theorem
Authors: Chi-Kwong Li, Roy Mathias
Venue: SIAM Journal on Matrix Analysis and Applications (1998)

For $x \in \hbox{{\bbb R}}^n$ and $1 \le k \le n$, define \[ \|x\|_k \equiv \sum_{i=1}^k |x_{[i]}| , \] where $x_{[1]}, \dots, x_{[n]}$ are the entries of $x$ such that $|x_{[1]}| \ge \cdots \ge |x_{[n]}|$. It is shown that \[ \|x\|^2 \leq \|y\| \|z\| \] for all permutation invariant absolute norms on $\hbox{{\bbb R}}^n$ if and only if \[ \|x\|_k^2 \le \|y\|_k\|z\|_k, \qquad k = 1, 2, \ldots, n. \] This generalizes Ky Fan's dominance theorem and implies similar results for unitarily invariant norms on the space of matrices that have application in some recent work of Bhatia, Kittaneh, and Li [ Linear and Multilinear Algebra, to appear] on inequalities for commutators. Further generalizations of the above result are also obtained.
Modeling with Extend
Authors: David Krahl
Venue: Proceedings of the 28th conference on Winter simulation (1996)

This document presents an overview of the Extend modeling environment, emphasizing Extend's ability to model a wide range of systems. Extend is a general purpose graphically oriented discrete event and continuous simulation application with an integrated authoring environment and development system.