ppxscal/embedding_network huggingface dataset:
Perceptrons with Polynomial Post-Processing
Authors: L. Sanzogni, R. F. Bonner, R. Chan
Venue: Proceedings of the 8th International Conference on Tools with Artificial Intelligence (1996)

We introduce tensor product neural networks, composed of a layer of unvariute neurons followed by a net of polynomial post-processing. We look at the general approximation problem by these networks observing in particular their relationship to the Stone-Weierstruss theorem f o r uniform function algebras. The implementation of the post-processing us a two-layer network with logarithmic and exponential neurons leads to potentially important ' generalized' product networks, which however require a complex approximation theory of Miintz-Szasz-Ehrenpreis type. A buck-propagation algorithm for product networks is presented and used in three computational experiments. I n particular, approximation by a sigmoid product network is compared to that of a single layer radial basis network, and a multiple layer sigmoid network. Keywords neural network approximation, polynomial post-processing, product unit
Sparse Partial Pivoting in Time Proportional to Arithmetic Operations
Authors: John R. Gilbert, Timothy Peierls
Venue:  (1986)

Existing sparse partial pivoting algorithms can spend asymptomatically more time manipulating data structures than doing arithmetic, although they are tuned to be efficient on many large problems. We present an algorithm to factor sparse matrices by Gaussian elimination with partial privoting in time proportional to the number of arithmetic operations. Implementing this algorithm requires only simple data structures and gives a code that is competitive with, and often faster than, existing sparse codes. The key idea is a new triangular solver that uses depth-first search and topological ordering to take advantage of sparsity in the right-hand side.
Interactive self-replicating, self-incrementing and self-decrementing loops
Authors: André Stauffer, Moshe Sipper
Venue: Proceedings of the eighth international conference on Artificial life (2002)

Self-replicating loops presented to date are usually worlds unto themselves, inaccessible to observer once the replication process is launched. In this paper we present a self-replicating loop which allows for user interaction. Specifically, the user can control the loop's replication as well as the size of the replica. After presenting the design of this novel loop, we delineate its physical implementation in our electronic wall for bio-inspired applications, the Bio Wall.
Software Measurement Process - Standardization and Application
Authors: John McGarry, David N. Card, Jerome Peasant
Venue: Proceedings of the 4th IEEE International Symposium and Forum on Software Engineering Standards (1999)

This 1/2 day tutorial will provide an overview of the requirements for implementing a viable software measurement process to support an organization's technical and business objectives. The tutorial defines those measurement activities and tasks which have proven to be successful in actual application with respect to both process and product measurement.Software measurement experience is directly related to the design of ISO/IEC 15939, a new international standard under development defining the requirements for implementing a software measurement process. The architecture and content of ISO/IEC 15939 will be discussed, as well as its interfaces to other software engineering standards such as ISO/IEC 12207, 15504, 9126 and 14143.Practical approaches for the projected implementation of ISO/IEC 15939 will also be presented. The first example will be based upon Ericsson's Measurement Process Model (ESMF), currently being implemented within the organization to support software and systems engineering efforts. Another example is "Practical Software Measurement" (PSM), a U.S. DoD sponsored initiative designed to insert software measurement into day-to-day practice. Copies of the PSM guidebook and tool will be provided to each participant. The tutorial will relate both Ericsson's experience and the PSM guidance to the projected requirements of ISO/IEC 15939.
Completing partial combinatory algebras with unique head-normal forms
Authors: Inge Bethke, Jan W Klop, Roel Vrijer
Venue:  (1995)

In this note, we prove that having unique head-normal forms is a sufficient condition on partial combinatory algebras to be completable. As application, we show that the pca of strongly normalizing CL-terms as well as the pca of natural numbers with partial recursive function application can be extended to total combinatory algebras.
Automatic extraction and description of human gait models for recognition purposes
Authors: David Cunado, Mark S. Nixon, John N. Carter
Venue: Computer Vision and Image Understanding (2003)

Using gait as a biometric is of emerging interest. We describe a new model-based moving feature extraction analysis is presented that automatically extracts and describes human gait for recognition. The gait signature is extracted directly from the evidence gathering process. This is possible by using a Fourier series to describe the motion of the upper leg and apply temporal evidence gathering techniques to extract the moving model from a sequence of images. Simulation results highlight potential performance benefits in the presence of noise. Classification uses the k-nearest neighbour rule applied to the Fourier components of the motion of the upper leg. Experimental analysis demonstrates that an improved classification rate is given by the phase-weighted Fourier magnitude information over the use of the magnitude information alone. The improved classification capability of the phase-weighted magnitude information is verified using statistical analysis of the separation of clusters in the feature space. Furthermore, the technique is shown to be able to handle high levels of occlusion, which is of especial importance in gait as the human body is self-occluding. As such, a new technique has been developed to automatically extract and describe a moving articulated shape, the human leg, and shown its potential in gait as a biometric.
Software System Development with Unified Modeling Language
Authors: Igor B. Ushakov
Venue: Proceedings of the 4th IEEE International Symposium and Forum on Software Engineering Standards (1999)

This tutorial provides hands-on experience in applying the UML modeling approach to real-world complex software system based on examples in the area of train automation and telecommunication. The goal of the tutorial is to: Present basic knowledge necessary for successful application of UML in the context of OO iterative and incremental software development processes. Demonstrate how UML elements are used and combined with other techniques and tools, such as, requirements management and traceability in DOORS, design patterns and Standard Template Library. NOTE: Rational Rose 4.0 for C++ is used for specifying and documenting the system under development.The tutorial gives quick reference on Rose basic features, how to integrate it with CM tools, customize the GUI and add user defined commands to a set of existing tools. Rose's code generation properties and scripting facility are explained to produce robust and reusable source code. Detailed instructions on how to map the UML object model to C++, Java or SQL are provided.The tutorial also traces the evolution of UML from its origins in the Booch, Rumbaugh and Jacobson methods through UML 1.1; and provides an easy transition for analysts and designers who are familiar with the original techniques into the new notation. This tutorial is aimed at a half-day presentation. Our experience provides interested audience with many insights into: OO design with UML notation. Numerous tips on how to implement the design with the Rose modeling tool. How to generate C++ or Java source code. How to model data for databases with SQL mapping. How to apply iterative and incremental software development processes to software system construction.
I/O Phase Characterization of TPC-H Query Operations
Authors: Meenakshi A. Kandaswamy, Robert L. Knighten
Venue: Proceedings of the 4th International Computer Performance and Dependability Symposium (2000)

With the introduction of newer faster processors, speedier interconnects and sophisticated I/O system designs, the processing capabilities of servers built in current market place are ever increasing, but so are the myriad commercial applications that they are used for. Unfortunately, detailed studies capturing the demands of commercial applications/workloads have been very few.In this paper we characterize the I/O activity of the 22 I/O-intensive database queries of the commercial decision support system (DSS) benchmark, namely, TPC-H and a smaller set of queries called "DSS-lite" that perform individual database operations. TPC-H query behavior varies throughout its execution but we identify "phases" in a query during which the performance is close forming a steady state. We use the DSS-lite results and query plan information to decipher the various phases of the TPC-H queries and characterize their I/O requirements, which can aid in forecasting or planning a DSS system's I/O capacity.
An RPC Mechanism for Transportable Agents
Authors: Saurab Nog, Sumit Chawla, David Kotz
Venue:  (1996)

Transportable agents are autonomous programs that migrate from machine to machine, performing complex processing at each step to satisfy client requests. As part of their duties agents often need to communicate with other agents. We propose to use remote procedure call (RPC) along with a flexible interface definition language (IDL), to add structure to inter-agent communication. The real power of our Agent RPC comes from a client-server binding mechanism based on flexible IDL matching and from support for multiple simultaneous bindings. Our agents are programmed in Agent Tcl; we describe how the Tcl implementation made RPC particularly easy to implement. Finally, although our RPC is designed for Agent Tcl programs, the concepts would also work for standard Tcl programs.
Strongly Universal Interval Hypergraphs
Authors: L A Rosenberg
Venue:  (1986)

An $n$-vertex {\em interval hypergraph} (I-hypergraph, for short) $H$ comprises the set $V _ n~=~\{ 1,2, \cdot \cdot \cdot , n \}$ of vertices and a multiset $E(H)$ of hyperedges, each hyperedge a subset of $V _ n$ of the form $\{k, k+1, \cdot \cdot \cdot , k+r\}$ $(k \geq 1, r \leq n-k)$. The {\em size} $SIZE(H)$ of the I-hypergraph $H$ is the sum of the cardinalities of its hyperedges. An {\em embedding} of a graph $G=(V,E)$ in an $n$-vertex I-hypergraph $H$ comprises an injection $\mu _ {_ V} : V \rightarrow V _ n$, plus an injection $\mu _ e :E \rightarrow E(H)$ satisfying: for all $(u,v) \in E$, $\{ \mu _ {_ V} (u), \mu _ {_ V} (v)\} \subseteq \mu _ e (u,v)$. The $n$-vertex I-hypergraph $H$ is {\em strongly universal} for the finite family of graphs $\Gamma$ if: given any $W \subseteq V _ n$ and any graph $G=(V,E) \in \Gamma$ with $|V| \leq |W|$, there is an embedding of $G$ in $H$ such that $\mu _ {_ V} (V) \subseteq W$. In this paper, we present an algorithm for constructing a small strongly universal I-hypergraph for a given finite family of graphs $\Gamma$: Say that $\Gamma$ has an $\alpha$-separator $(1/2 \leq \alpha > 1)$ of size $S(n)$: each $m$-vertex graph in $\Gamma$ can be partitioned, by removing at most $S(m)$ edges, into two subgraphs, each in $\Gamma$ and each having at most $\alpha m$ vertices. Then our algorithm produces a strongly universal I-hypergraph $H( \Gamma )$ for $\Gamma$, of size \[ SIZE(H( \Gamma ))~=~m \cdot \left ( \sum _ {k=1} ^ {log~ m} ~ \sum _ {1=0} ^ {\lambda (k)}~ S( \alpha ^ i 2 ^ k ) \right ) , \] where $m$ is the number of vertices in the largest graph in $\Gamma$ and $\lambda (k)= log _ {1 / \alpha} k$. For many families $\Gamma$, including binary trees and any family for which $S(n)$ is algebraic in $n$, the I-hypergraphs $H( \Gamma )$ are optimal in $SIZE$ (to within a constant factor). This study is inspired by one approach to the design of fault-tolerant arrays of processors.
Multi-attribute lexicon generation by hyperlinked embedded access structure
Authors: Wen-Jann Yang, R. Sridhar, P. Palumbo
Venue: Proceedings of the 1997 International Symposium on Database Engineering & Applications (1997)

Providing a lexicon for all possible postal addresses can support decision making for handwritten address interpretation. The possibility of uncertainty can be reduced by choosing the highest confident record in the provided lexicon as the target postal address. For a large database with multi-attribute records, traditional access methods are not efficient enough to generate the lexicon. This paper proposes a hyperlinked embedded access structure (HEAS) which combines the features of inverted file structure and doubly-chained tree structure with unique data compression schemes. The raw United State Postal Service (USPS) database is organized according to the proposed access structure, and the organized database serves as a knowledge base for interpreting handwritten addresses. The organization cost, storage requirement, and query cost are analyzed and compared to conventional inverted file and doubly-chained tree structures.
Efficient processing of spatial selection and join operations using SB/sup +/-tree
Authors: A. Ibrahim, F. Fotouhi, A. Al-Badameh
Venue: Proceedings of the 1997 International Symposium on Database Engineering & Applications (1997)

Introduces a spatial access method, the SB/sup +/-tree, that is based on the B/sup +/-tree structure. For each axis of the space, a set of indexing points is generated; an indexing point is created whenever a new minimum bounding rectilinear rectangle (MBR) begins or ends. These indexing points are then used to create an SB/sup +/-tree. We present algorithms using an SB/sup +/-tree for performing two spatial selection operators (window intersection and point containment), and one spatial join operator (region containment). Analytically, we show the improved performance of the window intersection operation using an SB/sup +/-tree over using existing paged-secondary memory spatial access structures such as the R/sup */-tree.
Converting a Swap-Based System to do Paging in an Architecture Lacking Page-Referenced Bits
Authors: Ozalp Babaoglu, William Joy
Venue:  (1981)

This paper discusses the modifications made to the UNIX operating system for the VAX-11/780 to convert it from a swap-based segmented system to a paging-based virtual memory system. Of particular interest is that the host machine architecture does not include page-referenced bits. We discuss considerations in the design of page-replacement and load-control policies for such an architecture, and outline current work in modeling the policies employed by the system. We describe our experience with the chosen algorithms based on benchmark-driven studies and production system use.
A Compact Layout Technique for Reducing Switching Current Effects in High Speed Circuits
Authors: And A. Nunez
Venue: Proceedings of the 2nd International Symposium on Quality Electronic Design (2001)

A full-custom layout style and its cell model is presented. Its power supply and ground rails distribution is not only of very low self-inductance, but it is also independent of cell dimensions. Cell layouts following the proposed model reduces greatly switching current effects at high frequency. The underlying cell architecture is regular and suitable to design automation without sacrificing any advantages of the full-custom design. Layout channel density of a subset of MCNC'91 two-level circuit benchmarks have been obtained. Comparisons demonstrate that the layout of combinational circuits in the high speed cell model are compact and minimize the routing area. A cell compiler has be used as a cell library builder and it is embedded in a random logic macrocell and an iterative logic array generator. It is shown that the cell and macrocell compiler generates complex and compact layouts. The technique is demonstrated for GaAs processes up to 4GHz, but it can be directly applied to deep submicron CMOS processes as well. The ACM Portal is published by the Association for Computing Machinery. Copyright © 2010 ACM, Inc. Terms of Usage Privacy Policy Code of Ethics Contact Us Useful downloads: Adobe Acrobat QuickTime Windows Media Player Real Player
A "flight data recorder" for enabling full-system multiprocessor deterministic replay
Authors: Min Xu, Rastislav Bodik, Mark D. Hill
Venue: Proceedings of the 30th annual international symposium on Computer architecture (2003)

Debuggers have been proven indispensable in improving software reliability. Unfortunately, on most real-life software, debuggers fail to deliver their most essential feature --- a faithful replay of the execution. The reason is non-determinism caused by multithreading and non-repeatable inputs. A common solution to faithful replay has been to record the non-deterministic execution. Existing recorders, however, either work only for datarace-free programs or have prohibitive overhead.As a step towards powerful debugging, we develop a practical low-overhead hardware recorder for cachecoherent multiprocessors, called Flight Data Recorder (FDR). Like an aircraft flight data recorder, FDR continuously records the execution, even on deployed systems, logging the execution for post-mortem analysis.FDR is practical because it piggybacks on the cache coherence hardware and logs nearly the minimal threadordering information necessary to faithfully replay the multiprocessor execution. Our studies, based on simulating a four-processor server with commercial workloads, show that when allocated less than 7% of system's physical memory, our FDR design can capture the last one second of the execution at modest (less than 2%) slowdown.
Novel algorithms for multicast communication in self-routing MIN-based ATM switches
Authors: Jaehyung Park, Hyunsoo Yoon, Jung Wan Cho
Venue: Proceedings of the 1996 International Conference on Network Protocols (ICNP '96) (1996)

We discuss the multicast communication in the self-routing multistage interconnection network (MIN) for constructing the internal architecture of asynchronous transfer mode (ATM) switches. Many applications of ATM switches require multicast communications in addition to conventional point-to-point communications. This paper presents a novel approach to supporting multicast communication, on the basis of the recursive scheme that recycles a multicast packet one or more times through the network to reach at desired destinations. We also propose cost-effective multicast algorithms providing deadlock-freedom in MIN-based ATM switches. The proposed algorithms require a small and fixed number of recycling passes and a reasonable number of links used. The proposed algorithms can be easily applicable to buffered MIN-based ATM switches.
CorrectandAlmostCompleteDiagnosisofProcessorGrids
Authors: Stefano Chessa, Piero Maestrini
Venue:  (1999)

GivenasetNofninterconnectedprocessors,someofwhichmaybe faulty,theSystem-LevelDiagnosisaimsatidentifyingthefaultyprocessorsby analyzingtheoutcomesoftheavailableinterprocessortests.Executionofa testrequiresthattheinvolvedunitsbeconnected.Regularorquasiregular interconnectionschemesdeservespecialattention,duetotheirwidespreaduse inparallelarchitectures.Themostcommonapproachtothediagnosisofregular systemshasbeenprobabilistic,thusleadingtoresultswhosecorrectnesscan onlybeevaluatedprobabilistically.Inthispaper,anewdeterministic algorithmisintroduced,whichidentifiesasetFoffaultyprocessorsanda setKofnon-faultyprocessors,withF+K=T,whichthediagnosisalgorithmitselfassertsfor everyspecificdiagnosisexperiment,togetherwiththediagnosis.Resultsof extensivesimulationstudiesarereported,fromwhichitisseenthatthe diagnosiscanbeexpectedtobecompleteoralmostcompletewheneverthenumber offaultsisnomorethanT,andthatthedegreeofcompletenessremainsquite satisfactoryaslongasthenumberoffaultsisbelown/3.Itisalsoseenthat thediagnosisisalmostcertainlycorrectaslongasthenumberoffaultsis belown/2.
A study of storage partitioning using a mathematical model of locality
Authors: E. G. Coffman, Thomas A. Ryan
Venue: ACM SIGOPS Operating Systems Review (1972)

Both fixed and dynamic storage partitioning procedures are examined for use in multiprogramming systems. The storage requirement of programs is modeled as a stationary Gaussian process. Experiments justifying this model are described. By means of this model dynamic storage partitioning is shown to provide substantial increases in storage utilization and operating efficiency over fixed partitioning.
High-level brokerage services for the e-learning domain
Authors: L. Anido, J. Rodríguez, M. Caeiro, J. M. Santos
Venue: Computer Standards Interfaces (2003)

A sizeable percentage of OMG activity is focused on standardizing services and facilities in specific vertical markets through Domain Task Forces. This paper presents a contribution to this process in the e-learning domain where an important standardization effort is currently being carried out. We describe the different stages involved in the definition of software services for specific application domains using an MDA-oriented methodology proposed by the authors. The outcome of the application of this methodology is four specifications for distributed and interoperable high-level brokerage environments where learning objects can be publicized, located and retrieved.
Processor Controlled Off-Processor I/O
Authors: Marcel Rosu
Venue:  (1995)

The performance of modern RISC processors on operating system code is well below application code performance. The kernel code implementing communication services across the network is not an exception. Modern networking technologies are characterized by a small packet size, which further increases the communication overhead. We took the approach of removing the kernel layer from the cross-machine communication path while still providing protection. The presence of a programmable communication processor on the network adapter made this experiment possible. The firmware running on the communication processor implements a Virtual Communication Machine (VCM); applications communicate with the VCM through shared memory without having to switch to kernel mode. Data is transferred directly between application buffers and the network without any intermediate buffering in the user or kernel spaces. The VCM architecture makes this possible; in particular, the VCM can be programmed to access any location in the address space of an application. The main processor controls the communication but it is not directly involved with it; as a consequence, the overhead on the main processor is very low. The design not only provides very low latencies, but also minimizes the effect of communication on the main processor data caches. We implemented the datagram subset of the Berkeley sockets interface on top of the VCM interface and integrated it with a user-level thread package. Multicast capabilities were added to the interface. Performance measured at both the VCM and socket layers is presented.