ppxscal/embedding_network huggingface dataset:
Visualizing the Performance of Parallel Programs
Authors: Michael T. Heath, Jennifer A. Etheridge
Venue: IEEE Software (1991)

ParaGraph, a software tool that provides a detailed, dynamic, graphical animation of the behavior of message-passing parallel programs and graphical summaries of their performance, is presented. ParaGraph animates trace information from actual runs to depict behavior and obtain the performance summaries. It provides twenty-five perspectives on the same data, lending insight that might otherwise be missed. ParaGraph's features are described, its use is explained, its software design is briefly discussed, and its displays are examined in some detail. Future work on ParaGraph is indicated.
The Minimum Number of Errors in the N-Parity and its Solution with an Incremental Neural Network
Authors: J. Manuel Torres-Moreno, Julio C. Aguilar, Mirta B. Gordon
Venue: Neural Processing Letters (2002)

The N-dimensional parity problem is frequently a difficult classification task for Neural Networks. We found an expression for the minimum number of errors &nu;f as function of N for this problem, performed by a perceptron. We verified this quantity experimentally for N&equals;1,&hellip;,15 using an optimal train perceptron. With a constructive approach we solved the full N-dimensional parity problem using a minimal feedforward neural network with a single hidden layer of h&equals;N units.
Dynamic 3-D Scene Analysis Through Synthesis Feedback Control
Authors: R. Koch
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1993)

The analysis of 3-D scenes consisting of nonrigid moving objects using 2-D image sequences is discussed. A parametric description of dynamic objects is extracted, and the time-variant scene parameters are estimated throughout the sequence by employing an analysis-by-synthesis approach. Images are synthesized from the parametric scene description and compared with the original images input to the camera. Frame differences between the synthesized and original images are evaluated to obtain an estimated scene parameter update. The analysis method is applied to videophone scenes in the form of a data compression algorithm, whereby the scene parameters are transmitted and the output sequence is synthesized at the receiver.
StrongARMing Portable Communications
Authors: Tim Litch, Jeff Slaton
Venue: IEEE Micro (1998)

The StrongARM SA-1100 is an integrated microprocessor designed for use in portable, battery powered applications. Intended for the new breed of handheld devices, such as wallet PCs, smartphones and subnotebooks, the SA-1100 integrates a variety of peripheral functions commonly relegated to ASIC devices onto a single chip. In a die size of 75 mm2, the SA-1100 incorporates the SA-1 core, a 16k Icache, an 8k dcache, a memory controller, PCMCIA support, timers (including a real-time clock), 28 general-purpose I/Os, an interrupt controller, a DMA controller, and clocking and power management controller along with an LCD contoller and eight serial controllers. The SA-1100 delivers an estimated 230 Dhrystone MIPs at 200 MHz and consumes 250 mW in typical operation. During its low-power sleep mode, it draws a maximum of 50 uA.
A Terabit Multiservice Switch
Authors: Kenneth Y. Yun
Venue: IEEE Micro (2001)

The Cyclone switch architecture enables a scalable switching platform from multiple Gbits to multiple Tbits per second in five custom 0.18-micron CMOS ICs. A wire-speed scheduling capability supports eight quality of service classes and a million flows.
Compatible cell connections for multifamily dynamic logic gates
Authors: Rolando Ramírez Ortiz, John P. Knight
Venue: IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2002)

Dynamic Logic is an alternative way of making logic circuit cells and numerous techniques have been developed to take advantage of its unique characteristics. Particularly, techniques such as the true-single-phase-clock (TSPC) have been used very successfully for fast and low-power applications. However one cannot synthesize dynamic logic gates with the same ease as static gates. One reason is there are no simple rules to connect the many circuit types of dynamic gates to static gates. This paper addresses the problem of finding connection rules for a given set of gate types. The fundamental cell circuit types for dynamic logic gates are analyzed first together with static logic gates. A common set of principles of operation and connections are then identified and later applied to discover which are the feasible connections between cell circuit types identified.
Connecting Tools Using Message Passing in the Field Environment
Authors: Steven P. Reiss
Venue: IEEE Software (1990)

An overview is given of the Field environment, which was developed to show that highly integrated, interactive environments like those on PCs can be implemented on workstations and can be used for classical-language and large-scale programming. Field connects tools with selective broadcasting, which follows the Unix philosophy of letting independent tools cooperate through simple conventions, demonstrating that this simple approach is feasible and desirable. Field achieves its goals by providing a consistent graphical front end and a simple integration framework that lets existing and new Unix tools cooperate. The front end is based on a tool set called the Brown workstation environment. The framework combines selective broadcasting with an annotation editor that provides consistent access to the source code in multiple contexts and with a set of specialized interactive analysis tools. Field's integration framework and message facility are described.
Digital Video Coding Techniques for US High-Definition TV
Authors: Eric Petajan
Venue: IEEE Micro (1992)

Motion-compensated transform coding is proposed for video compression in systems for the US terrestrial broadcast of high-definition television (HDTV). A noncritical overview of the video coding techniques used in the four proposed digital HDTV systems, that provides basic descriptions of the discrete cosine transform, motion estimation and compensation, adaptive quantization, variable-length coding, and compressed video data formatting is presented.
3-D Translational Motion and Structure from Binocular Image Flows
Authors: L. Li, J. H. Duncan
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1993)

Image flow fields from parallel stereo cameras are analyzed to determine the relative 3-D translational motion of the camera platform with respect to objects in view and to establish stereo correspondence of features in the left and right images. A two-step procedure is suggested. In the first step, translational motion parameters are determined from linear equations the coefficients of which consist of the sums of measured quantities in the two images. Separate equations are developed for cases when measurements of either the full optical flow or the normal flow are available. This computation does not require feature-to-feature correspondence. In addition, no assumption is made about the surfaces being viewed. In the second step of the calculation, with the knowledge of the estimated translational motion parameters, the binocular flow information is used to find features in one image that correspond to given features in the other image. Experimental results with synthetic and laboratory images indicate that the method provides accurate results even in the presence of noise.
Rule Acquiring Expert Controllers
Authors: C. G. Looney
Venue: IEEE Transactions on Knowledge and Data Engineering (1991)

A paradigm is developed for a controller to learn to control an environment by use of a benefit measure to judge the control. Rules are acquired that fire in a stimulus-response fashion for control, and rules continue to be acquired to adapt to an evolving environment. The model includes both knowledge acquisition and skill refinement through bottom-up (data driven) learning of the top-down control strategy. It is more flexible than hardware learning systems such as ADELINE or MADELINE. The controller model self-organizes by acquiring rules, and adapts by continuing to update its rules while controlling an external environment. It does this by judging the benefit of feedback due to the selected control rules and keeping counts in cells from which a rule function is generated.
The GenVoca Model of Software-System Generators
Authors: Don Batory, Vivek Singhal, Jeff Thomas, Sankar Dasari, Bart Geraci, Marty Sirkin
Venue: IEEE Software (1994)

An emerging breed of generators synthesize complex software systems from libraries of reusable components. These generators, called GenVoca generators, produce high-performance software and offer substantial increases in productivity. GenVoca is a blueprint for creating domain-specific software component technologies. Predator and Adage are based directly on GenVoca. Experimental evidence from the Predator project supports claims of performance and productivity with this model.
An active mail system
Authors: John Hogg, Stelios Gamvroulas
Venue: Proceedings of the 1984 ACM SIGMOD international conference on Management of data (1984)

Conventional electronic mail is passive text that is created, sent and read. Any further actions must be initiated by the recipient. By contrast, an "intelligent message" (imessage) is an active program that carries on a dialogue with the recipient. The imessage may subsequently route itself to other users as a result of the responses it receives, and it eventually returns these responses to the original sender.This paper describes a prototype intelligent mail system and discusses some of the problems involved in implementing such a system in a distributed environment.
Interactive metamorphosis and carving in a multi-volume scene
Authors: Maxim Kazakov, Alexander Pasko, Valery Adzhiev
Venue: Proceedings of the 1st international conference on Computer graphics and interactive techniques in Australasia and South East Asia (2003)

The paper presents an approach to modeling scenes composed of multiple volumes with a possibility of a fast navigation through such a scene as well as interactive editing of volumes in it. This work is oriented towards an artistic application that includes selection and editing of new shapes for further production in real material. The objects are edited in terms of interactive carving and metamorphosis operations. Initial shapes are represented as functionally defined 3D volume models with implicit surfaces. The metamorphosis generates a variety of shapes one of which can be selected by an artist. Once the artist is satisfied with the metamorphosis results, he/she can perform carving on its surface to fine tune an overall appearance. Interactive visualization is based on the isosurface polygonization with some optimizations for interactive object editing. The implementation is efficient enough to be able to maintain interactive rate with all operations even on an ordinary personal computer with an average graphic card.
A Model for Database Allocation Incorporating a Concurrency Control Mechanism
Authors: S. Ram, R. E. Marsten
Venue: IEEE Transactions on Knowledge and Data Engineering (1991)

The impact of incorporating a specific concurrency control mechanism (CCM) into the file allocation problem (FAP) is discussed. Depending on the specific CCM use, the communication flows in a network will vary. To allocate data optimally, one must identify the exact communication flows in the network. It is this aspect that has been ignored in past research on the FAP. A linear mixed-integer programming model formulated for the FAP is given. The model incorporates the WRITE LOCKS ALL-READ LOCKS ONE mechanism for concurrency control. A special algorithm based on the implicit representation of variable upper bounds is developed to solve the model. Detailed analysis for various configurations of a network is performed. Several potential applications for the model are identified.
Limits on Interconnection Network Performance
Authors: A. Agarwal
Venue: IEEE Transactions on Parallel and Distributed Systems (1991)

The latency of direct networks is modeled, taking into account both switch and wiredelays. A simple closed-form expression for contention in buffered, direct networks is derived and found to agree closely with simulations. The model includes the effects of packet size and communication locality. Network analysis under various constraints and under different workload parameters reveals that performance is highly sensitive to these constraints and workloads. A two-dimensional network is shown to have the lowest latency only when switch delays and network contention are ignored; three- or four-dimensional networks are favored otherwise. If communication locality exists, two-dimensional networks regain their advantage. Communication locality decreases both the base network latency and the network bandwidth requirements of applications. It is shown that a much larger fraction of the resulting performance improvement arises from the reduction in bandwidth requirements than from the decrease in latency.
A Collaborative Program to Retrain Lockheed Martin Aero Engineers
Authors: Jorge Díaz-Herrera, Mike Murphy, Dawn Ramsey
Venue: IEEE Software (2002)

This article is a report on an innovative retraining program designed to take a surplus of engineers from traditional areas at Lockheed Martin Aeronautics Company in Marietta, Georgia, and retrain them through a combination of coursework at Southern Polytechnic State University and a practicum back at the company into software engineers. The article addresses the planning and implementation phases as well as the results to date and recommendations for others considering such partnerships. The authors also present insights into the curriculum, its evolution, and issues regarding how such instruction can be made more effective.
Synthesizing Coordination Requirements for Heterogeneous Autonomous Agents
Authors: Munindar P. Singh
Venue: Autonomous Agents and Multi-Agent Systems (2000)

As agents move into ever more important applications, there is a natural growth in interest in techniques for synthesizing multiagent systems. We describe an approach for engineering the coordination requirements of a multiagent system based on an analysis of conversation instances extracted from usage scenarios. This approach exploits the notion of Dooley graphs that were recently introduced to the multiagent systems community from the linguistics and discourse analysis literature. We show how, with a few key modifications, Dooley graphs can be used to generate coordination requirements and constraints on the behavior models of the agents participating in a multiagent system.Our present approach is embodied in the context of our recent work on a distributed coordination service for heterogeneous, autonomous agents. This approach takes as input (a) agent skeletons, giving compact descriptions of the given agents in terms of their events that are significant for coordination, as well as (b) relationships among the events occurring in these skeletons. A natural question is how may the skeletons and relationships be produced in the first place. It turns out that a methodology that begins with Dooley graphs can readily yield the skeletons and relationships needed to achieve the desired coordination.Consequently, our approach combines the benefits of an intuitive methodology with a formal and distributed framework for developing multiagent systems from autonomous agents.
Availability of k-Coterie
Authors: H. Kakugawa, S. Fujita, M. Yamashita, T. Ae
Venue: IEEE Transactions on Computers (1993)

The distributed k-mutual-exclusion problem (k-mutex problem) is the problem of guaranteeing that at most k processes at a time can enter a critical section at a time in a distribution system. A method proposed for the solution of the distributed mutual exclusion problem (i.e., 1-mutex problem) by D. Barbara and H. Garcia-Molina (1987) is an extension of majority consensus and uses coteries. The goodness of coterie-based 1-mutex algorithm strongly depends on the availability of coterie, and it has been shown that majority coterie is optimal in this sense, provided that: the network topology is a complete graph, the links never fail, and p, the reliability of the process, is at least 1/2. The concept of a k-coterie, an extension of a coterie, is introduced for solving the k-mutex problem, and lower and upper bounds are derived on the reliability p for k-majority coterie, a natural extension of majority coterie, to be optimal, under conditions (1)-(3). For example, when k=3, p must be greater than 0.994 for k-majority coterie to be optimal.
A Testability Strategy for Microprocessor Architecture
Authors: F. Catthoor, J. van Sas, L. Inze, H. De Man
Venue: IEEE Design Test (1989)

The authors present a method for fully testing chips designed using synthesis and silicon compilation. The method is targeted for a multiprocessor architecture that implements low-speed to medium-speed signal-processing algorithms. By taking advantage of the specific properties of the architecture, the method allows a chip to be partitioned into several functional units. The authors use the C-test concept instead of the traditional automatic test-pattern generation to derive a compact set of test vectors. The fault model covers both the stuck-at class and part of the transistor stuck-open and stuck-closed cases. For large units with embedded memory, the authors adopt a self-test approach.
The Paradigm Compiler for Distributed-Memory Multicomputers
Authors: Prithviraj Banerjee, John A. Chandy, Manish Gupta, Eugene W. Hodges IV, John G. Holm, Antonio Lain, Daniel J. Palermo, Shankar Ramaswamy, Ernesto Su
Venue: Computer (1995)

The authors describe a flexible compiler framework for distributed-memory multicomputers, called Paradigm (Parallelizing Compiler for Distributed-Memory, General-Purpose Multicomputers). To extract computational power from a multicomputer, users must often expend significant time and energy to write efficient software. Paradigm addresses this problem by automatically parallelizing sequential programs. Besides handling traditional compiler optimizations, Paradigm focuses on several other areas within a unified platform. These include automatic data distribution, communication optimizations, support for irregular computations, exploitation of functional and data parallelism, and multithreaded execution. Automatic data partitioning involves several choices. These include array alignment, distribution (block or cyclic), block size, and mesh configuration. Paradigm addresses these decisions in distinct phases. The compiler supports both regular and irregular computations. For regular computations, the compiler uses efficient processor-tagged descriptors to handle the simplest and most frequent cases. It uses more general, inequality-based representations for the difficult cases. This lets Paradigm compile a larger proportion of programs without jeopardizing compilation speed. In addition, to reduce the overhead caused by frequent communications, the compiler employs message coalescing, message verification, message aggregation, and coarse-grain pipelining. For irregular computations, Paradigm uses two sequences of code: an inspector for preprocessing and an executor for performing the actual computations. The Parallel Irregular Library with Application of Regularity (PILAR) provides Paradigm's irregular runtime support. Finally, the authors describe how Paradigm uses functional and data parallelism and multithreading to improve overall execution efficiency.
An Example of Deriving Performance Properties from a Visual Representation of Program Execution
Authors: Marc Abrams
Venue: IEEE Transactions on Parallel and Distributed Systems (1997)

Through geometry, program visualization can yield performance properties. We derive all possible synchronization sequences and durations of blocking and concurrent execution for two process programs from a visualization mapping processes, synchronization, and program execution to Cartesian graph axes, line segments, and paths, respectively. Relationships to Petri nets are drawn.
Built-In Self-Test: Assuring System Integrity
Authors: Bernd Könemann, Ben Bennetts, Najmi Jarwala, Benoit Nadeau-Dostie
Venue: Computer (1996)

Testing electronic products is a crucial part of the manufacturing process. This is particularly the case with today's complex products, in which even the smallest hardware defect can cause serious malfunctions. Integrated circuits being their life on a wafer and are tested even before the wafer is diced into chips. The chips are subsequently packaged and used in higher level electronics. Each manufacturing step can introduce new defects. However, as products become more complex, it becomes more difficult to use traditional external testing methods. This is the case because the integrated-circuit chips that that these products contain have an increasing number of deeply embedded core functions and are also operating at increasing frequencies. In addition, testing equipment has bandwidth and performance limitations. In many cases, BIST , which moves critical test and measurement functions inside chips, can be used to conduct the necessary testing. BIST, which utilizes scanning technology, provides the stimulus-generation and response-processing capabilities necessary to test complex logic structures and embedded memory. Embedded BIST functions match the chip's capabilities, which can make them very effective testing mechanisms. Also, BIST stays with the chip throughout its life. Moreover, the addition of BIST features to electronics hardware frequently doesn't significantly increase a product's size, cost, and production time, as was the case in the past.
The AzusA 16-Way Itanium Server
Authors: Fumio Aono, Masayuki Kimura
Venue: IEEE Micro (2000)

AzusA is the 16-way optimized ItaniumTM processor-based server with enhanced reliability, availability and serviceability (RAS) features required for enterprise-level computing. With its low memory access latencies and small remote/local ratio, AzusA is expected to demonstrate consistent performance scalability for all kinds of workloads.
Distributed Performance Monitoring: Methods, Tools, and Applications
Authors: R. Hofmann, R. Klar, B. Mohr, A. Quick, M. Siegle
Venue: IEEE Transactions on Parallel and Distributed Systems (1994)

A method for analyzing the functional behavior and the performance of programs in distributed systems is presented. We use hybrid monitoring, a technique which combines advantages of both software monitoring and hardware monitoring. The paper contains a description of a hardware monitor and a software package (ZM4/SIMPLE) which make our concepts available to programmers, assisting them in debugging and tuning of their code. A short survey of related monitor systems highlights the distinguishing features of our implementation. As an application of our monitoring and evaluation system, the analysis of a parallel ray tracing program running on the SUPRENUM multiprocessor is described. It is shown that monitoring and modeling both rely on a common abstraction of a system's dynamic behavior and therefore can be integrated to one comprehensive methodology. This methodology is supported by a set of tools.
Engineering a visual field
Authors: Clifford Singer
Venue: Octogon Mathematical Magazine (2002)

Of the branches of mathematics, geometry has, from the earliest Hellenic period, been given a curious position that straddles empirical and exact science. Its standing as an empirical and approximate science stems from the practical pursuits of artistic drafting, land surveying and measuring in general. From the prominence of visual applications, such as figures and constructions in the twentieth century Einstein's General Theory of Relativity holds that the geometry of space-time is dependent upon physical quantities. On the other hand, earlier on in history, the symmetry and perfect regularity of certain geometric figures were taken as representative of a higher order knowledge than that afforded by sense experience.