ppxscal/embedding_network huggingface dataset:
Grid-based simulation and the method of conditional least squares
Authors: Katherine B. Ensor, Peter W. Glynn
Venue: Proceedings of the 28th conference on Winter simulation (1996)

This paper is concerned with the use of simulation to compute the conditional expectations that arise in the method of conditional least squares. Our approach involves performing simulations at each point on a discrete grid imbedded within a statistical parameter space. Our main result concerns the number of grid points and amount of simulation necessary in order to obtain a degree of accuracy comparable to that in the case in the which the conditional expectations are available in closed form.
Allocation strategies for Ada tasks on hypercube multi-processors
Authors: Pen-Nan Lee, Ravinder P. Reddy, Yiwei Chen
Venue: Proceedings of the conference on TRI-ADA '90 (1990)

An important aspect of the efficient use of a hypercube computer to solve a given problem is the assignment of subtasks to processors in such a way that communication overhead is low. Without such strategies the gains in parallelism are negated by the increased communication costs. This paper presents strategies to assign tasks to subcubes of the Hypercube to decrease the communication distance between cooperating tasks of a hypercube computer running the Ada runtime system. Such allocation was not feasible previously because of the limitations imposed by the termination method employed. This paper (1) presents a new, more efficient termination method to solve this problem, (2) a static and (3) a dynamic method to allocate tasks to nodes of the hypercube.
Catenable double-ended queues
Authors: Chris Okasaki
Venue: ACM SIGPLAN Notices (1997)

Catenable double-ended queues are double-ended queues (deques) that support catenation (i.e., append) efficiently without sacrificing the efficiency of other operations. We present a purely functional implementation of catenable deques for which every operation, including catenation, takes O(1) amortized time. Kaplan and Tarjan have independently developed a much more complicated implemen-tation of catenable deques that achieves similar worst-case bounds. The two designs are superficially similar, but differ in the underlying mechanism used to achieve efficiency in a persistent setting (i.e., when used in a non-single-threaded fashion). Their implementation uses a technique called recursive slowdown, while ours relies on the simpler mechanism of lazy evaluation.Besides lazy evaluation, our implementation also exemplifies the use of two additional language features: polymorphic recursion and views. Neither is indispensable, but both significantly simplify the presentation.
Indexed BDDs: Algorithmic Advances in Techniques to Represent and Verify Boolean Functions
Authors: Jawahar Jain, James Bitner, Magdy S. Abadir, Jacob A. Abraham, Donald S. Fussell
Venue: IEEE Transactions on Computers (1997)

A new Boolean function representation scheme, the Indexed Binary Decision Diagram (IBDD), is proposed to provide a compact representation for functions whose Ordered Binary Decision Diagram (OBDD) representation is intractably large. We explain properties of IBDDs and present algorithms for constructing IBDDs from a given circuit. Practical and effective algorithms for satisfiability testing and equivalence checking of IBDDs, as well as their implementation results, are also presented. The results show that many functions, such as multipliers and the hidden-weighted-bit function, whose analysis is intractable using OBDDs, can be efficiently accomplished using IBDDs. We report efficient verification of Booth multipliers, as well as a practical strategy for polynomial time verification of some classes of unsigned array multipliers.
Combining card marking with remembered sets: how to save scanning time
Authors: Alain Azagury, Elliot K. Kolodner, Erez Petrank, Zvi Yehudai
Venue: Proceedings of the 1st international symposium on Memory management (1998)

We consider the combination of card marking with remembered sets for generational garbage collection as suggested by Hosking and Hudson [3]. When more than two generations are used, a naive implementation may cause excessive and wasteful scanning of the cards and thus increase the collection time. We offer a simple data structure and a corresponding algorithm to keep track of which cards need be scanned for which generation. We then extend these ideas for the Train Algorithm of [4]. Here, the solution is more involved, and allows tracking of which card should be scanned for which car-collection in the train.
Everything you ever wanted to know about software engineering education, but were afraid to ask (panel)
Authors: Nancy R. Mead, Thomas B. Hilburn, Donald J. Bagert, Michael Ryan, Oddur Benediktsson, Frances Van Scoy
Venue: Proceedings of the 6th annual conference on the teaching of computing and the 3rd annual conference on Integrating technology into computer science education: Changing the delivery of computer science education (1998)

In this panel, we will address questions on software engineering education that are voted on by the conference attendees in advance of the session. A sample set of questions will be posted. Conference attendees who will then vote on the questions to be addressed by the panel will augment these. After the panellists provide answers to a given question, the discussion will be opened up for follow-up questions or comments by the conference attendees.
The visual display of information in an information retrieval environment
Authors: Donald B. Crouch
Venue: Proceedings of the 9th annual international ACM SIGIR conference on Research and development in information retrieval (1986)

This paper gives an overview of the graphical techniques which have been used in the representation of information in a document collection environment. An assessment of the applicability of existing multivariate data graphical techniques to the vector space model is presented.
A Low-Power Encoder For Pyramid Vector Quantization of Subband Coefficients
Authors: Won Namgoong, Teresa H. Meng
Venue: Journal of VLSI Signal Processing Systems (1997)

A real-time, low-power video encoder design for pyramid vector quantization (PVQ) has been presented. The quantizer is estimated to dissipate only 2.1 mW for real-time video compression of images of 256 &times; 256 pixels at 30 frames per second in standard 0.8-micronCMOS technology with a 1.5 V supply. Applying this quantizer to subband decomposed images, the quantizer performs better than JPEG on average. We achieve this high level of power efficiency with image quality exceeding that of variable rate codes through algorithmic and architectural reformulation. The PVQ encoder is well-suited for wireless, portable communication applications.
Performance evaluation of hierarchical distributed simulators
Authors: Doo-Kwon Baik, Bernard P. Zeigler
Venue: Proceedings of the 17th conference on Winter simulation (1985)

A model can be decomposed into components, then mapped onto a network of simulators for execution. With different levels of decompositions, we are interested in finding the optimal model decomposition that can be implemented on a particular structure of distributed simulators. This is done by comparing performance measures such as the minimum response time or the maximum throughout per unit of hardware complexity. We claim that the need for a model capable of performance evaluation is an important concern in designing distributed simulators. Thus a methodology for performance evaluation and simulation modelling of hierarchically specified distributed simulators is required. From the empirical results, we found that simulating a given distributed simulator model is suitable to get optimal performances, that is, each model has an optimal decomposition level in terms of performance. The influential performance measures are the average of simulation run times and the product of the average run time and the hardware complexity of the given simulator model.
An accurate and efficient gate level delay calculator for MOS circuits
Authors: Foong-Charn Chang, Chin-Fu Chen, Prasad Subramaniam
Venue: Proceedings of the 25th ACM/IEEE Design Automation Conference (1988)

This paper describes an accurate and efficient gate level delay calculator that automatically characterizes and computes the gate delays of MOS circuits. The high accuracy is attributed to a sophisticated delay model, which includes an accurate representation of the waveform, a consistent and meaningful definition of delay, a consideration of waveform slope effects at both the input and output of a gate, and an innovative approach for handling transmission gate circuits. Meanwhile, the high efficient delay characterization is accomplished through a fast timing simulation technique instead of using a circuit simulation or a timing simulation technique, a theorem to reduce a two-dimensional delay table into a scaled one-dimensional table, and an incremental characterization process. The delay calculator has been used in a production timing analyzer and a production multiple delay simulator since 1986. The results show that the multiple delay simulator performs 5000 times faster than a SPICE-like circuit simulator at only 15% cost of accuracy. Gate delay models, delay characterization, and practical examples are presented in this paper.
Model development and verification for high level analog blocks
Authors: Chandramouli Visweswariah, Rakesh Chadha, Chin-Fu Chen
Venue: Proceedings of the 25th ACM/IEEE Design Automation Conference (1988)

Behavioral modeling of analog circuitry is an important step in making the design of large, mixed analog-digital chips manageable. Towards that end, this paper proposes a methodology for describing arbitrary analog blocks at the behavioral level. In order to verify the functionality of such behavioral models before incorporation into a simulation environment, a verification tool, ACME, has been developed. The designer's knowledge of the subcircuit is relied upon to generate good models. However, in some special cases, such as analog filters described as Laplace transforms or in the z-domain, the generation of time-domain models conforming to the above methodology has been automated. The tools modgens and modgenz convert transfer functions H (s) and H (z), respectively, into state-space representations in the time-domain. The behavioral models for the analog blocks are suitable for simulation along with digital subcircuits to accomplish mixed analog-digital simulation.
On the Stability of the Discontinuous Galerkin Method for the Heat Equation
Authors: Ch. G. Makridakis, I. Babuska
Venue: SIAM Journal on Numerical Analysis (1997)

This paper analyzes stability properties of a class of discontinuous Galerkin methods for the heat equation. It is shown that the finite element projection associated with these methods is stable with respect to a mesh-dependent norm---a discrete analogue of the space--time $L^2$-norm. Optimal order-regularity error bounds in $L^2([0, T]; L^2 (\Omega))$ are derived.
The design and implementation of a program development system based on rewriting method
Authors: Sun Yongquiang, Lin Kai, Shen Li
Venue: ACM SIGPLAN Notices (1997)

In this paper, we present a program development system based on rewriting method with the goal of providing an powerful tool for automatic software development and rapid prototyping. New mechanisms for defining constrained types and optimal rules are introduced to functional programming languages to achieve strong expressiveness. The enhanced functional programming language is combined with an algebraic specification language. Thus, the design from specification to program can be supported, and the efficiency and flexibility of programming can also be improved. In this system, both static and dynamic techniques are used to deal with constrained type check. All function definitions, computation constraints and optimal rules are regarded as rewriting rules. In order to provide a strong support for a large group of TRSs which may be neither terminating nor orthogonal, we propose a method using structure measure to decide TRSs' confluences. Based on this method, we present a partial completion algorithm to generate a rewriting model from a specification. Depending on term rewriting system, the mixed language system computes with parallel outermost and needed reduction. We explain the principles and implementation techniques in detail, some examples are provided.
A Web based configuration control system for team projects
Authors: Ronald Curtis
Venue: Proceedings of the twenty-eighth SIGCSE technical symposium on Computer science education (1997)

In courses involving team programming projects, it is desirable to have team members share files, and establish procedures for developing a configuration. Often, faculty members also wish to track each team to detect team problems and to determine the team dynamics.This paper describes a system that uses the Web to provide a simple to use student interface for getting and submitting files to their team for building a new configuration. It also describes some of the tools available to the faculty member to organize the teams. Since the system backend is programmable, the faculty member can add any functionality desired.
Comment on "A New Public-Key Cipher System Based Upon the Diophantine Equations"
Authors: S. R. Blackburn, S. Murphy, K. G. Paterson
Venue: IEEE Transactions on Computers (1997)

The public key system proposed by Lin et al. [1] is insecure, even if used as a private key system.
GigaHertz MUX-DEMUX Chip with HF BIST
Authors: Lars Hellberg, Owe Thessén, Hannu Tenhunen, José-Maria Gobbi
Venue: Analog Integrated Circuits and Signal Processing (1997)

Full functional test at speed, in-situ is an ideal choice for use for detection of errors in circuit behaviour for high speed broadband communication circuits and to avoid test set-up disturbances on high frequency signals. This article presents a novel technique to solve the high frequency test of Gbit/s data rate Time-Division Multiplexer/Demultiplexer circuits. This in-situ test technique is based on conventional pseudo-random sequence generation and signature analysis. By linear feedback interconnect and reusable architecture the multiplexer/demultiplexer circuits can operate as generator/analyser with minimal degeneration of bit shift rate. Circuit simulation showed that the system operates correctly with a clock frequency up to 3 GHz in a silicon bipolar technology with a current gain cut-off frequency f_T = 15 GHz.
A scheduling and pipelining algorithm for hardware/software systems
Authors: Smita Bakshi, Daniel D. Gajski
Venue: Proceedings of the 10th international symposium on System synthesis (1997)

Given a hardware/software partitioned specification and an allocation (number and type) of processors, we present an algorithm to (1) map each of the software behaviors (or tasks) to processors, (2) pipeline the system specification, and (3) schedule the behaviors in each pipe stage, amongst selected hardware components and processors, so as to satisfy a throughput constraint at minimal hardware cost. Thus, to achieve high performance, not only are critical tasks implemented as pipelined hardware architectures, but the system is also divided into concurrently executing stages. Furthermore, to offset the cost of this increased concurrency, non-critical sections are implemented on processors or as cheaper hardware blocks. Our experiments demonstrate the feasibility of our approach and the necessity of system pipelining in high performance design.
Using ZPL to develop a parallel chaos router simulator
Authors: Wilkey Richardson, Mary L. Bailey, William H. Sanders
Venue: Proceedings of the 28th conference on Winter simulation (1996)

This paper reports on our experience in writing a parallel version of a chaos router simulator using the new data driven parallel language ZPL. The simulator is a large program that tests the capabilities of ZPL. The (parallel) ZPL program is compared with the existing serial implementation on two very different architectures: a 16-processor Intel Paragon and a cluster of eight Alpha work stations. On the Paragon, the simulator performs best when simulating medium- to large-sized routers, and on the Alpha cluster, it performs best when simulating large routers. Thus a user can choose the parallel platform best suited to the router size.
A Hypergraph Framework for Optimal Model-Based Decomposition ofDesign Problems
Authors: Nestor F. Michelena, Panos Y. Papalambros
Venue: Computational Optimization and Applications (1997)

Decomposition of large engineering system models is desirable since increased model size reduces reliability and speed of numerical solution algorithms. The article presents a methodology for optimal model-based decomposition (OMBD) of design problems, whether or not initially cast as optimization problems. The overall model is represented by a hypergraph and is optimally partitioned into weakly connected subgraphs that satisfy decomposition constraints. Spectral graph-partitioning methods together with iterative improvement techniques are proposed for hypergraph partitioning. A known spectral K-partitioning formulation, which accounts for partition sizes and edge weights, is extended to graphs with also vertex weights. The OMBD formulation is robust enough to account for computational demands and resources and strength of interdependencies between the computational modules contained in the model.
Future developments in information technology (abstract)
Authors: Ian M. Ross
Venue: Proceedings of the 25th ACM/IEEE Design Automation Conference (1988)

The primary information technologies, microelectronics and photonics, continue to improve their performance at extraordinary rates and are not expected to reach any fundamental theoretical limitations before the turn of the century. In his keynote address, Ian Ross will review progress in information technologies to date, consider its prospects and assess the emerging technologies and systems that may follow, with an emphasis on the engineering challenges ahead. In 1963, Dr. Ross received the Morris N. Liebmann Award from the Institute of Radio Engineers, now a part of the IEEE. In 1969 and 1975 he received the Public Service Group Achievement Award from the National Aeronautics and Space Administration. Dr. Ross is a Fellow of the Institute of Electrical and Electronics Engineers and was elected to the National Academy of Engineering in April 1973. In May 1981, he was elected to a Fellowship in the American Academy of Arts and Sciences. He was elected to the National Academy of Sciences in April 1982.
Infinite-Dimensional Linear Programming Approach to SingularStochastic Control
Authors: Michael I. Taksar
Venue: SIAM Journal on Control and Optimization (1997)

We consider a multidimensional singular stochastic control problem with state-dependent diffusion matrix and drift vector and control cost depending on the position and direction of displacement of the controlled process. The objective is to minimize the total expected discounted cost. We write an equivalent infinite-dimensional linear programming problem on a subspace of the space conjugate to ${\cal C}({\Bbb R}^n)\times {\cal C}({\Bbb R}^{n}\times B)$, where $B$ is the unit sphere in ${\Bbb R}^n$. We write a dual linear program and prove absence of duality gap. The dual program characterizes the optimal cost function as a maximal solution to the variational inequality with gradient constraints.
Drawing graphs to convey proximity: an incremental arrangement method
Authors: Jonathan D. Cohen
Venue: ACM Transactions on Computer-Human Interaction (TOCHI) (1997)

Graph drawings are increasingly finding their way into user interfaces to convey a variety of relationships. This article deals with rendering graphs to show proximity between vertices by making their configuration (screen) distances reflect their distances in the graph. An arrangement method is described that achieves good drawings at speeds suitable for user interaction on a desktop computer. The method is &ldquo;incremental&rdquo; in that it first arranges a small portion of the graph, then arranges successively larger fractions of the graph until a suitable arrangement for the entirety is achieved. The incremental approach not only offers speed improvements, but avoids many of the suboptimal solutions reached with other iterative approaches. Algorithms are described in pseudocode, and results are presented.
A Quantitative Model of the Security Intrusion Process Based on Attacker Behavior
Authors: Erland Jonsson, Tomas Olovsson
Venue: IEEE Transactions on Software Engineering (1997)

This paper is based on a conceptual framework in which security can be split into two generic types of characteristics, behavioral and preventive. Here, preventive security denotes the system's ability to protect itself from external attacks. One way to describe the preventive security of a system is in terms of its interaction with the alleged attacker, i.e., by describing the intrusion process. To our knowledge, very little is done to model this process in quantitative terms. Therefore, based on empirical data collected from intrusion experiments, we have worked out a hypothesis on typical attacker behavior. The hypothesis suggests that the attacking process can be split into three phases: the learning phase, the standard attack phase, and the innovative attack phase. The probability for successful attacks during the learning and innovative phases is expected to be small, although for different reasons. During the standard attack phase it is expected to be considerably higher. The collected data indicates that the breaches during the standard attack phase are statistically equivalent and that the times between breaches are exponentially distributed. This would actually imply that traditional methods for reliability modeling could be applicable.
An overview of debugging tools
Authors: Rob Law
Venue: ACM SIGSOFT Software Engineering Notes (1997)

This paper reviews empirical studies on debugging models and the findings associated with these models. There is a discussion on the evolution of program slicing applied to program debugging and different generations of debugging tools are analyzed and criticized.Finally, a programming environment section provides examples of program maintenance tools.
Program analysis: a toolmaker's perspective
Authors: Reinhard Wilhelm
Venue: ACM SIGPLAN Notices (1997)

Program Analysis is largely based on generic theories that have the potential for toolmaking. Intensive research should go into the still open problems faced by the creators of program analysis generators. To date, the more generic method of abstract interpretation has advantages for toolmaking compared to type inference based and set based analysis methods.
Process reuse using a template approach: a case-study from avionics
Authors: W. Lam
Venue: ACM SIGSOFT Software Engineering Notes (1997)

This paper reports on the practical reuse of requirements engineering processes for aero-engine control systems. An approach is presented which uses templates to model typical activities in a process, where a process execution is seen as the instantiation of the template. The paper begins with the motivations for process reuse, and then describes aspects of the template approach in greater detail. The lessons learnt about process reuse based on our experience are summarised. The paper concludes with an early evaluation on the practicality of the approach, and highlights areas of further work.