ppxscal/embedding_network huggingface dataset:
A structured approach to instrumentation system development and evaluation
Authors: Abdul Waheed, Diane T. Rover
Venue: Proceedings of the 1995 ACM/IEEE conference on Supercomputing (CDROM) (1995)

Software instrumentation is a widely used technique for parallel program performance evaluation, debugging, steering, and visualization. With increasing sophistication of parallel tool development technologies and broadening of application areas where these tools are being used, runtime data collection and management activities are growing in importance; we use the term instrumentation system (IS) to refer to components that support these activities in state-of-the-art parallel tool environments. An IS consists of Local Instrumentation Servers, an Instrumentation System Manager, and a Transfer Protocol. The overheads and perturbation effects attributed to an IS must be accounted for to ensure correct and efficient representation of program behavior, especially for on-line and real-time environments. Moreover, an IS is a key facilitator of integration of tools in an environment. In this paper, we define the primary components of an IS and their roles in an integrated environment, and classify ISs according to selected features. We introduce a structured approach to plan, design, model, evaluate, implement, and validate an IS. The approach provides a means to formally address domain-specific requirements. The modeling and evaluation processes are illustrated in the context of three distinctive IS case studies for PICL, Paradyn, and Vista. Valuable feedback on performance effects of IS parameters and policies can assist developers in making design decisions early in the software development cycle. Additionally, use of structured software engineering methods can support the mapping of an abstract IS model to an implementation of the IS.
Interval Availability Analysis Using Denumerable Markov Processes: Application to Multiprocessor Subject to Breakdowns and Repair
Authors: Gerardo Rubino, Bruno Sericola
Venue: IEEE Transactions on Computers (1995)

Interval availability is a dependability measure defined by the fraction of time during which a system is operational over a finite observation period.The computation of its distribution allows the user to ensure thatthe probability that its system will achieve a given availability level is high enough. The system is assumed to be modeled as a Markov process with countable state space. We propose a new algorithm to compute the interval availability distribution. One of its main advantages is that, in some cases, it applies even to infinite state spaces. This is useful, for instance, in case of models taking into accountcontention with unbounded buffers. This important feature is illustrated on models of multiprocessor systems subject to breakdowns and repair. When the model is finite, we show through a numerical example that the new technique can perform very well.Index Terms¿ Denumerable Markov processes, dependability prediction, interval availability distribution, repairable computer systems, transient analysis, queues with breakdowns, uniformization.
Confessions of a used-program salesman: lessons learned
Authors: Will Tracz
Venue: ACM SIGSOFT Software Engineering Notes (1995)

Software reuse is the second oldest programming profession. Ever since the first program logic board was wired, people have been looking for ways of saving time and money by building upon other's efforts and not &ldquo;not re-inventing any wheels.&rdquo; This article summarizes the lessons I have learned as used-program salesman. Using this analogy, I will examine efforts made to institutionalize software reuse.
Knowledge-level analysis of planning systems
Authors: André Valente
Venue: ACM SIGART Bulletin (1995)

Planning is one of the most important and oldest fields of AI. However, there is no consensus on how to compare and classify planning systems and methods. Neither the traditional view of planning as search nor the formalization efforts have been able to provide a basis for a classification scheme.This article explores the idea that a perspective based on Newell's knowledge level can be useful for this task. We present a knowledge-level analysis of classical planning systems in terms of models of the problem-solving methods they used. Rather than reengineering these systems in detail, however, our goal is to show how this type of analysis can help define which roles knowledge may play in planning tasks, and how these roles can be used to compare planning methods in terms of (i) which types of knowledge are used, (ii) how they are structured in what we call domain models. As a tool to analyze and represent planning methods we use the KADS methodology.
Computation of Pseudo-Differential Operators
Authors: Gang Bao, William W. Symes
Venue: SIAM Journal on Scientific Computing (1996)

A simple algorithm is described for computing general pseudo-differential operator actions. Our approach is based on the asymptotic expansion of the symbol together with the fast Fourier transform (FFT). The idea is motivated by the characterization of the pseudo-differential operator algebra. We show that the algorithm is efficient through analyzing its complexity. Some numerical experiments are also presented.
Concerning Difference Matrices
Authors: Charles J. Colbourn, Donald L. Kreher
Venue: Designs, Codes and Cryptography (1996)

Several new constructions for difference matrices are given. One class of constructions uses pairwise balanced designs to develop new difference matrices over the additive group of \GF(q). A second class of constructions gives difference matrices over groups whose orders are not (necessarily) prime powers.
Designing meeting support systems in a user-centered manner: the case of the Helsinki prototype system
Authors: Petri Maaranen, Kalle Lyytinen
Venue: Proceedings of conference on Organizational computing systems (1995)

Multilateral diplomacy faces pressures to improve the efficiency of its operations. Because meetings play a central role in diplomacy they form one promising target in productivity improvements. Diplomatic meetings are rife with political maneuvering and embedded with pervasive diplomatic rituals and protocols which all affect considerably the content and form of successful technology interventions. In this paper we describe a meeting support system called the Helsinki Prototype System. To our knowledge it was the first meeting support system (MSS) which was intended to support multilateral diplomatic meetings. It was designed for the fourth Follow-up meeting of the Conference on Security and Cooperation in Europe. We illustrate how we conducted the requirements specification process and describe the major outcomes of the design process.
A leaf-cell generator for silicon compilers
Authors: D. de Abreu Moreira, L. T. Walczowski
Venue: ACM SIGPLAN OOPS Messenger (1995)

A program for the design of leaf cells for silicon compilers of digital VLSI (Very Large Scale Integrated) circuits, is being developed. This program uses rule based reasoning and genetic algorithmic search techniques, whenever each is appropriate. Leaf cells are subcircuits of a complexity comparable with SSI (Small Scale Integration) components such as one-bit adders, flip-flops or multiplexers. They typically contain between 10 to 100 transistors. Silicon compilers can use libraries of ready designed leaf cells or each leaf cell can be automatically generated [1] by synthesis tools such as the program we are developing. The main advantage of the synthesis approach is that circuit performance will not be sacrificed since a new, optimal layout will be produced whatever the complexity of the circuit and whenever the fabrication process is upgraded.
A set of Ada packages for high-precision calculations
Authors: B. G. S. Doman, C. J. Pursglove, W. M. Coen
Venue: ACM Transactions on Mathematical Software (TOMS) (1995)

The packages described here are designed to perform efficient high-accuracy calculations in cases where there can be serious loss of significance due to rounding errors. Numbers are represented by a value part with a variable number of digits in the mantissa and an error estimate which is updated throughout the calculation and which gives a range of possible values for the result of the calculation. For economy and speed, intermediate results are truncated so that the least-significant digits correspond to values only a few orders of magnitude smaller than the error estimate. Type definitions and the standard arithmetic operations, together with conversions to and from integers, are provided in one package. The mathematical constants &pgr; and Euler's gamma are incorporated to a maximum precision of 320 digits in a package that also contains all of the standard elementary functions. Separate packages contain input and output procedures and conversion to and from floating-point types.
Scheduling memory constrained jobs on distributed memory parallel computers
Authors: Cathy McCann, John Zahorjan
Venue: Proceedings of the 1995 ACM SIGMETRICS joint international conference on Measurement and modeling of computer systems (1995)

We consider the problem of multiprocessor scheduling of jobs whose memory requirements place lower bounds on the fraction of the machine required in order to execute. We address three primary questions in this work:1. How can a parallel machine be multiprogrammed with minimal overhead when jobs have minimum memory requirements?2. To what extent does the inability of an application to repartition its workload during runtime affect the choice of processor allocation policy?3. How rigid should the system be in attempting to provide equal resource allocation to each runnable job in order to minimize average response time?This work is applicable both to parallel machines and to networks of workstations supporting parallel applications.
Circuit partitioning with logic perturbation
Authors: David Ihsin Cheng, Chih-Chang Lin, Malgorzata Marek-Sadowska
Venue: Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design (1995)

Traditionally, the circuit partitioning problem is done by first modeling a circuit as a graph and then partitioning is performed on the modeling graph. Using the concept of alternative wires, we propose an efficient method that is able to preserve a local optimal solution in the graph domain while a different graph, representing the same circuit, is generated. When a conventional graph partitioning technique reaches a local optimal solution, our proposed technique generates a different graph that is logically equivalent to the original circuit, and that has equal or better partitioning solution. Faced with a different graph which is newly generated, together with a currently good partitioning solution, a conventional graph partitioning technique may then escape from the local optimum and continue searching for better solutions in a different graph domain. The proposed technique can be combined with almost any graph partitioner. Experiments show encouraging results.
Multivariate Classification through Adaptive Delaunay-Based C0 Spline Approximation
Authors: David Cubanski, David Cyganski
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1995)

This paper introduces a new method for adaptively building a multivariate C0 spline approximation from scattered samples of an unknown function. The central feature of the method is a means for adaptively tesselating an approximation space to form a multidimensional mesh over which the spline fitting then occurs. The mesh used is a Delaunay tesselation of the approximation space whose vertices lie at a subset of the scattered sample locations. The specific subset of sample locations used is adaptively determined by repeated overfitting and simplification of the resulting spline approximation.Overfitting and simplification is an attractive paradigm for high-dimensional approximation problems because it provides a means for forming an approximation that is complex only in regions where the scattered sample data provide sufficient evidence of complexity in the underlying unknown function. Overfitting and simplification is effectively exploited in this new approach as the function representation used is not subject to certain recursive dependencies.The properties of the new technique are demonstrated in the context of an easily visualized bivariate classification problem. The technique is then applied to a 10-dimensional clinical ECG classification problem, and the results are compared to those obtained with a perceptron based neural network.
Test register insertion with minimum hardware cost
Authors: Albrecht P. Stroele, Hans-Joachim Wunderlich
Venue: Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design (1995)

Implementing a built-in self-test by a "test per clock" scheme offers advantages concerning fault coverage, detection of delay faults, and test application time. Such a scheme is implemented by test registers, for instance BILBOs and CBILBOs, which are inserted into the circuit structure at appropriate places. An algorithm is presented which is able to find the cost optimal placement of test registers for nearly all the ISCAS'89 sequential benchmark circuits, and a suboptimal solution with slightly higher costs is obtained for all the circuits within a few minutes of computing time. The algorithm can also be applied to the Minimum Feedback Vertex Set problem in partial scan design, and an optimal solution is found for all the benchmark circuits. The resulting self-testable circuits are analyzed. It is found that often CBILBOs lead to a minimum hardware overhead and also simplify test scheduling and test control.
Preconditioned Krylov Subspace Methods for Lyapunov Matrix Equations
Authors: Marlis Hochbruck, Gerhard Starke
Venue: SIAM Journal on Matrix Analysis and Applications (1995)

The authors study the iterative solution of Lyapunov matrix equations $$ A X + X A^{T} = - D^{T} D $$ by preconditioned Krylov subspace methods. These solution techniques are of interest for problems leading to large and sparse matrices $A$ as those arising from certain applications in large space structure control theory. We show how conjugate gradient (CG)-type methods for nonsymmetric linear systems can be applied to this type of equation utilizing the special structure when computing matrix-vector and inner products. In contrast to recently developed methods for such matrix equations based on Krylov subspaces associated with $A$, the authors implicitly work with the equivalent system of linear equations involving the Kronecker sum $M = A \otimes I_N + I_N \otimes A$. Motivation for this new approach comes from the observation that it allows the straightforward incorporation of preconditioners. Several preconditioners for such problems are presented and analyzed. In particular, since the solution matrix $X$ is known to be symmetric, it is of interest to know which of the methods produces symmetric iterates in each step. It is proven that this is the case for alternating direction implicit (ADI)-type and (point) symmetric successive overrelaxation (SSOR) preconditioning in association with the quasiminimal residual (QMR) method. As numerical results show, it is essential to use preconditioning in association with Krylov subspace methods. Several preconditioners for such problems are presented and analyzed. Finally numerical examples are presented where the different preconditioners are compared.
ALPHA/Sim simulation software tutorial
Authors: Kendra E. Moore, John E. Brennan
Venue: Proceedings of the 27th conference on Winter simulation (1995)

ALPHA/Sim is a general purpose, discrete event simulation tool. ALPHA/Sim allows a user to graphically build a simulation model, enter input data via integrated forms, execute the simulation model, and view the simulation results, within a single graphical environment. We introduce ALPHA/Sim and describe how to use ALPHA/Sim to build, simulate, and analyze a simple queueing type system. In addition, we briefly describe some advanced features and list some sample applications.
On characterizing bandwidth requirements of parallel applications
Authors: Anand Sivasubramaniam, Aman Singla, Umakishore Ramachandran, H. Venkateswaran
Venue: Proceedings of the 1995 ACM SIGMETRICS joint international conference on Measurement and modeling of computer systems (1995)

Synthesizing architectural requirements from an application viewpoint can help in making important architectural design decisions towards building large scale parallel machines. In this paper, we quantify the link bandwidth requirement on a binary hypercube topology for a set of five parallel applications. We use an execution-driven simulator called SPASM to collect data points for system sizes that are feasible to be simulated. These data points are then used in a regression analysis for projecting the link bandwidth requirements for larger systems. The requirements are projected as a function of the following system parameters: number of processors, CPU clock speed, and problem size. These results are also used to project the link bandwidths for other network topologies. Our study quantifies the link bandwidth that has to be made available to limit the network overhead in an application to a specified tolerance level. The results show that typical link bandwidths (200-300 MBytes/sec) found in current commercial parallel architectures (such as Intel Paragon and Cray T3D) would have fairly low network overhead for the applications considered in this study. For two of the applications, this overhead is negligible. For the other applications, this overhead can be limited to about 30% of the execution time provided the problem sizes are increased commensurate with the processor clock speed. The technique presented can be useful to a system architect to synthesize the bandwidth requirements for realizing well-balanced parallel architectures.
Cyberspace across the Sahara: computing in North Africa
Authors: A. K. Danowitz Y. Nassef, S. E. Goodman
Venue: Communications of the ACM (1995)

Spanning 7.2 million square kilometers from the Atlantic Ocean to the Red Sea, and encompassing the Great Saharan Desert and Nile River Valley, North Africa embraces Mauritania, Western Sahara, Morocco, Algeria, Tunisia, Libya, and Egypt. Charting the development of information technology (IT) is as challenging as traversing the souks, the labyrinthine ancient marketplaces.
A simulation model of a surveillance radar data processing system using HI-MASS
Authors: Steven D. Farr, Douglas G. Fritz, Alex F. Sisti, Robert G. Sargent
Venue: Proceedings of the 27th conference on Winter simulation (1995)

The paper discusses the model specification, construction of the executable model, model execution, and the simulation results of a simulation model of a surveillance radar data processing system that was developed using the Hierarchical Modeling and Simulation System (HI-MASS). HI-MASS is an object oriented C++ based system that supports model specification (modeling) using the Hierarchical Control Flow Graph Model paradigm and executes simulation models using the sequential synchronous simulation execution algorithm. Models specified in this model paradigm use two complementary hierarchical specification structures, one to specify the model components and their interconnections and the other to specify the behaviors of the individual components. The components and their interconnections are specified in HI-MASS via visual interactive modeling.
Multi-dimensional resource scheduling for parallel queries
Authors: Minos N. Garofalakis, Yannis E. Ioannidis
Venue: Proceedings of the 1996 ACM SIGMOD international conference on Management of data (1996)

Scheduling query execution plans is an important component of query optimization in parallel database systems. The problem is particularly complex in a shared-nothing execution environment, where each system node represents a collection of time-shareable resources (e.g., CPU(s), disk(s), etc.) and communicates with other nodes only by message-passing. Significant research effort has concentrated on only a subset of the various forms of intra-query parallelism so that scheduling and synchronization is simplified. In addition, most previous work has focused its attention on one-dimensional models of parallel query scheduling, effectively ignoring the potential benefits of resource sharing. In this paper, we develop an approach that is more general in both directions, capturing all forms of intra-query parallelism and exploiting sharing of multi-dimensional resource nodes among concurrent plan operators. This allows scheduling a set of independent query tasks (i.e., operator pipelines) to be seen as an instance of the multi-dimensional bin-design problem. Using a novel quantification of coarse grain parallelism, we present a list scheduling heuristic algorithm that is provably near-optimal in the class of coarse grain parallel executions (with a worst-case performance ratio that depends on the number of resources per node and the granularity parameter). We then extend this algorithm to handle the operator precedence constraints in a bushy query plan by splitting the execution of the plan into synchronized phases. Preliminary performance results confirm the effectiveness of our scheduling algorithm compared both to previous approaches and the optimal solution. Finally, we present a technique that allows us to relax the coarse granularity restriction and obtain a list scheduling method that is provably near-optimal in the space of all possible parallel schedules.
Partitioning and reduction of RC interconnect networks based on scattering parameter macromodels
Authors: Haifang Liao, Wayne Wei-Ming Dai
Venue: Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design (1995)

This paper presents a linear time algorithm to reduce a large RC interconnect network into subnetworks which are approximated with lower order equivalent RC circuits. The number of RC elements can be reduced between 50% and 90%. Instead of increasing approximation order for a network with large number of ports which will result in inefficiency at best and ill-conditioned matrices at worst, we partition the original network into several subnetworks, each of which is approximated by lower order model. The reduced circuits are guaranteed to be stable. The experiment results show that the number of circuit elements in a reduced network is O(N) for typical clock networks, where N is the number of external ports. The simulation time can be reduced by two to three orders of magnitude while the response of the reduced circuits is within five percent of that of the original circuits.
Higher order objects in pure object-oriented languages
Authors: Thomas Kühne
Venue: ACM SIGPLAN OOPS Messenger (1995)

In this paper we present a method of directly translating higher order functions from functional programs into object-oriented programs. We show how to pass methods to generalized algorithms in pure object-oriented languages without extending the language. The translation allows partial parameterization, including currying, and conforms to strong typing. Finally we compare our method with conventional object-oriented approaches in terms of locality and reusability.