ppxscal/embedding_network huggingface dataset:
Power estimation for cycle-accurate functional descriptions of hardware
Authors: Lin Zhong, S. Ravi, A. Raghunathan, N. K. Jha
Venue: Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design (2004)

Cycle-accurate functional descriptions (CAFD) are being widely adopted in integrated circuit (IC) design flows. Power estimation can potentially benefit from the inherent increase in simulation efficiency of cycle-based functional simulation. Currently, most approaches to hardware power estimation operate at the register-transfer level (RTL), or lower levels of design abstraction. Attempts at power estimation for functional descriptions have suffered from poor accuracy because the design decisions performed during their synthesis lead to an unavoidable, large uncertainty in any power estimate that is based solely on the functional description. We propose a methodology for CAFD power estimation that combines the accuracy achieved by power estimation at the structural RTL with the efficiency of cycle-accurate functional simulation. We achieve this goal by viewing a CAFD as an abstraction of a specific, known RTL implementation that is synthesized from it. We identify correlations between a CAFD and its RTL implementation, and "back-annotate" information into the CAFD solely for the purpose of power estimation. The resulting RTL-aware CAFD contains a layer of code that instantiates virtual placeholders for RTL components, and maps values of CAFD variables into the RTL components' inputs/outputs, thus enabling efficient and accurate power estimation. Power estimation is performed in our methodology by simply co-simulating the RTL-aware CAFD with a simulatable power model library that contains power macro-models for each RTL component. We present techniques to further improve the speed of CAFD power estimation, through the use of control state-based adaptive power sampling. We have implemented and evaluated the proposed techniques in the context of a commercial C-based hardware design flow. Experiments with a number of large industrial designs (up to 1 million gates) demonstrate that the proposed methodology achieves accuracy very close to RTL power estimation with two-to-three orders of magnitude speedup in estimation times.
Automatically Maintaining Wrappers for Web Sources
Authors: Juan Raposo, Alberto Pan, Manuel Alvarez, Justo Hidalgo
Venue: Proceedings of the 9th International Database Engineering & Application Symposium (2005)

A substantial subset of the web data follows some kind of underlying structure. Nevertheless, HTML does not contain any schema or semantic information about the data it represents. A program able to provide software applications with a structured view of those semi-structured web sources is usually called a wrapper. Wrappers are able to accept a query against the source and return a set of structured results, thus enabling applications to access web data in a similar manner to that of information from databases. A significant problem in this approach arises because web sources may experiment changes that invalidate the current wrappers. In this paper, we present novel heuristics and algorithms to address this problem. Our approach is based on collecting some query results during wrapper operation. Then, when the source changes, they are used to generate a set of labeled examples that are then provided as input to a wrapper induction algorithm able to regenerate the wrapper. We have tested our methods in several real-world web data extraction domains, obtaining high accuracy in all the steps of the process.
Revisiting dictionary-based compression: Research Articles
Authors: Przemysław Skibiński, Szymon Grabowski, Sebastian Deorowicz
Venue: Software&mdash;Practice Experience (2005)

An attractive way to increase text compression is to replace words with references to a text dictionary given in advance. Although there exist a few works in this area, they do not fully exploit the compression possibilities or consider alternative preprocessing variants for various compressors in the latter phase. In this paper, we discuss several aspects of dictionary-based compression, including compact dictionary representation, and present a PPM&sol;BWCA-oriented scheme, word replacing transformation, achieving compression ratios higher by 2&ndash;6&percnt; than the state-of-the-art StarNT (2003) text preprocessor, working at a greater speed. We also present an alternative scheme designed for LZ77 compressors, with the advantage over StarNT of reaching up to 14&percnt; in combination with gzip. Copyright &copy; 2005 John Wiley & Sons, Ltd.
Linear Asymmetric Classifier for cascade detectors
Authors: Jianxin Wu, Matthew D. Mullin, James M. Rehg
Venue: Proceedings of the 22nd international conference on Machine learning (2005)

The detection of faces in images is fundamentally a rare event detection problem. Cascade classifiers provide an efficient computational solution, by leveraging the asymmetry in the distribution of faces vs. non-faces. Training a cascade classifier in turn requires a solution for the following subproblems: Design a classifier for each node in the cascade with very high detection rate but only moderate false positive rate. While there are a few strategies in the literature for indirectly addressing this asymmetric node learning goal, none of them are based on a satisfactory theoretical framework. We present a mathematical characterization of the node-learning problem and describe an effective closed form approximation to the optimal solution, which we call the Linear Asymmetric Classifier (LAC). We first use AdaBoost or AsymBoost to select features, and use LAC to learn a linear discriminant function to achieve the node learning goal. Experimental results on face detection show that LAC can improve the detection performance in comparison to standard methods. We also show that Fisher Discriminant Analysis on the features selected by AdaBoost yields better performance than AdaBoost itself.
The study on Common/Unique issues in PLM/CAD integration and a design of flexible integration architecture
Authors: Yubin Xia, Zhibin Yang, Li Zhang, Yinan Zhang, Liangyun Hu
Venue: Proceedings of the The Fifth International Conference on Computer and Information Technology (2005)

To adapt to vertiginous customer demands, fierce competition and innovation of production, modern enterprises require a flexible and open information integration platform. Based on a thorough study on Common/Unique issues in PLM/CAD integration, this paper presents a flexible and open PLM/CAD integration architecture. This architecture constructs distributed integration applications using Processor components, which overcomes shortcomings of traditional integration patterns. Then, key technologies related to realize PLM/CAD flexible integration are discussed in detail, such as Processor technology and two integration mechanisms, and finally, a case of PLM/CAD flexible integration is introduced. It improves flexibility, reusability and extensibility of integration systems and achieves seamless integrations between PLM and CAD systems more efficiently.
Passive TCP Stream Estimation of RTT and Jitter Parameters
Authors: Jason But, Urs Keller, Grenville Armitage
Venue: Proceedings of the The IEEE Conference on Local Computer Networks 30th Anniversary (2005)

There exist many tools to passively monitor a link for traffic flows. They are typically used near the edge of the network, but not necessarily at the termination point of data flows - usually within a few hops of endpoints. Round Trip Time (RTT) values for individual flows is of interest for network management purposes and can be used to indicate user experienced network delay, and in network design decisions. Determining the RTT when not at an end-point of a data flow is complicated by the fact that packets may be seen out of order and that witnessed packets may not reach their destination. In this paper we present an algorithm to estimate running RTT and Jitter characteristics of TCP streams monitored at the midpoint of a TCP flow.
3D Modeling with the Tinmith Mobile Outdoor Augmented Reality System
Authors: Wayne Piekarski
Venue: IEEE Computer Graphics and Applications (2006)

Researchers at the Wearable Computer Lab at the University of South Australia have been performing research into outdoor augmented reality (AR) systems for the last seven years. During this time the technology has vastly improved, resulting in more accurate systems that have better quality output. While tracking and registration are important issues in the area of AR, it's also important that we have suitable user interfaces that let people effectively view information and control the computer to get the desired output. Therefore, the Tinmith project explores the problem of interacting with a mobile AR system outdoors and the types of possible applications.
Definition of Protocols for Secure Anonymous Purchase
Authors: Borja Richart, Ramon Marti, Jaime Delgado, Abdul H. Sadka, Peter Sweeney
Venue: Proceedings of the Joint International Conference on Autonomic and Autonomous Systems and International Conference on Networking and Services (2005)

Digital watermarking is the art of hiding information in digital contents such as images, audio clips, and videos. We can take advantage of this technique by adding author information as well as buying information for a digital purchase. In this paper we propose a protocol for secure anonymous digital purchase to deter buyers from executing illegal redistribution of digital contents. We propose a protocol to allow merchants to obtain a proof of treachery from dishonest buyers.
Transparent Remote File Access in the Minimum Intrusion Grid
Authors: Rasmus Andersen, Brian Vinter
Venue: Proceedings of the 14th IEEE International Workshops on Enabling Technologies: Infrastructure for Collaborative Enterprise (2005)

This paper describes the implementation of a thin user-level layer to be installed on Grid resources. The layer fits in the Minimum intrusion Grid design by imposing as few requirements on the resource as possible and communicates with the server using only trusted and widely used protocols. The model offers transparent, on-demand remote file access. By catching all application operations on input files, these operations are directed towards the remote copy on the server, thus eliminating the need for transferring the complete input file. This implementation is targeted at the Minimum Intrusion Grid project, which strives for minimum intrusion on the resource executing a job. In "minimum intrusion" lies that a client need not install any dedicated Grid software, forcing the proposed model to use a user-level layer that automatically overrides GLIBC I/O calls.
Characterization of CDMA2000 Cellular Data Network Traffic
Authors: Carey Williamson, Emir Halepovic, Hongxia Sun, Yujing Wu
Venue: Proceedings of the The IEEE Conference on Local Computer Networks 30th Anniversary (2005)

This paper describes the analysis of low-level measurements from a CDMA2000 1x cellular data network. The network traces record detailed information about wireless Internet packet data call activity on the network, including mobile station identity, call initiation, burst behaviour, supplementary channel usage, soft handoffs, and call termination. The analysis in this paper focuses on one continuous week-long trace data set, representative of cellular data network activity. The results from the analysis illustrate the burstiness of the packet call arrival process and the diurnal patterns of cellular data users. The results also characterize the activity per cell site, activity per user, data burst activity, user mobility, and the density of cellular network coverage. Several observations reinforce known results about heavytailed properties in wired Internet traffic, while others show interesting differences in wireless versus wireline traffic.
On Generating Pseudo-Functional Delay Fault Tests for Scan Designs
Authors: Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz
Venue: Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (2005)

In designs using DFT such as scan some of the faults that are untestable in the circuit without DFT become testable after DFT insertion. Additionally, scan tests may scan in illegal or unreachable states that cause non-functional operation of the circuit during test. This may cause higher than normal power dissipation and demands on supply current. We propose new techniques to determine illegal states of circuits that can be used during ATPG to prohibit tests using such states. The resulting tests are essentially functional or pseudo-functional.
Operating Guidelines - an Automata-Theoretic Foundation for the Service-Oriented Architecture
Authors: Peter Massuthe, Karsten Schmidt
Venue: Proceedings of the Fifth International Conference on Quality Software (2005)

In the service-oriented architecture (SOA), we distinguish three roles of service owners: service providers, service requesters, and service brokers. Each service provider publishes information to the broker about how requesters can interact with its service. Thus, the broker can assign a fitting service provider to a querying requester. We propose the information published to the broker to be operating guidelines. Operating guidelines are essentially communication instructions for the service requester. We present an automata-theoretic approach that is centered around operating guidelines and is capable of implementing all tasks arising in the SOA.
A Self Checking Reed Solomon Encoder: Design and Analysis
Authors: G. C. Cardarilli, S. Pontarelli, M. Re, A. Salsano
Venue: Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (2005)

Reed Solomon codes are widely used to identify and correct data errors in transmission and storage systems. Due to the vital importance of these blocks, a very important research topic is the study of the effects of faults on their behavior. The presented architecture exploits some properties of the arithmetic operations on GF(2n) Galois Field, related to the parity of the binary representation of the elements of the field. The encoder has been mapped on an SRAM based FPGA, the self-checking property has been analyzed using a SEU fault model and the performances in terms of area and delay overhead are presented.
A Power Efficient Decoder for 2GHz, 6-bit CMOS Flash-ADC Architecture
Authors: Syed Masood Ali, Rabin Raut, Mohamad Sawan
Venue: Proceedings of the Fifth International Workshop on System-on-Chip for Real-Time Applications (2005)

The thermometer code to binary code (TC-to-BC) decoder is found to be one of the major limitations for flash type ADCs to perform satisfactorily for ultra high speed operations with minimum power dissipation. The authors propose a solution based on current mode approach to implement a Neural Network based Parallel ADC-decoder that is suitable for both system-on-chip and off-chip applications. The successful implementation is being presented for a 6-bit, 2GHz, with less than 19mW average power dissipation. The design was simulated using Cadence Spectre in a standard TSMC 0.18um technology.
Layered unequal loss protection with pre-interleaving for fast progressive image transmission over packet-loss channels
Authors: Jianfei Cai, Xiangjun Li, Chang Wen Chen
Venue: ACM Transactions on Multimedia Computing, Communications, and Applications (TOMCCAP) (2005)

Most existing unequal loss protection (ULP) schemes do not consider the minimum quality requirement and usually have high computation complexity. In this research, we propose a layered ULP (L-ULP) scheme to solve these problems. In particular, we use the rate-based optimal solution with a local search to find the average forward error correction (FEC) allocation and use the gradient search to find the FEC solution for each layer. Experimental results show that the executing time of L-ULP is much faster than the traditional ULP scheme but the average distortion is worse. Therefore, we further propose to combine the L-ULP with the pre-interleaving to have an improved L-ULP (IL-ULP) system. By using the pre-interleaving, we are able to delay the occurrence of the first unrecoverable loss in the source bitstream and thus improve the loss resilience performance. With the better loss resilience performance in the source bitstream, our proposed IL-ULP scheme is allowed to have a weaker FEC protection and allocate more bits to the source coding which leads to the improvement of overall performance. Experimental results show that our proposed IL-ULP scheme even outperforms the global optimal result obtained by any traditional ULP scheme while the complexity of IL-ULP is almost the same as L-ULP.
Low-Power Design Approach of 11FO4 256-Kbyte Embedded SRAM for the Synergistic Processor Element of a Cell Processor
Authors: Toru Asano, Joel Silberman, Sang H. Dhong, Osamu Takahashi, Michael White, Scott Cottier, Takaaki Nakazato, Atsushi Kawasumi, Hiroshi Yoshihara
Venue: IEEE Micro (2005)

The Synergistic Processor Element is a new architecture oriented for multimedia and streaming processing. In this architecture, the memory is not a cache but a private or scratch pad memory. Such a memory is simple and needs to be high-frequency and large space in low-power. This design uses an 11 fan-out of four (11F04), six-cycle, fully pipelined, embedded 256-Kbyte SRAM for this purpose. The design's memory is not one hard macro, but a group of custom macros physically distributed to optimize the pipeline.
Maintaining information in fully dynamic trees with top trees
Authors: Stephen Alstrup, Jacob Holm, Kristian De Lichtenberg Mikkel Thorup
Venue: ACM Transactions on Algorithms (TALG) (2005)

We design top trees as a new simpler interface for data structures maintaining information in a fully dynamic forest. We demonstrate how easy and versatile they are to use on a host of different applications. For example, we show how to maintain the diameter, center, and median of each tree in the forest. The forest can be updated by insertion and deletion of edges and by changes to vertex and edge weights. Each update is supported in O(log n) time, where n is the size of the tree(s) involved in the update. Also, we show how to support nearest common ancestor queries and level ancestor queries with respect to arbitrary roots in O(log n) time. Finally, with marked and unmarked vertices, we show how to compute distances to a nearest marked vertex. The latter has applications to approximate nearest marked vertex in general graphs, and thereby to static optimization problems over shortest path metrics.Technically speaking, top trees are easily implemented either with Frederickson's [1997a] topology trees or with Sleator and Tarjan's [1983] dynamic trees. However, we claim that the interface is simpler for many applications, and indeed our new bounds are quadratic improvements over previous bounds where they exist.
Flexible Couplings: Diffusing Neuromodulators and Adaptive Robotics
Authors: Andy Philippides, Phil Husbands, Tom Smith, Michael O'Shea
Venue: Artificial Life (2005)

Recent years have seen the discovery of freely diffusing gaseous neurotransmitters, such as nitric oxide (NO), in biological nervous systems. A type of artificial neural network (ANN) inspired by such gaseous signaling, the GasNet, has previously been shown to be more evolvable than traditional ANNs when used as an artificial nervous system in an evolutionary robotics setting, where evolvability means consistent speed to very good solutions &mdash; here, appropriate sensorimotor behavior-generating systems. We present two new versions of the GasNet, which take further inspiration from the properties of neuronal gaseous signaling. The plexus model is inspired by the extraordinary NO-producing cortical plexus structure of neural fibers and the properties of the diffusing NO signal it generates. The receptor model is inspired by the mediating action of eurotransmitter receptors. Both models are shown to significantly further improve evolvability. We describe a series of analyses suggesting that the reasons for the increase in evolvability are related to the flexible loose coupling of distinct signaling mechanisms, one "chemical" and one "electrical."
Integrating Database Technology with Comparison-based Parallel Performance Diagnosis: The PerfTrack Performance Experiment Management Tool
Authors: Karen L. Karavanic, John May, Kathryn Mohror, Brian Miller, Kevin Huck, Rashawn Knapp, Brian Pugh
Venue: Proceedings of the 2005 ACM/IEEE conference on Supercomputing (2005)

PerfTrack is a data store and interface for managing performance data from large-scale parallel applications. Data collected in different locations and formats can be compared and viewed in a single performance analysis session. The underlying data store used in PerfTrack is implemented with a database management system (DBMS). PerfTrack includes interfaces to the data store and scripts for automatically collecting data describing each experiment, such as build and platform details. We have implemented a prototype of PerfTrack that can use Oracle or PostgreSQL for the data store. We demonstrate the prototype's functionality with three case studies: one is a comparative study of an ASC purple benchmark on high-end Linux and AIX platforms; the second is a parameter study conducted at Lawrence Livermore National Laboratory (LLNL) on two high end platforms, a 128 node cluster of IBM Power 4 processors and BlueGene/L; the third demonstrates incorporating performance data from the Paradyn Parallel Performance Tool into an existing PerfTrack data store.
On flow-sensitive security types
Authors: Sebastian Hunt, David Sands
Venue: Conference record of the 33rd ACM SIGPLAN-SIGACT symposium on Principles of programming languages (2006)

This article investigates formal properties of a family of semantically sound flow-sensitive type systems for tracking information flow in simple While programs. The family is indexed by the choice of flow lattice.By choosing the flow lattice to be the powerset of program variables, we obtain a system which, in a very strong sense, subsumes all other systems in the family (in particular, for each program, it provides a principal typing from which all others may be inferred). This distinguished system is shown to be equivalent to, though more simply described than, Amtoft and Banerjee's Hoare-style independence logic (SAS'04).In general, some lattices are more expressive than others. Despite this, we show that no type system in the family can give better results for a given choice of lattice than the type system for that lattice itself.Finally, for any program typeable in one of these systems, we show how to construct an equivalent program which is typeable in a simple flow-insensitive system. We argue that this general approach could be useful in a proof-carrying-code setting.
Physical and Virtual Partitioning in OLAP Database Clusters
Authors: Camille Furtado, Alexandre A. B. Lima, Esther Pacitti, Patrick Valduriez, Marta Mattoso
Venue: Proceedings of the 17th International Symposium on Computer Architecture on High Performance Computing (2005)

On-line analytical processing (OLAP) applications require high performance database support to achieve good response time (crucial for decision making). Database clusters provide a cost-effective alternative to parallel database systems. For OLAP applications, that typically use heavy weight queries, intra-query parallelism yields better performance as it reduces the execution time of individual queries. Intra-query parallelism is based on processing the same query on different subsets of the query table. Combining physical and virtual partitioning to define table subsets provides flexibility in intra-query parallelism while optimizing disk space usage and data availability. Experiments with our partitioning technique using TPC-H benchmark queries on a 32-dual node cluster gave linear and super-linear speedup, thereby reducing significantly the time of typical OLAP heavy weight queries.