ppxscal/embedding_network huggingface dataset:
Mobile-Agent Coordination Models for Internet Applications
Authors: Giacomo Cabri, Letizia Leonardi, Franco Zambonelli
Venue: Computer (2000)

Internet applications face challenges that mobile agents and the adoption of enhanced coordination models may overcome. Each year more applications shift from intranets to the Internet, and Internet-oriented applications become more popular. New design and programming paradigms can help harness the Web's potential. Traditional distributed applications assign a set of processes to a given execution environment that, acting as local-resource managers, cooperate in a network- unaware fashion. In contrast, the mobile-agent paradigm defines applications as consisting of network-aware entities-agents-which can exhibit mobility by actively changing their execution environment, transferring themselves during execution. The authors propose a taxonomy of possible coordination models for mobile-agent applications, then use their taxonomy to survey and analyze recent mobile-agent coordination proposals. Their case study, which focuses on a Web-based information-retrieval application, helps show that the mobility of application components and the distribution area's breadth can create coordination problems different from those encountered in traditional distributed applications.
Strong Stability Preserving Properties of Runge&ndash;Kutta Time Discretization Methods for Linear Constant Coefficient Operators
Authors: Sigal Gottlieb, Lee-Ad J. Gottlieb
Venue: Journal of Scientific Computing (2003)

Strong stability preserving (SSP) high order Runge&ndash;Kutta time discretizations were developed for use with semi-discrete method of lines approximations of hyperbolic partial differential equations, and have proven useful in many other applications. These high order time discretization methods preserve the strong stability properties of first order explicit Euler time stepping. In this paper we analyze the SSP properties of Runge Kutta methods for the ordinary differential equation ut&equals;Lu where L is a linear operator. We present optimal SSP Runge&ndash;Kutta methods as well as a bound on the optimal timestep restriction. Furthermore, we extend the class of SSP Runge&ndash;Kutta methods for linear operators to include the case of time dependent boundary conditions, or a time dependent forcing term.
Fault Isolation in an Integrated Diagnostic Environment
Authors: William R. Simpson, John W. Sheppard
Venue: IEEE Design Test (1993)

The use of information flow models to conduct efficient fault isolation strategies is described. Of particular concern is optimizing diagnosis to minimize some objective cost function. A technique that can include multiple cost criteria such as test time, skill level, and failure frequency, as well as information value, is discussed.
A Parallel Algorithm for Reconfiguring a Multibutterfly Network with Faulty Switches
Authors: A. V. Goldberg, B. M. Maggs, S. A. Plotkin
Venue: IEEE Transactions on Computers (1994)

This paper describes a deterministic algorithm for reconfiguring a multibutterfly network with faulty switches. Unlike previous reconfiguration algorithms, the algorithm is performed entirely by the network, without the aid of any off-line computation, even though many of the switches may be faulty. The algorithm reconfigures an N-input multibutterfly network in O(logN) time. After reconfiguration, the multibutterfly can tolerate f worst-case faults and still route any permutation between some set of N/spl minus/O(f) inputs and N/spl minus/O(f) outputs in O(log N) time.
Total irredundance in graphs
Authors: Odile Favaron, Teresa W. Haynes, Stephen T. Hedetniemi, Michael A. Henning, Debra J. Knisley
Venue: Discrete Mathematics (2002)

A set S of vertices in a graph G is called a total irredundant set if, for each vertex υ in G, υ or one of its neighbors has no neighbor in S - {υ}. We investigate the minimum and maximum cardinalities of maximal total irredundant sets.
A Model for Software Practices from the Accounting Profession
Authors: Bryan Kocher
Venue: IEEE Software (2000)

The author opens by comparing Y2K-related problems with the US stock market crash of 1929. Just as regulations for the US accounting profession stemmed from the stock market crash, the author calls out for an Information Systems Standards Board, arguing that such an organization could have prevented Y2K-related problems--and could prevent such fiascos from occurring in the future.
A new algorithm for routing tree construction with buffer insertion and wire sizing under obstacle constraints
Authors: Xiaoping Tang, Ruiqi Tian, Hua Xiang, D. F. Wong
Venue: Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design (2001)

Buffer insertion and wire sizing are critical in deep submicron VLSI design. This paper studies the problem of constructing routing trees with simultaneous buffer insertion and wire sizing in the presence of routing and buffer obstacles. No previous algorithms consider all these factors simultaneously. Previous dynamic programming based algorithm is first extended to solve the problem. However, with the size of routing graph increasing and with wire sizing taken into account, the time and space requirement increases enormously. Then a new approach is proposed to formulate the problem as a series of graph problems. The routing tree solution is obtained by finding shortest paths in a series of graphs. In the new approach, wire sizing can be handled almost without any additional time and space requirement. Moreover, the time and space requirement is only polynomial in terms of the size of routing graph. Our algorithm differs from traditional dynamic programming, and is capable of addressing the problem of inverter insertion and sink polarity. Both theoretical and experimental results show that the graph-based algorithm outperforms the DP-based algorithm by a large margin. We also propose a hierarchical approach to construct routing tree for a large number of sinks.
The Path Integral Approach to Financial Modeling and Options Pricing
Authors: Vadim Linetsky
Venue: Computational Economics (1998)

In this paper we review some applications of the path integral methodology of quantum mechanics to financial modeling and options pricing. A path integral is defined as a limit of the sequence of finite-dimensional integrals, in a much the same way as the Riemannian integral is defined as a limit of the sequence of finite sums. The risk-neutral valuation formula for path-dependent options contingent upon multiple underlying assets admits an elegant representation in terms of path integrals (Feynman&ndash;Kac formula). The path integral representation of transition probability density (Green&lsquo;s function) explicitly satisfies the diffusion PDE. Gaussian path integrals admit a closed-form solution given by the Van Vleck formula. Analytical approximations are obtained by means of the semiclassical (moments) expansion. Difficult path integrals are computed by numerical procedures, such as Monte Carlo simulation or deterministic discretization schemes. Several examples of path-dependent options are treated to illustrate the theory (weighted Asian options, floating barrier options, and barrier options with ladder-like barriers).
Network Engineering for Agile Belief Network Models
Authors: Kathryn Blackmond Laskey, Suzanne M. Mahoney
Venue: IEEE Transactions on Knowledge and Data Engineering (2000)

The construction of a large, complex belief network model, like any major system development effort, requires a structured process to manage system design and development. This paper describes a belief network engineering process based on the spiral system lifecycle model. The problem of specifying numerical probability distributions for random variables in a belief network is best treated not in isolation, but within the broader context of the system development effort as a whole. Because structural assumptions determine which numerical probabilities or parameter values need to be specified, there is an interaction between specification of structure and parameters. Evaluation of successive prototypes serves to refine system requirements, ensure that modeling and elicitation effort are focused productively, and prioritize directions of enhancement and improvement for future prototypes. Explicit representation of semantic information associated with probability assessments facilitates tracing of the rationale for modeling decisions, as well as supporting maintenance and enhancement of the knowledge base.
MAGIC: A Multiattribute Declustering Mechanism for Multiprocessor Database Machines
Authors: S. Ghandeharizadeh, D. J. DeWitt
Venue: IEEE Transactions on Parallel and Distributed Systems (1994)

During the past decade, parallel database systems have gained increased popularity dueto their high performance, scalability, and availability characteristics. With the predictedfuture database sizes and complexity of queries, the scalability of these systems tohundreds and thousands of processors is essential for satisfying the projected demand.Several studies have repeatedly demonstrated that both the performance and scalabilityof a parallel database system are contingent on the physical layout of the data acrossthe processors of the system. If the data are not declustered appropriately, theexecution of an operation might waste system resources, reducing the overall processingcapability of the system. With earlier, single-attribute partitioning mechanisms such asthose found in the Tandem, Teradata, Gamma, and Bubba parallel database systems,range selections on any attribute other than the partitioning attribute must be sent to allprocessors containing tuples of the relation, while range selections on the partitioningattribute can be directed to only a subset of the processors. Although using all theprocessors for an operation is reasonable for resource intensive operations, directing aquery with minimal resource requirements to processors that contain no relevant tupleswastes CPU cycles, communication bandwidth, and I/O bandwidth. As a solution, thispaper describes a new partitioning strategy, multiattribute grid declustering (MAGIC),which can use two or more attributes of a relation to decluster its tuples across multipleprocessors and disks. In addition, MAGIC declustering, unlike other multiattributepartitioning mechanisms that have been proposed, is able to support range selections aswell as exact match selections on each of the partitioning attributes. This capabilityenables a greater variety of selection operations to be directed to a restricted subset ofthe processors in the system. Finally, MAGIC partitions each relation based on theresource requirements of the queries that constitute the workload for the relation and theprocessing capacity of the system in order to ensure that the proper number ofprocessors are used to execute queries that reference the relation.
Design and Self-Test for Switched-Current Building Blocks
Authors: Thomas Olbrich, Andrew Richardson
Venue: IEEE Design Test (1996)

Switched-current designs are receiving increasing interest within the VLSI community as the technique allowing analogue functions to be implemented on a digital process. In addition, switched-current designs tend to be robust and compatible with the trend for reduced supply voltages. This article describes the design of a novel type of switched-current memory cell with a built-in-self-test option. The cell is digitally controlled and can be used as a building block for a range of analogue functions. A divide-by-two circuit for reference signal generation in algorithmic A-to-D converters is given as an example application.Furthermore, two self-test approaches for these building blocks are described and their effectiveness evaluated. Over 3000 single faults have been simulated in HSPICE to obtain the fault coverage using an open/short fault model. The self-test functions are easy to apply, need only a very small overhead and result in fault coverages up to 95% for shorts and 60% for open-circuits.The analysis of undetected faults revealed that certain circuit structures used in the demonstrators which are common to analogue and mixed-signal designs are practically untestable.
On-Line Control and Deadlock-Avoidance in a Page-Parallel Multiprocessor Rasterizer
Authors: Y. Birk
Venue: IEEE Transactions on Parallel and Distributed Systems (1993)

A rasterizer converts a document described in some page-description language into asequence of full-page bitmaps (pagemaps), which can then be printed or displayed. Thepage-parallel rasterizer harnesses multiple processors to work on the same document,thereby permitting cost-effective high-speed rasterization of complex documents. Anygiven page is processed by a single processor, hence the name. For performance reasons,it is desirable to permit out-of-order rasterization as well as to share memory andcomputation results among the processors. However, this can result in deadlock. Onlinealgorithms are presented for controlling the rasterizer so as to avoid deadlock withoutbeing overly restrictive. It is shown that previously proposed approaches for deadlockavoidance cannot be applied directly due to a special form of nonexclusive allocation ofshared resources. A solution is given, thereby extending the applicability of deadlockavoidance. The approach should be useful in a variety of similar situations that may occurin other applications.
Volume Leases for Consistency in Large-Scale Systems
Authors: Jian Yin, Lorenzo Alvisi, Michael Dahlin, Calvin Lin
Venue: IEEE Transactions on Knowledge and Data Engineering (1999)

This article introduces volume leases as a mechanism for providing server-driven cache consistency for large-scale, geographically distributed networks. Volume leases retain the good performance, fault tolerance, and server scalability of the semantically weaker client-driven protocols that are now used on the web. Volume leases are a variation of object leases, which were originally designed for distributed file systems. However, whereas traditional object leases amortize overheads over long lease periods, volume leases exploit spatial locality to amortize overheads across multiple objects in a volume. This approach allows systems to maintain good write performance even in the presence of failures. Using trace-driven simulation, we compare three volume lease algorithms against four existing cache consistency algorithms and show that our new algorithms provide strong consistency while maintaining scalability and fault-tolerance. For a trace-based workload of web accesses, we find that volumes can reduce message traffic at servers by 40 percent compared to a standard lease algorithm, and that volumes can considerably reduce the peak load at servers when popular objects are modified.
Rational Coordination in Multi-Agent Environments
Authors: Piotr J. Gmytrasiewicz, Edmund H. Durfee
Venue: Autonomous Agents and Multi-Agent Systems (2000)

We adopt the decision-theoretic principle of expected utility maximization as a paradigm for designing autonomous rational agents, and present a framework that uses this paradigm to determine the choice of coordinated action. We endow an agent with a specialized representation that captures the agent's knowledge about the environment and about the other agents, including its knowledge about their states of knowledge, which can include what they know about the other agents, and so on. This reciprocity leads to a recursive nesting of models. Our framework puts forth a representation for the recursive models and, under the assumption that the nesting of models is finite, uses dynamic programming to solve this representation for the agent's rational choice of action. Using a decision-theoretic approach, our work addresses concerns of agent decision-making about coordinated action in unpredictable situations, without imposing upon agents pre-designed prescriptions, or protocols, about standard rules of interaction. We implemented our method in a number of domains and we show results of coordination among our automated agents, among human-controlled agents, and among our agents coordinating with human-controlled agents.
Applying an XC6200 to Real-Time Image Processing
Authors: Roger Woods, David Trainor, Jean-paul Heron
Venue: IEEE Design Test (1998)

This article presents a novel FPGA implementation of a two dimensional (8x8) point Discrete Cosine Transform. It is shown how the development of a suitable architectural style can produce high quality circuit designs for a specific technology, in this case the Xilinx XC6200 series of FPGA. Distributed arithmetic and exploitation of parallelism and pipelining are used to produce a DCT implementation on a single FPGA that operates at 25 frames per second with VGA resolution which is the equivalent of 2 Billion Multiplications or additions per second.
Bridging Rifts
Venue: IEEE Software (1990)

No abstract available The ACM Portal is published by the Association for Computing Machinery. Copyright © 2010 ACM, Inc. Terms of Usage Privacy Policy Code of Ethics Contact Us Useful downloads: Adobe Acrobat QuickTime Windows Media Player Real Player
Direct Recovery of Planar-Parallax from Multiple Frames
Authors: Michal Irani, P. Anandan, Meir Cohen
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (2002)

In this paper, we present an algorithm that estimates dense planar-parallax motion from multiple uncalibrated views of a 3D scene. This generalizes the "plane+parallax" recovery methods to more than two frames. The parallax motion of pixels across multiple frames (relative to a planar surface) is related to the 3D scene structure and the camera epipoles. The parallax field, the epipoles, and the 3D scene structure are estimated directly from image brightness variations across multiple frames, without precomputing correspondences.
VLSI, MCM, and WSI: A Design Comparison
Authors: Earl E. Swartzlander,  Jr.
Venue: IEEE Design Test (1998)

This article provides a quantitative comparison of VLSI, MCM and WSI on the basis of silicon area, substrate size and power consumption. These parameters are estimated and then calculated for two example processors: a stand-alone computer and a specialized DSP processor. For both examples, the MCM chips should cost the least in production, but they require the largest (and presumably the most expensive) package and will consume the most power.
Yet another approach to the extended ternary Golay code
Authors: Ales Drápal
Venue: Discrete Mathematics (2002)

A new proof of the uniqueness and of the existence of the extended ternary Golay code is presented. The proof connects the code to the projective plane of order 3 and is of an elementary nature.
Universal Fault Diagnosis for Lookup Table FPGAs
Authors: Tomoo Inoue, Satoshi Miyazaki, Hideo Fujiwara
Venue: IEEE Design Test (1998)

In this article, we introduce universal fault diagnosis such that when applied to an unprogrammed FPGA, it locates a fault in any faulty programmed FPGA corresponding to the unprogrammed FPGA. If a faulty part in an FPGA can be identified prior to programming it, we can implement a required logic function on the fault-free part by isolating the faulty part. Then, we propose a universal fault diagnosis procedure that locates a faulty CLB in a look-up table FPGA. The complexity of the universal diagnosis procedure for FPGAs with block-sliced loading is independent of its array size, i.e., C-diagnosable.
Making a Difference in the Schools
Authors: Tom DeMarco
Venue: IEEE Software (1990)

Schools represent a challenge for the software industry. Although diverting corporate resources to schools may appear to be folly in the short run, in the long run it is a strategy for survival. The author calls on programmers and their organizations to devote their time and services to schools at the primary and secondary levels. He describes some efforts already underway, and proposes a two-part plan for companies to follow. The first part is to lend some assistance in the computerization of the schools. The second part is to begin the introduction of salaried knowledge workers (their time contributed by the businesses that employ them) into the schools as individual tutors, teaching assistants, and aides.
SpeechActs: A Spoken-Language Framework
Authors: Paul Martin, Frederick Crabbe, Stuart Adams, Eric Baatz, Nicole Yankelovich
Venue: Computer (1996)

SpeechActs is a prototype testbed for developing spoken natural language applications. It lets software developers without special expertise in speech or natural language create applications with which users can speak naturally, as if they were conversing with a personal assistant. We believe we have achieved a degree of conversational naturalness similar to that of the outstanding Air Traffic Information Systems dialogues, and we have done so with simpler natural language techniques. Currently, SpeechActs supports a handful of speech recognizers: BBN's Hark, Texas Instruments' Dagger, and Nuance Communications' recognizers. These recognizers are all continuous--they accept normally spoken speech with no artificial pauses between words--and speaker-independent--they require no training by individual users. For output, the framework provides text-to-speech support for Centigram's TruVoice and AT&T's TrueTalk. As an existing set of applications, SpeechActs is both a proof of concept and an effective system that about a dozen people now depend upon when they travel. Powerful enough to be useful, it is easy to use with little training. As a framework for building speech applications, SpeechActs' contributions include a Unified Grammar to create synchronized grammars for speech recognition and semantic parsing, reusable plug-in speech components, and the Swiftus natural language processor. SpeechActs also includes important discourse management techniques. Both the discourse stack and a simple context queue in SpeechActs model the current state of the discourse so that SpeechActs can respond naturally. These simple, straightforward components combine to make SpeechActs a powerful framework in which to design speech applications.
Alpha 21164 Manufacturing Test Development and Coverage Analysis
Authors: Carol J. Stolicny, Richard Davies, Pamela McKernan, Tuyen Truong
Venue: IEEE Design Test (1998)

Today's competitive market demands high quality levels for electronic devices including state-of-the-art microprocessors. Unfortunately, the full-custom design methodology and performance constraints of the Alpha 21164, a deep sub-micron, superscalar microprocessor, precluded brute force use of design-for-test (DFT) techniques such as full-scan insertion and automated test pattern generation. In addition, scan testing alone cannot guarantee the desired quality level for microprocessors in this genre. As a result, functional tests play a key role in achieving the quality goals of the Alpha 21164.