ppxscal/embedding_network huggingface dataset:
An 8-bit 40 MS/s Pipeline A/D Converter for WCDMA Testbed
Authors: Lauri Sumanen, Mikko Waltari, Kari Halonen
Venue: Analog Integrated Circuits and Signal Processing (2000)

This paper describes an 8-bit 40 MS/s pipeline A/D converter suitable for WCDMA receiver applications. Small power consumption is achieved by using 1.5 bit/stage pipeline architecture and by scaling the capacitor values along the converter. Digital correction allows also to use very low power dynamic comparators. The multiplying D/A converters (MDACs) utilize a modified folded cascode amplifier. The circuit is designed and fabricated in a 0.5 &mu;m CMOS technology. The measured DNL is 0.85 LSB and INL 1.91 LSB. The converter achieves over 48 dBc SFDR and more than 41 dBc SNDR dissipating 61 mW from a 2.7 V supply.
KPPCDL: an Internet based shared environment for introductory programming education
Authors: Alfred J. Rossi
Venue: ACM SIGCSE Bulletin (1999)

The Karel++ Collaborative Laboratory is an Internet based educational tool, which facilitates the learning of Object-Oriented programming techniques, by providing a shared development environment for the building of student programs written in the Karel++ language. KPPCDL offers remote sharing of Karel++ program elements, collaborative source code editing, textual and graphical notification of both coarse and finely grained remote updates, remote and local views of developing program elements, updated views for late comers, background source parsing, and real-time memo sending. The system combines features of both centralized and replicated architectures, and provides for both synchronous and asynchronous collaboration.
Validating the ISO/IEC 15504 Measure of Software Requirements Analysis Process Capability
Authors: Khaled El Emam, Andreas Birk
Venue: IEEE Transactions on Software Engineering (2000)

ISO/IEC 15504 is an emerging international standard on software process assessment. It defines a number of software engineering processes and a scale for measuring their capability. One of the defined processes is software requirements analysis (SRA). A basic premise of the measurement scale is that higher process capability is associated with better project performance (i.e., predictive validity). This paper describes an empirical study that evaluates the predictive validity of SRA process capability. Assessments using ISO/IEC 15504 were conducted on 56 projects world-wide over a period of two years. Performance measures on each project were also collected using questionnaires, such as the ability to meet budget commitments and staff productivity. The results provide strong evidence of predictive validity for the SRA process capability measure used in ISO/IEC 15504, but only for organizations with more than 50 IT Staff. Specifically, a strong relationship was found between the implementation of requirements analysis practices as defined in ISO/IEC 15504 and the productivity of software projects. For smaller organizations, evidence of predictive validity was rather weak. This can be interpreted in a number of different ways: that the measure of capability is not suitable for small organizations or that the SRA process capability has less effect on project performance for small organizations.
Prediction Capabilities of Boolean and Stack Filters forLossless Image Compression
Authors: Doina Petrescu, Ioan Tabus, Moncef Gabbouj
Venue: Multidimensional Systems and Signal Processing (1999)

This paper proposes optimal Boolean, stack, and FIR-Boolean hybrid filters for realizing the prediction stage in lossless grey-level image compression. New optimal design procedures for Boolean filters are introduced, where the optimality criterion is the Error Entropy (EE). The use of the EE-optimal and MAE-optimal Boolean and stack filters in the sequential prediction structure is considered, under different instances: global-optimal, block-optimal, adaptive-size-block-optimal and multiresolution. An extensive simulation study is carried out for analyzing and comparing the performances of the newly introduced predictors and various other sequential predictors. The EE-optimal Boolean predictors prove to be the most efficient predictors. More refined filtering structures, such as block-optimal or adaptive-size-block-optimal are suitable for the prediction task when the prediction mask ought to be small. The proposed progressive transmission structure based on optimal Boolean prediction is shown to outperform HINT HINT progressive lossless coding scheme.
High Dynamic Range Design for &Sigma;&Delta;M with Wide Input Ranges
Authors: Hung-Chuan Pai, Steven B. Bibyk
Venue: Analog Integrated Circuits and Signal Processing (1999)

A new design algorithm is introduced to improve the input ranges of Sigma-Delta Modulation (&Sigma;&Delta;M). Modified digital error correction techniques are proposed and employed to carry out the wide range DAC of a &Sigma;&Delta; modulator. This design algorithm includes the advantages from both single-bit &Sigma;&Delta;M and multi-bit &Sigma;&Delta;M. This paper utilizes a second order lowpass &Sigma;&Delta; modulator as an explanatory example to demonstrate our design process as well as the performance improvement. The analytical results from a quasilinear model are described to offer a theoretical explanation of the system performance. This algorithm can also be applied to bandpass and MASH architectures.
Improved interconnect sharing by identity operation insertion
Authors: Dirk Herrmann, Rolf Ernst
Venue: Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design (1999)

This paper presents an approach to reduce interconnect cost by insertion of identity operations in a CDFG. Other than previous approaches, it is based on systematic pattern analysis and automated transformation selection. The cost function controlling transformation selection is derived with statistical experiments and is optimized using practical benchmarks. The results show significantly reduced interconnect cost for most register architectures and application examples.
Waveform Relaxation for Functional-Differential Equations
Authors: Barbara Zubik-Kowal, Stefan Vandewalle
Venue: SIAM Journal on Scientific Computing (1999)

The convergence of waveform relaxation techniques for solving functional-differential equations is studied. New error estimates are derived that hold under linear and nonlinear conditions for the right-hand side of the equation. Sharp error bounds are obtained under generalized time-dependent Lipschitz conditions. The convergence of the waveform method and the quality of the a priori error bounds are illustrated by means of extensive numerical data obtained by applying the method of lines to three partial functional-differential equations.
Information technology and the Internet: the Singapore experience
Authors: Tien Chia, Bu Sung Lee, Chai Kiat Yeo
Venue: Information Technology for Development (1998)

Singapore, a small nation with limited resources, has in three decades transformed itself from a British colony to one of the seven Asian economic tigers registering high economic growth. The borderless world of cyberspace has spawn a new digital global economy. To spur Singapore on to new economic growth, the government has identified information technology (IT) as the strategic tool. This paper presents the IT experience of Singapore in the 1980s and the latest IT plan (IT2000) for the 1990s and beyond to build a national information infrastructure (NII) to ensure Singapore&rsquo;s continuous growth in the future. The initiatives and incentives taken by the government to promote the use of the NII and snapshots of the progress of the NII deployment to date are discussed. In particular, the paper focuses on the evolution of Internet in Singapore&semi; it highlights its phenomenal growth and how this growth has spurred the development of an Internet infrastructure, Internet services and applications, and Internet-related policies. Internet has become an integral part and a key component of the NII and is hailed as the de facto mechanism for making the services of the NII available to the masses. It has accelerated the NII&rsquo;s development and deployment, despite the fact that it was never in the blueprint of IT2000. The paper concludes by examining the challenges faced in fulfilling the IT2000 vision and how Singapore can overcome the obstacles. With the strong IT infrastructure laid and the government&rsquo;s continuous support and commitment to IT development, it is well poised to harness existing and new technologies and effectively deploy them for economic growth and realisation of the IT2000 vision.
An Object-Oriented Toolbox for Spectral Element Analysis
Authors: Yves Dubois-Pelerin, Vincent Van Kemenade, Michel Deville
Venue: Journal of Scientific Computing (1999)

A common bottleneck for numericists is the complexity of the implementation programs. The usual procedural programming approach demands time and effort to program, develop, and test new formulations. This article addresses a particularly involved subject area, that of spectral element methods with mortars for large-scale applications. It is shown that the implementation burden can be alleviated by resorting to an object-oriented design approach. A toolbox consisting of a set of object-oriented classes is discussed. In order to solve a particular problem at hand, the user proceeds by creating an application where he/she loosely activates objects of the classes. When an operation exceeds the functionalities of the classes, the user can enrich these classes or create new ones. Practical examples are provided. Issues concerning computational efficiency and concurrent execution are addressed.
Computer Aided Verification of Lamport's Fast Mutual Exclusion Algorithm Using Colored Petri Nets and Occurrence Graphs with Symmetries
Authors: Jens Bæk Jørgensen, Lars Micheal Kristensen
Venue: IEEE Transactions on Parallel and Distributed Systems (1999)

In this paper, we present a computer tool for verification of distributed systems. As an example, we establish the correctness of Lamport's Fast Mutual Exclusion Algorithm. The tool implements the method of occurrence graphs with symmetries (OS-graphs) for Colored Petri Nets (CP-nets). The basic idea in the approach is to exploit the symmetries inherent in many distributed systems to construct a condensed state space. We demonstrate a significant increase in the number of states which can be analyzed. The paper is to a large extent self-contained and does not assume any prior knowledge of CP-nets (or any other kinds of Petri Nets) or OS-graphs. CP-nets and OS-graphs are not our invention. Our contribution is the development of the tool and verification of the example, demonstrating how the method of occurrence graphs with symmetries can be put into practice.
User performance in relation to 3D input device design
Authors: Shumin Zhai
Venue: ACM SIGGRAPH Computer Graphics (1998)

Based mainly on a series of studies the author conducted at the University of Toronto, this article reviews the usability of various six degrees of freedom (6 DOF) input devices for 3D user interfaces. The following issues are covered in the article: the multiple aspects of input device usability (performance measures), mouse based 6 DOF interaction, mouse modifications for 3D interfaces, free-moving isotonic 6 DOF devices, desktop isometric and elastic 6 DOF devices, armature-based 6 DOF devices, position vs. rate control and the form factors of 6 DOF control handle. These issues are treated at an introductory and practical level, with pointers to more technical and theoretical references.
Automatic Mapping of System of N-Dimensional Affine Recurrence Equations (SARE) onto Distributed Memory Parallel Systems
Authors: Alessandro Marongiu, Paolo Palazzari
Venue: IEEE Transactions on Software Engineering (2000)

Automatic extraction of parallelism from algorithms, and the consequent parallel code generation, is a challenging problem. In this work, we present a procedure for automatic parallel code generation in the case of algorithms described through Set of Affine Recurrence Equations (SARE); starting from the original SARE description in an N-dimensional iteration space, the algorithm is converted into a parallel code for an (eventually virtual) m-dimensional distributed memory parallel machine ($m
The content and access dynamics of a busy Web server (poster session)
Authors: Venkata N. Padmanabhan, Lili Qiu
Venue: Proceedings of the 2000 ACM SIGMETRICS international conference on Measurement and modeling of computer systems (2000)

We study the MSNBC Web site, one of the busiest in the Internet today. We analyze the dynamics of content creation and modification as well as client accesses. Our key findings are (a) files tend to change little upon modification, (b) a small set of files get modified repeatedly, (c) file popularity follows a Zipf-like distribution with an &agr; much larger than reported in previous, proxy-based studies, and (d) there is significant temporal stability in file popularity but not much stability in the domains from which popular content is accessed. We discuss implications of these findings.
The Midpoint Scheme and Variants for Hamiltonian Systems: Advantages and Pitfalls
Authors: Uri M. Ascher, Sebastian Reich
Venue: SIAM Journal on Scientific Computing (1999)

The (implicit) midpoint scheme, like higher-order Gauss-collocation schemes, is algebraically stable and symplectic, and it preserves quadratic integral invariants. It may appear particularly suitable for the numerical solution of highly oscillatory Hamiltonian systems, such as those arising in molecular dynamics or structural mechanics, because there is no stability restriction when it is applied to a simple harmonic oscillator. Although it is well known that the midpoint scheme may also exhibit instabilities in various stiff situations, one might still hope for good results when resonance-type instabilities are avoided.In this paper we investigate the suitability of the midpoint scheme for highly oscillatory, frictionless mechanical systems, where the step size k is much larger than the system's small parameter $\varepsilon$, in the case that the solution remains bounded as $\varepsilon \rightarrow 0$. We show that in general one must require that $k^2/\varepsilon$ be small enough or else even the errors in slowly varying quantities like the energy may grow undesirably (especially when fast and slow modes are tightly coupled) or, worse, the computation may yield misleading information. In some cases this may already happen when $k = O(\varepsilon )$. The same holds for higher-order collocation at Gaussian points. The encountered restrictions on k are typically still better than the corresponding ones for explicit schemes.
Local Oscillator Generation Circuit for Direct Conversion Transmitter
Authors: Jan Riska, Risto Kaunisto, Petteri Alinikula, Kari Halonen
Venue: Analog Integrated Circuits and Signal Processing (2000)

In this paper a fully monolithic on-chip local oscillator signal generation circuit is presented for eliminating the negative effect of coupling between bond-wires, package pins and output and input lines of the power amplifier output to the local oscillator input for direct conversion transmitters. The proposed circuit generates the local oscillator signal at frequencies 1710&ndash;1785 GHz which is harmonically uncorrelated from two input signals at 464 MHz and 1792&ndash;2088 MHz. The required building blocks are a frequency divider, a mixer and an active band-pass filter. Fully monolithic high frequency band-pass filters have not been available until recently, and the designed circuit is in fact one of the first applications reported for MMIC active filters in cellular phones. The circuit is designed with a 0.5 &mu;m GaAs MESFET technology and the performance is verified with on-chip measurements.
Impact of CC-NUMA Memory Management Policies on the Application Performance of Multistage Switching Networks
Authors: L. N. Bhuyan, H. Wang, R. Iyer
Venue: IEEE Transactions on Parallel and Distributed Systems (2000)

In this paper, the impact of memory management policies and switch design alternatives on the application performance of cache-coherent nonuniform memory access (CC-NUMA) multiprocessors is studied in detail. Memory management plays an important role in determining the performance of NUMA multiprocessors by dictating the placement of data among the distributed memory modules. We analyze memory traces of several scientific applications for three different memory management techniques, namely buddy, round-robin, and first-touch policies, and compare their memory system performance. Interconnection network switch designs that consider virtual channels and varying number of input buffers per switch are presented. Our performance evaluation is based on execution-driven simulation methodology to capture the dynamic changes in the network traffic during execution of the applications. It is shown that the use of cut-through switching with buffers and virtual channels can improve the average message latency tremendously. However, the choice of memory management policy affects the amount of network traffic and the network access pattern. Thus, we vary the memory management policy and confirm the performance benefits of improved switch designs. Results of sensitivity studies by varying switch design parameters, cache block size, and memory page size are also presented. We find that a combination of first-touch memory management policy and a switch design with virtual channels and increased buffer space can reduce the average message latency by as high as 70 percent.
On Homotopy-Smoothing Methods for Box-Constrained Variational Inequalities
Authors: Xiaojun Chen, Yinyu Ye
Venue: SIAM Journal on Control and Optimization (1999)

A variational inequality problem with a mapping $g:\Re^n \to \Re^n$ and lower and upper bounds on variables can be reformulated as a system of nonsmooth equations $F(x)=0$ in $\Re^n$. Recently, several homotopy methods, such as interior point and smoothing methods, have been employed to solve the problem. All of these methods use parametric functions and construct perturbed equations to approximate the problem. The solution to the perturbed system constitutes a smooth trajectory leading to the solution of the original variational inequality problem. The methods generate iterates to follow the trajectory. Among these methods Chen--Mangasarian and Gabriel--Mor&eacute; proposed a class of smooth functions to approximate $F$. In this paper, we study several properties of the trajectory defined by solutions of these smooth systems. We propose a homotopy-smoothing method for solving the variational inequality problem, and show that the method converges globally and superlinearly under mild conditions. Furthermore, if the involved function $g$ is an affine function, the method finds a solution of the problem in finite steps. Preliminary numerical results indicate that the method is promising.
IS &ldquo;maintainability&rdquo;: should it reduce the maintenance effort?
Authors: E. Burton Swanson
Venue: ACM SIGMIS Database (1999)

This paper reexamines information system (IS) maintainability and takes a new and inclusive view of it and its effects. It proposes that an IS is maintainable to the extent that its maintenance, operation, and use is economical in its use of resources. A model is offered which puts IS maintainability in the larger developmental context and suggests a number of related propositions. To the question of whether increased maintainability should reduce an organization's maintenance effort, a straightforward analysis leads to what, for some, may be a surprising answer. Where IS maintainability is enhanced, organizations can sometimes be better off by sustaining, not decreasing, their overall maintenance efforts.
Successive Approximations of Linear Control Models
Authors: John R. Birge, Samer Takriti
Venue: SIAM Journal on Control and Optimization (1999)

We present a technique for approximating sequences of linear programs with varying right-hand sides and study the geometric properties of this approximation. Our approximation has an efficiency advantage over optimal solutions. When applied to deterministic control problems, the suggested technique outperforms the linear feedback model and provides accurate results (error of 5.8% in our numerical example). Numerical experience with stochastic models indicates that this approach may outperform the limited lookahead policies while maintaining low computational requirements.
Is wire tapering worthwhile?
Authors: Charles J. Alpert, Anirudh Devgan, Stephen T. Quay
Venue: Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design (1999)

Wire sizing and buffer insertion/sizing are critical optimizations in deep submicron design. The past years have seen several studies of buffer insertion, wire sizing, and their simultaneous optimization. When wiring long interconnect, tapering, i.e., reducing the wire width as the distance from the driver increases, has proven effective. However, tapering is not widely utilized in industry since it is difficult to integrate into a complete routing methodology. This work examines the benefits of wire sizing with tapering when combined with buffer insertion. We perform several experiments with actual IBM technologies. Results indicate that wire tapering reduces delay typically by less than 5% compared to uniform wire sizing, when buffers can be inserted. Consequently, we suggest that it may not be worthwhile to maintain a routing methodology that supports wire tapering.
Very Low-Voltage Switched-Current Circuits in Standard Digital CMOS Process
Authors: Nianxiong Tan
Venue: Analog Integrated Circuits and Signal Processing (1999)

The inherent simplicity of switched-current circuits makes them suitable for low-voltage and very low voltage operation. This paper presents the design of 1.2-V switched-current circuits in a standard digital CMOS process. The core elements are the proposed fully differential SI memory cell and high resolution current quantizer. A delay line and a second-order delta-sigma modulator are implemented and measured. The delay line occupies an active chip area of 0.2 mm^2 and dissipates a power of 0.2 mW, and the modulator occupies an active chip area of 0.47 mm^2 and dissipates a power of 0.78 mW. The measured total harmonic distortion of the delay line is less than &minus;48 dB with a 60% input modulation index and the measured dynamic range of the modulator is 10 bits.
Buffer block planning for interconnect-driven floorplanning
Authors: Jason Cong, Tianming Kong, David Zhigang Pan
Venue: Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design (1999)

This paper studies buffer block planning for interconnect-driven floorplanning in deep submicron designs. We first introduce the concept of feasible region (FR) for buffer insertion, and derive closed-form formula for FR. We observe that the FR for a buffer is quite large in general even under fairly tight delay constraint. Therefore, FR gives us a lot of flexibility to plan for buffer locations. We then develop an effective buffer block planning (BBP) algorithm to perform buffer clustering such that the overall chip area and the buffer block number can be minimized. To the best of our knowledge, this is the first in-depth study on buffer planning for interconnect-driven floorplanning with both area and delay consideration.
CHI meets PLoP: an interaction patterns workshop
Authors: Jan O. Borchers
Venue: ACM SIGCHI Bulletin (2000)

This report summarizes the results of a workshop on pattern languages for human-computer interaction which took place at the ChiliPLoP'99 Conference on Pattern Languages of Programming.It suggests a definition and taxonomy for interaction patterns, explains how Writers' Workshops are used to improve patterns, and points out some surprising issues about pattern languages as they are understood by key players in that field. It shows the importance of user interface and software engineering researchers to exchange their thoughts on this hot topic.