ppxscal/embedding_network huggingface dataset:
Space/time trade-offs in hash coding with allowable errors
Authors: Burton H. Bloom
Venue: Communications of the ACM (1970)

In this paper trade-offs among certain computational factors in hash coding are analyzed. The paradigm problem considered is that of testing a series of messages one-by-one for membership in a given set of messages. Two new hash-coding methods are examined and compared with a particular conventional hash-coding method. The computational factors considered are the size of the hash area (space), the time required to identify a message as a nonmember of the given set (reject time), and an allowable error frequency. The new methods are intended to reduce the amount of space required to contain the hash-coded information from that associated with conventional methods. The reduction in space is accomplished by exploiting the possibility that a small fraction of errors of commission may be tolerable in some applications, in particular, applications in which a large amount of data is involved and a core resident hash area is consequently not feasible using conventional methods. In such applications, it is envisaged that overall performance could be improved by using a smaller core resident hash area in conjunction with the new methods and, when necessary, by using some secondary and perhaps time-consuming test to &ldquo;catch&rdquo; the small fraction of errors associated with the new methods. An example is discussed which illustrates possible areas of application for the new methods. Analysis of the paradigm problem demonstrates that allowing a small number of test messages to be falsely identified as members of the given set will permit a much smaller hash area to be used without increasing reject time.
An Orientation Reliability Matrix for the Iterative Closest Point Algorithm
Authors: Byung-Uk Lee, Chul-Min Kim, Rae-Hong Park
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (2000)

This paper proposes a matrix which represents the reliability of the rotation components of the iterative closest point (ICP) algorithm in range image registration. We show that the reliability of the ICP algorithm depends on the surface normal vectors of the object.
Participant stakeholder evaluation as a design process
Authors: Richard Giordano, David Bell
Venue: Proceedings on the 2000 conference on Universal Usability (2000)

This paper discusses participant stakeholder evaluation and its use in designing an evaluative protocol for inter-firm development and sharing of web-based learning modules. Participant stakeholder evaluation involves participants as researchers who design and evaluate evaluative protocols. It has a strong link with participatory action research and collaborative inquiry methods where the line is blurred between &ldquo;the researcher&rdquo; and &ldquo;the researched.&rdquo; Participatory evaluation methods were used as a method in support of system design to help define features of learning modules, define content, and to enhance usability and effectiveness in work contexts. Preliminary results strongly suggest that these techniques are successful in uncovering usability issues during the process of design, were instrumental in helping define an architecture for learning modules, help to increase user acceptance, and inform company strategy
Virtues and Problems of an Active Help System for UNIX
Authors: Maria Virvou, John Jones, Mark Millington
Venue: Artificial Intelligence Review (2000)

An empirical study undertaken on a cross-section of UNIX users at an academic site reveals a role for an active form of help system, rather than the more usual passive kind. Sample scripts supporting this view are presented and the kind of aid required for these examples is discussed. It is then proposed that to provide such aid requires the construction and maintenance of an individual model of each user.
The Odd-Even Turn Model for Adaptive Routing
Authors: Ge-Ming Chiu
Venue: IEEE Transactions on Parallel and Distributed Systems (2000)

This paper presents a model for designing adaptive wormhole routing algorithms for meshes without virtual channels. The model restricts the locations where some turns can be taken so that deadlock is avoided. In comparison with previous methods, the degree of routing adaptiveness provided by the model is more even for different source-destination pairs. The mesh network may benefit from this feature in terms of communication efficiency. Simulation results show that the even adaptiveness provided by the odd-even turn model makes message routing less vulnerable to nonuniform factors such as hot spot traffic. In addition, this property results in a smaller fluctuation of the network performance with respect to different traffic patterns.
A Continuation Method for a Right Definite Two-Parameter Eigenvalue Problem
Authors: Bor Plestenjak
Venue: SIAM Journal on Matrix Analysis and Applications (2000)

The continuation method has been successfully applied to the classical $Ax=\lambda x$ and to the generalized $Ax=\lambda Bx$ eigenvalue problems. Shimasaki applied the continuation method to the right definite two-parameter problem, which resulted in a discretization of a two-parameter Sturm--Liouville problem. We show that the continuation method can be used for a general right definite two-parameter problem and we give a sketch of the algorithm. For a local convergent method we use the tensor Rayleigh quotient iteration (TRQI), which is a generalization of the Rayleigh iterative method to two-parameter problems. We show its convergence and compare it with Newton's method and with the generalized Rayleigh quotient iteration (GRQI), studied by Ji, Jiang, and Lee.
A display system for the Stellar graphics supercomputer model GS1000
Authors: Brian Apgar, Bret Bersack, Abraham Mammen
Venue: Proceedings of the 15th annual conference on Computer graphics and interactive techniques (1988)

This paper describes a high performance display system that has been incorporated into the overall architecture of the Stellar Graphics Supercomputer Model GS1000. The display system is tightly coupled to the CPU, memory system and vector processing unit of this supercomputer, and is capable of rendering 150,000 shaded triangles/sec, and 600,000 short vectors/sec. The goal of the architecture is to share hardware resources between the CPU and display system and achieve a high bandwidth connection between them. This coupling of the display system and the processor, the architecture of the rendering processor, and the two ASICs that are used to implement the rendering processor are described.In addition, the display system architecture is contrasted to other approaches to high performance graphics, and design trade-offs and possible extensions are described. The implementation of popular display algorithms on the architecture is discussed, and their performance specified. The reader is advised that Stellar Computer Inc. is seeking patent protection for work described in this paper.
A computer generated aid for cluster analysis
Authors: Robert L. Ling
Venue: Communications of the ACM (1973)

A computer generated graphic method, which can be used in conjunction with any hierarchical scheme of cluster analysis, is described and illustrated. The graphic principle used is the representation of the elements of a data matrix of similarities or dissimilarities by computer printed symbols (of character overstrikes) of various shades of darkness, where a dark symbol corresponds to a small dissimilarity. The plots, applied to a data matrix before clustering and to the rearranged matrix after clustering, show at a glance whether clustering brought forth any distinctive clusters. A well-known set of data consisting of the correlations of 24 psychological tests is used to illustrate the comparison of groupings by four methods of factor analysis and two methods of cluster analysis.
Buffer minimization in pass transistor logic
Authors: H. Zhou, A. Aziz
Venue: Proceedings of the 2000 international conference on Computer-aided design (2001)

With the shrinking feature sizes and increasing transistor counts on chips, the push for higher speed and lower power makes it necessary to look for alternative design styles which offer better performance characteristics than static CMOS. Among them, pass transistor logic (PTL) circuits give great promise. Since the delay in a pass-transistor chain is quadratically proportional to the number of stages, and a signal may degenerate when passing through a transistor, buffers are necessary to guarantee performance and restore signal strength in PTL circuits. In this paper, we first analyze the effects of buffer insertion on a circuit and give the sufficient and necessary condition for safe buffer insertion. Then the buffer minimization problem is formulated, which asks for a minimum number of buffers to make sure that no path has length longer than a given upper bound. Although NP-hard in general, we show that, when buffers are required on multiple fan-outs, it can be solved linearly. We also consider the case when buffers are inverters, where phase assignment are done on MCNC logic synthesis and optimization benchmarks; compared with a level-by-level insertion,a large number of buffers are saved.
The external auditor's review of computer controls
Authors: Charles R. Litecky, Larry E. Rittenberg
Venue: Communications of the ACM (1981)

The Foreign Corrupt Practices Act of 1977, coupled with growing demands for corporate accountability, have forced both auditors and computer administrators to evaluate computer based controls. Computer administrators can benefit from both a knowledge of an auditor's approaches to evaluating controls and his/her recommendations for control improvements. Here, a survey of the control evaluation practices and desirable control features identified by computer auditors is presented, along with recommendations to ease the burden of the auditor's review. The authors' suggestions should ease the tasks of internal control analysis and of preparation for possible public reports on an organization's system of internal control.
Reprogrammable network packet processing on the field programmable port extender (FPX)
Authors: John W. Lockwood, Naji Naufel, Jon S. Turner, David E. Taylor
Venue: Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays (2001)

A prototype platform has been developed that allows processing of packets at the edge of a multi-gigabit-per-second network switch. This system, the Field Programmable Port Extender (FPX), enables packet processing functions to be implemented as modular components in reprogrammable hardware. All logic on the on the FPX is implemented in two Field Programmable Gate Arrays (FPGAs). Packet processing functions in the system are implemented as dynamically-loadable modules.Core functionality of the FPX is implemented on an FPGA called the Networking Interface Device (NID). The NID contains the logic to transmit and receive packets over a network, dynamically reprogram hardware modules, and route individual traffic flows. A full, non-blocking, switch is implemented on the NID to route packets between the networking interfaces and the modular components. Modular components of the FPX are implemented on a second FPGA called the Reprogrammable Application Device (RAD). Modules are loaded onto the RAD via reconfiguration and/or partial partial reconfiguration of the FPGA.Through the combination of the NID and the RAD, the FPX can individually reconfigure the packet processing functionality for one set of traffic flows, while the rest of the system continues to operate. The platform simplifies the development and deployment of new hardware-accelerated packet processing circuits. The modular nature of the system allows an active router to migrate functionality from softare plugins to hardware modules.
Mixed Partitions of Projective Geometries
Authors: Arrigo Bonisoli, Antonio Cossidente
Venue: Designs, Codes and Cryptography (2000)

Starting from a linear collineation of \PG(2n-1,q) suitably constructed from a Singer cycle of \GL(n,q), we prove the existence of a partition of \PG(2n-1,q) consisting of two (n-1)-subspaces and caps, all having size (q^n-1)/(q-1) or (q^n-1)/(q+1) according as n is odd or even respectively. Similar partitions of quadrics or hermitian varieties into two maximal totally isotropic subspaces and caps of equal size are also obtained. We finally consider the possibility of partitioning the Segre variety {\cal S}_{2,2} of \PG(8,q) into caps of size q^2+q+1 which are Veronese surfaces.
Experimental personalized array translator system
Authors: H. Hellerman
Venue: Communications of the ACM (1964)

A system designed for intimate man-machine interaction in a general-purpose problem-solving environment is experimentally operational. The system utilizes an array-oriented symbolic source language containing powerful statement types. These include numeric, Boolean, relational and selection operators on operands which can be entire arrays. The system also permits simple specification of test and argument arrays in single statements. The completely symbolic operating system includes display and entry of program and data. Sequence control is aided by an interrupt switch which allows the user to interact with the program during execution. In addition to normal stored program sequencing, the system provides trace options and the ability to enter any statement for immediate execution. Present implementation of the system is with an interpretive translator on an IBM 1620 computer.
Parametric polymorphism in Java: an approach to translation based on reflective features
Authors: Mirko Viroli, Antonio Natali
Venue: Proceedings of the 15th ACM SIGPLAN conference on Object-oriented programming, systems, languages, and applications (2000)

The introduction of parametric polymorphism in Java with translation approaches has been shown to be of considerable interest, allowing the definition of extensions of Java on top of the existing Virtual Machines. Homogeneous translations furthermore, seem to be more useful than heterogeneous, avoiding the continuous increase of library code with redundant information. At this time however, homogeneous approaches aren't as flexible as heterogeneous, with extensions failing to integrate well with base language typing. In this paper, using some of the features of the Core Reflection of Java, we introduce a homogeneous translation in which run-time information about instantiation of type-parameters is carried, allowing full integration of parame-terized types with Java typing. Performance overhead is greatly decreased using a brand new translation technique based on the deferring of the management of type information at load-time. The same power and flexibility of previous heterogeneous approaches is obtained while maintaining homogeneous translation advantages.
Symbiotic jobscheduling for a simultaneous mutlithreading processor
Authors: Allan Snavely, Dean M. Tullsen
Venue: ACM SIGPLAN Notices (2000)

Simultaneous Multithreading machines fetch and execute instructions from multiple instruction streams to increase system utilization and speedup the execution of jobs. When there are more jobs in the system than there is hardware to support simultaneous execution, the operating system scheduler must choose the set of jobs to coscheduleThis paper demonstrates that performance on a hardware multithreaded processor is sensitive to the set of jobs that are coscheduled by the operating system jobscheduler. Thus, the full benefits of SMT hardware can only be achieved if the scheduler is aware of thread interactions. Here, a mechanism is presented that allows the scheduler to significantly raise the performance of SMT architectures. This is done without any advance knowledge of a workload's characteristics, using sampling to identify jobs which run well together.We demonstrate an SMT jobscheduler called SOS. SOS combines an overhead-free sample phase which collects information about various possible schedules, and a symbiosis phase which uses that information to predict which schedule will provide the best performance. We show that a small sample of the possible schedules is sufficient to identify a good schedule quickly. On a system with random job arrivals and departures, response time is improved as much as 17% over a schedule which does not incorporate symbiosis.
Computing the nxm shortest path efficiently
Authors: Tetsuo Shibuya
Venue: Journal of Experimental Algorithmics (JEA) (2000)

Computation of all the shortest paths between multiple sources and multiple destinations on various networks is required in many problems, such as the traveling salesperson problem (TSP) and the vehicle routing problem (VRP). This paper proposes new algorithms that compute the set of shortest paths efficiently by using the A<sup>*</sup> algorithm. The efficiency and properties of these algorithms are examined by using the results of experiments on an actual road network.
Improving Goldschmidt Division, Square Root, and Square Root Reciprocal
Authors: Milos D. Ercegovac, Laurent Imbert, David W. Matula, Jean-Michel Muller, Guoheng Wei
Venue: IEEE Transactions on Computers (2000)

The aim of this paper is to accelerate division, square root, and square root reciprocal computations when the Goldschmidt method is used on a pipelined multiplier. This is done by replacing the last iteration by the addition of a correcting term that can be looked up during the early iterations. We describe several variants of the Goldschmidt algorithm, assuming 4-cycle pipelined multiplier, and discuss obtained number of cycles and error achieved. Extensions to other than 4-cycle multipliers are given. If we call $G_m$ the Goldschmidt algorithm with $m$ iterations, our variants allow us to reach an accuracy that is between that of $G_3$ and that of $G_4$, with a number of cycle equal to that of $G_3$.
Conversion of limited-entry decision tables to computer programs&mdash;a proposed modification to Pollack's algorithm
Authors: Keith Shwayder
Venue: Communications of the ACM (1971)

Pollack has proposed an algorithm for converting decision tables into flowcharts which minimize subsequent execution time when compiled into a computer program. Two modifications o this algorithm are proposed. The first relies on Shannon's noiseless coding theorem and the communications concept of entropy but does not completely test the ELSE Rule. The second modification completely tests the ELSE Rule but results in more executions than the first modification. Both modifications result in lower execution time than Pollack's algorithm. However, neither modification guarantees a globally optimal solution.
An O(n) algorithm for determining a near-optimal computation order of matrix chain products
Authors: Francis Y. Chin
Venue: Communications of the ACM (1978)

This paper discusses the computation of matrix chain products of the form M1 &times; M22 &times; &middot;&middot;&middot; &times; Mn where Mi's are matrices. The order in which the matrices are computed affects the number of operations. A sufficient condition about the association of the matrices in the optimal order is presented. An O(n) algorithm to find an order of computation which takes less than 25 percent longer than the optimal time Topt is also presented. In most cases, the algorithm yields the optimal order or an order which takes only a few percent longer than Topt (less than 1 percent on the average).
A note on sub-expression ordering in the execution of arithmetic expressions
Authors: Peter J. Denning, G. Scott Graham
Venue: Communications of the ACM (1973)

A counterexample to the supposed optimality of an algorithm for generating schedules for trees of tasks with unequal execution times is presented. A comparison with the &ldquo;critical path&rdquo; heuristic is discussed.
Computer system design using a hierarchical approach to performance evaluation
Authors: B. Kumar, E. S. Davidson
Venue: Communications of the ACM (1980)

The concept of a hierarchy of performance models is introduced. It is argued that such a hierarchy should consist of models spanning a wide range of accuracy and cost in order to be a cost-effective tool in the design of computer systems. Judicious use of the hierarchy can satisfy the conflicting needs of high accuracy and low cost of performance evaluation. A system design procedure that uses the hierarchy is developed. The concepts developed are illustrated by applying them to a case study of system design. The results of optimizations conducted using a two-level performance model hierarchy and a simple cost model are discussed. In almost all the experiments conducted, the optimization procedure converged to a region very close to a locally optimum system. The efficiency of the procedure is shown to be considerably greater than that of the brute force approach to system design.
Novel Voltage-Tunable, Low-Voltage Linear CMOS Transconductor
Authors: W. H. Lai, X. W. Zhang, M. F. Li
Venue: Analog Integrated Circuits and Signal Processing (2000)

A novel voltage-tunable, low-voltage linear CMOS transconductor design is described. The design is based on the improvement of the cross-coupled pairs. SPICE simulation results show that using BSIM models, MOSIS 2-&mu;m n-well process parameters and a power supply of &plusmn;2.5 V, the linearity error is less than 0.4% over a differential input voltage range of &plusmn;1.2 V. The THD for a differential input voltage of 1\,\hbox {\it V}_{\it {pp}} at 1 kHz is 1.3%.
Database nation: the death of privacy in the 21st century
Authors: Simson Garfinkel
Venue:  (2001)

Fifty years ago, in 1984, George Orwell imagined a future in which privacy was demolished by a totalitarian state that used spies, video surveillance, historical revisionism, and control over the media to maintain its power. Those who worry about personal privacy and identity--especially in this day of technologies that encroach upon these rights--still use Orwell's "Big Brother" language to discuss privacy issues. But the reality is that the age of a monolithic Big Brother is over. And yet the threats are perhaps even more likely to destroy the rights we've assumed were ours. Database Nation: The Death of Privacy in the 21st Century shows how, in these early years of the 21st century, advances in technology endanger our privacy in ways never before imagined. Direct marketers and retailers track our every purchase; surveillance cameras observe our movements; mobile phones will soon report our location to those who want to track us; government eavesdroppers listen in on private communications; misused medical records turn our bodies and our histories against us; and linked databases assemble detailed consumer profiles used to predict and influence our behavior. Privacy--the most basic of our civil rights--is in grave peril. Simson Garfinkel--journalist, entrepreneur, and international authority on computer security--has devoted his career to testing new technologies and warning about their implications. This newly revised update of the popular hardcover edition of Database Nation is his compelling account of how invasive technologies will affect our lives in the coming years. It's a timely, far-reaching, entertaining, and thought-provoking look at the serious threats to privacy facing us today. The book poses a disturbing question: how can we protect our basic rights to privacy, identity, and autonomy when technology is making invasion and control easier than ever before? Garfinkel's captivating blend of journalism, storytelling, and futurism is a call to arms. It will frighten, entertain, and ultimately convince us that we must take action now to protect our privacy and identity before it's too late.