ppxscal/embedding_network huggingface dataset:
Bridging the Gap Between Object-Oriented and Logic Programming
Authors: Timothy Koschmann, Martha Walton Evens
Venue: IEEE Software (1988)

A description is given of an interface that was developed between Loops and Xerox Quintus Prolog. Loops is an extension to the Xerox AI environment to support object-oriented programming; Xerox Quintus Prolog is a version of Prolog that runs on Xerox Lisp machines. Such a bridge enables all the support tools of both environments to be accessed, and degradation of performance that occurs when one language is implemented top of another is avoided. The interface has three layers. At the lowest level, a set of Prolog predicates gives the Prolog programmer access to Loops objects. This lowest level is the bridge from Prolog to Loops. At the next level, programming tools in the Loops environment let object methods be defined in Prolog. At the highest level, the Prolog programmer can treat Prolog clauses as Loops objects that can be manipulated outside the Prolog database. Each layer can be used independently.
A scalable parallel algorithm for sparse Cholesky factorization
Authors: Anshul Gupta, Vipin Kumar
Venue: Proceedings of the 1994 ACM/IEEE conference on Supercomputing (1994)

In this paper, we describe a scalable parallel algorithm for sparse Cholesky factorization, analyze its performance and scalability, and present experimental results of its implementation on a 1024-processor nCUBE2 parallel computer. Through our analysis and experimental results, we demonstrate that our algorithm improves the state of the art in parallel direct solution of sparse linear systems by an order of magnitude--both in terms of speedups and the number of processors that can be utilized effectively for a given problem size. This algorithm incurs strictly less communication overhead and is more scalable than any known parallel formulation of sparse matrix factorization. We show that our algorithm is optimally scalable on hypercube and mesh architectures and that its asymptotic scalability is the same as that of dense matrix factorization for a wide class of sparse linear systems, including those arising in all two- and three- dimensional finite element problems.
Using At-Speed BIST to Test LVDS Serializer/Deserializer Function
Authors: Magnus Eckersand, Fredrik Franzon, Ken Filliter
Venue: Journal of Electronic Testing: Theory and Applications (2002)

LVDS is the acronym for Low-Voltage-Differential-Signaling and is described in both the ANSI/TIA/EIA-644 and IEEE 1596.3 standards. High performance yet Low Power and EMI have made LVDS a popular choice for high-speed card-to-card serial links. A typical application is the serializer/deserializer (ser/des) function where wide TTL datastreams including clock is converted to a serial LVDS bit stream, sent over a cable, and deserialization and clock recovery performed on the receiving card. This is a powerful design technique but presents interesting challenges from a testability perspective. First, LVDS links have a much different fault spectrum than the well-established stuck-at models used for TTL logic levels. The LVDS interconnect is a transmission line model, where the signal carrying integrity of the cable, fault models and fault detection are very frequency dependent. In addition, the Ser/Des function with clock recovery requires the two devices to achieve synchronization, so efforts to test the link and ser/des functionality must meet the timing requirements of the internal logic. Ideally, any built-in-test capability for the link should be accessible via the JTAG port to take advantage of the existing industry tools and infrastructure.This paper describes a JTAG activated at-speed BIST technique used to test a high-speed ser/des chip set and cable.
Is the Patent Office Correctly Examining Computer-Related Patent Applications? 1
Venue: Computer (1994)

Computer industry critics complain that the Patent Office is not shouldering its share of the burden and may even be granting patents it knows are invalid. One frequent criticism is that the Patent Office is granting broad or powerful patents because it is unable to properly assess the merits of an invention in view of previously patented work, that is, prior-art developments. The ACM Portal is published by the Association for Computing Machinery. Copyright © 2010 ACM, Inc. Terms of Usage Privacy Policy Code of Ethics Contact Us Useful downloads: Adobe Acrobat QuickTime Windows Media Player Real Player
Auditing Causal Relationships of Group Multicast Communications in Group-Oriented Distributed Systems
Authors: Woei-Jiunn Tsaur, Shi-Jinn Horng
Venue: The Journal of Supercomputing (2001)

Auditability is a crucial aspect of distributed computing security. In a distributed computation environment, we may therefore want to prevent corrupt processes from denying or forging causal relationships between events. The audit of causal relationships of group multicast communications is an important component in achieving a solution to the problem of group-oriented distributed computing security. In this paper, a new approach to audit causal relationships of group multicast communications in group-oriented distributed systems is proposed. The goal of the auditing service is to collect, maintain, make available, and validate irrefutable evidence regarding causal relationships in group-oriented distributed systems. We affirm that the denial of existing causal relationships and the forgery of nonexistent causal relationships in group-oriented distributed systems can be correctly audited by our proposed approach. Also, auditing the causal delivery ordering for group multicast communications can actually be achieved. Moreover, we have validated the proposed auditing scheme to a moderately complex example. Experience indicates that the proposed scheme is indeed very useful.
Designing Circuits with Partial Scan
Authors: Vishiwani D. Agrawal, Kwang-Ting Cheng, Daniel D. Johnson, Tony Sheng Lin
Venue: IEEE Design Test (1988)

In this scan design methodology, only selected faults are targeted for detection. These faults are those not detected by the designer's functional vectors. The test generator decides exactly which flip-flops should be scanned using one of two methods. In the first method, all possible tests are generated for each target fault, and the set of tests requiring the fewest flip-flops is selected. In the second method, only one test is generated for each fault, and the use of flip-flops is avoided as much as possible during test generation. Examples of actual VLSI circuits show a savings of at least a 40% in full-scan overhead.
Interactive spectral volume rendering
Authors: Steven Bergner, Torsten Möller, Mark S. Drew, Graham D. Finlayson
Venue: Proceedings of the conference on Visualization '02 (2002)

We describe a method for volume rendering using a spectral representation of colour instead of the traditional RGB model. It is shown how to use this framework for a novel exploration of datasets through enhanced transfer function design. Furthermore, our framework is extended to allow real-time re-lighting of the scene created with any rendering method. The technique of post-illumination is introduced to generate new spectral images for arbitrary light colours in real-time. Also a tool is described to design a palette of lights and materials having certain properties such as selective metamerism or colour constancy. Applied to spectral transfer functions, different light colours can accentuate or hide specific qualities of the data. In connection with post-illumination this provides a new degree of freedom for guided exploration of volumetric data, which cannot be achieved using the RGB model.
Exact travel time calculations for simple three-dimensional earth models in seismic exploration using computer algebra
Authors: B. M. Hartley
Venue: Computers Geosciences (2002)

In this paper we have used computer algebra to trace rays through relatively simple three-dimensional models applicable to seismic exploration and have calculated travel times of the rays for given values of ray source to receiver spacing. Using standard techniques, analytical expressions which give travel time in terms of source receiver spacing or offset can only be derived for a single layer or where non-physical assumptions are made. The symbolic mathematics system, Maple, is used to generate parametric equations which give offset and travel time as analytical expressions with the parametric variable being the initial direction cosines of the ray as it leaves the source. These equations contain symbolic constants such as interval velocities and layer dips and depths which define the layering of the model. The parametric equations may be solved after assigning numerical values to the model parameters, using the internal functionality of Maple. Faster solutions can be obtained by exporting the parametric equations as C subroutines and using a fast numerical method. In order to make the solution to the equations rapid, some elements of the Jacobian matrix, being the derivatives of the ray position with respect to the initial direction cosines are also calculated as analytical expressions and output as C subroutines by Maple. These are used in a 3D Newton's method to converge rapidly to a solution which gives the initial direction cosines for a given value of offset. The direction cosines are substituted into the subroutine derived from the analytical expression for travel time. The subroutines for each ray path are used in separate programs and the solutions for each ray path and the construction of shot records and CMP gathers are managed through a simple graphics interface. Solutions for the travel times are fast and inherently accurate, limited only by computer precision. Current limitations of computer power confine the solutions to a model comprising three layers with different velocities and dips but a number of complex ray paths can be traced including surface multiple reflections, and peg-leg and inter-bed multiples.
MediaWorm: A QoS Capable Router Architecture for Clusters
Authors: Ki Hwan Yum, Eun Jung Kim, Chita R. Das, Aniruddha S. Vaidya
Venue: IEEE Transactions on Parallel and Distributed Systems (2002)

With the increasing use of clusters in real-time applications, it has become essential to design high-performance networks with Quality-of-Service (QoS) guarantees. In this paper, we explore the feasibility of providing QoS in wormhole switched routers, which are widely used in designing scalable, high-performance cluster interconnects. In particular, we are interested in supporting multimedia video streams with CBR and VBR traffic, in addition to the conventional best-effort traffic. The proposed MediaWorm router uses a rate-based bandwidth allocation mechanism, called Fine-Grained VirtualClock (FGVC), to schedule network resources for different traffic classes. Our simulation results on an 8-port router indicate that it is possible to provide jitter-free delivery to VBR/CBR traffic up to an input load of 70-80 percent of link bandwidth and the presence of best-effort traffic has no adverse effect on real-time traffic. Although the MediaWorm router shows a slightly lower performance than a pipelined circuit switched (PCS) router, commercial success of wormhole switching, coupled with simpler and cheaper design, makes it an attractive alternative. Simulation of a (\big. 2 \times 2\bigr.) fat-mesh using this router shows performance comparable to that of a single switch and suggests that clusters designed with appropriate bandwidth balance between links can provide required performance for different types of traffic.
Intelligent-Memory Architecture for Artificial Neural Networks
Authors: Jürgen Büddefeld, Karl E. Grosspietsch
Venue: IEEE Micro (2002)

Execution of artificial neural networks, especially for online pattern recognition, mainly depends on time-efficient execution of weighted sums. A new architecture achieves this goal, with a computation time superior to the time complexity of sequential von neumann machines. This architecture uses additional logic to extend the functionality of conventional ram. The authors discuss an implementation of this architecture that uses reconfigurable logic.
Software Fault Tolerance in Architectures with Hierarchical Protection Levels
Authors: Brenda M. Ozaki, Eduardo B. Fernandez, Ehud Gudes
Venue: IEEE Micro (1988)

The effect on software fault tolerance of hardware features such as hierarchical privilege levels (rings), the use of descriptors for memory protection, separated virtual address spaces, and ring crossings that enforce specific energy points is considered. A strategy that uses a separate programming layer, the recovery layer, to handle fault-tolerant aspects of process interactions is discussed. The recovery metaprogram (RPM) which monitors the run-time behavior of the application program and coordinates error detection, recovery, and reconfiguration, is examined, focusing on privilege levels, which provide protection against error propagation, RMP implementation, and conversations. The intel 80286 has been used as a sample implementation vehicle, but most of the discussion applies to any machine with a similar range of features. Extension to multiprocessor systems is indicated.
Advances in Feedforward Neural Networks: Demystifying Knowledge Acquiring Black Boxes
Authors: Carl G. Looney
Venue: IEEE Transactions on Knowledge and Data Engineering (1996)

We survey research of recent years on the supervised training of feedforward neural networks. The goal is to expose how the networks work, how to engineer them so they can learn data with less extraneous noise, how to train them efficiently, and how to assure that the training is valid. The scope covers gradient descent and polynomial line search, from backpropagation through conjugate gradients and quasi-Newton methods. There is a consensus among researchers that adaptive step gains (learning rates) can stabilize and accelerate convergence and that a good starting weight set improves both the training speed and the learning quality. The training problem includes both the design of a network function and the fitting of the function to a set of input and output data points by computing a set of coefficient weights. The form of the function can be adjusted by adjoining new neurons and pruning existing ones and setting other parameters such as biases and exponential rates. Our exposition reveals several useful results that are readily implementable.
IEEE P1149.5 Module Test and Maintenance Bus
Authors: Pat McHugh
Venue: IEEE Design Test (1992)

The objectives and intended uses of the proposed IEEE P1149.5 Module Test and Maintenance Bus standard are reviewed. Design-for-test features being used in component designs to aid in component, board, subsystem, and system test and maintenance are reviewed. The relationship of the IEEE P1149.5 MTM bus to other test buses is outlined, and the operation protocol is described. Extensions of the standard to meet the needs of specifications are discussed.
Rank, term rank, and chromatic number
Authors: Donniell E. Fishkind, Andrei Kotlov
Venue: Discrete Mathematics (2002)

Let G be a graph with a nonempty edge set, and with rank rk(G), term rank Rk(G), and chromatic number χ(G). We characterize Rk(G) as being the maximum number of colors in certain proper colorings of G. In particular, we observe that χ(G) ≤ Rk(G), with equality holding if and only if (besides isolated vertices) G is either complete or a star. For a twin-free graph G, we observe the bound Rk(G) = O(√2rk(G)) and we show that this bound is sharp.
Design and Test of an Integrated Cryptochip
Authors: Karlheinz Hafner, Hartmut Ritter, Thomas M. Schwair, Stefan Wallstab, Michael Deppermann, Juergen Gessner, Stefan Koesters, Wolf-Deitrich Moeller, Gerd Sandweg
Venue: IEEE Design Test (1991)

A self-testing cryptographic coprocessing chip that provides high security for any data protected through its use is described. The design philosophy and chip architecture are examined. Detailed design and test methods and solutions are given, and it is explained why the chip's design interacts well in networks and with secure hard disks.
C# Essentials
Authors: Ben Albahari, Brad Merrill, Peter Drayton
Venue:  (2001)

:Concise but thorough, this second edition of C# Essentials introduces the Microsoft C# programming language, including the Microsoft .NET Common Language Runtime (CLR) and .NET Framework Class Libraries (FCL) that support it. This book's compact format and terse presentation of key concepts serve as a roadmap to the online documentation included with the Microsoft .NET Framework SDK; the many examples provide much-needed context. This new edition has been updated to cover the final release of the C# language. In addition to overviews of C#, the CLR, and the FCL, this new edition of C# Essentials covers: Every C# language element and its syntax, in reference format, including new keywords The major C# datatypes, with code examples Common C# programming tasks Interoperation with legacy Win32 APIs and COM components, and the use of C/C++ style pointers within the managed context of the CLR Common development issues C# Essentials is an easy way for experienced programmers to evaluate and get up to speed quickly on the language best suited to developing web applications and services on the new Microsoft .NET platform.
Population-Based Learning: A Method for Learning from Examples Under Resource Constraints
Authors: B. W. Wah
Venue: IEEE Transactions on Knowledge and Data Engineering (1992)

A learning model for designing heuristics automatically under resource constraints is studied. The focus is on improving performance-related heuristic methods (HMs) in knowledge-lean application domains. It is assumed that learning is episodic, that the performance measures of an episode are dependent only on the final state reached in evaluating the corresponding test case, and that the aggregate performance measures of the HMs involved are independent of the order of evaluation of test cases. The learning model is based on testing a population of competing HMs for an application problem, and switches from one to another dynamically, depending on the outcome of previous tests. Its goal is to find a good HM within the resource constraints, with proper tradeoff between cost and quality. It extends existing work on classifier systems by addressing issues related to delays in feedback, scheduling of tests of HMs under limited resources, anomalies in performance evaluation, and scalability of HMs. Experience in applying the learning method is described.
A Trie Compaction Algorithm for a Large Set of Keys
Authors: Jun-ichi Aoe, Katsushi Morimoto, Masami Shishibori, Ki-Hong Park
Venue: IEEE Transactions on Knowledge and Data Engineering (1996)

A trie structure is frequently used for various applications, such as natural language dictionaries, database systems, and compilers. However, the total number of states (and transitions between them) of a trie becomes large so that space cost may not be acceptable for a huge key set. In order to resolve this disadvantage, this paper presents a new scheme, called "two-trie," that enables us to perform efficient retrievals, insertions, and deletions for the key sets. The essential idea is to construct two tries for both front and rear compressions of keys, which is similar to a DAWG (Directed Acyclic Word-Graph). The approach differs from a DAWG in that the two-trie approach presented can uniquely determine information corresponding to keys while a DAWG cannot. For an efficient implementation of the two-trie, two types of data structures are introduced. The theoretical and experimental observations show that the method presented is more practical than existing ones considering the use of dynamic key sets, storing information of keys, and compression of transitions.
On the space chromatic number
Authors: Oren Nechushtan
Venue: Discrete Mathematics (2002)

The chromatic number of the space is the minimum number of colors needed to color all points of the Euclidean space so that no two points of the same color are at unit distance. We show that this number is at least 6, improving the best-known previous bound of 5.
Suprema and infima of association schemes
Authors: R. A. Bailey
Venue: Discrete Mathematics (2002)

Partitions on a set are partially ordered by nesting: partition F is nested in partition G if every class of F is contained in a class of G. In this partial order, the supremum of two partitions is the finest partition which nests them both. An association scheme on a finite set Ω is just a partition of Ω × Ω which satisfies some technical conditions. An incomplete-block design is said to be partially balanced with respect to a given association scheme if that scheme is nested in the concurrence partition of the design. The supremum of two association schemes is also an association scheme. As a consequence, if an incomplete-block design is partially balanced at all then there is a unique coarsest association scheme with respect to which it is partially balanced. Infima of association schemes are not well behaved in general. However, some special classes of association scheme of interest to statisticians permit interesting conclusions about infima.
From Language Concepts to Implementation Concepts
Authors: Robert Milne
Venue: Higher-Order and Symbolic Computation (2000)

We outline some of the impact of Christopher Strachey, particularly by referring to work on program equivalence and implementation correctness for programming languages.
Concurrency Control for Mixed Transactions in Real-Time Databases
Authors: Victor C. S. Lee, Kwok-wa Lam, Sheung-Lun Hung
Venue: IEEE Transactions on Computers (2002)

Many recent studies have suggested that the optimistic concurrency control (OCC) protocols outperform the locking-based protocols in real-time database systems (RTDBS). However, the OCC protocols suffer from the problem of unnecessary transaction restarts that is detrimental to transactions meeting their deadlines. The problem is more intensified in mixed transaction environments where both hard and firm real-time transactions exist. Firm transactions are more vulnerable to restarts when they are in conflict with hard transactions on data access. In this paper, we have addressed the problem and devised an effective OCC protocol with dynamic adjustment of serialization order (DASO), called OCC-DA, for RTDBS with mixed transactions. This protocol can avoid unnecessary transaction restarts by dynamically adjusting the serialization order of the conflicting transactions with respect to the validating transaction. As a result, much resource can be saved and more firm transactions can meet their deadlines without affecting the execution of hard transactions. The characteristics of the OCC-DA protocol have been examined in detail by simulation. The results show that the performance of the OCC-DA protocol is consistently better than the other two popular protocols, OCC with forward validation and OCC with Wait-50, over a wide range of system settings. In particular, the OCC-DA protocol provides a more significant performance gain in mixed transaction environments.