ppxscal/embedding_network huggingface dataset:
A programmable hardware accelerator for compiled electrical simulation
Authors: David M. Lewis
Venue: Proceedings of the 25th ACM/IEEE Design Automation Conference (1988)

This paper describes a high performance hardware accelerator for electrical simulation, with a speedup of over 500 for a uniprocessor. The processor addresses a variety of problems ranging from timing simulation to circuit simulation. The accelerator combines special purpose units, such as a high speed device evaluator, with fully programmable general purpose processors. The specialized processors offer extremely high speed for performance critical parts of the simulation. The general purpose processors are optimized for compiled electrical simulation, and use a very long instruction word I(VLIW) architecture. The network solution is compiled into VLIW code. This paper concentrates on those features of the machine that are designed for circuit simulation algorithms, such as SPICE. A simplified example is used to expose the hardware and software techniques used to attack the problem, and estimate the performance improvement due to each technique.
An Accurate and Robust Flux Splitting Scheme for Shock and Contact Discontinuities
Authors: Yasuhiro Wada, Meng-Sing Liou
Venue: SIAM Journal on Scientific Computing (1997)

A flux splitting scheme (AUSMDV) has been constructed with an aim at removing numerical dissipation of the Van Leer-type flux vector splittings on a contact discontinuity. The obtained scheme is also recognized as an improved advection upstream splitting method (AUSM) by Liou and Steffen. The proposed scheme has the following favorable properties: accurate and robust resolution for shock and contact (steady and moving) discontinuities; conservation of enthalpy for steady flows; algorithmic simplicity; and easy extension to general conservation laws such as that for chemically reacting flows. A simple shock fix is presented to cure the numerical shock instability associated with the ``carbuncle phenomenon'' and an entropy fix to remove an expansion shock or glitch at the sonic point. Extensive numerical experiments were conducted to validate the proposed scheme for a wide range of problems, and the results are compiled for comparison with several recent upwind methods.
Location- and Density-Based Hierarchical Clustering Using Similarity Analysis
Authors: Peter Bajcsy, Narendra Ahuja
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1998)

This paper presents a new approach to hierarchical clustering of point patterns. Two algorithms for hierarchical location- and density-based clustering are developed. Each method groups points such that maximum intracluster similarity and intercluster dissimilarity are achieved for point locations or point separations. Performance of the clustering methods is compared with four other methods. The approach is applied to a two-step texture analysis, where points represent centroid and average color of the regions in image segmentation.
An Efficient VLSI Architecture for Full-Search Block MatchingAlgorithms
Authors: Chen-Yi Lee, Mei-Cheng Lu
Venue: Journal of VLSI Signal Processing Systems (1997)

This paper presents a novel memory-based VLSI architecture for full search block matching algorithms. We propose a semi-systolic array to meet the requirements of high computational complexity, where data communications are handled in two styles: (1) global connections for search data and (2) local connections for partial sum. Data flow is handled by a multiple-port memory bank so that all processor elements function on target data items. Thus hardware efficiency achieved can be up to 100%. Both semi-systolic array structure and related memory management strategies for full-search block matching algorithms are highlighted and discussed in detail in the paper.
Cross-tabulation algorithms
Authors: Martin Barghoorn
Venue: ACM SIGAPL APL Quote Quad (1996)

The cross-tabulation technique is a common tool for data analysis and other statistical purposes. But when the datasets are large the standard software such as spreadsheet programs cannot process all the data or the database programs are too slow. It is therefore necessary to offer efficient APL programs which are well designed for cross-tabulations. There are various algorithms in APL but which ones are appropriate for such tasks?
Use of parallel level 3 BLAS in LU factorization on three vector multiprocessors the ALLIANT FX/80, the CRAY-2, and the IBM 3090 VF
Authors: M. J. Daydé, I. S. Duff
Venue: Proceedings of the 4th international conference on Supercomputing (1990)

We show how to transform the B-spline curve and surface fitting problems into suffix computations of continued fractions. Then a parallel substitution scheme is introduced to compute the suffix values on a newly proposed mesh-of-unshuffle network. The derived parallel algorithm allows the curve interpolation through n points to be solved in &Ogr;(log n) time using &THgr;n/log n) processors and allows the surface interpolation through m x n points to be solved in &Ogr;(log m log n) time using &THgr; (mn/(log m log n)) processors. Both interpolation algorithms are cost-optimal for their respective problems. Besides, the surface fitting problem can be even faster solved in &Ogr;(log m + log n) time if &THgr;(mn) processors are used in the network.
On the need for a popular formal semantics
Authors: David A. Schmidt
Venue: ACM SIGPLAN Notices (1997)

The technology transfer from semantics research to mainstream computing has been hampered by specialization of techniques at the expense of calculational clarity. A "popular semantics" is proposed as a remedy.
Signal processing at 250 MHz using high-performance FPGA's
Authors: Brian Von Herzen
Venue: Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays (1997)

This paper describes an application in high-performance signal processing using reconfigurable computing engines. The application is a 250 MHz cross-correlator for radio astronomy and was developed using the fastest available Xilinx FPGA's. We will report experimental results on the operation of CMOS FPGA's at 250 MHz, and describe the architectural innovations required to build a 250 MHz reconfigurable signal processor. Extensions of the technique to a variety of high-performance real-time signal processing algorithms are discussed. The results of this design work provide important clues as to how to improve FPGA architectures to better support real-time signal processing at hundreds of MHz. In particular, direct routing resources between logic elements are critical to preserving high performance. These routing resources need to be symmetric in order to allow for two-way communications between logic elements. Four-way symmetry and regularity would allow for orthogonal transformations of processing elements in a hierarchical fashion. Finally, experimental results indicate that clock buffering is frequently the cause of ultimate failure in speed and performance tests. Wave pipelining techniques may be suitable in clock distribution to improve performance to match that of other elements in the system.
De Bruijn Sequences and Perfect Factors
Authors: Chris J. Mitchell
Venue: SIAM Journal on Discrete Mathematics (1997)

In this paper we describe new constructions for de Bruijn sequences and Perfect Factors. These constructions are all based upon the idea of constructing one sequence (or set of sequences) from another. As a result of this fact, the sequences obtained from these construction methods possess simple decoding algorithms based on decoding the sequences used to construct them. Such decoding algorithms are of importance in position--location applications.
Verifying hardware in its software context
Authors: R. Kurshan, V. Levin, M. Minea, D. Peled, H. Yenigün
Venue: Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design (1997)

We describe a method for verifying hardware whose correct behavior depends upon its software interface. It is presumed that the hardware is presented as a synchronous RTL model whereas the software is presented as an asynchronous abstraction. Our methodology incorporates partial order reduction on the software side, and localization reduction, to deal with the computational complexity of the verification. The partial order reduction is implemented as a constraint on the transition relation of a synchronous transformation of the software model. The reduced transformed model then may be verified using a verification algorithm whose scope is purely synchronous models, without modification. Thus, independent of the interface verification problem, this gives a general method for combining partial order reduction with symbolic model-checking.
Efficient circuit partitioning to extend cycle simulation beyond synchronous circuits
Authors: Charles J. DeVane
Venue: Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design (1997)

Cycle simulation techniques, such as levelized compiled code, can ordinarily be applied only to synchronous designs. They usually cannot be applied to designs containing circuit features like combinational paths, multiple clock domains, generated clocks, asynchronous resets, and transparent latches. This paper presents a novel partitioning algorithm that partitions a non-cycle-simulatable circuit containing these features into sub-circuits that can be cycle simulated. Cycle simulation techniques can be applied to the individual sub-circuits, and the whole collection of sub-circuits can be simulated together using conventional co-simulation techniques. Empirical results demonstrate that this approach brings the benefits of cycle simulation to circuits that were previously impossible to cycle simulate. The partitioning algorithm requires time and space linear in the size of the circuit, and in practice is very fast. We also discuss how the key ideas presented here can be applied to accelerate HDL simulation.
Embedding Torus on the Star Graph
Authors: Dilip K. Saikia, R. Badrinath, Ranjan K. Sen
Venue: IEEE Transactions on Parallel and Distributed Systems (1998)

In this paper, we present a scheme for efficient embedding of torus of any dimension on a star graph. The dilation of the embedding is four. The expansion is small. Congestion depends upon the routing scheme used. With one routing scheme, the congestion is bound by a small constant $(\approx 2)$ with an increase in expansion cost. For a second routing scheme, the congestion is O(n), for an n-star, with bounded expansion.
Multilevel Evaluation of Integral Transforms with Asymptotically Smooth Kernels
Authors: A. Brandt, C. H. Venner
Venue: SIAM Journal on Scientific Computing (1998)

Multilevel algorithms developed for the fast evaluation of integral transforms and the solution of the corresponding integral and integrodifferential equations rely on smoothness properties of the discrete kernel (matrix) and thereby on grid uniformity (see [A. Brandt and A. A. Lubrecht, J. Comput. Phys., 90 (1990), pp. 348--370], [C. H. Venner and A. A. Lubrecht, Multigrid Methods IV: Proc. 4th European Multigrid Conference, Amsterdam 1993, P. Hemker and P. Wesseling, eds., Birkhäuser, Basel, 1994]). However, in actual applications, e.g., in contact mechanics, in many cases a substantial increase of efficiency can be obtained using nonuniform grids, since the solution is smooth in large parts of the domain with large gradients that occur only locally. In this paper a new algorithm is presented which relies on the smoothness of the continuum kernel only, independent of the grid configuration. This will facilitate the introduction of local refinements, wherever needed. Also, the evaluations will generally be faster; for a d-dimensional problem only O(sd + 1) operations per gridpoint are needed if s is the order of discretization. The algorithm is tested using a one-dimensional model problem with logarithmic kernel. Results are presented using both a second- and a fourth-order discretization. For testing purposes and to compare with results presented in [A. Brandt and A. A. Lubrecht, J. Comput. Phys., 90 (1990), pp. 348--370], uniform grids covering the entire domain were considered first.
A Survey of Test Techniques for MCM Substrates
Authors: Madhavan Swaminathan, Bruce Kim, Abhijit Chatterjee
Venue: Journal of Electronic Testing: Theory and Applications (1997)

This paper provides a survey of MCM substrate test techniques. Test techniques that are based on capacitance, resistance, electron beam, latent opens, time domain network analysis (TDNA) and RF resonator are discussed. In this paper, test techniques are applied to interconnect testing.
Low-Voltage Direct I/Q-Modulator and Power Amplifier for2-GHz Transmitter
Authors: Jiri Király, Sami Kalajo, Pertti Ikäläinen, Veikko Porra
Venue: Analog Integrated Circuits and Signal Processing (1998)

An integrated 1&ndash;2 GHz GaAs MESFET direct conversion I/Q-modulator and a power amplifier operating at a supply voltage of 3 V have been designed and fabricated. The core of the I/Q-modulator, a 90&deg; phase shifter, is realized with a 2-section 4-phase RC-filter. The I/Q-modulator converts a baseband signal directly to the 1.1&ndash;2.0 GHz RF frequency. Without any external adjustment, the carrier rejection and the sideband rejection are better than 30 dBc and 26 dBc, respectively. The output power of the modulator is &minus; 6.5 dBm at a LO frequency of 1.75 GHz and for a baseband signal level of 180 mV (100 kHz). The power consumption of the I/Q-modulator is 200 mW at 3-V supply voltage. The 3-V power amplifier is a three stage amplifier having the first two stages biased to class A and the last stage to class AB. The maximum output power of the three stage MESFET power amplifier is &plus;27 dBm and the maximum available power gain is 32 dB. An external output matching circuit is used to feed the output to a 50 &OHgr; load. The die sizes of the modulator and power amplifier are 2.7 x 1.3mm ^2 and 2.0 x 2.0mm^2 , respectively. The circuits have been processed with GEC-Marconi GaAs F20 process.
Java as a specification language for hardware-software systems
Authors: Rachid Helaihel, Kunle Olukotun
Venue: Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design (1997)

The specification language is a critical component of the hardware-software co-design process since it is used for functional validation and as a starting point for hardware- software partitioning and co-synthesis. This paper pro poses the Java programming language as a specification language for hardware-software systems. Java has several characteristics that make it suitable for system specification. However, static control and dataflow analysis of Java programs is problematic because Java classes are dynamically linked. This paper provides a general solution to the problem of statically analyzing Java programs using a technique that pre-allocates most class instances and aggressively resolve memory aliasing using global analysis. The output of our analysis is a control dataflow graph for the input specification. Our results for sample designs show that the analysis can extract fine to coarse-grained concurrency for subsequent hardware-software partitioning and co-synthesis steps of the hardware-software co- design process to exploit.
Multigrid Method for Ill-Conditioned Symmetric Toeplitz Systems
Authors: Raymond H. Chan, Qian-Shun Chang, Hai-Wei Sun
Venue: SIAM Journal on Scientific Computing (1998)

In this paper, we consider solutions of Toeplitz systems Anu = b where the Toeplitz matrices An are generated by nonnegative functions with zeros. Since the matrices An are ill conditioned, the convergence factor of classical iterative methods, such as the damped Jacobi method, will approach one as the size n of the matrices becomes large. Here we propose to solve the systems by the multigrid method. The cost per iteration for the method is of O(n log n) operations. For a class of Toeplitz matrices which includes weakly diagonally dominant Toeplitz matrices, we show that the convergence factor of the two-grid method is uniformly bounded below one independent of n, and the full multigrid method has convergence factor depending only on the number of levels. Numerical results are given to illustrate the rate of convergence.
R D and Global Manufacturing Performance
Authors: Jinfa Chen, David D. Yao, Shaohui Zheng, Robert F. Bordley, Carlos F. Daganzo, John E. Ettlie
Venue: Management Science (1998)

R&D intensity and manufacturing performance were evaluated in this study of 600 durable goods firms in 20 countries. In a path-analytic model, R&D intensity was significantly associated with improvements in market share (R2 = 34%), controlling for firm size, previous market share, and regardless of industry or region of the world. Market share increases were also significantly correlated with improvements in manufacturing agility (R2 = 4%). Agility improvement was significantly correlated with R&D intensity, and computerization in manufacturing, controlling for firm size and region, and did exhibit industry effects, with electronic equipment firms elevated on this measure. Computerization exhibited regional (not industry) differences, with South American firms depressed on this measure. The role of computerization in manufacturing and agility in firm innovativeness are discussed.
The optimal placement of casualty evacuation assets: a linear programming model
Authors: Scott C. Sundstrom, Christopher G. Blood, Serge A. Matheny
Venue: Proceedings of the 28th conference on Winter simulation (1996)

Through the use of linear programming techniques, the optimal number and positioning of patient evacuation assets within a theater of operations may be determined to ensure the orderly transport of casualties from the front lines to third echelon medical treatment facilities. The Probabilistic Location Set Covering Problem has been chosen as the core module for a linear programming model to assist in these deterniinations. The Optimal Placement of Casualty Evacuation Assets (OPTEVAC) model prompts the user to enter the dimensions of the theater, troop deployment nodes, types of evacuation assets available, and preferred locations of medical treatment facilities. The OPTEVAC model then provides output as to the required numbers of ground and air ambulances as well as the optimal positioning of those evacuation assets and ambulance exchange points.
Building a scaleable geo-spatial DBMS: technology, implementation, and evaluation
Authors: Jignesh Patel, JieBing Yu, Navin Kabra, Kristin Tufte, Biswadeep Nag, Josef Burger, Nancy Hall, Karthikeyan Ramasamy, Roger Lueder, Curt Ellmann, Jim Kupsch, Shelly Guo, Johan Larson, David De Witt, Jeffrey Naughton
Venue: ACM SIGMOD Record (1997)

This paper presents a number of new techniques for parallelizing geo-spatial database systems and discusses their implementation in the Paradise object-relational database system. The effectiveness of these techniques is demonstrated using a variety of complex geo-spatial queries over a 120 GB global geo-spatial data set.
Teaching OOP in C++ using an artificial life framework
Authors: Richard E. Pattis
Venue: ACM SIGCSE Bulletin (1997)

This paper explores the framework method for teaching object-oriented programming. Specifically, it describes a hierarchy of C++ classes that implement the framework for an Artificial Life simulator. Students learn how to read these classes and extend them via inheritance: they design and implement subclasses that encapsulate the behavior and state of environments and the entities that inhabit them. The simulator constructs an artificial world from objects of these subclasses; then, it animates these objects as they interact during the simulation. This paper includes one sample project and both subclasses that implement its solution.
Register promotion in C programs
Authors: John Lu, Keith D. Cooper
Venue: Proceedings of the ACM SIGPLAN 1997 conference on Programming language design and implementation (1997)

The combination of pointers and pointer arithmetic in C makes the task of improving C programs somewhat more difficult than improving programs written in simpler languages like Fortran. While much work has been published that focuses on the analysis of pointers, little has appeared that uses the results of such analysis to improve the code compiled for C. This paper examines the problem of register promotion in C and presents experimental results showing that it can have dramatic effects on memory traffic.
A fantasy adventure game as a learning environment: why learning to program is so difficult and what can be done about it
Authors: Robert Moser
Venue: Proceedings of the 2nd conference on Integrating technology into computer science education (1997)

A number of factors contribute to the difficulty of learning computer programming, and by examining some of these factors we can hope to design an environment that is more conducive to the learning process. I analyse some of these problems and find that one possible solution is to embed the educational content into a fantasy adventure game. Designing an educational game is, however, fraught with difficulties beyond those normally associated with writing such a program, as there are conflicts between educational and entertainment goals. Described are a few of these conflicts from the early stages of my project, and the compromises that they have engendered.
Design of object-oriented simulations in C++
Authors: Jeffrey A. Joines, Stephen D. Roberts
Venue: Proceedings of the 28th conference on Winter simulation (1996)

An object-oriented simulation (OOS) consisting of a set of object classes written in C++ can be used to create simulation models and packages. The simulations built with these tools possess the benefits of an object-oriented design, including the use of encapsulation, inheritance, polymorphism, run-time binding, and parameterized typing. These concepts are illustrated by creating a set of object frames which encapsulate simulation requirements. Simulation modeling is contained within a set of modeling frameworks. A network queuing simulation language is developed which has several notable features not available in other non-OOS languages. OOS provides full accessibility to the base language, faster executions, portable models and executables, a multi-vendor programming language, and a growing variety of complementary development tools.
A Note on Sequences with the Shift and Add Property
Authors: S. R. Blackburn
Venue: Designs, Codes and Cryptography (1996)

A sequence of elements from a finite field satisfies the shift and add property if the componentwise sum of any two shifts of the sequence is either a shift of the sequence or the all zero sequence. A sequence whose elements lie in an arbitrary group satisfies the shift and multiply property if the componentwise product of any two shifts of the sequence is either a shift of the sequence or the all identity sequence. The paper classifies sequences which have the shift and add property or the shift and multiply property.
Understanding class evolution through atomic changes
Authors: K. Rangarajan
Venue: ACM SIGPLAN Notices (1998)

Class-based object-oriented programming languages encourage developers to implement a software system as a collection of classes and objects. When the software evolves across versions for various reasons, changes are made to one or more classes in the original version. Our research focus is on studying the class evolution pattern looking for clues about minimizing retest effort. In this article, we show that class evolution is governed by a finite set of atomic changes that are language-specific, discuss some properties of these changes and show how they may be identified for a programming language.