ppxscal/embedding_network huggingface dataset:
Planning the Software Industrial Revolution
Authors: Brad J. Cox
Venue: IEEE Software (1990)

The author traces the US history of invention and technology transfer from the 1700s to the present and asks whether software development can stop being a process-centered cottage industry by the application of interchangeable parts technology. He maintains that a revolution is needed to accomplish this and outlines the steps of such a revolution. The author clarifies the meaning of object oriented, discusses the value rigidity trap, and provides a commercial example of the approach that he advocates.
Performance of Shared Memory in a Parallel Computer
Authors: K. Donovan
Venue: IEEE Transactions on Parallel and Distributed Systems (1991)

A method for analyzing the lengths of memory queues when the network is conflict-free isdescribed. An algorithm based on this method is shown to efficiently determine the upperand lower bounds of the queue length. Analysis indicates that the strategy of usinghashing to spread data across memory modules is a good one. Results show that if thesize of the system is increased while maintaining a constant ratio of numbers ofprocessors to memories, then, asymptotically, the slowdown in performance from conflictsat the memory modules is Theta (log m/log log m). For m and n less than 100000 andlambda between 0.25 and 4.0, the graphical data confirm this growth rate.
COTS-Based Systems Top 10 List
Authors: Victor R. Basili, Barry Boehm
Venue: Computer (2001)

This list offers hypotheses for examining CBS project decisions in light of empirical data samples.
Insider Power Techniques for Microsoft Windows XP
Authors: Paul Mcfedries, Austin Wilson, Geoff Winslow
Venue:  (2003)

Tweak Windows® XP for ultimate performance with the undocumented secrets and hidden gems of the experts who work with the technology every day. Use their best techniques, practices, hacks, tricks, and workarounds to put all of your PC's muscle to work.
SPI Patterns: Learning from Experience
Authors: Marina Blanco, Pedro Gutiérrez, Giuseppe Satriani
Venue: IEEE Software (2001)

The European Software Institute maintains one of the most important repositories of software process improvement experiences, containing results of more than 250 European organizations. This article provides an overview of the repository content, and presents patterns that produce the repository SPI knowledge to help organizations plan an improvement initiative.
Fast visualization of plane-like structures in voxel data
Authors: Steffen Prohaska, Hans Christian Hege
Venue: Proceedings of the conference on Visualization '02 (2002)

We present a robust, noise-resistant criterion characterizing plane-like skeletons in binary voxel objects. It is based on a distance map and the geodesic distance along the object's boundary. A parameter allows to control the noise sensitivity.If needed, homotopy with the original object might be reconstructed in a second step, using an improved distance ordered thinning algorithm.The skeleton is analyzed to create a geometric representation for rendering. Plane-like parts are transformed into an triangulated surface not enclosing a volume by a suitable triangulation scheme. The resulting surfaces have lower triangle count than those created with standard methods and tend to maintain the original geometry, even after simplification with a high decimation rate. Our algorithm allows to interactively render expressive images of complex 3D structures, emphasizing independently plane-like and rod-like structures.The methods are applied for visualization of the microstructure of bone biopsies.
A general technique for querying XML documents using a relational database system
Authors: Jayavel Shanmugasundaram, Eugene Shekita, Jerry Kiernan, Rajasekar Krishnamurthy, Efstratios Viglas, Jeffrey Naughton, Igor Tatarinov
Venue: ACM SIGMOD Record (2001)

There has been recent interest in using relational database systems to store and query XML documents. Each of the techniques proposed in this context works by (a) creating tables for the purpose of storing XML documents (also called relational schema generation), (b) storing XML documents by shredding them into rows in the created tables, and (c) converting queries over XML documents into SQL queries over the created tables. Since relational schema generation is a physical database design issue -- dependent on factors such as the nature of the data, the query workload and availability of schemas -- there have been many techniques proposed for this purpose. Currently, each relational schema generation technique requires its own query processor to efficiently convert queries over XML documents into SQL queries over the created tables. In this paper, we present an efficient technique whereby the same query-processor can be used for all such relational schema generation techniques. This greatly simplifies the task of relational schema generation by eliminating the need to write a special-purpose query processor for each new solution to the problem. In addition, our proposed technique enables users to query seamlessly across relational data and XML documents. This provides users with unified access to both relational and XML data without them having to deal with separate databases.
Implementing Macro Test in Silicon Compiler Design
Authors: Frans Beenker, Barry J. Dekker, Richard Stans, Max Van der Star
Venue: IEEE Design Test (1990)

A testability strategy for a complex VLSI device that is implemented in the Piramid digital-signal-processor silicon compiler is presented. The macro test method proposed supports built-in self-test, scan test, restricted partial scan, and test-control logic at various levels in the design hierarchy. The strategy uses techniques such as a macro test plan, transfer information, and intermediate vector storage. The overhead from adding testability is only 10% of the total area and test-program generation is done with 100% fault coverage in a very short time, since there is no need for global test-pattern generation. A set of tools that guide the testability implementation from design to the final test program is described.
Unique square property and fundamental factorizations of graph bundles
Authors: Blaz Zmazek, Janez Zerovnik
Venue: Discrete Mathematics (2002)

Graph bundles generalize the notion of covering graphs and graph products. In Imrich et al. (Discrete Math. 167/168 (1998) 393) authors constructed an algorithm that finds a presentation as a nontrivial cartesian graph bundle for all graphs that are cartesian graph bundles over triangle-free simple base using the relation δ* having the square property. An equivalence relation R on the edge set of a graph has the (unique) square property if and only if any pair of adjacent edges which belong to distinct R-equivalence classes span exactly one induced 4-cycle (with opposite edges in the same R-equivalence class). In this paper we define the unique square property and show that any weakly 2-convex equivalence relation possessing the unique square property determines the fundamental factorization of a graph as a nontrivial cartesian graph bundle over an arbitrary base graph, whenever it separates degenerate and nondegenerate edges of the factorization.
Timing-Driven Partial Scan
Authors: Jing-yang Jou, Kwang-ting (tim) Cheng
Venue: IEEE Design Test (1995)

We present a partial scan approach, which aims at reducing both area overhead and performance degradation caused by test logic. Given a target speed and an initial design that meets the target, the algorithm selects a minimum set of scan flip-flops, if they exist, that (1) will break all sequential cycles and (2) will not violate the performance requirement after the scan logic is added. If such a set does not exist, the algorithm will find a set of scan flip-flops in which (1) all sequential cycles are broken and (2) the total area increase caused by the scan logic and the subsequent performance optimization to meet the target speed is minimized.Experimental results on some of the ISCAS'89 sequential circuits are presented as well as comparisons between the new method and the existing methods. For circuits synthesized by automatic synthesis tools, we suggest a new design flow, which selects/inserts the partial scan logic after area optimization, but before performance optimization. For meeting both performance and testability requirements, the new design flow tends to produce designs with less area increase than the traditional design flow, which considers testability and adds test logic after performance optimization.This work represents an important concept for considering the three major design parameters, namely, performance, area, and testability, together during the synthesis phase for obtaining the right partial scan solution.
Free Dimensions-An Effective Approach to Achieving Fault Tolerance in Hypercubes
Authors: Pei-Ji Yang, C. s. Raghavendra, Sing-Ban Tien
Venue: IEEE Transactions on Computers (1995)

Hypercube network is an attractive structure for parallel processing due to its symmetry and regularity. In this paper, we use the concept of free dimensions to achieve fault tolerance in hypercubes without requiring additional spare processing nodes; such additional redundancy requires modification of hypercube structure. A free dimension is defined to be a dimension across which both end nodes are not faulty.Given an n-dimensional hypercube, Qn, and a set of f¿n faulty nodes, we present an efficient algorithm to find free dimensions, and show that at least n¿f+ 1 free dimensions exist. Free dimensions can be used to partition Qn into subcubes such that each subcube contains at most one fault. Such a partitioning helps in achieving fault tolerance via emulation, embedding, reconfiguration. It also helps in designing efficient routing and broadcasting algorithms in faulty hypercubes.
On Distributed Dynamic Channel Allocation in Mobile Cellular Networks
Authors: Jianping Jiang, Ten-Hwang Lai, Neelam Soundarajan
Venue: IEEE Transactions on Parallel and Distributed Systems (2002)

Distributed dynamic channel allocation (DDCA) is a fundamental resource management problem in mobile cellular networks. It has a flavor of distributed mutual exclusion but is not exactly a mutual exclusion problem (because a channel may be reused in different cells). In this paper, we establish the exact relationship between the two problems. Specifically, we introduce the problem of relaxed mutual exclusion to model one important aspect of the DDCA problem. We develop a general algorithm that guarantees relaxed mutual exclusion for a single resource and prove necessary and sufficient conditions for the information structure. Considering distributed dynamic channel allocation as a special case of relaxed mutual exclusion, we apply and extend the algorithm to further address the issues that arise in distributed channel allocation such as deadlock resolution, dealing with multiple channels, design of efficient information structures, and channel selection strategies. Based on these results, we propose an example distributed channel allocation scheme using one of the information structures proposed. Analysis and simulation results are provided and show that the results of this research can be used to design more efficient distributed channel allocation algorithms.
EPR Adoption and Dual Record Maintenance in the U.S.: Assessing Variation in Medical Systems Infrastructure
Authors: Daniel P. Lorence, Amanda Spink, Michael C. Richards
Venue: Journal of Medical Systems (2002)

The growing adoption of evidence-based medicine in the United States is acting to cause fundamental changes in the delivery of healthcare management services. With the increasing incorporation of electronic patient records (EPRs) into the day-to-day practice of medicine, it necessitates greater dependence on adequate functioning of such resources, as they become more frequently used as a clinical complement in the practice of medicine. Assessing the patterns of adoption of EPRs is likewise of increasing importance, with the recent imposition of uniform government data collection and management requirements. The medium of data storage and maintenance within many organizations is a critical factor in the ultimate delivery of service, with a like need for an integrated, designated medium for the management of data becoming paramount. This study examines, on a nationwide basis, variation in reported adoption of EPRs within U.S. healthcare organizations, and the related maintenance of dual electronic/paper record systems.
From Monsoon to StarT-Voyager: University-Industry Collaboration
Authors: Arvind, Anton T. Dahbura, Alejandro Caro
Venue: IEEE Micro (2000)

The delicate balance between academia and industry conducting joint research can be difficult to maintain. The authors share many lessons learned from such an alliance on a dataflow microprocessor project.
Separating a Color Signal into Illumination and Surface Reflectance Components: Theory and Applications
Authors: J. Ho, B. V. Funt, M. S. Drew
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1990)

A separation algorithm for achieving color constancy and theorems concerning its accuracy are presented. The algorithm requires extra information, over and above the usual three values mapping human cone responses, from the optical system. However, with this additional information-specifically, a sampling across the visible range of the reflected, color-signal spectrum impinging on the optical sensor-the authors are able to separate the illumination spectrum from the surface reflectance spectrum contained in the color-signal spectrum which is, of course, the product of these two spectra. At the heart of the separation algorithm is a general statistical method for finding the best illumination and reflectance spectra, within a space represented by finite-dimensional linear models of statistically typical spectra, whose product closely corresponds to the spectrum of the actual color signal. Using this method, the authors are able to increase the dimensionality of the finite-dimensional linear model for surfaces to a realistic value. One method of generating the spectral samples required for the separation algorithm is to use the chromatic aberration effects of a lens. An example of this is given. The accuracy achieved in a large range of tests is detailed, and it is shown that agreement with actual surface reflectance is excellent.
Coming of Age in an Object-Oriented World
Authors: Grady Booch
Venue: IEEE Software (1994)

The author predicts that increasing connectivity and consumer demands will power an unprecedented growth in software's volume and complexity, then explains why the flexibility and robustness of an object-oriented approach can best meet these future challenges.
Point set surfaces
Authors: Marc Alexa, Johannes Behr, Daniel Cohen-Or, Shachar Fleishman, David Levin, Claudio T. Silva
Venue: Proceedings of the conference on Visualization '01 (2001)

We advocate the use of point sets to represent shapes. We provide a definition of a smooth manifold surface from a set of points close to the original surface. The definition is based on local maps from differential geometry, which are approximated by the method of moving least squares (MLS). We present tools to increase or decrease the density of the points, thus, allowing an adjustment of the spacing among the points to control the fidelity of the representation.To display the point set surface, we introduce a novel point rendering technique. The idea is to evaluate the local maps according to the image resolution. This results in high quality shading effects and smooth silhouettes at interactive frame rates.
Run-Time Disambiguation: Coping with Statically Unpredictable Dependencies
Authors: A. Nicolau
Venue: IEEE Transactions on Computers (1989)

A technique called run-time disambiguation (RTD) is presented for antialiasing of indirect memory references that cannot normally be disambiguated at compile time. The technique relies on assumptions about the run-time behavior of a program to allow static transformations of the code, in an effort to extract parallelism. The importance of the technique lies in its ability to supplement (and even partially replace) more expensive fully static dependency analysis. RTD works even in situations where the fully static approach is completely ineffective. Evidence of the importance of memory disambiguation in general, and RTD in particular, for parallelizing compilers, is presented. The implementation and effectiveness of the technique in the context of the Bulldog compiler is discussed.
A Notation for Deterministic Cooperating Processes
Authors: K. Mani Chandy, Ian Foster
Venue: IEEE Transactions on Parallel and Distributed Systems (1995)

This paper proposes extensions of sequential programming languages for parallel programming that have the following features:Dynamic Structures: The process structure is dynamic. Processes and variables can be created and deleted.Paradigm Integration: The programming notation supports shared memory and message passing models.Determinism: Demonstrating that a program is deterministic_all executions with the same input produce the same output¿is straightforward. Programs can be written so that compilers can verify that the programs are deterministic. Nondeterministic constructs can be introduced in a sequence of refinement steps to obtain greater efficiency if required.The ideas have been incorporated in an extension of Fortran, but the underlying sequential imperative language is not central to the ideas described here. A compiler for the Fortran extension, called Fortran M, is available by anonymous ftp from Argonne National Laboratory. Fortran M has been used for a variety of parallel applications.
Design Verification of the WE 32106 Math Accelerator Unit
Authors: Peter M. Maurer
Venue: IEEE Design Test (1988)

An overview is given of the MAU, an IEEE-compatible floating-point accelerator that operates as a coprocessor for the WE 32100 CPU. The chip provides virtually all the features that the IEEE-754 floating-point standard requires, with added software that provides a fully conforming system. A description is then given of the approach used for its design verification, which resulted in a unit that has exhibited no bugs, even two years after its first silicon implementation. Designers used two sets of tools during verification. With the first set, they reduced the time needed to create and execute tests and simplified the development of system tests. With the second set, they created a random test system, which plugged the holes left by system tests. Work underway to apply the techniques to other chips is described.
Design of New DSP Instructions and Their Hardware Architecture for High-Speed FFT
Authors: Jae Sung Lee, Myung H. Sunwoo
Venue: Journal of VLSI Signal Processing Systems (2003)

This paper presents new DSP (Digital Signal Processor) instructions and their hardware architecture for high-speed FFT. The instructions perform new operation flows, which are different from the MAC (Multiply and Accumulate) operation on which existing DSP chips heavily depend. This paper proposes the DPU (Data Processing Unit) supporting the instructions and shows it to be two times faster than existing DSP chips for FFT. The architecture has been modeled by the Verilog HDL and logic synthesis has been performed using the 0.35 &mu;m standard cell library. The maximum operating clock frequency is about 144.5 MHz and the architecture will be employed on an application-specific DSP chip.
Test-Case Generation with IOGen
Authors: Timothy E. Lindquist, Joyce R. Jenkins
Venue: IEEE Software (1988)

The IOGen static-analysis tool for a subset of Ada addresses part of the problem of verification of software reliability. It uses a technique based on symbolic execution and produces a set of I/O pairs that represent execution paths through a program. The authors present IOGen's design and demonstrate how to use it to test programs and validate Ada software interfaces. Although IOGen is specific to an Ada subset, the same technique can be applied to any language with a grammar that uses a left-to-right scan with one look-ahead token producing a leftmost derivation (an LL(1) grammar).
Process-Oriented Software Education
Venue: IEEE Software (1994)

In the last few years, development organizations have come to recognize that software development has moved beyond the capabilities of individual programmers and is now an engineering activity performed by teams, and the quality of a software product is highly dependent on the quality of the process used to develop it. The process movement has had a visible effect on the software industry, but how should it influence educators? In this article, the author describes his institution's response. He presents some new views of mature ideas on software quality and productivity.
A Deterministic Multivariate Interpolation Algorithm for Small Finite Fields
Authors: Zeljko Zilic, Zvonko G. Vranesic
Venue: IEEE Transactions on Computers (2002)

We present a new multivariate interpolation algorithm over arbitrary fields which is primarily suited for small finite fields. Given function values at arbitrary $\big. t\bigr.$ points, we show that it is possible to find an n-variable interpolating polynomial with at most $\big. t\bigr.$ terms, using the number of field operations that is polynomial in $\big. t\bigr.$ and $\big. n\bigr.$. The algorithm exploits the structure of the multivariate generalized Vandermonde matrix associated with the problem. Relative to the univariate interpolation, only the minimal degree selection of terms cannot be guaranteed and several term selection heuristics are investigated toward obtaining low-degree polynomials. The algorithms were applied to obtain Reed-Muller and related transforms for incompletely specified functions.
Utilitarian Desires
Authors: Jérôme Lang, Leendert Van Der Torre, Emil Weydert
Venue: Autonomous Agents and Multi-Agent Systems (2002)

Autonomous agents reason frequently about preferences such as desires and goals. In this paper we propose a logic of desires with a utilitarian semantics, in which we study nonmonotonic reasoning about desires and preferences based on the idea that desires can be understood in terms of utility losses (penalties for violations) and utility gains (rewards for fulfillments). Our logic allows for a systematic study and classification of desires, for example by distinguishing subtly different ways to add up these utility losses and gains. We propose an explicit construction of the agent's preference relation from a set of desires together with different kinds of knowledge. A set of desires extended with knowledge induces a set of &lsquo;distinguished&rsquo; utility functions by adding up the utility losses and gains of the individual desires, and these distinguished utility functions induce the preference relation.
Rapidly Prototyping Real-Time Systems
Authors: Luqi, Valdis Berzins
Venue: IEEE Software (1988)

A prototyping approach that uses modularity and reusable components is described that enables large real-time systems to be prototyped rapidly. It combines a computational model tailored for real-time systems with a high-level prototyping language (the Prototype System Description Language), a systematic design method for rapid prototype construction, and an automated prototyping environment. The method meets the following requirements: the prototype satisfies its requirements and is traceable to them; the prototype is easy to modify; and the prototype code is easy to read and analyze.