ppxscal/embedding_network huggingface dataset:
Broadcast Protocols for Distributed Systems
Authors: P. M. Melliar-Smith, L. E. Moser, V. Agrawala
Venue: IEEE Transactions on Parallel and Distributed Systems (1990)

An innovative approach is presented to the design of fault-tolerant distributed systems that avoids the several rounds of message exchange required by current protocols for consensus agreement. The approach is based on broadcast communication over a local area network, such as an Ethernet or a token ring, and on two novel protocols, the Transprotocol, which provides efficient reliable broadcast communication, and the Totalprotocol, which with high probability promptly places a total order on messages and achieves distributed agreement even in the presence of fail-stop, omission, timing, and communication faults. Reliable distributed operations, such as locking, update, and commitment, typically require only a single broadcast message rather than the several tens of messages required by current algorithms.
Proceedings of the 1st international conference on Computer graphics and interactive techniques in Australasia and South East Asia
Venue: Computer graphics and interactive techniques in Australasia and South East Asia (2003)

Welcome to GRAPHITE 2003. This is the first of an annual series of conferences, organised by two newly formed computer graphics associations ANZGRAPH (for Australia and New Zealand) and SEAGRAPH (for Southeast Asia). We trust this conference will bring the excitement and vibrancy of the annual SIGGRAPH conference to the region, with a host of new ideas, insights and technologies.The event was inspired by a delegation representing the ACM, ACM SIGGRAPH and EUROGRAPHICS, which visited to Australia, New Zealand and Singapore in March and April 2002. The visit was a delight and members of the delegation were bowled over by the warmth of the reception everywhere, and by the quality and breadth of activity related to computer graphics permeating the region. The discussions focused on two areas. Firstly how appropriate and useful it would be to establish professional groupings in the region so that international liaisons with those active in the field in Australia, New Zealand and South East Asia could be channelled and facilitated. Secondly it was felt that an international event which brought more interaction between the regional and global communities would be a major benefit. The GRAPHITE series of conferences is the result of this thinking and brings together a spectrum of truly global research activity.These proceedings are the archival record of the papers program for the conference. We have been impressed by the breadth and quality of the work submitted. The 32 full papers and 19 sketches are drawn from research groups in 13 countries; ranging from Japan to the USA, with Europe well represented alongside the high quality regional contributions from research leaders in Singapore, Australia and New Zealand. The geographical spread is matched by the spread of topics and applications, and we feel sure that there are topics of interest to anyone working in the field, with presentations to match. The submitted work is complemented by the three invited presentations and we are pleased to be able to include extended abstracts of these talks with the proceedings.
Dependence Uniformization: A Loop Parallelization Technique
Authors: T. H. Tzen, L. M. Ni
Venue: IEEE Transactions on Parallel and Distributed Systems (1993)

Data dependence uniformization, a method for overcoming the difficulties in parallelizing a doubly nested loop with irregular dependence constraints is proposed. This approach is based on the concept of vector decomposition. A simple set of basic dependences is developed from which all dependence constraints can be composed. The set of basic dependences is added to every iteration to replace all original dependences so that the dependence constraints become uniform. An efficient synchronization method ispresented to obey the uniform dependence constraints in every iteration.
Pentium 4 Performance-Monitoring Features
Authors: Brinkley Sprunt
Venue: IEEE Micro (2002)

The Intel Pentium 4's unique performance-monitoring features overcome many limitations and problems found in previous processors. Pentium 4 Xeon performance monitoring supports simultaneous multithreaded execution features.
Scripting: Higher-Level Programming for the 21st Century
Authors: John K. Ousterhout
Venue: Computer (1998)

A fundamental change is occurring in the way people write computer programs, away from system programming languages such as C or C++ to scripting languages such as Perl or Tcl. Although many people are participating in the change, few realize that the change is occurring and even fewer know why it is happening. This article explains why scripting languages will handle many of the programming tasks in the next century better than system programming languages. System programming languages were designed for building data structures and algorithms from scratch, starting from the most primitive computer elements. Scripting languages are designed for gluing: They assume the existence of a set of powerful components and are intended primarily for connecting components. System programming languages are strongly typed to help manage complexity, while scripting languages are typeless to simplify connections among components and provide rapid application development. Scripting languages and system programming languages are complementary, and are typically used together in component frameworks. However, several recent trends have greatly expanded the applicability of scripting languages. These trends will continue over the next decade, with more and more new applications written entirely in scripting languages and system programming languages used primarily for creating components.
Hypertool: A Programming Aid for Message-Passing Systems
Authors: M. Y. Wu, D. D. Gajski
Venue: IEEE Transactions on Parallel and Distributed Systems (1990)

Programming assistance, automation concepts, and their application to a message-passing system program development tool called Hypertool are discussed. Hypertool performs scheduling and handles the communication primitive insertion automatically, thereby increasing productivity and eliminating synchronization errors. Two algorithms, based on the critical-path method, are presented for scheduling processes statically. Hypertool also generates the performance estimates and other program quality measures to help programmers improve their algorithms and programs.
A Fuzzy Controller with an Optimized Defuzzification Algorithm
Authors: Antonio Ruiz, Julio Gutiérrez, J. A. Felipe Fernández
Venue: IEEE Micro (1995)

The fuzzy controller architecture presented in this paper consists of a synchronous digital system which process fuzzy sets at two abstraction levels: fuzzy set level and domain element level. Its main features are the use of trapezia, encoded with four parameters, to represent the antecedent labels. The defuzzification is based in a novel algorithm which speeds up this process by avoiding the operation of division. The performance of the processor is not a constant but depends on the location of the centroid within the domain of the consequent, being better when the centroid is located at the centre of the domain, and worse when it becomes near to one of the ends. Consequently, it takes advantage from the fact that the centroid in an end is the least probable situation. Any case the processor gets significant improvements in speed and latency.
Performance Analysis of a Concurrent File Reorganization Algorithm for Record Clustering
Authors: E. Omiecinski, L. Lee, P. Scheuermann
Venue: IEEE Transactions on Knowledge and Data Engineering (1994)

Presents a simulation-based performance analysis of a concurrent file reorganization algorithm. We examine the effect on throughput of (a) buffer size, (b) degree of reorganization, (c) write probability of transactions, (d) multiprogramming level, and (e) degree of clustered transactions. The problem of file reorganization that we consider involves altering the placement of records on pages of a secondary storage device. In addition, we want this reorganization to be done in place, i.e. using the file's original storage space for the newly reorganized file. Our approach is appropriate for a non-in-place reorganization as well. The motivation for such a physical change, i.e. record clustering, is to improve the database system's performance, i.e. minimizing the number of page accesses made in answering a set of queries. There are numerous record clustering algorithms, but they usually do not solve the entire problem, i.e., they do not specify how to efficiently reorganize the file to reflect the clustering assignment that they determine. In previous work, we have presented an algorithm that is a companion to general record clustering algorithms, i.e. it actually transforms the file. In this work we show through simulation that our algorithm, when run concurrently with user transactions, provides an acceptable level of overall database system performance.
A Case for Intelligent RAM
Authors: David Patterson, Thomas Anderson, Neal Cardwell, Richard Fromm, Kimberly Keeton, Christoforos Kozyrakis, Randi Thomas, Katherine Yelick
Venue: IEEE Micro (1997)

Two trends call into question the current practice of microprocessors and DRAMs being fabricated as different chips on different fab lines: 1) the gap between processor and DRAM speed is growing at 50% per year; and 2) the size and organization of memory on a single DRAM chip is becoming awkward to use in a system, yet size is growing at 60% per year. Intelligent RAM, or IRAM, merges processing and memory into a single chip to lower memory latency, increase memory bandwidth, and improve energy efficiency as well as to allow more flexible selection of memory size and organization. In addition, IRAM promises savings in power and board area. We review the state of microprocessors and DRAMs today, explore some of the opportunities and challenges for IRAMs, and finally estimate performance and energy efficiency of three IRAM designs.
Leaving the Prison: Permitting Partner Choice and Refusal in Prisoner's Dilemma Games
Authors: Esther Hauk
Venue: Computational Economics (2001)

We propose a simple rule of thumb on how to choose one's game partner that allows economic agents who care about the future to learn to cooperate in the iterated prisoner's dilemma. This rule of thumb uses partner selection strategically to reward cooperative behavior and teach defectors a lesson. This reward and punishment scheme leads to higher payoffs of non-exploitive strategies and slowly converts defectors, who are attracted by the higher payoffs, into non-exploitive types. Simulations show that the convergence to stable cooperative behavior is rather fast.
Learning in Gibbsian Fields: How Accurate and How Fast Can It Be?
Authors: Song Chun Zhu, Xiuwen Liu
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (2002)

Gibbsian fields or Markov random fields are widely used in Bayesian image analysis, but learning Gibbs models is computationally expensive. The computational complexity is pronounced by the recent minimax entropy (FRAME) models which use large neighborhoods and hundreds of parameters. In this paper, we present a common framework for learning Gibbs models. We identify two key factors that determine the accuracy and speed of learning Gibbs models: The efficiency of likelihood functions and the variance in approximating partition functions using Monte Carlo integration. We propose three new algorithms. In particular, we are interested in a maximum satellite likelihood estimator, which makes use of a set of precomputed Gibbs models called "satellites" to approximate likelihood functions. This algorithm can approximately estimate the minimax entropy model for textures in seconds in a HP workstation. The performances of various learning algorithms are compared in our experiments.
Asim: A Performance Model Framework
Authors: Joel Emer, Pritpal Ahuja, Eric Borch, Artur Klauser, Chi-Keung Luk, Srilatha Manne, Shubhendu S. Mukherjee, Harish Patil, Steven Wallace, Nathan Binkert, Roger Espasa, Toni Juan
Venue: Computer (2002)

The longevity and usefulness of a microprocessor performance modelhas historically depended on the model writer's skills and discipline. However,at Compaq the models became extremely complex and unmanageablebecause designers lacked a structured way to develop them.To cope with these complexities, Compaq researchers began developing Asimin late 1998 to allow model writers to faithfully represent the detailed timing of set of issues identified during two standards efforts: the IEEE Std. 1061-1998 for a Software Quality Metrics Methodology and the American National Standard Recommended Practice for Software Reliability (ANSI/AIAA R-013-1992). The second approach ties these knowledge requirements to phases in thesoftware development life cycle. Together, these approaches define a bodyof knowledge that shows software engineers why and when to measure quality.Focusing on the entire software development life cycle, rather than just the coding phase, gives software engineers the comprehensive knowledge they need toenhance software quality and supports early detection and resolution of qualityproblems. The integration of product and process measurements lets engineersassess the interactions between them throughout the life cycle.Software engineers can apply this body of knowledge as a guideline for incorporating quality measurement in their projects. Professional licensing and training programs will also find it useful.
Supporting Reuse with Object Technology
Authors: David C. Rine
Venue: Computer (1997)

Is there a way to develop software that is of higher quality and yet takes less time and effort to produce? Many software developers believe there is, through reusing high-quality, tested software already developed. Unfortunately, software reuse has proven difficult to achieve. Organizations attempting to implement a software reuse program face both technical and nontechnical problems. What do software developers have to do to successfully implement reuse? In 1995, George Mason University undertook a study to investigate the relationships between software reuse investment and capability, productivity, and quality, as well as many of the theories proposed by the literature. The study found that a product-line and software architecture approach are higher predictors of decreased effort and increased quality than software reuse alone. On the other hand, it found no relationship between software reuse capability and the library approach.
Qualitative and Quantitative Reliability Assessment
Authors: Karama Kanoun, Mohamed Kaâniche, Jean-Claude Laprie
Venue: IEEE Software (1997)

Traditional system reliability efforts have failed to focus on software reliability. To remedy this, the authors propose a method that uses descriptive analyses, trend analyses, and reliability models to control testing activities, evaluate software reliability, and plan maintenance.
MPGS: An Interactive Tool for the Specification and Generation of Multimedia Presentations
Authors: Elisa Bertino, Elena Ferrari, Marco Stolf
Venue: IEEE Transactions on Knowledge and Data Engineering (2000)

Multimedia presentations are composed of objects belonging to different data types such as video, audio, text, and image. An important aspect is that, quite often, the user defining a presentation needs to express sophisticated temporal and spatial constraints among the objects composing the presentation. In this paper, we present a system (called MPGS¿Multimedia Presentation Generator System) which supports the specification of constraints among multimedia objects and the generation of multimedia presentations according to the specified constraints. The constraint model provided by MPGS is very flexible and powerful in terms of the kinds of object constraints it can represent. A large number of innovative features are supported including: asynchronous and simultaneous spatial constraints; components of interest and priority levels; motion functions. Obviously, the flexibility provided to the users requires the development of nontrivial techniques to check constraint consistency and to generate a presentation satisfying the specified constraints. In this paper, we illustrate the solutions we have devised in the framework of MPGS.
Measuring Cache and TLB Performance and Their Effect on Benchmark Runtimes
Authors: Alan Jay Smith, Rafael H. Saavedra
Venue: IEEE Transactions on Computers (1995)

In previous research, we have developed and presented a model for measuring machines and analyzing programs, and for accurately predicting the running time of any analyzed program on any measured machine. That work is extended here by: 1) developing a high level program to measure the design and performance of the cache and TLB units; 2) using those measurements, along with published miss ratio data, to improve the accuracy of our runtime predictions; 3) using our analysis tools and measurements to study and compare the design of several machines, with particular reference to their cache and TLB performance. As part of this work, we describe the design and performance of the cache and TLB for ten machines. The work presented in this paper extends a powerful technique for the evaluation and analysis of both computer systems and their workloads; this methodology is valuable both to computer users and computer system designers.
Three Decades of HDLs: Part I, CDL Through TI-HDL
Authors: Yaohan Chu, Donald L. Dietmeyer, James R. Duley, Fredrick J. Hill, Mario R. Barbacci, Charles W. Rose, Greg Ordy, Bill Johnson, Martin Roberts
Venue: IEEE Design Test (1992)

Current hardware description languages (HDLs) benefit from the efforts of designers of hardware description languages dating back to the mid 1960s. The developers of six HDLs discuss their motivations and their views of how their work relates to the present very-high-speed integrated circuit HDLs (VHDLs). The languages discussed are Computer Design Languages (CDL). Digital Systems Design Languages (DDL). A Hardware Programming Language (AHPL), Instruction Set Processor Specifications (ISPS), Instruction Set Processor Prime (ISP'), and Texas Instruments Hardware Description Language (TI-HDL).
Integrated version and transaction group model for shared engineering databases
Authors: D. Roller, O. Eck, S. Dalakakis
Venue: Data Knowledge Engineering (2002)

This paper presents a cooperative transaction model for shared engineering databases which provides a higher degree of concurrency and process parallelism in CAD. As opposed to traditional transaction models where intra-transaction results are isolated, the presented model allows exchanging and sharing of data and supports the integration of subresults into a common solution. The realization of the transaction system is based on concepts of active and object-oriented database systems.
A Network Flow Model for Load Balancing in Circuit-Switched Multicomputers
Authors: S. H. Bokhari
Venue: IEEE Transactions on Parallel and Distributed Systems (1993)

In multicomputers that utilize circuit switching or wormhole routing, communicationoverhead depends largely on link contention-the variation due to distance between nodesis negligible. This has a major impact on the load balancing problem. In this case there are some nodes with an excess load (sources) and other with a deficit load (sinks). Amatching of sources to sinks is required to avoid contention. The problem is madecomplex by the hardwired routing on currently available machines: The user can controlonly which nodes communicate but not how the messages are routed. Network flowmodels of message flow in the mesh and the hypercube have been developed to solvethis problem. The crucial property of these models is the correspondence betweenminimum cost flows and correctly routed messages. To solve a given load balancingproblem, a minimum cost flow algorithm is applied to the network. This permits theefficient determination of a maximum contention free matching of sources to sinks that, in turn, tells how much of the given imbalance can be eliminated without contention.
A safe variant of the unsafe integer arithmetic of JavaTM
Authors: Jürgen F. H. Winkler
Venue: Software&mdash;Practice Experience (2002)

Computers are finite machines and, therefore, the arithmetic operations in a programming language are different from their mathematical counterparts. These restrictions seem not to have been, in general, fully appreciated in programming languages and in computer science textbooks. One example is the programming language Java, which makes it difficult to warn the user in cases in which arithmetic operations produce incorrect results. In this paper we look at integer arithmetic in Java and develop a safe variant of the arithmetic operations in Java. The design of the safe variant of +, -un, -bin, *, / and ** for the types byte, short, int and long reveals a number of deficiencies of Java in integer arithmetic, floating point arithmetic and program structure. Some of these deficiencies are also present in other contemporary programming languages. The paper therefore ends with some proposals for the design of the arithmetic elements of programming languages.
Heuristic Algorithms for Scheduling Iterative Task Computations on Distributed Memory Machines
Authors: Tao Yang, Cong Fu
Venue: IEEE Transactions on Parallel and Distributed Systems (1997)

Many partitioned scientific programs can be modeled as iterative executions of computational tasks and represented by iterative task graphs (ITGs). An ITG may or may not have dependence cycles. In this paper, we consider the symbolic scheduling of ITGs on distributed memory architectures with nonzero communication overhead and propose heuristic algorithms for scheduling both cyclic and acyclic ITGs without searching an entire iteration space. Our approach incorporates techniques of software pipelining, graph unfolding, directed acyclic graph (DAG) scheduling, and load balancing. We analyze the asymptotic optimality of the algorithms to show that the derived schedules are competitive to optimal solutions. We also study the sensitivity of scheduling performance on inaccurate weights. Finally, we present experimental results to demonstrate the effectiveness of the optimization techniques.
The CORDIC Algorithm: New Results for Fast VLSI Implementation
Authors: J. Duprat, J. -M. Muller
Venue: IEEE Transactions on Computers (1993)

After a brief survey of the CORDIC algorithm, some new results that allow fast and easy signed-digit implementation of CORDIC, without modifying the basic iteration step are given. A slight modification would make it possible to use a carry-save representation of numbers, instead of a signed-digit one. The method, called the branching CORDIC method, consists of performing in parallel two classic CORDIC rotations. It gives a constant normalization factor. An online implementation of the algorithm is proposed with an online delay equal to 5 for the sine and cosine functions.
An Efficient Algorithm for Mutual Exclusion Using Queue Migration in Computer Networks
Authors: V. Kumar, J. Place, G. -C. Yang
Venue: IEEE Transactions on Knowledge and Data Engineering (1991)

A nonsymmetric deadlock-free mutual exclusion algorithm for computer networks is presented. The algorithm requires O(m) messages to synchronize m modes in a lightly loaded system, and the performance approaches a constant k dependent on m as the workload increases. In a medium to heavily loaded system, it outperforms other proposed algorithms and its performance is independent of network topology.