ppxscal/embedding_network huggingface dataset:
IG-based genetically optimized fuzzy polynomial neural networks with fuzzy set-based polynomial neurons
Authors: Sung-Kwun Oh, Seok-Beom Roh, Witold Pedrycz, Tae-Chon Ahn
Venue: Neurocomputing (2007)

In this study, we introduce and investigate a new topology of fuzzy-neural networks-fuzzy polynomial neural networks (FPNN) that is based on a genetically optimized multiplayer perceptron with fuzzy set-based polynomial neurons (FSPNs). We also develop a comprehensive design methodology involving mechanisms of genetic optimization and information granulation. In the sequel, the genetically optimized FPNN (gFPNN) is formed with the use of fuzzy set-based polynomial neurons (FSPNs) composed of fuzzy set-based rules through the process of information granulation. This granulation is realized with the aid of the C-means clustering (C-Means). The design procedure applied in the construction of each layer of an FPNN deals with its structural optimization involving the selection of the most suitable nodes (or FSPNs) with specific local characteristics (such as the number of input variable, the order of the polynomial, the number of membership functions, and a collection of specific subset of input variables) and address main aspects of parametric optimization. Along this line, two general optimization mechanisms are explored. The structural optimization is realized via genetic algorithms (GAs) and HCM method whereas in case of the parametric optimization we proceed with a standard least square estimation (learning). Through the consecutive process of structural and parametric optimization, a flexible neural network is generated in a dynamic fashion. The performance of the designed networks is quantified through experimentation where we use two modeling benchmarks already commonly utilized within the area of fuzzy or neurofuzzy modeling.
Visual Verification and Analysis of Cluster Detection for Molecular Dynamics
Authors: Sebastian Grottel Guido Reina Jadran Vrabec Thomas Ertl
Venue: IEEE Transactions on Visualization and Computer Graphics (2007)

A current research topic in molecular thermodynamics is the condensation of vapor to liquid and the investigation of this process at the molecular level. Condensation is found in many physical phenomena, e.g. the formation of atmospheric clouds or the processes inside steam turbines, where a detailed knowledge of the dynamics of condensation processes will help to optimize energy efficiency and avoid problems with droplets of macroscopic size. The key properties of these processes are the nucleation rate and the critical cluster size. For the calculation of these properties it is essential to make use of a meaningful definition of molecular clusters, which currently is a not completely resolved issue. In this paper a framework capable of interactively visualizing molecular datasets of such nucleation simulations is presented, with an emphasis on the detected molecular clusters. To check the quality of the results of the cluster detection, our framework introduces the concept of flow groups to highlight potential cluster evolution over time which is not detected by the employed algorithm. To confirm the findings of the visual analysis, we coupled the rendering view with a schematic view of the clusters' evolution. This allows to rapidly assess the quality of the molecular cluster detection algorithm and to identify locations in the simulation data in space as well as in time where the cluster detection fails. Thus, thermodynamics researchers can eliminate weaknesses in their cluster detection algorithms. Several examples for the effective and efficient usage of our tool are presented.
Power-Aware Link Maintenance (PALM) for Mobile Ad Hoc Networks
Authors: Sungsoon Cho, John P. Hayes
Venue: Proceedings of the 32nd IEEE Conference on Local Computer Networks (2007)

We propose a power-aware link maintenance (PALM) algorithm for mobile ad hoc networks (MANETs) that simultaneously performs transmission power control and route connectivity maintenance. Unlike most topology control algorithms, PALM manages the transmission power of active nodes only, and thus eliminates energy and channel resource waste due to unnecessary beaconing. The basic idea of PALM is that by recording the received signal strength on packets, each node continuously estimates the required transmission power, and adapts to location changes due to mobility. We also introduce some efficient local link repair schemes. When a route change is needed due to node movement, overhearing nodes participate in data forwarding, and locally repair the route before disconnection without the need to propagate route error messages. Through these operations, PALM prevents frequent link breaks due to node mobility, reduces the occurrence of rerouting, and significantly improves network performance. Experimental results with the ns simulator confirm that PALM effectively conserves communication energy with modest overhead.
Automated Verification of Weak Equivalence within the smodels System*
Authors: Tomi Janhunen, Emilia Oikarinen
Venue: Theory and Practice of Logic Programming (2007)

In answer set programming (ASP), a problem at hand is solved by (i) writing a logic program whose answer sets correspond to the solutions of the problem, and by (ii) computing the answer sets of the program using an answer set solver as a search engine. Typically, a programmer creates a series of gradually improving logic programs for a particular problem when optimizing program length and execution time on a particular solver. This leads the programmer to a meta-level problem of ensuring that the programs are equivalent, i.e., they give rise to the same answer sets. To ease answer set programming at methodological level, we propose a translation-based method for verifying the equivalence of logic programs. The basic idea is to translate logic programs P and Q under consideration into a single logic program EQT(P,Q) whose answer sets (if such exist) yield counter-examples to the equivalence of P and Q. The method is developed here in a slightly more general setting by taking the visibility of atoms properly into account when comparing answer sets. The translation-based approach presented in the paper has been implemented as a translator called lpeq that enables the verification of weak equivalence within the smodels system using the same search engine as for the search of models. Our experiments with lpeq and smodels suggest that establishing the equivalence of logic programs in this way is in certain cases much faster than naive cross-checking of answer sets.
HD/SHD still image database system and image distribution in broadband network applications
Authors: Kayo Suzuki, Zbigniew Hulicki, Hiroaki Ikeda, Katsuhiro Ishimaru, Fumio Adachi
Venue: Computers and Electrical Engineering (2008)

This paper focuses on a practical design for an efficient scalable image database and retrieval system over broadband networks. It describes a concrete solution for the implementation of HD/SHD (high-definition/super-high-definition) still image retrieval services which can be used in different applications. The structure of the complete system, consisting of a directory server, an image server, and MMI (man-machine interface) devices, has been presented, detailing each element and their corresponding functions. The desired HD/SHD image is displayed on the HD-PDP (plasma display panel) with the aid of image matching. The proposed system generates image index automatically, eliminating special skills in preparing index images and crucially reducing the processing time (from 35min to 110s), and does not use keywords. It has been also shown that these indices can be used for quite accurate image retrieval, i.e., the system provides high precision rates (currently up to 98%) to the user, eliminating troubles encountered in the image retrieval operations due to limitation on the user's age, culture, knowledge, and languages. The broadband IP networks currently have a number of issues from the viewpoint of practical system operations, and so the requirements and issues needed for the networks are discussed from the viewpoint of in-service performance, differentiation among different types of services, secure connections, and so on, focusing on handling of HD/SHD still images.
Knowledge Acquisition Based on Human Adaptability
Authors: Tao Shang, Shuoyu Wang
Venue: Proceedings of the Fourth International Conference on Fuzzy Systems and Knowledge Discovery - Volume 02 (2007)

Intelligent behaviors of humans are based on owning knowledge and adaptive employment of knowledge, especially embodied in the adaptive settlement of unpredicted event. These imply greater adaptability of human to environmental variation as well as more intrinsic intelligence. Thus our researches address to induce human's adaptive behavior and investigate the effect of human adaptability on problem solving. In this paper, we constructed a driving simulator to induce human's adaptive action for obstacle avoidance and proposed the corresponding knowledge acquisition method based on human adaptability. Finally the resulting experiments demonstrated the characteristic of individual knowledge representing human's adaptive behavior as well as strategic variation embodying human adaptability.
On-Chip Interconnection Networks of the TRIPS Chip
Authors: Paul Gratz, Changkyu Kim, Karthikeyan Sankaralingam, Heather Hanson, Premkishore Shivakumar, Stephen W. Keckler, Doug Burger
Venue: IEEE Micro (2007)

The TRIPS chip prototypes two networks on chip to demonstrate the viability of a routed interconnection fabric for memory and operand traffic. In a 170-million-transistor custom ASIC chip, these NoCs provide system performance within 28 percent of ideal noncontended networks at a cost of 20 percent of the die area. Our experience shows that NoCs are area- and complexity-efficient means of providing high-bandwidth, low-latency on-chip communication.
Cheap Hardware Parallelism Implies Cheap Security
Authors: Onur Aciicmez, Jean-Pierre Seifert
Venue: Proceedings of the Workshop on Fault Diagnosis and Tolerance in Cryptography (2007)

Just recently pure software-based side-channel attacks against PC platforms raised lots of interests. This is due to the fact that these pure software-based side-channels could potentially undermine the ongoing trust and security efforts around the PC platform, cf. [25]. Fortunately, several follow-up works showed that these novel side-channel attacks --to a certain degree-- were relying on some very tricky Operating System or crypto software subtleties, but not on very unique CPU properties, cf. [13]. And indeed, some software countermeasures were sufficient to close those new and unforeseen information leakages in most incident cases. However, the present paper presents a new aspect within that PC oriented side-channel attack arena. Specifically, we present a novel square vs. multiplication oriented side-channel attack which is very unique to certain Simultaneous Multi Threading CPU architectures and it seems that it cannot be carried out on CPU architectures without SMT hardware assistance. The simple reason for this uniqueness of our novel attack is the fact that it doesn't rest -- as all other previous MicroArchitectural side-channel attacks -- upon a shared resource with the persistent state property between context/process switches, for e.g., caches, BTBs, etc. Instead, it is based upon the fact that Intel's Hyper- Threading technology shares the ALU's large parallel integer (floating-point) multiplier between its two hardware threads, where it is noteworthy that the multiplier obviously doesn't preserve its state during context switches. As the latest OpenSSL changes, i.e., protections against side-channels attacks are already in place, cf. [7, 8, 4], our paper doesn't introduce a new vulnerability into the OpenSSL library at all. Nevertheless, our attack has the following unintuitive property. Longer key sizes just make our attack scenario easier and not more difficult as one could assume at first sight. Thus, the present paper teaches that the sole presence of particular Multi Threading implementations requires a very deep understanding of the interplay between the underlying hardware and software, in order to appropriately judge the implied security consequences.
Fault-Tolerant Computing: An Introduction and a Perspective
Authors: C. R. Kime
Venue: IEEE Transactions on Computers (1975)

FAULT-TOLERANT computing has been defined as "the ability to execute specified algorithms correctly regardless of hardware failures, total system flaws, or program fallacies" [1]. To the extent that a system falls short of meeting the requirements of this definition, it can be labeled a partially fault-tolerant system [2]. Thus the definition of fault-tolerant computing provides a standard against which to measure all systems having a degree of fault tolerance. In particular, one can classify systems according to: 1), the amount of manual intervention required in performing three basic functions, and 2) the class of faults covered by three basic functions involved in fault tolerance: system validation, fault diagnosis, and fault masking or recovery. The word "fault" here is used to inclusively describe "failures, flaws, and fallacies" in the original definition. The first function is involved in the design and production of the system hardware and software, while the last two functions are embodied in the system itself. Likewise, the first function is directed to handling faults arising from design and production errors, whereas the last two functions are aimed at faults due to random hardware failures.
Distributed computation in wireless ad hoc grids with bandwidth control
Authors: Elisa Rondini, Stephen Hailes
Venue: Proceedings of the 5th international conference on Embedded networked sensor systems (2007)

There are many situations in which information from a Wireless Sensor Network (WSN) must be processed to provide a meaningful summary to an external agency in the minimum amount of time, all within the constraints of the processing power and bandwidth available within the network. Our interest is in supporting emergency response for indoors incidents. At present, there are only two choices about where computation might occur within a sensor network: (i) on individual sensor nodes, with the advantage of achieving substantial data reduction, decreasing the cost of transmission, and avoiding congestion; (ii) outside the sensor network, with the sensors simply supplying sinks or more powerful nodes with the data needed for the calculation. The latter approach does not require powerful nodes but necessitates a higher bandwidth network. If applications reach a level of sophistication at which they cannot be executed on a single node, then it would seem that the only option is to have processing performed centrally. The distributed systems community has proposed another solution to limited computing power on a single node: the distribution of complex applications within grids formed by high-end processors. However, since these devices are usually linked through high-speed connections, they do not experience bandwidth restrictions or congestion that are inevitable in any WSN due to the broadcast radio medium. So far, the existing approaches in this direction are hybrid, because they use clusters of nodes that rely on more powerful clusterheads to execute their computation. They tend to focus exclusively on the load availability of nodes during the distribution process, ignoring real communication issues because of the simulated environments in which they are mainly tested. The key contribution of our work is the introduction of a novel approach, which relies on distributing computation among a homogeneous grid of nodes, in an effort to port the Grid Computing paradigm within the WSNs. Moreover, we demonstrate by practical experimentation that there are significant benefits to be gained by considering local network conditions in addition to load information during distribution. We present results from our implementation of two different algorithms on real Tmote Sky sensor testbeds running the Contiki OS [3]. The first is a novel algorithm while the second is an adaptation of an already existing distribution algorithm [2], both modified to take into account real bandwidth requirements.
RCRT: rate-controlled reliable transport for wireless sensor networks
Authors: Jeongyeup Paek, Ramesh Govindan
Venue: Proceedings of the 5th international conference on Embedded networked sensor systems (2007)

Emerging high-rate applications (imaging, structural monitoring, acoustic localization) will need to transport large volumes of data concurrently from several sensors. These applications are also loss-intolerant. A key requirement for such applications, then, is a protocol that reliably transport sensor data from many sources to one or more sinks without incurring congestion collapse. In this paper, we discuss RCRT, a rate-controlled reliable transport protocol suitable for constrained sensor nodes. RCRT uses end-to-end explicit loss recovery, but places all the congestion detection and rate adaptation functionality in the sinks. This has two important advantages: efficiency and flexibility. Because sinks make rate allocation decisions, they are able to achieve greater efficiency since they have a more comprehensive view of network behavior. For the same reason, it is possible to alter the rate allocation decisions (for example, from one that ensures that all nodes get the same rate, to one that ensures that nodes get rates in proportion to their demands), without modifying sensor code at all. We evaluate RCRT extensively on a 40-node wireless sensor network testbed and show that RCRT achieves more than twice the rate achieved by a recently proposed interference-aware distributed rate-control protocol, IFRC [23].
Digital Art: When Artistic and Cultural Muse Merges with Computer Technology
Authors: Adérito Fernandes Marcos
Venue: IEEE Computer Graphics and Applications (2007)

Digital technologies have become ostensibly ubiquitous and highly expressive over the last 15 years. Today, more people are exploring innovations in information and communications technology in global communication networks, as well as in media tools, to create new aesthetical representational forms of information. In this article, the author discusses and analyzes the concepts and definitions behind digital art and the technological issues related to artistic and cultural heritage applications.
Energy transfer in a dispersion-managed Korteweg-de Vries system
Authors: Houria Triki
Venue: Mathematics and Computers in Simulation (2007)

We consider the propagation of weakly nonlinear, weakly dispersive waves in an inhomogeneous media within the framework of the variable-coefficient Korteweg-de Vries equation. An analytical formula with which to compute the energy transfer between neighboring solitary waves is derived. The resulting expression shows that the energy change in a variable KdV system is essentially due the two-wave mixing, contrary to the energy change in a nonlinear Schrodinger system, which results from the intrachannel four-wave mixing. By considering the case of Gaussian solitary wave solutions, we have determined the transfer of energy in the system analytically and numerically.
Efficient interactive query expansion with complete search
Authors: Holger Bast, Debapriyo Majumdar, Ingmar Weber
Venue: Proceedings of the sixteenth ACM conference on Conference on information and knowledge management (2007)

We present an efficient realization of the following interactive search engine feature: as the user is typing the query, words that are related to the last query word and that would lead to good hits are suggested, as well as selected such hits. The realization has three parts: (i) building clusters of related terms, (ii) adding this information as artificial words to the index such that (iii) the described feature reduces to an instance of prefix search and completion. An efficient solution for the latter is provided by the CompleteSearch engine, with which we have integrated the proposed feature. For building the clusters of related terms we propose a variant of latent semantic indexing that, unlike standard approaches, is completely transparent to the user. By experiments on two large test-collections, we demonstrate that the feature is provided at only a slight increase in query processing time and index size.
A New Class of Cellular Automata
Authors: Hosna Jabbari, Jon C. Muzio, Lin Sun
Venue: Proceedings of the 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (2007)

In this paper we present a new class of one-dimensional cellular automata which does not have the design complexity of two dimensional cellular automata but achieves higher fault coverage than the two most commonly used maximal length linear finite state machines: linear hybrid cellular automata and linear feedback shift registers. This class of cellular automata is based on a i've-cell neighbourhood, giving it a much richer transition structure, but still keeping the interconnection complexity very low. A recurrence relation is given to enable the efficient calculation of the characteristic polynomial. The effectiveness of the new cellular automata is investigated by using them as generators for built-in self-test of the ISCAS 85 and ISCAS 89 benchmark circuits. While the resulting fault coverage is never worse than using the traditional linear feedback shift register as the generator, in about half of the circuits the fault coverage is significantly improved, in some cases by more than 20%.
System Architecture for Software Peripherals
Authors: S. Choudhuri, T. Givargis
Venue: Proceedings of the 2007 Asia and South Pacific Design Automation Conference (2007)

Software peripherals (Lioupis et al., 2001) have been proposed as a design alternative to traditional peripherals. We propose a software architecture, design methodology and scheduling scheme for implementing software peripherals on general purpose processors, with fast context switch and high resolution timers. Our design flow automatically generates code for scheduling software peripherals. We demonstrate the feasibility of our proposed work by experimenting with a set of five software peripherals scheduled to execute on a MIPS processor. Our performance evaluations show that the performance impact of the software peripherals on user-level tasks is minimal (i.e., 10.11% on a 100 MHz processor) - strongly suggesting that with the right architecture, software peripherals can be efficiently accommodated in typical embedded applications.
RBoot: Software Infrastructure for a Remote FPGA Laboratory
Authors: Kushal Datta, Ron Sass
Venue: Proceedings of the 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (2007)

Traditional FPGA education either involves a physical laboratory room with workstations connected to individual FPGA experimenter boards or simulation platforms. Physical labs are expensive to maintain and require substantial floor space. In addition, students need to be physically present in the laboratories to access the FPGA boards. On the other hand, it is often the case that simulation platforms do not provide the students an adequate, in-depth understanding of concepts (such as synthesis on FPGAs). In this short paper, a third option -- a remote FPGA Laboratory -- is illustrated. This option uses software to allow students and researchers in geographically distributed locations to remotely access a pool of 64 Xilinx ML-310 Boards over the Internet. To the best of our knowledge, a remote FPGA facility of this kind is unique. The infrastructure described here gives remote users the ability to dynamically power on/off the FPGA boards, upload/download files, configure the boards online and execute synthesized designs while sending input and output through the Internet. Advantages include considerable savings in space, greater accessibility for users, ease of maintenance, and the ability to better schedule resources.