ppxscal/embedding_network huggingface dataset:
Consummating virtuality to support more polymorphism in C++
Authors: Wen-Ke Chen, Jia-Su Sun, Zhi-Min Tang
Venue: ACM SIGPLAN Notices (1997)

Inheritance together with virtual functions in C++ provides programmers much polymorphism, an important facility of object-oriented design and programming. However, they can hardly be applied to enrich a family of classes (including the base classes and their derived classes) with some common features. Multiple inheritance and virtual base classes are usually hired to solve such a problem, or templates can also be employed for the same purpose. Unfortunately, these approaches are unnatural and costly. Moreover, virtual base classes deflect from the concept of dynamic binding behind virtual functions and therefore complicate the incomplete virtuality in C++. In this paper, we demonstrate that truly virtual base classes can be utilized to solve the problem effectively and efficiently, and can be used to express explicitly what virtual base classes do implicitly in a more flexible and lucid way. In addition, they along with virtual data members can provide further polymorphism and a type-safe and efficient alternative to constrained genericity and multiple inheritance in some cases, and hence facilitate the design and implementation of extensible and portable software, especially libraries of classes.
Managing Ada development risk in a non-Ada-based workstation environment
Authors: Kourosh R. Dinyari, Thomas M. Johndrew, Kenneth J. Lamarche
Venue: Proceedings of the conference on TRI-ADA '90 (1990)

There is increasing demand for systems with user friendly interfaces to complex automation. Workstations are especially well-suited for these complex systems because interactive graphics coupled with multiprocessing capability is offered in one small platform. Unfortunately, the current available graphics workstations are essentially a hostile environment for Ada developers. However, a successful Ada implementation within project cost and schedule constraints can be achieved when the problems that cause the environment to be hostile are identified, understood, and managed. We have identified the major problems associated with Ada development in a non-Ada based workstation environment through our experience gained on three Ada implementations. These major problems relate to vendor support of Ada, not problems associated with the Ada language itself. We also identified portability problems of Ada code developed in a non-Ada based environment. Portability of Ada code between platforms of the same vendor, as well as across different vendor platforms is addressed. Because Ada developers are forced to generate Ada code that interfaces with system dependent features of non-Ada based environments, implementation risk is high unless mitigated through a risk management process. Accordingly, we present a set of criteria to be used in the platform selection process. Application of these criteria exposes hidden problems of each candidate platform, and leads to selection of the platform with the least risk. We supplement these selection criteria with development guidelines for production of more portable Ada code regardless of which platform is chosen.
Fast and Processor Efficient Parallel Matrix Multiplication Algorithms on a Linear Array With a Reconfigurable Pipelined Bus System
Authors: Keqin Li, Yi Pan, Si Qing Zheng
Venue: IEEE Transactions on Parallel and Distributed Systems (1998)

We present efficient parallel matrix multiplication algorithms for linear arrays with reconfigurable pipelined bus systems (LARPBS). Such systems are able to support a large volume of parallel communication of various patterns in constant time. An LARPBS can also be reconfigured into many independent subsystems and, thus, is able to support parallel implementations of divide-and-conquer computations like Strassen's algorithm. The main contributions of the paper are as follows: We develop five matrix multiplication algorithms with varying degrees of parallelism on the LARPBS computing model, namely, MM1, MM2, MM3, and compound algorithms ${\cal C}_1(\epsilon)$ and ${\cal C}_2(\delta).$ Algorithm ${\cal C}_1(\epsilon)$ has adjustable time complexity in sublinear level. Algorithm ${\cal C}_2(\delta)$ implies that it is feasible to achieve sublogarithmic time using o(N3) processors for matrix multiplication on a realistic system. Algorithms MM3, ${\cal C}_1(\epsilon),$ and ${\cal C}_2(\delta)$ all have o(N3) cost and, hence, are very processor efficient. Algorithms MM1, MM3, and ${\cal C}_1(\epsilon)$ are general-purpose matrix multiplication algorithms, where the array elements are in any ring. Algorithms MM2 and ${\cal C}_2(\delta)$ are applicable to array elements that are integers of bounded magnitude, or floating-point values of bounded precision and magnitude, or Boolean values. Extension of algorithms MM2 and ${\cal C}_2(\delta)$ to unbounded integers and reals are also discussed.
3D Surface Reconstruction Using Occluding Contours
Authors: Edmond Boyer, Marie-Odile Berger
Venue: International Journal of Computer Vision (1997)

This paper addresses the problem of 3D surface reconstruction using image sequences. It has been shown that shape recovery from three or more occluding contours of the surface is possible given a known camera motion. Several algorithms, which have been recently proposed, allow such a reconstruction under the assumption of a linear camera motion. A new approach is presented which deals with the reconstruction problem directly from a discrete point of view. First, a theoretical study of the epipolar correspondence between occluding contours is achieved. A correct depth formulation is then derived from a local approximation of the surface up to order two. This allows the local shape to be estimated, given three consecutive contours, without any constraints on the camera motion. Experimental results are presented for both synthetic and real data.
A 100 MHz to 1 GHz Variable Gain Amplifier in a 8 GHz 1.2&micro;m BiCMOS Process
Authors: Juha Häkkinen, Timo Rahkonen, Juha Kostamovaara
Venue: Analog Integrated Circuits and Signal Processing (1998)

A variable gain amplifier with linear gain control has been implemented in a commercially available 8 GHz 1.2 &micro;m BiCMOS process. The gain adjustment linearization is based on forcing a linearly controllable current through diode-connected transistors, thus generating an internal logarithmic control voltage for the Gilbert-type variable gain cell. A Cherry-Hopper type gain stage is used to provide most of the available gain. Thus, the maximum differential gain is 10 dB with over 1 GHz bandwidth and &minus;6.9 dBm input &minus;-1 dB compression power. Gain adjustment range of 50 dB at 200 MHz and 38 dB at 960 MHz is reported. The chip area is 1.15 &times; 2.15 mm and it consumes 40 mA from a 5 V supply.
Fast identification of untestable delay faults using implications
Authors: Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal
Venue: Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design (1997)

We propose a novel algorithm to rapidly identify untestable delay faults using pre-computed static logic implications. Our fault-independent analysis identifies large sets of untestable faults, if any, without enumerating them. The cardinalities of these sets are obtained by using a counting algorithm that has quadratic complexity in the number of lines. Since our method is based on an incomplete set of logic implications, it gives only a lower bound of the number of untestable faults. A post-processing step can list the untestable faults, if desired. Targeting untestable delay faults for test generation by an automatic test pattern generation (ATPG) tool can be avoided. The method works on the segment delay fault model and its special case, the path delay fault model, to identify robustly untestable, non-robustly untestable, and functionally unsensitizable delay faults. Results on benchmark circuits show that many delay faults are identified as untestable in a very short time. For the benchmark circuit c6288, our algorithm identified 1.978 x 10^20 functionally unsensitizable path faults in 3 CPU seconds.
DEVise (demo abstract): integrated querying and visual exploration of large datasets
Authors: M. Livny, R. Ramakrishnan, K. Beyer, G. Chen, D. Donjerkovic, S. Lawande, J. Myllymaki, K. Wenger
Venue: Proceedings of the 1997 ACM SIGMOD international conference on Management of data (1997)

DEVise is a data exploration system that allows users to easily develop, browse, and share visual presentations of large tabular datasets (possibly containing or referencing multimedia objects) from several sources. The DEVise framework, implemented in a tool that has been already successfully applied to a variety of real applications by a number of user groups, makes several contributions. In particular, it combines support for extended relational queries with powerful data visualization features. Datasets much larger than available main memory can be handled&mdash;DEVise is currently being used to visualize datasets well in excess of 100MB&mdash;and data can be interactively examined at several levels of detail: all the way from meta-data summarizing the entire dataset, to large subsets of the actual data, to individual data records. Combining querying (in general, data processing) with visualizations gives us a very versatile tool, and presents several novel challenges. Our emphasis is on developing an intuitive yet powerful set of querying and visualization primitives that can be easily combined to develop a rich set of visual presentations that integrate data from a wide range of application domains. In this demo, we will present a number of examples of the use of the DEVise tool for visualizing and interactively exploring very large datasets, and report on our experience in applying it to several real applications.
On the Enumeration and Generation of Nonweight Equivalent Rate \frac{1}{2} Convolutional Codes
Authors: Jean Conan
Venue: Designs, Codes and Cryptography (1997)

The weight equivalence of rate \frac{1}{2} binary convolutional codes and the problem of enumeration and generation of all nonweight equivalent codes is considered for a given memory order m. This is done during the generation process by first ordering the encoders into classes such that it becomes easy to recognize the weight equivalence as well as the catastrophic error propagation conditions. Subclasses of respectively self and nonself reciprocal as well as catastrophic and noncatastrophic encoders are introduced. The cardinal number of these classes and subsequently the number of &rsquo;&rsquo;nonweight equivalent&lsquo;&lsquo; codes are then computed recursively as a function of m. Finally, since all the relations amount to simple convolutions they are compactly represented by generating functions which are tabulated.
GURPR&mdash;a method for global software pipelining
Authors: Bogong Su, Shiyuan Ding, Jian Wang, Jinshi Xia
Venue: Proceedings of the 20th annual workshop on Microprogramming (1987)

The software pipelining technique is an effective approach to the optimization of loops in array processor programs and microprograms. In this paper we present a global URPR algorithm&mdash;GURPR to optimize loops of different structures based on the LURPR method we presented in 1986. We start with a brief introduction to LURPR, then discuss the pipelining of loops with abnormal entries, conditional exits, more than one path, nested loops and subroutine calls respectively. Finally we present the complete GURPR algorithm.
Correcting the Geometry and Color of Digital Images
Authors: M. Jackowski, A. Goshtasby, S. Bines, D. Roseman, C. Yu
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1997)

A unified method for correcting the geometry and color of digital images is presented. The method uses a color chart with a prearranged array of known color patches. Using the true geometry and color of the chart and geometry and color of the image of the chart, transformation functions that describe the geometry and color characteristics of the camera are determined. The transformation functions are then used to correct the geometry and color of obtained images. Experimental results of the proposed method on images acquired under different scene illuminations and camera settings are presented and evaluated.
A Subtree-Partitioning Algorithm for Inducing Parallelism in Network Simplex Dual Updates
Authors: Betty L. Hickman, Dan Scott
Venue: Computational Optimization and Applications (1997)

This paper reports on the development of a very efficient method for partitioning the network simplex basis subtree in which dual values must be updated during a pivot. The partitioning procedure may be concurrently executed by multiple processes. The resulting rapid decomposition of the subtree allows an arbitrary number of processes to be utilized in the actual dual update. This approach alleviates a primary limitation of the most efficient parallel network simplex implementation published to date. The new code performs at least as well as the previous implementation on medium-scale problems and reduces average solution time by over 34% on large-scale problems.
Concurrent Asynchronous Broadcast on the MetaNet
Authors: Yoram Ofek, Bülent Yener, Moti Yung
Venue: IEEE Transactions on Computers (1997)

The problem solved in this work is how multiple nodes in a network with an arbitrary topology can broadcast concurrently, in an asynchronous manner, to all other nodes. Asynchronous means that the nodes do not coordinate their broadcast, and, therefore, it is possible that all nodes will start to broadcast at the same time. Simultaneous broadcast by many nodes can cause traffic congestion, which can result in a traffic loss. The main property of the broadcast algorithms presented in this work is that under any arbitrary broadcast pattern there will be no packet or cell loss due to internal traffic congestion.The routing mechanism used by the broadcast algorithm can be viewed as a variant of deflection routing, which means that a node makes on-line routing decisions based on the local flow of traffic (i.e., internal load conditions). Unlike other deflection techniques, the MetaNet routing is along a global sense of direction, which guarantees that packets will reach their destinations. Thus, we call this method convergence routing (previous deflection algorithms did not guarantee deterministic routing convergence, i.e., a cell/packet can be deflected indefinitely inside the network). As a result of the convergence property, the deflection routing used in this work is the only one with broadcast capability.
Formal specification and verification of hardware: a comparative case study
Authors: V. Stavridou, H. Barringer, D. A. Edwards
Venue: Proceedings of the 25th ACM/IEEE Design Automation Conference (1988)

Formal methods are applied with increased frequency in the specification and verification of digital systems as an alternative to traditional methods of establishing correctness, such as simulation and testing. This article briefly outlines the goals and the philosophy of the HArdware VErification project at the Department of Computer Science within the University of Manchester. Our objective here is to report on the results of a first controlled experiment comparing formalisms and systems that are currently used for formally specifying and verifying both hardware and software systems. Our strategy consists of working with incrementally &ldquo;harder&rdquo; test cases, which are used to investigate the characteristics and thus the pros and cons of each formalism. The example used is a purely combinational device.
Using a network simulation package to teach the client-server model
Authors: Michael W. Dixon, Tanya J. McGill, Johan M. Karlsson
Venue: Proceedings of the 2nd conference on Integrating technology into computer science education (1997)

The client-server model is fast becoming the most common form of network architecture used in data communications. It's popularity can be seen in the phenomenal expansion of the World Wide Web. It is essential that students understand the client-server model, and that they learn how to design client-server networks and to analyze their performance. This paper describes a project to achieve this via problem solving sessions using simulation to facilitate understanding of the design and performance analysis of networks using a client-server architecture. Students will be able to gain experience designing client-server networks and testing their designs for efficiency and expandability.
Fast and Compact 16 by 16 Cellular Neural Network Implementation
Authors: Ari Paasio, Adam Dawidziuk, Kari Halonen, Veikko Porra
Venue: Analog Integrated Circuits and Signal Processing (1997)

The paper presents a Cellular Neural Network implementation based on a high gain sigmoid operation. The required simplifications to the original theory are described that allow the use of high gain. With this design black and white images can be processed. The basic building blocks in a cell are described. A 16\times 16 cells network has been designed and processed with 1.2 micron CMOS technology. Measurement results which show the operation of the network are presented.
Integrating process mapping and simulation
Authors: Charles R. Harrell, Kevin C. Field
Venue: Proceedings of the 28th conference on Winter simulation (1996)

This paper presents two different yet successful approaches that have been taken for integrating process mapping technology and simulation technology. The discussion is based on two actual implementations in which two different process mapping tools were separately integrated with ProModel simulation software. The process mapping tools used in the integration were Design/IDEF from Meta Software Corporation and ABC FlowCharter from Micrografx, Incorporated. Both of these tools have been widely adopted in government and private industries for process reengineering. Also, both tools are based on different paradigms which present unique challenges for use with simulation. Design/IDEF is based on the IDEF-O modeling paradigm which is highly structured with limited adaptability. ABC FlowCharter is an unstructured process diagramming tool which is adaptable for doing all types of diagramming. In effect, they both plug into ProModel as a front-end interface. The implementation of the bridge is different in both instances, however one approach uses a modified version of the process mapping tool while the other utilizes OLE automation without having to modify either the process mapping software or the simulation software. This presentation deals with the issues and challenges encountered in each integration effort. We will also discuss how these challenges were addressed and how a successful solution was implemented. Finally, we "I assess the suitability of integrating process mapping and simulation and compare the relative outcome of each. The successful integration of process mapping and simulation is a major step towards a complete integration of process reenginecring technologies.
NETWORK II.5 tutorial
Authors: William J. Garrison
Venue: Proceedings of the 17th conference on Winter simulation (1985)

This tutorial will acquaint the reader with a powerful modelling tool which can dramatically reduce the amount of time it takes to simulate a computer system. The NETWORK 11.5 world view and the class of problems it addresses will be discussed. A summary of NETWORK 11.5 capabilities will be presented. To tie the tutorial concepts together, an example of using NETWORK 11.5 is included.
Global illumination using local linear density estimation
Authors: Bruce Walter, Philip M. Hubbard, Peter Shirley
Venue: ACM Transactions on Graphics (TOG) (1997)

This article presents the density estimation framework for generating view-independent global illumination solutions. It works by probabilistically simulating the light flow in an environment with light particles that trace random walks origination at luminaires and then using statistical density estimation techniques to reconstruct the lighting on each surface. By splitting the computation into separate transport and reconstruction stages, we gain many advantages including reduced memory usage, the ability to simulate nondiffuse transport, and natural parallelism. Solutions to several theoretical and practical difficulties in implementing this framework are also described. Light sources that vary spectrally and directionally are integrated into a spectral particle tracer using nonuniform rejection. A new local linear density estimation technique eliminates boundary bias and extends to arbitrary polygons. A mesh decimation algorithm with perceptual calibration is introduced to simplify the Gouraud-shaded representation of the solution for interactive display.
An accelerated introductory computer science course sequence for non-traditional Master's students
Authors: J. Denbigh Starkey, Ray S. Babcock, Anne S. DeFrance
Venue: Proceedings of the twenty-eighth SIGCSE technical symposium on Computer science education (1997)

All Computer Science Departments that offer graduate degrees share a common problem---many students, with degrees in other disciplines, apply to pursue a Master's degree in Computer Science, but have to make up a large number of undergraduate deficiencies before taking graduate classes. These students are typically above traditional age, have jobs and families, and cannot easily afford to make the time commitment that is necessary to be able to complete the deficiencies before taking the classes that become their graduate program. The Computer Science Department at Montana State University has a solution to this problem.We have developed two accelerated introductory courses, CS 252 and 254, where enrollment is restricted to students who already have degrees in other disciplines. These classes, which have two lectures and six hours of laboratory work each week, replace 26 semester credits of regular coursework, and let potential graduate students remove their required undergraduate deficiencies about a year faster than would otherwise be possible.
Competition Graphs of Hamiltonian Digraphs
Authors: David R. Guichard
Venue: SIAM Journal on Discrete Mathematics (1998)

K. F. Fraughnaugh et al. proved that a graph G is the competition graph of a hamiltonian digraph possibly having loops if and only if G has an edge clique cover ${\cal C}=\{C_1,\ldots,C_n\}$ that has a system of distinct representatives. [SIAM J. Discrete Math., 8 (1995), pp. 179--185]. We settle a question left open by their work, by showing that the words "possibly having loops" may be removed.
Designing algorithms on hierarchical memory multiprocessors
Authors: Luigi Brochard, Alex Freau
Venue: Proceedings of the 4th international conference on Supercomputing (1990)

We study here the behavior of two numerical algorithms (matrix multiplications and finite difference methods) on a three-level memory hierarchy multiprocessor RP3. Using different versions of these algorithms which differ on data placement (global, local, global and cacheable, local and cacheable) and on data access (blocked on non-blocked), we study the impact of these parameters on the performance of the program. This performance analysis is done using a very accurate monitoring system (VPMC) which records instructions, memory requests, cache requests and misses. We perform also a theoretical performance analysis of these programs using a model of computation and communication. Good agreements are found between theoretical and experimental results. As a conclusion we discuss the use of local memory on such a machine and show it is not worth with the RP3 ratio of communication between local and global memories. We also discuss optimal use of cache, show the optima can only be met under some cache properties (private store-in cache with user control of write-back) and show blocked optimal algorithms are to be used to meet it.