ppxscal/embedding_network huggingface dataset:
A System for PCB Automated Inspection Using Fluorescent Light
Authors: Y. Hara, H. Doi, K. Karasaki, T. Iida
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1988)

Research was performed on the detection of faults such as shorts, cuts, and nicks in a printed circuit board pattern. The possibility was investigated of detecting a pattern by illuminating a printed circuit board with violet or ultraviolet rays and detecting the pattern using the (yellow or other) fluorescent light emitted by the base material consisting of glass-epoxy or glass-polyimide, etc. It was found that the pattern could be detected clearly by selecting an optical fiber that would separate the emitted fluorescent light from the illumination and using a detector consisting of a high-sensitivity TV camera that produces a silhouette image in which the base material is bright and the pattern is dark. A printed-circuit-board pattern inspector using this approach was developed. Test operation of the inspector in a plant demonstrated that it performs consistently good pattern inspections.
Time and Cost Evaluation Schemes of Multiple Copies of Data in Distributed Database Systems
Authors: Makoto Yoshida, Kyoko Mizumachi, Atsushi Wakino, Ikuo Oyake, Yutaka Matsushita
Venue: IEEE Transactions on Software Engineering (1985)

In comparison to centralized database systems, distributed database systems have certain advantages depending on the manner in which data are redundantly distributed. These advantages are improvement in response time, better data availability, reduction in transmission cost, etc.
A New Built-In Self-Test Design for PLA's with Hligh Fault Coverage and Low Overhead
Authors: Robert Treuer, Vinod K. Agarwal, Hideo Fujiwara
Venue: IEEE Transactions on Computers (1987)

This correspondence presents a new built-in self-test design for PLA's, that has a lower area overhead and higher multiple fault coverage (of three types of faults: crosspoint, stuck, and bridging) than any existing design. This new design uses function independent test input patterns (which are generated on chip), compresses the output responses into a function independent string of parity bits (whose fault-free expected values are generated on-line with a simple circuit), and detects all siqgle faults and more than ( 1 --2(m+2n) of all multiple faults where m and n represent the number of product terms and input variables, respectively.
Another look at automatic text-retrieval systems
Authors: Gerard Salton
Venue: Communications of the ACM (1986)

Evidence from available studies comparing manual and automatic text-retrieval systems does not support the conclusion that intellectual content analysis produces better results than comparable automatic systems.
Predicting fill for sparse orthogonal factorization
Authors: Thomas F. Coleman, Anders Edenbrandt, John R. Gilbert
Venue: Journal of the ACM (JACM) (1986)

In solving large sparse linear least squares problems A x &sime; b, several different numeric methods involve computing the same upper triangular factor R of A. It is of interest to be able to compute the nonzero structure of R, given only the structure of A. The solution to this problem comes from the theory of matchings in bipartite graphs. The structure of A is modeled with a bipartite graph, and it is shown how the rows and columns of A can be rearranged into a structure from which the structure of its upper triangular factor can be correctly computed. Also, a new method for solving sparse least squares problems, called block back-substitution, is presented. This method assures that no unnecessary space is allocated for fill, and that no unnecessary space is needed for intermediate fill.
Texture Measures for Carpet Wear Assessment
Authors: L. H. Siew, R. M. Hodgson, E. J. Wood
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1988)

Two standard approaches for texture analysis make use of numerical features of the second-order gray-level statistics, and on first-order statistics of gray-level differences, respectively. Feature sets of these types, all designed analogously, were used to analyze four sets of carpet samples exposed to different degrees of wear. It was found that some of the features extracted from the spatial gray-level-dependence matrix, neighboring gray-level-dependence matrix, gray-level difference method, and the gray-level run-length method allowed discrimination of degrees of wear in wool carpet. The methods developed could be of use in quality control.
Computing in the home: shifts in the time allocation patterns of households
Authors: Nicholas P. Vitalari, Alladi Venkatesh, Kjell Gronhaug
Venue: Communications of the ACM (1985)

An empirical study of 282 users of home computers was conducted to explore the relationship between computer use and shifts in time allocation patterns in the household. Major changes in time allocated to various activities were detected. Prior experience with computers (i.e., prior to purchase of the home computer) was found to have a significant impact on the time allocation patterns in the household. The study provides evidence that significant behavior changes can occur when people adopt personal computers in their homes.
TEX output from MACSYMA-like systems
Authors: Richard J. Fateman
Venue: ACM SIGSAM Bulletin (1987)

Programs have been written to combine MACSYMA-like algebraic manipulation programs with the TEX typesetting system. This allows a user who has computed a complex expression to easily generate commands for typesetting it accurately.
A presentation and comparison of four information system development methodologies
Authors: P Mannino
Venue: ACM SIGSOFT Software Engineering Notes (1987)

The objective of this paper is to provide a comparison of the following four information processing system development methodologies: The Box Structure Methodology, Application Prototyping, JSD and SASD. Each approach provides a unique and different set of activities that can be followed, with emphasis on different aspects of the life cycle. For this reason, no one methodology is superior in all areas and aspects of the development life cycle. However, each one is superior in its own sense, depending on the type of system being developed. The Box Structure Methodology provides a rigorous coverage of the analysis and design phases in the development life cycle, with the use of design graphics, and a design graphics language. JSD and SASD also use graphical structures as well. However, SASD relies heavily on dataflow diagrams in the analysis and design phases, where as JSD incorporates functions, time requirements, actions, and data into its diagrams in the analysis phase, and then applies them in the implementation phase, without ever going through a design step. Finally, the Application Prototyping development methodology offers an approach that centers around the development of a prototype, which is heavily dependent upon user interaction with the user in the feasibility and analysis phases, but does not offer any design, implementation, or maintenance techniques. A methodology is only approiate for a developer, once he/she has considered these fact, and determined the system's target environment.
Ternary Scan Design for VLSI Testability
Authors: M Hu, K C Smith
Venue: IEEE Transactions on Computers (1986)

In this correspondence, a new scheme is proposed in which ternary clocking signals are used to replace binary clocking signals in VLSI scan-testing designs. This scheme has the same advantage of high testability as the binary scan method [1], but it eliminates the mode- selecting signal line. Since this mode-selecting line must be routed to each flip-flop in the binary scan scheme, the saving is significant in reducing the circuit interconnection complexity and chip area. This correspondence describes the new ternary scheme in detail, and also suggests appropriate circuit designs using CMOS technology. Furthermore, comparisons are made between ternary scan and binary scan [3] and between ternary scan and a scan scheme using binary with a local decoder [2].
Markup systems and the future of scholarly text processing
Authors: James H. Coombs, Allen H. Renear, Steven J. DeRose
Venue: Communications of the ACM (1987)

Markup practices can affect the move toward systems that support scholars in the process of thinking and writing. Whereas procedural and presentational markup systems retard that movement, descriptive markup systems accelerate the pace by simplifying mechanical tasks and allowing the authors to focus their attention on the content.
Should ACM or Sigsmall/PC publish courseware?
Authors: Larry Press
Venue: ACM SIGSMALL/PC Notes (1987)

Personal computers with high-bandwidth displays, optical storage, and voice output devices offer a significant advantage for computer assisted instruction, and they will eventually become an integral part of the university curriculum. Since many of our members are teachers, perhaps ACM or our SIG should be involved in the refereeing, publishing or distribution of courseware. This paper speculates on publication options and criteria.
Validation of a Jungian instrument for MIS research
Authors: Charles H. Mawhinney, Albert L. Lederer
Venue: ACM SIGCPR Computer Personnel (1988)

The Jungian personality typology has been widely used in MIS research to investigate personal characteristics of MIS participants. The Personal Style Inventory (PSI) is a Jungian instrument in the public domain which has received little previous attention from the MIS community. Reliability, concurrent validity, and construct validity were investigated in an experiment where this instrument was directly compared with the Abbreviated Version of the Myers-Briggs Type Indicator (MBTI/AV) utilizing a sample of undergraduate business majors. Although the PSI was found to be a somewhat weaker instrument, the ability to directly incorporate it into other questionnaires makes it a useful tool for research utilizing a blind mail survey methodology.
Functional Test Generation for Digital Circuits Described Using Binary Decision Diagrams
Authors: Magdy S. Abadir, Hassan K. Reghbati
Venue: IEEE Transactions on Computers (1986)

This correspondence presents a test generation methodology for VLSI circuits described at the functional level. A VLSI circuit is modeled as a network of functional modules such as registers, adders, RAM's, and MUX's. The functions of the individual modules are described using binary decision diagrams. A functional fault model is developed independent of the implementation details of the circuit. A generalized D algorithm is proposed for generating tests to detect functional as well as gate-level faults. Algorithms which perform fault excitation, implication, D propagation, and line justification on the functional modules are also described.
The Ada ASEET team
Authors: C. McDonald
Venue: ACM SIGAda Ada Letters (1988)

The purpose of this paper is to acquaint the Ada software engineering community with the activities of the Ada Software Engineering Education and Training Team. This paper discusses the background of the Team, the present working groups, and future activities that will be sponsored by the Team. Questions concerning the Team may be addressed to any of the Team members listed at the end of this article.
Characteristics of Prototype CMOS Quaternary Logic Encoder-Decoder Circuits
Authors: J L Mangin, K W Current
Venue: IEEE Transactions on Computers (1986)

The use of quaternary logic input and output signals for delivering information on and off chip could reduce the number of required package pins or increase the amount of information conveyed on a fixed number of package pins. In this correspondence, we discuss the performance of prototype CMOS binary-to-quaternary encoder and quaternary-to-binary decoder test circuits that have been realized on a gate array IC chip.
Microprocessor architectures: a comparison based on code generation by compiler
Authors: Niklaus Wirth
Venue: Communications of the ACM (1986)

By carefully tuning computer and compiler, it is possible to avoid the otherwise inevitable compromises between complex compiling algorithms and less-than-optimal compiled code, where the key to performance appears to lie neither in sophisticated nor drastically reduced architectures, but in the key concepts of regularity and completeness.
Financing for high technology ventures
Authors: R. G. Garrick, C. M. Mayhall
Venue: Proceedings of the 1987 Fall Joint Computer Conference on Exploring technology: today and tomorrow (1987)

Over the past few years, many individuals have generated technology ideas, either spinning off from existing ventures or established new ventures to develop those technologies. Generally, the largest barrier that stands in the way of the development of such ideas is an inability to obtain financing for the venture.
Synthesis of two-party error-recoverable protocols
Authors: C V Ramamoorthy, Y Yaw, R Aggarwal, J Song
Venue: Proceedings of the ACM SIGCOMM conference on Communications architectures protocols (1986)

We have developed a correct, general, and efficient procedure of synthesizing two-party error-recoverable protocols for noisy channels where messages could be lost, corrupted, and/or missequenced. The state explosion problem has been tackled by synthesizing the error-recoverable protocol (ERP) from its noiseless local entity model using certain rules. This reduction arises from the approaches of local modeling and elaboration. We expect that these two approaches will also play a major role in tackling the complexity problems in designing multi-party protocols. Measures of efficiency and functionality improvements have been discussed.
Test Data Selection and Quality Estimation Based on the Concept of Essential Branches for Path Testing
Authors: T. Chusho
Venue: IEEE Transactions on Software Engineering (1987)

A new coverage measure is proposed for efficient and effective software testing. The conventional coverage measure for branch testing has such defects as overestimation of software quality and redundant test data selection because all branches are treated equally. These problems can be avoided by paying attention to only those branches essential for path testing. That is, if one branch is executed whenever another particular branch is executed, the former branch is nonessential for path testing. This is because a path covering the latter branch also covers the former branch. Branches other than such nonessential branches will be referred to as essential branches.
Achieving speedups for APL on an SSIMD parallel computer
Authors: Ray Greenlaw, Larry Snyder
Venue: ACM SIGAPL APL Quote Quad (1988)

This paper contains a summary of the results presented in [GS87]. In [GS87] the potential for speeding up APL by using an idealized non-shared memory parallel computer was investigated. APL's dyadic, reduction, and subscript operators were simulated on a 4-connected mesh SIMD parallel computer. The findings support the thesis that parallelism can speedup a majority of "typical" APL programs and not just those programs that are especially suited to parallelization. APL requires no sophisticated compilation techniques like Paraphase and PFC, because the operators in APL are inherently parallel.
Heuristic acceleration of force-directed placement
Authors: R. Forbes
Venue: Proceedings of the 24th ACM/IEEE Design Automation Conference (1987)

Two heuristic methods are presented for accelerating convergence of a force-directed placement problem. The first stabilizes the derivative of the repulsion force. The second uses information on device movement and instability characteristics to make a predictive extrapolation. Convergence is accelerated by replacing iterations with the faster heuristic iterations. A standard implementation from the literature is made three to four times faster by using these techniques.
Organization and analysis of a gracefully-degrading interleaved memory system
Authors: K. Cheung, G. Sohi, K. Saluja, D. Pradhan
Venue: Proceedings of the 14th annual international symposium on Computer architecture (1987)

A hardware mechanism has been proposed to reconfigure an interleaved memory system. The reconfiguration scheme is such that, at any instant all fault-free memory banks in the memory system are utilized in interleaved manner. A performance metric is defined which takes into account the bandwidth and the page-fault rate in an interleaved memory system. The reconfiguration scheme proposed in this paper is analyzed for a number of distinct programs using the performance metric defined in the paper. It is shown that the system performance degrades slowly, as the number of faulty banks increase, in a memory system using the proposed reconfiguration scheme.
An analysis of geometric modeling in database systems
Authors: Alfons Kemper, Mechtild Wallrath
Venue: ACM Computing Surveys (CSUR) (1987)

The data-modeling and computational requirements for integrated computer aided manufacturing (CAM) databases are analyzed, and the most common representation schemes for modeling solid geometric objects in a computer are described. The primitive instancing model, the boundary representation, and the constructive solid geometry model are presented from the viewpoint of database representation. Depending on the representation scheme, one can apply geometric transformations to the stored geometric objects. The standard transformations, scaling, translation, and rotation, are outlined with respect to the data structure aspects. Some of the more recent developments in the area of engineering databases with regard to supporting these representation schemes are then explored, and a classification scheme for technical database management systems is presented that distinguishes the systems according to their level of object orientation: structural or behavioral object orientation. First, several systems that are extensions to the relational model are surveyed, then the functional data model DAPLEX, the nonnormalized relational model NF2, and the database system R2D2 that provides abstract data types in the NF2 model are described.
The 1986-1987 Taulbee Survey (Computer Science Graduates, Employment Survey)
Authors: David Gries, Dorothy Marsh
Venue: Computer (1988)

The authors describe the results of a survey completed in December 1987 on the production and employment of PhDs and faculty of PhD-granting computer science/engineering departments during the academic year, 1986-7. All 123 computer science departments (111 US and 12 Canadian) participated. In addition, for the first time, 22 US departments offering the PhD in computer engineering (CE) were included. CE statistics are reported separately so that comparisons with previous years can be made for computer science (CS), but the intention is to merge all statistics for CS and CE after several years.
Bi-directional networks for large parallel processors
Authors: Matthew Moore, Charles McDowell
Venue: ACM SIGARCH Computer Architecture News (1987)

In SIMD parallel processors, the interconnection network is the subject of much design effort. A simple trick is presented which allows a multi-stage network to realize more communication patterns with the same wiring topology. Examples are given of bi-directional networks which produce several useful permutations that the standard networks cannot.
An expert system for dynamic scheduling
Authors: D Ford, S Floyd
Venue: Proceedings of the ACM SIGART international symposium on Methodologies for intelligent systems (1986)

Traditionally, scheduling problems have been viewed as static in nature (i.e., a schedule is developed for a particular planning horizon and adhered to) and were cast as having one or more clearly defined objectives (e.g., minimize overall completion time, maximize resource utilization, etc.). These problems were most commonly solved via application of optimal seeking algorithms, heuristics or simulation analysis [1] [5] [9] [10] [17]. The payload scheduling problem is representative of a class of scheduling problems which are highly dynamic in nature. That is, the various parameters can change at any time, and the objectives themselves may change also. The nature of this class of problems is such that they can be most effectively solved by knowledge based expert systems [2] [3] [8] [13] [19] [20].
Ray tracing JELL-OTM Brand Gelatin
Authors: Paul S. Heckbert
Venue: ACM SIGGRAPH Computer Graphics (1987)

Ray tracing has established itself in recent years as the most general image synthesis algorithm. Researchers have investigated ray-surface intersection calculations for a number of surface primitives, including checkerboards, glass balls, green fractal hills, mandrills, abstract blue surfaces, more glass balls, robot arms, pool balls, low-resolution clouds, morphine molecules, aquatic blobby things making strange noises, fantastic cities, and running skeletons. Unfortunately, nobody has ray traced any food. The Dessert Realism Project here at Pixar is addressing this problem. This paper presents new technology for ray tracing Jell-O reg; brand gelatin. We believe the method may have application to other brands of gelatin and perhaps pudding as well.
An Automatic Circuit Diagram Reader with Loop-Structure-Based Symbol Recognition
Authors: Akio Okazaki, Shou Tsunekawa, Takashi Kondo, Kazuhiro Mori, Eiji Kawamoto
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1988)

A high-performance logic circuit diagram reader was developed for VLSI-CAD data input. Almost all logic circuit symbols include one or more loop structures. A description is given of an efficient method for recognition of these loop-structured symbols. The proposed method consists of two processes: symbol segmentation and symbol identification. Symbol identification is achieved by a powerful hybrid method which uses heuristics to mediate between template matching and feature extraction. The entire symbol recognition process is carried out under a decision-tree control strategy. The entire recognition system for circuit diagrams is briefly explained, including character string recognition and connecting line analysis.
Safety and correct translation of relational calculus formulas
Authors: A. Van Gelder, R. Topor
Venue: Proceedings of the sixth ACM SIGACT-SIGMOD-SIGART symposium on Principles of database systems (1987)

Not all queries in relational calculus can be answered &ldquo;sensibly&rdquo; once disjunction, negation, and universal quantification are allowed. The class of relational calculus queries, or formulas, that have &ldquo;sensible&rdquo; answers is called the domain independent class, which is known to be undecidable. Subsequent research has focused on identifying large decidable subclasses of domain independent formulas In this paper we investigate the properties of two such classes the evaluable formulas and the allowed formulas. Although both classes have been defined before, we give simplified definitions, present short proofs of their man properties, and describe a method to incorporate equality. Although evaluable queries have sensible answers, it is not straightforward to compute them efficiently or correctly. We introduce relational algebra normal form for formulas from which form the correct translation into relational algebra is trivial. We give algorithms to transform an evaluable formula into an equivalent allowed formula, and from there into relational algebra normal form. Our algorithms avoid use of the so-called Dom relation, consisting of all constants appearing in the database or the query. Finally, we describe a restriction under which every domain independent formula is evaluable, and argue that evaluable formulas may be the largest decidable subclass of the domain independent formulas that can be efficiently recognized.