ppxscal/embedding_network huggingface dataset:
Consistency in replicated continuous interactive media
Authors: Martin Mauve
Venue: Proceedings of the 2000 ACM conference on Computer supported cooperative work (2000)

In this paper we investigate how consistency can be ensured for replicated continuous interactive media, i.e., replicated media which change their state in reaction to user initiated operations as well as because of the passing of time. Typical examples for this media class are networked computer games and distributed VR applications. Existing approaches to reach consistency for replicated discrete interactive media are briefly outlined and it is shown that these fail in the continuous domain. In order to allow a thorough discussion of the problem, a formal definition of the term consistency in the continuous domain is given. Based on this definition we show that an important tradeoff relationship exists between the responsiveness of the medium and the appearance of short-term inconsistencies. Until now this tradeoff was not taken into consideration for consistency in the continuous domain, thereby severely limiting the consistency related fidelity for a large number of applications. We show that for those applications the fidelity can be significantly raised by voluntarily decreasing the responsiveness of the medium. This concept is called local lag. It enables the distribution of continuous interactive media that are more vulnerable to short-term inconsistencies than, e.g., battlefield simulations. We prove that the concept of local lag is valid by describing how local lag was successfully used to ensure consistency in a 3D telecooperation application.
Virtual time synchronization over unreliable network transport
Authors: Kalyan Perumalla, Richard Fujimoto
Venue: Proceedings of the fifteenth workshop on Parallel and distributed simulation (2001)

In parallel and distributed simulations, it is sometimes desirable that the application's time-stamped events and/or the simulator's time-management control messages be exchanged over a combination of reliable and unreliable network channels. A challenge in developing infrastructure for such simulations is to correctly compute simulation time advances despite the loss of some simulation events and/or control messages. Presented here are algorithms for synchronization in distributed simulations performed directly over best-effort network transport. The algorithms are presented in a sequence of progressive refinement, starting with all reliable transport and finishing with combinations of reliable and unreliable transports for both time-stamped events and time management messages. Performance results from a preliminary implementation of these algorithms are also presented. To our knowledge, this is the first work to solve asynchronous time synchronization performed directly over unreliable network transport.
A Content-Addressable Memory Using &ldquo;Switched Diffusion Analog Memory with Feedback Circuit&rdquo;
Authors: Tomochika Harada, Shigeo Sato, Koji Nakajima
Venue: Analog Integrated Circuits and Signal Processing (2000)

For the purpose of realizing a new intelligent system and its simplified VLSI implementation, we propose a new nonvolatile analog memory called &ldquo;switched diffusion analog memory with feedback circuit (FBSDAM).&rdquo; FBSDAM has linear writing and erasing characteristics. Therefore, FBSDAM is useful for memorizing an analog value exactly. We also propose a new analog content-addressable memory (CAM) which has neural-like learning and discriminating functions which discriminate whether an incoming pattern is an unknown pattern or a stored pattern. We design and fabricate the CAM using FBSDAM by means of the 4 &mu;m double-poly single-metal CMOS process and nonvolatile analog memory technology which are developed by us. The chip size is 3.1 mm&times;3.1 mm. We estimate that the CAM is composed of 50 times fewer transistors and requires 70 times fewer calculation steps than a typical digital computer implemented using similar technology.
On self-organizing sequential search heuristics
Authors: Ronald Rivest
Venue: Communications of the ACM (1976)

This paper examines a class of heuristics for maintaining a sequential list in approximately optimal order with respect to the average time required to search for a specified element, assuming that each element is searched for with a fixed probability independent of previous searches performed. The &ldquo;move to front&rdquo; and &ldquo;transposition&rdquo; heuristics are shown to be optimal to within a constant factor, and the transposition rule is shown to be the more efficient of the two. Empirical evidence suggests that transposition is in fact optimal for any distribution of search probabilities.
Integrating an intensive experience with communication skills development into a computer science course
Authors: Lori Pollock
Venue: ACM SIGCSE Bulletin (2001)

This paper describes how a technical computer science course was transformed into an intensive communication skills course without sacrificing the technical content of the course. By integrating this experience into existing technical courses, the acquired skills are specific to the CS context without requiring an additional course. The main contribution of this paper is a set of activities which are targeted to building communications skills required for successful research in computer science at any level, but also generally useful for computer science students entering careers not involving basic research. We describe the specific methods and tools implemented in a way to provide considerable support, guidance, and feedback to students without a large investment by the professor.
Static and Dynamic Program Compilation by Interpreter Specialization
Authors: Scott Thibault, Charles Consel, Julia L. Lawall, Renaud Marlet, Gilles Muller
Venue: Higher-Order and Symbolic Computation (2000)

Interpretation and run-time compilation techniques are increasingly important because they can support heterogeneous architectures, evolving programming languages, and dynamically-loaded code. Interpretation is simple to implement, but yields poor performance. Run-time compilation yields better performance, but is costly to implement. One way to preserve simplicity but obtain good performance is to apply program specialization to an interpreter in order to generate an efficient implementation of the program automatically. Such specialization can be carried out at both compile time and run time.Recent advances in program-specialization technology have significantly improved the performance of specialized interpreters. This paper presents and assesses experiments applying program specialization to both bytecode and structured-language interpreters. The results show that for some general-purpose bytecode languages, specialization of an interpreter can yield speedups of up to a factor of four, while specializing certain structured-language interpreters can yield performance comparable to that of an implementation in a general-purpose language, compiled using an optimizing compiler.
Group participation computer demonstration
Authors: E. M. McCormick
Venue: Communications of the ACM (1963)

Engelbart1 has reported on some demonstrations in which a group functions as various parts of a digital computer. These demonstrations are concerned with binary operations including addition. However, there are occasions when it is desirable to have a group participate in a simulation which is not at this detailed level of computer operation. This note suggests a demonstration which allows a group to simulate the execution of a computer routine itself.
Least squares fitting of a great circle through points on a sphere
Authors: Leendert De Witte
Venue: Communications of the ACM (1960)

version of itself which, running as a COUNTESS program, generated machine code for the Control Data Corporation CDC-1604 computer. This second compiler was then used to generate a version of NELIAC for the CDC-1604. All three versions of NELIAC accepted essentially identical input language.
Using SMV for cryptographic protocol analysis: a case study
Authors: Yuqing Zhang, Chunling Wang, Jianping Wu, Xing Li
Venue: ACM SIGOPS Operating Systems Review (2001)

SMV is a tool for checking finite state systems. In this paper, a methodology is presented for using SMV to analyze cryptographic protocols. We illustrate the feasibility of the approach by analyzing Needham-Schroeder Public-Key Protocol and discover the well-known attack upon the protocol.
Computer organization in the breadth-first course
Authors: Grant W. Braught
Venue: Journal of Computing Sciences in Colleges (2001)

The topic of computer organization in the breadth-first CS course is addressed. A set of materials and a particular ordering of sub-topics is suggested to maximize the &ldquo;cognitive hooks&rdquo; for students. A new entry point to computer organization based on a natural physical metaphor of knobs and switches is introduced. The K S Model 1 machine simulator is developed based on the knob and switch metaphor. The K S simulator starts as a simple datapath and is built up in several carefully planned increments until a complete stored program machine is constructed. The use of the K S machine simulator is placed in context by a short discussion of how it is used to motivate the investigation of binary representation, arithmetic, logic gates and combinational logic circuits. An intuitive model for CMOS technology is introduced and used to demonstrate the tie between logic gates and transistors in the computer. Finally, some qualitative observations are offered and improvements are suggested.
Mapping Parallel Application Communication Topology to Rhombic Overlapping-Cluster Multiprocessors
Authors: Kenneth Hoganson
Venue: The Journal of Supercomputing (2000)

This paper extends research into rhombic overlapping-connectivity interconnection networks into the area of parallel applications. As a foundation for a shared-memory non-uniform access bus-based multiprocessor, these interconnection networks create overlapping groups of processors, buses, and memories, forming a clustered computer architecture where the clusters overlap. This overlapping-membership characteristic is shown to be useful for matching parallel application communication topology to the architecture's bandwidth characteristics. Many parallel applications can be mapped to the architecture topology so that most or all communication is localized within an overlapping cluster, at the low latency of processor direct to cache (or memory) over a bus. The latency of communication between parallel threads does not degrade parallel performance or limit the graininess of applications. Parallel applications can execute with good speedup and scaling on a proposed architecture which is designed to obtain maximum advantage from the overlapping-cluster characteristic, and also allows dynamic workload migration without moving the instructions or data. Scalability limitations of bus-based shared-memory multiprocessors are overcome by judicious workload allocation schemes, that take advantage of the overlapping-cluster memberships. Bus-based rhombic shared-memory multiprocessors are examined in terms of parallel speedup models to explain their advantages and justify their use as a foundation for the proposed computer architecture. Interconnection bandwidth is maximized with bi-directional circular and segmented overlapping buses. Strategies for mapping parallel application communication topologies to rhombic architectures are developed. Analytical models of enhanced rhombic multiprocessor performance are developed with a unique bandwidth modeling technique, and are compared with the results of simulation.
Professionalism in the computing field
Authors: Aaron Finerman
Venue: Communications of the ACM (1975)

The term professional means different things to different people; nevertheless, there are certain general technical and social standards normally associated with a professional. Further, the term is more generally applied to the practitioner rather than to the researcher. But within the rather broad definition specified, the computing practitioner is, as yet, not regarded as a professional. Each of the four types of institutions&mdash;academic, industry, government, and the professional society&mdash;that educate, employ, regulate, and mold the practitioner contributes to the &ldquo;nonprofessional&rdquo; status of the computing practitioner. The roles of these institutions are examined, various shortcomings are noted, and recommended changes are suggested. In the last analysis, professional status is not bestowed; it is earned. However, universities and industry, specifically, can make certain improvements to help the computing practitioner achieve professional status.
Syntactic source to source transforms and program manipulation
Authors: Jacques J. Arsac
Venue: Communications of the ACM (1979)

Syntactic transforms are the source to source program transformations which preserve the history of computation, and thus do not modify the execution time. Combined with a small number of primitive semantic transforms, they provide a powerful tool for program manipulation. A complete catalogue of syntactic transforms, and its use for solution of a system of program equations, is given. Examples of derivation of more complex source to source transformations are also presented. Two case studies illustrate the way in which syntactic and semantic source to source transformations may be used for development of clear, simple, and reasonably efficient programs.
P2EDAS: Asynchronous, Distributed Event Driven Simulation Algorithm with Inconsistent Event Preemption for Accurate Execution of VHDL Descriptions on Parallel Processors
Authors: Sumit Ghosh
Venue: IEEE Transactions on Computers (2001)

The DoD's Very high speed integrated circuit Hardware Description Language, VHDL, is aimed at allowing hardware designers to accurately describe, simulate, and validate combinational and sequential hardware designs on computers prior to building a prototype. Since its conception in the early 1980s, an important goal of VHDL has been to execute complex models concurrently and efficiently on parallel processors. To achieve this objective while exploiting the maximum theoretical parallelism, one requires a deadlock-free, asynchronous, distributed, discrete event simulation algorithm. The YADDES approach, proposed in the literature, achieves deadlock-free, distributed, discrete event simulation, but suffers from an important limitation. YADDES assumes that every entity is characterized by a single propagation delay. In contrast, for hardware entities such as gates, flip-flops, ALUs, and microprocessors, two or more propagation delay values are used corresponding to every path between the input and output. While the use of multiple delays aims at accurate representation of reality, often inconsistent events may be generated that must be detected and preempted. This paper describes a new Asynchronous, Parallel, Event Driven Simulation algorithm with inconsistent event Preemption, $P^{2}EDAS$. $P^{2}EDAS$ represents a significant advancement in that it permits the use of any number of propagation delays for every path between the input and output of every hardware entity. $P^{2}EDAS$ permits, for the first time, accurate, concurrent, asynchronous, and efficient, i.e., deadlock-free and null-message-free, execution of VHDL models of sequential and combinatorial digital designs on parallel processors. A model refers to a VHDL entity. It is a conservative algorithm in that only those output transitions, if any, are asserted at the output of a model following its execution, that are guaranteed correct. In addition, it accurately detects and preempts inconsistent events. To achieve efficiency in the simulation of actual system designs, especially large-scale designs, $P^{2}EDAS$ is designed to exploit coarse-grain parallelism, focusing on entities with significant computational complexities. $P^{2}EDAS$ is not limited to VHDL models only, it extends to hardware descriptions described in any high-level hardware description language. This paper presents a detailed description of the algorithm, illustrative examples, and mathematical proofs of correctness, freedom from deadlock, and termination of simulation in finite time. $P^{2}EDAS$ is implemented for VHDL on both a multithreaded shared memory multiprocessor and a network of Pentium-based Linux workstations, configured as a loosely coupled parallel processor. Performance analysis reveals that $P^{2}EDAS$ achieves superior speedup for a number of representative digital designs, including a large computer system¿the DLX architecture.
On the feasibility of voice input to an on-line computer processing system
Authors: Howard A. Elder
Venue: Communications of the ACM (1970)

An on-line digital computer processing system is considered in which an ordinary telephone is the complete terminal device, input to the computer being provided as a sequence of spoken words, and output to the user being audio responses from the machine. The feasibility of implementing such a system with a FORTRAN-like algebraic compiler as the object processor is considered. Details of a specific word recognition program are given. This technique depends on three simplifying restrictions, namely, a &ldquo;small&rdquo; vocabulary set, &ldquo;known&rdquo; speakers, and a &ldquo;moment of silence&rdquo; between each input word. Experimental results are presented giving error rates for different experimental conditions as well as the machine resources required to accommodate several users at a time. The results show that at this time it is both economically and logically feasible to handle at least 40 users at a time with an IBM 360/65 computer.
Safely creating correct subclasses without seeing superclass code
Authors: Clyde Ruby, Gary T. Leavens
Venue: ACM SIGPLAN Notices (2000)

A major problem for object-oriented frameworks and class libraries is how to provide enough information about a superclass, so programmers can safely create new subclasses without giving away the superclass's code. Code inherited from the superclass can call down to methods of the subclass, which may cause nontermination or unexpected behavior. We describe a reasoning technique that allows programmers, who have no access to the code of the superclass, to determine both how to safely override the superclass's methods and when it is safe to call them. The technique consists of a set of rules and some new forms of specification. Part of the specification would be generated automatically by a tool, a prototype of which is planned for the formal specification language JML. We give an example to show the kinds of problems caused by method overrides and how our technique can be used to avoid them. We also argue why the technique is sound and give guidelines for library providers and programmers that greatly simplify reasoning about how to avoid problems caused by method overrides.
Problems of storage allocation in a multiprocessor multiprogrammed system
Authors: R. J. Maher
Venue: Communications of the ACM (1961)

Multiprogramming is defined here as the use of a buffered processor by time-sharing its central control and its memory between two or more object programs under control of an executive system.
User program measurement in a time-shared environment
Authors: Alan G. Nemeth, Paul D. Dovner
Venue: Communications of the ACM (1971)

A general discussion of the measurement of software systems is followed by a description of a hardware and software scheme for measuring user programs in a time-shared environment. The TX-2 computer at MIT Lincoln Laboratory was used for the implementation of such a system and the characteristics of this implementation are reported. A scenario showing the system in use is presented. Finally, it is shown how other time-sharing systems may provide similar measuring facilities.
PDEL&mdash;a language for partial differential equations
Authors: Alfonso F. Cárdenas, Walter J. Karplus
Venue: Communications of the ACM (1970)

Conventional computer methods available to solve continuous system problems characterized by partial differential equations are very time-consuming and cumbersome. A convenient, easy to learn and to use, high level problem oriented language to solve and study partial differential equation problems has been designed; a practical translator for the language has also been designed, and a working version of it has been constructed for a significant portion of the language. This Partial Differential Equation Language, PDEL, is outlined, and the highlights of the translator are briefly summarized.
Heavy machinery for deforestation: establishing a dialogue between GHC and HUGS for program transformation development
Authors: Aaron J. Wheeler
Venue: Journal of Computing Sciences in Colleges (2001)

Functional programmers pride themselves on writing elegant and modular programs for the case with which such programs can be read, updated, and extended. In the modular style of programming, larger programs are written as compositions of smaller mix-and-match components that communicate via intermediate data structures. Unfortunately, however, intermediate data structures are a major source of inefficiency in functional programs, consuming both unnecessary time and unnecessary space. As a result, the development of techniques to remove intermediate data structures from &mdash; or deforest &mdash; functional programs is important in overcoming the inefficiencies of functional languages while reaping their benefits.
A 3-step approach for performance-driven whole-chip routing
Authors: Yih-Chih Chou, Youn-Long Lin
Venue: Proceedings of the 2001 Asia and South Pacific Design Automation Conference (2001)

We propose a 3-step approach for whole-chip detail routing. In the first step, we construct a performance-driven Steiner tree for each net ignoring the existence of other nets. In the second step, we optimally assign significant wire segments of all trees to the tracks of a two-dimensional, two-layer grid under the design rule constraint. Finally, in the third step, we complete the remaining local short connection between net terminals and those assigned wire segments and resolve any violations or congestion. We have incorporated this approach into an industrial VDSM design flow. Experimental results on large benchmark circuits implemented in a TSMC 0.18um CMOS process have demonstrated the effectiveness of the proposed approach. We achieve more than 14% improvement over a state-of-art commercial performance-driven router in a critical path delay. Our tool can be viewed as a preprocessor for a router. Users do not have to change their existing design flow. Only a small time-efficient step is needed to achieve the performance gain.
Realization of semiconductor device synthesis with the parallel genetic algorithm
Authors: Zhao Li, Xiaofeng Xie, Wenjun Zhang, Zhilian Yang
Venue: Proceedings of the 2001 Asia and South Pacific Design Automation Conference (2001)

In this presented paper, to accomplish semiconductor device synthesis for TCAD application, the Parallel Genetic Algorithm is applied as the core searching algorithm for "acceptability region" of device designables, which satisfy the designed device performance. The results of some experiments on FIBMOS are shown, which indicate the Parallel Genetic Algorithm is an efficient and fast searching algorithm to fulfill device synthesis. Some potential problems related to device synthesis are also discussed.