ppxscal/embedding_network huggingface dataset:
Data path placement with regularity
Authors: Terry Tao Ye, Giovanni De Micheli
Venue: Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design (2000)

As more data processing functions are integrated into systems-on-chip, data path is becoming a critical part of the whole VLSI design. However, traditional physical design methodology can not satisfy the data path performance requirement because it has no knowledge of the data path bit-sliced structure. In this paper, an Abstract Physical Model (APM) is proposed to extract bit-slice regularity information from Data Flow Graph (DFG) and it is used for interconnect and congestion planning. A two step heuristic algorithm is introduced to optimize the linear placement of APM to satisfy both the wire length and routing track budget.
An adaptive lapped biorthogonal transform and its application in orientation adaptive image coding
Authors: Toshihisa Tanaka, Yukihiko Yamashita
Venue: Signal Processing (2002)

We present the theory and design of an adaptive lapped biorthogonal transform for image coding. The proposed transform consists of basis functions overlapping across adjacent blocks and non-overlapping basis functions, where the basis functions' centers of symmetry are aligned. Because of the alignment, we can use the symmetric extension method at image boundaries when we transform an input image. Next, we show that the optimal non-overlapping basis functions in the minimal mean square error sense can be found by solving an eigenvalue problem without numerical search when the feasible overlapping basis functions are given. This derivation is enabled by the subspace Karhunen-Loève transform which provides the optimal approximation of an original signal in a given subspace, and which has been proposed by the present authors. We show an orientation adaptive example, where each adaptive transform is characterized by the angle of edges in image blocks. In the encoder, each block is selectively transformed by one of orientation adaptive transforms. Experimental results show that the use of adaptation improves the quality of decoded images.
Implementing Location Independent Invocation
Authors: A. P. Black, Y. Artsy
Venue: IEEE Transactions on Parallel and Distributed Systems (1990)

The problems of finding objects in large and wide-area networks where objects may change their location in volatile memory as well as on stable storage are presented. The authors discuss possible solutions and describe those adopted in the Hermes system (a corporate wide, real life office application). They have designed and developed a location-independent-invocation (LII) mechanism that combines finding with invocation, using temporal location information. The mechanism also updates the system's knowledge of an object's location as a side-effect of invocation and object migration. Assumptions about object mobility indicate that objects are likely to be found within a few propagations of an invocation. If they cannot be found in this way, stable-storage and name services are used to locate the object. The major contribution of this work is to show how LII can be achieved in a large and dynamic environment in which objects are supported by neither are operating system nor the programming language.
Making Java Work for Microcontroller Applications
Authors: Sérgio Akira Ito, Luigi Carro, Ricardo Pezzuol Jacobi
Venue: IEEE Design Test (2001)

The authors investigate complete system development using a Java machine aimed at FPGA devices. A new design strategy targets a single FPGA chip, within which the dedicated Java microcontroller-FemtoJava-is synthesized.
On Concurrent Test of Core-Based SOC Design
Authors: Yu Huang, Wu-Tung Cheng, Chien-Chung Tsai, Nilanjan Mukherjee, Omer Samman, Yahya Zaidan, Sudhakar M. Reddy
Venue: Journal of Electronic Testing: Theory and Applications (2002)

In this paper, a method to solve the resource allocation and test scheduling problems together in order to achieve concurrent test for core-based System-On-Chip (SOC) designs is presented. The primary objective for concurrent SOC test is to reduce test application time under the constraints of SOC pins and peak power consumption. The methodology used in this paper is not limited to any specific Test Access Mechanism (TAM). Additionally, it can also be applied to SOC budgeting at design phase to predict a tradeoff between test application time and SOC pins needed. The contribution of this paper is the formulation of the problem as a well-known 2-dimensional bin-packing problem. A best-fit heuristic algorithm is adopted to achieve optimal solution.
Comparison of the Acquisition Performance of the Matched Filter and Integrate-and-Dump Receivers in a Multipath Delay and Fading Environment
Authors: Hu Lan, C. J. Burkley
Venue: Wireless Personal Communications: An International Journal (1999)

The Matched Filter and the Integrate-and-Dump circuit techniques are both attractive acquisition methods for CDMA systems. Acquisition using the matched filter technique has attracted considerable interest in recent years since it shows a better performance in the presence of Gaussian noise. On the other hand acquisition using an integrate-and-dump circuit is attractive because it is less complex to implement. However, the acquisition performance can be affected significantly by the channel characteristics. In this paper, a numerical method and a computer simulation have been developed in order to compare the two acquisition systems in different propagation environments. Results show that the acquisition using a matched filter is much faster than that using the integrate-and-dump circuit for the reception of spread-spectrum signals in the presence of Gaussian noise. However, in a multipath delay and fading environment, the results show that the mean acquisition time using the matched filter is not always faster than that using the integrate-and-dump circuit. The results show that it depends on the fading, the delay, the number of users and the signal-to-noise ratio.
Avoiding Surprises: Some Thoughts on Standards
Authors: Stacy Leistner
Venue: IEEE Micro (1998)

This article describes the voluntary consensus standards process and how the American National Standards Institute (ANSI) works with both national and international standards bodies to ensure U.S. interests are well represented in the global community. Voluntary consensus standards, which are documents written by industry professionals from both the public and private sectors, are the heart of the U.S. standards system. While ANSI does not develop standards, it accredits standards developers with expertise in a particular subject to write and maintain standards documents related to that industry. For example, the IEEE has been heavily involved in the development of standards for the information technology industry. Also featured is an explanation on how standards are developed, and ANSI's role in providing neutral forums where its members identify, discuss and agree upon solutions to standards and conformity assessment issues.
Using Building Blocks to Design Analog Neuro-Fuzzy Controllers
Authors: Fernando Vidal-Verdú, Angel Rodríguez-Vázquez
Venue: IEEE Micro (1995)

Analog circuits are natural candidates to design fuzzy controller chips with optimum speed/power figures for low and medium precision applications, up to about 1%. This paper presents a parallel architecture for fuzzy controllers and a methodology for their realization in the form of analog CMOS chips. These chips can be made to learn through adaptation of some electrically-controllable parameters, guided by a dedicated hardware-compatible learning algorithm. The proposed design methodology emphasizes simplicity at the circuit level -- a prerequisite to increasing processor complexity and operation speed. It is illustrated through a three-input, four-rule controller chip in a 1.5mm CMOS single-poly, double-metal technology.
Piecewise Linear Projection Based on Self-Organizing Map
Authors: Tommy W. S. Chow, Sitao Wu
Venue: Neural Processing Letters (2002)

A piecewise linear projection algorithm, based on kohonen's Self-Organizing Map, is presented. Using this new algorithm, neural network is able to adapt its neural weights to accommodate with input space, while obtaining reduced 2-dimensional subspaces at each neural node. After completion of learning process, first project input data into their corresponding 2-D subspaces, then project all data in the 2-D subspaces into a reference 2-D subspace defined by a reference neural node. By piecewise linear projection, we can more easily deal with large data sets than other projection algorithms like Sammon's nonlinear mapping (NLM). There is no need to re-compute all the input data to interpolate new input data to the 2-D output space.
The Utilization of Matrix Structure to Generate Optimized Code from MATLAB Programs
Authors: Bret A. Marsolf, Kyle A. Gallivan, Harry A. G. Wijshoff
Venue: International Journal of Parallel Programming (1999)

The FALCON development environment was designed around three basic data representations: scalars, vectors, and dense matrices. Utilizing the FALCON interactive restructuring system, the environment has been enhanced to allow the identification of structures within sparse matrices, such as diagonal matrices or symmetric matrices, and the use of this information for improving performance of the generated code. In addition, the environment supports the modification of the representation of the data. Such modifications have been shown to provide significant performance improvements.
MMX Technology Extension to the Intel Architecture
Authors: Alex Peleg, Uri Weiser
Venue: IEEE Micro (1996)

The MMX TM Technology extension to the Intel Architecture is designed to accelerate multimedia and communications software running on Intel Architecture processors. The technology introduces new data types and instructions that implement a SIMD architecture model and is defined in a way that maintains full compatibility with all existing Intel Architecture processors, operating systems, and applications. MMX technology on average delivers 1.5 to 2 times performance gains for multimedia and communications applications in comparison to running on the same processor but without using MMX technology. This extension is the most significant addition to the Intel Architecture since the Intel I386 and will be implemented on proliferations of the Pentium processor family and also appear on future Intel Architecture processors.
Min-area retiming on flexible circuit structures
Authors: Jason Baumgartner, Andreas Kuehlmann
Venue: Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design (2001)

In this paper we present two techniques for improving min-area retiming that combine the actual register minimization with combinational optimization. First, we discuss an on-the-fly retiming approach based on a sequential And/Inverter/Register graph. With this method the circuit structure is sequentially compacted using a combination of register "dragging" and And vertex hashing. Second, we present an extension of the classical retiming formulation that allows an optimal sharing of fanin registers of And clusters, similar to traditional fanout register sharing. The combination of both techniques is capable of minimizing the circuit size beyond that possible with a standard Leiserson and Saxe retiming approach on a static netlist structure. Our work is primarily aimed at optimizing the performance of reachability-based verification methods. However, the presented techniques are equally applicable to sequential redundancy removal in technology-independent logic synthesis. A large set of experiments using benchmark and industrial circuits demonstrate the effectiveness of the described techniques.
Microcontroller Design Advantages for Portable Computing
Authors: George Milne, Ashis Khan, Simon Rayne, Juha Christensen
Venue: IEEE Micro (1997)

The ARM CPU family is widely recognized as being ideal for hand-held computing applications and there already exist a number of products using discrete CPUs. The traditional route to further reducing costs and power consumption is integration, i.e. of the peripherals with the CPU. While the ARM7100 follows this route and is the first of a series of high-integration portable computer microcontrollers, it also incorporates many innovative features, solving design, test, roadmap and time-to-market issues. The ARM7100 was the result of collaboration between Psion and ARM. Psion had specific requirements, for CPU performance, peripheral integration and low overall power consumption including a number of power management features. Prior to the ARM7100, ARM had designed a number of high-integration parts and from this experience had developed new bus architecture ideas. These were incorporated into the ARM7100 to produce a highly modular design, giving benefits to both the silicon designer and the product manufacturer. The ARM7100 can be considered in several ways: a reference design for microcontroller designers (and test engineers), enabling a fast-start for customer-specific designs, the micro component of a hardware platform for hand-held computing systems, such as portable computers, browsers or smart phones. (This system includes a vertical software offering, from device drivers and operating system, to applications complete with a developers environment), an off-the-shelf standard product enabling products to be rapidly designed without the delay or up-front development costs of an ASIC or customer-specific part, the first member of a family of ARM-powered standard parts, enabling portable computer designers to plan and implement a range of products sharing a common architecture, and development environment, This article firstly describes the ARM7100 device and then attempts to highlight key device features, in an interesting and relevant manner, by describing two new innovative products from Psion, and a new start-up company, OptionExist.
Applications performance under OSF/1 AD and SUNMOS on Intel Paragon XP/S-15
Authors: Subhash Saini, Horst D. Simon
Venue: Proceedings of the 1994 ACM/IEEE conference on Supercomputing (1994)

On Paragon, two operating systems are available: (a) OSF/1 AD, and (b) SUNMOS. The chief drawbacks of OSF/1 AD are (a) OSF/1 AD takes about 8 MB of memory on each node of the Paragon, (b) messages can be sent only at a bandwidth of 30-35 MB per second compared to 200 MB per second peak advertised rate, (c) latencies are on the order of 100 microseconds using Intel NX calls under OSF1/ AD. All these drawbacks can be minimized by using SUNMOS. SUNMOS takes only 250 KB of memory on each node and can send messages at bandwidth of 170 MB per second with latencies of 70 microseconds. We have measured the performance of applications under OSF/1 AD and SUNMOS and found that under OSF/1 AD, performance does not scale as the number of nodes increases, whereas under SUNMOS it seems to scale because of higher communication bandwidth.
A Practitioners' Review of Industrial Agent Applications
Authors: H. Van Dyke Parunak
Venue: Autonomous Agents and Multi-Agent Systems (2000)

ERIM's1 Center for Electronic Commerce (CEC) hosted a two-day Workshop on Industrial Agents (WINA) in Ann Arbor, MI on Nov. 12&ndash;13, 1998. Participation in the workshop was by invitation only, and was restricted to companies with whom the CEC is doing business or developing collaborations in agent technologies. Because of its industrial focus, the workshop's objectives have a rather different emphasis than research-oriented workshops and conferences. The projects discussed at the workshop and summarized in this report fall into three areas of increasing generality: focused applications, broadly applicable tools, and methodological guidelines.
A Synthesis Environment for Designing DSP Systems
Authors: A. E. Casavant, M. A. d'Abreu, M. Dragomirecky, D. A. Duff, J. R. Jasica, M. J. Hartman, K. S. Hwang, W. D. Smit
Venue: IEEE Design Test (1989)

The authors describe a high-level synthesis tool that addresses the broad range of throughput requirements inherent in all DSP (digital signal processor) systems. The primary role of this system, called FACE (flexible architecture compilation environment), is to provide a set of algorithms that adequately support architecturally specific hardware synthesis for a class of DSP applications. They first identify the shortcomings of Parsifal, an earlier synthesis system, and discuss the requirements for FACE. They examine briefly the architectural issues. They then describe FACE's synthesis algorithms.
Discovering Structural Association of Semistructured Data
Authors: Ke Wang, Huiqing Liu
Venue: IEEE Transactions on Knowledge and Data Engineering (2000)

Many semistructured objects are similarly, though not identically, structured. We study the problem of discovering ¿typical¿ substructures of a collection of semistructured objects. The discovered structures can serve the following purposes: 1) the ¿table-of-contents¿ for gaining general information of a source, 2) a road map for browsing and querying information sources, 3) a basis for clustering documents, 4) partial schemas for providing standard database access methods, and 5) user/customer's interests and browsing patterns. The discovery task is impacted by structural features of semistructured data in a nontrivial way and traditional data mining frameworks are inapplicable. We define this discovery problem and propose a solution.
Wearable Devices: New Ways to Manage Information
Authors: Mark Billinghurst, Thad Starner
Venue: Computer (1999)

Although the Information Age has many upsides, one of its major downsides is information overload. Indeed, the amount of information easily pushes the limit of what people can manage. This conflict drives research to seek a solution to humanity's information woes. As computers have shrunk from room size to palm size, so they have also moved from being passive accessories, such as laptops and personal digital assistants, to wearable appliances that form an integral part of our personal space. Wearable computers are always on and accessible. As the computer moves from desktop to coat pocket to the human body, its ability to help manage, sort, and filter information will become more intimately connected to our daily lives. In the next five years, expect to see wearable computing technology embedded in application-specific portable devices such as digital music players and cellular phones. By the next decade, you may have a device that gives continuous access to computing and communications resources on a machine intelligent enough to know what you're interested in, when to give it to you, and how to present it in the most appropriate manner. Artificial intelligence will augment human intelligence to make information management as natural as any other physiological function, freeing the human intellect to focus on creative rather than computational functions.
Adaptive cancellation of stationary interference in the presence of structured nonstationary interference
Authors: Michael Frey, Karl Gerlach
Venue: Signal Processing (2002)

Adaptive linear cancellation of interference is a key technique for enhancing the performance of many current and planned radar and wireless communication systems. Present methods of cancellation have limited capability when the interference is strongly nonstationary. A maximum likelihood-based cancellation procedure is given for Gaussian interference with a partially known nonstationary covariance component. This procedure is designed for adaptive cancellation implemented by a systolic cascaded array and performs well in computer Monte Carlo experiments.
Automata for the Assessment of Knowledge
Authors: Cornelia E. Dowling, Cord Hockemeyer
Venue: IEEE Transactions on Knowledge and Data Engineering (2001)

The results of this paper can be applied to construct efficient algorithms for the adaptive assessment of the students' knowledge. The problem of knowledge assessment is a special case of the problem of assessing the state of a system. These results are obtained suggesting a new assessment algorithm whose formal equivalence to previously suggested assessment algorithms is proven. A simulation study illustrates the vast improvements of efficiency with the new algorithm.
Transient power management through high level synthesis
Authors: Vijay Raghunathan, Srivaths Ravi, Anand Raghunathan, Ganesh Lakshminarayana
Venue: Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design (2001)

The use of nanometer technologies is making it increasingly important to consider transient characteristics of a circuit's power dissipation (e.g., peak power, and power gradient or differential) in addition to its average power consumption. Current transient power analysis and reduction approaches are mostly at the transistor- and logic-levels. We argue that, as was the case with average power minimization, architectural solutions to transient power problems can complement and significantly extend the scope of lower-level techniques.In this work, we present a high-level synthesis approach to transient power management. We demonstrate how high-level synthesis can impact the cycle-by-cycle peak power and peak power differential for the synthesized implementation. Further, we demonstrate that it is necessary to consider transient power metrics judiciously in order to minimize or avoid area and performance overheads. In order to alleviate the limits on parallelism imposed by peak power constraints, we propose a novel technique based on the selective insertion of data monitor operations in the behavioral description. We present enhanced scheduling algorithms that can accept constraints on transient power characteristics (in addition to the conventional resource and performance constraints). Experimental results on several example designs obtained using a state-of-the-art commercial design flow and technology library indicate that high-level synthesis with transient power management results in significant benefits -- peak power reductions of up to 32% (average of 25%), and peak power differential reductions of up to 58% (average of 42%) -- with minimal performance overheads.
Authenticating Network-Attached Storage
Authors: Benjamin C. Reed, Edward G. Chron, Randal C. Burns, Darrell D. E. Long
Venue: IEEE Micro (2000)

We present an architecture for network-authenticated disks that implements distributed file systems without file servers or encryption. Our system provides network clients with direct network access to remote storage.
Explicit Graphs in a Functional Model for Spatial Databases
Authors: M. Erwig, R. H. Güting
Venue: IEEE Transactions on Knowledge and Data Engineering (1994)

Observing that networks are ubiquitous in applications for spatial databases, we define a new data model and query language that especially supports graph structures. This model integrates concepts of functional data modeling with order-sorted algebra. Besides object and data type hierarchies, graphs are available as an explicit modeling tool, and graph operations are part of the query language. Graphs have three classes of components, namely, nodes, edges, and explicit paths. These are at the same time object types within the object type hierarchy and can be used like any other type. Explicit paths are useful because real-world objects often correspond to paths in a network. Furthermore, a dynamic generalization concept is introduced to handle heterogeneous collections of objects in a query. In connection with spatial data types, this leads to powerful modeling and querying capabilities for spatial databases, in particular for spatially embedded networks such as highways, rivers, public transport, and so forth. We use multilevel order-sorted algebra as a formal framework for the specification of our model. Roughly spoken, the first-level algebra defines types and operations of the query language, whereas the second-level algebra defines kinds (collections of types) and type constructors as functions between kinds, and so provides the types that can be used at the first level.