ppxscal/embedding_network huggingface dataset:
Collective Coordinates and Length-Scale Competition in Spatially Inhomogeneous Soliton-Bearing Equations
Authors: Angel Sánchez, A. R. Bishop
Venue: SIAM Review (1998)

Perturbed, one-dimensional, integrable (i.e., soliton-bearing) equations arise in many applied contexts when trying to improve the (usually highly idealized) description of problems of interest in terms of the purely integrable equations. In particular, when the assumption of perfect homogeneity is dropped to account for unavoidable impurities or defects, perturbations depending on the spatial coordinate must be added to the original equation. In this review, we use the one-dimensional sine-Gordon (sG) equation perturbed by a spatially periodic term as a generic paradigm to discuss the main perturbative techniques available for the study of this class of problems. To place the work in context, we summarize the approaches developed to date and focus on the collective coordinate approach as one of the most useful tools. We introduce several versions of this perturbative method and relate them to more involved procedures. We analyze in detail the application to the sG equation, but the procedure is very general. To illustrate this other examples of the application of collective coordinates are briefly revisited. In our case study, this approach helps us identify perturbative and nonperturbative regimes, yielding a very simple picture of the former. Beyond perturbative calculations, the same example of the inhomogeneous sG equation allows us to introduce a phenomenon, termed length scale competition, which we show to be a rather general mechanism for the appearance of complex spatiotemporal behavior in perturbed integrable systems, as other instances discussed in the review show. Such nonperturbative results are obtained by means of numerical simulations of the full perturbed problem; numerical linear stability analysis is also used to clarify the origins of the instability originated by this competition. To complement our description of the techniques employed in these studies, computational details of our numerical simulations are also included. Finally, the paper closes with a discussion of the above ideas and a speculative outlook on general questions concerning the interplay of nonlinearity with disorder.
Spectral Approximation of Third-Order Problems
Authors: Wilhelm Heinrichs
Venue: Journal of Scientific Computing (1999)

We consider the pseudospectral approximation of third-order problems. The spectral operator is constructed. An eigenvalue analysis with the calculation of the characteristic polynomial is presented. The eigenvalues of the spectral operator are numerically determined. An efficient preconditioner based on finite differences is constructed. Numerical results are presented.
Mixed-Mode Programmable and Scalable Architecture for On-Chip Learning
Authors: Bassem A. Alhalabi, Magdy A. Bayoumi, Bassem Maaz
Venue: Analog Integrated Circuits and Signal Processing (1999)

Typical analog VLSI architectures for on-chip learning are limited in functionality, and scale poorly under variable problem size. We present a scalable hybrid analog-digital architecture for backpropagation learning in multilayer feedforward neural networks, which integrates the flexible functionality and programmability of digital control functions with the efficiency of analog parallel neural computation. The architecture is fully scalable, both in the parallel analog functions of forward and backward signal propagation through synaptic and neural functional units (SynMod and NeuMod), and in the global and local digital functions controlling recall, learning, initialization, monitoring and built-in test. The architecture includes local provisions for long-term weight storage using refresh, which is transparent to the functional operation both during recall and learning. &ldquo;Refresh While Learning&rdquo; (RWL) provides a means to compensate for the finite precision of the quantized analog weights during learning. We include simulation results for a network of 32&times;32 neurons, mapped in parallel onto a MassPar computational engine, which validate the functionality of the architecture on simple character recognition tasks, and demonstrate robust operation of the trained network under 4-bit quantization of the weights owing to the RWL technique.
&ldquo;Square Root Domain&rdquo; Filter Design and Performance
Authors: Murat Eskiyerli, Alison Payne
Venue: Analog Integrated Circuits and Signal Processing (2000)

This paper discusses the implementation and performance of square root domain filters, which can be considered as the CMOS equivalent of the bipolar log domain technique. The square root design methodology is based on exploiting the MOSFET large-signal square law characteristic to implement filters which are input-output linear, but operate with internally non-linear signals. The design of subcircuits required for the implementation of square root domain filters is described based on the MOSFET translinear principle, and various performance issues are discussed. Simulation and measured results are also presented to confirm the validity of this approach, which may be attractive for low-voltage operation at frequencies in the MHz range.
Construction of Certain Cyclic Distance-Preserving CodesHaving Linear-Algebraic Characteristics
Authors: A. J. Van Zanten, Agung Lukito
Venue: Designs, Codes and Cryptography (1999)

An ordered list of binary words of length n is called a distance-preserving \langle m,n\rangle-code, if the list distance between two words is equal to their Hamming distance, for distances up to m. A technique for constructing cyclic \langle m,n\rangle-codes is presented, based on the standard Gray code and on some simple tools from linear algebra.
Improving the Run Time and Quality of Nested Dissection Ordering
Authors: Bruce Hendrickson, Edward Rothberg
Venue: SIAM Journal on Scientific Computing (1998)

When performing sparse matrix factorization, the ordering of matrix rows and columns has a dramatic impact on the factorization time. This paper describes an approach to the reordering problem that produces significantly better orderings than prior methods. The algorithm is a hybrid of nested dissection and minimum degree ordering, and combines an assortment of different algorithmic advances. New or improved algorithms are described for graph compression, multilevel partitioning, and separator improvement. When these techniques are combined, the resulting orderings average 39% better than minimum degree over a suite of test matrices, while requiring roughly 2.7 times the run time of Liu's multiple minimum degree.
Parallel mixed-technology simulation
Authors: Peter Frey, Radharamanan Radhakrishnan
Venue: Proceedings of the fourteenth workshop on Parallel and distributed simulation (2000)

Circuit simulation has proven to be one of the most important computer aided design (CAD) methods for the analysis and validation of integrated circuit designs. A popular approach to describing circuits for simulation purposes is to use a hardware description language such as VHDL. Similar efforts have also been carried out in the analog domain that has led to tools such as SPICE. However, with the growing trend of hardware designs that contain both analog and digital components, design environments that seamlessly integrate analog and digital circuitry are needed. Simulation of such circuit is however, exacerbated by the higher resource (CPU and memory) demands that arise when analog and digital models are integrated in a mixed-mode (analog and digital) simulation. One solution to this problem is to use PDES algorithms on a distributed platform. However, a synchronization interface between the analog and digital simulation environment is required to achieve integrated mixed-mode simulation. In this paper, we present the issues involved in the construction of synchronization protocols which support mixed-mode simulation in a distributed simulation environment. The proposed synchronization protocols provide an interface between an optimistic (Time Warp based) discrete-event simulation kernel and any continuous time simulation kernel. Empirical and formal analyses were conducted to ensure correctness and completeness of the protocols and the results of these analyses are also presented.
A General Interprocedural Framework for Placement of Split-Phase Large Latency Operations
Authors: Gagan Agrawal
Venue: IEEE Transactions on Parallel and Distributed Systems (1999)

Overlapping split-phase large latency operations with computations is a standard technique for improving performance on modern architectures. In this paper, we present a general interprocedural technique for overlapping such accesses with computation. We have developed an Interprocedural Balanced Code Placement (IBCP) framework, which performs analysis on arbitrary recursive procedures and arbitrary control flow and replaces synchronous operations with a balanced pair of asynchronous operations. We have evaluated this scheme in the context of overlapping I/O operations with computation. We demonstrate how this analysis is useful for applications which perform frequent and large accesses to disks, including applications which snapshot or checkpoint their computations or out-of-core applications.
Applied General Equilibrium Modeling with MPSGE as a GAMS Subsystem: AnOverview of the Modeling Framework and Syntax
Authors: Thomas F. Rutherford
Venue: Computational Economics (1999)

This paper describes a programming environment for economic equilibrium analysis. The system introduces the Mathematical Programming System for General Equilibrium analysis (MPSGE, Rutherford 1987) within the Generalized Algebraic Modelling System (GAMS, Brooke, Kendrick and Meeraus (1988)). This arrangement exploits GAMS&lsquo; set-oriented algebraic syntax for data manipulation and report writing. The system based on the tabular MPSGE input format provides a compact, non-algebraic representation of a model&lsquo;s nonlinear equations. This paper provides an overview of the modelling environment and three worked examples in tax policy analysis.
Dynamic delay time compensation for sampling capillaries used in respiratory mass spectrometry
Authors: Luc Eberhard, Christoph Haberthür, Ben Fabry, Josef Guttmann
Venue: Technology and Health Care (1999)

In intensive care patients who receive ventilatory support or full mechanical ventilation, valuable information can be drawn from gas exchange measurements. In this setting, the most favorable method for gas exchange measurement is by simultaneous recording of gas concentrations and gas flow, and by time resolved multiplication and accumulation. This paper presents a new method to compensate for the signal delay time which occurs when a sampling capillary is used for measuring gas concentrations with a respiratory mass spectrometer or some equivalent sidestream gas analyzer. The signal delay of gas concentrations must be accurately compensated to avoid error accumulation in gas exchange calculation. A delay time can be easily measured with a test gas in a laboratory setup and be readily compensated for during the measurements in a ventilated patient. This is a standard procedure which gives reasonable results under normal conditions. Special attention is however required in cases where the gas viscosity changes due to large changes in gas composition, e.g., those used for diagnostic breathing or ventilatory maneuvers. Such changes of viscosity will influence the delay time of the capillary, because they affect its flow resistance. As a consequence they will degrade the quality of measurements when done with a simple fixed delay compensation. The method described here consists of an algorithm which enables compensation for such a temporally changing delay time due to changes in gas composition.
Stable Internet routing without global coordination
Authors: Lixin Gao, Jennifer Rexford
Venue: ACM SIGMETRICS Performance Evaluation Review (2000)

The Border Gateway Protocol (BGP) allows an autonomous system (AS) to apply diverse local policies for selecting routes and propagating reachability information to other domains. However, BGP permits ASes to have conflicting policies that can lead to routing instability. This paper proposes a set of guidelines for an AS to follow in setting its routing policies, without requiring coordination with other ASes. Our approach exploits the Internet's hierarchical structure and the commercial relationships between ASes to impose a partial order on the set of routes to each destination. The guidelines conform to conventional traffic-engineering practices of ISPs, and provide each AS with significant flexibility in selecting its local policies. Furthermore, the guidelines ensure route convergence even under changes in the topology and routing policies. Drawing on a formal model of BGP, we prove that following our proposed policy guidelines guarantees route convergence. We also describe how our methodology can be applied to new types of relationships between ASes, how to verify the hierarchical AS relationships, and how to realize our policy guidelines. Our approach has significant practical value since it preserves the ability of each AS to apply complex local policies without divulging its BGP configurations to others.
Student well-being in a computing department
Authors: J. R. Davy, K. Audin, M. Barkham, C. Joyner
Venue: Proceedings of the 5th annual SIGCSE/SIGCUE ITiCSEconference on Innovation and technology in computer science education (2000)

We describe a project exploring the relationships between factors in the learning environment, student well-being and learning outcomes, in the context of a Computing department. A range of established psychometric tests identified areas of unhelpful stress in the working environment and measures were implemented to rectify these. A significant improvement in measured student well-being followed.
Efficient incremental rerouting for fault reconfiguration in field programmable gate arrays
Authors: Shantanu Dutt, Vimalvel Shanmugavel, Steve Trimberger
Venue: Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design (1999)

The ability to reconfigure around manufacturing defects and operational faults increases FPGA chip yield, reduces system downtime and maintenance in field operation, and increases reliabilities of mission- and life-critical systems. The fault reconfiguration technique discussed in this work use the principle of node covering in which reconfiguration is achieved by constructing replacement chains of cells from faulty cells to spare/unused ones. A key issue in such reconfiguration is efficient incremental rerouting in the FPGA. Previous methods for node-covering based reconfiguration are &ldquo;static&rdquo; in the sense that extra interconnects are added a-priori as part of the initial circuit routing so that a specific fault pattern (e.g., one fault per row) can be tolerated [1]. This, however, results in worst-case track overheads and also in an inflexibility to tolerate other realistic fault patterns. In this paper, we develop dynamic reconfiguration and incremental rerouting techniques that are fault specific. In this approach, the FPGA is initially routed without any extra interconnects for reconfiguration. When faults occur, the routed nets have to be minimally perturbed to allow these interconnects to be inserted &ldquo;on-the-fly&rdquo; for reconfiguration. These requirements are addressed in our minimally incremental rerouting technique Conv_T-DAG, which uses a cost-directed depth-first search strategy. We prove several results that establishes the near-optimality of Conv_T-DAG in terms of track overhead. To the best of our knowledge, this is the first time that an incremental rerouting technique has been developed for FPGAs. For several benchmark circuits, the static approach to tolerating one fault per row resulted in a 43% to 34% track overhead. Using the dynamic reconfiguration approach and Conv_T-DAG results in an average overhead of only 16%&mdash;an improvement of more than 50%. Over all circuits, the reconfiguration time per fault ranges from 16.8 to 72.9 secs. Simulation of smaller fault sets of one to four faults show very small track overheads ranging from 1.75% to 4.49%. Conv_T-DAG can also be used for interconnect fault tolerance.
Process-oriented approach for role-finding to implement role-based security administration in a large industrial organization
Authors: Haio Roeckle, Gerhard Schimpf, Rupert Weidinger
Venue: Proceedings of the fifth ACM workshop on Role-based access control (2000)

In this paper we describe the work in progress with a process-oriented approach for role-finding to implement Role-Based Security Administration. Our results stem from using a recently proposed role model and procedural model at Siemens AG ICN, a large industrial organization. The core of this paper presents the data model, which integrates business processes, role based security administration and access control. Moreover, a structured top-down approach is outlined which is the basis for derivation of suitable business roles from enterprise process models. A brief description is given on how these results may be used to first build the Role Catalog and then support the implementation of RBAC and a single point of administration and control, using a cross-platform administration tool.
Quasi-Shuffle Products
Authors: Michael E. Hoffman
Venue: Journal of Algebraic Combinatorics: An International Journal (2000)

Given a locally finite graded set A and a commutative, associative operation on A that adds degrees, we construct a commutative multiplication &ast; on the set of noncommutative polynomials in A which we call a quasi-shuffle product&semi; it can be viewed as a generalization of the shuffle product III. We extend this commutative algebra structure to a Hopf algebra (U, &ast;, &Delta;)&semi; in the case where A is the set of positive integers and the operation on A is addition, this gives the Hopf algebra of quasi-symmetric functions. If rational coefficients are allowed, the quasi-shuffle product is in fact no more general than the shuffle product&semi; we give an isomorphism exp of the shuffle Hopf algebra (U, III, &Delta;) onto (U, &ast;, &Delta;) the set L of Lyndon words on A and their images &lcub; exp(w) &mid; w &epsis; L&rcub; freely generate the algebra (U, &ast;). We also consider the graded dual of (U, &ast;, &Delta;). We define a deformation &ast;_q of &ast; that coincides with &ast; when q &equals; 1 and is isomorphic to the concatenation product when q is not a root of unity. Finally, we discuss various examples, particularly the algebra of quasi-symmetric functions (dual to the noncommutative symmetric functions) and the algebra of Euler sums.
A measurement analysis of Internet traffic over frame relay
Authors: Judith L. Jerkins, John Monroe, Jonathan L. Wang
Venue: ACM SIGMETRICS Performance Evaluation Review (1999)

Various approaches have been proposed and implemented to relieve the congestion in the Public Switched Telephone Networks (PSTNs) induced by recent meteoric growth of Internet services. The Internet/Intranet Transport Service (IITS) offered by the Southwestern Bell Telephone (SWBT) Company provides an example of one such implementation which off-loads the long-holding time data traffic from PSTNs to a packet technology (in this case Frame Relay).This paper describes analysis of 1997 IITS traffic jointly performed by SWBT and Bellcore with the goal of gaining insights into the nature of the Internet traffic over the Frame Relay technology, and deriving practical traffic engineering guidelines for efficiently managing the network elements to provide Quality-of-Service (QoS) to customers. The analysis was carried out at the frame level as well as the call level. The results demonstrate that traffic (both frame and byte count processes) at the frame level is self-similar with long-range dependent characteristics, while call arrivals are inhomogeneous Poisson processes and call holding times have heavy tails. Frame size statistics are explored, revealing a packet fragmentation issue that can unnecessarily decrease resource efficiency. The impacts of load balancing schemes (implemented by the equipment suppliers) on the traffic characteristics is also observed.
Projection Learning
Authors: Leslie G. Valiant
Venue: Machine Learning (1999)

A method of combining learning algorithms is described that preserves attribute-efficiency. It yields learning algorithms that require a number of examples that is polynomial in the number of relevant variables and logarithmic in the number of irrelevant ones. The algorithms are simple to implement and realizable on networks with a number of nodes linear in the total number of variables. They include generalizations of Littlestone&lsquo;s Winnow algorithm, and are, therefore, good candidates for experimentation on domains having very large numbers of attributes but where nonlinear hypotheses are sought.
Decidability and undecidability results for boundedness of linear recursive queries
Authors: Moshe Y. Vardi
Venue: Proceedings of the seventh ACM SIGACT-SIGMOD-SIGART symposium on Principles of database systems (1988)

If it is possible to eliminate recursion from a Datalog program P, then P is said to be bounded. It was shown by Gaifman et al that the problem of deciding whether a given Datalog program is bounded is undecidable, even for linear programs that has one 4-ary intensional predicate. We sharpen that result by showing that the problem of deciding whether a given Datalog program is bounded is undecidable, even for linear programs that has one binary intensional predicate. We then consider linear programs with a single recursive rule. We show that if the intensional predicate is binary, then the boundedness problem for such program is decidable, in fact, it is NP-complete.
IO-Lite: a unified I/O buffering and caching system
Authors: Vivek S. Pai, Peter Druschel, Willy Zwaenepoel
Venue: ACM Transactions on Computer Systems (TOCS) (2000)

This article presents the design, implementation, and evaluation of IO -Lite, a unified I/O buffering and caching system for general-purpose operating systems. IO-Lite unifies all buffering and caching in the system, to the extent permitted by the hardware. In particular, it allows applications, the interprocess communication system, the file system, the file cache, and the network subsystem to safely and concurrently share a single physical copy of the data. Protection and security are maintained through a combination of access control and read-only sharing. IO-Lite eliminates all copying and multiple buffering of I/O data, and enables various cross-subsystem optimizations. Experiments with a Web server show performance improvements between 40 and 80% on real workloads as a result of IO-Lite.