ppxscal/embedding_network huggingface dataset:
Comments on a technique for counting ones
Authors: P. M. Sherman
Venue: Communications of the ACM (1960)

Peter Wegner [1] describes a short 704 SAP program that is faster than the standard technique. The expected number of loops&mdash;of five instructions each&mdash;for a word half of whose bits are ones, is 18 in this program.
The Online Transportation Problem
Authors: Bala Kalyanasundaram, Kirk R. Pruhs
Venue: SIAM Journal on Discrete Mathematics (2000)

We study the online transportation problem under the assumption that the adversary has only half as many servers at each site as the online algorithm. We show that the GREEDY algorithm is $\Theta( {\rm min}(m, \lg C))$-competitive under this assumption, where m is the number of server sites and C is the total number of servers. We then present an algorithm BALANCE, which is a simple modification of the GREEDY algorithm, that is, O(1)-competitive under this assumption.
Enforcing workflow authorization constraints using triggers
Authors: Fabio Casati, Silvana Castano, Maria Grazia Fugini
Venue: Journal of Computer Security (1998)

Workflow design involves modeling different aspects of a business process. Among these aspects, workflow design should consider also security requirements. These relate to the authorizations for the users in the organization to execute workflow tasks according to the security policies about handling business processes and workflow data. This paper presents an approach based on triggers to specify and enforce workflow authorization constraints for a flexible assignment of tasks to roles and agents. The approach has been conceived in the framework of the WIDE Workflow Management System. Authorization triggers specify when and how the set of authorizations for a given workflow should be changed and which actions should be taken by the system or by the administrator. A basic set of triggers is provided enforcing security policies common to workflow systems, such as need-to-know and task confinement. Methodological issues related to trigger design for a given workflow application are discussed and an approach based on authorization patterns is illustrated. The paper shows how authorization patterns can be instantiated into triggers and briefly discusses aspects related to the analysis of a set of authorization triggers defined for a given workflow application.
Approximation algorithms for the 0-extension problem
Authors: Gruia Calinescu, Howard Karloff, Yuval Rabani
Venue: Proceedings of the twelfth annual ACM-SIAM symposium on Discrete algorithms (2001)

In the 0-extension problem, we are given a weighted graph with some nodes marked as terminals and a semi-metric on the set of terminals. Our goal is to assign the rest of the nodes to terminals so as to minimize the sum, over all edges, of the product of the edge's weight and the distance between the terminals to which its endpoints are assigned. This problem generalizes the multiway cut problem of Dahlhaus, Johnson, Papadimitriou, Seymour, and Yannakakis and is closely related to the metric labeling problem introduced by Kleinberg and Tardos. We present approximation algorithms for O-EXTENSION. In arbitrary graphs, we present an &Ogr;(log k)-approximation algorithm, k being the number of terminals. We also give &Ogr;(1)-approximation guarantees for weighted planar graphs. Our results are based on a natural metric relaxation of the problem, previously considered by Karzanov. It is similar in flavor to the linear programming relaxation of Garg, Vazirani, and Yannakakis for the multicut problem and similar to relaxations for other graph partitioning problems. We prove that the integrality ratio of the metric relaxation is at least c&radic;lgk for a positive c for infinitely many k. Our results improve some of the results of Kleinberg and Tardos and they further our understanding on how to use metric relaxations.
Trace-driven steady-state probability estimation in FSMs with application to power estimation
Authors: D. Marculescu, R. Marculescu M. Pedram
Venue: Proceedings of the conference on Design, automation and test in Europe (1998)

This paper illustrates, analytically and quantitatively, the effect of high-order temporal correlations on steady-state and transition probabilities in finite state machines (FSMs). As the main theoretical contribution, we extend the previous work done on steady-state probability calculation in FSMs to account for complex spatiotemporal correlations which are present at the primary inputs when the target machine models real hardware and receives data from real applications. More precisely: 1) using the concept of constrained reachability analysis, the correct set of Chapman-Kolmogorov equations is constructed; and 2) based on stochastic complementation and iterative aggregation/disaggregation techniques, exact and approximate methods for finding the state occupancy probabilities in the target machine are presented. From a practical point of view, we show that assuming temporal independence or even using first-order temporal models is not sufficient due to the inaccuracies induced in steady-state and transition probability calculations. Experimental results show that, if the order of the source is underestimated, not only the set of reachable sets is incorrectly determined, but also the steady-state probability values can be more than 100% off from the correct ones. This strongly impacts the accuracy of the total power estimates that can be obtained via probabilistic approaches.
Porting from IRIX to Linux
Authors: George Koharchik, Brian Roberts
Venue: Linux Journal (2001)

Coding for portability to Linux: examples from the ACRT land vehicle port.
Whole program compilation for embedded software: the ADSL experiment
Authors: A. Johan Cockx
Venue: Proceedings of the ninth international symposium on Hardware/software codesign (2001)

The increasing complexity and decreasing time-to-market of embedded software forces designers to write more modular and reusable code, using for example object-oriented techniques and languages such as C++. The resulting memory and runtime overhead cannot be removed by traditional optimizing compilers; a global, whole program analysis is required. To evaluate the potential of whole program optimization techniques, we have manually optimized the embedded software of a commercial ADSL modem. Using only techniques that can be automated, a memory footprint reduction of newly 60% has been achieved. We conclude that a consistent and aggressive use of whole system optimization techniques is feasible and worthwhile, and that the implementation of such techniques in a compiler for embedded software will allow software designers to write more modular and reusable code without suffering the associated implementation overhead.
Sorting on a mesh-connected parallel computer
Authors: C. D. Thompson, H. T. Kung
Venue: Communications of the ACM (1977)

Two algorithms are presented for sorting n2 elements on an n &times; n mesh-connected processor array that require O (n) routing and comparison steps. The best previous algoritmhm takes time O(n log n). The algorithms of this paper are shown to be optimal in time within small constant factors. Extensions to higher-dimensional arrays are also given.
A CS/SE approach to a real-time embedded systems software development course
Authors: Joseph M. Clifton
Venue: ACM SIGCSE Bulletin (2001)

This paper describes an approach to a course in real-time embedded systems that focuses on software development issues. The course attempts to integrate topics from traditional computer science, infuse software engineering principles, and give some exposure to hardware concerns. Another important component of the course is experience with developing software for multiple platforms.
Pattern matching for sets of segments
Authors: Alon Efrat, Piotr Indyk, Suresh Venkatasubramanian
Venue: Proceedings of the twelfth annual ACM-SIAM symposium on Discrete algorithms (2001)

In this paper we present algorithms for a number of problems in geometric pattern matching where the input consist of a collections of segments in the plain. Our work consists of two main parts. In the first, we address problems and measures that relate to collections of orthogonal line segments in the plane. Such collections arise naturally from problems in mapping buildings and robot exploration. We propose a new measure of segment similarity called a coverage measure, and present efficient algorithms for maximising this measure between sets of axis-parallel segments under translations. Our algorithms run in time &Ogr;(n3polylogn) in the general case, and run in time &Ogr;(n3polylogn) for the case when all segments are horizontal. In addition, we show that when restricted to translations that are only vertical, the Hausdorff distance between two sets of horizontal segments can be computed in time roughly &Ogr;(n3/2polylog n). These algorithms are significant improvements over the general algorithm of Chew et al. that takes time &Ogr;(n4 log2 n). In the second part of this paper we address the problem of matching polygonal chains. We study the well known Fr&eacute;chet distance, and present the first algorithm for computing the Fr&eacute;chet distance under general translations. Our methods also yield algorithms for computing a generalization of the Fr&eacute;chet distance, and we present a simple approximation algorithm for the Fr&eacute;chet distance and its generalization that runs in time &Ogr;(n2polylogn).
A CMOS Offset Phase Locked Loop for a GSM Transmitter
Authors: Taizo Yamawaki, Masaru Kokubo, Hiroshi Hagisawa
Venue: Analog Integrated Circuits and Signal Processing (2000)

This paper describes a CMOS offset phase locked loop (OPLL) for a global system for mobile communications (GSM) transmitter. The OPLL is a PLL with a down-conversion mixer in the feedback path and is used in the transmit (Tx) path as a frequency converter. It has a tracking bandpass filter characteristic in such a way that the OPLL can suppress the noise in the GSM receiving band (Tx noise) without a duplexer. When the loop bandwidth of the OPLL was 1.0 MHz, the Tx noise level of &minus;163.5 dBc/Hz, the phase error of 0.66&deg; rms, and the settling time of 40 &mu;s were achieved. The IC was implemented by using 0.35-&mu;m CMOS process. It takes 860 &mu;m&times;620 &mu;m of total chip area and consumes 17.6 mA with a 3.0 V power supply.
The future of automatic digital computers
Authors: Andrew D. Booth
Venue: Communications of the ACM (1960)

Before discussing the future I want to talk about the past, which I find a source of disappointment. One of the things which prompted me to give the lecture its title was that a number of people who should know better have recently given tongue and pen to the statement that &ldquo;new, second generation computers are with us&rdquo; and that these machines are better than anything which has been thought of before. The first part of this lecture will attempt to disabuse you of this idea for, far from thinking that any second generation computer exists, I think that we are only just seeing the growing up of first generation computers. To justify this statement I remark that, in 1946-7, I worked with the late John von Neumann on the logical and physical design of computing machines. Von Neumann wrote, at the Institute for Advanced Study at Princeton, two reports [1, 2] on aims and objectives to which we may look to see the type of computer which was envisaged at that time. This computer was in fact a machine having, in retrospect, certain rather interesting characteristics. The most obvious of these is speed of operation and this was desired to be such that a 40 bit addition or subtraction would take about 10 micro-seconds. There is no computing machine commercially available in this country which achieves this addition time. The multiplication time of the von Neumann machine varied from 400 micro-seconds for the crudest scheme to 50 micro-seconds for a more sophisticated logical device which still made no use of the steam-roller electronics to be seen in at least one machine of the present day, which achieves a rather worse performance. So much for second generation speed!
Web-based simulation: revolution or evolution?
Authors: Ernest H. Page, Arnold Buss, Paul A. Fishwick, Kevin J. Healy, Richard E. Nance, Ray J. Paul
Venue: ACM Transactions on Modeling and Computer Simulation (TOMACS) (2000)

The nature of the emerging field of web-based simulation is examined in terms of its relationship to the fundamental aspects of simulation research and practice. The presentation, assuming a form of debate, is based on a panel session held at the first International Conference on Web-Based Modeling and Simulation, which was sponsored by the Society for Computer Simulation during 11-14 January 1998 in San Diego, California. While no clear &ldquo;winner&rdquo; is evident in this debate, the issues raised here certainly merit ongoing attention and contemplation.
The LACONIQ monitor: time sharing for online dialogues
Authors: Daniel L. Drew
Venue: Communications of the ACM (1967)

The LACONIQ (Laboratory Computer Online Inquiry) Monitor was developed primarily to support non-numerical applications such as retrieval from very large files by means of a &ldquo;dialogue&rdquo; between a system user and a retrieval application. The monitor was designed so that it could work with a small computer (an IBM System 360/30). Therefore techniques for resource allocation were important. For this reason the use of core storage, computational facilities, and input-output were all scheduled. An unusual feature of the system is that it is event-driven rather than clock-driven. The program segments called into execution by the remote CRT consoles are invariably run to completion rather than &ldquo;rolled-out&rdquo; to be brought back at a later time.
Sticks and stones: a coding scheme for parameterized verification
Authors: Amir Pnueli
Venue: Proceedings of the twentieth annual ACM symposium on Principles of distributed computing (2001)

We consider the problem of Uniform Algorithmic Verification of Parameterized Systems, which requires establishing in a single verification effort the correctness of a parameterized family of systems for any value of the parameter. As has been observed by several researchers, using regular expressions or equivalent formalisms (e.g. WS1S) as assertional language, we can perform symbolic model checking of systems of unbounded number of states. We start by showing that the verification problem can be viewed as taking place in a space of 3 dimensions: Time, Control, and Data. We will illustrate how regular expressions can be naturally applied to deal with any of these dimensions in case it becomes unbounded. Unfortunately, extending the tool of regular expressions to 2 dimension leads to undecidability. We therefore consider alternate ways of dealing with systems which have both unbounded control and unbounded data. By appropriate abstractions and encoding it is frequently possible to encode these two dimensions within a single dimension, using a coding scheme to which we refer as &ldquo;sticks and stones&rdquo;. The method will be illustrated on parameterized versions of the Bakery and Peterson's algorithms for mutual exclusion. Among other things, we will show that, in some cases, we can use languages more expressive than regular expressions and still get manageable verification algorithms. This is, for example, the case of Peterson's algorithm for N processes, which cannot be analyzed in terms of purely regular expressions.
Information retrieval on the web
Authors: Mei Kobayashi, Koichi Takeda
Venue: ACM Computing Surveys (CSUR) (2000)

In this paper we review studies of the growth of the Internet and technologies that are useful for information search and retrieval on the Web. We present data on the Internet from several different sources, e.g., current as well as projected number of users, hosts, and Web sites. Although numerical figures vary, overall trends cited by the sources are consistent and point to exponential growth in the past and in the coming decade. Hence it is not surprising that about 85% of Internet users surveyed claim using search engines and search services to find specific information. The same surveys show, however, that users are not satisfied with the performance of the current generation of search engines; the slow retrieval speed, communication delays, and poor quality of retrieved results (e.g., noise and broken links) are commonly cited problems. We discuss the development of new techniques targeted to resolve some of the problems associated with Web-based information retrieval and speculate on future trends.
A null-object detection algorithm for constructive solid geometry
Authors: Robert B. Tilove
Venue: Communications of the ACM (1984)

Constructive solid geometry (CSG) is the primary scheme used for representing solid objects in many contemporary solid modeling systems. A CSG representation is a binary tree whose nonterminal nodes represent Boolean operations and whose terminal nodes represent primitive solids. This paper deals with algorithms that operate directly on CSG representations to solve two computationally difficult geometric problems&mdash;null-object detection (NOD) and same-object detection (SOD). The paper also shows that CSG trees representing null objects may be reduced to null trees through the use of a new concept called primitive redundancy, and that, on average, tree reduction can be done efficiently by a new technique called spatial localization. Primitive redundancy and spatial localization enable a single complex instance of NOD to be converted into a number of simpler subproblems and lead to more efficient algorithms than those previously known.
A Smart-Scanning Analog VLSI Visual-Attention System
Authors: Tonia G. Morris, Stephen P. De Weerth
Venue: Analog Integrated Circuits and Signal Processing (1999)

We have implemented a hardware model of selective visual attention within the neuromorphic, analog VLSI paradigm. The system includes a highly-parallel winner-take-all selection with excitatory and inhibitory influences. The selection specifies positions of attention based on an array of intensity levels, which comprise a primitive saliency map. The excitation and inhibition control the strategy for shifts of attention from one position to the next. The combination of these fundamental building blocks demonstrates emergent properties that can be observed in real time due to the parallel hardware implementation. The system behaves as a smart-scanning sensor array. The basic characteristics of the scanning pattern are controlled by setting a number of analog parameters. In this paper we describe the system, focusing on the role that inhibition plays in the redirection of attention. We show experimental results from one-dimensional implementations of the hardware model. Analysis that explains the expected behavior for the two-element mode of operation is presented. The theoretical predictions are compared to experimental results.
Key management for encrypted broadcast
Authors: Avishai Wool
Venue: ACM Transactions on Information and System Security (TISSEC) (2000)

We consider broadcast applications where the transmissions need to be encrypted, such as direct broadcast digital TV networks or Internet multicast. In these applications the number of encrypted TV programs may be very large, but the secure memory capacity at the set-top terminals (STT) is severely limited due to the need to withstand pirate attacks and hardware tampering. Despite this, we would like to allow the service provider to offer different packages of programs to the users. A user who buys a package should be able to view every program belonging to that package, but nothing else. A flexible scheme should allow for packages of various sizes to be offered, from a single program up to all the programs. We suggest two novel schemes to manage the encryption keys for these applications. The schemes are highly flexible, and understandable to users, yet require very few keys to be stored in the STTs' secure memory. The computational power required of the STTs is very low. The security of these schems is as good or better than that offered by current technology.
A comparison of multivariate normal generators
Authors: Donald R. Barr, Norman L. Slezak
Venue: Communications of the ACM (1972)

Three methods for generating outcomes on multivariate normal random vectors with a specified variance-covariance matrix are presented. A comparison is made to determine which method requires the least computer execution time and memory space when utilizing the IBM 360/67. All methods use as a basis a standard Gaussian random number generator. Results of the comparison indicate that the method based on triangular factorization of the covariance matrix generally requires less memory space and computer time than the other two methods.
Reductions among high dimensional proximity problems
Authors: Ashish Goel, Piotr Indyk, Kasturi Varadarajan
Venue: Proceedings of the twelfth annual ACM-SIAM symposium on Discrete algorithms (2001)

We present improved running times for a wide range of approximate high dimensional proximity problems. We obtain subquadratic running time for each of these problems. These improved running times are obtained by reduction to Nearest Neighbour queries. The problems we consider in this paper are Approximate Diameter, Approximate Furthest Neighbours, Approximate Discrete Center, Approximate Metric Facility Location, Approximate Bottleneck Matching, and Approximate Minimum Weight Matching.
Dealing with Hardware in Embedded Software: A General Framework Based on the Devil Language
Authors: Fabrice Mérillion, Gilles Muller
Venue: ACM SIGPLAN Notices (2001)

Writing code that talks to hardware is a crucial part of any embedded project. Both productivity and quality are needed, but some flaws in the traditional development process make these requirements difficult to meet. We have recently introduced a new approach of dealing with hardware, based on the Devil language. Devil allows to write a high-level, formal definition of the programming interface of a peripheral circuit. A compiler automatically checks the consistency of a Devil specification, from which it generates the low-level, hardware-operating code. In our original framework, the generated code is dependent of the host architecture (CPU, buses, and bridges). Consequently, any variation in the hardware environment requires a specific tuning of the compiler. Considering the variability of embedded architectures, this is a serious drawback. In addition, this prevents from mixing different buses in the same circuit interface. In this paper, we remove those limitations by improving our framework in two ways. (i) We propose a better isolation between the Devil compiler and the host architecture. (ii) We introduce Trident, a language extension aimed at mapping one or several buses to each peripheral circuit.
Design for testability strategies using full/partial scan designs and test point insertions to reduce test application times
Authors: Toshinori Hosokawa, Masayoshi Yoshimura, Mitsuyasu Ohta
Venue: Proceedings of the 2001 Asia and South Pacific Design Automation Conference (2001)

As an LSI is on the two-dimensional plane, the number of external pins of an LSI does not equally increase to the number of gates. Therefore, the number of flip-flops on a scan path is relatively increasing. As the results, the test application time becomes longer. In this paper, three new DFT strategies are proposed to reduce the test application time. Experimental results showed the DFT strategies reduced the test application times by 46 to 82% compared with a conventional full scan design method.