ppxscal/embedding_network huggingface dataset:
Simulation based performance study of a dynamic routing algorithm
Authors: Anup Kumar, Savita Singh
Venue: ACM SIGSIM Simulation Digest (1992)

This paper discusses a new distributed, dynamic routing approach for communication networks. At each node, the best available route to the destination is selected and the message is forwarded to the next node on that route. The best route is evaluated at the new node again. The choice of the best mute is based on a parameter K, defined in the paper. This parameter is calculated for every path based on the characteristics of the path, such as - the number of hops, the speeds of the links, the load on the links, reliability of links etc. The method guarantees that as long as the network is connected the message will be delivered to the destination using the best available path. This approach does not have the counting to infinity problem and is loop-free. A comparative study of this scheme with some of the existing schemes is also included to demonstrate its generality and effectiveness.
Estimation Three-Dimensional Motion of Rigid Objects from Noisy Observations
Authors: Johan Philip
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1991)

An estimate is made of the motion of a rigid body from two noisy 2-D perspective projections using the least-squares method and the algebra of R.Y. Tsai and T.S. Huang (1984). The accuracy of the estimated motion parameters is influenced by the position of the features of the object used in the calculation. Four test variables are derived that indicate how the accuracy is affected, and they are used for discarding inaccurate estimates. Monte Carlo tests demonstrate the obtained accuracy.
Practical programmer: testing made palatable
Authors: Marc Rettig
Venue: Communications of the ACM (1991)

How one team made software testing an integral part of the development process.
A faster algorithm for finding the minimum cut in a graph
Authors: Jianxiu Hao, James B. Orlin
Venue: Proceedings of the third annual ACM-SIAM symposium on Discrete algorithms (1992)

We consider the problem of finding the minimum capacity cut in a network G with n nodes. This problem has applications to network reliability and survivability and is useful in subroutines for other network optimization problems. One can use a maximum flow problem to find a minimum cut separating a designated source node s from a designated sink node t, and by varying the sink node one can find a minimum cut in G as a sequence of at most 2n - 2 maximum flow problems. We then show how to reduce the running time of these 2n - 2 maximum flow algorithms to the running time for solving a single maximum flow problem. The resulting running time is O(nm log n2/m) for finding the minimum cut in either a directed or undirected network. The algorithm also determines the arc connectivity of either a directed or undirected network in O(nm) steps.
A safe approximate algorithm for interprocedural aliasing
Authors: William Landi, Barbara G. Ryder
Venue: ACM SIGPLAN Notices (1992)

During execution, when two or more names exist for the same location at some program point, we call them aliases. In a language which allows arbitrary pointers, the problem of determining aliases at a program point is &rgr;-space-hard [Lan92]. We present an algorithm for the Conditional May Alias problem, which can be used to safely approximate Interprocedural May Alias in the presence of pointers. This algorithm is as precise as possible in the worst case and has been implemented in a prototype analysis tool for C programs. Preliminary speed and precision results are presented.
The effect of employing advanced branching mechanisms in superscalar processors
Authors: Yen-Jen Oyang, Chun-Hung Wen, Yu-Fen Chen, Shu-May Lin
Venue: ACM SIGARCH Computer Architecture News (1990)

This paper discusses the effect of employing advanced branching mechanisms in superscalar processors. The motivation behind employing advanced branching mechanisms in superscalar processors is to reduce the control dependence, or in other words the number of branch operations, in the program so that instruction-level parallelism can be exploited more effectively. The second effect achieved by reducing the control dependence in the program is a decrease of the amount of branch penalty due to less branch operations. In this paper, two advanced branching mechanisms are discussed. The first mechanism involves incorporating multiple condition registers in superscalar processors. The second mechanism is a novel multi-way branching scheme proposed in this paper. A quantitative analysis on the effect of the two branching mechanisms shows that incorporating multiple condition registers can boost the superscalar processor performance by a factor of 16% to 20% while employing the proposed multi-way branching mechanism can achieve even greater performance improvement, up to 47%.
AP 527: an ORACLE SQL&mdash;APL2/PC auxiliary processor
Authors: Stephen Deerhake
Venue: ACM SIGAPL APL Quote Quad (1991)

An auxiliary processor (AP) for interfacing ORACLE SQL with APL2/PC, modeled after APL2/370's AP 127 auxiliary processor, is described. While providing direct compatibility with AP 127 service requests, the AP described here also offers several enhancements to AP 127 service requests. Although written for ORACLE SQL and 16-bit APL2/PC, the programming style employed provides a great deal of isolation between the database management system (DBMS) and target interpreter, thus providing a high degree of portability to both other DBMS implementations (e.g., Database Manager under OS/2) and target interpreters. Besides providing SQL services for a desktop APL environment, the AP demonstrates that it is possible to write large auxiliary processors for APL2/PC using a high level language, and that the resultant AP can be installed in extended memory and run in protected 80x86 CPU execution mode.
A Neural Network Approach to the Labeling of Line Drawings
Authors: Gaby J. Salem, Tzay Y. Young
Venue: IEEE Transactions on Computers (1991)

A solution to the labeling of the drawings using a neural network approach is presented. Line-labeling constraints are designed into a modified Hopfield networks. The design of the energy function and the updating equation is described. The energy function includes higher order terms than in the usual quadratic Hopfield model to accommodate the higher-order interactions required by the labeling constraints. The physical model is modified accordingly. An additional layer of neurons is used to synthesize a realizable circuit. The resulting network combines the standard Hopfield-network neurons with neurons performing two- and three-way Boolean AND operations. Simulation of network behavior for various trihedral scenes produced successful results.
Color Reflectance Modeling Using a Polychromatic Laser Range Sensor
Authors: Réjean Baribeau, Marc Rioux, Guy Godin
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1992)

A system for simultaneously measuring the 3-D shape and color properties of objects is described. Range data are obtained by triangulation over large volumes of the scene, whereas color components are separated by means of a white laser. Details are given concerning the modeling and the calibration of the system for bidirectional reflectance-distribution functions measurements. A reflection model is used to interpret the data collected with the system in terms of the underlying physical properties of the target. These properties are the diffuse reflectance of the body material, the Fresnel reflectance of the air media interface, and the slope surface roughness of the interface. Experimental results are presented for the extraction of these parameters. By allowing the subtraction of highlights from color images and the compensation for surface orientation, spectral reflectance modeling can help to understand 3-D scenes. A practical example is given where a color and range image is processed to yield uniform regions according to material pigmentation.
Wafer-Scale Optimization Using Computational Availability
Authors: David L. Landis, Nitin Nigam, Joseph W. Yoder
Venue: Computer (1992)

It is shown that, given the ability to restructure wafer-level designs, there are different ways to employ redundancy. Redundancy is evaluated by estimating system computational availability over a mission lifetime. This technique is illustrated using two wafer-scale integration (WSI) case studies. The first is a very-fine-grained programmable systolic data processor (PSDP) that contains 4- and 8-b paths, RAM, and control optimized for signal and data processing applications. The second, the Mosaic multicomputer architecture, is a less fine-grained homogeneous architecture in which each node contains a 16-b microprocessor and associated RAM and ROM. Potential benefits of implementing these parallel processing architectures in wafer scale are discussed.
Prospects for WSI: A Manufacturing Perspective
Authors: Wojciech Maly
Venue: Computer (1992)

A manufacturing cost model that describes the relationships among characteristics of modern manufacturing processes, investment costs to achieve these characteristics, and basic IC parameters, including both die size and minimum feature size, is used to explain major trends in the past 20 yr of microelectronics. Results from this model indicate that it is not possible to continue progress in microelectronics through minimizing feature size, that the drive toward larger dies will gain momentum and lead gradually toward wafer-scale integration (WSI), and that manufacturing costs will keep WSI from becoming practical in the immediate future. Active-substrate flip-chip multichip modules (MCMs) are presented as an alternative that may provide both the performance gain and cost efficiency required.
Timing optimization for multi-level combinational networks
Authors: Kuang-Chien Chen, Saburo Muroga
Venue: Proceedings of the 27th ACM/IEEE Design Automation Conference (1991)

This paper presents a timing optimization algorithm SDLR (acronym of SYLON-DREAM Level-Reduction), which is used in the SYLON-DREAM logic synthesizer for speeding up combinational multi-level networks. In SDLR, gates on critical paths are identified and their level numbers counted from the inputs of the network are maximally reduced by a level-reduction procedure. Gates which are not on the critical paths are processed by an area reduction procedure to reduce network area without increasing its maximum depth. SDLR uses the concept of permissible functions in both level and area reduction procedures, and it can directly process networks consisting of simple gates or negative gates (i.e., MOS cells). Experimental results obtained for benchmark functions show that SDLR is an effective algorithm which can reduce network delay with no or minimal area increase.
A Fortran to C converter
Authors: S. I. Feldman
Venue: ACM SIGPLAN Fortran Forum (1990)

We have produced a program that automatically converts ANSI standard Fortran 77 [1] to C [8]. It has converted many Fortran programs without manual intervention; it is easily available --- free of charge (and of warranty) --- by electronic mail and ftp.
Constructing matrix representations of finitely presented groups
Authors: S. A. Linton
Venue: Journal of Symbolic Computation (1991)

The Todd-Coxeter coset enumeration algorithm is one of the most important tools of computational group theory. It may be viewed as a means of constructing permutation representations of finitely presented groups. In this paper we present an analogous algorithm for directly constructing matrix representations over various fields. In fact the algorithm is more general than this, and can be used to construct matrix representations of finitely generated algebras. The algorithm (with some restrictions) has been implemented as a C program and some results obtained with this implementation are described.
Compile-Time Scheduling and Assignment of Data-Flow Program Graphs with Data-Dependent Iteration
Authors: Soonhoi Ha, Edward A. Lee
Venue: IEEE Transactions on Computers (1991)

Four scheduling strategies for dataflow graphs onto parallel processors are classified: (1) fully dynamic, (2) static-assignment, (3) self-timed, and (4) fully static. Scheduling techniques valid for strategies (2), (3), and (4) are proposed. The focus is on dataflow graphs representing data-dependent iteration. A known probability mass function for the number of cycles in the data-dependent iteration is assumed, and how a compile-time decision about assignment and/or ordering as well as timing can be made is shown. The criterion used is to minimize the expected total idle time caused by the iteration. In certain cases, this will also minimize the expected makespan of the schedule. How to determine the number of processors that should be assigned to the data-dependent iteration is shown. The method is illustrated with a practical programming example.
Range searching with efficient hierarchical cuttings
Authors: Jiří Matoušek
Venue: Proceedings of the eighth annual symposium on Computational geometry (1992)

We present an improved space/query time tradeoff for the general simplex range searching problem, matching known lower bounds up to small polylogarithmic factors. In particular, we construct a linear-space simplex range searching data structure with O(n1&ndash;1/d) query time, which is optimal for d=2 and probably also for d>2. Further we show that multilevel range searching data structures can be built with only a polylogarithmic overhead in space and query time per level (the previous solutions require at least a small fixed power of n). We show that Hopcroft's problem (detecting an incidence among n lines and n points) can be solved in time n4/32O(log n). In all these algorithms, we apply Chazelle's results on computing optimal cuttings.
Design process and decision rationale models for the N-Chime interface system
Authors: Sigfried Treu, D. Peter Sanderson, Roman Rozin, Ravi Sharma
Venue: ACM SIGCHI Bulletin (1990)

The N-CHIME interface system was designed with the broad objective of enabling, or "empowering," different types of users to carry out effective modeling and simulation applications with the Hierarchical Simulation Language (HSL). A design methodology was developed that is based on a "parallel processes" model: a triad of parallel design processes, one directed at each of the user, the interface, and the application. For comprehensive and systematic interface design, such a methodology is essential. N-CHIME has been implemented and tested. This paper presents an overview of the design models and some of the resulting tools and techniques supportive of the application-specific user. It also highlights the importance of providing online access to the design decision rationales that were used for the various user-visible tools and devices.
The KAT (Knowledge-Action-Transformation) Approach to the Modeling and Evaluation of Reliability and Availability Growth
Authors: Jean-Claude Laprie, Karama Kanoun, Christian Béounes, Mohamed Kaâniche
Venue: IEEE Transactions on Software Engineering (1991)

An approach for the modeling and evaluation of reliability and availability of systems using the knowledge of the reliability growth of their components is presented. Detailed models of reliability and availability for single-component systems are derived under much weaker assumption than usually considered. These models, termed knowledge models, enable phenomena to be precisely characterized, and a number of properties to be deduced. Since the knowledge models are too complex to be applied in real life for performing predictions, simplified models for practical purposes (action models) are discussed. The hyperexponential model is presented and applied to field data of software and hardware failures. This model is shown to be comparable to other models as far as reliability of single-component systems is concerned: in addition, it enables estimating and predicting the reliability of multicomponent systems, as well as their availability. The transformation approach enables classical Markov models to be transformed into other Markov models which account for reliability growth. The application of the transformation to multicomponent systems is described.
Using forcing to prove completeness of resolution and paramodulation
Authors: John Pais, Gerald E. Peterson
Venue: Journal of Symbolic Computation (1991)

A technique for establishing completeness results for theorem proving systems in first-order logic with equality is presented. This technique is an adaptation of model theoretic forcing, which was originally designed to provide a method for constructing models of certain first-order logical theories. Our method applies to term orderings which may have infinitely many infinite extents, but transfinite trees are not used. We illustrate this method by proving the completeness of resolution and paramodulation, and the completeness of a set of inference rules consisting of restrictive forms of resolution and paramodulation, simplification and deletion of subsumed clauses.
TUGS&mdash;a tool for teaching computer graphics
Authors: John Clevenger, Rick Chaddock, Roger Bendig
Venue: ACM SIGGRAPH Computer Graphics (1991)

One of the best methods of teaching students about the principles underlying computer graphics systems is to have them develop an implementation of a "graphics pipeline" supporting modeling, viewing, and rendering operations. When completed, such an implementation represents a sophisticated package capable of producing complex images. However, these complex images typically cannot be generated until at or very near the completion of the project. We describe a tool called TUGS which has been developed to support the incremental development of a complex graphics system and which provides the ability to produce complex images early in the development process.TUGS is a complete graphics modeling and rendering system built from a highly-modularized set of primitive operations. Students can replace individual pieces of the TUGS system with their own implementations, while retaining use of the remaining TUGS routines. This allows incremental development of a complete system, while at the same time providing the ability to generate complete images. It also provides a vehicle for selective consideration of the many issues involved in modeling and rendering systems; those areas deemed most important can be assigned to students for implementation, while TUGS can be relied on to provide compatible implementations for the others. TUGS also includes a substantial collection of support routines to help reduce the "overhead" incurred in implementation efforts. These include command input parsing, 3D transformations, vector and matrix algebra operations, metafile storage, and support for device-independent low-level graphics, as well as many others.
A formal approach to program inversion
Authors: Wei Chen
Venue: Proceedings of the 1990 ACM annual conference on Cooperation (1990)

In this paper, we introduce a formal approach to inverting programs, which is developed in [2]. We demonstrate its usefulness in programming by applying it to develop an in-place algorithm for the so-called LU-multiplication, which might be otherwise hard to find.
Direct Computation of Qualitative 3-D Shape and Motion Invariants
Authors: Daphna Weinshall
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1991)

Structure from motion often refers to the computation of three-dimensional structure from a matched sequence of images. However, a depth map of a surface is difficult to compute and may not be a good representation for storage and recognition. Given matched images it is shown that the sign of the normal curvature in a given direction at a given point in the image can be computed from a simple difference of slopes of line segments in one image. Using this result, local surface patches can be classified as convex, concave, cylindrical, hyperbolic (saddle point), or planar. At the same time, the translational component of the optical flow, from which the focus of expansion can be computed, is obtained.
Omni-Directional Stereo
Authors: Hiroshi Ishiguro, Masashi Yamamoto, Saburo Tsuji
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1992)

Omnidirectional views of an indoor environment at different locations are integrated into a global map. A single camera swiveling about the vertical axis takes consecutive images and arranges them into a panoramic representation, which provides rich information around the observation point: a precise omnidirectional view of the environment and coarse ranges to objects in it. Using the coarse map, the system autonomously plans consecutive observations at the intersections of lines connecting object points, where the directions of the imaging are estimated easily and precisely. From two panoramic views at the two planned locations, a modified binocular stereo method yields a more precise, but with direction-dependent uncertainties, local map. New observation points are selected to decrease the uncertainty, and another local map is yielded, which is then integrated into a more reliable global representation of the world with the adjacent local maps.
Alphonse: incremental computation as a programming abstraction
Authors: Roger Hoover
Venue: ACM SIGPLAN Notices (1992)

Alphonse is a program transformation system that uses dynamic dependency analysis and incremental computation techniques to automatically generate efficient dynamic implementations from simple exhaustive imperative program specifications.
X-Window interface to SMART, an advanced text retrieval system
Authors: Tong Li, Victoria Chiu, Fredric Gey
Venue: ACM SIGIR Forum (1992)

In a research environment for text and document retreival, the experimental functionality is and must be paramount. However, for long-term durability of a software product, the user-interface is seen as a critical component to successful development. In order to explore the effort involved in developing a modern user interface to a text retrieval system, the authors chose to implement a limited X-Window interface to the Cornell University SMART system. The first section of this paper will briefly introduce the history of the SMART system, its command line interface, and the goal of this project; the second will discuss the scope of the project; the development and integration strategies will be covered in sections three and four; then some ideas on the desired enchancements in section five.
New sparseness results on graph spanners
Authors: Barun Chandra, Gautam Das, Giri Narasimhan, José Soares
Venue: Proceedings of the eighth annual symposium on Computational geometry (1992)

Let G=(V,E) be an n-vertex connected graph with positive edge weights. A subgraph G&prime; = (V,E&prime;) is a t-spanner of G if for all u, v &egr; V,the weighted distance between u and v in G&prime; is at most t times the weighted distance between u and v in G. We consider the problem of constructing sparse spanners, and the weight, defined as the sum of the edge weights in the spanner. In this paper, we concentrate on constructing spanners of small weight. For an arbitrary positive edge-weighted graph G, for any t> 1, and any &egr;>0, we show that a t-spanner of G with weight O(n(2+&egr;)/(t-1>) &bull;wt(MST) can be constructed in polynomial time. We also show that (log2n)-spanners of weight O(log n)&bull;wt(MST) can be constructed. We then consider spanners for complete graphs induced by a set of points in d-dimensional real normed space. The weight of an edge xy is the norm of the xy vector. We show that for these graphs, t-spanners with total weight O(log n)&bull;wt(MST) can be constructed in polynomial time.