ppxscal/embedding_network huggingface dataset:
Systems analysis: a systemic analysis of a conceptual model
Authors: Itzhak Shemer
Venue: Communications of the ACM (1987)

Adopting an appropriate model for systems analysis, by avoiding a narrow focus on the requirements specification and increasing the use of the systems analyst's knowledge base, may lead to better software development and improved system life-cycle management.
Object-oriented simulation modeling with C++/CSIM17
Authors: Herb Schwetman
Venue: Proceedings of the 27th conference on Winter simulation (1995)

C++/CSIM17 is toolkit for constructing process-oriented, discrete-simulation models by writing C++ programs. The use of C++ as the implementation language for the model means that the majority of the object-oriented techniques and methodologies that have been developed for C++ programmers can be applied to the design and implementation of simulation models.
The quest for excellence in designing CS1/CS2 assignments
Authors: Todd J. Feldman, Julie D. Zelenski
Venue: Proceedings of the twenty-seventh SIGCSE technical symposium on Computer science education (1996)

We identify the principles involved in designing effective programming assignments for CS1/CS2. Through a case study of a particularly successful recursion assignment, we establish several prerequisites that must be present in the foundation of a potential assignment and discuss techniques for engineering exceptional assignments through changes to their more malleable components.
Web server workload characterization: the search for invariants
Authors: Martin F. Arlitt, Carey L. Williamson
Venue: ACM SIGMETRICS Performance Evaluation Review (1996)

The phenomenal growth in popularity of the World Wide Web (WWW, or the Web) has made WWW traffic the largest contributor to packet and byte traffic on the NSFNET backbone. This growth has triggered recent research aimed at reducing the volume of network traffic produced by Web clients and servers, by using caching, and reducing the latency for WWW users, by using improved protocols for Web interaction.Fundamental to the goal of improving WWW performance is an understanding of WWW workloads. This paper presents a workload characterization study for Internet Web servers. Six different data sets are used in this study: three from academic (i.e., university) environments, two from scientific research organizations, and one from a commercial Internet provider. These data sets represent three different orders of magnitude in server activity, and two different orders of magnitude in time duration, ranging from one week of activity to one year of activity.Throughout the study, emphasis is placed on finding workload invariants: observations that apply across all the data sets studied. Ten invariants are identified. These invariants are deemed important since they (potentially) represent universal truths for all Internet Web servers. The paper concludes with a discussion of caching and performance issues, using the invariants to suggest performance enhancements that seem most promising for Internet Web servers.
Optimal Broadcast in All-Port Wormhole-Routed Hypercubes
Authors: Ching-Tien Ho, Ming-Yang Kao
Venue: IEEE Transactions on Parallel and Distributed Systems (1995)

We give an optimal algorithm that broadcasts on an $n$-dimensional hypercube in $\Theta(n/\log_2(n+1))$ routing steps with wormhole, $e$-cube routing and all-port communication. Previously, the best algorithm of McKinley and Trefftz requires $\lceil{n/2} \rceil$ routing steps. We also give routing algorithms that achieve tight time bounds for $n \le 7$.
Correlation-induction techniques for estimating quantiles in simulation experiments
Authors: Athanassios N. Avramidis, James R. Wilson
Venue: Proceedings of the 27th conference on Winter simulation (1995)

To estimate selected quantiles of the response of a finite-horizon simulation, we develop statistical methods based on correlation-induction techniques for variance reduction, with emphasis on antithetic variates and Latin hypercube sampling. The proposed multiple-sample quantile estimator is the average of negatively correlated quantile estimators computed from disjoint samples of the response, where negative correlation is induced between corresponding responses in different samples while mutual independence of responses is maintained within each sample. The proposed single-sample quantile estimator is computed from negatively correlated responses within one overall sample. We establish a central limit theorem for the single-sample estimator based on Latin hypercube sampling, showing that asymptotically this estimator is unbiased and has smaller variance than the comparable direct-simulation estimator based on independent replications. We also show that if the response is monotone in the simulation's random-number inputs and if the response satisfies some other regularity conditions, then asymptotically the multiple-sample estimator is unbiased and has smaller mean square error than the direct-simulation estimator.
Algorithm 673: Dynamic Huffman coding
Authors: Jeffrey Scott Vitter
Venue: ACM Transactions on Mathematical Software (TOMS) (1989)

We present a Pascal implementation of the one-pass algorithm for constructing dynamic Huffman codes that is described and analyzed in a companion paper. The program runs in real time; that is, the processing time for each letter of the message is proportional to the length of its codeword. The number of bits used to encode a message of t letters is less than t bits more than that used by the well-known two-pass algorithm. This is best possible for any one-pass Huffman scheme. In practice, it uses fewer bits than all other Huffman schemes. The algorithm has applications in file compression and network transmission.
Phased Logic: Supporting the Synchronous Design Paradigm with Delay-Insensitive Circuitry
Authors: Daniel H. Linder, James C. Harden
Venue: IEEE Transactions on Computers (1996)

Phased logic is proposed as a solution to the increasing problem of timing complexity in digital design. It is a delay-insensitive design methodology that seeks to restore the separation between logical and physical design by eliminating the need to distribute low-skew clock signals and carefully balance propagation delays. However, unlike other methodologies that avoid clocks, phased logic supports the cyclic, deterministic behavior of the synchronous design paradigm. This permits the designer to rely chiefly on current experience and CAD tools to create phased logic systems. Marked graph theory is used as a framework for governing the interaction of phased logic gates that operate directly on Level-Encoded two-phase Dual-Rail (LEDR) signals. A synthesis algorithm is developed for converting clocked systems to phased logic systems and is applied to benchmark examples. Performance results indicate that phased logic tends to be tolerant of logic delay imbalances and has predictable worst-case timing behavior. Although phased logic requires additional circuitry, it has the potential to shorten the design cycle by reducing timing complexities.
Analysis and caching of dependencies
Authors: Martín Abadi, Butler Lampson, Jean-Jacques Lévy
Venue: Proceedings of the first ACM SIGPLAN international conference on Functional programming (1996)

We address the problem of dependency analysis and caching in the context of the lambda;-calculus. The dependencies of a lambda;-term are (roughly) the parts of the lambda;-term that contribute to the result of evaluating it. We introduce a mechanism for keeping track of dependencies, and discuss how to use these dependencies in caching.
Lessons learned from implementing the CORBA persistent object service
Authors: Jan Kleindienst, František Plášil, Petr Tůma
Venue: ACM SIGPLAN Notices (1996)

In this paper, the authors share their experiences gathered during the design and implementation of the CORBA Persistent Object Service. There are two problems related to a design and implementation of the Persistence Service: first, OMG intentionally leaves the functionality core of the Persistence Service unspecified; second, OMG encourages reuse of other Object Services without being specific enough in this respect. The paper identifies the key design issues implied both by the intentional lack of OMG specification and the limits of the implementation environment characteristics. At the same time, the paper discusses the benefits and drawbacks of reusing other Object Services, particularly the Relationship and Externalization Services, to support the Persistence Service. Surprisingly, the key lesson learned is that a direct reuse of these Object Services is impossible.
Scalable concurrent counting
Authors: Maurice Herlihy, Beng-Hong Lim, Nir Shavit
Venue: ACM Transactions on Computer Systems (TOCS) (1995)

The notion of counting is central to a number of basic multiprocessor coordination problems, such as dynamic load balancing, barrier synchronization, and concurrent data structure design. We investigate the scalability of a variety of counting techniques for large-scale multiprocessors. We compare counting techniques based on: (1) spin locks, (2) message passing, (3) distributed queues, (4) software combining trees, and (5) counting networks. Our comparison is based on a series of simple benchmarks on a simulated 64-processor Alewife machine, a distributed-memory multiprocessor currently under development at MIT. Although locking techniques are known to perform well on small-scale, bus-based multiprocessors, serialization limits performance, and contention can degrade performance. Both counting networks and combining trees outperform the other methods substantially by avoiding serialization and alleviating contention, although combining-tree throughput is more sensitive to variations in load. A comparison of shared-memory and message-passing implementations of counting networks and combining trees shows that message-passing implementations have substantially higher throughput.
Optimal probabilistic allocation of customer types to servers
Authors: S. C. Borst
Venue: Proceedings of the 1995 ACM SIGMETRICS joint international conference on Measurement and modeling of computer systems (1995)

The model under consideration consists of n customer types attended by m parallel non-identical servers. Customers are allocated to the servers in a probabilistic manner; upon arrival customers are sent to one of the servers according to an m times; n matrix of routing probabilities. We consider the problem of finding an allocation that minimizes a weighted sum of the mean waiting times. We expose the structure of an optimal allocation and describe for some special cases in detail how the structure may be exploited in actually determining an optimal allocation.
Software for simulation
Authors: Jerry Banks
Venue: Proceedings of the 27th conference on Winter simulation (1995)

This tutorial describes computer languages and other software packages that support discrete-event simulation.
Model and call admission control for distributed applications with correlated bursty traffic
Authors: Jose Roberto Fernandez, Matt W. Mutka
Venue: Proceedings of the 1995 ACM/IEEE conference on Supercomputing (CDROM) (1995)

As network capacities increase, wide-area distributed parallel computing may become feasible. This paper addresses one of the issues involved in using an asynchronous transfer mode (ATM) network for such a purpose ¿ that of developing an appropriate call admission control (CAC) procedure for such applications given the special nature of their traffic. In this proposal, connections belonging to the same application and sharing the same link are allowed to utilize the linkbandwidth in a strongly correlated manner. However, connections belonging to different applications are still assumed to be independent. This allows the development of a tabular approach for keeping track of the aggregate bandwidth demand of the applications sharing the same link. The proposed approach is compared with two related approaches (one more conservative and another more aggressive) and is shown to strike a balance between utilization and loss rate.
A Cartesian Parallel Nested Dissection Algorithm
Authors: Michael T. Heath, Padma Raghavan
Venue: SIAM Journal on Matrix Analysis and Applications (1995)

This paper is concerned with the distributed parallel computation of an ordering for a symmetric positive definite sparse matrix. The purpose of the ordering is to limit fill and enhance concurrency in the subsequent Cholesky factorization of the matrix. A geometric approach to nested dissection is used based on a given Cartesian embedding of the graph of the matrix in Euclidean space. The resulting algorithm can be implemented efficiently on massively parallel, distributed memory computers. One unusual feature of the distributed algorithm is that its effectiveness does not depend on data locality, which is critical in this context, since an appropriate partitioning of the problem is not known until after the ordering has been determined. The ordering algorithm is the first component in a suite of scalable parallel algorithms currently under development for solving large sparse linear systems on massively parallel computers.
Eigenvalues and expansion of regular graphs
Authors: Nabil Kahale
Venue: Journal of the ACM (JACM) (1995)

The spectral method is the best currently known technique to prove lower bounds on expansion. Ramanujan graphs, which have asymptotically optimal second eigenvalue, are the best-known explicit expanders. The spectral method yielded a lower bound of k/4 on the expansion of linear-sized subsets of k-regular Ramanujan graphs. We improve the lower bound on the expansion of Ramanujan graphs to approximately k/2. Moreover, we construct a family of k-regular graphs with asymptotically optimal second eigenvalue and linear expansion equal to k/2. This shows that k/2 is the best bound one can obtain using the second eigenvalue method. We also show an upper bound of roughly 1+k-1 on the average degree of linear-sized induced subgraphs of Ramanujan graphs. This compares positively with the classical bound 2k-1 . As a byproduct, we obtain improved results on random walks on expanders and construct selection networks (respectively, extrovert graphs) of smaller size (respectively, degree) than was previously known.
Business process redesign an information architecture: exploring the relationships
Authors: James T. C. Teng, William J. Kettinger
Venue: ACM SIGMIS Database (1995)

Business process redesign (BPR) and information architecture (IA) have been recognized as high priority agenda items in organizations during the 1990s. This paper explores the relationships between the two concepts. Specifically, this paper focuses on three main concerns: how IA supports BPR, how the lack of IA hinders BPR, and what approach to IA can facilitate BPR? The paper begins with a brief review of the development and implementation of each concept. This is followed by an examination of how IA and BPR are related to business processes, both existing and newly designed processes. This analysis, in conjunction with results from field research, provide the basis for nine propositions regarding the BPR and IA relationship. In support of BPR, IS professionals have the opportunity not only to contribute to a firm's business objectives, but also to begin to achieve IA's promise while avoiding some of IA's past implementation problems. It is hoped that further research based on these propositions will lead to more complete answers and perhaps more specific questions on the BPR/IA relationships.
Comments on "Efficiently Computing and Representing Aspect Graphs of Polyhedral Objects"
Authors: Aldo Laurentini
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1996)

This correspondence is originated by the definition of aspect given in a recent paper [1] on the computation of aspect graphs of polyhedra. Simple examples are presented which show that the data stored according to this definition can be unsuitable for identifying an object or its attitude through a topological match. A definition is suggested which does not incur the problems pointed out.
On the Reuse of Additions in Matrix Multiplication
Authors: K. Kalorkoti
Venue: SIAM Journal on Computing (1995)

We consider the problem of multiplying pairs of matrices by means of quadratic algorithms in terms of the reuse of additions. We show that if such an algorithm is to be significantly faster than the naive matrix multiplication method then it must reuse additions to a great extent. (For example, any quadratic or bilinear algorithm for $n\times n$ matrix multiplication that does not reuse additions, except when reusing nonscalar steps, requires at least $n^3/8-n^2/4+n/8$ arithmetic operations.
Semantics for update rule programs and implementation in a relational database management system
Authors: Louiqa Raschid, Jorge Lobo
Venue: ACM Transactions on Database Systems (TODS) (1996)

In this paper, we present our research on defining a correct semantics for a class of update rule (UR) programs, and discuss implemanting these programs in a DBMS environment. Update rules execute by updating relations in a database which may cause the further execution of rules. A correct semantics must guarantee that the execution of the rules will terminate and that it will produce a minimal updated database. The class of UR programs is syntactically identified, based upon a concept that is similar to stratification. We extend that strict definition of stratification and allow a relaxed criterion for partitioning of the rules in the UR program. This relaxation allows a limited degree of nondeterminism in rule execution. We define an execution semantics based upon a monotonic fixpoint operator TUR, resulting in a set of fixpoints for UR. The monotionicity of the operator is maintained nby explicitly representing the effect of asserting and retracting tuples in the database. A declarative semantics for the update rule program is obtained by associating a normal logic program UR to represent the UR program. We use the stable model semantics which characterize a normal logic program by a set of minimal models which are called stable models. We show the equivalence between the set of fixpoints for UR and the set of stable models for UR. We briefly discuss implementing the fixpoint semantics of the UR program in a DBMS environment. Relations that can be updated by the rules are updatable relations and they are extended with two flags. An update rule is represented by a database query, which queries the updatable relations as well as database relaions, i.e., those relations which are not update by rules. We describe an algorithm to process the queries and compute a fixpoint in the DBMS environment and obtain a final database.
Pittsburgh Supercomputing Center high school initiative in computational science: report on findings (school years: 1991&ndash;92, 1992&ndash;93, 1993&ndash;94)
Authors: Casey Porto
Venue: Proceedings of the 1995 ACM/IEEE conference on Supercomputing (CDROM) (1995)

The purpose of the Pittsburgh Supercomputing Center's High School Initiative was to motivate students to pursue careers in science, mathematics, engineering and computer science. The initiative generated excitement among teachers and their students by providing them with the opportunity to work on a project of their choosing using the world's fastest supercomputer - the same machine used by leading researchers working on today's most challenging scientific problems. The program gave teachers the means and support to institutionalize their computational science project into the curriculum so that the impact of the program would continue from year to year with each new class of students.
Evaluation of an adaptive traffic control technique with underlying system changes
Authors: Richard H. Smith, Daniel C. Chin
Venue: Proceedings of the 27th conference on Winter simulation (1995)

A key problem in traffic engineering is the optimization of the flow of vehicles through a given road network. Improving the timing of the traffic signals at intersections in the network is generally the most powerful and cost-effective means of achieving this goal. Recent efforts have resulted in the development of a fundamentally different approach for optimal centralized signal timing control that eliminates the need for an open-loop model of the traffic network dynamics. The approach is based on a neural network (NN) serving as the basis for the control law, with the internal NN weight estimation occurring real-time in closed-loop mode via the simultaneous perturbation stochastic approximation (SPSA) algorithm. The paper investigates the application of such a non-network-model-based approach and illustrates the approach through a simulation on a nine-intersection, mid-Manhattan, New York network. The simulated traffic network contains varying short and long-term congestion behavior and short-term stochastic, nonlinear effects. The approach results in a net 10% reduction in vehicle wait time relative to the performance of the existing, in-place strategy.
Type extension through polymorphism
Authors: F. Warren Burton
Venue: ACM Transactions on Programming Languages and Systems (TOPLAS) (1990)

A record data type can be extended by addition of more fields. The extended type is a subtype of the original, in that any value of the extended type can be regarded as a value of the original type by ignoring the additional fields. This results in a type hierarchy. Milner [3] has proposed a polymorphic type system. With the Milner approach, the type of a function may contain type variables. This also results in a type hierarchy. In a language with a polymorphic type system, if it is anticipated that a record type will need to be extended, then the record type can be defined to have a dummy extension field. In the parent type, the extension field will have null contents of type void. The type of the extension field can differ with different subtypes. The approach can be extended to allow a type to be subtype of two or more parent types. To a limited extent, this approach can be used in Ada and other languages with generic program units.
Improving balanced scheduling with compiler optimizations that increase instruction-level parallelism
Authors: Jack L. Lo, Susan J. Eggers
Venue: Proceedings of the ACM SIGPLAN 1995 conference on Programming language design and implementation (1995)

Traditional list schedulers order instructions based on an optimistic estimate of the load latency imposed by the hardware and therefore cannot respond to variations in memory latency caused by cache hits and misses on non-blocking architectures. In contrast, balanced scheduling schedules instructions based on an estimate of the amount of instruction-level parallelism in the program. By scheduling independent instructions behind loads based on what the program can provide, rather than what the implementation stipulates in the best case (i.e., a cache hit), balanced scheduling can hide variations in memory latencies more effectively.Since its success depends on the amount of instruction-level parallelism in the code, balanced scheduling should perform even better when more parallelism is available. In this study, we combine balanced scheduling with three compiler optimizations that increase instruction-level parallelism: loop unrolling, trace scheduling and cache locality analysis. Using code generated for the DEC Alpha by the Multiflow compiler, we simulated a non-blocking processor architecture that closely models the Alpha 21164. Our results show that balanced scheduling benefits from all three optimizations, producing average speedups that range from 1.15 to 1.40, across the optimizations. More importantly, because of its ability to tolerate variations in load interlocks, it improves its advantage over traditional scheduling. Without the optimizations, balanced scheduled code is, on average, 1.05 times faster than that generated by a traditional scheduler; with them, its lead increases to 1.18.