ppxscal/embedding_network huggingface dataset:
Complete Orthogonal Decomposition for Weighted Least Squares
Authors: Patricia D. Hough, Stephen A. Vavasis
Venue: SIAM Journal on Matrix Analysis and Applications (1997)

This paper proposes a complete orthogonal decomposition (COD) algorithm for solving weighted least-squares problems. In applications, the weight matrix can be highly ill conditioned, and this can cause standard methods like QR factorization to return inaccurate answers in floating-point arithmetic. Stewart and Todd independently established a norm bound for the weighted least-squares problem that is independent of the weight matrix. Vavasis proposed a definition of a "stable" solution of weighted least squares based on this norm bound: The solution computed by a stable algorithm must satisfy an accuracy bound that is not affected by ill conditioning in the weight matrix. A forward error analysis shows that the COD algorithm is stable in this sense, but it is simpler and more efficient than the algorithm proposed by Vavasis. Our forward error bound is contrasted to the backward error analysis of other previous works on weighted least squares.
Challenges in worldwide IP reuse (panel with embedded tutorial): applying VSIA standards to system on chip design
Authors: Rita Glover, Takahide Inoue, John Teets, Doug Fairbairn, Larry Cooke, Steve Schulz, Raj Raghavan, Jean-Louis Bories, Wally Rhines
Venue: Proceedings of the 34th annual Design Automation Conference (1997)

Advances in IC process technology have enabled the design of complex systems on a single chip. System-on-chip developers need to be able to mix and match pre-designed, best-in-class functional blocks from many providers if they are to meet design deadlines with limited design engineering resources. Consequently, there is a rising interest in the creation, distribution, and design application of reusable, interoperable blocks of intellectual property, referred to as "IP" or "virtual components." This panel will explore the opportunities and challenges for design innovation offered by a worldwide, open reuse mechanism for virtual components.The session will begin with an embedded tutorial case study on the VSIA (Virtual Socket Interface Alliance) approach to design reuse. Then IP providers and users will discuss the technical and business challenges in establishing a mechanism for reuse of virtual components. The panelists will also discuss the issues in integrating virtual components from multiple providers into system-on-chip designs.
STANFINS: one year later
Authors: Julia Ottenweller, Nathan Palmer
Venue: Proceedings of the conference on TRI-ADA '90 (1990)

How well Ada technology has withstood the challenges (among them an expansion of the system to a DoD-wide scope) since last year's report on this two million line financial accounting system.
A genetic algorithms tutorial tool for numerical function optimisation
Authors: E. K. Burke, D. B. Varley
Venue: Proceedings of the 2nd conference on Integrating technology into computer science education (1997)

The field of Genetic Algorithms has grown into a huge area over the last few years. Genetic Algorithms are adaptive methods, which can be used to solve search and optimisation problems over a period of generations, based upon the principles of natural selection and survival of the fittest. This paper describes an innovative tool to introduce the basics of the subject of Genetic Algorithms called GAVIn (Genetic Algorithms Visual Interface). It focuses on the domain of numerical function optimisation problems as these form a good basis for learning and operator comparison. The other problem domains are too varied and problem dependent to form a general, robust learning tool.
A Small-Sample Correction for Testing for gth-Order Serial Correlation with Artificial Regressions
Authors: David A. Belsley
Venue: Computational Economics (1997)

Monte Carlo experiments establish that the usual &rsquo;t-statistic&lsquo; used for testing for first-order serial correlation with artificial regressions is far from being distributed as a Student&lsquo;s t in small samples. Rather, it is badly biased in both mean and variance and results in grossly misleading tests of hypotheses when treated as a Student&lsquo;s t. (Similar distortions plague the familiar Durbin&ndash;Watson statistic.) Simply computed corrections for the mean and variance are derived, however, which are shown to lead to a transformed statistic producing acceptable tests. The test procedure is detailed and exemplar code provided.
λτ-Space Representation of Images and Generalized Edge Detector
Authors: Muhittin Gökmen, Anil K. Jain
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1997)

An image and surface representation based on regularization theory is introduced in this paper. This representation is based on a hybrid model derived from the physical membrane and plate models. The representation, called the ¿¿-representation, has two dimensions; one dimension represents smoothness or scale while the other represents the continuity of the image or surface. It contains images/surfaces sampled both in scale space and the weighted Sobolev space of continuous functions. Thus, this new representation can be viewed as an extension of the well-known scale space representation. We have experimentally shown that the proposed hybrid model results in improved results compared to the two extreme constituent models, i.e., the membrane and the plate models. Based on this hybrid model, a generalized edge detector (GED) which encompasses most of the well-known edge detectors under a common framework is developed. The existing edge detectors can be obtained from the generalized edge detector by simply specifying the values of two parameters, one of which controls the shape of the filter (¿) and the other controls the scale of the filter (¿). By sweeping the values of these two parameters continuously, one can generate an edge representation in the ¿¿ space, which is very useful for developing a goal-directed edge detection scheme for a specific task. The proposed representation and the edge detector have been evaluated qualitatively and quantitatively on several different types of image data such as intensity, range, and stereo images.
Linear Recursive Networks and Their Applications in Distributed Systems
Authors: Wen-Jing Hsu, Moon Jung Chung, Amitabha Das
Venue: IEEE Transactions on Parallel and Distributed Systems (1997)

We present a new class of interconnection topologies called the Linear Recursive Networks (LRNs) and examine their possible applications in distributed systems. Each LRN is characterized by a recursive pattern of interconnection which can be specified by simple parameters. Basic properties such as node degree, diameter, and the performance of routing algorithms for all LRNs are then collectively analyzed in terms of these parameters. By choosing appropriate values for the parameters, our results can assist a network designer in selecting a topology with required routing performance and cost of interconnection. A subclass of LRNs, called Congruent LRNs (CLRNs), is also identified here and shown to possess desirable properties for more tightly coupled systems. It is shown that the CLRNs include existing networks such as hypercube and generalized Fibonacci cubes. These results suggest that the linear recursive networks potentially have applications in interconnecting distributed systems.
Resource-bounded partial evaluation
Authors: Saumya Debray
Venue: Proceedings of the 1997 ACM SIGPLAN symposium on Partial evaluation and semantics-based program manipulation (1997)

Most partial evaluators do not take the availability of machine-level resources, such as registers or cache, into consideration when making their specialization decisions. The resulting resource contention can lead to severe performance degradation---causing, in extreme cases, the specialized code to run slower than the unspecialized code. In this paper we consider how resource considerations can be incorporated within a partial evaluator. We develop an abstract formulation of the problem, show that optimal resource-bounded partial evaluation is NP-complete, and discuss simple heuristics that can be used to address the problem in practice.
Augmenting organizational memory: a field study of answer garden
Authors: Mark S. Ackerman
Venue: ACM Transactions on Information Systems (TOIS) (1998)

A growing concern for organizations and groups has been to augment their knowledge and expertise. One such augmentation is to provide an organizational memory, some record of the organization's knowledge. However, relatively little is known about how computer systems might enhance organizational, group, or community memory. This article presents Answer Garden, a system for growing organizational memory. The article describes the system and its underlying implementation. It then presents findings from a field study of Answer Garden. The article discusses the usage data and qualitative evaluations from the field study, and then draws a set of lessons for next-generation organizational memory systems.
Schur complement preconditioned conjugate gradient methods for spline collocation equations
Authors: Christina C. Christara
Venue: ACM SIGARCH Computer Architecture News (1990)

We are interested in the efficient solution of linear second order Partial Differential Equation (PDE) problems on rectangular domains. The PDE discretisation scheme used is of Finite Element type and is based on quadratic splines and the collocation methodology. We integrate the Quadratic Spline Collocation (QSC) discretisation scheme with a Domain Decomposition (DD) technique. We develop DD motivated orderings of the QSC equations and unknowns and apply the Preconditioned Conjugate Gradient (PCG) method for the solution of the Schur Complement (SC) system. Our experiments show that the SC-PCG-QSC method in its sequential mode is very efficient compared to standard direct band solvers for the QSC equations. We have implemented the SC-PCG-QSC method on the iPSC/2 hypercube and present performance evaluation results for up to 32 processors configurations. We discuss a type of nearest neighbour communication scheme, in which the amount of data transfer per processor does not grow with the number of processors. The estimated efficiencies are at the order of 90%.
Trading Signed Designs and Some New 4-(12, 5, 4) Designs
Authors: G. B. Khosrovshahi, A. Nowzari-Dalini, R. Torabi
Venue: Designs, Codes and Cryptography (1997)

Variations of the trade-off method exist in the literature of design theory and have been utilized by some authors to produce some t-designs with or without repeated blocks. In this paper we explore a new version of this algorithmic method (i) to produce 20 nonisomorphic and rigid 4-(12,5,4) designs, (ii) to study the spectrum of support sizes of 4-(12,5,4) designs. Along these, we also present a new design invariant for testing isomorphism among designs and a new way of representing t-designs.
On-Line Learning Fokker-Planck Machine
Authors: J. A. K. Suykens, H. Verrelst, J. Vandewalle
Venue: Neural Processing Letters (1998)

In this letter we present an on-line learning version of the Fokker-Planck machine. The method makes use of a regularized constrained normalized LMS algorithm in order to estimate the time-derivative of the parameter vector of a radial basis function network. The RBF network parametrizes a transition density which satisfies a Fokker-Planck equation, associated to continuous simulated annealing. On-line learning using the constrained normalized LMS method is necessary in order to make the Fokker-Planck machine applicable to large scale nonlinear optimization problems.
The design of an efficient simulator for the Pentium Pro processor
Authors: David A. Sykes, Brain A. Malloy
Venue: Proceedings of the 28th conference on Winter simulation (1996)

The increasing size and complexity of computer systems has created the need to develop new techniques to facilitate the design and evaluation of developing architectures. The most common technique applied to the development of new architectures is simulation, which permits detailed accurate modeling of the architecture. However, there are several problems associated with using simulation in developing computer systems. First, traditional simulation approaches are not flexible enough to permit easy extension or modification of the model. While most simulators are parameterized to provide flexibility, parameterization alone is not adequate to permit the modification and extension required for developing architectures. Second, traditional simulation approaches are computation intensive, slowing development and prohibiting simulation of large programs. To address the first problem, we use an object-oriented design for our simulator to produce a flexible, extensible model. To address the second problem, we incorporate the decode step of processor simulation into the state of each instruction object, saving the time to simulate the decode during execution. We have implemented a prototype of our design and initial experiments with the object oriented prototype, coded in C++, ran twice as fast as another prototype that we implemented using the traditional approach to simulation where the simulator was written in C.
Integrating ordinary type and many languages with the APL alphabet and keyboard
Authors: Paul Berry
Venue: ACM SIGAPL APL Quote Quad (1985)

To enjoy the advantages of APL, for too many years the APL user has had to forego &ldquo;ordinary&rdquo; characters and keyboards. This has been a major inconvenience to English-speaking North Americans, who have had to adjust to an unconventional keyboard and a character set without lower case, and even worse for Europeans, who found their national keyboards ignored and their national characters unrecognized. With improvements in technology, a change of orientation is possible. Where formerly APL was conceived as a closed system, independent of everybody else's typography, now it is possible to integrate APL with each nation's standard keyboard. This paper proposes a return to conventional lowercase and caps for APL alphabetics, keyboards that offer APL characters without disturbing conventional layouts, and a major expansion of the APL character set to embrace the characters of a world-wide set of languages.
On issues and tradeoffs in design of fault tolerant VOD servers
Authors: Leana Golubchik
Venue: ACM SIGMETRICS Performance Evaluation Review (1997)

Recent technological advances in digital signal processing, data compression techniques, and high speed communication networks have made Video-on-Demand (VOD) servers feasible. A challenging task in such systems is servicing multiple clients simultaneously while satisfying real-time requirements of continuous delivery of objects at specified rates. To accomplish these tasks and realize economies of scale associated with servicing a large user population, a VOD server requires a large disk subsystem. Although a single disk is fairly reliable, a large disk farm can have an unacceptably high probability of disk failure. Furthermore, due to real-time constraints, the reliability and availability requirements of VOD systems are even more stringent than those of traditional information systems. In this paper we discuss some of the main issues and tradeoffs associated with providing fault tolerance in multidisk VOD systems.
Text-Line Extraction and Character Recognition of Document Headlines With Graphical Designs Using Complementary Similarity Measure
Authors: Minako Sawaki, Norihiro Hagita
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1998)

A method for recognizing characters on graphical designs is proposed. A new projection feature that separates text-line regions from backgrounds, and adaptive thresholding in displacement matching are introduced. Experimental results for newspaper headlines with graphical designs show a recognition rate of 97.7 percent.
A Comprehensive Reconfiguration Scheme for Fault-Tolerant VLSI/WSI Array Processors
Authors: Yung-Yuan Chen, Shambhu J. Upadhyaya, Ching-Hwa Cheng
Venue: IEEE Transactions on Computers (1997)

This paper presents an effective reconfiguration scheme consisting of detailed spare replacement, processor placement, routing, and switch programming mechanisms. A new switch programming scheme is proposed to reduce the hardware overhead of reconfiguration. A thorough yield simulation tool has been developed for accurate prediction of yield by considering the effects of defect clusters and switching network failures. This yield simulation tool can also be used to obtain the information on the performance degradation, spare replacement, processor placement, routing and the switch programming algorithm survival probability.
Tuning architecture at run-time
Authors: E. Luque, J. Sorribes, A. Ripoll
Venue: Proceedings of the 20th annual workshop on Microprogramming (1987)

We describe the structure and operational mode of a coprocessor system which, when incorporated in a microprogrammed system to carry out Dynamic Vertical Migration, improves execution speed for any program. The coprocessor includes an interconnection mechanism between the machine code and the instruction set microcode. The interconnections (Intermediate instructions) are created in parallel with machine instruction execution and so do not increase normal execution time. This intermediate code is stored dynamically in coprocessor memory saving the fetching and decoding phases in subsequent executions, speeding up the execution of repetitive machine code. The coprocessor structure is organized around three basic elements : Interconnection Memory, Interconnection Memory Management Unit and Coprocessor Control Unit. A software simulator has been developed to analyse coprocessor behaviour and a theoretical model has been formulated from the results of these analyses.
InfoSleuth: agent-based semantic integration of information in open and dynamic environments
Authors: R. J. Bayardo,  Jr., W. Bohrer, R. Brice, A. Cichocki, J. Fowler, A. Helal, V. Kashyap, T. Ksiezyk, G. Martin, M. Nodine, M. Rashid, M. Rusinkiewicz, R. Shea, C. Unnikrishnan, A. Unruh, D. Woelk
Venue: Proceedings of the 1997 ACM SIGMOD international conference on Management of data (1997)

The goal of the InfoSleuth project at MCC is to exploit and synthesize new technologies into a unified system that retrieves and processes information in an ever-changing network of information sources. InfoSleuth has its roots in the Carnot project at MCC, which specialized in integrating heterogeneous information bases. However, recent emerging technologies such as internetworking and the World Wide Web have significantly expanded the types, availability, and volume of data available to an information management system. Furthermore, in these new environments, there is no formal control over the registration of new information sources, and applications tend to be developed without complete knowledge of the resources that will be available when they are run. Federated database projects such as Carnot that do static data integration do not scale up and do not cope well with this ever-changing environment. On the other hand, recent Web technologies, based on keyword search engines, are scalable but, unlike federated databases, are incapable of accessing information based on concepts. In this experience paper, we describe the architecture, design, and implementation of a working version of InfoSleuth. We show how InfoSleuth integrates new technological developments such as agent technology, domain ontologies, brokerage, and internet computing, in support of mediated interoperation of data and services in a dynamic and open environment. We demonstrate the use of information brokering and domain ontologies as key elements for scalability.
Web-based simulation: some personal observations
Authors: Paul A. Fishwick
Venue: Proceedings of the 28th conference on Winter simulation (1996)

The web has a short history, but has grown at an exponential pace since its introduction six years ago. Web-based simulation represents the connection between the web and the field of simulation. Web based simulation is not an existing field but rather an idea which represents an interest on the part of simulationists to exploit web technology. To further this cause, I present some issues and concepts in web based simulation to serve as a back drop for a more formal discussion, and potentially the formation of a new simulation sub-area.
Timing analysis based on primitive path delay fault identification
Authors: Mukund Sivaraman, Andrzej J. Strojwas
Venue: Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design (1997)

We present a novel timing analysis mechanism which is based on identifying primitive path delay faults (primitive PDFs) in a circuit. We show that this approach gives the exact maximum delay of the circuit under the floating mode of operation assumption. Our timing analysis approach provides a framework where component delay correlations and signal correlations arising from fabrication process, signal propagation, and signal interaction effects can be handled very accurately. Under these effects, timing analysis using previously reported floating mode timing analyzers, e.g., viability, TrueD-F etc., is very pessimistic. Our timing analysis approach based on primitive PDF identification is also more efficient than conventional floating mode path sensitization analysis mechanisms in situations where critical paths need to be re-identified due to component delay speedup (e.g., post-layout delay optimization). We demonstrate the applicability of our timing analysis approach for a variety of benchmark circuits, and demonstrate the pessimism of conventional floating mode timing analysis approaches in accounting for signal propagation effects.
Concurrency control in a VLSI design database
Authors: I. Widya, T. G. R. van Leuken, P. van der Wolf
Venue: Proceedings of the 25th ACM/IEEE Design Automation Conference (1988)

This paper explores a concurrency control mechanism which is suitable for the protection of VLSI design data against interfering concurrent accesses. VLSI design transactions are typically of long duration with frequent concurrent read-write and read-read accesses. A version mechanism is known to be very effective in long duration transaction systems with frequent concurrent read-write accesses. Although a design version mechanism, which is offered to the designers to maintain the evolution of design objects, has different aims than a version mechanism for concurrency control, a two-version mechanism fits very well in the former. This paper shows that a two-version two-phase locking mechanism, slightly adapted to a design system, is sufficient. The existence of a design manager, which prevents certain sequences of design transactions, simplifies the concurrency control protocol significantly.
On Convergence of Attainability Sets for Controlled Two-Scale Stochastic Linear Systems
Authors: Yuri Kabanov, Sergei Pergamenshchikov
Venue: SIAM Journal on Control and Optimization (1997)

A limit of attainability sets is found for a linear two-scale stochastic system for the case when the diffusion coefficient of the fast variable is of order $\varepsilon^{1/2}$. The attainability set is defined as the set of distributions of attainable terminal values of solutions of stochastic differential equations. As a corollary we calculate a limit of the optimal value of the terminal cost in the stochastic Mayer problem.