In Search of the Origin of VHDL's Delta Delays
Venue: Proceedings of the 3rd International Symposium on Quality Electronic Design (2002)

Delta delays permeate the current VHDL 1076 standard and have been a source of much confusion and serious problems. The original VHDL architects had introduced delta delays in VHDL, motivated by the following scenario. When a digital system consists of two components Cl and C2 with delays dl and d2 respectively, such that dl >> d2, it should be fine to treat d2 as zero in the simulation and thereby enhance the simulation throughput. Thus, the user was encouraged to ignore the delay for C2 and assured that the simulation would still generate accurate results. The architects soon discovered, upon implementation, that zero delays lead to uncertainty in simulation, especially for sequential systems, a fact that had already been well documented in the simulation literature. To resolve the problem, they introduced the notion of delta delays wherein the VHDL compiler, at compile time, first detects and then automatically replaces every instance of zero delay usage in a VHDL description, with a delta delay. While the VHDL 1076 language reference manual (LRM) does not provide much details, a delta delay value is a non-zero time interval, selected by the VHDL compiler, such that an indefinite number of such intervals may be accommodated within a simulation timestep .The simulation timestep is clearly defined by those delays of components, such as dl, that are significant. According to the architects, this new notion of delta delays is guaranteed to yield accurate simulation results, despite ignoring component delays such as d2 and without any further user intervention. In essence, the notion of delta delay imparted a false sense of trust among users in that VHDL had somehow solved the problem with zero delays and this tempted designers to use zero delays freely and without appropriate restraint. Not surprisingly, this has led spurious errors that not only confront designers with inconsistent simulation results but defy insight into the cause of the error. To address these problems, a number of VHDL handbooks have included special sections on how to get around such problems in VHDL and, at leading international HDL conferences, during presentations, authors and members of the audience exchange information on how to avoid pitfalls in VHDL by writing tricky code. All of these clearly contradict the spirit of objectivity and logic in science and is of great concern since ICs and computers designed in VHDL will continue to fly planes, control nuclear reactors and power stations, and run the nation's financial system. The greatest conceptual difficulty with delta delay is that it constitutes a significant impediment to the concurrent execution of VHDL models on parallel processors in the future. While the error with delta delay is undeniable and seems readily visible, it is intellectually puzzling how and when delta delay successfully bypassed a critical and rigorous scientific analysis. Since VHDL architects claim to have borrowed the concept directly from Conlan's BCL model of time, one must examine BCL to uncover the truth. Unfortunately, even the literature on BCL offers no direct reasons underlying the need to introduce it. Thus, the search must play detective namely, turn to history and critically examine the contemporary scientific thinkings and technical developments, especially in modeling continuous electronic systems through discrete event techniques. This paper uncovers a plausible explanation, one that is logical and self-consistent, relative to the origin of BCL which, in turn, reveals the source of the problem with delta delays. The paper explains the scientific difficulties with delta delays and offers a solution to the problem that is practically realizable and, surprisingly, straightforward and simple.