ppxscal/embedding_network huggingface dataset:
Hadamard Matrices from Weighing Matrices via Signed Groups
Authors: R. Craigen, H. Kharaghani
Venue: Designs, Codes and Cryptography (1997)

We further develop the ideas introduced in [4], giving a fuller description of how to obtain Hadamard matrices from certain weighing matrices. Drawing on sequences with zero autocorrelation and the theory of signed groups, we give classes of Hadamard matrices including at least 170 new orders 2^tp,p \leq 3999 . We also illustrate how this method increases the versatility of some recent constructions that use block sequences.
Analysis of the Spatial Error for a Class of Finite Difference Methods for Viscous Incompressible Flow
Authors: Brian R. Wetton
Venue: SIAM Journal on Numerical Analysis (1997)

Several first- and second-order finite difference methods for incompressible flow based on prescribed forms of the discrete gradient and divergence operators are considered. Expansions for the spatial error for these methods are presented. So-called alternating expansions and numerical boundary layers are required to describe the errors arising from schemes with decoupled pressure approximations and regularizing terms, respectively. Alternating expansions in the discrete projection operator can be amplified by the viscous term and lead to a reduction in the accuracy of the computed pressure. These error expansions can be combined with simple stability estimates to show the convergence of the discrete solutions to the nonlinear time-dependent and steady problems when a discrete adjoint condition is satisfied. However, the analysis here does not consider the split-step nature of projection methods. Convergence order predictions are verified in a careful numerical study.
Simulation modeling and optimization using ProModel
Authors: Deborah Benson
Venue: Proceedings of the 28th conference on Winter simulation (1996)

The ProModel optimization Suite is a powerful yet easy-to-use simulation tool for modeling all types of manufacturing systems ranging from small job shops and machining cells to large mass production and flexible manufacturing systems. ProModel is a Windows based system with an intuitive graphical interface and object-oriented modeling constructs that eliminate the need for programming. It combines the flexibility of a general purpose simulation language with the convenience of a data-driven simulator. In addition, ProModel utilizes an optimization tool called SimRunner which performs sophisticated "what-if" analysis by running automatic factorial design of experiments on the model, providing the best answer possible. This tutorial provides an overview of the ProModel Optimization Suite and presents its modeling, analysis, and optimization capabilities.
Delay bounded buffered tree construction for timing driven floorplanning
Authors: Maggie Kang, Wayne W.-M. Dai, Tom Dillinger, David LaPotin
Venue: Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design (1997)

As devices and lines shrink into the deep submicron range, the propagation delay of signals can be effectively improved by repowering the signals using intermediate buffers placed within the routing trees. Almost no existing timing driven floorplanning and placement approaches consider the option of buffer insertion. As such, they may exclude solutions, particularly early in the design process, with smaller overall area and better routability. In this paper, we propose a new methodology in which buffered trees are used to estimate wire delay during floorplanning. Instead of treating delay as one of the objectives, as done by the majority of previous work, we formulate the problem in terms of Delay Bounded Buffered Trees (DBB-tree) and propose an efficient algorithm to construct a DBB spanning tree for use during floorplanning. Experimental results show that the algorithm is very effective. Using buffer insertion at the floorplanning stage yields significantly better solutions in terms of both chip area and total wire length.
The use of simulation in the optimization of a cellular manufacturing system
Authors: Stacy M. Sammons, Jeffery K. Cochran
Venue: Proceedings of the 28th conference on Winter simulation (1996)

In the evaluation of a cellular manufacturing system, multiple factors should be considered, including the flow of the parts and the assignment of the workers. Simulation techniques can be effectively used in order to understand and optimize the behavior of the system. In this paper, a work cell is evaluated by means of discrete simulation using SLAM It. An optimization method is presented to determine the best alternative among proposed changes to the system. The structure of the approach allows the optimization to be performed with direction given by management. The results reveal that priority ranking of the parts, automated testing, and distributed job functions implemented together would produce the most significant improvement in the utilization of the team members.
Node-covering, Error-correcting Codes and Multiprocessors with Very High Average Fault Tolerance
Authors: Shantanu Dutt, Nihar R. Mahapatra
Venue: IEEE Transactions on Computers (1997)

Structural fault tolerance (SFT) is the ability of a multiprocessor to reconfigure around faulty processors or links in order to preserve its original processor interconnection structure. In this paper, we focus on the design of SFT multiprocessors that have low switch and link overheads, but can tolerate a very large number of processor faults on the average. Most previous work has concentrated on deterministic k-fault-tolerant (k-FT) designs in which exactly k spare processors and some spare switches and links are added to construct multiprocessors that can tolerate any k processor faults. However, after k faults are reconfigured around, much of the extra links and switches can remain unutilized. It is possible within the basic node-covering framework, which was introduced by Dutt and Hayes as an efficient k-FT design method, to design FT multiprocessors that have the same amount of switches and links as, say, a two-FT deterministic design, but have s spare processors, where $s \gg 2,$ so that, on the average, k = ¿(s) (k¿s) processor failures can be reconfigured around. Such designs utilize the spare link and switch capacity very efficiently, and are called probabilistic FT designs. An elegant and powerful method to construct covering graphs or CG's, which are key to obtaining the probabilistic FT designs, is to use linear error-correcting codes (ECCs). We show how to construct probabilistic designs with very high average fault tolerance but low wiring and switch overhead using ECCs like the 2D-parity, full-two, 3D-parity, and full-three codes. This design methodology is applicable to any multiprocessor interconnection topology and the resulting FT designs have the same node degree as the non-FT target topology. We also analyze the deterministic fault tolerance for these designs and develop efficient layout strategies for them. Finally, we compare the proposed probabilistic designs to some of the best deterministic and probabilistic designs proposed in the past, and show that our designs can meet a given mean-time-to-failure (MTTF) specification at much lower hardware costs (switch complexity, redundant wiring area, and spare-processor overhead) than previous designs. Further, for a given number of spare processors, our designs have close-to-optimal reconfigurabilities that are much better than those of previous probabilistic designs.
Splicer: a heuristic approach to connectivity binding
Authors: Barry M. Pangre
Venue: Proceedings of the 25th ACM/IEEE Design Automation Conference (1988)

This paper describes a tool for constructing the connectivity between hardware components given a stategraph that the components are to be mapped into. Examples taken from previous papers in the field are used to demonstrate this connectivity binder. The important results of this paper point to heuristics that are used to generate solutions to the problem. Questions addressed include: how much of the state-graph must be considered at one time to give reasonable results and how the search space can be pruned to achieve good solutions quicker. The code for this project is written in C and runs under 4.2 BSD UNIX.
Events which will influence intensive care units in future
Authors: Wolfgang Friesdorf, Bernd Classen, Bernhard Schwilk, Sergio Konichezky
Venue: Technology and Health Care (1997)

Objective: To find out and analyse the events which are expected to influence the future of Intensive Care Units (ICU). Design: Three round Delphi study. Setting: In a first preparation round 9 events were defined. In the two rating rounds an international panel of 60 experts (heads of ICUs) estimated the time when the events may come true and whether they are desired or not. Results: Computer tools are desired and expected in the near future (before the year 2000) for audit, quality assurance, record keeping and telecommunication; complex closed loops and nursing robots will not be used in clinical routine before 2005, they are not desired.
Formal models of distributed memory management
Authors: Christian Ungureanu, Benjamin Goldberg
Venue: Proceedings of the second ACM SIGPLAN international conference on Functional programming (1997)

We develop am abstract model of memory management in distributed systems. The model is low-level enough so that we can express communication, allocation and garbage collection, but otherwise hides many of the lower-level details of an actual implementation.Recently, such formal models have been developed for memory management in a functional, sequential setting [10]. The models are rewriting systems whose terms are programs. Programs have both the "code" (control string) and the "store" syntactically apparent. Evaluation is expressed as conditional rewriting and includes store operations. Garbage collection becomes a rewriting relation that removes part of the store without affecting the behavior of the program.Distribution adds another dimension to an already complex problem. By using techniques developed for communicating and concurrent systems [9], we extend their work to a distributed environment. Sending and receiving messages is also made apparent at the syntactic level. A very general garbage collection rule based on reachability is introduced and proved correct. Now proving correct a specific collection strategy is reduced to showing that the relation between programs defined by the strategy is a sub-relation of the general relation. Any actual implementation which is capable of providing the transitions (including their atomicity constraints) specified by the strategy is therefore correct.This model allows us to specify and prove correct in a compact manner two garbage collectors; the first one does a simple garbage collection local to a node. The second garbage collector uses migration of data in order to be able to reclaim inter-node cyclic garbage.
3D Symmetry Detection Using The Extended Gaussian Image
Authors: Changming Sun, Jamie Sherrah
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1997)

Symmetry detection is important in the area of computer vision. A 3D symmetry detection algorithm is presented in this correspondence. The symmetry detection problem is converted to the correlation of the Gaussian image. Once the Gaussian image of the object has been obtained, the algorithm is independent of the input format. The algorithm can handle different kinds of images or objects. Simulated and real images have been tested in a variety of formats, and the results show that the symmetry can be determined using the Gaussian image.
Recursive channel router
Authors: W. Heyns, K. Van Nieuwenhove
Venue: Proceedings of the 25th ACM/IEEE Design Automation Conference (1988)

This paper describes an extended 'true' VHV-model 3 layer channel routing algorithm. The algorithm is based on the observation that, after having routed a track on either the top or bottom side of the channel, one can define a new channel routing problem and call the router recursively. The routing task then is reduced to making optimal use of a track. Routing of a track is done in 2 steps. For the first step, we will present a segment selection method, which aims at reducing the channel density. The second step further fills up the track and, at the same time, aims at reducing the heights of the vertical constraint graphs.
Beyond ML
Authors: John C. Reynolds
Venue: ACM SIGPLAN Notices (1997)

We believe that the most pressing problem in programming-language design is to control the interference that arises when functional and imperative programming are combined, and to give the user more control of storage allocation, without sacrificing the virtues of higher-order procedures, rigorous typing, and modularity that characterize ML. Towards this end, we intend to pursue research on Algol-like languages, linear typing, and the use of regions for storage allocation.
Symbolic Handling of Bridging Fault Effects
Authors: Michele Favalli, Marcello Dalpasso
Venue: Journal of Electronic Testing: Theory and Applications (1997)

This paper introduces a new fault simulation methodology based on symbolic handling of fault effects. Boolean variables are related to faulty signals, and fault effects are propagated by computing gate output expressions by means of BDDs. The proposed technique can handle in a single simulation step such faults as resistive bridges, that exhibit a parametric behavior, thus requiring more simulations with conventional techniques.
On retrieval tests with an inhomogeneous query collection
Authors: Friedbert Jochum
Venue: Proceedings of the 8th annual international ACM SIGIR conference on Research and development in information retrieval (1985)

Retrieval tests are often performed with an inhomogeneous query collection, that means certain properties of queries vary within the collection. This paper investigates under which conditions this inhomogeneity may lead to a loss of measurement precision and validity and should be controlled by an experimental design. In particular, interrelationships between the design of a retrieval test, inhomogeneity of the query collection and measurement theoretical properties of the evaluation measure will be discussed. Based on these results, some recommendations for experimental design of retrieval tests are presented.
A Family of Symplectic Integrators: Stability, Accuracy, and Molecular Dynamics Applications
Authors: Robert D. Skeel, Guihua Zhang, Tamar Schlick
Venue: SIAM Journal on Scientific Computing (1997)

The following integration methods for special second-order ordinary differential equations are studied: leapfrog, implicit midpoint, trapezoid, Störmer--Verlet, and Cowell--Numerov. We show that all are members, or equivalent to members, of a one-parameter family of schemes. Some methods have more than one common form, and we discuss a systematic enumeration of these forms. We also present a stability and accuracy analysis based on the idea of "modified equations" and a proof of symplecticness. It follows that Cowell--Numerov and "LIM2" (a method proposed by Zhang and Schlick) are symplectic. A different interpretation of the values used by these integrators leads to higher accuracy and better energy conservation. Hence, we suggest that the straightforward analysis of energy conservation is misleading.
Cipher Instruction Search Attack on the Bus-Encryption Security Microcontroller DS5002FP
Authors: Markus G. Kuhn
Venue: IEEE Transactions on Computers (1998)

A widely used bus-encryption microprocessor is vulnerable to a new practical attack. This type of processor decrypts on-the-fly while fetching code and data, which are stored in RAM only in encrypted form. The attack allows easy, unauthorized access to the decrypted memory content.
How to preserve the benefits of design patterns
Authors: Ellen Agerbo, Aino Cornils
Venue: ACM SIGPLAN Notices (1998)

The rapid evolution of Design Patterns has hampered the benefits gained from using Design Patterns. The increase in the number of Design Patterns makes a common vocabulary unmanageable, and the tracing problem obscures the documentation that should be enhanced by using Design Patterns. We present an analysis of Design Patterns that will strongly reduce the number of Fundamental Design Patterns and show how strong language abstractions can solve the tracing problem and thereby enhance the documentation.
The implementation of the hierarchical abstract simulator on the HEP computer
Authors: Arturo I. Concepcion
Venue: Proceedings of the 17th conference on Winter simulation (1985)

A methodology is being developed to map the hierarchical abstract simulator onto distributed simulator architectures. The hierarchical abstract simulator is a multicomponent, multilevel discrete event models communicating via message passing. This paper reports on an alternative mapping realization of the hierarchical abstract simulator by using DENELCOR's FORTRAN 77, an extension of FORTRAN 77 for parallel programming, on the Heterogeneous Element Processor (HEP) computer. Several runs were made on the implementation and it was found out that there are three constraints that affect the performance (execution time) of the HEP implementation: number of processors available, degree of synchronization and intercommunication, and workload.
Formal semantics of confidentiality in multilevel logic databases
Authors: Adrian Spalka
Venue: Proceedings of the 1994 workshop on New security paradigms (1994)

This paper presents a new formal approach to the definition of confidentiality in multilevel logic databases. We regard a multilevel secure database as an extension of an open database which preserves the database-semantics. We give four definitions of confidentiality which capture various degrees of information on secrets. Three of them are relevant in the presence of the Closed World Assumption. We present their formalisation within standard predicate logic and their interpretation for multilevel databases. From this viewpoint, the definitions lead to a formal semantics of the Simple-Security-Property and the *-property. In particular, we demonstrate that the traditional interpretation of these properties represents just a special case of our formalism.
Exploring Martian planetary images: C++ exercises for CS1
Authors: Harriet J. Fell, Viera K. Proulx
Venue: ACM SIGCSE Bulletin (1997)

We present a series of programming exercises based on photographic images of Mars collected by the NASA Viking Orbiter. Even without the news that there may once have been life on Mars [1], we feel that these exercises provide an exciting platform for exploring machine representation of data, presentation of data, and methods of storing and extracting data from files. All exercises are on the level easily mastered in the first programming course.
Equiorthogonal Frequency Hypercubes: Preliminary Theory
Authors: Ilene H. Morgan
Venue: Designs, Codes and Cryptography (1998)

Using a strong definition of frequency hypercube, we define a strengthened form of orthogonality, called equiorthogonality, for sets of such hypercubes. We prove that the maximum possible number of mutually equiorthogonal frequency hypercubes (MEFH) of order n and dimension d based on m distinct symbols is (n-1)^d/(m-1). A set of (n-1)^d/(m-1) such MEFH is called a complete set. Because of the stronger conditions on the hypercubes, we can find complete sets of MEFH of all lower dimensions within any complete set of MEFH; this useful property is not shared by sets of mutually orthogonal hypercubes using the usual, weaker definition.
Partial scan delay fault testing of asynchronous circuits
Authors: Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexander Saldanha, Alexander Taubin
Venue: Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design (1997)

Asynchronous circuits operate correctly only under timing assumptions. Hence testing those circuits for delay faults is crucial. This paper describes a three-step method to detect possible delay faults in a sequential asynchronous circuit. The delays that are to be tested must be provided by the synthesis system. By using this information a set of paths in the circuit that must be tested is identified (step 1). For these paths the circuit is made acyclic by inserting at least one scan latch in every cycle (step 2). Then test patterns are generated for these paths (step 3). These test patterns consist of setup and initialization vectors and the final test vector. We provide effective procedures to solve both the initialization and the test pattern generation problem. The latter problem is solved by reduction to a classical problem of stuck-at test pattern generation for a related combinational circuit. Finally, a heuristic is proposed to determine which state variables must become part of a scan chain, or for which input variables the positive and negative phase must be driven independently in test mode. Experimental results shows that a high level of path delay fault testability can be achieved with partial scan.
Goal driven simulation intelligent back ends: a state of the art review
Authors: Louis A. Molina, Carlos Gandarillas, Martha A. Centeno
Venue: Proceedings of the 28th conference on Winter simulation (1996)

Goal driven simulation (GDS) seeks to automate many of the output analysis and experimental design tasks of a simulation study. Theoretically, its use allows the reallocation of the simulation expert to other tasks. ODS capabilities include determining parameters to change, suggesting a rate of change, and testing these changes against a pre-established set of goals. Realizing GDS, however, requires the integration of techniques such as object oriented design, knowledge based systems, and neural nets. Before achieving this integration, there are still several issues to resolve including the type of interaction these techniques would have among themselves. This paper explores several of the issues concerning the realization of goal driven simulation systems, their impact on the simulation modeling methodology, how GDS works, and the need for its development.
Evaluating software engineering methods and tool part 5: the influence of human factors
Authors: Barbara Ann Kitchenham, Lindsay Jones
Venue: ACM SIGSOFT Software Engineering Notes (1997)

In previous articles, we have considered a number of general issues concerned with evaluating methods and tools. In the next few articles we describe how to perform a specific type of evaluation exercise called Feature Analysis.This article discusses the principles of feature analysis and describes how to identify features and establish a means of scoring products against those features. Later articles consider how to plan a feature-based evaluation and how to analyze the results of an evaluation.
Discovering models of software processes from event-based data
Authors: Jonathan E. Cook, Alexander L. Wolf
Venue: ACM Transactions on Software Engineering and Methodology (TOSEM) (1998)

Many software process methods and tools presuppose the existence of a formal model of a process. Unfortunately, developing a formal model for an on-going, complex process can be difficult, costly, and error prone. This presents a practical barrier to the adoption of process technologies, which would be lowered by automated assistance in creating formal models. To this end, we have developed a data analysis technique that we term process discovery. Under this technique, data describing process events are first captured from an on-going process and then used to generate a formal model of the behavior of that process. In this article we describe a Markov method that we developed specifically for process discovery, as well as describe two additional methods that we adopted from other domains and augmented for our purposes. The three methods range from the purely algorithmic to the purely statistical. We compare the methods and discuss their application in an industrial case study.