ppxscal/embedding_network huggingface dataset:
SpikeCell: a deterministic spiking neuron
Authors: C. Godin, M. B. Gordon, J. D. Muller
Venue: Neural Networks (2002)

We present a model of spiking neuron that emulates the output of the usual static neurons with sigimodial activation functions. It allows for hardware implementations of standard feedforward networks, trained off-line with any classical learning algorithm (i.e. back-propagation and its variants). The model is validated on hand-written digits recognition, and image classification tasks. A digital architecture is proposed and evaluated. The area needed for implementing the spiking neuron on a chip is 10 times smaller than that for the corresponding static neuron. The accuracy of the network's output increases with time, and reaches that of the emulated static neural network after an adequate integration period. Single errors in the spike trains, or interruption of the relaxation process, due for example to irradiation in harsh environments, are harmless.
Modeling and simulation of mixed traffic on a prioritized shared medium
Authors: Jeffrey J. Evans Cynthia S. Hood
Venue: International Journal of Network Management (2003)

Network access systems (NAS) such as digital loop carriers (DLC) are increasingly utilizing a shared medium, such as Hybrid Fiber Coax (HFC) to provide point-to-multi-point access from the public switched telephone network (PSTN) to the end user (consumer). New services, such as direct access to the packet switched network (PSN, WWW) have been added to DLC equipment in such a way as to provide for a prioritized set of services over a shared medium in an effort to take advantage of otherwise unused bandwidth. The introduction of such services requires the modeling and analysis of these network access systems. This becomes complex when considering the variability in different service type traffic characteristics. This work identifies a traffic engineering problem of prioritized circuit switched and packet switched (PSTN/PSN) traffic over the same shared medium as it may relate to &ldquo;perceived&rdquo; quality of service (QoS).
Counting Photons in the &Lambda;-Experiment
Authors: Anita Dabrowska
Venue: Open Systems Information Dynamics (2002)

Dehmelt's &Lambda;-experiment for a three-level atom with simultaneously driven strong and weak transition is studied within quantum stochastic calculus approach. The statistics of the emitted photons is found by the method of generating functional of the corresponding two-dimensional output counting process. In particular, the average waiting times for a count are calculated.
From Multimedia Retrieval to Knowledge Management
Authors: Pedro J. Moreno, J. M. Van Thong, Beth Logan, Gareth J. F. Jones
Venue: Computer (2002)

Despite recent advances, multimedia use in knowledge management remains largely limited to retrieval systems. Multimedia data introduces several challenges to KM systems, including the uncertainties associated with media analyzers and the need for good scalability and effective user interfaces. Architectures capable of handling system complexity will also play a crucial role in deploying multimedia-based KM solutions. The prospects for fully exploiting multimedia content are promising. Given current trends in audio and video analysis, multimedia storage and distribution over the Internet, developments in XML representations, and integration with knowledge portals, the authors expect multimedia data to become truly pervasive.
Multilevel Filtering for High-Dimensional Image Data: Why and How
Authors: Raymond T. Ng, Dominic Tam
Venue: IEEE Transactions on Knowledge and Data Engineering (1999)

It has been shown that filtering is a promising way to support efficient content-based retrievals from image data. However, all existing studies on filtering restrict their attention to two levels. In this paper, we consider filtering structures that have at least three levels. In the first half of the paper, by analyzing the CPU and I/O costs of various structures, we provide analytic evidence on why three-level structures can often outperform corresponding two-level ones. We provide further experimental results showing that the three-level structures are typically the best, and can beat the two-level ones by a wide margin. In the second half of the paper, we study how to find the (near-) optimal three-level structure for a given dataset. We develop an optimizer that can handle this task effectively and efficiently. Experimental results indicate that in tens of seconds of CPU time, the optimizer can find a filtering structure whose total runtime per query exceeds that of the real optimal structure by only 2-3 percent .
Cracking the 500-Language Problem
Authors: Ralf Lämmel, Chris Verhoef
Venue: IEEE Software (2001)

Constructing analysis and modification tools for software assets is laborious because you first need to implement the underlying parser for the software's specific programming language. These implementations are generally not in the public domain. So, parser development for any of the 500+ languages in use today implies a major up-front investment. The authors propose a solution that will work for virtually all languages: the rapid development of renovation parsers by stealing the grammars. They also share lessons learned.
A Service Acquisition Mechanism for Server-Based Heterogeneous Distributed Systems
Authors: R. N. Chang, C. V. Ravishankar
Venue: IEEE Transactions on Parallel and Distributed Systems (1994)

This paper presents a mechanism that facilitates and enhances the use of independentlyadministered remote network servers in the presence of server interface heterogeneity.The mechanism is designed under the client-service model, which extends theclient-server model with an abstraction of service to decouple abstract server capabilitiesfrom concrete server interface specifics such as server interface binding protocols andthe interface operation invocation protocols. The mechanism selects servers,accommodates server interface heterogeneity, and handles server access failures as perthe abstract server capabilities desired by the client. It could return the identity of theserver used for each service access invocation to facilitate billing, refining servicespecifications, and reporting server-specific errors. This paper also illustrates a C libraryinterface to this mechanism, and describes a language veneer over the C programminglanguage demonstrating how a typed procedural language could be extended by a fewlanguage constructs to support the mechanism under the client-service model. In thislanguage, server capabilities are referenced by abstract data type (ADT) objects, and areaccessed by invoking the objects' interface operations using a call-by-value-resultparadigm.
CMOS Circuits with Subvolt Supply Voltages
Authors: Mircea R. Stan
Venue: IEEE Design Test (2002)

This overview of multiple-voltage use in low-power design proposes a circuit taxonomy to help determine the most effective low-power techniques for specific circuit types and presents related simulation results.
Low power system scheduling and synthesis
Authors: Niraj K. Jha
Venue: Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design (2001)

Many scheduling techniques have been presented recently which exploit dynamic voltage scaling (DVS) and dynamic power management (DPM) for both uniprocessors and distributed systems, as well as both real-time and non-real-time systems. While such techniques are power-aware and aim at extending battery lifetimes for portable systems, they need to be augmented to make them battery-aware as well. We will survey such power-aware and battery-aware scheduling algorithms. Also, system synthesis algorithms for real-time systems-on-a-chip (SOCs), distributed and wireless client-server embedded systems, etc., have begun optimizing power consumption in addition to system price. We will survey such algorithms as well, and point out some open problems.
Developing the AMD-K5 Architecture
Authors: Dave Christie
Venue: IEEE Micro (1996)

The K5TM microprocessor project at AMD created the basis for Advanced Micro Devices' first independently designed implementations of the x86 architecture. The first-time nature of this project, coupled with the complexity of the x86 architecture, presented many unique challenges and constraints to the designers. Nevertheless, the end result is the only x86-compatible microprocessor architecture that can speculatively decode and execute up to four x86 instructions at a time, with out-of-order instruction execution. An equally significant result of the project is a very robust x86 development and verification methodology.
An algorithm for simultaneous pin assignment and routing
Authors: Hua Xiang, Xiaoping Tang, D. F. Wong
Venue: Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design (2001)

Macro-block pin assignment and routing are important tasks in physical design planning. Existing algorithms for these problems can be classified into two categories: 1) a two-step approach where pin assignment is followed by routing, and 2) a net-by-net approach where pin assignment and routing for a single net are performed simultaneously. None of the existing algorithms is "exact" in the sense that the algorithm may fail to route all nets even though a feasible solution exists. This remains to be true even if only 2-pin nets between two blocks are concerned. In this paper, we present the first polynomial-time exact algorithm for simultaneous pin assignment and routing for 2-pin nets from one block (source block) to all other blocks. In addition to finding a feasible solution whenever one exists, it guarantees to find a pin-assignment/routing solution with minimum cost &alpha; &middot; W + &beta; &middot; V, where W is the total wirelength and V is the total number of vias. Our algorithm has various applications: 1) It is suitable in ECO (Engineering Change Order) situations where a designer wants to incrementally modify the existing solution instead of redoing everything after a design change. 2) Given any pin assignment and routing solution obtained by any existing method, our algorithm can be used to increase the number of routed nets and reduce the routing cost. Furthermore, it provides an efficient algorithm for the pin assignment and routing problem of all blocks. The method is applicable to both global and detailed routing with arbitrary routing obstacles on multiple layers. Experimental results demonstrate its efficiency and effectiveness.
A Low-Power Network for On-Line Diagnosis of Heart Patients
Authors: Richard Coggins, Marwan Jabri, Barry Flower, Stephen Pickard
Venue: IEEE Micro (1995)

A system has been developed for the classification of Intracardiac Electrograms (ICEG). The system is comprised of an analog VLSI neural network, an Implantable Cardioverter Defibrillator (ICD) and a PC-based software training environment. Analog implementation techniques were chosen to meet the strict power and area requirements of implantable systems. The robustness of the neural network architecture reduces the impact of noise, drift, and offsets inherent in analog approaches. The neural network chip is a 10:6:3 multilayer perceptron with on- chip digital weight storage, a bucket brigade input to feed the ICEG to the network and a winner-take-all circuit at the output. The chip was implemented in 1.2-um CMOS and consumes less than 200-nW maximum average power in an area of 2.2x2.2mm2. The network was trained in loop with the ICD in the signal processing path. Results are presented, demonstrating the advantages of combining neural network and and low-power analog circuit techniques by distinguishing certain dangerous arrhythmia, not currently possible in existing ICDs.
Advanced Hi-Fill&#x00AE; for interconnect liner applications
Authors: N. Urbansky, S. R. Burgess, S. Schmidbauer, U. Heydenreich, H. Donohue, I Moncrieff, C. Görgens
Venue: Microelectronic Engineering (2002)

Ti/TiN liner and barrier deposition for low contact resistance tungsten plug interconnect metallisation schemes represent a major challenge for current and future aspect ratios of interconnect vias. For Ti, bottom coverage is important to minimise contact and via resistance and for TiN, good sidewall coverage is required to maintain the integrity of the W fill process. This paper describes the fundamental operation and characterisation of a novel ionised dual metal/metal nitride deposition chamber--Advanced Hi-Fill®. Discussed is the incorporation of Advanced Hi-Fill® technology into a BEOL production environment. Production data for via level interconnects manufactured in a 0.17-µm logic product as well as contact level for a 0.14-µm DRAM product is presented.
Regularity driven logic synthesis
Authors: Thomas Kutzschebauch, Leon Stok
Venue: Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design (2000)

We present a new and innovative logic synthesis approach using regularity information of a design to selectively apply transformations and globally guide the synthesis process.Since traditional logic synthesis applies transformations without consideration of global design characteristics such as regularity and dataflow, it destroys a substantial amount of regular structures. In addition, due to the non-incremental nature of most logic transformations, synthesis relies vastly on the computationally expensive concept of trial and error application of transformations, a time-consuming process in the synthesis of large designs.The proposed approach addresses both shortcomings of traditional logic synthesis and describes a mechanism to speed up logic synthesis and preserve regularity. It selectively applies transformations to places with similar characteristics and to the same stage of a regular structure, introducing a notion of dataflow-aware synthesis.Preservation of regular structures has tremendous advantages to the following physical design stages. It yields high-density layouts, shorter wiring length and improved delay. In addition, the layout becomes more predictable at an earlier design stage.
An O(log2 N) Depth Asymptotically Nonblocking Self-Routing Permutation Network
Authors: C. Ferrone, G. a. De Biase, A. Massini
Venue: IEEE Transactions on Computers (1995)

A self-routing multi-logN permutation network is presented and studied. This network has 3log2N¿ 2 depth and $N(\log_2^\gamma N)$(3log2, N¿ 2)/2 nodes, where N is the number of network inputs and ¿ a constant very close to 1. A parallel routing algorithm runs in 3log2N¿ 2 time on this network. The overall system (network and algorithm) can work in pipeline and it is asymptotically nonblocking in the sense that its blocking probability vanishes when N increases, hence the quasi-totality of the information synchronously arrives in 3log2N¿ 2 steps at the network outputs. This network presents very good fault tolerance, a modular architecture, and it is suitable for information exchange in very large scale parallel processors and communication systems.
A Neural Network Model of Semantic Processing Errors in Parkinson&lsquo;s Disease
Authors: Paul A. Watters, Malti Patel
Venue: Neural Processing Letters (1999)

Recent research has indicated that degradation of dopaminergic pathways in the mesolimbic forebrain and neocortex are related to the language processing deficits observed in Parkinson&lsquo;s disease (PD) patients, with experimental investigations indicating that the semantic system suffers the greatest impairment. PD patients make slower responses and more errors in semantic judgement tasks compared to controls, even though nonsemantic performance on word-search tasks is unimpaired. These findings are used in this study to predict the performance of the semantic system of the dual-route model of skilled reading (DRC), where the connection strengths between word and word sense levels in the system are systematically manipulated to produce PD-like reductions in dopamine transmission. Low excitation between layers is predicted to produce PD errors in semantic judgements of polysemous words which have a low sense-frequency delta (s.f.d.), that is, a small difference in sense frequency between at least two word senses. Judgements made on high s.f.d words resulted in 100% correct responses over all excitation values, with a stable solution reached at 39&ndash;48 epochs. However, for low s.f.d words, incorrect responses were made for low to medium levels of excitation (30&ndash;50% errors), only providing the correct solution for medium to high levels of excitation. An interaction was also observed for low s.f.d words between high lateral inhibition in the word sense level, and low-medium excitation, to produce the results most characteristic of PD semantic errors. The results of this study confirm that competitive and inhibitory mechanisms related to dopaminergic gain are responsible for impaired PD performance on semantic processing tasks.
CD-ROM: Technology Whose Time Is Coming (Soon)
Venue: IEEE Software (1990)

No abstract available The ACM Portal is published by the Association for Computing Machinery. Copyright © 2010 ACM, Inc. Terms of Usage Privacy Policy Code of Ethics Contact Us Useful downloads: Adobe Acrobat QuickTime Windows Media Player Real Player
A Knowledge-Based Environment for Modeling and Simulating Software Engineering Processes
Authors: P. Mi, W. Scacchi
Venue: IEEE Transactions on Knowledge and Data Engineering (1990)

The design and representation schemes used in constructing a prototype computational environment for modeling and simulating multiagent software engineering processes are described. This environment is called the articulator. An overview of the articulator's architecture identifying five principal components is provided. Three of the components, the knowledge metamodel, the software process behavior simulator, and a knowledge base querying mechanism, are detailed and examples are included. The conclusion reiterates what is unique to this approach in applying knowledge engineering techniques to the problems of understanding the statics and dynamics of complex software engineering processes.
A Fault-Tolerant Distributed Subcube Management Scheme for Hypercube Multicomputer Systems
Authors: Yi-long Chen, Jyh-Charn Liu
Venue: IEEE Transactions on Parallel and Distributed Systems (1995)

This paper proposes a fault-tolerant distributed subcube management scheme for hypercube multicomputer systems. Gracefully degradable subcube management is supported by a data structure, called the distributed subcube table (DST), and a fault-tolerant broadcast protocol, called the reliably synchronized broadcast (RSB). In an n-dimensional hypercube, DST is the collection of 2nlocal subcube tables (LSTs), ${\mbi DST = \{LST_0,\,LT_1,\,\dots,\,LST^n_{2-1}\}}$, where LSTx is a bit-mapped table assigned to Nx, a fault-free node whose address is x. LSTx, ¿x, is n+ 1 bits long, and it records the status (free/busy) of certain subcubes adjacent to Nx. The RSB diagnoses and avoids faults during interprocessor communication to prevent faulty nodes from being allocated for job execution. In addition to possessing a fault-tolerant design, our scheme can also achieve comparable or better performance than existing centralized schemes, as verified by extensive simulation.
Adaptive QoS parameters approach to modeling Internet performance
Authors: Shin-Jer Yang, Hung-Cheng Chou
Venue: International Journal of Network Management (2003)

Due to the recent advances in Internet technologies and applications, the issue of Quality of Service (QoS) is more essential to Internet performance. In this paper, we address and discuss the influence factors and also finalize the QoS parameters for Internet performance. Then we present the simulation procedure for monitoring the performance evaluation and propose the algorithm for tuning the performance value. Based on simulation results and performance analysis, we can tune and adjust possible parameters' values and then refine the influence level of each QoS parameter. Finally, Internet performance can be enhanced and maintained through using the proposed approach over several sub-networks. Hence, it increases the adaptability for implementing the QoS Internet.
Solving dimensioning tasks for proportionally fair networks carrying elastic traffic
Authors: Pål Nilsson, Michal Pióro
Venue: Performance Evaluation (2002)

The paper studies optimal dimensioning problems associated with the notion of "proportional fairness" (PF) considered for packet networks carrying elastic (greedy) traffic, i.e. the traffic streams that can use up, perhaps within certain assumed bounds, any bandwidth that is assigned to them. We give effective, simple and explicit solutions to the introduced optimisation tasks based on the dual optimisation theory, and illustrate them with numerical examples. The explicit solutions can guide a network operator how to proceed when introducing PF into his network.
Fitting Optimal Piecewise Linear Functions Using Genetic Algorithms
Authors: Jennifer Pittman, C. A. Murthy
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (2000)

Constructing a model for data in ${\cal R}^{2}$ is a common problem in many scientific fields, including pattern recognition, computer vision, and applied mathematics. Often little is known about the process which generated the data or its statistical properties. For example, in fitting a piecewise linear model, the number of pieces, as well as the knot locations, may be unknown. Hence, the method used to build the statistical model should have few assumptions, yet, still provide a model that is optimal in some sense. Such methods can be designed through the use of genetic algorithms. In this paper, we examine the use of genetic algorithms to fit piecewise linear functions to data in ${\cal R}^{2}$. The number of pieces, the location of the knots, and the underlying distribution of the data are assumed to be unknown. We discuss existing methods which attempt to solve this problem and introduce a new method which employs genetic algorithms to optimize the number and location of the pieces. Experimental results are presented which demonstrate the performance of our method and compare it to the performance of several existing methods. We conclude that our method represents a valuable tool for fitting both robust and nonrobust piecewise linear functions.
Indexing Techniques for Queries on Nested Objects
Authors: E. Bertino, W. Kim
Venue: IEEE Transactions on Knowledge and Data Engineering (1989)

Three index organizations are introduced for use in the evaluation of a query in an object-oriented or nested relational database. Detailed models of the three indexes are developed. Using the models, the storage cost, retrieval cost, and update cost of these indexes are evaluated, and a number of observations are made about the use of these indexes for evaluating queries for object-oriented or nested relational databases. A comparison of the combined retrieval and update costs for the three indexes is also included. It is shown that the degree of reference sharing among objects for the various classes in the path influences both the retrieval and update costs.