ppxscal/embedding_network huggingface dataset:
APL and SAS in co-operation
Authors: E. Karjala
Venue: ACM SIGAPL APL Quote Quad (1987)

This paper describes two different menu-driven applications, in which APL software and the Statistical Analysis System (SAS) are used together. In one (TTK = The Statistical Database System) SAS is called during the execution of an APL application to produce color maps from the data retrieved and probably modified in an APL application. In the other (the ZT System) APL is called during the execution of a SAS application to handle complicated functions of the whole application. Some attention is also given to the effective FORTRAN-based input/output routines utilized in both of these applications.
Architecture and compiler tradeoffs for a long instruction wordprocessor
Authors: Robert Cohn, Thomas Gross, Monica Lam
Venue: ACM SIGARCH Computer Architecture News (1989)

A very long instruction word (VLIW) processor exploits parallelism by controlling multiple operations in a single instruction word. This paper describes the architecture and compiler tradeoffs in the design of iWarp, a VLIW single-chip microprocessor developed in a joint project with Intel Corp. The iWarp processor is capable of specifying up to nine operations in an instruction word and has a peak performance of 20 million floating-point operations and 20 million integer operations per second. An optimizing compiler has been constructed and used as a tool to evaluate the different architectural proposals in the development of iWarp. We present here the analysis and compiler optimizations for those architectural features that address two key issues in the design of a VLIW microprocessor: code density and a streamlined execution cycle. We support the results of our analysis with performance data for the Livermore Loops and a selection of programs from the LINPACK library.
Economic analysis of microcomputer hardware
Authors: Brian D. Lynch, H. Raghav Rao, Winston T. Lin
Venue: Communications of the ACM (1990)

Economic analysis of the hardware characteristics of the personal computer segment of the microcomputer market indicates that the variables that most affect cost are the bundle of attributes offered by the micros. Interestingly, certain technological characteristics found to be important explanatory variables for cost in larger computers were not found to be significant for micros.
ASSIGN: a qualitative approach to outside plant design engineering
Authors: Richard Farenci, Doreen Vorce, Elizabeth Hahn, Jeffrey Hogan, John S. Kaminski
Venue: Proceedings of the 2nd international conference on Industrial and engineering applications of artificial intelligence and expert systems - Volume 1 (1989)

Learning how to build a knowledge base that contains a representative set of modifications used to resolve unassignable orders.
Easily Testable Iterative Logic Arrays
Authors: Cheng-Wen Wu, Peter R. Cappello
Venue: IEEE Transactions on Computers (1990)

Iterative logic arrays (ILAs) are studied with respect to two testing problems. First, a variety of conditions is presented. Meeting these conditions guarantees an upper bound on the size of the test set for the ILA under consideration. Second, techniques for designing optimally testable ILAs are presented. The arrays treated are, in some cases, more general than those that have been reported by other researchers: they include multidimensional and inhomogeneous arrays. Octagonally connected arrays and bilateral arrays are also discussed. The results indicate that the characteristics of the individual cell functions (e.g. whether they are bijective) are a good guide to the test complexity of the overall array. Matrix multiplication, as an example, is shown to have several different optimally testable implementations. The results are useful for combinational and pipelined arrays and for certain systolic arrays.
A New Class of Fault-Tolerant Static Interconnection Networks
Authors: D. B. Skillicorn
Venue: IEEE Transactions on Computers (1988)

The authors present a new class of interconnection networks using combinatorial block designs. These networks are highly structured and have strong fault-tolerant properties. They also have a free parameter that allows tradeoffs to be made between performance and cost in a fairly continuous way.
High-Speed CAM-Based Architecture for a Prolog Machine (ASCA)
Authors: J. Naganuma, T. Ogura, S.-I. Yamada, T. Kimura
Venue: IEEE Transactions on Computers (1988)

A content addressable memory (CAM)-based machine architecture is proposed for a high-speed Prolog machine. This Prolog machine attempts to speed up the total Prolog execution performance by using a hierarchical pipelined scheme and a CAM-based backtracking scheme. The hierarchical pipelined scheme reduces the total number of Prolog execution steps to half of that using the conventional method. The CAM-based backtracking is efficiently and quickly achieved by using CAM's sophisticated garbage collection function, which eliminates the need for stacks and additional operation cycles. In this machine, all Prolog execution can be simply controlled by a semantic information 'inference depth' without any address handling by storing all working information, binding and control information, in CAMs. This machine attains a performance of 100 KLIPS (kilo logical inference per second) on the deterministic append program in the interpretive mode, and also attains high performance in the nondeterministic program.
Cube structures for multiprocessors
Authors: Krishnan Padmanabhan
Venue: Communications of the ACM (1990)

The exact structural relationship between the hypercube and multistage interconnection networks for multiprocessors is characterized here. By varying the node architecture, structures other than these two interconnection schemes can be derived.
Improvements of an incremental evaluation algorithm for ordered attribute grammars
Authors: D. Yeh, U. Kastens
Venue: ACM SIGPLAN Notices (1988)

Three improvements are suggested upon an incremental attribute evaluation algorithm proposed by the first author. The resulting algorithm allows multiple subtree replacement and cancels three auxiliary tables required by the previous version.
Trace Inference, Curvature Consistency, and Curve Detection
Authors: P. Parent, S. W. ucker
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1989)

An approach is described for curve inference that is based on curvature information. The inference procedure is divided into two stages: a trace inference stage, which is the subject of the present work, and a curve synthesis stage. It is shown that recovery of the trace of a curve requires estimating local models for the curve at the same time, and that tangent and curvature information are sufficient. These make it possible to specify powerful constraints between estimated tangents to a curve, in terms of a neighborhood relationship called cocircularity, and between curvature estimates, in terms of a curvature consistency relation. Because all curve information is quantized, special care must be taken to obtain accurate estimates of trace points, tangents, and curvatures. This issue is addressed specifically to the introduction of a smoothness constraint and a maximum curvature constraint. The procedure is applied to two types of images: artificial images designed to evaluate curvature and noise sensitivity, and natural images.
Applying a theory of graphical presentation to the graphic design of user interfaces
Authors: Jock Mackinlay
Venue: Proceedings of the 1st annual ACM SIGGRAPH symposium on User Interface Software (1988)

The increasing availability of computers with high-quality graphics and fonts has created an opportunity and an obligation for user interface designers. The opportunity is that designers can use graphical techniques to design more effective user interfaces. The obligation is that they must become experts at the design of graphical user interfaces. Current user interface toolkits provide very little design assistance. This paper describes a theory that supports automatic design of graphical presentations of relational information and shows how to extend it to support theory-driven design of graphical user interfaces. &ldquo;A picture worth a thousand words must first be a good picture&rdquo; [Bow68]
Topologies' - computational messaging for multicomputers
Authors: K. Schwan, W. Bo
Venue: Proceedings of the third conference on Hypercube concurrent computers and applications: Architecture, software, computer systems, and general issues - Volume 1 (1988)

The programming of a large-scale multicomputer that exhibits an interconnection structure known to the applications programmer (e.g. a hypercube or mesh) requires the explicit construction and use of complex communication structures for connecting the application's parallel tasks. Such structures are used for a wide variety of functions, including the exchange of data or control information relevant to the tasks' computations and/or communications required for task synchronization, message forwarding/filtering under program control, and others. Topologies is an operating system construct with which programmers may efficiently implement arbitrary communication graphs linking multiple tasks of a parallel program. In addition, with each topology may be associated user-defined services, which may perform computations for communications traversing the topology. For example, application-dependent services may compute global sums or minima for values being communicated among the tasks linked by a topology, and the operating system or programmer may use a topology's concatenation service in the implementation of monitoring, file storage, or virtual terminal services. Communication topologies are currently implemented as an extension of the Intel iPSC hypercube's operating system kernel and are used with several applications programs, including a large finite element analysis program used for metalforming applications (termed ALPID). Future extensions concern the restructuring of the operating system kernel to support services of different 'weights' and hardware support for the efficient execution of selected services in conjunction with message routing.
Microarchitecture modelling through ADL
Authors: E. S.T. Fernandes
Venue: Proceedings of the 21st annual workshop on Microprogramming and microarchitecture (1988)

ADL is an Architecture Description Language that has been developed to model computer architectures at different levels of detail, as for instance, at the microarchitecture level. Target architectures described in ADL are processed by the support system of the language which generates an interpreter program related to the description of the target machine. The interpreter reproduces the behavior of the architecture being modeled, including the interpretation of the target code. In addition to a brief review of the language and the implementation details of its support system, this paper also shows some methods to deal with target machine parallelism, and the modeling of two microprogrammable machines.
The Chain Pyramid: Hierarchical Contour Processing
Authors: P. Meer, C. A. Sher, A. Rosenfeld
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1990)

A novel hierarchical approach toward fast parallel processing of chain-codable contours is presented. The environment, called the chain pyramid, is similar to a regular nonoverlapping image pyramid structure. The artifacts of contour processing on pyramids are eliminated by a probabilistic allocation algorithm. Building of the chain pyramid is modular, and for different applications new algorithms can be incorporated. Two applications are described: smoothing of multiscale curves and gap bridging in fragmented data. The latter is also employed for the treatment of branch points in the input contours. A preprocessing module allowing the application of the chain pyramid to raw edge data is also described. The chain pyramid makes possible fast, O(log(image/sub -/size)), computation of contour representation in discrete scale-space.
A portable global optimizer and linker
Authors: M. E. Benitez, J. W. Davidson
Venue: ACM SIGPLAN Notices (1988)

To reduce complexity and simplify their implementation, most compilers are organized as a set of passes or phases. Each phase performs a particular piece of the compilation process. In an optimizing compiler, the assignment of function and order of application of the phases is a critical part of the design. A particularly difficult problem is the arrangement of the code generation and optimization phases so as to avoid phase ordering problems caused by the interaction of the phases. In this paper, we discuss the implementation of a compiler/linker that has been designed to avoid these problems. The key aspect of this design is that the synthesis phases of the compiler and the system linker share the same intermediate program representation. This results in two benefits. It permits the synthesis phases of the compiler to be performed in any order and repeatedly, thus eliminating potential phase ordering problems. Second, it permits code selection to be invoked at any point during the synthesis phases as well as at link time. The ability to perform code selection at link time presents many opportunities for additional optimizations. Measurements about the effectiveness of using this approach in a C compiler on two different machines are presented.
Distributed simulation using hierarchical rollback
Authors: R. L. Gimarco
Venue: Proceedings of the 21st conference on Winter simulation (1989)

As the complexity of computer and communication systems increases, it becomes increasingly difficult to construct and evaluate models of these systems which can be used to study their performance under varying conditions. A modeling technique which is once again gaining in popularity due to its generality and ability to represent systems in varying degrees of detail is discrete event simulation.Constructing a simulation model of a real or proposed system is well understood and many tools are available. The major problem which arises is model evaluation. Due to the complexity and level of detail in a simulation model, it may require an excessive amount of time and computer resources to perform the evaluation. There is an area of current research, though, which is addressing these performance problems: distributed simulation.Distributed simulation has the potential to reduce the often lengthy run-time required for complex discrete event simulation by using multiple, cooperating processors instead of a single processor for model execution. Also, the computer resource requirements can more easily be satisfied by spreading the demand across a set of processors rather than depending on a single processor to furnish the required resources.In this paper a new technique for distributed simulation called hierarchical rollback is presented. Hierarchical rollback employs multiple processors for the evaluation of a single simulation model. Synchronization and coordination of the processors is based on a unique checkpoint/rollback mechanism. It will be shown how hierarchical rollback can be used to execute a hierarchical simulation model on a distributed set of processors.
Dynamic program slicing
Authors: Hiralal Agrawal, Joseph R. Horgan
Venue: Proceedings of the ACM SIGPLAN 1990 conference on Programming language design and implementation (1990)

Program slices are useful in debugging, testing, maintenance, and understanding of programs. The conventional notion of a program slice, the static slice, is the set of all statements that might affect the value of a given variable occurrence. In this paper, we investigate the concept of the dynamic slice consisting of all statements that actually affect the value of a variable occurrence for a given program input. The sensitivity of dynamic slicing to particular program inputs makes it more useful in program debugging and testing than static slicing. Several approaches for computing dynamic slices are examined. The notion of a Dynamic Dependence Graph and its use in computing dynamic slices is discussed. The Dynamic Dependence Graph may be unbounded in length; therefore, we introduce the economical concept of a Reduced Dynamic Dependence Graph, which is proportional in size to the number of dynamic slices arising during the program execution.
Co-operation of a Macintosh laboratory for Rensselaer's technical writing program
Authors: Sharon Roy
Venue: Proceedings of the 16th annual ACM SIGUCCS Conference on User Services (1988)

Rensselaer Polytechnic Institute's Macintosh Laboratory is a partnership between Information Technology Services and the Department of Language Literature and Communication that attempts to meet a variety of instructional needs. One of the great promises of microcomputers has been to ease the integration of computing into the curriculum by allowing individual departments to design their own computing environments. Unfortunately, that promise has eluded many departments because their programs and their budgets are not large enough to justify the cost of microcomputer laboratories solely for their use. When a department does manage to obtain a private facility, they often have neither the interest nor the staff to keep it open for general campus use. Here at Rensselaer, most faculty who want to use microcomputers in their teaching schedule time in the public microcomputer sites operated by ITS and scheduled through the Registrar's Office. The Registrar's Office has identified a growing demand for these facilities, but the special requests we receive indicate that these general purpose labs are often inadequate for special subject-area needs. An equipment grant from Apple Computer provided an opportunity to serve the specialized needs of the Department of Language, Literature and Communication as well as the general campus need for microcomputer access though a jointly operated Macintosh Laboratory. This paper describes the configuration of the lab and its local area network and some of the problems we encountered in setting it up. But the focus is on the way the lab is actually used in the instructional program of LL C and some of the administrative problems and successes we have encountered in our cooperative venture.
Performance analysis of the hypercube line switch
Authors: K. Bratbergsengen
Venue: Proceedings of the third conference on Hypercube concurrent computers and applications: Architecture, software, computer systems, and general issues - Volume 1 (1988)

Our first effort went into designing and analyzing the hypercube network as a message passing switch. We aimed at making a VLSI chips, one for each node, which should store and forward the messages. Message passing have some negative effects: Message delays are both unpredictable and significant, nodes have to be able to store messages, thereby increasing chip size, and finally it was discovered during simulation tests that deadlocks occurred rather frequently. Later a remedy for deadlock was found, but the other negative indicators are still valid. The result: we abandoned the message passing method and turned to line switching. Still there should be one chip in each node. The hypercube line switching node has one communication path to each neighbor (D lines in a D dimensional cube) and two paths to the node computer. The chip should be able to participate in decentralized routing through the cube, and when a connection is established: hold a path through the node. An outline of the node functions will be given. A line switching hypercube network will have enormous data transmission capacity. In a D dimensional cube with N=2D nodes, at most N channels can be active at the same time. (Remember that each node computer has both an input port and an output port). 10 MB/sec data transfer rate on each channel is well within reach. The critical operation is to establish a path through the hypercube. Set up time varies with network size and load, clock frequency and actual path through the network. With the same clock frequency as already mentioned, the normal set up time under light load conditions is from 1 to 3 microseconds. An analysis of the path setup process has been carried out. The focus has been on the probability of being able to establish a path under a given load condition. The load is defined as the number of established (active) channels over N. Two approximate analytical models are developed and compared with results from a simulation model. All models give the same picture, and it is safe to say that for loads less or equal to 50% the probability of getting through is very high, almost 1.0 for larger cubes, i.e. D > 8. For loads larger than 80% almost all requests are denied.
Blending algebraic surfaces
Authors: J. Warren
Venue: ACM Transactions on Graphics (TOG) (1989)

A new definition of geometric continuity for implicitly defined surfaces is introduced. Under this definition, it is shown that algebraic blending surfaces (surfaces that smoothly join two or more surfaces) have a very specific form. In particular, any polynomial whose zero set blends the zero sets of several other polynomials is always expressible as a simple combination of these polynomials. Using this result, new methods for blending several algebraic surfaces simultaneously are derived.
Efficient aggregation of multiple PLs in distributed memory parallel simulations
Authors: D. M. Nicol, C. C. Michael, P. Inouye
Venue: Proceedings of the 21st conference on Winter simulation (1989)

The state of research in parallel simulation now demands that we experiment with a multitude of simulation models. It is evident that large-scale simulations involving many interacting logical processes should be a focal point of such experimentation, as large-scale simulations will benefit the most from parallelism. This realization raises a number of issues. Large-scale parallel simulations must aggregate many logical processes onto each machine in a distributed memory architecture. This fact creates internal management problems--how does one synchronize in such a setting? How does one efficiently find and manage the simulation workload? If we are to experiment with multiple models, what underlying functions can we extract to program once, and use many times? This paper describes YAWNS, Yet Another Windowing Network Simulator, for dealing with these problems.
The synthesis and rendering of eroded fractal terrains
Authors: F. K. Musgrave, C. E. Kolb, R. S. Mace
Venue: Proceedings of the 16th annual conference on Computer graphics and interactive techniques (1989)

In standard fractal terrain models based on fractional Brownian motion the statistical character of the surface is, by design, the same everywhere. A new approach to the synthesis of fractal terrain height fields is presented which, in contrast to previous techniques, features locally independent control of the frequencies composing the surface, and thus local control of fractal dimension and other statistical characteristics. The new technique, termed noise synthesis, is intermediate in difficulty of implementation, between simple stochastic subdivision and Fourier filtering or generalized stochastic subdivision, and does not suffer the drawbacks of creases or periodicity. Varying the local crossover scale of fractal character or the fractal dimension with altitude or other functions yields more realistic first approximations to eroded landscapes. A simple physical erosion model is then suggested which simulates hydraulic and thermal erosion processes to create gloabl stream/valley networks and talus slopes. Finally, an efficient ray tracing algorithm for general height fields, of which most fractal terrains are a subset, is presented.