ppxscal/embedding_network huggingface dataset:
SerialExpress-A High-Performance Workstation Interconnect
Authors: David V. James, David B. Gustavson, Balint Fleischer
Venue: IEEE Micro (1998)

SerialExpress refers to the draft standard developed by the IEEE P2100 working group. This article focuses on the technical aspects of the draft; future articles will address SerialExpress implementation technologies and applciations. SerialExpress provides buslike services (as defined in IEEE 1212-1991) but uses longer distance point-to-point links. Concepts developed in IEEE 1394-1995 Serial bus and IEEE 1596-1992 Scalable Coherent Interface (SCI) are leveraged and extended. The objective of this working group is to develop a low-cost, technology-independcent, high-bandwidth, low-latency, distance-insensitive scalable protocol for system areas network (SAN) applications. Within this environment, buslike read and write transactions provide an efficient mechanism for transferring data and control information between processor and I/O nodes. The bandwidth, distance, and latency objectives mandated the concurrent transmission of small (64 data-byte packets and avoiding the arbitration delay constraints of a broadcast bus protocol. This solution scales over a wide range of technologies.
Performance Considerations of Shared Virtual Memory Machines
Authors: Xian-He Sun, Jianping Zhu
Venue: IEEE Transactions on Parallel and Distributed Systems (1995)

Generalized speedup is defined as parallel speed over sequential speed. In this paper the generalized speedup and its relation with other existing performance metrics, such as traditional speedup, efficiency, scalability, etc., are carefully studied. In terms of the introduced asymptotic speed, we show that the difference between the generalized speedup and the traditional speedup lies in the definition of the efficiency of uniprocessor processing, which is a very important issue in shared virtual memory machines. A scientific application has been implemented on a KSR-1 parallel computer. Experimental and theoretical results show that the generalized speedup is distinct from the traditional speedup and provides a more reasonable measurement. In the study of different speedups, an interesting relation between fixed-time and memory-bounded speedup is revealed. Various causes of superlinear speedup are also presented.
Business Object Component Architecture
Authors: Tom Digre
Venue: IEEE Software (1998)

The Common Business Object Framework aims at coming up with a set of system-level abstractions and interoperability standards to simplify and standardize business systems development. The author asserts that Boca provides a solution to the challenge of segregating core business information from the technological specifics of its home system while allowing different applications to exchange data across the enterprise.
A simplified EM algorithm for detection of CPM signals in a fading multipath channel
Authors: Linda M. Zeger, Hisashi Kobayashi
Venue: Wireless Networks (2002)

Application of the EM (Expectation-Maximization) algorithm to sequence estimation in an unknown channel can in principle produce MLSE (maximum likelihood sequence estimates) that are not dependent on a particular channel estimate. The Expectation step of this algorithm cannot be directly performed for continuous phase modulated (CPM) signals transmitted in a time varying multipath channel. We therefore derive a simplification of the EM algorithm for CPM signals in this channel. Simulations applied to the Global System for Mobile Communications (GSM) show that the simplified EM algorithm significantly decreases the amount of training data needed for the channel model considered, and removes the majority of the bit errors that are due to imperfect knowledge of the channel.
Test Synthesis with Alternative Graphs
Authors: Raimund Ubar
Venue: IEEE Design Test (1996)

A new, generalized approach on the basis of alternative graphs (AG) to test synthesis and analysis for digital systems is proposed. AGs permit an efficient uniform model for describing the structure, functions, as well faults in a wide class of digital circuits at different representation levels. This model also supports a wide class of test design tasks--test generation, two- or multivalued simulation, test quality analysis, statistical fault grading, testability analysis, etc. Unlike the known methods, the proposed AG approach allows the use of a single uniform model library for solving these tasks.
Multilevel Extendible Hashing: A File Structure for Very Large Databases
Authors: D. H. C. Du, S. -R. Tong
Venue: IEEE Transactions on Knowledge and Data Engineering (1991)

A dynamic hashing scheme based on extendible hashing is proposed whose directory can grow into a multilevel directory. The scheme is compared to the extendible hashing and the extendible hashing tree schemes. The simulation results reveal that the proposed scheme is superior than the other two with respect to directory space utilization, especially for files with nonuniform record distribution. This scheme can be easily extended to multikey file systems and also has good performance.
An Efficient Video-on-Demand Model
Authors: William E. Wright
Venue: Computer (2001)

The author proposes a design for an efficient video-on-demand system that uses a practical, technologically sophisticated model to serve the home movie-viewing needs of a wide audience, including meeting peak demand for popular, newly released films. In this VoD model, each customer's VoD terminal connects to a television set and the network. Using the network, the customer contacts the VoD provider to request a movie at a specific time. The movie plays without interruption unless the user decides to pause it. The VoD network's bandwidth permits data transfer at a rate equal to or exceeding the rate at which the TV consumes the data. The terminal buffer's large capacity permits uninterrupted movie playing. The system includes the scheduling algorithm, buffer policy, file-storage lay-out, and a feedback mechanism for denying new requests when the system becomes nearly saturated. OEID--one-way elevator with interleaving and delayed start--includes a one-way elevator algorithm for each disk for each round and provides double buffering for each video stream. Other features include interleaved movie file storage and transmission of a warning message when the terminal nears starvation. Interleaving with delayed start offers the optimal strategy for storing movie files on disks because it permits maximum overlap of the read operations--seek, latency, and transfer-- over all disks, whereas striping overlaps only the transfer component. Also, OEID permits an almost perfectly balanced workload over all disks, on every round, regardless of movie popularity.
Facilitating system-of-systems evolution with architecture support
Authors: Pin Chen, Jun Han
Venue: Proceedings of the 4th International Workshop on Principles of Software Evolution (2001)

The evolution of system-of-systems (SOS) is an emerging challenge and requires systematic architecture capabilities and support. This paper discusses the features of SOS evolution and introduces a key concept, Architecture Evolution Environment, to facilitate the evolution. We argue that an architecture solution for specific evolution requirements can be reached only when its evolution environment is addressed.
Consistency in Dataflow Graphs
Authors: E. A. Lee
Venue: IEEE Transactions on Parallel and Distributed Systems (1991)

Analytical properties of programming languages with dataflow graph semantics arediscussed. It is shown that one of the most serious problems with these languages is thatsubtle inconsistencies between parts of the dataflow graph can be inadvertently created.These inconsistencies can lead to deadlock, or in the case of nonterminating programs, tounbounded memory requirements. Consistency is defined to mean that the same numberof tokens is consumed as produced on any arc, in the long run. A token-flow model isdeveloped for testing for inconsistency. The method is a generalization of consistencychecks for synchronous dataflow (SDF) graphs. The token-flow model is compared tosimilar tests applied to hybrid dynamical systems. It is argued that dataflow semanticsmake steady-state analysis possible, leading to a simpler method in most cases.
A Parallel Neural Processor for Real-Time Applications
Authors: Giovanni Danese, Francesco Leporati, Stefano Ramat
Venue: IEEE Micro (2002)

Training and testing artificial neural networks can be challenging and time-consuming. experiments with tworeal-time applications compared three approaches for implementing a multilayer perceptron neural network. In both applications, the special-purpose processor performed best.
Optimal Allocation for Partially Replicated Database Systems on Ring Networks
Authors: A. B. Stephens, Y. Yesha, K. Humenik
Venue: IEEE Transactions on Knowledge and Data Engineering (1994)

Considers a distributed database with partial replication of data objects located on a ring network. Certain placements of replicated objects are shown to optimize the probability of read-only success and the probability of write-only success. We also obtain optimal placements for k-terminal reliability and expected minimal path length for read-only and write-only operations.
A New \mathcal{NP}-Complete Problem and Public-Key Identification
Authors: David Pointcheval, Guillaume Poupard
Venue: Designs, Codes and Cryptography (2003)

The appearance of the theory of zero-knowledge, presented by Goldwasser, Micali and Rackoff in 1985, opened a way to secure identification schemes. The first application was the famous Fiat-Shamir scheme based on the problem of modular square roots extraction. In the following years, many other schemes have been proposed, some Fiat-Shamir extensions but also new discrete logarithm based schemes. Therefore, all of them were based on problems from number theory. Their main common drawback is high computational load because of arithmetical operations modulo large integers. Implementation on low-cost smart cards was made difficult and inefficient.With the Permuted Kernels Problem (PKP), Shamir proposed the first efficient scheme allowing for an implementation on such low-cost smart cards, but very few others have afterwards been suggested.In this paper, we present an efficient identification scheme based on a combinatorial \mathcal{NP}-complete problem: the Permuted Perceptrons Problem (PPP). This problem seems hard enough to be unsolvable even with very small parameters, and some recent cryptanalysis studies confirm that position. Furthermore, it admits efficient zero-knowledge proofs of knowledge and so it is well-suited for cryptographic purposes. An actual implementation completes the optimistic opinion about efficiency and practicability on low-cost smart cards, and namely with less than 2KB of EEPROM and just 100 Bytes of RAM and 6.4 KB of communication.
Worst case burstiness increase due to FIFO multiplexing
Authors: Vicent Chlovi, Juan Echagüe, Jean-Yves Le Boudec
Venue: Performance Evaluation (2002)

We consider a FIFO multiplexer fed by flows that are individually constrained by arrival curves, and look for the best possible arrival curve for every output flow. This problem arises in scenarios where aggregate multiplexing is performed, such as differentiated services or front ends to optical switches. We obtain an exact result for a fluid model and for piecewise linear concave arrival curves, which are common in practice and correspond to combinations of leaky buckets.
Delimiting the range of effectiveness of scalable on-demand streaming
Authors: Haonan Tan, Derek L. Eager, Mary K. Vernon
Venue: Performance Evaluation (2002)

Previous analyses of scalable streaming protocols for delivery of stored multimedia have largely focused on how the server bandwidth required for full-file delivery scales as the client request rate increases or as the start-up delay is decreased. This previous work leaves unanswered three questions that can substantively impact the desirability of using these protocols in some application domains, namely: (1) Are simpler scalable download protocols preferable to scalable streaming protocols in contexts where substantial start-up delays can be tolerated? (2) If client requests are for (perhaps arbitrary) intervals of the media file rather than the full-file, are there conditions under which streaming is not scalable (i.e., no streaming protocol can achieve sub-linear scaling of required server bandwidth with request rate)? (3) For systems delivering a large collection of objects with a heavy-tailed distribution of file popularity, can scalable streaming substantially reduce the total server bandwidth requirement, or will this requirement be largely dominated by the required bandwidth for relatively cold objects?This paper addresses these questions primarily through the development of tight lower bounds on required server bandwidth, under the assumption of Poisson, independent client requests. Implications for other arrival processes are also discussed. Previous work and results presented in this paper suggest that these bounds can be approached by implementable policies. With respect to the first question, the results show that scalable streaming protocols require significantly lower server bandwidth in comparison to download protocols for start-up delays up to a large fraction of the media playback duration. For the second question, we find that in the worst-case interval access model, the minimum required server bandwidth, assuming immediate service to each client, scales as the square root of the request rate. Finally, for the third question, we show that scalable streaming can provide a factor of log K improvement in the total minimum required server bandwidth for immediate service, as the number of objects K is scaled, for systems with fixed minimum object request popularity.
The Smart Way to Buy Information Technology: How to Maximize Value and Avoid Costly Pitfalls
Authors: Brad L. Peterson, Diane M. Carco
Venue:  (1998)

:This one-of-a-kind book helps companies make the most of their IT acquisitions budget by avoiding bad technology investments and harmful vendor relationships.
Misconceptions About Real-Time Databases
Authors: John A. Stankovic, Sang Hyuk Son, Jorgen Hansson
Venue: Computer (1999)

Increasingly, computer systems--even general-purpose systems--are requiring real-time support, so it's not surprising to hear more about real-time databases.Unfortunately, there are many misconceptions about the real-time aspects of databases. Mainstream database users who don't have any experience with real-time systems mistakenly think they are synonymous with speed. Others argue that conventional database technology can be used in real-time applications.To help bring order to the current state of confusion, the authors review nine common misconceptions about real-time databases. They also describe key research areas that need to be addressed to encourage increased activity in this challenging area.
Survival of the Fastest: Improving Service Velocity
Authors: Neil C. Olsen
Venue: IEEE Software (1995)

The literature of software engineering rarely focuses on time as the dominant factor in software projects. But service velocity -- the rate at which software can be deployed to market or customized -- has a more significant influence on project decisions than quality, predictability, risk, cost, or productivity. Even in the noncommercial software market, where profit considerations may not dominate, the rate at which work can be serviced affects all other measurable elements more profoundly than any other factor.I have been a software engineer for more than 20 years, and schedules, market windows, and release dates have dominated my work process, my technical designs, and my life. This is generally true of my colleagues as well. As an engineer, I also feel the need to codify my observations and subjective experience with mathematical models so that I can understand my predicament, not merely testify to it.In this article, I make a case for improving the rate of development and deployment of software applications from the perspective of a business sponsor. My goals are to increase profit, beat the competition, establish a reputation, build market share, and increase shareholder value. My challenge is to select the best software technologies, staff, information-engineering processes, and organizational structures to achieve rapid deployment and satisfy customer demands.
Genetic Programming Experiments with Standard and Homologous Crossover Methods
Authors: James V. Hansen
Venue: Genetic Programming and Evolvable Machines (2003)

While successful applications have been reported using standard GP crossover, limitations of this approach have been identified by several investigators. Among the most compelling alternatives to standard GP crossover are those that use some form of homologous crossover, where code segments that are exchanged are structurally or syntactically aligned in order to preserve context and worth. This paper reports the results of an empirical comparison of GP using standard crossover methods with GP using homologous crossover methods. Ten problems are tested, five each of pattern recognition and regression.Results suggest that in terms of generalization accuracy, homologous crossover does generate consistently better performance. In addition, there is a consistently lower fraction of introns that are generated in the solution code.
Analysis and optimisation of the HIPERLAN Channel Access Contention Scheme
Authors: S. Chevrel, A. H. Aghvami, H.-Y. Lach, L. Taylor
Venue: Wireless Personal Communications: An International Journal (1997)

This paper analyses the HIPERLAN channel access mechanism. Both a purely mathematical and a simulation model are built in order to evaluate the two successive phases of the contention scheme. Several optimisations, based on the choice of parametric values, are proposed, evaluated and compared.
Experience in Validation of PowerPCTM Microprocessor Embedded Arrays
Authors: Li-C. Wang, Magdy S. Abadir
Venue: Journal of Electronic Testing: Theory and Applications (1999)

Design validation for embedded arrays remains as a challenging problem in today&lsquo;s microprocessor design environment. Although several methods for validating embedded arrays have been proposed, not much has been done to characterize the strengths and weaknesses of these methods. This paper provides a comprehensive study of various design validation approaches adopted at the Somerset PowerPC Design Center in the past, including methods from both formal verification and test generation. Effectiveness of these approaches will be measured based on automatic design error injection and simulation at both gate and transistor levels. Experience of using different validation approaches on recent PowerPC microprocessor arrays will be analyzed and discussed.
On finite weakly {s, t}-semiaffine linear spaces
Authors: Vito Napolitano
Venue: Discrete Mathematics (2002)

In this note finite weakly {s,t}-semiaffine linear spaces are studied. If there is a good point of degree n + 1 then those with different point degree are classified. In the other cases some classes of them are characterized.
Reliability Testing of Rule-Based Systems
Authors: Alberto Avritzer, Johannes P. Ros, Elaine J. Weyuker
Venue: IEEE Software (1996)

Rule-based software systems are becoming more common in industrial settings, particularly to monitor and control large, real-time systems. The authors describe an algorithm for reliability testing of rule-based systems and their experience using it to test an industrial network surveillance system.
Parallel Distributed-Time Logic Simulation
Authors: Larry Soule, Anoop Gupta
Venue: IEEE Design Test (1989)

The Chandy-Misra algorithm offers more parallelism than the standard event-driven algorithm for digital logic simulation. With suitable enhancements, the Chandy-Misra algorithm also offers significantly better parallel performance. The authors present methods to optimize the algorithm using information about the large number of global synchronization points, called deadlocks, that limit performance. They classify deadlocks and describe them in terms of circuit structure. The proposed methods that use domain-specific knowledge to avoid deadlocks and present a way to reduce greatly the time it takes to resolve a deadlock. For one benchmark circuit, the authors eliminated all deadlocks using their techniques and increased the average number of logic elements available for concurrent execution from 45 to 160. Simulation results for a 60-processor machine show that the Chandy-Misra algorithm outperforms the event-driven algorithm by a factor of 2 to 15.
Designing an Alpha Microprocessor
Authors: Matt Reilly
Venue: Computer (1999)

Processor design teams at Digital and now Compaq Computer Corp. have been designing and building micro-processors for about 20 years. For the past 10 years, they have been designing Alpha processors with the goal of maintaining industry-leading performance during each generation. Over time, the teams have developed a process to support this goal. Defining and designing a high-performance processor is high adventure in computer engineering. Nevertheless, this journey into new technologies and the unknown has a well-defined path. The author, a computer architect, shares the process the Alpha design teams use to develop their processors. From early product definition to delivery of the design (tape out) and debug, the article gives an insider's view of the steps in building a microprocessor. It also gives a glimpse of what it's like to work on such a project. The author sees the most striking and defining characteristic of the Alpha design team as its sense of a shared culture. The design processes are encoded, more often than not, in a set of rituals rather than a set of documents. The process is passed on from the more experienced engineers to those at the start of their careers. This cultural memory is embodied in the group as a whole.
Formal SDOs: They're Still Alive
Authors: Gary S. Robinson
Venue: IEEE Micro (2000)

I recently changed companies and with that move I changed my standards focus. I now attend standards groups that work on SCSI, Fibre Channel, Ethernet, and the like. Ethernet, as IEEE P802, was started in February of 1980, and SCSI is about the same age. What's interesting is that after all my years away from these groups they're still going strong and are still very valuable (even though I wasn't there). The last IEEE-P802 meeting had over 800 attendees. The ACM Portal is published by the Association for Computing Machinery. Copyright © 2010 ACM, Inc. Terms of Usage Privacy Policy Code of Ethics Contact Us Useful downloads: Adobe Acrobat QuickTime Windows Media Player Real Player
Self-Routing Technique in Perfect-Shuffle Networks Using Control Tags
Authors: S. -T. Huang, S. K. Tripathi
Venue: IEEE Transactions on Computers (1988)

The self-routing technique using control tags on multiple-pass perfect-shuffle networks is generalized. In particular, they show that bit-permute-complement permutations can be realized and unscrambled in (2n-1) passes or less, where n=log/sub 2/N, N being the number of terminals on either side. They also show that most of the frequently used permutations are in the intersection of omega-realizing and inverse-omega-realizing sets and can be realized and unscrambled in n passes.