ppxscal/embedding_network huggingface dataset:
Scoped hybrid automatic repeat reQuest with forward error correction (SHARQFEC)
Authors: Roger G. Kermode
Venue: ACM SIGCOMM Computer Communication Review (1998)

Reliable multicast protocols scale only as well as their ability to localize traffic. This is true for repair requests, repairs, and the session traffic that enables receivers to suppress extraneous requests and repairs. We propose a new reliable multicast traffic localization technique called Scoped Hybrid Automatic Repeat reQuest with Forward Error Correction (SHARQFEC). SHARQFEC operates in an end-to-end fashion and localizes traffic using a hierarchy of administratively scoped regions. Session traffic is further reduced through the use of a novel method for indirectly determining the distances between session members. For large sessions, this mechanism reduces the amount of session traffic by several orders of magnitude over non-scoped protocols such as Scalable Reliable Multicast (SRM). Forward Error Correction is selectively added to regions which are experiencing greater loss, thereby reducing the volume of repair traffic and recovery times. Receivers request additional repairs as necessary. Simulations show that SHARQFEC out performs both SRM and non-scoped hybrid Automatic Repeat reQuest / Forward Error Correction protocols. Assuming the widespread deployment of administrative scoping, SHARQFEC could conceivably provide scalable reliable delivery to tens of millions of receivers without huge increases in network bandwidth.
Efficient Algorithms for Interface Timing Verification
Authors: Ti-Yen Yen, Alex Ishii, Al Casavant, Wayne Wolf
Venue: Formal Methods in System Design (1998)

This paper presents algorithms for computing separations between events that are constrained to obey prespecified relationships in their relative time of occurrence. The algorithms are useful for interface timing verification, where event separations are checked against timing requirements. The first algorithm computes separations when only linear and max constraints exist. The algorithm must converge to correct maximum separation values in a finite number of steps, or report an inconsistence of the constraints, irrespective of the existence of infinite constraint bounds or infinite event separations. It is conjectured to run in O(V E + V^2 log V) time, where V is the number of events, and E is the number of relationships between them. The other algorithms extend the first, and compute event separations in the NP-complete version of the problem where min constraints exist. Experiments demonstrate the algorithms are efficient in practice.
The Game of Life with Ada tasks
Authors: Gertrude Levine
Venue: ACM SIGAda Ada Letters (1997)

The Game of Life is a popular programming project, both in computer science courses and on the World Wide Web. It is commonly implemented with a bounded array of values representing the cells of life. This project provides an appealing visual representation of cells living or dying over repeated generations.An Ada implementation using tasks allows a number of interesting features. State information can be retained between calls. A generic declaration defines a conceptually unbounded grid, which a distributed implementation with tasks can potentially implement. Tasking communication provides an exercise in both inter-cell communication and in deadlock prevention. Lastly, the independence of cell communication can allow for relaxing the synchronization of cell generations.
Embedding of Generalized Fibonacci Cubes in Hypercubes with Faulty Nodes
Authors: Feng-Shr Jiang, Shi-Jinn Horng, Tzong-Wann Kao
Venue: IEEE Transactions on Parallel and Distributed Systems (1997)

The generalized Fibonacci cubes (abbreviated to GFCs) [4] were recently proposed as a class of interconnection topologies, which cover a spectrum ranging from regular graphs such as the hypercube to semiregular graphs such as the second-order Fibonacci cube in [1]. It has been shown that the kth order GFC of dimension n + k is equivalent to an n-cube for 0 ¿n
Mismatch Characterization of Submicron MOS Transistors
Authors: J. Bastos, M. Steyaert, A. Pergoot, W. Sansen
Venue: Analog Integrated Circuits and Signal Processing (1997)

The characterization of transistor mismatch in a standard 0.7 &micro;m CMOS technology is presented. A new method for matching parameter extraction has been used. Mismatch parameters based on measurements on 10000 nMOS and 10000 pMOS transistors have been extracted. It is observed that the threshold voltage mismatch linear dependency on the inverse of the square root of the effective channel area no longer holds for transistors of 0.7 &micro;m channel length. An extended model based on the physical causes of threshold voltage mismatch is proposed. Contrary to the established theory, it is observed that transistors with channel length below 1 &micro;m have less current mismatch than what is predicted by a linear relationship with the channel area.
Specialization of lazy functional logic programs
Authors: M. Alpuente, M. Falaschi, P. Julián, G. Vidal
Venue: Proceedings of the 1997 ACM SIGPLAN symposium on Partial evaluation and semantics-based program manipulation (1997)

Partial evaluation is a method for program specialization based on fold/unfold transformations [8, 25]. Partial evaluation of pure functional programs uses mainly static values of given data to specialize the program [15, 44]. In logic programming, the so-called static/dynamic distinction is hardly present, whereas considerations of determinacy and choice points are far more important for control [12]. We discuss these issues in the context of a (lazy) functional logic language. We formalize a two-phase specialization method for a non-strict, first order, integrated language which makes use of lazy narrowing to specialize the program w.r. t. a goal. The basic algorithm (first phase) is formalized as an instance of the framework for the partial evaluation of functional logic programs of [2, 3], using lazy narrowing. However, the results inherited by [2, 3] mainly regard the termination of the PE method, while the (strong) soundness and completeness results must be restated for the lazy strategy. A post-processing renaming scheme (second phase) is necessary which we describe and illustrate on the well-known matching example. This phase is essential also for other non-lazy narrowing strategies, like innermost narrowing, and our method can be easily extended to these strategies. We show that our method preserves the lazy narrowing semantics and that the inclusion of simplification steps in narrowing derivations can improve control during specialization.
A New Metric for Grey-Scale Image Comparison
Authors: Dale L. Wilson, Adrian J. Baddeley, Robyn A. Owens
Venue: International Journal of Computer Vision (1997)

Error measures can be used to numerically assess the differences between two images. Much work has been done on binary error measures, but little on objective metrics for grey-scale images. In our discussion here we introduce a new grey-scale measure, &Delta;_g, aiming to improve upon the most common grey-scale error measure, the root-mean-square error. Our new measure is an extension of the authors&lsquo; recently developed binary error measure, &Delta;_b, not only in structure, but also having both a theoretical and intuitive basis. We consider the similarities between &Delta;_b and &Delta;_g when tested in practice on binary images, and present results comparing &Delta;_g to the root-mean-squared error and the Sobolev norm for various binary and grey-scale images. There are no previous examples where the last of these measures, the Sobolev norm, has been implemented for this purpose.
Simulation and animation of the operation of a fast food restaurant
Authors: Kambiz Farahmand, Alejandro Francisco Garza Martinez
Venue: Proceedings of the 28th conference on Winter simulation (1996)

A model was developed for the Simulation and Animation of the Drive-Thru (DT) and the lobby sections of a fast food restaurant. A discrete, non continuous, parallel simulation of the operation using animation in the Witness environment has made it possible to utilize real time data or forecasted data to optimize scheduling and maximize operation efficiency. Performance measures such as the number of customers balking from the system, the average time each customer spends in the system, the average waiting time for the customers, the average queue length before and after placing an order, the average time to fill an order and even the average utilization of each employee could be determined. The results could serve as basis to provide recommendations on how to improve efficiency and throughput for the fastest growing industry and the largest employer in the US. The modeling methodology and the tracking mechanism could also prove useful for the manufacturing or other service industries employing similar queuing techniques.
Prototyping of the receiver unit for a broadband access network
Authors: A. Hein, J. Dalcolmo, P. Le Corre, R. Lauwereins, M. Adé
Venue: Proceedings of the 10th international symposium on System synthesis (1997)

To exploit the potential of two-way communication on CATV networks for advanced interactive telecommunication applications like video-on-demand, a high speed modem for up-stream communication is currently under development. We are using the rapid prototyping tool GRAPE to evaluate the digital receiver part of the modem which is described in detail in this paper. The sampling rates achieved for a modem on multiple DSP processors are reported.
Temporal aggregation in active database rules
Authors: Iakovos Motakis, Carlo Zaniolo
Venue: Proceedings of the 1997 ACM SIGMOD international conference on Management of data (1997)

An important feature of many advanced active database prototypes is support for rules triggered by complex patterns of events. Their composite event languages provide powerful primitives for event-based temporal reasoning. In fact, with one important exception, their expressive power matches and surpasses that of sophisticated languages offered by Time Series Management Systems (TSMS), which have been extensively used for temporal data analysis and knowledge discovery. This exception pertains to temporal aggregation, for which, current active database systems offer only minimal support, if any. In this paper, we introduce the language TREPL, which addresses this problem. The TREPL prototype, under development at UCLA, offers primitives for temporal aggregation that exceed the capabilities of state-of-the-art composite event languages, and are comparable to those of TSMS languages. TREPL also demonstrates a rigorous and general approach to the definition of composite event language semantics. The meaning of a TREPL rule is formally defined by mapping it into a set of Datalog1S rules, whose logic-based semantics characterizes the behavior of the original rule. This approach handles naturally temporal aggregates, including user-defined ones, and is also applicable to other composite event languages, such as ODE, Snoop and SAMOS.
Building program optimizers with rewriting strategies
Authors: Eelco Visser, Zine-el-Abidine Benaissa, Andrew Tolmach
Venue: ACM SIGPLAN Notices (1999)

We describe a language for defining term rewriting strategies, and its application to the production of program optimizers. Valid transformations on program terms can be described by a set of rewrite rules; rewriting strategies are used to describe when and how the various rules should be applied in order to obtain the desired optimization effects. Separating rules from strategies in this fashion makes it easier to reason about the behavior of the optimizer as a whole, compared to traditional monolithic optimizer implementations. We illustrate the expressiveness of our language by using it to describe a simple optimizer for an ML-like intermediate representation.The basic strategy language uses operators such as sequential composition, choice, and recursion to build transformers from a set of labeled unconditional rewrite rules. We also define an extended language in which the side-conditions and contextual rules that arise in realistic optimizer specifications can themselves be expressed as strategy-driven rewrites. We show that the features of the basic and extended languages can be expressed by breaking down the rewrite rules into their primitive building blocks, namely matching and building terms in variable binding environments. This gives us a low-level core language which has a clear semantics, can be implemented straightforwardly and can itself be optimized. The current implementation generates C code from a strategy specification.
State saving for interactive optimistic simulation
Authors: Steve Franks, Fabian Gomes, Brian Unger, John Cleary
Venue: Proceedings of the eleventh workshop on Parallel and distributed simulation (1997)

Time Warp's optimistic scheduling requires the maintenance of simulation state history to support rollback in the event of causality violations. State history, and the ability to rollback the simulation, can provide unique functionality for human-in-the-loop simulation environments. This paper investigates the use of Time Warp to output valid simulation state in a near real-time manner, re-execute portions of the simulation, and interactively probe simulation values to ascertain underlying causes of transient behavior.A shared-memory, multi-threaded interactive simulation architecture is presented and the additional state saving requirements imposed by interactivity are examined. The shortcomings of existing state saving schemes lead us to propose Multiplexed State Saving (MSS). By interleaving checkpointing and incremental state logs MSS provides bounded rollback costs and asynchronous access to prior simulation state. The interaction algorithms and MSS form a scalable, bounded cost component suitable for use in a real-time interactive Time Warp system.
On high-bandwidth data cache design for multi-issue processors
Authors: Jude A. Rivers, Gary S. Tyson, Edward S. Davidson, Todd M. Austin
Venue: Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture (1997)

Highly aggressive multi-issue processor designs of the past few years and projections for the decade, require that we redesign the operation of the cache memory system. The number of instructions that must be processed (including incorrectly predicted ones) will approach 16 or more per cycle. Since memory operations account for about a third of all instructions executed, these systems will have to support multiple data references per cycle. In this paper, we explore reference stream characteristics to determine how best to meet the need for ever increasing access rates. We identify limitations of existing multi-ported cache designs and propose a new structure, the Locally-Based Interleaved Cache (LBIC), to exploit the characteristics of the data reference stream while approaching the economy of traditional multi-bank cache design. Experimental results show that the LBIC structure is capable of outper forming current multi-ported approaches.
Annealing of Iterative Stochastic Schemes
Authors: Haitao Fang, Guanglu Gong, Minping Qian
Venue: SIAM Journal on Control and Optimization (1997)

Annealing of general iterative stochastic schemes is studied by using Wentzell's large deviation theory. The convergence of this algorithm is shown under some conditions. The closed form of the critical constant is specified in terms of its potential function of the mean model.
Large-Scale Parallel Data Clustering
Authors: Dan Judd, Philip K. McKinley, Anil K. Jain
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1998)

Algorithmic enhancements are described that enable large computational reduction in mean square-error data clustering. These improvements are incorporated into a parallel data-clustering tool, P-CLUSTER, designed to execute on a network of workstations. Experiments involving the unsupervised segmentation of standard texture images were performed. For some data sets, a 96 percent reduction in computation was achieved.
A decomposition approach to variance reduction
Authors: Barry L. Nelson
Venue: Proceedings of the 17th conference on Winter simulation (1985)

For analyzing stochastic models, simulation trades the tractability problems of analytical techniques for the problem of sampling variability. Variance reduction techniques (VRTs) attack this problem by transforming the simulation experiment in a way that makes it more statistically efficient. Unfortunately, VRTs are infrequently used, even though significant reductions are possible in practical problems. This tutorial introduces some basic concepts of variance reduction, and uses a new taxonomy of VRTs as the basis for an algorithm to select appropriate VRTs for general simulation experiments.
Composition Validation and Subjectivity in GenVoca Generators
Authors: Don Batory, Bart J. Geraci
Venue: IEEE Transactions on Software Engineering (1997)

GenVoca generators synthesize software systems by composing components from reuse libraries. GenVoca components are designed to export and import standardized interfaces, and thus be plug-compatible, interchangeable, and interoperable with other components. In this paper, we examine two different but important issues in software system synthesis. First, not all syntactically correct compositions of components are semantically correct. We present simple, efficient, and domain-independent algorithms for validating compositions of GenVoca components. Second, components that export and import immutable interfaces are too restrictive for software system synthesis. We show that the interfaces and bodies of GenVoca components are subjective, i.e., they mutate and enlarge upon instantiation. This mutability enables software systems with customized interfaces to be composed from components with "standardized" interfaces.
Hardware implementation of a general multi-way jump mechanism
Authors: Soo-Mook Moon, Scott D. Carson, Ashok K. Agrawala
Venue: Proceedings of the 23rd annual workshop and symposium on Microprogramming and microarchitecture (1990)

A VLIW architecture capable of testing multiple conditions in one cycle must support effective multiway (conditional) jumps. In this paper, a hardware-implemented, fast, and space-efficient multi-way jump mechanism is developed that speeds up the execution of multiple conditional jumps and reduces wasted storage. A cluster of multiple conditional jumps packed in an instruction can form an arbitrary rooted DAG (Directed Acyclic Graph), where each node corresponds to a condition. Our scheme provides a hardware device called an M-unit, which can combinationally produce the next target address using an encoded description of the DAG and the actual test bits. A technique to reduce the number of different configurations is introduced, along with a memory packing scheme that minimizes wasted memory.
A Fast Algorithm to Map Functions Forward
Authors: Wayne Lawton
Venue: Multidimensional Systems and Signal Processing (1997)

Mapping functions forward is required in image warping and other signal processing applications. The problem is described as follows: specify an integer d \geq 1, a compact domain D \subset R^{d}, lattices L_{1}, L_{2} \subset R^{d}, and a deformation function F : D \rightarrow R^{d} that is continuously differentiable and maps D one-to-one onto F(D). Corresponding to a function J : F(D) \rightarrow R, define the function I = J \circ F. The forward mapping problem consists of estimating values of J on L_{2} \cap F(D), from the values of I and F on L_{1} \cap D. Forward mapping is difficult, because it involves approximation from scattered data (values of I\circ F^{-1} on the set F(L_{1} \cap D)), whereas backward mapping (computing I from J) is much easier because it involves approximation from regular data (values ofJ on L_{2} \cap D). We develop a fast algorithm that approximates J by an orthonormal expansion, using scaling functions related to Daubechies wavelet bases. Two techniques for approximating the expansion coefficients are described and numerical results for a one dimensional problem are used to illustrate the second technique. In contrast to conventional scattered data interpolation algorithms, the complexity of our algorithm is linear in the number of samples.
On Upper Bounds for Minimum Distance and Covering Radiusof Non-binary Codes
Authors: Tero Laihonen, Simon Litsyn
Venue: Designs, Codes and Cryptography (1998)

We consider upper bounds on two fundamental parameters of a code; minimum distance and covering radius. New upper bounds on the covering radius of non-binary linear codes are derived by generalizing a method due to S. Litsyn and A. Tiet&auml;v&auml;inen lt:newu and combining it with a new upper bound on the asymptotic information rate of non-binary codes. The upper bound on the information rate is an application of a shortening method of a code and is an analogue of the Shannon-Gallager-Berlekamp straight line bound on error probability. These results improve on the best presently known asymptotic upper bounds on minimum distance and covering radius of non-binary codes in certain intervals.
Formal verification of complex coherence protocols using symbolic state models
Authors: Fong Pong, Michel Dubois
Venue: Journal of the ACM (JACM) (1998)

Directory-based coherence protocols in shared-memory multiprocessors are so complex that verification techniques based on automated procedures are required to establish their correctness. State enumeration approaches are well-suited to the verification of cache protocols but they face the problem of state space explosion, leading to unacceptable verification time and memory consumption even for small system configurations. One way to manage this complexity and make the verification feasible is to map the system model to verify onto a symbolic state model (SSM). Since the number of symbolic states is considerably less than the number of system states, an exhaustive state search becomes possible, even for large-scale sytems and complex protocols.In this paper, we develop the concepts and notations to verifiy some properties of a directory-based protocol designed for non-FIFO interconnection networks. We compare the verification of the protocol with SSM and with the Stanford Mur 4 , a verification tool enumerating system states. We show that SSM is much more efficient in terms of verification time and memory consumption and therefore holds that promise of verifying much more complex protocols. A unique feature of SSM is that it verifies protocols for any system size and therefore provides reliable verification results in one run of the tool.
A database management system for a VLSI design system
Authors: Gwo-Dong Chen, Tai-Ming Parng
Venue: Proceedings of the 25th ACM/IEEE Design Automation Conference (1988)

A special purpose database management system for VLSI design environment is presented. Besides supporting design data management and tools integration, the system provides lots of facilities for supporting fast development of efficient and powerful VLSI CAD tools. This system could simplify the task and reduce efforts of implementing an integrated VLSI design system.