ppxscal/embedding_network huggingface dataset:
Grape-II: A System-Level Prototyping Environment for DSP Applications
Authors: Rudy Lauwereins, Marc Engels, Marleen Adé, J. a. Peperstraete
Venue: Computer (1995)

Grape-II (Graphical Rapid Prototyping Environment) is an advanced system-level development environment for specifying, compiling, debugging, simulating, and emulating digital-signal-processing applications. Its structured prototyping methodology reduces programming effort, and its use of general-purpose reusable hardware minimizes development cost. The general-purpose hardware consists of commercial DSP processors, bond-out versions of core processors, and FPGAs linked to form a powerful, heterogeneous multiprocessor, such as the Paradigm RP developed within the Retides (Real-Time DSP Emulation System) Esprit project and marketed by InCA/Zycad. Grape-II automates the prototyping methodology for these systems by offering tools for resource estimation, partitioning, assignment, routing, scheduling, code generation, and parameter modification. This prototyping approach has been successfully used for an audio processor for the consumer market, for a sender, receiver and channel simulator for digital audio broadcasting, and for a real- time video encoder for mobile applications. The video-encoder case study, described in the article, resulted in a full-speed operational prototype. This and other successes demonstrate the feasibility of the authors' strategy for prototyping real-time color video compression on a commercial DSP multiprocessor.
Static scheduling of multi-domain memories for functional verification
Authors: Murali Kudlugi, Charles Selvidge, Russell Tessier
Venue: Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design (2001)

Over the past decade both the quantity and complexity of available on-chip memory resources have increased dramatically. In order to ensure accurate ASIC behavior, both logic functions and memory resources must be successfully verified before fabrication. Often, the functional verification of contemporary ASIC memory is complicated by the presence of multiple design clocks that operate asynchronously to each other. The presence of multiple clock domains presents significant challenges for large parallel verification systems such as parallel simulators and logic emulators that model both design logic and memory. Specifically, multiple asynchronous design clocks make it difficult to verify that design hold times are met during memory model execution and causality along memory data/control paths is preserved during signal communication. In this paper, we describe new scheduling heuristics for memory-based designs with multiple asynchronous clock domains that are mapped to parallel verification systems. Our scheduling approach scales to an unlimited number of clock domains and converges quickly to a feasible solution if one exists. It is shown that when our technique is applied to an FPGA-based emulator containing 48MB of SRAM, evaluation fidelity is maintained and increased verification performance is achieved for large, memory-intensive circuits with multiple asynchronous clock domains.
The Problem of Sparse Image Coding
Authors: Arthur E. C. Pece
Venue: Journal of Mathematical Imaging and Vision (2002)

Linear expansions of images find many applications in image processing and computer vision. Overcomplete expansions are often desirable, as they are better models of the image-generation process. Such expansions lead to the use of sparse codes. However, minimizing the number of non-zero coefficients of linear expansions is an unsolved problem. In this article, a generative-model framework is used to analyze the requirements, the difficulty, and current approaches to sparse image coding.
NiSi salicide technology for scaled CMOS
Authors: Hiroshi Iwai, Tatsuya Ohguro, Shun-ichiro Ohmi
Venue: Microelectronic Engineering (2002)

Salicide is one of the indispensable techniques for high-performance logic devices and its importance increases as the device dimensions become small towards sub-100 nm and hence, the source/drain sheet resistance becomes large. TiSi2 used popularly as the silicide material has been eventually replaced by CoSi2, because of its relatively stable nature during the salicide process. For sub-100-nm technology node, CoSi2 is expected to be further replaced by NiSi. NiSi has several advantages over TiSi2 and CoSi2 for the ultra-small CMOS process. They are (1) low temperature silicidation process, (2) low silicon consumption, (3) no bridging failure property, (4) smaller mechanical stress, (5) no adverse narrow line effect on sheet resistance, (6) smaller contact resistance for both n- and p-Si, and (7) higher activation rate of B for SiGe poly gate electrode. In this paper, NiSi salicide technology is explained.
A Tracking Clock Recovery Receiver for 4-Gbps Signaling
Authors: John Poulton, William J. Dally, Steve Tell
Venue: IEEE Micro (1998)

Results of an experimental 0.5-micron CMOS, 4-Gbps signaling chip show the effectiveness of a simple transition-filter equalization technique. The chip uses a tracking clock recovery receiver, in which a 21-phase clock is servoed to center every other clock on the center of the data "eye."
Standards-Are Software Engineering Process Standards Really Necessary?
Authors: F. J. Buckley, M. V. Zelkowitz
Venue: Computer (1992)

The need for software engineering process standards-as opposed to product standards-is discussed from two different viewpoints. M.V. Zelkowitz states that process standards are generally written as policy statements on how to conduct certain processes. As such, they give the framework of the underlying model, but not enough guidance to specify details. They are fuzzy and hard to implement, and they make conformance testing extremely difficult. F.J. Buckley responds to several significant issues raised in Zelkowitz's arguments.
Validating PowerPC Microprocessor Custom Memories
Authors: Narayanan Krishnamurthy, Andrew K. Martin, Magdy S. Abadir, Jacob A. Abraham
Venue: IEEE Design Test (2000)

Due to the high cost of correcting errors in a final product, there is a growing impetus in the industry towards methodologies that can yield correct designs in the first manufacturing run. Design validation methodologies that combine simulation techniques with formal reasoning can be effective in ensuring correct operation of software and hardware systems. We present a validation methodology for PowerPC custom memories based on symbolic simulation and present results on an industrial project at Somerset. We also show why simulation is necessary to complement formal mathematical reasoning in verifying certain classes of custom designed circuits. We then present our results and outline our goals in the areas of design validation using symbolic simulation.
Learning Classification Rules from Database in the Context of Knowledge Acquisition and Representation
Authors: R. Yasdi
Venue: IEEE Transactions on Knowledge and Data Engineering (1991)

A method for learning knowledge from a database is used to address the bottleneck of manual knowledge acquisition. An attempt is made to improve representation with the assistance of experts and from computer resident knowledge. The knowledge representation is described in the framework of a conceptual schema consisting of a semantic model and an event model. A concept classifies a domain into different subdomains. As a method of knowledge acquisition, inductive learning techniques are used for rule generation. The theory of rough sets is used in designing the learning algorithm. Examples of certain concepts are used to induce general specifications of the concepts called classification rules. The basic approach is to partition the information into equivalence classes and to derive conclusions based on equivalence relations. In a sense, what is involved is a data-reduction process, where the goal is to reduce a large database of information to a small number of rules describing the domain. This completely integrated approach includes user interface, semantics, constraints, representations of temporal events, induction, etc.
EVA: an interactive web-based collaborative learning environment
Authors: Leonid Sheremetov, Adolfo Guzmán Arenas
Venue: Computers Education (2002)

In this paper, a Web-based learning environment developed within the project called Virtual Learning Spaces (EVA, in Spanish) is described. The environment is composed of knowledge, collaboration, consulting and experimentation spaces as a collection of agents and conventional software components working over the knowledge domains. All user interfaces are Web pages, generated dynamically by servlets, applets and agents. The article describes theoretical underpinnings, EVA's architecture, implementation of particular software modules and agents, and the application results.
MIST: an algorithm for memory miss traffic management
Authors: Peter Grun, Nikil Dutt, Alex Nicolau
Venue: Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design (2000)

Cache misses represent a major bottleneck in embedded systems performance. Traditionally, compilers optimistically treated all memory accesses as cache hits, relying on the memory controller to account for longer miss delays. However, the memory controller has only a local view of the program, and is not able to efficiently hide the latency of these memory operations. Our compiler technique actively manages cache misses, and performs global miss traffic optimizations, to better hide the latency of the memory operations. Our memory-aware compiler scheduled several benchmarks on the TIC6211 processor architecture with a direct mapped cache, and generated an average of 61.6% improvement over the best schedule of the traditional (memory-transparent) optimizing compiler, demonstrating the utility of our miss traffic optimization approach.
A 65+ Gflop/s unstructured finite element simulation of chemically reacting flows on the Intel Paragon
Authors: John N. Shadid, Scott A. Hutchinson, Harry K. Moffat, Gary L. Hennigan, Bruce Hendrickson, Robert W. Leland
Venue: Proceedings of the 1994 ACM/IEEE conference on Supercomputing (1994)

Many scientific and engineering applications require a detailed analysis of complex systems with strongly coupled fluid flow, thermal energy transfer, mass transfer and nonequilibrium chemical reactions. Here we describe the performance of a newly developed application code, SALSA, designed to simulate these complex flows on large-scale parallel machines such as the Intel Paragon. SALSA uses 3D unstructured finite element methods to model geometrically complex flow systems. Fully implicit time integration, multicomponent mass transport and general gas phase and surface species non-equilibrium chemical kinetics are employed. Using these techniques we have obtained over 65 Gflop/s on a 3D chemically reacting flow CVD problem for Silicon Carbide (SiC) deposition. This represents 46% of the peak performance of our 1904 node Intel Paragon, an outstanding computational rate in view of the required unstructured data communication.
Architectural Design of a Common Operating Environment
Authors: Shawn Butler, David Diskin, Norman Howes, Kathleen Jordan
Venue: IEEE Software (1996)

The architecture for the Global Command and Control System's new common operating environment will comprise several modern architectural concepts currently used in complex, distributed systems. We plan to reduce the environment's complexity by using architectural components supported by existing commercial products and standards.
Reducing Control Points in Surface Interpolation
Authors: Les A. Piegl, Wayne Tiller
Venue: IEEE Computer Graphics and Applications (2000)

A method for interpolating rows of data points with B-spline surfaces is presented. In each row the number points can differ, requiring a skinning-type operator to pass a surface through the points. To avoid data explosion as a result of knot merging, we introduce a new curve interpolation method that uses knots from a given input knot vector. Depending on the initial knot vector and how it is updated during interpolation from row to row, the new method reduces the number of surface control points by 60-97%.
A Parametric Approach to Deductive Databases with Uncertainty
Authors: Laks V. S. Lakshmanan, Nematollaah Shiri
Venue: IEEE Transactions on Knowledge and Data Engineering (2001)

Numerous frameworks have been proposed in recent years for deductive databases with uncertainty. On the basis of how uncertainty is associated with the facts and rules in a program, we classify these frameworks into implication-based (IB) and annotation-based (AB) frameworks. In this paper, we take the IB approach and propose a generic framework, called the parametric framework, as a unifying umbrella for IB frameworks. We develop the declarative, fixpoint, and proof-theoretic semantics of programs in our framework and show their equivalence. Using the framework as a basis, we then study the query optimization problem of containment of conjunctive queries in this framework and establish necessary and sufficient conditions for containment for several classes of parametric conjunctive queries. Our results yield tools for use in the query optimization for large classes of query programs in IB deductive databases with uncertainty.
Interactive Spoken-Language Processing in a Hybrid Connectionist System
Authors: Stefan Wermter, Volker Weber
Venue: Computer (1996)

We have developed a hybrid connectionist/symbolic spoken-language processing system.The SCREEN (Symbolic Connectionist Robust Enterprise for Natural Language) system has to be sufficiently robust to analyze real-world spoken language, which is unpredictable and full of errors. SCREEN uses as its input word hypotheses generated by a speech recognizer, which identifies spoken words for spoken-language processing. After receiving word hypotheses, the system produces many utterance hypotheses and then determines which are most likely to be accurate. The system is robust enough to continue processing spoken language even when encountering incorrect word hypotheses produced by speech recognizers. SCREEN learns a flat syntax, semantics, and pragmatics representation, and deals with uncommon syntactic and semantic language irregularities. It can be used for relatively large and complex tasks. Early connectionist networks could be used only for relatively small tasks.
Serial Interfacing for Embedded-Memory Testing
Authors: Benoit Nadeau-Dostie, Allan Silburt, Vinod K. Agarwal
Venue: IEEE Design Test (1990)

A serial interfacing scheme in which several embedded memories share the built-in, self-test circuit is presented. For external testing, this approach requires only two serial pins for access to the data path. There is considerable savings in routing area, and fewer external pins are needed to test random-access memories with wide words, such as those in application-specific integrated circuits for telecommunications. Even though the method uses serial access to the memory, a test pattern is applied every clock cycle because the memory itself shifts the test data. The method has been adapted to four common algorithms. In implementations of built-in self-test circuitry on several product chips, the area overhead was found to be acceptable.
Parallel Merge Sort with Load Balancing
Authors: Minsoo Jeon, Dongseung Kim
Venue: International Journal of Parallel Programming (2003)

Parallel merge sort is useful for sorting a large quantity of data progressively. The merge sort should be parallelized carefully since the conventional algorithm has poor performance due to the successive reduction of the number of participating processors by half, and down to one in the last merging stage. The proposed load-balanced merge sort utilizes all processors throughout the computation. It evenly distributes data to all processors in each stage. Thus every processor is forced to work in all phases. Significant performance enhancement has been achieved up to a speedup of (P&minus;1)/log P where P is the number of processors. Experimental results demonstrate a speedup of 9.6 (upper bound of 10.7) on 32-processor Cray T3E when sorting 4M 32-bit integers, and a speed up of 2.3 (upper bound of 2.8) on an 8-node PC cluster.
Artificial Intelligence and Financial Services
Authors: L. F. Pau
Venue: IEEE Transactions on Knowledge and Data Engineering (1991)

The author surveys key requirements and specific design techniques for artificial intelligence (AI) applications in the financial services industry. After discussing some of the fundamental challenges which the financial services industry presents for decision technology, the motivations for the use of AI are related to a number of typical applications, which are broadly categorized into suitable development and delivery environments and generic domain utilities required from shells or customized systems for that industry. Markets and trades are then shown to be well described in terms of knowledge representation and data structures, by object-oriented features embedded into logic programming environments. Conflict resolution strategies, preference aggregation and revealed beliefs are studied. A formal analysis of investment decision criteria is given. An example from currency risk management exemplifies this area. Intelligent information screens are presented to stress the need for knowledge-based techniques in financial information retrieval.
Dry oxidation mechanisms of copper in trenches
Authors: L. Carbonell, P. Ratchev, R. Caluwaerts, M. Van Hove, B. Verlinden, K. Maex
Venue: Microelectronic Engineering (2002)

The effect of trace oxygen on the annealing of Cu/Ta(N)/SiO2/Si(001) damascene structures was studied. The dry oxidation of copper was investigated by annealing the wafers at 420 °C for 20 min in N2 ambients with oxygen concentrations ranging from 0 to 2500 ppm in a Rapid Thermal Processing (RTP) system. Electron Backscattered Diffraction (EBSD) mapping (also called 'Orientation Imaging Microscopy' (OIM)) and high resolution Scanning Electron Microscopy (SEM) were used to determine the structure, texture and chemical composition of the annealed copper. For low oxygen contents, the oxidation of the surface in bonding areas is initiated at the grain boundaries and on (111) oriented grains. The oxidation is selective and depends on the segregation of sulphur at the surface of grains with a specific orientation. For higher oxygen concentrations, the oxidation occurs readily and is dependent on the trench geometry, increasing with decreasing line width. In this case, the dimensions, the distribution of impurities in the trenches, and the microstructure of the copper modify the oxidation rate in the small features.
Assessing the Soft Error Rate of Digital Architectures Devoted to Operate in Radiation Environment: A Case Studied
Authors: R. Velazco, S. Rezgui, H. Ziade
Venue: Journal of Electronic Testing: Theory and Applications (2003)

The effects of transient bit flips on the operation of processor based architectures is investigated through fault injection experiments performed in the hardware itself by means of the interruption mechanism. Such an approach is based on the execution, as the consequence of an interruption signal assertion, of pieces of code called CEU (Code Emulating Upsets), asynchronously downloaded in a suitable memory area. This paper focuses in the methodology followed to set-up CEU injection experiments on a digital architecture, illustrating it main steps by means of a studied case: the 80C51 microcontroller. Results obtained from automated fault injection sessions performed using the capabilities of a devoted test system, will point out the capabilities and limitations of the studied approach.
The Responsive Workbench: A Virtual Work Environment
Authors: Wolfgang Krüger, Christian-A. Bohn, Bernd Fröhlich, Heinrich Schüth, Wolfgang Strauss, Gerold Wesche
Venue: Computer (1995)

The daily experiences of professionals who work chiefly at desks and tables have become the basis for modeling human-computer interaction. The scientific visualization process particularly benefits from special human-computer interfaces that support such things as walk-through experiences and virtual object manipulation. In a departure from systems that focus on immersing the user in a virtual environment, the Responsive Workbench has a user-centered, task-driven point of view and--with its computer-connected sensors and reaction devices--is a responsive environment. While specifically examining the working environments of physicians, automotive engineers, and architects, the authors explain the workbench design, hardware and software tool implementations, and some application experiences. Applications determined to be particularly amenable to Responsive Workbench development included medical education and body process representation; dynamic simulations for automotive design, specifically the virtual windtunnel and a mixing process; and landscape and environmental planning. The authors describe results and how they adapted the workbench to each discipline. In all applications, the most important and natural manipulation tool for virtual environments is the user's hand. The Responsive Workbench environment depends on the actual hand, not a computer-generated representation. The user wears a glove device with a Polhemus sensor mounted on the back. The authors list common problems that the workbench shares with other virtual environments and identify sample solutions. They also define areas for future Responsive Workbench development.
Teaching Agents to Learn: From User Study to Implementation
Authors: David Maulsby, Ian H. Witten
Venue: Computer (1997)

Graphical user interfaces have helped center computer use on viewing and editing, rather than on programming. Yet the need for end-user programming continues to grow. Software developers have responded to the demand with a barrage of customizable applications and operating systems. But the learning curve associated with a high level of customizability-even in GUI-based operating systems-often prevents users from easily modifying their software. Ironically, the question has become, "What is the easiest way for end users to program?" Perhaps the best way to customize a program, given current interface and software design, is for users to annotate tasks-verbally or via the keyboard-as they are executing them. Experiments have shown that users can "teach" a computer most easily by demonstrating a desired behavior. But the teaching approach raises new questions about how the system, as a learning machine, will correlate, generalize, and disambiguate a user's instructions. To understand how best to create a system that can learn, the authors conducted an experiment in which users attempt to train an intelligent agent to edit a bibliography. Armed with the results of these experiments, the authors implemented an interactive machine learning system, which they call Configurable Instructible Machine Architecture. Designed to acquire behavior concepts from few examples, Cima keeps users informed and allows them to influence the course of learning. Programming by demonstration reduces boring, repetitive work. Perhaps the most important lesson the authors learned is the value of involving users in the design process. By testing and critiquing their design ideas, users keep the designers focused on their objective: agents that make computer-based work more productive and more enjoyable.