ppxscal/embedding_network huggingface dataset:
Critical path analysis of TCP transactions
Venue: Workshop on Data communication in Latin America and the Caribbean (2001)

Improving the performance of data transfers in the Internet (such as Web transfers) requires a detailed understanding of when and how delays are introduced. Unfortunately, the complexity of data transfers like those using HTTP is great enough that identifying the precise causes of delays is difficult. In this paper we describe a method for pinpointing where delays are introduced into applications like HTTP by using critical path analysis. By constructing and profiling the critical path, it is possible to determine what fraction of total transfer latency is due to packet propagation, network variation (e.g., queuing at routers or route fluctuation). packet losses, and delays at the server and at the client. We have implemented our techique in a tool called tcpeval that automates critical path analysis for Web transactions. We show that our analysis method is robust enough to analyze traces taken for two different TCP implementations (Linux and FreeBSD). To demonstrate the utility of our approach, we present the results of critical path analysis for a set of Web transactions taken over 14 days under a variety of server and network conditions. The results show that critical path analysis can shed considerable light on the causes of delays in Web transfers, and can expose subtleties in the behavior of the entire end-to-end system.
Security&hyphen;enhanced packet video with dynamic multicast throughput adjustment
Authors: Han&hyphen;Chieh Chao T. Y. Wu Jiann&hyphen;Liang Chen
Venue: International Journal of Network Management (2001)

In recent years, the Internet population has increased at an explosive rate. Many problems exist because Internet packets are not encrypted and the bandwidth is not large enough. In this research, we propose a datagram encryption technique and dynamic bandwidth throughput adjustment. Security is enhanced using secret keys selected from a Key&hyphen;Database. Not only is a double encryption tunnel offered but also the whole plaintext can be encrypted more than one key depending on the encryption block size chosen. Copyright &copy; 2001 John Wiley Sons, Ltd.
Periodic Orbits in a Class of Re-Entrant Manufacturing Systems
Authors: Ivonne Diaz-Rivera, Dieter Armbruster, Tom Taylor
Venue: Mathematics of Operations Research (2000)

Queue changes associated with each step of a manufacturing system are modeled by constant vector fields (fluid model of a queueing network). Observing these vector fields at fixed events reduces them to a set of piecewise linear maps. It is proved that these maps show only periodic or eventually periodic orbits. An algorithm to determine the period of the orbits is presented. The dependence of the period on the processing rates is shown for a 3(4)-step, 2-machine problem.
CMOS combinational circuit sizing by stage-wise tapering
Authors: S. Pullela, R. Panda, A. Dharchoudhury, G. Vijayan, D. Blaauw
Venue: Proceedings of the conference on Design, automation and test in Europe (1998)

We describe a fast (linear time) procedure to optimally size transistors in a chain of multi-input gates/stages. The fast sizing is used in a simultaneous sizing and restructuring optimization procedure, to accurately predict relative optimal performance of alternative circuit structures for a given total area. The idea extends the concept of optimally sizing a buffer chain, and uses tapering constants based on the position of a stage in a circuit, and the position of a transistor in a stack.
Dynamic I/O power management for hard real-time systems
Authors: Vishnu Swaminathan, Krishnendu Chakrabarty, S. S. Iyengar
Venue: Proceedings of the ninth international symposium on Hardware/software codesign (2001)

Power consumption is an important design parameter for embedded and portable systems. Software-controlled (or dynamic) power management (DPM) has recently emerged as an attractive alternative to inflexible hardware solutions. DPM for hard real-time systems has received relatively little attention. In particular, energy-driven I/O device scheduling for real-time systems has not been considered before. We present the first online DPM algorithm, which we call Low Energy Device Scheduler (LEDES), for hard real-time systems. LEDES takes as inputs a predetermined task schedule and a device-usage list for each task and it generates a sequence of sleep/working states for each device. It guarantees that real-time constraints are not violated and it also minimizes the energy consumed by the I/O devices used by the task set. LEDES is energy-optimal under the constraint that the start times of the tasks are fixed. We present a case study to show that LEDES can reduce energy consumption by almost 50%.
Contextual understanding by computers
Authors: Joseph Weizenbaum
Venue: Communications of the ACM (1967)

A further development of a computer program (ELIZA) capable of conversing in natural language is discussed. The importance of context to both human and machine understanding is stressed. It is argued that the adequacy of the level of understanding achieved in a particular conversation depends on the purpose of that conversation, and that absolute understanding on the part of either humans or machines is impossible. 0
Randomized binary search technique
Authors: S. R. Arora, W. T. Dent
Venue: Communications of the ACM (1969)

A mathematical model is developed for the mean and variance of the number of trials to recover a given document in a randomly received list of files. The search method described is binary in nature and offers new potential for information retrieval systems.
Optimizing bit-time computer simulation
Authors: Jesse H. Katz
Venue: Communications of the ACM (1963)

A major component of a bit-time computer simulation program is the Boolean compiler. The compiler accepts the Boolean functions representing the simulated computer's digital circuits, and generates corresponding sets of machine instructions which are subsequently executed on the &ldquo;host&rdquo; computer. Techniques are discussed for increasing the sophistication of the Boolean compiler so as to optimize bit-time computer simulation. The techniques are applicable to any general-purpose computer.
Automated systematic testing for constraint-based interactive services
Authors: Patrice Godefroid, Lalita J. Jagadeesan, Radha Jagadeesan Konstantin Läufer
Venue: ACM SIGSOFT Software Engineering Notes (2000)

Constraint-based languages can express in a concise way the complex logic of a new generation of interactive services for applications such as banking or stock trading, that must support multiple types of interfaces for accessing the same data. These include automatic speech-recognition interfaces where inputs may be provided in any order by users of the service. We study in this paper how to systematically test event-driven applications developed using such languages. We show how such applications can be tested automatically, without the need for any manually-written test cases, and efficiently, by taking advantage of their capability of taking unordered sets of events as inputs.
Performance - manufacturability tradeoffs in IC design
Authors: H. T. Heineken, W. Maly
Venue: Proceedings of the conference on Design, automation and test in Europe (1998)

Traditional VLSI design objectives are to minimize time-to-first-silicon while maximizing performance. Such objectives lead to designs which are not optimum from a manufacturability perspective. The objective of this paper is to illustrate the above claim by performing performance/ manufacturability tradeoff analysis. The basis for such an analysis, in which the relationship between a product's clock frequency and wafer productivity is modeled, is described in detail. New applied yield models are discussed as well.
Runtime and quality tradeoffs in FPGA placement and routing
Authors: Chandra Mulpuri, Scott Hauck
Venue: Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays (2001)

Many applications of FPGAs, especially logic emulation and custom computing, require the quick placement and routing of circuit designs. In these applications, the advantages FPGA-based systems have over software simulation are diminished by the long run-times of current CAD software used to map the circuit onto FPGAs. To improve the run-time advantage of FPGA systems, users may be willing to trade some mapping quality for a reduction in CAD tool runtimes. In this paper, we seek to establish how much quality degradation is necessary to achieve a given runtime improvement. For this purpose, we implemented and investigated numerous placement and routing algorithms for FPGAs. We also developed new tradeoff-oriented algorithms, where a tuning parameter can be used to control this quality vs. runtime tradeoff. We show how different algorithms can achieve different points within this tradeoff spectrum, as well as how a single algorithm can be tuned to form a curve in the spectrum. We demonstrate that the algorithms vary widely in their tradeoffs, with the fastest algorithm being 8x faster than the slowest, and the highest quality algorithm being 5x better than the least quality algorithm. Compared to the commercial Xilinx CAD tools, we can achieve a 3x speed-up by allowing 1.27x degradation in quality, and a factor of 1.6x quality improvement with 2x slowdown.
Optimal scheduling for disconnected cooperation
Authors: Grzegorz Greg Malewicz, Alexander Russell, Alex Shvartsman
Venue: Proceedings of the twentieth annual ACM symposium on Principles of distributed computing (2001)

We consider a distributed environment consisting of n processors that need to perform t tasks. We assume that communication is initially unavailable and that processors begin work in isolation. At some unknown point of time an unknown collection of processors may establish communication. Before processors begin communication they execute tasks in the order given by their schedules. Our goal is to schedule work of isolated processors so that when communication is established for the first time, the number of redundantly executed tasks is controlled. We quantify worst case redundancy as a function of processor advancements through their schedules. In this work we refine and simplify an extant deterministic construction for schedules with n &nle; t, and we develop a new analysis of its waste. The new analysis shows that for any pair of schedules, the number of redundant tasks can be controlled for the entire range of t tasks. Our new result is asymptotically optimal: the tails of these schedules are within a 1 + O(n-&frac14;) factor of the lower bound. We also present two new deterministic constructions one for t &nge; n, and the other for t &nge; n3/2, which substantially improve pairwise waste for all prefixes of length t/&radic;n, and offer near optimal waste for the tails of the schedules. Finally, we present bounds for waste of any collection of k &nge; 2 processors for both deterministic and randomized constructions.
Mathematical model for a documentation system
Authors: Allen Kent
Venue: Communications of the ACM (1961)

The Center is currently engaged in a number of theoretical and basic research investigations which are expected to lead to the formulation of a theory of documentation and of searching strategy. A basic program is leading to the development of a mathematical model for a documentation system. Work is proceeding (1) on a comprehensive investigation of the properties of aggregates and systems of messages in order to arrive at a general theory of &ldquo;measure&rdquo; for documentation systems, (2) on an analysis of the algebra that is imposed on the message complex, and (3) on a detailed study of the concept of mapping in documentation.
Modeling, evaluation, and testing of paradyn instrumentation system
Authors: Abdul Waheed, Diane T. Rover, Jeffrey K. Hollingsworth
Venue: Proceedings of the 1996 ACM/IEEE conference on Supercomputing (CDROM) (1996)

This paper presents a case study of modeling, evaluating, and testing the data collection services (called an instrumentation system) of the Paradyn parallel performance measurement tool using well-known performance evaluation and experiment design techniques. The overall objective of the study is to use modeling- and simulation-based evaluation to provide feedback to the tool developers to help them choose system configurations and task scheduling policies that can significantly reduce the data collection overheads. We develop and parameterize a resource occupancy (ROCC) model for Paradyn instrumentation system (IS) for an IBM SP-2 platform. This model is parameterized with a measurement-based workload characterization and subsequently used to answer several "what if" questions regarding configuration options and two policies to schedule instrumentation system tasks: collect-and-forward (CF) and batch-and-forward (BF) policies. Simulation results indicate that the BF policy can significantly reduce the overheads. Based on this feedback, the BF policy was implemented in Paradyn IS as an option to manage the data collection. Measurement-based testing results obtained from this enhanced version of Paradyn IS are reported in this paper and indicate more than 60% reduction in the direct IS overheads when the BF policy is used.
Local Encoding Transformations for Optimizing OBDD-Representations of Finite State Machines
Authors: Christoph Meinel, Thorsten Theobald
Venue: Formal Methods in System Design (2001)

Ordered binary decision diagrams are the state-of-the-art representation of switching functions. In order to keep the sizes of OBDDs tractable, heuristics and dynamic reordering algorithms are applied to optimize the underlying variable order. When finite state machines are represented by OBDDs the state encoding can be used as an additional optimization parameter. In this paper, we analyze local encoding transformations which can be applied dynamically. First, we investigate the potential of re-encoding techniques. We then propose the use of an XOR-transformation and show why this transformation is most suitable among the set of all encoding transformations. The presented theoretical framework establishes a new optimization technique for OBDDs.
Performance evaluation of multiple time scale TCP under self-similar traffic conditions
Authors: Kihong Park, Tsunyi Tuan
Venue: ACM Transactions on Modeling and Computer Simulation (TOMACS) (2000)

Measurements of network traffic have shown that self-similarity is a ubiquitous phenomenon spanning across diverse network environments. In previous work, we have explored the feasibility of exploiting long-range correlation structure in self-similar traffic for congestion control. We have advanced the framework of multiple time scale congestion control and shown its effectiveness at enhancing performance for rate-based feedback control. In this article, we extend the multiple time scale control framework to window-based congestion control, in particular, TCP. This is performed by interfacing TCP with a large time scale module that adjusts the aggressiveness of bandwidth consumpton behavior exhibited by TCP as a function of large time scale network state, that is, information that exceeds the time horizon of the feedback loop as determined by RTT. How to effectively utilize such information&mdash;due to its probabilistic nature, dispersion over multiple time scales, and realization on top of existing window-based congestion controls&mdash;is a nontrivial problem. First, we define a modular extension of TCP (a function call with a simple interface that applies to various flavors of TCP, e.g., Tahoe, Reno, and Vegas) and show that it significantly improves performance. Second, we show that multiple time scale TCP endows the underlying feedback control with proacativity by bridging the uncertainty gap associated with reactive controls which is exacerbated by the high delay-bandwidth product in broadband wide area networks. Third, we investigate the influence of three traffic control dimensions&mdash;tracking ability, connection duration, and fairness&mdash;on performance. Performance evaluation of multiple time scale TCP is facilitated by a simulation benchmark environment based on physical modeling of self-similar traffic. We explicate our methodology for disc
A component model for standardized web-based education
Venue: Journal on Educational Resources in Computing (JERIC) (2001)

We present a layered component model to support Web-based collaborative applications. We show how this model lets programmers focus on the particular logic of their applications, avoiding most of the issues related to collaboration, access control, and network management. The proposed model is organized into three layers on top of a foundation composed of commercial-off-the-shelf services and standard Internet protocols. The service level provides a network-transparent communications layer, database access, and distributed data interchange. The component level offers typical collaborative services, like user management, auditing, user-oriented messaging, higher-level events, project management, and a bulletin board. The application level supports actual applications constructed using the services offered by the underlying layers. A Web-based educational application has been developed over this framework to illustrate the process. This tele-education system, which follows the recommendations of the main institutions involved in the learning technology standardization process, is the second contribution presented by the authors.
An English language question answering system for a large relational database
Authors: David L. Waltz
Venue: Communications of the ACM (1978)

By typing requests in English, casual users will be able to obtain explicit answers from a large relational database of aircraft flight and maintenance data using a system called PLANES. The design and implementation of this system is described and illustrated with detailed examples of the operation of system components and examples of overall system operation. The language processing portion of the system uses a number of augmented transition networks, each of which matches phrases with a specific meaning, along with context registers (history keepers) and concept case frames; these are used for judging meaningfulness of questions, generating dialogue for clarifying partially understood questions, and resolving ellipsis and pronoun reference problems. Other system components construct a formal query for the relational database, and optimize the order of searching relations. Methods are discussed for handling vague or complex questions and for providing browsing ability. Also included are discussions of important issues in programming natural language systems for limited domains, and the relationship of this system to others.
The trade-off between implicit and explicit data distribution in shared-memory programming paradigms
Authors: Dimitrios S. Nikolopoulos, Eduard Ayguadé, Theodore S. Papatheodorou, Constantine D. Polychronopoulos, Jesús Labarta
Venue: Proceedings of the 15th international conference on Supercomputing (2001)

This paper explores previously established and novel methods for scaling the performance of OpenMP on NUMA architectures. The spectrum of methods under investigation includes OS-level automatic page placement algorithms, dynamic page migrationd manual data distribution. The trade-off that these methods face lies between performance and programming effort. Automatic page placement algorithms are transparent to the programmer, but may compromise memory access locality. Dynamic page migration is also transparent, but requires careful engineering of online algorithms to be effective. Manual data distribution on the other requires substantial programming effort and architecture-specific extensions to OpenMP, but may localize memory accesses in a nearly optimal manner. The main contributions of the paper are: a classification of application characteristics, which identifies clearly the conditions under which transparent methods are both capable and sufficient for optimizing memory locality in an OpenMP program; and the use of two novel runtime techniques, runtime data distribution based on memory access traces and affinity scheduling with iteration schedule reuse, as competitive substitutes of manual data distribution in several important classes of applications.
Current-Mode High Output Impedance Sinusoidal Oscillator Configuration Employing Single FTFN
Authors: Uğur Çam, Ali Toker, Oğuzhan ÇiÇekoğlu, Hakan Kuntman
Venue: Analog Integrated Circuits and Signal Processing (2000)

In this study, a general current-mode high output impedance sinusoidal oscillator configuration is proposed. The proposed oscillator configuration uses a single four terminal floating nullor (FTFN), two capacitors and five resistors. The oscillator configuration exhibits high output impedance which makes easy to drive loads without using any buffering devices and provide non-interactive control of oscillation condition and oscillation frequency. The proposed topology also yields single frequency oscillators with reduced number of passive components. All of the proposed oscillators permit good frequency stability and exhibit low active and passive sensitivities. Theoretical analysis is verified with experimental results.
Comparative analysis of the DES cryptographic processor's architecture (abstract only)
Authors: Viktor Melnyk, Tymur Korkishko, Anatoly Melnyk, Juergen Baesig
Venue: Proceedings of the symposium on Contemporary computing in Ukraine (2000)

On this article the DES algorithm and comparative analysis of the DES cryptographic processor's architecture were considered. As the criteria of comparision the performance of the processor's work and equipment volume were taken.
Enhanced reuse and teamwork capabilities for an object-oriented extension of VHDL
Authors: M. Mrva
Venue: Proceedings of the conference on Design, automation and test in Europe (1998)

This paper presents a proposal for enabling VHDL to better support reuse and collaboration. Base idea is passing on the adequate information to partners working in an object-oriented hardware design environment. Appropriate subgoals for achieving this are: · an optimal mix of necessary abstraction and sufficient precision,· a formal description consisting of implementation constraints and knowledge requirements, and · the non-formal concept of mutual consideration.Several loans are made from· the software domain: Java interfaces, type models, and the request for habitability,· the VHDL Annotation Language.This is not an experience report, for the idea of adopting the mentioned software concepts to hardware design is new. It is rather a guided tour to some "panorama views". Although they may not seem related to each other at first glance, they turn out to altogether support a common goal: understanding and communicating VHDL-based designs better.
Method for partial rewriting of magnetic tape
Authors: James A. Miller
Venue: Communications of the ACM (1964)

In simulating the operation of a large storage computer on the IBM 7094, a technique was developed whereby sections of the computer memory which were stored on magnetic tape (IBM 729 Mod II tape drive) could be rewritten without affecting other sections stored on the same tape. The ACM Portal is published by the Association for Computing Machinery. Copyright © 2010 ACM, Inc. Terms of Usage Privacy Policy Code of Ethics Contact Us Useful downloads: Adobe Acrobat QuickTime Windows Media Player Real Player