ppxscal/embedding_network huggingface dataset:
Face to interface: facial affect in (hu)man and machine
Authors: Diane J. Schiano, Sheryl M. Ehrlich, Krisnawan Rahardja, Kyle Sheridan
Venue: Proceedings of the SIGCHI conference on Human factors in computing systems (2000)

Facial expression of emotion (or &ldquo;facial affect&rdquo;) is rapidly becoming an area of intense interest in the computer science and interaction design communities. Ironically, this interest comes at a time when the classic findings on perception of human facial affect are being challenged in the psychological research literature, largely on methodological grounds. This paper presents two studies on perception of facial affect. Experiment 1 provides new data on the recognition of human facial expressions, using experimental methods and analyses designed to systematically address the criticisms and help resolve this controversy. Experiment 2 is a user study on affect in a prototype robot face; the results are compared to the human data of Experiment 1. Together they provide a demonstration of how basic and more applied research can mutually contribute to this rapidly developing field.
A formula for the re-inspection decision
Authors: Tom Adams
Venue: ACM SIGSOFT Software Engineering Notes (1999)

Various recommendations concerning the re-inspection decision can be found in the literature. Some are based on general assumptions or estimates concerning the downstream cost of defects and the proportion of defects that get past the inspection "filter". None of these recommendations allow you to work with your own data or assumptions concerning specific types of documents. This article provides a way to make the re-inspection decision using your own data.
Modulo scheduling for the TMS320C6x VLIW DSP architecture
Authors: Eric Stotzer, Ernst Leiss
Venue: Proceedings of the ACM SIGPLAN 1999 workshop on Languages, compilers, and tools for embedded systems (1999)

Digital Signal Processing (DSP) architectures are specialized for high performance numerical algorithms such as those found in communication and multimedia applications. The development of efficient compilers for DSP processors is a growing research area. The Texas Instruments TMS320C6x (C6x) is a Very Long Instruction Word (VLIW) DSP architecture capable of issuing eight operations in parallel. In this paper, we present the results of implementing a software pipelining algorithm for the C6x. We provide a description of the C6x and detail the architectural features that impact software pipelining such as a moderately sized register file, constraints on code size, homogeneous resources, and multiple assignment code. We discuss how we adapted modulo scheduling to implement software pipelining for the C6x. Finally, we present the results of modulo scheduling a set of 40 loop kernel benchmarks and measure the algorithm in terms of schedule quality and algorithm complexity.
Numerical Approach to Double Well Problems
Authors: Martin Kruzík
Venue: SIAM Journal on Numerical Analysis (1998)

This paper deals with two-sided numerical energy estimates of a solution to two-dimensional double well problems. These estimates are obtained by computing the energy appropriate for the polyconvex envelope and an upper estimate of the energy appropriate for the rank-one convex envelope of the energy density. Examples of computed laminated microstructures are shown.
Auditing Boolean attributes
Authors: Jon Kleinberg, Christos Papadimitriou, Prabhakar Raghavan
Venue: Proceedings of the nineteenth ACM SIGMOD-SIGACT-SIGART symposium on Principles of database systems (2000)

We study the problem of auditing databases which support statistical sum queries to protect the security of sensitive information; we focus on the special case in which the sensitive information is Boolean. Principles and techniques developed for the security of statistical database in the case of continuous attributes do not apply here. We prove certain strong complexity results suggesting that there is no general efficient solution for the auditing problem in this case. We propose two efficient algorithms: The first is applicable when the sum queries are one-dimensional range queries (we prove that the problem is NP-hard even in the two-dimensional case). The second is an approximate algorithm that maintains security, although it may be too restrictive. Finally, we consider a &ldquo;dual&rdquo; variant, with continuous data but an aggregate function that is combinatorial in nature. Specifically, we provide algorithms for two natural definitions of the auditing condition when the aggregate function is MAX.
O-O, what's happening to DB2?
Authors: M. Carey, D. Chamberlin, D. Doole, S. Rielau, N. Mattos, S. Narayanan, B. Vance, R. Swagerman
Venue: ACM SIGMOD Record (1999)

In this presentation, we will describe a collection of new object-relational features that have been added to IBM's DB2 Universal Database (UDB) system. The features to be described include support for structured types, object references, and hierarchies of typed tables and views. These features will be covered from the perspective of a database designer or end user. In addition to presenting the features presently available in DB2 UDB V5.2, which became available in Fall 1998, we will discuss the expected evolution and impact of this technology over time.
Fault-Tolerant Rate-Monotonic Scheduling
Authors: Sunondo Ghosh, Rami Melhem, Daniel Mossé, Joydeep Sen Sarma
Venue: Real-Time Systems (1998)

Due to the critical nature of the tasks in hard real-time systems, it is essential that faults be tolerated. In this paper, we present a scheme which can be used to tolerate faults during the execution of preemptive real-time tasks. We describe a recovery scheme which can be used to re-execute tasks in the event of single and multiple transient faults and discuss conditions that must be met by any such recovery scheme. We then extend the original Rate Monotonic Scheduling (RMS) scheme and the exact characterization of RMS to provide tolerance for single and multiple transient faults. We derive schedulability bounds for sets of real-time tasks given the desired level of fault tolerance for each task or subset of tasks. Finally, we analyze and compare those bounds with existing bounds for non-fault-tolerant and other variations of RMS.
Does computer-generated speech manifest personality? an experimental test of similarity-attraction
Authors: Clifford Nass, Kwan Min Lee
Venue: Proceedings of the SIGCHI conference on Human factors in computing systems (2000)

This study examines whether people would interpret and respond to paralinguistic personality cues in computer-generated speech in the same way as they do human speech. Participants used a book-buying website and heard five book reviews in a 2 (synthesized voice personality: extrovert vs. introvert) by 2 (participant personality: extrovert vs. introvert) balanced, between-subjects experiment. Participants accurately recognized personality cues in TTS and showed strong similarity-attraction effects. Although the content was the same for all participants, when the personality of the computer voice matched their own personality: 1) participants regarded the computer voice as more attractive, credible, and informative; 2) the book review was evaluated more positively; 3) the reviewer was more attractive and credible; and 4) participants were more likely to buy the book. Match of user voice characteristics with TTS had no effect, confirming the social nature of the interaction. We discuss implications for HCI theory and design.
Algorithmic foundations for a parallel vector access memory system
Authors: Binu K. Mathew, Sally A. McKee, John B. Carter, Al Davis
Venue: Proceedings of the twelfth annual ACM symposium on Parallel algorithms and architectures (2000)

This paper presents mathematical foundations for the design of a memory controller subcomponent that helps to bridge the processor/memory performance gap for applications with strided access patterns. The Parallel Vector Access (PVA) unit exploits the regularity of vectors or streams to access them efficiently in parallel on a multi-bank SDRAM memory system. The PVA unit performs scatter/gather operations so that only the elements accessed by the application are transmitted across the system bus. Vector operations are broadcast in parallel to all memory banks, each of which implements an efficient algorithm to determine which vector elements it holds. Earlier performance evaluations have demonstrated that our PVA implementation loads elements up to 32.8 times faster than a conventional memory system and 3.3 times faster than a pipelined vector unit, without hurting the performance of normal cache-line fills. Here we present the underlying PVA algorithms for both word interleaved and cache-line inter-leaved memory systems.
On failure of the pruning technique in &ldquo;Error repair in shift-reduce parsers&rdquo;
Authors: Eberhard Bertsch, Mark-Jan Nederhof
Venue: ACM Transactions on Programming Languages and Systems (TOPLAS) (1999)

A previous article presented a technique to compute the least-cost error repair by incrementally generating configurations that result from inserting and deleting tokens a syntactically incorrect input. An additional mechanism to improve the run-time efficiency of this algorithm by pruning some of the configurations was discussed as well. In this communication we show that the pruning mechanism may lead to suboptimal repairs or may block all repairs. Certain grammatical errors in a common construct of the Java programming language also lead to the above kind of failure.
Communication-Efficient Parallel Sorting
Authors: Michael T. Goodrich
Venue: SIAM Journal on Computing (1999)

We study the problem of sorting n numbers on a p-processor bulk-synchronous parallel (BSP) computer, which is a parallel multicomputer that allows for general processor-to-processor communication rounds provided each processor sends and receives at most h items in any round. We provide parallel sorting methods that use internal computation time that is $O({n\log n \over p})$ and a number of communication rounds that is $O({\log n \over \log (h+1)})$ for $h=\Theta(n/p)$. The internal computation bound is optimal for any comparison-based sorting algorithm. Moreover, the number of communication rounds is bounded by a constant for the (practical) situations when $p\le n^{1-{1/c}}$ for a constant $c\ge 1$. In fact, we show that our bound on the number of communication rounds is asymptotically optimal for the full range of values for p, for we show that just computing the "or" of n bits distributed evenly to the first O(n/h) of an arbitrary number of processors in a BSP computer requires $\Omega(\log n/\log (h+1))$ communication rounds.
The Nonexistence of Some Optimal Ternary Codes of DimensionFive
Authors: Ivan N. Landjev
Venue: Designs, Codes and Cryptography (1998)

We prove the nonexistence of codes with parameters [143,5,94]_3 and [147,5,97]_3. This determines the exact value of n_3(5,d) for d=94,95,96,97,98,99. These were the only d&lsquo;s for which the exact value of n_3(5,d) was not known.
On Parallelizing the Multiprocessor Scheduling Problem
Authors: Ishfaq Ahmad, Yu-Kwong Kwok
Venue: IEEE Transactions on Parallel and Distributed Systems (1999)

Existing heuristics for scheduling a node and edge weighted directed task graph to multiple processors can produce satisfactory solutions but incur high time complexities, which tend to exacerbate in more realistic environments with relaxed assumptions. Consequently, these heuristics do not scale well and cannot handle problems of moderate sizes. A natural approach to reducing complexity, while aiming for a similar or potentially better solution, is to parallelize the scheduling algorithm. This can be done by partitioning the task graphs and concurrently generating partial schedules for the partitioned parts, which are then concatenated to obtain the final schedule. The problem, however, is nontrivial as there exists dependencies among the nodes of a task graph which must be preserved for generating a valid schedule. Moreover, the time clock for scheduling is global for all the processors (that are executing the parallel scheduling algorithm), making the inherent parallelism invisible. In this paper, we introduce a parallel algorithm that is guided by a systematic partitioning of the task graph to perform scheduling using multiple processors. The algorithm schedules both the tasks and messages, and is suitable for graphs with arbitrary computation and communication costs, and is applicable to systems with arbitrary network topologies using homogeneous or heterogeneous processors. We have implemented the algorithm on the Intel Paragon and compared it with three closely related algorithms. The experimental results indicate that our algorithm yields higher quality solutions while using an order of magnitude smaller scheduling times. The algorithm also exhibits an interesting trade-off between the solution quality and speedup while scaling well with the problem size.
Fast deterministic consensus in a noisy environment
Authors: James Aspnes
Venue: Proceedings of the nineteenth annual ACM symposium on Principles of distributed computing (2000)

It is well known that the consensus problem cannot be solved deterministically in an asynchronous environment, but that randomized solutions are possible. We propose a new model, called noisy scheduling, in which an adversarial schedule is perturbed randomly, and show that in this model randomness in the environment can substitute for randomness in the algorithm. In particular, we show that a simplified, deterministic version of Chandra's wait-free shared-memory consensus algorithm [16] solves consensus in time at most logarithmic in the number of active processes. The proof of termination is based on showing that a race between independent delayed renewal processes produces a winner quickly. In addition, we show that the protocol finishes in constant time using quantum and priority-based scheduling on a uniprocessor, suggesting that it is robust against the choice of model over a wide range.
Performance of a joint CDMA/PRMA protocol with heavy-tailed ON/OFF source
Authors: M. Wang, Z. S. Wang, Wei Lu, J. L. Lin, D. R. Chen
Venue: Wireless Networks (1999)

The performance of a joint CDMA/PRMA protocol with heavy-tailed ON/OFF source has been studied. Compared with the random access scheme, the PRMA protocol improves the system performance (such as packet loss, throughput) whether the traffic is SRD or LRD. The less bursty traffic is, the greater the improvement. The buffer design should take into account knowledge about the network traffic such as the presence or absence of the Noah effect in a typical source, especially of \alpha_{\mathrm{on}, the intensity of the Noah effect of ON-period. The smaller \alpha_{\mathrm{on} is, the smaller the buffering gain, and the more packets will be lost. LRD has impacts on the overall system performance. The Noah effect, especially \alpha_{\mathrm{off}, the intensity of the Noah effect of OFF-period, has significant impact on the overall system performance such as capacity, time delay, etc. As \alpha_{\mathrm{off} gets closer to 1, the traffic becomes more bursty, the system capacity is decreased and time delay is increased.
A Four Part Outcome Measurement System
Authors: Hal Mark
Venue: Journal of Medical Systems (1999)

It is suggested that health care outcome measurement systems can be usefully conceptualized in terms of four components. This approach is discussed and illustrated with references to PsychSentinel, a system for measuring psychiatric outcomes. The four components are generic in the sense that they could be used to guide the development of a system for measuring outcomes for any medical specialty. The development of the components are sequential and interdependent. For each component developmental issues and guiding principles are presented. The four components are&semi; a patient classification system, a measure of clinical change (the outcome), a risk-adjustment methodology, and one or more sets of reference norms.
Interactive textbook and interactive Venn diagram: natural and intuitive interfaces on augmented desk system
Authors: Hideki Koike, Yoichi Sato, Yoshinori Kobayashi
Venue: Proceedings of the SIGCHI conference on Human factors in computing systems (2000)

This paper describes two interface prototypes which we have developed on our augmented desk interface system, EnhancedDesk. The first application is Interactive Textbook, which is aimed at providing an effective learning environment. When a student opens a page which describes experiments or simulations, Interactive Textbook automatically retrieves digital contents from its database and projects them onto the desk. Interactive Textbook also allows the student hands-on ability to interact with the digital contents. The second application is the Interactive Venn Diagram, which is aimed at supporting effective information retrieval. Instead of keywords, the system uses real objects such as books or CDs as keys for retrieval. The system projects a circle around each book; data corresponding the book are then retrieved and projected inside the circle. By moving two or more circles so that the circles intersect each other, the user can compose a Venn diagram interactively on the desk. We also describe the new technologies introduced in EnhancedDesk which enable us to implement these applications.
Indexing the edges&mdash;a simple and yet efficient approach to high-dimensional indexing
Authors: Beng Chin Ooi, Kian-Lee Tan, Cui Yu, Stephane Bressan
Venue: Proceedings of the nineteenth ACM SIGMOD-SIGACT-SIGART symposium on Principles of database systems (2000)

In this paper, we propose a new tunable index scheme, called iMinMax(&Ogr;), that maps points in high dimensional spaces to single dimension values determined by their maximum or minimum values among all dimensions. By varying the tuning &ldquo;knob&rdquo; &Ogr;, we can obtain different family of iMinMax structures that are optimized for different distributions of data sets. For a d-dimensional space, a range query need to be transformed into d subqueries. However, some of these subqueries can be pruned away without evaluation, further enhancing the efficiency of the scheme. Experimental results show that iMinMax(&Ogr;) can outperform the more complex Pyramid technique by a wide margin.
System level design and debug of high-performance embedded media systems (embedded tutorial)
Authors: Kees A. Vissers, Pieter van der Wolf, Gert-Jan van Rootselaar
Venue: Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design (1999)

This tutorial on System Level Design practices in Philips consists of three parts. In the first part we discuss application domain characteristics and architectures for video processing. High performance video processing applications impose severe demands on architectures. The architectures need to provide both high bandwidth for communication and high processing power for computation. Such architectures often consist of a combination of programmable cores and more dedicated coprocessors. This is illustrated with the TriMedia based VLIW cores combined with dedicated coprocessors, e.g., an HD resolution MPEG-2 decoder and a dedicated video output processing unit. Several architectures that are developed within Philips will be illustrated. These include the programmable TriMedia VLIW media processor, a dataflow style stream processing architecture, and more dedicated solutions for video processing. Furthermore the future trend of building platforms out of these components will be illustrated.In the second part we discuss the design technology that is employed to perform architecture modeling and evaluation and design space exploration. During the initial stages of architecture design several decisions with a large impact are taken. In Philips, practice is developed to model architectures at a high level of abstraction. With such models architectural options can be explored quantitatively. Such explorations are driven by a suite of characteristic benchmark applications. Several levels of architecture modeling will be illustrated. Methods and tools used for exploration ob both a multiprocessor system including a dedicated MPEG-2 decoder and a future VLIW core will be presented.In the third part we discuss a methodology for System-On-a-Chip debug. For today's multi-million transistor designs, existing design verification techniques cannot guarantee that first silicon is designed error free. Therefore, techniques are necessary to quickly debug first-silicon. In this presentation, we present a methodology for debugging multiple clock domain systems-on-a-chip. The methodology supports the insertion of special debug components in the design (Design-for-Debug). After silicon becomes available debugger tool software is used to interact with these components to enable silicon debugging from a workstation. The tool software provided features such as the ones commonly found in simulation environments e.g., breakpoints and virtual probles. The application of these techniques to a dataflow style video processor will be illustrated.
A New Plethysm Formula for Symmetric Functions
Authors: William F. Doran Iv
Venue: Journal of Algebraic Combinatorics: An International Journal (1998)

This paper gives a new formula for the plethysm of power-sum symmetric functions and Schur symmetric functions with one part. The form of the main result is that for &mu; &vdash; b,p_\mu(\underline x) \circ s_a(\underline x) = \sum_{T} \underline \omega^{{\rm maj}_\mu(T)} s_{{\rm sh} (T)}(\underline x) where the sum is over semistandard tableaux T of weight ab, {\underline\omega} is a root of unity, and maj&mu;(T) is a major index like statistic on semistandard tableaux.An Sb-representation, denoted S&lambda;,b, is defined. In the special case when &lambda; &vdash; b, S&lambda;,b is the Specht module corresponding to &lambda;. It is shown that the character of S&lambda;,b on elements of cycle type &mu; is \sum_T {\underline\omega}^{{\rm maj}_\mu (T)} where the sum is over semistandard tableaux T of shape &lambda; and weight ab. Moreover, the eigenvalues of the action of an element of cycle type &mu; acting on S&lambda;,b are &lcub;{\underline \omega}^{{\rm maj}_\mu(T)} : T&rcub;. This generalizes J. Stembridge&lsquo;s result [11] on the eigenvalues of elements of the symmetric group acting on the Specht modules.
Expressive and efficient pattern languages for tree-structured data (extended abstract)
Authors: Frank Neven, Thomas Schwentick
Venue: Proceedings of the nineteenth ACM SIGMOD-SIGACT-SIGART symposium on Principles of database systems (2000)

It would be desirable to have a query language for tree-structured data that is (1) as easily usable as SQL, (2) as expressive as monadic second-order logic (MSO), and (3) efficiently evaluable. The paper develops some ideas in this direction. Towards (1) the specification of sets of vertices of a tree by combining conditions on their induced subtree with conditions on their path to the root is proposed. Existing query languages allow regular expressions (hence MSO logic) in path conditions but are limited in expressing subtree conditions. It is shown that such query languages fall short of capturing all MSO queries. On the other hand, allowing a certain guarded fragment of MSO-logic in the specification of subtree conditions results in a language fulfilling (2), (3) and, anguably, (1).
A case for more case study research in the implementation of information technology in less-developed countries4
Authors: Ramiro Montealegre
Venue: Information Technology for Development (1999)

While the potentially crucial role of information technology in the development of Third World countries has been widely prescribed, the evolving interaction between IT and the organization during the process of IT implementation and its implications for managers in these environments, has received little attention. This paper argues for more fieldwork to better analyze the dynamic interweaving between the new technology and the social/organizational setting in which it is being embedded.