ppxscal/embedding_network huggingface dataset:
On k-Set Consensus Problems in Asynchronous Systems
Authors: Roberto de Prisco, Dahlia Malkhi, Michael Reiter
Venue: IEEE Transactions on Parallel and Distributed Systems (2001)

In this paper, we investigate the k-set consensus problem in asynchronous distributed systems. In this problem, each participating process begins the protocol with an input value and by the end of the protocol must decide on one value so that at most k total values are decided by all correct processes. We extend previous work by exploring several variations of the problem definition and model, including for the first time investigation of Byzantine failures. We show that the precise definition of the validity requirement, which characterizes what decision values are allowed as a function of the input values and whether failures occur, is crucial to the solvability of the problem. For example, we show that allowing default decisions in case of failures makes the problem solvable for most values of k despite a minority of failures, even in face of the most severe type of failures (Byzantine). We introduce six validity conditions for this problem (all considered in various contexts in the literature), and demarcate the line between possible and impossible for each case. In many cases, this line is different from the one of the originally studied k-set consensus problem.
Minimizing system modification in an incremental design approach
Authors: Paul Pop, Petru Eles Traian Pop Zebo Peng
Venue: Proceedings of the ninth international symposium on Hardware/software codesign (2001)

In this paper we present an approach to mapping and scheduling of distributed embedded systems for hard real-time applications, aiming at minimizing system modification cost. We consider an incremental design process that starts from an already existing system running a set of applications. We are interested to implement new functionality so that the already running applications are disturbed as little as possible and there is a good chance that, later, new functionality can easily be added to the resulted system. The mapping and scheduling problem are considered in the context of a realistic communication model based on a TDMA protocol.
Supply-Chain Excellence for Accelerated Improvement
Authors: Archie Lockamy, Reginald M. Beal, Wilbur I. Smith
Venue: Interfaces (2000)

Many firms have begun employing an integrative approach called supply-chain management (SCM) to manage their raw-materials-supply-production-distribution systems. 3M Company uses SCM to achieve its companywide goals of increasing customer satisfaction and loyalty, doubling the speed of key business processes, and reducing inventories and costs. 3M's experience indicates that to derive tangible benefits from SCM a firm must (1) create a clear vision of what it wants to accomplish, (2) establish and communicate companywide supply-chain goals, (3) develop a definition of its supply chain and formulate goals for improving supply-chain operations, (4) develop a process for implementing SCM, and (5) develop measures for assessing progress toward achieving business-unit and companywide goals.
Using on-computer exams to ensure beginning students' programming competency
Authors: Norman Jacobson
Venue: ACM SIGCSE Bulletin (2000)

The first programming course at UC Irvine has traditionally used graded programming assignments to assess students' programming competence and readiness to undertake the programming required in the next course. Problems with this approach led to replacing the assignments with on-computer programming exams. Several improvements in the course and its ability to reliably meet its goals have resulted.
A Wavelet Packet Algorithm for Classification and Detectionof Moving Vehicles
Authors: Amir Averbuch, Eyal Hulata, Valery Zheludev, Inna Kozlov
Venue: Multidimensional Systems and Signal Processing (2001)

In this paper we propose a robust algorithm that solves two related problems: 1) Classification of acoustic signals emitted by different moving vehicles. The recorded signals have to be assigned to pre-existing categories independently from the recording surrounding conditions. 2) Detection of the presence of a vehicle in a certain class via analysis of its acoustic signature against the existing database of recorded and processed acoustic signals. To achieve this detection with practically no false alarms we construct the acoustic signature of a certain vehicle using the distribution of the energies among blocks which consist of wavelet packet coefficients. We allow no false alarms in the detection even under severe conditions; for example when the acoustic recording of target object is a superposition of the acoustics emitted from other vehicles that belong to other classes. The proposed algorithm is robust even under severe noise and a range of rough surrounding conditions. This technology, which has many algorithmic variations, can be used to solve a wide range of classification and detection problems which are based on acoustic processing which are not related to vehicles. These have numerous applications.
Verification of Similar FSMs by Mixing Incremental Re-encoding, Reachability Analysis, and Combinational Checks
Authors: Stefano Quer, Gianpiero Cabodi, Paolo Camurati, Luciano Lavagno, Ellen M. Sentovich, Robert K. Brayton
Venue: Formal Methods in System Design (2000)

State space exploration is often used to prove properties about sequential behavior of Finite State Machines (FSMs). For example, equivalence of two machines is proved by analyzing the reachable state set of their product machine. Nevertheless, reachability analysis is infeasible on large practical examples. Combinational verification is far less expensive, but on the other hand its application is limited to combinational circuits, or particular design schemes. Finally, approximate techniques imply sufficient, not strictly necessary conditions.The purpose of this paper is to extend the applicability of purely combinational checks. This is generally achieved through state minimization, partitioning, and re-encoding the FSMs to factor out their differences. We focus on re-encoding. In particular, we present an incremental approach to re-encoding for verification that transforms the product machine traversal into a combinational verification in the best case, and into a computationally simpler product machine traversal in the general case.Experimental results demonstrate the effectiveness of this technique on medium-large circuits where other techniques may fail.
The case for registered routing switches in field programmable gate arrays
Authors: Deshanand P. Singh, Stephen D. Brown
Venue: Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays (2001)

FPGAs are characterized by a programmable interconnect that contains highly resistive and capacitive elements. While the configurable structure of the interconnect allows for the implementation of arbitrary circuits, it has also become a significant bottleneck for high-speed circuits. Even if there are only a few signal paths that run along long stretches of interconnect, it is these paths that may determine the maximum operating frequency of the circuit.In this paper we investigate architectural features that could allow us to automatically pipeline the delay associated with long routes without an excessive area penalty. The goal is to reschedule circuit operations in such a way that a signal may use multiple clock cycles to traverse a long route, rather than requiring a single long clock period. This rescheduling would not effect the timing of the visible outputs~(~no latency is added to the overall system~).Specifically, we analyze the effects of adding a small number of registered routing switches to an FPGA architecture with segmented routing resources. A parameterized FPGA architecture is studied where the percentage of registered routing switches is varied and the speed improvement and area penalty is evaluated. Novel algorithms are presented that allow a circuit to best utilize an architecture with a given percentage of registered switches. We believe that this is the first study that attempts to evauate the tradeoffs associated with switches required in FPGA architectures.Our experiments indicate that the architectural features introduced can produce significant speedup for high speed circuits without excessive area costs. We believe that these techniques will become increasingly important in the future as deep sub-micron process technologies shrink, and wire delays become even more significant.
High performance visualization of time-varying volume data over a wide-area network status
Authors: Kwan-Liu Ma, David M. Camp
Venue: Proceedings of the 2000 ACM/IEEE conference on Supercomputing (CDROM) (2000)

This paper presents an end-to-end, low-cost solution for visualizing time-varying volume data rendered on a parallel computer located at a remote site. Pipelining and careful grouping of processors are used to hide I/O time and to maximize processor utilization. Compression is used to significantly cut down the cost of transferring output images from the parallel computer to a display device through a wide-area network. This complete rendering pipeline makes possible highly efficient rendering and remote viewing of high-resolution time-varying data sets in the absence of high-speed network and parallel I/O support. To study the performance of this rendering pipeline and to demonstrate high-performance remote visualization, tests were conducted on a PC cluster in Japan as well as an SGI Origin 2000 operated at the NASA Ames Research Center with the display located at UC Davis.
Price/performance patterns of U. S. computer systems
Authors: E. G. Cale, L. L. Gremillion, J. L. McKenney
Venue: Communications of the ACM (1979)

Econometric models of the U.S. computer market have been developed to study the relationships between system price and hardware performance. Single measures of price/performance such as &ldquo;Grosch's Law&rdquo; are shown to be so oversimplified as to be meaningless. Multiple-regression models predicting system cost as a function of several hardware characteristics do, however, reveal a market dichotomy. On one hand there exists a stable, price predictable market for larger, general purpose computer systems. The other market is the developing one for small business computer systems, a market which is relatively unstable with low price predictability.
On Quiescent Reliable Communication
Authors: Marcos Kawazoe Aguilera., Wei Chen, Sam Toueg
Venue: SIAM Journal on Computing (2000)

We study the problem of achieving reliable communication with quiescent algorithms (i.e., algorithms that eventually stop sending messages) in asynchronous systems with process crashes and lossy links. We first show that it is impossible to solve this problem in asynchronous systems (with no failure detectors). We then show that, among failure detectors that output lists of suspects, the weakest one that can be used to solve this problem is $\diamond \cal P,$ a failure detector that cannot be implemented. To overcome this difficulty, we introduce an implementable failure detector called Heartbeat and show that it can be used to achieve quiescent reliable communication. Heartbeat is novel: in contrast to typical failure detectors, it does not output lists of suspects and it is implementable without timeouts. With Heartbeat, many existing algorithms that tolerate only process crashes can be transformed into quiescent algorithms that tolerate both process crashes and message losses. This can be applied to consensus, atomic broadcast, k-set agreement, atomic commitment, etc.
Methodology for repeater insertion management in the RTL, layout, floorplan and fullchip timing databases of the Itanium microprocessor
Authors: R. McInerney, K. Leeper, T. Hill, H. Chan, B. Basaran, L. McQuiddy
Venue: Proceedings of the 2000 international conference on Computer-aided design (2001)

In this paper, we describe a methodology for inserting repeaters into the RTL, Layout, Floorplan and Fullchip timing databases of the ItaniumTM processor.
Reflection as a mechanism for software integrity verification
Authors: Diomidis Spinellis
Venue: ACM Transactions on Information and System Security (TISSEC) (2000)

The integrity verification of a device's controlling software is an important aspect of many emerging information appliances. We propose the use of reflection, whereby the software is able to examine its own operation, in conjunction with cryptographic hashes as a basis for developing a suitable software verification protocol. For more demanding applications meta-reflective techniques can be used to thwart attacks based on device emulation strategies. We demonstrate how our approach can be used to increase the security of mobile phones, devices for the delivery of digital content, and smartcards.
Regular expression types for XML
Authors: Haruo Hosoya, Jérôme Vouillon, Benjamin C. Pierce
Venue: Proceedings of the fifth ACM SIGPLAN international conference on Functional programming (2000)

We propose regular expression types as a foundation for XML processing languages. Regular expression types are a natural generalization of Document Type Definitions (DTDs), describing structures in XML documents using regular expression operators (i.e., *, ?, |, etc.) and supporting a simple but powerful notion of subtyping.The decision problem for the subtype relation is EXPTIME-hard, but it can be checked quite efficiently in many cases of practical interest. The subtyping algorithm developed here is a variant of Aiken and Murphy's set-inclusion constraint solver, to which are added several optimizations and two new properties: (1) our algorithm is provably complete, and (2) it allows a useful "subtagging" relation between nodes with different labels in XML trees.
Efficient global fanout optimization algorithms
Authors: Rajeev Murgai
Venue: Proceedings of the 2001 Asia and South Pacific Design Automation Conference (2001)

Fanout optimization is a fundamental problem in timing optimization. Most of the research has focused on the fanout optimization problem for a single net (or the local fanout optimization problem - LFO). The real goal, however, is to optimize the delay through the entire circuit by fanout optimization incurring minimum area penalty and without violating the pin loading constraints. This is known as the global fanout optimization (GFO) problem. In this paper, we show that the techniques proposed so far in the literature are either impractical or ineffective for large designs. We propose simple yet efficient and effective schemes for GFO and show that they outperform the "nearly-optimum" reverse topological (RT) algorithm [9] on large industrial designs. One of these schemes yields only 0.3% worse circuit delay on average, but incurs only 18.5% of the area penalty as compared to the RT algorithm and is about 3 times faster. A popularly used mincut-based strategy [7] was not found to be effective.
An architecture for the evolution of Web applications (poster session)
Authors: Paulo Caroli, Carlos José P. de Lucena, Marcus Fontoura
Venue: Addendum to the 2000 proceedings of the conference on Object-oriented programming, systems, languages, and applications (Addendum) (2000)

This work presents a software architecture that is especially useful for managing the evolution of web applications. Web-based systems are a range of applications for which there are no technological standards and new concepts and tools are currently under evolution. Examples of this lack of standards include the transition from CGI scripts to Java Servlets and to Java Server Pages (JSP). Therefore, the maintenance and evolution of web applications is an important topic for software developers and the software research community. The proposed architecture combines the n-tier, broker, and blackboard architectural patterns.
Allocation of Surgeries to Operating Rooms by Goal Programing
Authors: Irem Ozkarahan
Venue: Journal of Medical Systems (2000)

High usage rate in a surgical suite is extremely important in meeting the increasing demand for health care services and reducing costs to improve quality of care. In this paper a goal programming model which can produce schedules that best serve the needs of the hospital, i.e., by minimizing idle time and overtime, and increasing satisfaction of surgeons, patients, and staff, is described. The approach involves sorting the requests for a particular day on the basis of block restrictions, room utilization, surgeon preferences and intensive care capabilities. The model is tested using the data obtained during field studies at Dokuz Eylul University Hospital. The model is also tested for alternative achievement functions to examine the model's ability to satisfy abstract goals.
Open Source in Electronic Design Automation
Authors: Michael Baxter
Venue: Linux Journal (2001)

An interview with Stephen Williams, the creator of the Icarus Veriolg compiler.
Design and analysis of physical design algorithms
Authors: Majid Sarrafzadeh, Elaheh Bozorgzadeh, Ryan Kastner, Ankur Srivastava
Venue: Proceedings of the 2001 international symposium on Physical design (2001)

We will review a few key algorithmic and analysis concepts with application to physical design problems. We argue that design and detailed analysis of algorithms is of fundamental importance in developing better physical design tools and to cope with the complexity of present-day designs.
Multiprogram scheduling: parts 1 and 2. introduction and theory
Authors: E. F. Codd
Venue: Communications of the ACM (1960)

In order to exploit fully a fast computer which possesses simultaneous processing abilities, it should to a large extent schedule its own workload. The scheduling routine must be capable of extremely rapid execution if it is not to prove self-defeating. The construction of a schedule entails determining which programs are to be run concurrently and which sequentially with respect to each other. A concise scheduling algorithm is described which tends to minimize the time for executing the entire pending workload (or any subset of it), subject to external constraints such as precedence, urgency, etc. The algorithm is applicable to a wide class of machines.
Bitwise operations
Authors: C. Strachey
Venue: Communications of the ACM (1961)

Recent contributions on the subject of counting the ones or reversing the digits of a binary word have prompted some rather more general observations on bitwise operations which treat each binary digit in a computer word as a separate entity.
An Efficient SuperGrid Protocol for High Availability and Load Balancing
Authors: Akhil Kumar
Venue: IEEE Transactions on Computers (2000)

Recently there has been a resurgence of interest in quorum-based methods for maintaining consistency of a group of replicated servers as a way to achieve load balancing in addition to high availability. We describe a SuperGrid protocol that performs well for small number of items (less than 100) and evaluate its performance analytically and through simulation experiments. Although it has been shown that it is possible to construct quorum systems where the load is $O(1/\sqrt N )$ and the availability is $\exp ( - \Omega (\sqrt N ))$, these asymptotic results do not perform very well when the number of items is relatively small. In such cases, our results show that the Supergrid protocol outperforms the recent Crumbling Walls protocol and the Paths system. It is also simple and easy to implement.
CartaBlanca&mdash; a pure-Java, component-based systems simulation tool for coupled non-linear physics on unstructured grids
Authors: W. B. VanderHeyden, E. D. Dendy, N. T. Padial-Collins
Venue: Proceedings of the 2001 joint ACM-ISCOPE conference on Java Grande (2001)

This paper describes a component-based non-linear physical system simulation prototyping package written entirely in Java using object-oriented design to provide scientists and engineers a &ldquo;developer-friendly&rdquo; software environment for large-scale computational method and physical model development. The software design centers on the Jacobian-Free Newton-Krylov solution method surrounding a finite-volume treatment of conservation equations. This enables a clean component-based implementation. We first provide motivation for the development of the software and then describe software structure. Discussion of software structure includes a description of the use of Java's built-in thread facility that enables data-parallel, shared-memory computations on a wide variety of unstructured grids with triangular, quadrilateral, tetrahedral and hexahedral elements. We also discuss the use of Java's inheritance mechanism in the construction of a hierarchy of physics-systems objects and linear and non-linear solver objects that simplify development and foster software re-use. As a compliment to the discussion of these object hierarchies, we provide a brief review of the Jacobian-Free Newton-Krylov nonlinear system solution method and discuss how it fits into our design. Following this, we show results from preliminary calculations and then discuss future plans including the extension of the software to distributed memory computer systems.
Query expansion using phonetic confusions for Chinese spoken document retrieval
Authors: Yuk-Chi Li, Wai-Kit Lo, Helen M. Meng, P. C. Ching
Venue: Proceedings of the fifth international workshop on on Information retrieval with Asian languages (2000)

This paper presents a method of query expansion based on phonetic confusions for retrieving spoken documents using text queries. This method is applied to a Chinese spoken document retrieval task. A series of experiments have been carried out for Cantonese broadcast news documents using a multi-scale syllable-based retrieval approach. Our results show an improvement from AIR (average inverse rank) of 0.481 to 0.491 when we apply query expansion based on phonetic confusions to our retrieval task.
Customer context server application enabling customer-focused e-commerce
Authors: Bert Barabas, Mark van Gulik
Venue: Addendum to the 2000 proceedings of the conference on Object-oriented programming, systems, languages, and applications (Addendum) (2000)

Fragmentation of customer data across internal product based systems is preventing a meaningful customer dialog across channels. This problem is compounded further by the addition of new Internet and customer-facing applications from multiple vendors. The typical clicks and mortar company has dozens of e-commerce and product-based systems containing millions of records with customer information without the ability to consolidate the data into a common customer view. Maintaining profitable customer relationships in such an environment requires a new approach. The Customer Context Server application uses a set of frameworks and subsystems operating on an object database to assemble and deliver, within a second, a continuously updated Customer Context to all customer touchpoints even in extremely high volume situations. The Customer Context Server application enables customer conversations to continue where they left off in a multi-vendor environment. The heart of the Customer Context Server application is the scalable Update Stream Processori (USP), which performs asynchronous contention-free updates on hundreds of processors concurrently. Several of the subsystems will be demonstrated including the active modeling and mapping systems used to refine the customer-relationship object mode] and assemble objects from record-based input data.