ppxscal/embedding_network huggingface dataset:
Some Upper Bounds on the Covering Radii of Linear CodesOver \F_q and Their Applications
Authors: H. Janwa, H. F. Mattson, Jr.
Venue: Designs, Codes and Cryptography (1999)

We show that the covering radius R of an [n,k,d] code over \F_q is bounded above by R\leq n-n_q(k, \lceil d/q\rceil). We strengthen this bound when R\leq d and find conditions under which equality holds.As applications of this and other bounds, we show that all binary linear codes of lengths up to 15, or codimension up to 9, are normal. We also establish the normality of most codes of length 16 and many of codimension 10. These results have applications in the construction of codes that attain t[n,k], the smallest covering radius of any binary linear [n,k] code.We also prove some new results on the amalgamated direct sum (&rsquo;&rsquo;ADS&lsquo;&lsquo;) construction of Graham and Sloane. We find new conditions assuring normality of the ADS; covering radius 1 less than previously guaranteed for ADS of codes with even norms; good covering codes as ADS without the hypothesis of normality, from concepts p- stable and s- stable; codes with best known covering radii as ADS of two, often cyclic, codes (thus retaining structure so as to be suitable for practical applications).
A fast scalable classifier tightly integrated with RDBMS
Authors: Liu Hongyan, Lu Hongjun, Chen Jian
Venue: Journal of Computer Science and Technology (2002)

In this paper, we report our success in building efficient scalable classifiers by exploring the capabilities of modern relational database management systems (RDBMS). In addition to high classification accuracy, the unique features of the approach include its high training speed, linear scalability, and simplicity in implementation. More importantly, the major computation required in the approach can be implemented using standard functions provided by the modern relational DBMS. Besides, with the effective rule pruning strategy, the algorithm proposed in this paper can produce a compact set of classification rules. The results of experiments conducted for performance evaluation and analysis are presented.
A fast and robust algorithm for 2D/3D panorama ultrasound data
Authors: Otmar Scherzer, Armin Schoisswohl
Venue: Real-Time Imaging (2002)

This paper presents a fast and robust algorithm for generating compound panorama images from partially (spatially) overlapping data sets. This method results in optimizing a nonlinear functional. We propose a multiscale approach for the solution of the optimization problem that is based on a multiresolution approximation of the image data. This approach makes the computations both fast and stable.
Increasing the Instruction Fetch Rate via Block-Structured Instruction Set Architectures
Authors: Eric Hao, Po-Yung Chang, Marius Evers, Yale N. Patt
Venue: International Journal of Parallel Programming (1998)

To exploit larger amounts of instruction level parallelism, processors are being built with wider issue widths and larger numbers of functional units. Instruction fetch rate must also be increased in order to effectively exploit the performance potential of such processors. Block-structured ISAs provide an effective means of increasing the instruction fetch rate. We define an optimization, called block enlargement, that can be applied to a block-structured ISA to increase the instruction fetch rate of a processor that implements that ISA. We have constructed a compiler that generates block-structured ISA code, and a simulator that models the execution of that code on a block-structured ISA processor. We show that for the SPECint95 benchmarks, the block-structured ISA improves the performance of an aggressive wide issue, dynamically scheduled processor by 15% while using simpler microarchitectural mechanisms to support wide issue and dynamic scheduling.
XFastMesh: fast view-dependent meshing from external memory
Authors: Christopher DeCoro, Renato Pajarola
Venue: Proceedings of the conference on Visualization '02 (2002)

We present a novel disk-based multiresolution triangle mesh data structure that supports paging and view-dependent rendering of very large meshes at interactive frame rates from external memory. Our approach, called XFastMesh, is based on a view-dependent mesh simplification framework that represents half-edge collapse operations in a binary hierarchy known as a merge-tree forest. The proposed technique partitions the merge-tree forest into so-called detail blocks, which consist of binary subtrees, that are stored on disk. We present an efficient external memory data structure and file format that stores all detail information of the multiresolution triangulation method using significantly less storage then previously reported approaches. Furthermore, we present a paging algorithm that provides efficient loading and interactive rendering of large meshes from external memory at varying and view-dependent level-of-detail. The presented approach is highly efficient both in terms of space cost and paging performance.
FIR filter synthesis algorithms for minimizing the delay and the number of adders
Authors: Hyeong Ju Kang, Hansoo Kim, In Cheol Park
Venue: Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design (2000)

As the complexity of digital filters is dominated by the number of multiplications, many works have focused on minimizing the complexity of multiplier blocks that compute the constant coefficient multiplications required in filters. Although the complexity of multiplier blocks is significantly reduced by using efficient techniques such as decomposing multiplications into simple operations and sharing common subexpressions, previous works have not considered the delay of multiplier blocks which is a critical factor in the design of complex filters. In this paper, we present new algorithms to minimize the complexity of multiplier blocks under the given delay constraints. By analyzing multiplier blocks in view of delay, three delay reduction methods are proposed and combined into previous algorithms. Since the proposed algorithms can generate multiplier blocks that meet the specified delay, a trade-off between delay and hardware complexity is enabled by changing the delay constraints. Experimental results show that the proposed algorithms can reduce the delay of multiplier blocks at the cost of a little increase of complexity.
Generalized Multiway Branch Unit for VLIW Microprocessors
Authors: Soo-Mook Moon, Scott D. Carson
Venue: IEEE Transactions on Parallel and Distributed Systems (1995)

VLIW processors use multiway branch instructions to achieve high-speed, parallel evaluation of control structures. This paper introduces a new multiway branch mechanism that allows constant-time branch-target resolution based on an arbitrary condition tree. The unique feature of this mechanism is its target selection unit, which yields a branch-target based on a set of condition bit values and a condition tree description. A representation of condition trees that results in a compact target selection unit is described, and the logic diagram of a target selection unit that provides a four-way branching is shown. Our experimental results on nontrivial integer benchmarks indicate that the proposed multiway branch unit can improve the performance of VLIW machines substantially (i.e., as much as a geometric mean of 35%), compared to using the conventional two-way branching.
Proceedings of the 30th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Venue: Annual Symposium on Principles of Programming Languages (2003)

This volume contains the papers and abstracts presented at POPL'03, the Thirtieth Annual ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages. The POPL conference is a forum for presentation of research on the design, foundations, analysis, and implementation of programming languages and programming systems. This year's conference is in New Orleans, Louisiana.A total of 126 extended abstracts were received in response to a call for papers. SIGPLAN policy forbids submission from members of the program committee. Each submission was read by members of the program committee and short reviews were collected and discussed by the committee as a whole. The deliberation led to the selection of 24 papers. Each abstract was judged according to the originality, clarity, innovation, perceived importance, and appropriateness to the expected audience. Due to the format of the conference, many good papers were not selected.In addition to the contributed papers, the POPL'03 program features three invited talks. The invited speakers were selected by the committee to complement and enhance the program of contributed papers.Although submissions were read and evaluated, the papers that appear in this volume may differ in form and content from the submitted abstracts. The conference selection process does not constitute full review of the work. It is expected that many of the papers printed here will be revised and submitted to refereed archival journals for publication.
The Mips R4000 Processor
Authors: Sunil Mirapuri, Michael Woodacre, Nader Vasseghi
Venue: IEEE Micro (1992)

The R4000, a highly integrated, 64-b RISC microprocessor that provides a simple solution to the increasing demands on the size of address space while maintaining full compatibility with previous Mips processors, is described. The microprocessor's on-chip central processing unit, floating point unit, memory management unit, primary caches, system interface logic, secondary cache control logic with flexible interface, the programmable system interface for high-performance multiprocessor servers and low-cost desktop systems, the flexible multiprocessor support, and the 1.2 million transistors implemented in CMOS technology are discussed. The R4000's superpipelining techniques allow it to process more instructions simultaneously than the previous generation of microprocessors. It is shown that, according to SPEC benchmark tests, it achieves the highest performance of any microprocessor chip
Guest Editors' Introduction: Expanding the Horizons of Location-Aware Computing
Authors: Roy Want, Bill Schilit
Venue: Computer (2001)

Thanks to technical progress on many fronts, we now have location-aware computer applications that sense their location and modify their settings, user interface, and functions accordingly.
Minimization of AND-EXOR Expressions Using Rewrite Rules
Authors: D. Brand, T. Sasao
Venue: IEEE Transactions on Computers (1993)

Conditions for generating optimal two-level AND-EXOR representations using rewrite rules are considered. Four results are presented. First, it is shown that a necessary condition for obtaining minimality is a temporary increase in the size of expressions during minimization. Second, a sufficient condition for obtaining minimality that consists of adding certain two rules to rule sets proposed in the literature is given. Third, transformations that allow the minimization of an expression to proceed by minimizing a transformed expression instead are defined. Fourth, it is determined experimentally that the above three theoretical results lead to better benchmarks results as well.
IC power distribution challenges
Authors: Sudhakar Bobba, Tyler Thorp, Kathirgamar Aingaran, Dean Liu
Venue: Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design (2001)

With each technology generation, delivering a timevarying current with reduced nominal supply voltage variation is becoming more difficult due to increasing current and power requirements. The power delivery network design becomes much more complex and requires accurate analysis and optimizations at all levels of abstraction in order to meet the specifications. In this paper, we describe techniques for estimation of the supply voltage variations that can be used in the design of the power delivery network. We also describe the decoupling capacitor hierarchy that provides a low impedance to the increasing high-frequency current demand and limits the supply voltage variations. Techniques for high-level power estimation that can be used for performance vs. power trade-offs to reduce the current and power requirements of the circuit are also presented.
A Quantitative Evaluation of Cache Types for High-Performance Computer Systems
Authors: C. E. Wu, Y. Hsu, Y. -H. Liu
Venue: IEEE Transactions on Computers (1993)

Parallel accesses to the table lookaside buffer (TLB) and cache array are crucial for high-performance computer systems, and the choice of cache types is one of the most important factors affecting cache performance. The authors classify caches according to both index and tag. Since both index and tag could be either virtual (V) or real (R), their classification results in four combinations or cache types. The real address caches with virtual tags for high-performance computer systems in this study are prediction-based, since index bins are generated from a small array and predictions could be false. As a result, they also discuss and evaluate real address MRU caches with real tags, and propose virtually indexed MRU caches with real tags. Each of the four cache types and MRU caches are discussed and evaluated using trace-driven simulation. The results show that a virtually indexed MRU cache with real tags is a good choice for high-performance computer systems.
Developing the GX Graphics Accelerator Architecture
Authors: Curtis R. Priem
Venue: IEEE Micro (1990)

A novel approach to acceleration is described whereby high-level graphics on entry-level workstations has become practical. In the GX, the host CPU functions as the intelligent controller and two large ASICs (application-specific ICs) supply hardwired graphics functions. An arbitrary quadrilateral is the GX's only geometric primitive. However, it can readily approximate circle and arc primitives with short line segments. In addition, the GX supports flat shading of images only when every pixel on a polygon is the same color or intensity. However, by breaking the object into many smaller objects (tessellation), each with its own color, users can obtain a visually acceptable approximation to Gouraud-shading techniques. A description is given of the frame buffer chip and its graphic attributes and of the transformation engine and cursor chip. The chips do not have the complex instructions found in CISC (complex-instruction-set-computer) processors; rather, they perform the equivalent of very complicated software subroutines. The high speed and scalable performance of the GX and its software interface are discussed.
Computationally Efficient Approximation ofa Probabilistic Model for Document Representationin the WEBSOM Full-Text Analysis Method
Authors: S. Kaski
Venue: Neural Processing Letters (1997)

WEBSOM is a recently developed neural method for exploring full-text document collections, for information retrieval, and for information filtering. In WEBSOM the full-text documents are encoded as vectors in a document space somewhat like in earlier information retrieval methods, but in WEBSOM the document space is formed in an unsupervised manner using the Self-Organizing Map algorithm. In this article the document representations the WEBSOM creates are shown to be computationally efficient approximations of the results of a certain probabilistic model. The probabilistic model incorporates information about the similarity of use of different words to take into account their semantic relations.
Comparison of maximum entropy and minimal mutual information in a nonlinear setting
Authors: Fabian J. Theis, Ch. Bauer, Elmar W. Lang
Venue: Signal Processing (2002)

In blind source separation (BSS), two different separation techniques are mainly used: minimal mutual information (MMI), where minimization of the mutual output information yields an independent random vector, and maximum entropy (ME), where the output entropy is maximized. However, it is yet unclear why ME should solve the separation problem, i.e. result in an independent vector. Yang and Amari have given a partial confirmation for ME in the linear case in [18], where they prove that under the assumption of vanishing expectation of the sources ME does not change the solutions of MMI except for scaling and permutation. In this paper, we generalize Yang and Amari's approach to nonlinear BSS problems, where random vectors are mixed by output functions of layered neural networks. We show that certain solution points of MMI are kept fixed by ME if no scaling in all layers is allowed. In general, ME, however, might also change the scaling in the non-output network layers, hence, leaving the MMI solution points. Therefore, we conclude this paper by suggesting that in nonlinear ME algorithms, the norm of all weight matrix rows of each non-output layer should be kept fixed in later epochs during network training.
View Integration: A Step Forward in Solving Structural Conflicts
Authors: S. Spaccapietra, C. Parent
Venue: IEEE Transactions on Knowledge and Data Engineering (1994)

Thanks to the development of the federated systems approach on the one hand and the emphasis on user involvement in database design on the other, the interest in schema integration techniques is significantly increasing. Theories, methods and tools have been proposed. Conflict resolution is the key issue. Different perceptions by schema designers may lead to different representations. A way must be found to support these different representations within a single system. Most current integration methodologies rely on modification of initial schemas to solve the conflicts. This approach needs a strong interaction with the database administrator, who has authority to modify the initial schemas. This paper presents an approach to view integration specifically intended to support the coexistence of different representations of the same real-world objects. The main characteristics of this approach are the following: automatic resolution of structural conflicts, conflict resolution performed without modification of initial views, use of a formal declarative approach for user definition of inter-view correspondences, applicability to a variety of data models, and automatic generation of structural and operational mappings between the views and the integrated schema. Allowing users' views to be kept unchanged should result in improved user satisfaction. Each user is able to define his own view of the database, without having to conform to some other user's view. Moreover, such a feature is essential in database integration if existing programs are to be preserved.
Efficient Rabin-type Digital Signature Scheme
Authors: Kaoru Kurosawa, Wakaha Ogata
Venue: Designs, Codes and Cryptography (1999)

Rabin&lsquo;s cryptosystem was proved to be as hard as factorization. However, Rabin&lsquo;s digital signature schemes is probabilistic. This paper shows two efficient Rabin type digital signature schemes, a basic scheme and an improved scheme. Both schemes run much faster than Rabin&lsquo;s scheme. They are deterministic and the size of a signature is much smaller than that of a signature in Rabin&lsquo;s scheme. Furthermore, it is proved that, by applying the technique of Bellare and Rogaway, the proposed scheme is secure against chosen plaintext attack. More precisely, breaking the proposed digital signature scheme by chosen plaintext attack is as hard as factoring N.
Integration of measurement tools in medical 3d visualizations
Authors: Bernhard Preim, Christian Tietjen, Wolf Spindler, Heinz Otto Peitgen
Venue: Proceedings of the conference on Visualization '02 (2002)

We discuss 3d interaction techniques for the quantitative analysis of spatial relations in medical visualizations. We describe the design and implementation of measurement tools to measure distances, angles and volumes in 3d visualizations. The visualization of measurement tools as recognizable 3d objects and a 3d interaction, which is both intuitive and precise, determines the usability of such facilities. Measurements may be carried out in 2d visualizations of the original radiological data and in 3d visualizations. The result of a measurement carried out in one view is also displayed in the other view appropriately. We discuss the validation of the obtained measures. Finally, we describe how some important measurement tasks may be solved automatically.
Polynomial Formal Verification of Multipliers
Authors: Martin Keim, Rolf Drechsler, Bernd Becker, Michael Martin, Paul Molitor
Venue: Formal Methods in System Design (2003)

Not long ago, completely automatical formal verification of multipliers was not feasible, even for small input word sizes. However, with Multiplicative Binary Moment Diagrams (&ast;BMD), which is a new data structure for representing arithmetic functions over Boolean variables, methods were proposed by which verification of multipliers with input word sizes of up to 256 Bits is now feasible. Unfortunately, only experimental data has been provided for these verification methods until now.In this paper, we give a formal proof that logic verification with &ast;BMDs is polynomially bounded in both, space and time, when applied to the class of Wallace-tree like multipliers. Using this knowledge online detection of design errors becomes feasible during a verification run.
Programming with Logical Queries, Bulk Updates, and Hypothetical Reasoning
Authors: Weidong Chen
Venue: IEEE Transactions on Knowledge and Data Engineering (1997)

This paper presents a language of update programs that integrates logical queries, bulk updates and hypothetical reasoning in a seamless manner. There is no syntactic or semantic distinction between queries and updates. Update programs extend logic programs with negation in both syntax and semantics. They allow bulk updates in which an arbitrary update is applied simultaneously for all answers of an arbitrary query. Hypothetical reasoning is naturally supported by testing the success or failure of an update. We describe an alternating fixpoint semantics of update programs and show that it can express all nondeterministic database transformations.
Using Patterns To Create Component Documentation
Authors: Jeffrey Kotula
Venue: IEEE Software (1998)

When designing a component, the developer holds certain usage scenarios in mind. But this is not enough. If customers do not understand the component's purpose and how its developer expected it to be used, they will misuse it. Good documentation is the primary means of communication between a software component's creator and its users, providing insight into design intent, use cases, and potential problems. The author provides four examples that show how patterns can provide guidance on documentation content, structure, and presentation.
An Effective Processor Allocation Strategy for Multiprogrammed Shared-Memory Multiprocessors
Authors: Kelvin K. Yue, David J. Lilja
Venue: IEEE Transactions on Parallel and Distributed Systems (1997)

Existing techniques for sharing the processing resources in multiprogrammed shared-memory multiprocessors, such as time-sharing, space-sharing, and gang-scheduling, typically sacrifice the performance of individual parallel applications to improve overall system utilization. We present a new processor allocation technique called Loop-Level Process Control (LLPC) that dynamically adjusts the number of processors an application is allowed to use for the execution of each parallel section of code, based on the current system load. This approach exploits the maximum parallelism possible for each application without overloading the system. We implement our scheme on a Silicon Graphics Challenge multiprocessor system and evaluate its performance using applications from the Perfect Club benchmark suite and synthetic benchmarks. Our approach shows significant improvements over traditional time-sharing and gang-scheduling. It has performance comparable to, or slightly better than, static space-sharing, but our strategy is more robust since, unlike static space-sharing, it does not require a priori knowledge of the applications' parallelism characteristics.