ppxscal/embedding_network huggingface dataset:
Thermodynamic Interpretation of the Quantum Error Correcting Criterion
Authors: Vladimir Korepin, John Terilla
Venue: Quantum Information Processing (2002)

Shannon's fundamental coding theorems relate classical information theory to thermodynamics. More recent theoretical work has been successful in relating quantum information theory to thermodynamics. For example, Schumacher proved a quantum version of Shannon's 1948 classical noiseless coding theorem. In this note, we extend the connection between quantum information theory and thermodynamics to include quantum error correction. There is a standard mechanism for describing errors that may occur during the transmission, storage, and manipulation of quantum information. One can formulate a criterion of necessary and sufficient conditions for the errors to be detectable and correctable. We show that this criterion has a thermodynamical interpretation.PACS: 03.67; 05.30; 63.10
Architecture for a Web-Accessible Simulation Environment
Authors: Siddhartha Chatterjee, M. Paramasivam, William J. Yakowenko
Venue: Computer (1997)

Despite the dynamic and interactive nature of the language underlying applets, the typical applet still performs a fixed set of operations. Users cannot easily reconfigure such a system to perform "what if" experiments or gather statistical or timing information for an experiment. Thus, while Java and the Web support dynamic interactions and enable exciting capabilities in educational software, few applications built on them exploit these capabilities. This article describes CSLab, a proof-of-concept prototype of a simulation environment that is easy to use, dynamic, and Web-accessible. It is designed from the ground up to exploit the inherent dynamic behavior of Java and the Web and to let end users capitalize on this behavior. The authors' goal was to build a framework within which to create, configure, and execute experiments, but instead of the physical sciences they focused on experimental algorithmics. The CSLab executable is a framework for creating various simulation experiments using available modules.
Performance Analysis of Buffer Coherency Policies in a Multisystem Data Sharing Environment
Authors: A. Dan, P. S. Yu
Venue: IEEE Transactions on Parallel and Distributed Systems (1993)

Six buffer coherency policies for a multisystem transaction processing environment are compared. These policies differ in their basic approaches on how and when the invalidated pages are identified or if the updated pages are propagated to the buffers of the remote nodes. They can be classified as detection, notification (of invalid pages), and (update) propagation oriented approaches. The policies trade off CPU overhead of coherency messages with buffer hit probability in different ways, resulting in a tradeoff of response time and maximum throughput. The main contribution is to develop analytical models to predict buffer hit probabilities under various buffer coherency policies assuming the LRU replacement policy and the independent reference model (IRM). The buffer models are validated using simulation models and show excellent agreement. Integrated analytic models capturing buffer hit probability and CPU overhead are developed to predict the overall response times under these coherency policies. The difference in buffer hit probabilities amongst various policies are found to be very sensitive to the skewness of the data access.
A Missing Link in Software Engineering
Authors: Steve Tockey
Venue: IEEE Software (1997)

Before software development can become a true engineering discipline, its practitioners must be well schooled in computer science, discrete mathematics, and a subject too rarely addressed in most university courses today: engineering economy.
Architectures for Exponentiation Over GD(2/sup n/) Adopted for Smartcard Application
Authors: B. Arazi
Venue: IEEE Transactions on Computers (1993)

Two exponentiation circuits are proposed. Using the fact that squaring is a linear operation over GF(2/sup n/), a time-space tradeoff in smartcard-based circuitry is presented. It is shown how multiplication is performed by a single shift, based on replacing the public key alpha /sup a/ in GF(2/sup n/) by its minimal polynomial. Other considerations, related to structure regularity and the possible use of dynamic shift registers, are also treated.
Three Views of Virtual Reality: An Overview
Venue: Computer (1993)

Virtual reality (VR) presents a synthetically generated environment to the user through visual, auditory, and other stimuli. A VR systems's head-mounted display, stereo graphics, and direct manipulation in three dimensions are outlined. Early work in VR and major technological hurdles in the areas of tracking, display, image generation, and software support are reviewed. Research directions and potential applications of VR are discussed.
Access pattern-based memory and connectivity architecture exploration
Authors: Peter Grun, Nikil Dutt, Alex Nicolau
Venue: ACM Transactions on Embedded Computing Systems (TECS) (2003)

Memory accesses represent a major bottleneck in embedded systems power and performance. Traditionally, designers tried to alleviate this problem by relying on a simple cache hierarchy, or a limited use of special purpose memory modules such as stream buffers. Although real-life applications contain a large number of memory references to a diverse set of data structures, a significant percentage of all memory accesses in the application are generated from a few memory instructions that exhibit predictable, well-known access patterns; this creates an opportunity for memory customization, targeting the needs of these access patterns. We present APEX, an approach that extracts, analyzes and clusters the most active access patterns in the application, and aggressively customizes the memory architecture to match the needs of the application. Moreover, though the memory modules are important, the rate at which the memory system can produce the data for the CPU is significantly impacted by the connectivity architecture between the memory subsystem and the CPU. Thus, it is critical to consider the connectivity architecture early in the design flow, in conjunction with the memory architecture. We couple the exploration of memory modules together with their connectivity, to evaluate a wide range of cost, performance, and energy connectivity architectures. We use a heuristic to prune the design space, guiding the exploration towards the most promising designs. We present experiments on a set of large real-life benchmarks, showing significant performance improvements for varied cost and power characteristics, allowing the designer to evaluate customized memory and connectivity configurations for embedded systems.
Cooling Load Density Optimization of an Irreversible Simple Brayton Refrigerator
Authors: Shengbing Zhou, Lingen Chen, Fengrui Sun, Chih Wu
Venue: Open Systems Information Dynamics (2002)

The performance optimization of an irreversible simple Brayton refrigerator coupled to constant-temperature heat reservoirs is carried out by taking the cooling load density, i.e., the ratio of cooling load to the maximum specific volume in the cycle, as the optimization objective using finite-time thermodynamics (FTT) or entropy generation minimization (EGM) in this paper. The analytical formulae about the relations between cooling load density and pressure ratio, as well as between coefficient of performance (COP) and pressure ratio are derived with the heat resistance losses in the hot- and cold-side heat exchangers, and the irreversible compression and expansion losses in the compressor and expander. The influences of the effectiveness of the heat exchangers, the temperature ratio of the reservoirs, and the efficiencies of the compressor and expander on the cooling load density versus COP are provided by numerical examples. The cooling load density optimization is performed by searching the optimum pressure ratio of the compressor, and searching the optimum distribution of heat conductance of the hot- and cold-side heat exchangers for the fixed total heat exchanger inventory. The influences of some design parameters, including the effectiveness of the heat exchangers between the working fluid and heat reservoirs, the efficiencies of compressor and expander, the temperature ratio of heat reservoirs, on the maximum cooling load density, the optimum heat conductance distribution and the optimum pressure ratio are provided by numerical examples. The refrigeration plant design with optimization leads to a smaller size including the compressor, expander, and the hot- and cold-side heat exchangers.
A Performance and Cost Analysis of Applying Superscalar Method to Mainframe Computers
Authors: Kiyoshi Inoue, Yooichi Shintani, Eiki Kamada, Toru Shonai
Venue: IEEE Transactions on Computers (1995)

This paper presents the results of evaluating the increased performance and cost of mainframe computers with superscalar architectures. Since mainframe users demand object compatibility, we assume the same object as that of nonsuperscalar machines. We compared four differently configured superscalar machines based on Hitachi¿s high-end mainframe computer, the HITAC M-880, varying the multiplicity of operand accessibility and arithmetic capability. In estimating performance, we considered the effect of critical path delay on machine cycle time. For scientific jobs, either dual operand accessibility or dual arithmetic capability, or both, improved performance (MIPS) by 11-28% while increasing CPU hardware cost by 2-21%. For online transaction processing (OLTP), no configuration increased performance more than 4%. To make the superscalar architecture more effective for OLTP, it is important to reduce execution cycles per instruction (CPI), by reducing overhead caused by sequential processes.
Low resistivity ohmic contacts on 4H-Silicon carbide for high power and high temperature device applications
Authors: S.-K. Lee, C.-M. Zetterling, M. Östling, J.-P. Palmquist, U. Jansson
Venue: Microelectronic Engineering (2002)

We investigated titanium based ohmic contacts using co-evaporated epitaxial titanium carbide (TiC) on highly doped n+-and p+-type epilayers as well as Al ion implanted layers for high power and high temperature device application. Epitaxially grown TiC ohmic contacts on epilayers as well as Al implanted layers of 4H-SiC were formed by UHV co-evaporation with Ti and C60 at low substrate temperature. The specific contact resistance (ρc) was as low as 5 × 10-6, 2 × 10-5, and 2 × 10-5 Ωcm2 for TiC contacts on n+, on p÷ epilayer, and on Al implanted layer, respectively, using a linear TLM measurement. In addition to TiC, we also investigated TiW (weight ratio 30:70) ohmic contacts to p- and n-type 4H-SiC for the purpose of long-term reliability tests at high temperature. The average ρc of sputtered TiW contacts was 4 × 10-5 for p+ and n+ epilayer. We also found that an evaporated top layer (Au or Pt) helps to protect from degradation of the contacts under long-term reliability tests with temperatures of up to 600°C in a vacuum chamber.
Checkpointing for Distributed Databases: Starting from the Basics
Authors: S. Pilarski, T. Kameda
Venue: IEEE Transactions on Parallel and Distributed Systems (1992)

Checkpointing in a distributed database system is analyzed by establishing a correspondence between consistent snapshots in a general distributed system and transaction-consistent checkpoints in a distributed database system. The analysis culminates in a useful condition for transaction-consistent checkpoints. Based on this condition, a general checkpointing scheme, which records a transaction-consistent set ofvalues of all or some selected data items is presented. These rules are implemented in some representative concurrency control protocols, i.e., those based on two-phase locking and timestamping. These implementations cause little interference with other activities in the database system.
Computing with Contexts
Authors: Ian A. Mason
Venue: Higher-Order and Symbolic Computation (1999)

We investigate a representation of contexts, expressions with holes in them, that enables them to be meaningfully transformed, in particular &alpha;-converted and &beta;-reduced. In particular we generalize the set of &lambda;-expressions to include holes, and on these generalized entities define &beta;-reduction (i.e., substitution) and filling so that these operations preserve &alpha;-congruence and commute. The theory is then applied to allow the encoding of reduction systems and operational semantics of call-by-value calculi enriched with control, imperative and concurrent features.
Generalizations of Eulerian partially ordered sets, flag numbers, and the M&#x00F6;bius function
Authors: Margaret M. Bayer, Gábor Hetyei
Venue: Discrete Mathematics (2002)

A partially ordered set is r-thick if every nonempty open interval contains at least r elements. This paper studies the flag vectors of graded, r-thick posets and shows the smallest convex cone containing them is isomorphic to the cone of flag vectors of all graded posets. It also defines a k-analogue of the Möbius function and k-Eulerian posets, which are 2k-thick. Several characterizations of k-Eulerian posets are given. The generalized Dehn-Sommerville equations are proved for flag vectors of k-Eulerian posets. A new inequality is proved to be valid and sharp for rank 8 Eulerian posets.
Modeling Multithreaded Applications Using Petri Nets
Authors: Krishna M. Kavi, Alireza Moshtaghi, Deng-Jyi Chen
Venue: International Journal of Parallel Programming (2002)

Since most modern computing systems contain multiple processing elements, applications are relying on multithreaded programming techniques that allow a program to execute multiple tasks concurrently to take advantage of the processing capabilities. Multithreaded programs are more difficult to design and test because of the nondeterministic execution orders and synchronization among the threads. Different approaches can be used to test Multithreaded Applications. In our approach we use Petri nets to represent the key elements of interactions among threads to identify potential problems such as race conditions, lost signals, and deadlocks. A tool called C2Petri has been developed which converts C-Pthreads programs to the equivalent Petri net model. This tool helps verification of Pthread-based programs. At present the tool has limited capabilities and we hope to expand the capabilities of our tool in the near future.
Scale Space Tracking and Deformable Sheet Models for Computational Vision
Authors: G. Whitten
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1993)

The deformable sheet, a physical model that provides a natural framework for addressing many vision problems that can be solved by smoothness-constrained optimization, is described. Deformable sheets are characterized by a global energy functional, and the smoothness constraint is represented by a linear internal energy term. Analogous to physical sheets, the model sheets are deformed by problem-specific external forces and, in turn, impose smoothness on the applied forces. The model unifies the properties of scale and smoothness into a single parameter that makes it possible to perform scale space tracking by properly controlling the smoothness constraint. Specifically, the desired scale space trajectory is found by solving a differential equation in scale. The simple analytic dependence on scale also provides a mechanism for adaptive step size control. Results from application of the deformable sheet model to various problems in computational vision are presented.
Fuzzy Logic Techniques in Multimedia Database Querying: A Preliminary Investigation of the Potentials
Authors: Didier Dubois, Henri Prade, Florence Sèdes
Venue: IEEE Transactions on Knowledge and Data Engineering (2001)

Fuzzy logic is known for providing a convenient tool for interfacing linguistic categories with numerical data and for expressing user's preference in a gradual and qualitative way. Fuzzy set methods have been already applied to the representation of flexible queries and to the modeling of uncertain pieces of information in databases systems, as well as in information retrieval. This methodology seems to be even more promising in multimedia databases which have a complex structure and from which documents have to be retrieved and selected not only from their contents, but also from ¿the idea¿ the user has of their appearance, through queries specified in terms of user's criteria. This paper provides a preliminary investigation of the potential applications of fuzzy logic in multimedia databases. The problem of comparing semistructured documents is first discussed. Querying issues are then more particularly emphasized. We distinguish two types of request, namely, those which can be handled within some extended version of an SQL-like language and those for which one has to elicit user's preference through examples.
Adaptive Workload Management through Elastic Scheduling
Authors: Giorgio Buttazzo, Luca Abeni
Venue: Real-Time Systems (2002)

In real-time computing systems, timing constraints imposed on application tasks are typically guaranteed off line using schedulability tests based on fixed parameters and worst-case execution times. However, a precise estimation of tasks&rsquo; computation times is very hard to achieve, due to the non-deterministic behavior of several low-level processor mechanisms, such as caching, prefetching, and DMA data transfer. The disadvantage of relying the guarantee test on a priori estimates is that an underestimation of computation times may jeopardize the correct behavior of the system, whereas an overestimation will certainly waste system resources and causes a performance degradation. In this paper, we propose a new methodology for automatically adapting the rates of a periodic task set without forcing the programmer to provide a priori estimates of tasks&rsquo; computation times. Actual executions are monitored by a runtime mechanism and used as feedback signals for predicting the actual load and achieving rate adaptation. Load balancing is performed using an elastic task model, according to which tasks utilizations are treated as springs with given elastic coefficients.
A Graphical Specification System for User-Interface Design
Authors: Andrew Harbert, William Lively, Sallie Sheppard
Venue: IEEE Software (1990)

An environment for creating user interfaces for embedded systems, called the graphical specification system (GSS), is presented. GSS combines graphical and minimal low-level textual specification with a prototyping capability for rapid user-interface design and evaluation. It is part of a larger embedded systems project at Lockheed, called Express. The user interface components, display components, user-machine interaction, interface-application interaction, and executive component are discussed. Two scenarios, developed with GSS tool prototypes, demonstrate how some GSS tools function. One is the construction of a display with two pairs of gauges, one Cartesian and one polar. The other is the design of a display for submarine tracking.
Magneto-tunneling spectroscopy of quantum structures
Authors: N. Mori, C. Hamaguchi, A. Patan&#x00E8;, L. Eaves, P. C. Main
Venue: Microelectronic Engineering (2002)

We perform numerical calculations to investigate the validity of magneto-tunneling spectroscopy in resonant tunneling diodes as a means of mapping wavefunctions. The effects of the emitter potential profile on wavefunction mapping are discussed.
Assignment of Task Modules in Hypercube Multicomputers with Component Failures for Communication Efficiency
Authors: Bing-Rung Tsai, K. G. Shin
Venue: IEEE Transactions on Computers (1994)

The problem of assigning task modules within a hypercube multicomputer with possible link failures is investigated. A concept of indirect optimization is introduced and a function, called communication traffic, is proposed as the objective of optimization. The assignments obtained from optimizing this function are shown to significantly improve the actual communication performance measure, called communication turnaround time, over random assignments.
A twisted-bundle layout structure for minimizing inductive coupling noise
Authors: Guoan Zhong, Cheng Kok Koh, Kaushik Roy
Venue: Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design (2000)

In this paper, we propose a novel twisted-bundle layout structure for minimizing inductive coupling noise. In this structure, we create several routing regions and re-order the routing of nets in each of these routing regions. The purpose is to create complementary and opposite current loops in the twisted-bundle layout structure, such that the magnetic fluxes arising from any signal net within a twisted group cancel each other in the current loop of a net of interest. The effectiveness of the twisted-bundle structure in minimizing coupling inductance has been verified by the application of FastHenry extraction on a 16-bit bus structure. We achieve about two orders of magnitude reduction in inductive coupling. SPICE simulations also show that the 16-bit twisted-bundle bus structure is able to maintain high signal integrity at high frequency of operation.
Improved load distribution in parallel sparse cholesky factorization
Authors: Edward Rothberg, Robert Schreiber
Venue: Proceedings of the 1994 ACM/IEEE conference on Supercomputing (1994)

Compared to the customary column-oriented approaches, block-oriented, distributed-memory sparse Cholesky factorization benefits from an asymptotic reduction in interprocessor communication volume and an asymptotic increase in the amount of concurrency that is exposed in the problem. Unfortunately, block-oriented approaches (specifically, the block fan-out method) have suffered from poor balance of the computational load. As a result, achieved performance can be quite low. This paper investigates the reasons for this load imbalance and proposes simple block mapping heuristics that dramatically improve it. The result is a roughly 20% increase in realized parallel factorization performance, as demonstrated by performance results from an Intel Paragon&trade; system. We have achieved performance of nearly 3.2 billion floating point operations per second with this technique on a 196-node Paragon system.
A symbolic simulation-based methodology for generating black-box timing models of custom macrocells
Authors: Clayton B. McDonald, Randal E. Bryant
Venue: Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design (2001)

We present a methodology for generating black-box timing models for full-custom transistor-level CMOS circuits. Our approach utilizes transistor-level ternary symbolic timing simulation to explore the input arrival time space and determine the input arrival time windows that result in proper operation. This approach integrates symbolic timing simulation into existing static timing analysis flows and allows automated modelling of the timing behavior of aggressive full-custom circuit design styles.
Model-Based Software Synthesis
Authors: Ben Abbott, Ted Bapty, Csaba Biegl, Gabor Karsai, Janos Sztipanovits
Venue: IEEE Software (1993)

The knowledge-representation and compilation techniques used in a model-based, automatic software synthesis environment are discussed. The environment was used to build Caddmus, a system with more than 250 cooperating processes. The real-time execution environment automatically generates a macro-dataflow computation from declarative models. Central to the approach is the Multigraph Architecture, which provides the framework for model-based synthesis in real-time, parallel-computing environments. Application of Caddmus to analysis of all data related to testing new and redesigned turbine engines is described.