ppxscal/embedding_network huggingface dataset:
Fully Adaptive Minimal Deadlock-Free Packet Routing in Hypercubes, Meshes, and other Networks: Algorithms and Simulations
Authors: G. D. Pifarré, L. Gravano, S. A. Felperin, J. L. C. Sanz
Venue: IEEE Transactions on Parallel and Distributed Systems (1994)

This paper deals with the problem of packet-switched routing in parallel machines.Several new routing algorithms for different interconnection networks are presented.While the new techniques apply to a wide variety of networks, routing algorithms will beshown for the hypercube, the two-dimensional mesh, and the shuffle-exchange. Althoughthe new techniques are designed for packet routing, they can be used alternatively forvirtual cut-through routing models. The techniques presented for hypercubes and meshesare fully-adaptive and minimal. A fully-adaptive and minimal routing is one in which allpossible minimal paths between a source and a destination are of potential use at thetime a message is injected into the network. Minimal paths followed by messagesultimately depend on the local congestion encountered in each node of the network. Allof the new techniques are completely free of deadlock situations.
Design erosion: problems and causes
Authors: Jilles van Gurp, Jan Bosch
Venue: Journal of Systems and Software (2002)

Design erosion is a common problem in software engineering. We have found that invariably, no matter how ambitious the intentions of the designers were, software designs tend to erode over time to the point that redesigning from scratch becomes a viable alternative compared to prolonging the life of the existing design. In this paper, we illustrate how design erosion works by presenting the evolution of the design of a small software system. In our analysis of this example, we show how design decisions accumulate and become invalid because of new requirements. Also it is argued that even an optimal strategy for designing the system (i.e. no compromises with respect to e.g. cost are made) does not lead to an optimal design because of unforeseen requirement changes that invalidate design decisions that were once optimal.
Teaching User-Interface Development
Venue: IEEE Software (1990)

No abstract available The ACM Portal is published by the Association for Computing Machinery. Copyright © 2010 ACM, Inc. Terms of Usage Privacy Policy Code of Ethics Contact Us Useful downloads: Adobe Acrobat QuickTime Windows Media Player Real Player
Memory Power Reduction for High-Speed Implementation of Turbo Codes
Authors: B. Bougard, L. Van Der Perre, F. Maessen, A. Giulietti, V. Derudder, F. Catthoor
Venue: Journal of VLSI Signal Processing Systems (2003)

Turbo codes achieve one of the highest coding gains known and should be the best candidates for error correction in high-speed communication systems. However, the standard implementation of their decoding algorithm suffers from a large latency and high power consumption making them improper for mobile interactive systems. To overcome this drawback, we carefully analyzed the Maximum A Posteriori algorithm, the key-building block of the decoder, and stated that memory accesses are the bottleneck. Therefore, we have systematically optimized the data transfer and storage. This paper presents the main results of this optimization, especially those concerning the memory organization and architecture.Both for the input and the metrics values, a memory sub-layer is introduced such that temporal data locality can be maximally exploited. The architecture is defined to optimally allocate memory units and assign arrays, such that the number of accesses is drastically reduced. The combined optimizations reduce the latency by a factor 600 and the energy per bit by a factor 20, breaking definitely an important obstruction to the application of turbo codes in high-speed communication systems.
Single-Reference Multiple Intermediate Signature (SREMIS) Analysis for BIST
Authors: André Ivanov, Yuejian Wu
Venue: IEEE Transactions on Computers (1995)

Compared to single signature analysis, checking multiple intermediate signatures has many advantages, e.g., smaller aliasing, easier computation of exact fault coverage, and shorter average test time. Conventionally, checking n signatures requires n references. Storing these references and comparing them with collected signatures imposes considerable hardware requirements. In this paper, we propose a novel multiple intermediate signature analysis scheme which checks n signatures against a single reference, thus making the circuitry for checking n signatures essentially the same as that for checking only one. The cost for implementing the proposed scheme is a very small nonrecurring CPU time expenditure in the design phase with no CUT modifications. In return, the proposed scheme yields significant recurring silicon area savings as well as reduced aliasing, and consequently higher test quality. This paper also defines a property for linear compactors that guarantees the existence of an initial state that necessarily yields two identical signatures at arbitrary check points for all circuits.
The Grid Protocol: A High Performance Scheme for Maintaining Replicated Data
Authors: S. Y. Cheung, M. H. Ammar, M. Ahamad
Venue: IEEE Transactions on Knowledge and Data Engineering (1992)

A new protocol for maintaining replicated data that can provide both high data availability and low response time is presented. In the protocol, the nodes are organized in a logical grid. Existing protocols are designed primarily to achieve high availability by updating a large fraction of the copies, which provides some (although not significant) load sharing. In the new protocol, transaction processing is shared effectively among nodes storing copies of the data, and both the response time experienced by transactions and the system throughput are improved significantly. The authors analyze the availability of the new protocol and use simulation to study the effect of load sharing on the response time of transactions. They also compare the new protocol with a voting-based scheme.
The History of the 4004
Authors: Federico Faggin, Marcian E. Hoff Jr., Stanley Mazor, Masatoshi Shima
Venue: IEEE Micro (1996)

The Intel 4004, completed in March 1971, is the world's first microprocessor, the product that sparked the beginning of the mass computerization of society. The history of this remarkable product is told by the four people responsible for its creation. Much has been written about the 4004, often reporting only the recollections of one of its developers. For the first time, the story is told by all four contributors working together to harmonize their recollections. This article describes the various phases of the 4004's creation: its conception; architecture development; design, layout, and debug; the circumstances surrounding its introduction into the marketplace; and the initial market reactions. A description of the 4004's operation and its technical details are also provided with many illustrative figures. In addition, the article includes a sidebar on the early marketing of the microprocessor, another important aspect that led to its success. This will be the definitive reference article for the future.
Solving Satisfiability Via Boltzmann Machines
Authors: A. d'Anjou, M. Graña, F. J. Torrealdea, M. C. Hernandez
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1993)

Boltzmann machines (BMs) are proposed as a computational model for the solution of the satisfiability (SAT) problem in the propositional calculus setting. Conditions that guarantee consensus function maxima for configurations of the BM associated with solutions to the satisfaction problem are given. Experimental results that show a linear behavior of BMs solving the satisfiability problem are presented and discussed.
Recursive discrete Fourier transform with unified IIR filter structures
Authors: Jar-Ferr Yang, Fu-Kun Chen
Venue: Signal Processing (2002)

In this paper, we propose two unified IIR filters to recursively compute the discrete Fourier transform (DFT). With the advantage of local connection, regularity and modularity, the proposed methods can compute all DFT coefficients with the same filter structure. Based on stability behavior, the proposed IIR filter structures with optimal coefficients can achieve more accurate results than the traditional ones whose filter coefficients should be changed for computing the different DFT coefficients. Simulation results verify the aforementioned theoretical observations.
The Cost of COTS
Authors: Nancy Talbert
Venue: Computer (1998)

In this interview, safety-critical systems expert John McDermid explores the sources of risk and the extra analysis work they require. In some cases, he says, this extra effort may erode attractive initial development costs in critical applications. McDermid describes why an application's characteristics are the major influences on the choice of whether to choose COTS or custom. For stringent applications-those that demand high integrity, reliability, and availability- the cost of creating a suitable assurance or safety argument may be prohibitive, or even impossible if there is insufficient access to the COTS software's design rationale. On the other hand, applications that emphasize flexibility may find that real-time kernels, which change relatively little and have seen extensive use, may be more robust than bespoke solutions. Hard data that would clarify the trade-offs between custom versus COTS solutions is still not available. McDermid states that more experience is needed to determine the relative costs of each solution. The observations should be made of a long-term development cycle that includes multiple upgrades and maintenance problems. Meanwhile, he states, the best strategies for those contemplating COTS use are to identify and plan for both project and COTS-specific risks and look beyond the initial development cost to the lifetime support of the product. Those who fail to do so may end up paying more than the COTS solution is worth.
High-Speed Area-Efficient Multiplier Design Using Multiple-Valued Current-Mode Circuits
Authors: S. Kawahito, M. Ishida, T. Nakamura, M. Kameyama, T. Higuchi
Venue: IEEE Transactions on Computers (1994)

Presents a very-large-scale-integration (VLSI)-oriented high-speed multiplier design method based on carry-propagation-free addition trees and a circuit technique, so-called multiple-valued current-mode (MVCM) circuits. The carry-propagation-free addition method uses a redundant digit set such as /spl lcub/0,1,2,3/spl rcub/ and /spl lcub/0,1,2,3,4/spl rcub/. The number representations using such redundant digit sets are called redundant positive-digit number representations. The carry-propagation-free addition is written by three steps, and the adder can be designed directly and efficiently from the algorithm using MVCM circuits. The designed multiplier internally using the MVCM parallel adder with the digit set /spl lcub/0,1,2,3/spl rcub/ in radix 2 has attractive features on speed, regularity of the structure, and reduced complexities of active elements and interconnections. A prototype CMOS integrated circuit of the MVCM parallel adder has been implemented, and its stable operation has been confirmed. Other possible schemes of multipliers with redundant digit sets using MVCM technology are discussed.
Yield Analysis of Reconfigurable Array Processors Based on Multiple-Level Redundancy
Authors: Y. -Y. Chen, S. J. Upadhyaya
Venue: IEEE Transactions on Computers (1993)

Presents and analyzes a new multiple-level redundancy scheme based on hierarchical and element level redundancy for the enhancement of yield and reliability of large area array processors. This scheme can effectively tolerate not only the random defects/faults, but also the clustered defects/faults. The analysis presented here is general in that it takes into account the chip-kill defects occurring in the support circuit area of the array processors and is applicable to a variety of array processors. The authors derive bounds for the support circuit area which will be useful in selecting the most cost-effective redundancy scheme for a given application. The concept of subprocessing element-level redundancy is discussed and it is shown that a combination of subprocessing element-level redundancy with hierarchical redundancy offers significant yield improvements, especially for array processors with large area processing elements. The problem of optimal redundancy is also addressed.
Rendering the first star in the universe: a case study
Authors: Ralf Kähler, Donna Cox, Robert Patterson, Stuart Levy, Hans Christian Hege, Tom Abel
Venue: Proceedings of the conference on Visualization '02 (2002)

For quantitative examination of phenomena that simultaneously occur on very different spatial and temporal scales, adaptive hierarchical schemes are required. A special numerical multilevel technique, associated with a particular hierarchical data structure, is so-called Adaptive Mesh Refinement (AMR). It allows one to bridge a wide range of spatial and temporal resolutions and therefore gains increasing popularity.We describe the interplay of several visualization and VR software packages for rendering time dependent AMR simulations of the evolution of the first star in the universe. The work was done in the framework of a television production for Discovery Channel Television, "The Unfolding Universe.". Parts of the data were taken from one of the most complex AMR simulation ever carried out: It contained up to 27 levels of resolution, requiring modifications to the texture based AMR volume rendering algorithm that was used to depict the density distribution of the gaseous interstellar matter. A voice and gesture controlled CAVE application was utilized to define camera paths following the interesting features deep inside the computational domains. Background images created from cosmological computational data were combined with the final renderings.
Assisting Managers in Project Definition: Foundations for Intelligent Decision Support
Authors: Kent D. Bimson, Linda Boehm Burris
Venue: IEEE Expert: Intelligent Systems and Their Applications (1989)

The authors are developing a knowledge-based software project management system called Watson, written in ART (Automated Reasoning Tool) and Common Lisp. Watson uses a robust conceptual model of the software project management domain as a foundation for assisting software managers in project definition and dynamic problem solving. They present three scenarios (illustrating how managers use Watson in defining project plans), describe the model of software project management constituting the system's conceptual framework, and examine the knowledge representation used to implement this model. The authors define three underlying reasoning processes Watson uses to maintain the integrity of a user's project data during project definition, and they discuss how Watson uses these foundational capabilities to provide more extensive support to managers by assisting in the automatic generation of project plan definitions.
Clustering on a Hypercube Multicomputer
Authors: S. Ranka, S. Sahni
Venue: IEEE Transactions on Parallel and Distributed Systems (1991)

Squared error clustering algorithms for single-instruction multiple-data (SIMD) hypercubes are presented. The algorithms are shown to be asymptotically faster than previously known algorithms and require less memory per processing element (PE). For a clustering problem with N patterns, M features per pattern, and K clusters, the algorithms complete in O(k+log NM) steps on NM processor hypercubes. This is optimal up to a constant factor. These results are extended to the case in which NMK processors are available. Experimental results from a multiple-instruction, multiple-data (MIMD) medium-grain hypercube are also presented.
Some Fundamental Properties of Multiple-Valued Kleenean Functions and Determination of Their Logic Formulas
Authors: Y. Hata, K. Nakashima, K. Yamato
Venue: IEEE Transactions on Computers (1993)

Multiple-valued Kleenean functions that are models of a Kleene algebra and are logic functions expressed by logic formulas composed of variables, constants, and logic operations AND OR, and NOT are discussed. The set of Kleenean functions, is a model with the largest number of logic functions among existing models of a Kleene algebra, such as fuzzy logic functions, regular ternary logic functions, and B-ternary logic functions. Mainly, it is shown that any p-valued Kleenean function is derived from a monotonic ternary input functions and any p-valued unate function is derived from a unate binary input function. The mapping relations between them and the method to determine the logic formula of the Kleenean function and unate function from that of the monotonic ternary input function and unate binary input function, respectively, are classified. 7-or-less-valued Kleenean functions and unate functions of 3-or-fewer variables are enumerated. It is known that the number of p-valued Kleenean functions increases stepwise and that of unate functions increases smoothly as p becomes larger.
No odd pairs in minimal imperfect NP5 graphs
Authors: Jean-Luc Fouquet
Venue: Information Processing Letters (2002)

We prove that a minimal imperfect graph containing a vertex which is not on any induced p5 has no odd pair.
Marketing Technology to Software Practitioners
Authors: Shari Lawrence Pfleeger, Winifred Menezes
Venue: IEEE Software (2000)

We can learn much from the business community about effective technology transfer. In particular, understanding the interests of different types of adopters can suggest to us the different kinds of evidence needed to convince someone to try an innovative technology. At the same time, the legal community offers us advice about what kinds of evidence are needed to build convincing cases that an innovation is an improvement over current practice. This article examines why and how we make technology selection decisions and also considers how evidence supporting these decisions helps or hinders the adoption of new technology.
High-Bandwidth Interleaved Memories for Vector Processors - A Simulation Study
Authors: G. S. Sohi
Venue: IEEE Transactions on Computers (1993)

A family of alternate interleaving schemes called permutation-based interleaving schemes for improving memory bandwidth for a wide range of access patterns in high-performance vector processing systems is described. Permutation-based interleaving schemes can be implemented with a small amount of additional hardware and with a minimal time overhead. The results of a detailed simulation analysis are reviewed. The simulation analysis suggests that, with adequate buffering, permutation-based interleaving schemes similar to those studied can be used to implement a high-bandwidth memory system for vector processors. The resulting memory system sustains its bandwidth for a wide variety of access patterns and for large bank busy times far better than a memory system with standard interleaving.
Optimal Algorithms for the Channel-Assignment Problem on a Reconfigurable Array of Processors with Wider Bus Networks
Authors: Shi-Jinn Horng, Horng-Ren Tsai, Yi Pan, Jennifer Seitzer
Venue: IEEE Transactions on Parallel and Distributed Systems (2002)

The computation model on which the algorithms are developed is the reconfigurable array of processors with wider bus networks (abbreviated to RAPWBN). The main difference between the RAPWBN model and other existing reconfigurable parallel processing systems is that the bus width of each network is bounded within the range \big. [2, \lceil \sqrt{N} \rceil]\bigr.. Such a strategy not only saves the silicon area of the chip as well as increases the computational power enormously, but the strategy also allows the execution speed of the proposed algorithms to be tuned by the bus bandwidth. To demonstrate the computational power of the RAPWBN, the channel-assignment problem is derived in this paper. For the channel-assignment problem with \big. N\bigr. pairs of components, we first design an \big. O(T + \lceil {N\over w} \rceil)\bigr. time parallel algorithm using \big. 2N\bigr. processors with a \big. 2N{\hbox{-}}\rm row\bigr. by \big. 2N{\hbox{-}}\rm column\bigr. bus network, where the bus width of each bus network is \big. w{\hbox{-}}\rm bit\bigr. for \big. 2 \leq w \leq \lceil \sqrt{N} \ \rceil\bigr. and \big. T={\lfloor \log _{w} N \rfloor}+1\bigr.. By tuning the bus bandwidth to the natural \big. \log N{\hbox{-}}\rm bit\bigr. and the extended \big. N^{1/c}{\hbox{-}}\rm bit\bigr. (\big. N^{1/c} > \log N\bigr.) for any constant \big. c\bigr. and \big. c \geq 1\bigr., two more results which run in \big. O(\log N /\log \log N)\bigr. and \big. O(1)\bigr. time, respectively, are also derived. When compared to the algorithms proposed by Olariu et al. [17] and Lin [14], it is shown that our algorithm runs in the equivalent time complexity while significantly reducing the number of processors to \big. O(N)\bigr..
Transaction Processing in Multilevel Secure Databases with Kernelized Architecture: Challenges and Solutions
Authors: Vijayalakshmi Atluri, Sushil Jajodia, Elisa Bertino
Venue: IEEE Transactions on Knowledge and Data Engineering (1997)

Multilevel security poses many challenging problems for transaction processing. The challenges are due to the conflicting requirements imposed by confidentiality, integrity, and availability¿the three components of security. We identify these requirements on transaction processing in Multilevel Secure (MLS) database management systems (DBMSs) and survey the efforts of a number of researchers to meet these requirements. While our emphasis is primarily on centralized systems based on kernelized architecture, we briefly overview the research in the distributed MLS DBMSs as well.
Knowledge-Based Systems for Financial Applications
Authors: David Leinweber
Venue: IEEE Expert: Intelligent Systems and Their Applications (1988)

Reasons for using knowledge-based systems are discussed, and technological innovations in rule-based programming are reviewed. The real-time performance requirements of financial applications are examined, and implementation efficiencies are considered. Financial application examples are described.
Statistical Process Control: Analyzing a Space Shuttle Onboard Software Process
Authors: William A. Florac, Anita D. Carleton, Julie R. Barnard
Venue: IEEE Software (2000)

The demand for increased efficiency and effectiveness of our software processes places measurement demands on the software engineering community beyond those traditionally practiced. Statistical and process thinking principles lead to the use of statistical process control methods to determine consistency and capability of the processes used to develop software. This article stems from a technical collaboration between the Software Engineering Institute and the Space Shuttle Onboard Software Project (collaboration established through Lockheed Martin at the time). The analytic factors involved in using statistical process control to analyze process behavior are discussed using the inspection process as the vehicle to illustrate the role of these factors.
Performance Analysis of Stereo, Vergence, and Focus as Depth Cues for Active Vision
Authors: Subhodev Das, Narendra Ahuja
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1995)

This paper compares the performances of the binocular cues of stereo and vergence, and the monocular cue of focus for range estimation using an active vision system. The performance of each cue is characterized in terms of sensitivity to errors in the imaging parameters. The effects of random, quantization errors are expressed in terms of the standard deviation of the resulting depth error. The effect of systematic, calibration errors on estimation using each cue is also studied. Performance characterization of each cue is utilized to evaluate the relative performance of the cues. Also discussed, based on such characterization, are ways to select a cue taking into account the computational and reliability aspects of the corresponding estimation process.