ppxscal/embedding_network huggingface dataset:
Argo: A System for Design by Analogy
Authors: Michael N. Huhns, Ramon D. Acosta
Venue: IEEE Expert: Intelligent Systems and Their Applications (1988)

The authors have developed domain-independent techniques for reasoning and learning by analogy, techniques that capture and apply problem-solving experience and that are useful for search-intensive problems found in the design domain. They have incorporated these techniques, plus nonmonotonic reasoning capability, into Argo, a tool for building knowledge-based systems that improve with use. They discuss learning from experience and also analogical reasoning and learning. They describe knowledge representation and interference in Argo and Argo's control strategy for design. An application to VLSI circuit design is provided. Various features of Argo are described.
Dynamic Configuration Management in Reliable Distributed Real-Time Information Systems
Authors: K. H. (Kane) Kim, Chittur Subbaraman
Venue: IEEE Transactions on Knowledge and Data Engineering (1999)

Large-scale information systems emerging in challenging application fields must meet the high standards of reliability, maintainability, and service interruption bound requirements. Their operations are entirely, or partially, of the distributed real-time data object manipulation type. A new architecture for such systems is presented in this paper. The original aspects of the architecture are mainly in two parts: 1) the time-triggered message-triggered object (TMO) structuring of the middleware and the application software of distributed real-time information systems; and 2) the dynamic configuration management subsystem (DCMS), based on the supervisor-based network surveillance (SNS) scheme. The positive impacts of this TMO structuring on maintainability and service interruption bounds are first discussed, with distributed replicated information service systems and other systems as examples. Then, the main discussion dwells on the DCMS architecture¿in particular, formal presentation of its key component: the SNS scheme. As a component of DCMS, the network surveillance (NS) subsystem enables fast learning by each interested fault-free node in the system of the faults or repair completion events occurring in other parts of the system. Currently, concrete real-time NS schemes effective in distributed systems based on point-to-point network architectures are scarce. The SNS scheme presented in this paper is a semicentralized real-time NS scheme effective in a variety of point-to-point networks. This scheme is highly scalable. An efficient implementation model for the SNS scheme is presented that can be easily adapted to various commercial operating system kernels. This paper also presents a formal analysis of the SNS scheme, on the basis of the implementation model, to obtain its strongly competitive tight bounds on the fault detection latency. Finally, some DCMS implementation issues are discussed that remain to be addressed in future research.
Techniques for Synthesis of Analog Integrated Circuits
Authors: Brian A. A. Antao, Arthur J. Brodersen
Venue: IEEE Design Test (1992)

The CAD tools that have been developed for automated analog synthesis are reviewed. The synthesis process is described. The major techniques employed by the tools are examined. They are knowledge-based hierarchical design, analytic design, and placement/routing. Critical design issues are identified. It is shown how the technique discussed could be combined in a comprehensive framework supporting design from specification to physical layout.
On the Advantages of Polar and Log-Polar Mapping for Direct Estimation of Time-To-Impact from Optical Flow
Authors: M. Tistarelli, G. Sandini
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1993)

The application of an anthropomorphic retina-like visual sensor and the advantages of polar and log-polar mapping for visual navigation are investigated. It is demonstrated that the motion equations that relate the egomotion and/or the motion of the objects in the scene to the optical flow are considerably simplified if the velocity is represented in a polar or log-polar coordinate system, as opposed to a Cartesian representation. The analysis is conducted for tracking egomotion but is then generalized to arbitrary sensor and object motion. The main result stems from the abundance of equations that can be written directly that relate the polar or log-polar optical flow with the time to impact. Experiments performed on images acquired from real scenes are presented.
Testing Expert Systems in Process Control
Authors: Kai Finke, Matthias Jarke, Roland Soltysiak, Peter Szczurko
Venue: IEEE Transactions on Knowledge and Data Engineering (1996)

Special features of process control expert systems (PCX) make it both necessary and feasible to test them in a comprehensive manner. FAITH, an automated regression testing environment for PCX, integrates five specially adapted testing techniques, exploiting external specifications gained from the process control environment. FAITH also offers a set of metrics which can be used to predict testability during the early phases of PCX development. FAITH has been developed for a major German chemicals company where it is routinely used for certifying PCX, and for guiding design-for-testability.
Synthesis of Mathematical-Modeling Software
Authors: Elaine Kant
Venue: IEEE Software (1993)

Sinapse, a knowledge-based, domain-specific system for synthesizing mathematical-modeling software, is discussed. Sinapse generates Fortran-77, Connection Machine Fortran, or C programs from specifications of mathematical equations and numerical methods. The synthesis process is divided into phases of refinement that attempt to duplicate the users' problem-solving processes in the design, implementation, and evolution states of mathematical modeling. These phases, with automated implementation, help modelers increase their productivity because they can write concise specifications and quickly experiment with variations on their models and algorithms by modifying specifications rather than implementations.
Personalized trading recommendation system
Authors: Jungsoon Yoo, Melinda Gervasio, Pat Langley
Venue: Proceedings of the 8th international conference on Intelligent user interfaces (2003)

The Stock Tracker is a personalized recommendation system for trading stocks. The system tailors its buy, sell, and hold recommendations to individual users through automatically acquired content-based models of user preferences. It relies on data gathered unobtrusively during the natural course of interacting with a user.
Dimensional dual hyperovals in projective spaces and c.AG*-geometries
Authors: Cécile Huybrechts
Venue: Discrete Mathematics (2002)

The two subjects of the title are studied, first independently and then by making them interact. Many questions arise from this interaction.In our intrinsic study of the first subject, we construct a new family of examples and define the notions of quotient and universality. For the second subject, we restrict the class c.AG* of circular extensions of dual affine spaces under the two geometrical conditions (LL) and (T) by showing that, apart from some extreme cases, every such rank three geometry can be erected into a rank 4 geometry. In particular, c.AG*n(q)-geometries satisfying (LL) and (T) with n ≥ 3 must have q even. We then deduce similar results for the first subject.
Railway Computation for Infinite Linear Systems
Authors: Paola Favati, Grazia Lotti, Ornella Menchi, Francesco Romani
Venue: International Journal of Parallel Programming (2002)

The problem of solving an infinite system of linear equations finitely expressed is addressed. Modifications of the Gauss&ndash;Seidel method are presented, especially suitable for the implementation on SMP machines with a small number of processors. One of the proposed parallel algorithms, which concentrates the computational efforts where they are most needed, results to be more efficient than the sequential algorithm, even from the point of view of the total number of operations.
An Efficient File Structure for Document Retrieval in the Automated Office Environment
Authors: D. H. -C. Du, S. Ghanta, K. J. Maly, S. M. Sharrock
Venue: IEEE Transactions on Knowledge and Data Engineering (1989)

A file system tailored to the general needs of the office environment is proposed. This system supports large numbers of a wide variety of documents and inexact fuzzy queries on the documents. The file system is based on a multilevel file structure that combines and extends multikey extendible hashing and signature files to create a document-retrieval system that is more time efficient than other previously proposed systems and is also space efficient.
A Robust Compile Time Method for SchedulingTask Parallelism on Distributed Memory Machines
Authors: Sekhar Darbha, Santosh Pande
Venue: The Journal of Supercomputing (1998)

The problem of compile time scheduling of tasks of a program represented as a directed acyclic graph (DAG) is NP-hard in its general form. A number of approaches have been proposed which attempt to solve the problem either sub-optimally for general cases or optimally for restrictive special cases. But all the compile time approaches suffer due to the inability to accurately model the computation and communication costs of the target architecture. A desirable property of a compile time scheduling algorithm is robustness against the variations in the computation and communication costs so that the run time performance is close to the compile time estimates; this aspect of scheduling has been left open in the literature.This paper first introduces a compile time scheduling algorithm for a variable number of available processors and then examines the impact of change of computation and communication costs on the generated schedule. The cost variations for all the nodes and all the edges are assumed to be uniform (in other words, all the node costs change by the same ratio and the edge costs change by the same ratio). This sort of variations could occur due to the inaccuracies in estimating the instruction execution times or the message passing delays. The ratio of the schedule length obtained by the new schedule based on the modified costs to the schedule length obtained by using the modified costs on the original schedule (obtained by initial costs) is used as a measure of the robustness of the algorithm. The essential conditions for robustness of the proposed algorithm are discussed and are demonstrated through an experimental study.
Utilization Based Schedulability Bounds for Age Constraint Process Sets in Real-Time Systems
Authors: Lars Lundberg
Venue: Real-Time Systems (2002)

Some real-time systems consist of a number of processes that operate under age constraints. In such systems, the maximum time from the start of process Li in cycle k to the end in cycle k+1 must not exceed the age constraint Ai for that process. The age constraint can be met by using fixed priority scheduling and periods equal to Ai/2. However, this approach restricts the number of process sets which are schedulable. In this paper, we define a method for obtaining process periods other than Ai/2. The periods are calculated in such a way that the age constraints are met. Our approach is better in the sense that a larger number of process sets can be scheduled compared to using periods equal to Ai/2. The main results in this paper are a number of performance bounds on age constraint processes. These bounds show that there is a significant gain in worst case as well as in best case behavior by using periods other than Ai/2, particularly when there are a large number of processes in the system.
Scheduling of Offset Free Systems
Authors: Joël Goossens
Venue: Real-Time Systems (2003)

In this paper, we study the problem of scheduling hard real-time periodic tasks. We consider independent tasks which are characterized by a period, a hard deadline and a computation time, but where the offsets may be chosen by the scheduling algorithm. We first show that we can restrict the problem by considering non-equivalent offset assignments. More precisely, we show that there are finitely many non-equivalent offset assignments and we propose a method to reduce significantly this number and consider only the minimal number of non-equivalent offset assignments. We then propose an optimal offset assignment rule which considers only the non-equivalent offset assignments. However the number of combinations remains exponential; for this reason, we also propose a nearly optimal algorithm with a more reasonable time complexity.
A General Methodology of Partitioning and Mapping for Given Regular Arrays
Authors: Xian Chen, Graham M. Megson
Venue: IEEE Transactions on Parallel and Distributed Systems (1995)

A methodology for partitioning and mapping of arbitrary uniform recurrence equations (UREs) expressed as computation graphs onto a given regular array is proposed. Deriving and based on a set of canonical dependencies together with two models of space projection, we give a general method of parallelization. The method has significant advantages in mapping an arbitrary computation graph onto a given processor array while preserving high efficiency in both communication and computation.
Emerging Standards for Component Software
Authors: Richard M. Adler
Venue: Computer (1995)

Software vendors have developed competing and incompatible standards to support and drive the compound document and component software technologies. These standards specify distinct object models, data storage models, and application interaction protocols. The incompatibilities have resulted in confusion in the market as vendors, users, system integrators, and developers struggle to sort out the standards' relative merits, weaknesses, and chances for commercial success. This article examines general technical concepts underlying compound documents and component software; the OpenDoc, OLE 2, COM, and CORBA standards that have been proposed for the two technologies; and the work that is underway to extend the standards and to achieve interoperability across them.
Segmentation of MR and CT Images Using a Hybrid Neural Network Trained by Genetic Algorithms
Authors: Zümray Dokur
Venue: Neural Processing Letters (2002)

A novel hybrid neural network trained by the genetic algorithms is presented. Genetic algorithms are used to improve the neural net's classification performance while minimizing the number of nodes. Each node of the network forms a closed region in the input space. The closed regions, which are formed by the nodes, intersect each other. The performance of the proposed hybrid neural network is compared with the multilayer perceptron, and the restricted Coulomb energy network for the segmentation of MR and CT head images. Experimental results show that the proposed neural network gives the best classification performance with a small number of nodes in short training times.
Operational Profiles in Software-Reliability Engineering
Authors: John D. Musa
Venue: IEEE Software (1993)

A systematic approach to organizing the process of determining the operational profile for guiding software development is presented. The operational profile is a quantitative characterization of how a system will be used that shows how to increase productivity and reliability and speed development by allocating development resources to function on the basis of use. Using an operational profile to guide testing ensures that if testing is terminated and the software is shipped because of schedule constraints, the most-used operations will have received the most testing and the reliability level will be the maximum that is practically achievable for the given test time. For guiding regression testing, it efficiently allocates test cases in accordance with use, so the faults most likely to be found, of those introduced by changes, are the ones that have the most effect on reliability.
Constructing H4, a Fast Depth-Size Optimal Parallel Prefix Circuit
Authors: Yen-Chun Lin, Yao-Hsien Hsu, Chun-Keng Liu
Venue: The Journal of Supercomputing (2003)

Given n values x1, x2,&hellip;,xn and an associative binary operation &otimes;, the prefix problem is to compute x1&otimes;x2&otimes;&tdot;&otimes;xi, 1&le;i&le;n. Prefix circuits are combinational circuits for solving the prefix problem. For any n-input prefix circuit D with depth d and size s, if d+s&equals;2n&minus;2, then D is depth-size optimal. In general, a prefix circuit with a small depth is faster than one with a large depth. For prefix circuits with the same depth, a prefix circuit with a smaller fan-out occupies less area and is faster in VLSI implementation. This paper is on constructing parallel prefix circuits that are depth-size optimal with small depth and small fan-out. We construct a depth-size optimal prefix circuit H4 with fan-out 4. It has the smallest depth among all known depth-size optimal prefix circuits with a constant fan-out; furthermore, when n&ge;136, its depth is less than, or equal to, those of all known depth-size optimal prefix circuits with unlimited fan-out. A size lower bound of prefix circuits is also derived. Some properties related to depth-size optimality and size optimality are introduced; they are used to prove that H4 is depth-size optimal.
Present day use of the internet for survey-based research
Authors: J. E. Gonzalez
Venue: Journal of Technology in Human Services (2002)

This article argues that Internet-based survey research studies are presently limited in their utility. What many consider "classical" blunders in political polling that took place in the 1930s are used as a vehicle for describing parallel methodological errors that may occur with present-day use of the Internet. Without thoughtful protocols, Internet-based surveys are susceptible to these familiar errors, which limit their predictive utility. Tools such as e-mail, file transfers, and data and information access/retrieval should continue to be the primary role of Internet use. A model that articulates the use of Internet technology in survey research is offered for consideration.
The Compiled Logic Simulator
Authors: Brion Keller, David P. Carlson, William Maloney
Venue: IEEE Design Test (1991)

A two-value, zero-delay simulator that computes signatures and analyzes fault coverage for circuits with built-in self-test (BIST) is described. The simulator, called the compiled logic simulator (CLS), is used with a monitor that simulates BIST control logic at a high level. The simulator's compiled code is well suited to the IBM 3090 pipeline and fault simulation using flat random patterns. The linear-feedback-shift-register simulation monitor is discussed. Performance results are presented. Fault simulation with one million random patterns on a 40000-gate circuit was done in 16 CPU minutes.
Artificial Life: A Constructive Lower Bound for Artificial Intelligence
Authors: Richard K. Belew
Venue: IEEE Expert: Intelligent Systems and Their Applications (1991)

Artificial life refers to computational investigations of questions involving the nature of life and its evolution; it is considered as a lower bound on artificial intelligence, as embodied in the statement that 'the dumbest smart thing you can do is stay alive'. The centrality of evolution to artificial life and the algorithmic approach to evolutionary modeling are examined. Approaches to modeling the environment are discussed and the relationship between artificial life and computation is explored.
A 2-(22, 8, 4) Design Cannot Have a 2-(10, 4, 4) Subdesign
Authors: Patric R. J. Östergård
Venue: Designs, Codes and Cryptography (2002)

The smallest BIBD, as for the number of points and blocks, whose existence is still undecided is 2-(22, 8, 4). Possible subconfigurations of such a design, namely 2-(10, 4, 4) designs, are here ruled out. The result is obtained by classifying all 2-(10, 4, 4) designs and trying to find 2-(22, 8, 4) designs by solving instances of the maximum clique problem.
A Novel Concurrent Error Detection Scheme for FFT Networks
Authors: D. L. Tao, C. R. P. Hartmann
Venue: IEEE Transactions on Parallel and Distributed Systems (1993)

The algorithm-based fault tolerance techniques have been proposed to obtain reliableresults at very low hardware overhead. Even though 100% fault coverage can betheoretically obtained by using these techniques, the system performance, i.e., faultcoverage and throughput, can be drastically reduced due to many practical problems,e.g., round-off errors. A novel algorithm-based fault tolerance scheme is proposed forfast Fourier transform (FFT) networks. It is shown that the proposed scheme achieves100% fault coverage theoretically. An accurate measure of the fault coverage for FFTnetworks is provided by taking the round-off error into account. The proposed scheme isshown to provide concurrent error detection capability to FFT networks with lowhardware overhead, high throughput, and high fault coverage.
Crossover in Grammatical Evolution
Authors: Michael O'neill, Conor Ryan, Maarten Keijzer, Mike Cattolico
Venue: Genetic Programming and Evolvable Machines (2003)

We present an investigation into crossover in Grammatical Evolution that begins by examining a biologically-inspired homologous crossover operator that is compared to standard one and two-point operators. Results demonstrate that this homologous operator is no better than the simpler one-point operator traditionally adopted.An analysis of the effectiveness of one-point crossover is then conducted by determining the effects of this operator, by adopting a headless chicken-type crossover that swaps randomly generated fragments in place of the evolved strings. Experiments show detrimental effects with the utility of the headless chicken operator.Finally, the mechanism of crossover in GE is analysed and termed ripple crossover, due to its defining characteristics. An experiment is described where ripple crossover is applied to tree-based genetic programming, and the results show that ripple crossover is more effective in exploring the search space of possible programs than sub-tree crossover by examining the rate of premature convergence during the run. Ripple crossover produces populations whose fitness increases gradually over time, slower than, but to an eventual higher level than that of sub-tree crossover.
Design of Supervised Classifiers Using Boolean Neural Networks
Authors: Srinivas Gazula, Mansur R. Kabuka
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1995)

In this paper we present two supervised pattern classifiers designed using Boolean neural networks (BNN). They are 1) nearest-to-an-exemplar (NTE) and 2) Boolean k-nearest neighbor (BKNN) classifier. The emphasis during the design of these classifiers was on simplicity, robustness, and the ease of hardware implementation. The classifiers use the idea of radius of attraction (ROA) to achieve their goal. Mathematical analysis of the algorithms presented in the paper is done to prove their feasibility. Both classifiers are tested with well-known binary and continuous feature valued data sets yielding results comparable with those obtained by similar existing classifiers.