ppxscal/embedding_network huggingface dataset:
Response Time Driven Multimedia Data Objects Allocation for Browsing Documents in Distributed Environments
Authors: Siu-Kai So, Ishfaq Ahmad, Kamalakar Karlapalem
Venue: IEEE Transactions on Knowledge and Data Engineering (1999)

Distributed information processing, in many world wide web applications, requires access, transfer, and synchronization of large multimedia data objects (MDOs) (such as, audio, video, and images) across the communication network. Moreover, the end users have started expecting very fast response times and high quality of service. Since the transfer of large MDOs across the communication network contributes to the response time observed by the end users, the problem of allocating these MDOs so as to minimize the response time becomes very challenging. This problem becomes more complex in the context of hypermedia documents (web pages), wherein the MDOs need to be synchronized during presentation to the end users. Note that the basic problem of data allocation in distributed database environments is NP-complete. Therefore, there is a need to pursue and evaluate solutions based on heuristics which generate near-optimal MDO allocation. In this paper, we address this problem by: 1) conceptualizing this problem by using a navigational model to represent hypermedia documents and their access behavior from end users, and by capturing the synchronization requirements on MDOs, 2) formulating the problem by developing a base case cost model for response time, and generalizing it to incorporate user interaction and buffer memory constraints, 3) designing two algorithms to find near-optimal solutions for allocating MDOs of the hypermedia documents while adhering to the synchronization requirements, and 4) evaluating the trade-off between the time complexity to get the solution and the quality of solution by comparing the solutions generated by the algorithms with the optimal solutions generated through an exhaustive search.
Specifying Graceful Degradation
Authors: M. P. Herlihy, J. M. Wing
Venue: IEEE Transactions on Parallel and Distributed Systems (1991)

A description is given of the relaxation lattice method, a new approach to specifyinggraceful degradation for a large class of programs. A relaxation lattice is a lattice ofspecifications parameterized by a set of constraints, where the stronger the set ofconstraints, the more restrictive the specification. While a program is able to satisfy itsstrongest set of constraints, it satisfies its preferred specification, but if changes to theenvironment force it to satisfy a weaker set, then it will permit additional weaklyconsistent computations which are undesired but tolerated. The use of relaxation latticesis illustrated by specifications for programs that tolerate (1) faults, such as site crashesand network partitions, (2) timing anomalies, such as attempting to read a value too soonafter it was written, (3) synchronization conflicts, such as choosing the oldest unlockeditem from a queue, and (4) security breaches, such as acquiring unauthorized capabilities.
A model of textual affect sensing using real-world knowledge
Authors: Hugo Liu, Henry Lieberman, Ted Selker
Venue: Proceedings of the 8th international conference on Intelligent user interfaces (2003)

This paper presents a novel way for assessing the affective qualities of natural language and a scenario for its use. Previous approaches to textual affect sensing have employed keyword spotting, lexical affinity, statistical methods, and hand-crafted models. This paper demonstrates a new approach, using large-scale real-world knowledge about the inherent affective nature of everyday situations (such as "getting into a car accident") to classify sentences into "basic" emotion categories. This commonsense approach has new robustness implications.Open Mind Commonsense was used as a real world corpus of 400,000 facts about the everyday world. Four linguistic models are combined for robustness as a society of commonsense-based affect recognition. These models cooperate and compete to classify the affect of text. Such a system that analyzes affective qualities sentence by sentence is of practical value when people want to evaluate the text they are writing. As such, the system is tested in an email writing application. The results suggest that the approach is robust enough to enable plausible affective text user interfaces.
A Hierarchical Test Methodology for Systems on Chip
Authors: Jin-Fu Li, Hsin-Jung Huang, Jeng-Bin Chen, Chih-Pin Su, Cheng-Wen Wu, Chuang Cheng, Shao-I Chen, Chi-Yi Hwang, Hsiao-Ping Lin
Venue: IEEE Micro (2002)

Integrating reusable cores from multiple sources is essential in system-on-a-chip design. The authors present a hierarchical methodology for testing these cores and the integrated system chip.
Mean flow in hexagonal convection: stability and nonlinear dynamics
Authors: Yuan-Nan Young, Hermann Riecke
Venue: Physica D (2002)

Weakly nonlinear hexagon convection patterns coupled to mean flow are investigated within the framework of coupled Ginzburg-Landau equations. The equations are in particular relevant for non-Boussinesq Rayleigh-Bénard convection at low Prandtl numbers. The mean flow is found to: (1) affect only one of the two long-wave phase modes of the hexagons, and (2) suppress the mixing between the two phase modes. As a consequence, for small Prandtl numbers the transverse and the longitudinal phase instability are expected to occur in sufficiently distinct parameter regimes that they can be studied separately. Through the formation of penta-hepta defects, they lead to different types of transient disordered states. The results for the dynamics of the penta-hepta defects shed light on the persistence of grain boundaries in such disordered states.
Specification, Planning, and Synthesis in a VHDL Design Environment
Authors: VIjay Nagasamy, Neerav Berry, Carlos Dangelo
Venue: IEEE Design Test (1992)

Silicon 1076, a very-high-speed integrated circuit hardware description language (VHDL) design environment developed for specifying, simulating, and synthesizing digital hardware, is described. The environment integrates software tools for architectural-level design space exploration and synthesis and RTL synthesis. Silicon 1076 supports a top-down design methodology, while making use of bottom-up design information such as area and delay of modules and interconnect and routing estimates. The flexible design environment allows the user to describe separate parts of the design at different abstraction levels and to perform mixed-level VHDL simulation and synthesis. With the synthesis tools, the user can perform high-level what-if analysis and planning by constraining and exploring portions of the design space.
Wrappers-a mechanism to support state-based authorisation in Web applications
Authors: M. S. Olivier, Ehud Gudes
Venue: Data Knowledge Engineering (2002)

The premises of this paper are (1) security is application dependent because application semantics directly influence proper protection; but (2) applications are generally too complex to be trusted to implement security as specified by the given security policy. These problems are aggravated if the application operates over time and space.This paper proposes the use of a simple program (a "wrapper") that has enough knowledge about a specific application's potential states and the actions that are permissible in each state. Using this knowledge, it is able to filter requests that should not reach an application at a given point.
Toward CAD-IP Reuse: A Web Bookshelf of Fundamental Algorithms
Authors: Andrew E. Caldwell, Igor L. Markov
Venue: IEEE Design Test (2002)

The free reuse of code and other types of CAD intellectual property can help EDA vendors, captive CAD organizations, and researchers address the design technology productivity gap. The Marco GSRC Bookshelf, a medium for CAD-IP reuse, is now operational and accessible to the general public over the Internet.
Knowledge-Based Approaches for Scheduling Problems: A Survey
Authors: S. J. Noronha, V. V. S. Sarma
Venue: IEEE Transactions on Knowledge and Data Engineering (1991)

Recent developments in artificial intelligence (AI) have led to the use of knowledge-based techniques for solving scheduling problems. The authors survey several existing intelligent planning and scheduling systems with the aim of providing a guide to the main AI techniques used. In view of the prevailing difference is usage of the terms planning and scheduling between AI and operations research (OR), a taxonomy of planning and scheduling problems is presented. The modeling of real world problems from closed deterministic worlds to complex real worlds is illustrated with a project scheduling example. Some of the more successful planning and scheduling systems are surveyed, and their features are highlighted. The AI approaches are consolidated into knowledge representation and problem solving in the project management context.
Built-In Self-Test of a CMOS ALU
Authors: E. Cerny, E. Aboulhamid, G. Bois, J. Cloutier
Venue: IEEE Design Test (1988)

A technique is proposed for implementing BIST (built-in self-test) in a CMOS arithmetic and logic unit (ALU). The approach covers single stuck-open faults and all functional faults that do not induce memory effects. The specific fault set covered by the test includes: (1) all single stuck-open faults on n and p transistors anywhere in the ALU (F1 faults); and (2) all functional faults that affect any single-bit slice of the (F2 faults), a functional fault being any fault that changes one combinational function into another. Functional faults in multiple slices are also detectable, as long as they do not generate identical responses in all even-numbered or odd-numbered ALU slices. With common techniques for test vector generation and response-verification, this BIST implementation provides higher fault coverage with only a small increase in surface area.
Very-High Radix Division with Prescaling and Selection by Rounding
Authors: M. D. Ercegovac, T. Lang, P. Montuschi
Venue: IEEE Transactions on Computers (1994)

A division algorithm in which the quotient-digit selection is performed by rounding the shifted residual in carry-save form is presented. To allow the use of this simple function, the divisor (and dividend) is prescaled to a range close to one. The implementation presented results in a fast iteration because of the use of carry-save forms and suitable recodings. The execution time is calculated and several convenient values of the radix are selected. Comparison with other dividers for radices 2/sup 9/ to 2/sup 18/ is performed using the same assumptions.
Lessons from Three Years of Inspection Data
Authors: Edward F. Weller
Venue: IEEE Software (1993)

The implementation of an inspection program as part of a standard development process for an operating system at Bull HN Information Systems Major Systems Division is reviewed. The methods used to collect and analyze the data and provide feedback to the development staff are described. The data are examined from the point of view of the entire organization and as they apply in individual case studies of particular project types.
Program and Verify Word-Line Voltage Regulator for Multilevel Flash Memories
Authors: Osama Khouri, Rino Micheloni, Giovanni Campardo, Guido Torelli
Venue: Analog Integrated Circuits and Signal Processing (2003)

This paper presents a word-line voltage generator for multilevel (ML) Flash memory programming. The required voltages are provided by a regulator supplied by an on-chip charge-pump voltage multiplier. A feedback loop including a digitally programmable resistive divider generates the staircase-shaped waveform needed for adequate ML programming accuracy as well as the read/verify voltage required for read and verify operations. A high-swing controlled-discharge circuit minimizes the settling time when switching from program to verify phases and vice versa. The same generator is used to provide the voltage required in read and in program mode, thus saving silicon area and minimizing current consumption. Experimental results of the proposed circuit integrated in a 4-level-cell 64-Mb NOR-type Flash memory are presented.
Codesign of Architectures for Automotive Powertrain Modules
Authors: Xiaobo Hu, Joseph G. D'Ambrosio, Brian T. Murray, Dah-Lain Tang
Venue: IEEE Micro (1994)

To guide design decisions in developing an optimized architecture for automotive powertrain modules, we relied upon analysis, a key to hardware-software codesign. Complicating such efforts are ongoing refinements to the underlying algorithms, ever stricter government standards, reusability demands, and late-arriving specifications for the controlled components. In our approach, configuration-level analysis lets us quickly and efficiently explore a large design space. Behavioral-level analysis validates decisions and optimizes hardware and software. Our codesign methodology extends to similar real-time embedded systems.
Split Weight Enumerators for the Preparata Codes with Applicationsto Designs
Authors: Iwan Duursma, Tor Helleseth, Chunming Rong, Kyeongcheol Yang
Venue: Designs, Codes and Cryptography (1999)

For quaternary Preparata and Kerdock codes of length N=2^m,m odd, we prove that the split complete weight enumerator for a coordinate partition into 3 and N-3 coordinates is independent of the chosen partition. The result implies that the words of a given complete weight in either a Preparata code or Kerdock code define a 3-design.
Agile Software Development: The Business of Innovation
Authors: Jim Highsmith, Alistair Cockburn
Venue: Computer (2001)

Agile development combines creative teamwork with an intense focus on effectiveness and maneuverability.
Comments on "A New Family of Cayley Graph Interconnection Networks of Constant Degree Four"
Authors: Guihai Chen, Francis C. M. Lau
Venue: IEEE Transactions on Parallel and Distributed Systems (1997)

Vadapalli and Srimani [2] have proposed a new family of Cayley graph interconnection networks of constant degree four. Our comments show that their proposed graph is not new but is the same as the wrap-around butterfly graph. The structural kinship of the proposed graph with the de Bruijn graph is also discussed.
Associativity-Based Routing for Ad Hoc Mobile Networks
Authors: Chai-Keong Toh
Venue: Wireless Personal Communications: An International Journal (1997)

This paper presents a new, simple and bandwidth-efficient distributed routing protocol to support mobile computing in a conference size ad-hoc mobile network environment. Unlike the conventional approaches such as link-state and distance-vector distributed routing algorithms, our protocol does not attempt to consistently maintain routing information in every node. In an ad-hoc mobile network where mobile hosts (MHs) are acting as routers and where routes are made inconsistent by MHs&lsquo; movement, we employ an associativity-based routing scheme where a route is selected based on nodes having associativity states that imply periods of stability. In this manner, the routes selected are likely to be long-lived and hence there is no need to restart frequently, resulting in higher attainable throughput. Route requests are broadcast on a per need basis. The association property also allows the integration of ad-hoc routing into a BS-oriented Wireless LAN (WLAN) environment, providing the fault tolerance in times of base stations (BSs) failures. To discover shorter routes and to shorten the route recovery time when the association property is violated, the localised-query and quick-abort mechanisms are respectively incorporated into the protocol. To further increase cell capacity and lower transmission power requirements, a dynamic cell size adjustment scheme is introduced. The protocol is free from loops, deadlock and packet duplicates and has scalable memory requirements. Simulation results obtained reveal that shorter and better routes can be discovered during route re-constructions.
Scheduling Semiconductor Wafer Production: An Expert System Implementation
Authors: Daryl V. Savell, Rafael A. Perez, Song W. Koh
Venue: IEEE Expert: Intelligent Systems and Their Applications (1989)

A flexible environment for the production of semiconductor wafers is described. This facility currently manufactures over 300 wafer products. Each product follows a different route through a series of discrete processing operations, more than 150 of which take place in the facility. An expert system approach to scheduling, which efficiently utilizes the processing equipment within each cell while meeting overall due dates of all wafer lots, is detailed. The results obtained with the expert system and its applicability are evaluated
Fault-tolerant routing with non-adaptive wormhole algorithms in mesh networks
Authors: Rajendra V. Boppana, Suresh Chalasani
Venue: Proceedings of the 1994 ACM/IEEE conference on Supercomputing (1994)

We present simple techniques to enhance the e-cube algorithm for fault-tolerant routing in mesh networks. These techniques are based on the concept of fault rings, which are formed using fault-free nodes and links around each fault region. We use fault rings to enhance the e-cube to route messages in the presence of rectangular block faults. We show that if fault rings do not overlap with one another--the sets of links in fault rings are pairwise disjoint, then two virtual channels per physical channel are sufficient to make the e-cube tolerant to any number of faulty blocks. For more complex cases such as overlapping fault rings and faults on network boundaries, three or four virtual channels are used. In all cases, the routing guarantees livelock and deadlock free delivery of each and every message injected into the network. Our simulation results for isolated faults indicate that the proposed method provides acceptable performance with as many as 10 percent faulty links.
Vectorization of a Generalized Procedure for Theorem Proving in Propositional Logic on Vector Computers
Authors: M. -Y. Fang, W. -T. Chen
Venue: IEEE Transactions on Knowledge and Data Engineering (1992)

Vectorization techniques for solving the theorem-proving problem in propositional logic on vector computers is presented. To take advantage of vector processing, the rules used in the deduction process are first generalized by considering more than one literal at a time. The soundness of the generalized rules is proved. The vectorized representation of the problem and algorithms based on the generalized rules is proposed. Experiments conducted on vector computers show that the vectorized procedure is effective.
An Efficient Heuristic for Permutation Packet Routing on Meshes with Low Buffer Requirements
Authors: F. Makedon, A. Symvonis
Venue: IEEE Transactions on Parallel and Distributed Systems (1993)

Even though exact algorithms exist for permutation routine of n/sup 2/ messages on an*n mesh of processors which require constant size queues, the constants are very largeand the algorithms very complicated to implement. A novel, simple heuristic for the above problem is presented. It uses constant and very small size queues (size=2). For all the simulations run on randomly generated data, the number of routing steps that is required by the algorithm is almost equal to the maximum distance a packet has to travel. A pathological case is demonstrated where the routing takes more than the optimal, and itis proved that the upper bound on the number of required steps is O(n/sup 2/).Furthermore, it is shown that the heuristic routes in optimal time inversion, transposition,and rotations, three special routing problems that appear very often in the design ofparallel algorithms.
Adapting, Correcting, and Perfecting Software Estimates: A Maintenance Metaphor
Authors: Tarek K. Abdel-Hamid
Venue: Computer (1993)

A hybrid continuous software estimation model supporting adaptive, corrective, and perfective estimation activities is described. The adaptive activity accommodates new system or user requirements or reflects new organizational realities. Corrective maintenance remedies an error detected in the software product, and perfective maintenance eliminates processing inefficiencies and enhances performance of the overall software system. An implementation using constructive cost model (Cocomo) and the system dynamics (SD) simulator is presented. Three examples are presented that demonstrate how the model can be used: before the project starts to adapt the Cocomo estimates to organizational realities, during software development to correct initial assumptions about sizing, and after project completion to perfect model estimates.
Display of Munsell color values, earthquakes, and other three- and four-parameter datasets in stereo 3D
Authors: Neil A. Wells
Venue: Computers Geosciences (2002)

A new version of the program 3D.BAS facilitates display of three- and four-parameter datasets, particularly earthquake distributions and Munsell color measurements, by using stereoscopic 3D scatterplots. With respect to earthquakes, hypocenters can be plotted on whole-earth spherical plots or on rectangular plots for specific regions. The program allows a series of earthquakes to be examined quake by quake, with coding of symbol shapes and/or colors for depths, magnitudes, time intervals, or individual identification. It also allows a variety of panning, zooming, slicing, rotation, projection, and stepping. It can handle datasets of 104 earthquakes, and can filter such a dataset for quakes below, between, or above specific depths or intensities, or within chosen distances on either side of an oblique line. With respect to Munsell colors, the program can plot the three constituent parameters (hue, lightness, and chroma) on a rectangular coordinate system that mimics the arrangement of a stack of pages of color chips, or on cylindrical and spherical coordinate systems (the Munsell "color cylinder" or "color sphere").
Centering small generalized polygons-projective pottery at work
Authors: Burkard Polster
Venue: Discrete Mathematics (2002)

The generalized triangle, quadrangle, and hexagons of order 2 are small point-line geometries that play a role in the theory of generalized polygons and buildings that is comparable to that of the Fano plane in the theory of projective planes. Virtually everybody working in discrete mathematics is familiar with the generalized triangle of order 2 aka the Fano plane, the smallest projective plane, PG(2,2), or the unique symmetric block design with parameters 2-(7, 3, 1), and its elementary representation as the geometrical configuration of an equilateral triangle together with its three medians and inscribed circle. The main purpose of this paper is to derive an elementary representation of the generalized hexagons of order 2 which extends naturally to a special representation of the projective space PG(5,2). Along the way, we also derive a similar representation of the generalized quadrangle of order 2 which turns out to be equivalent to the well-known representation of the quadrangle in terms of synthems and duads and which extends naturally to a representation of PG(3,2).
Game Theory and Decision Theory in Multi-Agent Systems
Authors: Simon Parsons, Michael Wooldridge
Venue: Autonomous Agents and Multi-Agent Systems (2002)

In the last few years, there has been increasing interest from the agent community in the use of techniques from decision theory and game theory. Our aims in this article are firstly to briefly summarize the key concepts of decision theory and game theory, secondly to discuss how these tools are being applied in agent systems research, and finally to introduce this special issue of Autonomous Agents and Multi-Agent Systems by reviewing the papers that appear.