ppxscal/embedding_network huggingface dataset:
New algorithms for min-cut replication in partitioned circuits
Authors: Hannah Honghua Yang, D. F. Wong
Venue: Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design (1995)

Abstract: Hwang and El Gamal (1992, 1995) formulated the min-cut replication problem, which is to determine min-cut replication sets for the components of a k-way partition such that the cut size of the partition is minimized after the replication. They gave an optimal algorithm for finding min-cut replication sets for a k-way partitioned digraph. However, their optimal min-cut replication algorithm does not guarantee min-cut replication sets of minimum sizes. Furthermore, their algorithm is not optimal for hypergraphs. In this paper, we optimally solve the min-area min-cut replication problem on digraphs, which is to find min-cut replication sets with the minimum sizes. More importantly, we give an optimal solution to the hypergraph min-area min-cut replication problem using a much smaller flow network model. We implemented our algorithms in a package called Hyper-MAMC, and interfaced Hyper-MAMC to the TAPIR package. On average, Hyper-MAMC produces 57.3% fewer cut nets and runs much faster than MO-Rep in the TAPIR package, on the same initial partitions of a set of MCNC Partition93 benchmark circuits.
Sparse Approximate Solutions to Linear Systems
Authors: B. K. Natarajan
Venue: SIAM Journal on Computing (1995)

The following problem is considered: given a matrix $A$ in ${\bf R}^{m \times n}$, ($m$ rows and $n$ columns), a vector $b$ in ${\bf R}^m$, and ${\bf \epsilon} > 0$, compute a vector $x$ satisfying $\| Ax - b \|_2 \leq {\bf \epsilon}$ if such exists, such that $x$ has the fewest number of non-zero entries over all such vectors. It is shown that the problem is NP-hard, but that the well-known greedy heuristic is good in that it computes a solution with at most $\left\lceil 18 \mbox{ Opt} ({\bf \epsilon}/2) \|{\bf A}^+\|^2_2 \ln(\|b\|_2/{\bf \epsilon}) \right\rceil$ non-zero entries, where $\mbox{Opt}({\bf \epsilon}/2)$ is the optimum number of nonzero entries at error ${\bf \epsilon}/2$, ${\bf A}$ is the matrix obtained by normalizing each column of $A$ with respect to the $L_2$ norm, and ${\bf A}^+$ is its pseudo-inverse.
Z-iteration: a simple method for throughput estimation in time-dependent multi-class systems
Authors: Ibrahim Matta, A. Udaya Shankar
Venue: Proceedings of the 1995 ACM SIGMETRICS joint international conference on Measurement and modeling of computer systems (1995)

Multiple-class multiple-resource (MCMR) systems, where each class of customers requires a particular set of resources, are common. These systems are often analyzed under steady-state conditions. We describe a simple method, referred to as Z-iteration, to estimate both transient and steady-state performances of such systems. The method makes use of results and techniques available from queueing theory, network analysis, dynamic flow theory, and numerical analysis. We show the generality of the Z-iteration by applying it to an ATM network, a parallel disk system, and a distributed batch system. Validations against discrete-event simulations show the accuracy and computational advantages of the Z-iteration.
Airdisks and airRAID (expanded extract): modeling and scheduling periodic wireless data broadcast
Authors: Ravi Jain, John Werth
Venue: ACM SIGARCH Computer Architecture News (1995)

A new generation of low-cost, low-power, and portable personal computer systems is emerging; sometimes these are referred to as palmtops or Personal Digital Assistants (PDAs). One of their key features is that they utilize wireless communication media, thus freeing the user from the constraints of wired or tethered communication. In fact, the wireless medium becomes a critical component of the I/O subsystem, allowing communication with fixed servers and other users. In particular, the broadcast nature of the wireless medium can be exploited to efficiently transmit information required by a large number of PDA users (e.g. stock quotes, sports updates, etc.), with software on the PDA being used to filter the information and present only the information of interest to the PDA user.We introduce a simple model, called the airdisk, for modeling the access of data transmitted periodically over wireless media as being analogous to the access of data from a standard magnetic disk. We consider several issues related to airdisks, such as their mean rotational latency under certain assumptions. The problem of scheduling the order in which data items are broadcast is analogous to that of determining how data should be laid out on the disk. Two problems of laying out data so as to minimize read time, given information about which data items are of most interest to the clients, are defined; both are shown to be NP-complete. We discuss ways in which the information about which items are of interest to clients can be obtained. Finally we consider how to increase the performance and storage capacity of airdisks, using the magnetic disk analogy as a guide. We suggest using multiple-track airdisks or borrowing the idea of Redundant Arrays of Inexpensive Disks (RAID) which is used for magnetic disks; for the wireless data broadcast environment we call the latter approach airRAID.
Instruction prefetching of systems codes with layout optimized for reduced cache misses
Authors: Chun Xia, Josep Torrellas
Venue: Proceedings of the 23rd annual international symposium on Computer architecture (1996)

High-performing on-chip instruction caches are crucial to keep fast processors busy. Unfortunately, while on-chip caches are usually successful at intercepting instruction fetches in loop-intensive engineering codes, they are less able to do so in large systems codes. To improve the performance of the latter codes, the compiler can be used to lay out the code in memory for reduced cache conflicts. Interestingly, such an operation leaves the code in a state that can be exploited by a new type of instruction prefetching: guarded sequential prefetching.The idea is that the compiler leaves hints in the code as to how the code was laid out. Then, at run time, the prefetching hardware detects these hints and uses them to prefetch more effectively. This scheme can be implemented very cheaply: one bit encoded in control transfer instructions and a prefetch module that requires minor extensions to existing next-line sequential prefetchers. Furthermore, the scheme can be turned off and on at run time with the toggling of a bit in the TLB. The scheme is evaluated with simulations using complete traces from a 4-processor machine. Overall, for 16-Kbyte primary instruction caches, guarded sequential prefetching removes, on average, 66% of the instruction misses remaining in an operating system with an optimized layout, speeding up the operating system by 10%. Moreover, the scheme is more cost-effective and robust than existing sequential prefetching techniques.
Reasoning about temporal relations: a maximal tractable subclass of Allen's interval algebra
Authors: Bernhard Nebel, Hans-Jürgen Bürckert
Venue: Journal of the ACM (JACM) (1995)

We introduce a new subclass of Allen's interval algebra we call &ldquo;ORD-Horn subclass,&rdquo; which is a strict superset of the &ldquo;pointisable subclass.&rdquo; We prove that reasoning in the ORD-Horn subclass is a polynomial-time problem and show that the path-consistency method is sufficient for deciding satisfiability. Further, using an extensive machine-generated case analysis, we show that the ORD-Horn subclass is a maximal tractable subclass of the full algebra (assuming P &ne; NP). In fact, it is the unique greatest tractable subclass amongst the subclasses that contain all basic relations.
Translating default logic into standard autoepistemic logic
Authors: Georg Gottlob
Venue: Journal of the ACM (JACM) (1995)

Since Konolige's translation of default logic into strongly grounded autoepistemic logic, several other variants of Moore's original autoepistemic logic that embody default logic have been studied. All these logics differ significantly from Moore's autoepistemic logic (standard AEL) in that expansions are subject to additional groundedness-conditions. Hence, the question naturally arises whether default logic can be translated into standard AEL at all. We show that a modular translation is not possible. However, we are able to construct a faithful polynomial-time translation from default logic into standard AEL, which is nonmodular. Our translation exploits the self-referentiality of AEL. It uses as an important intermediate step an embedding of Marek's and Truszczyn&acute;ski's nonmonotonic logic N into standard AEL. It follows from our results that the expressive power of standard AEL is strictly greater than that of default logic.
Cognition and software development
Authors: Webb Stacy
Venue: Communications of the ACM (1995)

Not long ago, programmers controlled computers by arranging wires on a control panel built into the side of a large floor-standing machine. Today palm-sized pointing devices are used to drag and drop visual images on machines smaller than a notebook. Dramatic differences like these make it easy to forget that software development still revolves around the needs of the computer at the expense of the needs of developers and end users.
Software pipelining
Authors: Vicki H. Allan, Reese B. Jones, Randall M. Lee, Stephen J. Allan
Venue: ACM Computing Surveys (CSUR) (1995)

Utilizing parallelism at the instruction level is an important way to improve performance. Because the time spent in loop execution dominates total execution time, a large body of optimizations focuses on decreasing the time to execute each iteration. Software pipelining is a technique that reforms the loop so that a faster execution rate is realized. Iterations are executed in overlapped fashion to increase parallelism.Let {ABC}n represent a loop containing operations A, B, C that is executed n times. Although the operations of a single iteration can be parallelized, more parallelism may be achieved if the entire loop is considered rather than a single iteration. The software pipelining transformation utilizes the fact that a loop {ABC}n is equivalent to A{BCA}n&minus;1BC. Although the operations contained in the loop do not change, the operations are from different iterations of the original loop.Various algorithms for software pipelining exist. A comparison of the alternative methods for software pipelining is presented. The relationships between the methods are explored and possibilities for improvement highlighted.
Informing memory operations: providing memory performance feedback in modern processors
Authors: Mark Horowitz, Margaret Martonosi, Todd C. Mowry, Michael D. Smith
Venue: Proceedings of the 23rd annual international symposium on Computer architecture (1996)

Memory latency is an important bottleneck in system performance that cannot be adequately solved by hardware alone. Several promising software techniques have been shown to address this problem successfully in specific situations. However, the generality of these software approaches has been limited because current architectures do not provide a fine-grained, low-overhead mechanism for observing and reacting to memory behavior directly. To fill this need, we propose a new class of memory operations called informing memory operations, which essentially consist of a memory operation combined (either implicitly or explicitly) with a conditional branch-and-link operation that is taken only if the reference suffers a cache miss. We describe two different implementations of informing memory operations---one based on a cache-outcome condition code and another based on low-overhead traps---and find that modern in-order-issue and out-of-order-issue superscalar processors already contain the bulk of the necessary hardware support. We describe how a number of software-based memory optimizations can exploit informing memory operations to enhance performance, and look at cache coherence with fine-grained access control as a case study. Our performance results demonstrate that the runtime overhead of invoking the informing mechanism on the Alpha 21164 and MIPS R10000 processors is generally small enough to provide considerable flexibility to hardware and software designers, and that the cache coherence application has improved performance compared to other current solutions. We believe that the inclusion of informing memory operations in future processors may spur even more innovative performance optimizations.
A structured approach for the definition of the semantics of active databases
Authors: Piero Fraternali, Letizia Tanca
Venue: ACM Transactions on Database Systems (TODS) (1995)

Active DBMSs couple database technology with rule-based programming to achieve the capability of reaction to database (and possibly external) stimuli, called events. The reactive capabilities of active databases are useful for a wide spectrum of applications, including security, view materialization, integrity checking and enforcement, or heterogeneous database integration, which makes this technology very promising for the near future. An active database system consists of a (passive) database and a set of active rules; the most popular form of active rule is the so-called event-condition-action (ECA) rule, which specifies an action to be executed upon the occurrence of one or more events, provided that a condition holds. Several active database systems and prototypes have been designed and partially or completely implemented. Unfortunately, they have been designed in a totally independent way, without the support of a common theory dictating the semantics of ECA rules, and thus often show different behaviors for rules with a similar form. In this article we consider a number of different possible options in the behavior of an active DBMS, based on a broad analysis of some of the best known implemented systems and prototypes. We encode these options in a user-readable form, called Extended ECA. A rule from any existing system can be rewritten in this formalism making all the semantic choices apparent. Then an EECA rule can be automatically translated into an internal (less readable) format, based on a logical style, which is called core format: the execution semantics of core rules is specified as the fixpoint of a simple transformation involving core rules. As an important premise to this research, a semantics for database updates and transactions has also been established, with respect to a notion of state that comprises both data and events. The article also presents an extensive bibliography on the subject of active databases.
How to model automated guided vehicle systems using ProModel for Windows
Authors: Merriel C. Dewsnup, Eugene Bollenbach
Venue: Proceedings of the 27th conference on Winter simulation (1995)

The ready availability of personal computers using the Windows Graphical User Interface combined with the ease of use of the ProModel for Windows simulation software and the need to demonstrate feasibility of proposed systems has resulted in a broad new group of modeling users who in the past had to wait for their ideas to be modeled by simulation experts. Previously the high cost of developing models on expensive hardware and difficult to learn software prevented many projects from being simulated. These projects did not benefit from the advantages of testing design ideas prior to implementation. This paper discusses the use of ProModel for Windows for modeling Automated Guided Vehicle Systems. The methodology and considerations needed to produce results with minimal effort are presented. The example presented here represents an actual system designed by Caterpillar Advanced Vehicle Systems.
Report on the 1995 international workshop on temporal databases
Authors: Arie Segev, Christian S. Jensen, Richard Thomas Snodgrass
Venue: ACM SIGMOD Record (1995)

This paper provides an overview of the 1995 International Workshop on Temporal Databases. It summarizes the technical papers and related discussions, and three panels: &ldquo;Wither TSQL3?&rdquo;, &ldquo;Temporal Data Management in Financial Applications,&rdquo; and &ldquo;Temporal Data Management Infrastructure Beyond.&rdquo;
Truth in SPEC benchmarks
Authors: Nikki Mirghafori, Margret Jacoby, David Patterson
Venue: ACM SIGARCH Computer Architecture News (1995)

The System Performance Evaluation Cooperative (SPEC) benchmarks are a set of integer and floating-point programs that are intended to be &ldquo;effective and fair in comparing the performance of high performance computing systems&rdquo;. SPEC ratings are often quoted in company advertising and have been trusted as the de facto measure of comparison for computer systems. Recently, there has been some concern regarding the fairness and the value of these benchmarks for comparing computer systems. In this paper we investigate the following two questions regarding the SPEC92 benchmark suite: 1) How sensitive are the SPEC ratings to various tunings? 2) How reproducible are the published results? For six vendors, we compare the published SPECpeak and SPECbase ratings, and observe an 11% average improvement in the SPECpeak ratings due to changes in the compiler flags alone. In our own attempt to reproduce the published SPEC ratings, we came across various &ldquo;explicit&rdquo; and &ldquo;hidden&rdquo; tuning parameters that we consider unrealistic. We suggest a new unit called SPECsimple that requires using only the -O compiler optimization flag, shared libraries, and standard system configuration. SPECsimple is designed to better match the performance experienced by a typical user. Our measured SPECsimples are 65-86% of the advertised SPECpeak performance. We conclude this paper by citing cases compiler optimizations specifically designed for SPEC programs, in which performance decreases drastically or the computed results are incorrect if the compiled program does not exactly match the SPEC benchmark program. These findings show that the fairness and value of the popular SPEC benchmarks are questionable.
Testing and Debugging Distributed Programs Using Global Predicates
Authors: S. Venkatesan, Brhama Dathan
Venue: IEEE Transactions on Software Engineering (1995)

Testing and debugging programs are more involved in distributed systems than in uniprocessor systems because of the presence of the communication medium and the inherent concurrency. Past research has established that predicate testing is an approach that can alleviate some of the problems in this area. However, checking whether a general predicate is true in a particular distributed execution appears to be a computationally hard problem. This paper considers a class of predicates called conjunctive form predicates (CFP) that is quite useful in distributed program development, but can be tested efficiently. We develop fully-distributed algorithms to test CFP's, prove that these algorithms are correct, and analyze them for their message complexity. The analysis shows that our techniques incur a fairly low overhead on the distributed system.
A Fault-Tolerant Tree Communication Scheme for Hypercube Systems
Authors: Yuh-Rong Leu, Sy-Yen Kuo
Venue: IEEE Transactions on Computers (1996)

The tree communication scheme was shown to be very efficient for global operations on data residing in the processors of a hypercube with time complexity of O(log2N), where N is the number of processors. This communication scheme is very useful for many parallel algorithms on hypercube multiprocessors. If a problem can be divided into independent subproblems, each subproblem can first be solved by one of the processors. Then, the tree communication scheme is invoked to merge the subresults into the final results. All the algorithms for problems with this property can benefit from the tree communication scheme. We propose a more general and efficient tree communication scheme in this paper. In addition, we also propose fault-tolerant algorithms for the tree communication scheme, by exploiting the unique properties of the tree communication scheme. The computation and communication slowdown is small (
Combined discrete-continuous simulation models in ProModel for Windows
Authors: J. Frederick Klingener
Venue: Proceedings of the 27th conference on Winter simulation (1995)

Although ProModel for Windows is primarily intended as a discrete event simulator aimed at part manufacturing systems, it supports construction of models that combine continuously varying processes that interact with discrete events. This paper proposes a general approach to modeling of combined discrete-continuous systems, describes the details of a particular example problem, and discusses some modeling issues.
Symmetric Matrices Representable by Weighted Trees Over a Cancellative Abelian Monoid
Authors: Hans-Jurgen Bandelt, Michael Anthony Steel
Venue: SIAM Journal on Discrete Mathematics (1995)

The classical result that characterizes metrics induced by paths in a labeled tree having positive real edge weights is generalized to allow the edge weights to take values in any cancellative abelian monoid satisfying the additional requirement that $x + x = y + y$ implies $x = y$. This includes the case of arbitrary real-valued edge weights, which applies to distance-hereditary graphs, thus yielding (unique) weighted tree representations for the latter.
Use of Adaptive Networks to Define Highly Predictable Protein Secondary&ndash;Structure Classes
Authors: Alan S. Lapedes, Evan W. Steeg, Robert M. Farber
Venue: Machine Learning (1995)

We present an adaptive, neural network method that determines new classes of protein secondary structure that are significantly more predictable from local amino&ndash;acid sequence than conventional classifications. Accurate prediction of the conventional secondary&ndash;structure classes, alpha-helix, beta-strand, and coil, from primary sequence has long been an important problem in computational molecular biology, with many ramifications, including multiple&ndash;sequence alignment, prediction of functionally important regions of proteins, and prediction of tertiary structure from primary sequence. The algorithm presented here uses adaptive networks to simultaneously examine both sequence and structure data, as available from, for example, the Brookhaven Protein Database, and to determine new secondary&ndash;structure classes that can be predicted from sequence with high accuracy. These new classes have both similarities to, and differences from, conventional secondary&ndash;structure classes. They represent a new, nontrivial classification of protein secondary structure that is predictable from primary sequence.
On the Learnability of Disjunctive Normal Form Formulas
Authors: Howard Aizenstein, Leonard Pitt
Venue: Machine Learning (1995)

We present two related results about the learnability of disjunctive normal form (DNF) formulas. First we show that a common approach for learning arbitrary DNF formulas requires exponential time. We then contrast this with a polynomial time algorithm for learning &ldquo;most&rdquo; (rather than all) DNF formulas. A natural approach for learning boolean functions involves greedily collecting the prime implicants of the hidden function. In a seminal paper of learning theory, Valiant demonstrated the efficacy of this approach for learning monotone DNF, and suggested this approach for learning DNF. Here we show that no algorithm using such an approach can learn DNF in polynomial time. We show this by constructing a counterexample DNF formula which would force such an algorithm to take exponential time. This counterexample seems to capture much of what makes DNF hard to learn, and thus is useful to consider when evaluating the run-time of a proposed DNF learning algorithm. This hardness result, as well as other hardness results for learning DNF, relies on the construction of particular hard-to-learn formulas, formulas that appear to be relatively rare. This raises the question of whether most DNF formulas are learnable. For certain natural definitions of &ldquo;most DNF formulas,&rdquo; we answer this question affirmatively.