ppxscal/embedding_network huggingface dataset:
Optimizing Power in ASIC Behavioral Synthesis
Authors: Raul San Martin, John P. Knight
Venue: IEEE Design Test (1996)

This article provides a tutorial survey of architectures of commercially available high-capacity field-programmable devices (FPDs), and gives a summary of recent research results in the field. In the survey section, we first define the relevant terminology in the field and then describe the recent evolution of FPDs. The three main categories of FPDs are delineated: Simple PLDs (SPLDs), Complex PLDs (CPLDs) and Field-Programmable Gate Arrays (FPGAs). We then give details of the architectures of all of the most important commercially available chips. The second part of the article gives an overview of the most important research results on FPD architecture over the past six years, and provides suggestions as to features that may be included in future architectures.
Challenges in power-ground integrity
Authors: Shen Lin, Norman Chang
Venue: Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design (2001)

With the advance of semiconductor manufacturing, EDA, and VLSI design technologies, circuits with increasingly higher speed are being integrated at an increasingly higher density. This trend causes correspondingly larger voltage fluctuations in the on-chip power distribution network due to IR-drop, L di/dt noise, or LC resonance. Therefore, Power-Ground integrity becomes a serious challenge in designing future high-performance circuits. In this paper, we will introduce Power-Ground integrity, addressing its importance, verification methodology, and problem solution.
A Codesign Approach for Safety-Critical Automotive Applications
Authors: Reinhard von Hanxleden, Ali Botorabi, Slawomir Kupczyk
Venue: IEEE Micro (1998)

Embedded systems assume increasing responsibilities in safety-critical automotive applications. For this class of applications, we have adopted a co-design approach based on successive validation phases. The first and most important design phase operates directly on an executable system specification, with a particular focus on fault modeling and robustness criteria, such as liveness and determinism. The second phase synthesizes subsystems into independent software processes that interact asynchronously with each other; the third phase results in a hardware/software prototype, for example a combination of FPGA and Microcontroller. We have applied this approach to the design of a bus-based airbag system.
Reliability of a Class of Multistage Interconnection Networks
Authors: X. Cheng, O. C. Ibe
Venue: IEEE Transactions on Parallel and Distributed Systems (1992)

The reliability of extra-stage interconnection networks is discussed. Three types of reliability are analyzed: terminal reliability, which is the probability that at least one fault-free path exists between a given input-output pair: network reliability, which is the probability that at least one fault-free path exists between every input-output pair; and broadcast reliability, which is the probability that at least one fault-free path exists between a given input and all outputs. A recursive expression for the broadcast reliability is obtained. Tight bounds are derived for the network reliability. The numerical results indicate that for practical networks (i.e. when network reliability is at least 0.5) the difference between the upper bound and the lower bound is no more than 2% of the lower bound.
Lagrange interpolation for the disk algebra: the worst case
Authors: Gerd Herzog
Venue: Journal of Approximation Theory (2002)

We consider Lagrange interpolation polynomials for functions in the disk algebra with nodes on the boundary of the unit disk. In case that the closure of the set of nodes does not cover the boundary of the unit disk we prove that there exists a residual set of functions in the disk algebra, such that the Lagrange interpolation polynomials of each of these functions form a dense subset of the space of all holomorphic functions defined on the unit disk.
Enhanced Reduced Pin-Count Test for Full-Scan Design
Authors: Harald Vranken, Tom Waayers, Hervé Fleury, David Lelouvier
Venue: Journal of Electronic Testing: Theory and Applications (2002)

This paper presents enhanced reduced pin-count test (E-RPCT) for low-cost test. E-RPCT is an extension of traditional RPCT for circuits in which a large number of digital IC pins is multiplexed for scan. The basic concept of E-RPCT is to provide access to the internal scan chains via an IEEE 1149.1 compatible boundary-scan architecture, instead of direct access via the IC pins. The boundary-scan chain performs serial/parallel conversion of test data. E-RPCT also provides I/O wrap to test non-contacted pins. The paper presents E-RPCT for full-scan design, as well as for full-scan core-based design.
Collective Intentions and the Maintenance of Social Practices
Authors: Wolfgang Balzer, Raimo Tuomela
Venue: Autonomous Agents and Multi-Agent Systems (2003)

This paper studies social practices and the dynamics of their maintenance in precise mathematical and logical terms. Roughly, social practices (such shaking hands, going regularly to sauna, eating a certain kind of food at Easter, etc.) are recurrent collective activities based on collective attitudes (&ldquo;shared we-attitudes&rdquo;), and the central kind of social practice under study here, is one based on collective intention. Social practices are the building blocks of human societies, and also of artificial ones. In this paper, we present a mathematical model representing the dynamics of social practices, and some properties of the process are subjected to detailed mathematical study.
GF(2m) Multiplication and Division Over the Dual Basis
Authors: Sebastian T. J. Fenn, Mohammed Benaissa, David Taylor
Venue: IEEE Transactions on Computers (1996)

In this paper an algorithm for GF(2m) multiplication/division is presented and a new, more generalized definition of duality is proposed. From these the bit-serial Berlekamp multiplier is derived and shown to be a specific case of a more general class of multipliers. Furthermore, it is shown that hardware efficient, bit-parallel dual basis multipliers can also be designed. These multipliers have a regular structure, are easily extended to different GF(2m) and hence suitable for VLSI implementations. As in the bit-serial case these bit-parallel multipliers can also be hardwired to carry out constant multiplication. These constant multipliers have reduced hardware requirements and are also simple to design. In addition, the multiplication/division algorithm also allows a bit-serial systolic finite field divider to be designed. This divider is modular, independent of the defining irreducible polynomial for the field, easily expanded to different GF(2m) and its longest delay path is independent of m.
Guest Editor's Introduction: Wearable Information Devices
Authors: Alex (Sandy) Pentland
Venue: IEEE Micro (2001)

There is an important distinction between wearable devices and those that are merely portable, the classic example being the pocket watch and wristwatch. The difference is simple: You have to pull out the pocket watch and open it to see the time,while the wristwatch enables you to see the time instantly, even while working with both hands. The ACM Portal is published by the Association for Computing Machinery. Copyright © 2010 ACM, Inc. Terms of Usage Privacy Policy Code of Ethics Contact Us Useful downloads: Adobe Acrobat QuickTime Windows Media Player Real Player
Leveraging Inconsistency in Software Development
Authors: Bashar Nuseibeh, Steve Easterbrook, Alessandra Russo
Venue: Computer (2000)

Software engineers make use of many descriptions, including analysis models, specifications, designs, program code, user guides, test plans, change requests, style guides, schedules, and process models. But since different developers construct and update these descriptions at various times during development, maintaining consistency among descriptions presents several problems.Descriptions tend to vary considerably. Individual descriptions can be illformed or self-contradictory and frequently evolve throughout the life cycle at different rates. Also, checking the consistency of a large, arbitrary set of descriptions is computationally expensive.The authors assert that maintaining consistency at all times is counterproductive. In many cases, it may be desirable to tolerate or even encourage inconsistency to facilitate distributed team-work and prevent premature commitment to design decisions. They advocate using inconsistency to highlight problem areas, using it as a tool to improve the development team's shared understanding, direct the process of requirements elicitation, and assist with verification and validation.
Concurrent Engineering in Product Development
Authors: R. A. Sprague, K. J. Singh, R. T. Wood
Venue: IEEE Design Test (1991)

Concurrent engineering, an integrated design approach that considers, from the outset, all elements of the product life cycle from conception through disposal, including quality, cost, schedule, and user requirements, is examined. A description is given of the US Defense Advanced Research Projects Agency DICE program, which is aimed at promoting the practice and acceptance of concurrent engineering in US industry. It is shown how the growing complexity of organizations and projects is defeating the sequential product-development process and how concurrent engineering, which encourages information sharing among all functions within a product's life cycle, offers tools that help deal with this complexity, resulting in products that get to market faster and cost less to develop.
Dynamic- and Static-priority Scheduling of Recurring Real-time Tasks
Authors: Sanjoy K. Baruah
Venue: Real-Time Systems (2003)

The recurring real-time task model for hard-real-time task is studied from a feasibility-analysis perspective. This model generalizes earlier models such as the sporadic task model and the generalized multiframe task model. Algorithms are presented for the static-priority and dynamic-priority feasibility-analysis of systems of independent recurring real-time tasks in a preemptive uniprocessor environment.
Semiblind space-time decoding in wireless communications: a maximum likelihood approach
Authors: Joaquín Míguez, Luis Castedo
Venue: Signal Processing (2002)

It has been recently shown that deploying multiple transmitting and receiving antennae can substantially improve the capacity of multipath wireless channels if the rich time-scattering is properly exploited. Space-time coding (STC) is a novel proposal that combines channel coding techniques suitable for multiple transmitting elements with signal processing algorithms that exploit the spatial and temporal diversity at the receiver. In this paper, we focus on the signal processing perspective and propose a novel space-time semiblind decoding scheme that performs maximum likelihood (ML) based channel estimation and data detection. The multiple input multiple output (MIMO) time-scattering channel is estimated using a block iterative expectation-maximization (EM) algorithm that fully exploits the statistical features of the transmitted signal together with the knowledge of a small number of transmitted symbols, hence the term semiblind. Data detection is efficiently carried out using the Viterbi algorithm. In order to reduce the computational load of the receiver, a modification of the EM algorithm with a potentially lower complexity is also suggested. Computer simulations show that the proposed semiblind decoder clearly outperforms conventional receivers that estimate the channel parameters exclusively from the a priori known transmitted symbols.
Extending Datalog with Declarative Updates
Authors: Mengchi Liu
Venue: Journal of Intelligent Information Systems (2003)

The semantics of static deductive databases is well understood based on the work in logic programming. In the past decade, various methods to incorporate update constructs into logic programming and deductive databases have been proposed. However, there is still no consensus about the appropriate treatment of dynamic behavior in deductive databases. In this paper, we propose a language called DatalogU, which is a minimal but powerful extension of Datalog with updates to base relations. DatalogU allows the user to program set-oriented complex database transactions with concurrent, disjunctive and sequential update operations in a simple and direct way. It has a simple and intuitive declarative semantics that naturally accounts for set-oriented updates in deductive databases.
Optimal Design and Sequential Analysis of VLSI Testing Strategy
Authors: P. S. Yu, C. M. Krishna, Y.-H. Lee
Venue: IEEE Transactions on Computers (1988)

A method for determining the optimal testing period and measuring the production yield is discussed. With the increased complexity of VLSI circuits, testing has become more costly and time-consuming. The design of a testing strategy, which is specified by the testing period based on the coverage function of the testing algorithm, involves trading off the cost of testing and the penalty of passing a bad chip as good. The optimal testing period is first derived, assuming the production yield is known. Since the yield may not be known a priori, an optimal sequential testing strategy which estimates the yield based on ongoing testing results, which in turn determines the optimal testing period, is developed next. Finally, the optimal sequential testing strategy for batches in which N chips are tested simultaneously is presented. The results are of use whether the yield stays constant or varies from one manufacturing run to another.
An Optimization Algorithm for Production Systems
Authors: T. Ishida
Venue: IEEE Transactions on Knowledge and Data Engineering (1994)

As the scale of rule-based expert systems increases, the efficiency of production systems becomes a pressing concern. Recently developed production systems thus enable users to specify an appropriate ordering or clustering of join operations. Various efficiency heuristics have been introduced to optimize production rules manually. However, since the heuristics often conflict With each other, users have to proceed by trial and error. The problem addressed in this paper is how to automatically determine efficient join structures for production system programs. Our algorithm does not directly apply efficiency heuristics to programs, but rather enumerates possible join structures under various constraints and selects the best one. For this purpose, the cost model for production systems is introduced to estimate the run-time cost of join operations. Evaluation results demonstrate that the proposed algorithm can generate programs that are as efficient as those obtained by manual optimization, and thus can reduce the burden of manual optimization.
An Instance-Weighting Method to Induce Cost-Sensitive Trees
Authors: K. M. Ting
Venue: IEEE Transactions on Knowledge and Data Engineering (2002)

We introduce an instance-weighting method to induce cost-sensitive trees. It is a generalization of the standard tree induction process where only the initial instance weights determine the type of tree to be induced¿minimum error trees or minimum high cost error trees. We demonstrate that it can be easily adapted to an existing tree learning algorithm. Previous research provides insufficient evidence to support the idea that the greedy divide-and-conquer algorithm can effectively induce a truly cost-sensitive tree directly from the training data. We provide this empirical evidence in this paper. The algorithm incorporating the instance-weighting method is found to be better than the original algorithm in terms of total misclassification costs, the number of high cost errors, and tree size in two-class data sets. The instance-weighting method is simpler and more effective in implementation than a previous method based on altered priors.
System-level power/performance analysis of portable multimedia systems communicating over wireless channels
Authors: Radu Marculescu, Amit Nandi, Luciano Lavagno, Alberto Sangiovanni-Vincentelli
Venue: Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design (2001)

This paper presents a new methodology for system-level power and performance analysis of wireless multimedia systems. More precisely, we introduce an analytical approach based on concurrent processes modeled as Stochastic Automata Networks (SANs) that can be effectively used to integrate power and performance metrics in system-level design. We show that 1) under various input traces and wireless channel conditions, the average-case behavior of a multimedia system consisting of a video encoder/decoder pair is characterized by very different probability distributions and power consumption values and 2) in order to identify the best trade-off between power and performance figures, one must take into consideration the entire environment (i.e., encoder, decoder, and channel) for which the system is being designed. Compared to using simulation, our analytical technique reduces the time needed to find the steady-state behavior by orders of magnitude, with some limited loss in accuracy compared to the exact solution. We illustrate the potential of our methodology using the MPEG-2 video as the driver application.
Message Complexity of the Tree Quorum Algorithm
Authors: Shyan-Ming Yuan, Her-Kun Chang
Venue: IEEE Transactions on Parallel and Distributed Systems (1995)

The tree quorum algorithm (TQA) uses a tree structure to generate intersecting (tree) quorums for distributed mutual exclusion. This paper analyzes the number of messages required to acquire a quorum in TQA. Let i be the depth of the complete binary tree used in TQA, and let Mi be the number of messages required to acquire a quorum or to determine that no quorum is accessible. We discuss Mi as a function of i and p, where $p\left({1\over 2}
An Algorithm for the Efficient Utilization of Bandwidth in the Slotted Ring
Authors: A. E. Kamal
Venue: IEEE Transactions on Computers (1992)

The slotted ring local area network is very efficient under light load, but suffers from severe performance degradations as the load increases, especially if message sizes are highly variable. An algorithm is presented, in the form of a medium access protocol, to allow for the efficient utilization of the bandwidth of the slotted ring. The protocol is based on the release of slots by destination stations of every slot, except for the first and last slots of a message transmission. This means that station latencies do not have to be increased. As a direct consequence of this property, the source and station identification do not have to be included in every slot, therefore reducing the message overhead. The algorithm results in an improved performance over the entire workload range, and under most workload conditions, therefore illustrating how far the performance of the slotted ring can go.
On the Conservation and Convergence to Weak Solutions of Global Schemes
Authors: Mark H. Carpenter, David Gottlieb, Chi-Wang Shu
Venue: Journal of Scientific Computing (2003)

In this paper we discuss the issue of conservation and convergence to weak solutions of several global schemes, including the commonly used compact schemes and spectral collocation schemes, for solving hyperbolic conservation laws. It is shown that such schemes, if convergent boundedly almost everywhere, will converge to weak solutions. The results are extensions of the classical Lax&ndash;Wendroff theorem concerning conservative schemes.
A New Conference Network for Group Communication
Authors: Yuanyuan Yang
Venue: IEEE Transactions on Computers (2002)

A conference refers to a group of members in a network who communicate with each other within the group. In this paper, we propose a novel design for a conference network which supports multiple disjoint conferences. The major component of the network is a multistage network composed of switch modules with fan-in and fan-out capability. A fast self-routing algorithm is developed for setting up routing paths in the conference network. For an \big. n \times n\bigr. conference network we design, the hardware cost is \big. O(n\log n)\bigr. and the routing time and communication delay vary from \big. O(1)\bigr. to \big. O(\log n)\bigr., depending on where the conference is allocated in the network. As can be seen, the new conference network is superior to existing designs in terms of hardware cost, routing time, and communication delay. The conference network proposed is rearrangeably nonblocking in general and is strictly nonblocking under some conference service policy. It can be used in applications that require efficient or real-time group communication.
Specializations of MacMahon symmetric functions and the polynomial algebra
Authors: Mercedes H. Rosas
Venue: Discrete Mathematics (2002)

A MacMahon symmetric function is a formal power series in a finite number of alphabets that is invariant under the diagonal action of the symmetric group. We use a combinatorial construction of the different bases of the vector space of MacMahon symmetric functions found by the author to obtain their image under the principal specialization: the powers, rising and falling factorials. Then, we compute the connection coefficients of the different polynomial bases in a combinatorial way.
Algebraic and Spectral Properties of General Toeplitz Matrices
Authors: A. Bultheel, P. Carrette
Venue: SIAM Journal on Control and Optimization (2002)

We consider problems related to the generalization of the classical Fourier basis to a basis of rational functions with prescribed poles outside the unit disk. We give some generalizations about the convergence and estimation of the Fourier coefficients with respect to this generalized basis. We also consider a rational generalization of the classical Toeplitz matrices and consider the asymptotic distribution of their spectrum. These bases and general Toeplitz matrices were considered by Ninness et al. in the context of least-squares system estimation where the prescribed poles allow to incorporate a priori knowledge into the system dynamics of the model.
A Knowledge-Based Fatal Incident Decision Model
Authors: S. Manivannan, S. Guthrie
Venue: IEEE Transactions on Knowledge and Data Engineering (1994)

A methodology for determining remains identification (ID) following a mass disaster is presented. The solution methodology is domain-independent and capable of addressing a wide range of assignment problems. A knowledge-based fatal incident decision model (FINDM) for providing a decision support to forensic scientists involved in the skeletal ID process is discussed. A mathematical framework for FINDM is developed that integrates a knowledge base with a network flow algorithm for resolving conflicts during the ID process. The FINDM framework has been implemented can an IBM PC and includes an observation advisor, an assignment advisor, and a conflict resolution module. Knowledge acquisition and representation issues are discussed, along with a numerical example and results. With respect to the remains ID problem, the FINDM approach shifts major efforts in resolving the problem from that of establishing a method of assignment to that of controlling the quality of data collected, improving domain knowledge, and analyzing conflicts.