ppxscal/embedding_network huggingface dataset:
Stabilization of multi-machine power system with facts equipment applying fuzzy control
Authors: Tomonobu Senjyu, Marta Molinas, Takashi Shiroma, Katsumi Uezato
Venue: Journal of Intelligent Fuzzy Systems: Applications in Engineering and Technology (1998)

This article presents an alternative application of fuzzy control to determine the control signal of Variable Series Capacitor (VSrC) for improving power system stability. VSrC is one of Flexible A.C. Transmission System (FACTS) equipment and has the ability to control the power flow directly by adjusting the condenser capacity. The adjustment of the condenser capacity is made according to the control signal UVSrC which is obtained using the fuzzy reasoning. The effectiveness of the proposed control scheme is demonstrated by computer simulations of the dynamic responses of multi-machine power systems.
A Synthesis Method for Cutpoint Cellular Arrays
Authors: G. K. Papakonstantinou
Venue: IEEE Transactions on Computers (1972)

In the present paper three theorems are developed to merge two columns in a cutpoint cellular array into one, depending on the sequence of cutpoint indices in each of the columns. An algorithm is then proposed for realizing arbitrary switching functions with a cutpoint cellular array, based on a set of rules derived from the above theorems. The algorithm is tested with numerous examples.
On the trade-off between speed and resiliency of flashworms and similar malcodes
Authors: Duc T. Ha, Hung Q. Ngo
Venue: Proceedings of the 2007 ACM workshop on Recurring malcode (2007)

Inspired by the Flash worm paper [1], we formulate and investigate the problem of finding a fast and resilient propagation topology and propagation schedule for Flash worms and similar malcodes. Resiliency means a very large proportion of infectable targets are still infected no matter which fraction of targets are not infectable. There is an intrinsic tradeoff between speed and resiliency, since resiliency requires transmission redundancy which slows down themalcode. To investigate this problem formally, we need an analytical model. We first show that, under a moderately general analytical model, the problem of optimizing propagation time isNP-hard. This fact justifies the need for a simpler model, which we present next. In this simplified model, we present an optimal propagation topology and schedule, which is then shown by simulationto be even faster than the Flash worm. Moreover, our worm is faster even when the source has much less bandwidth capability. We also show that for every preemptive schedule there exists a nonpreemptive schedule which is just as effective. This fact greatly simplifies the optimization proble In terms of the aforementioned tradeoff, we give a propagation topology based on extractor graphs which can reduce the infection time linearly while keeping the expected number of infected nodes exponentially close to optimal.
Energy-Efficient State Scheduling for Maximizing Sensor Network Lifetime under Coverage Constraint
Authors: Ali Chamam, Samuel Pierre
Venue: Proceedings of the Third IEEE International Conference on Wireless and Mobile Computing, Networking and Communications (2007)

Wireless sensor networks consist of a large number of low-power, limited-processing capability sensors that are deployed in a field to measure physical variables or detect events like intrusion or movement. In surveillance appli- cations, ensuring a high area coverage is an important is- sue requiring a certain number of sensors to be turned on to report events. In this paper, we address the problem of maximizing the sensor network lifetime under area cover- age constraint. For that, we propose a scheduling mecha- nism that calculates, for every time slot of the network op- erating period, an optimal covering subset of sensors that will be activated while all other sensors will go on Sleep. We model this problem as an Integer Linear Programming (ILP) problem, that we resolve using ILOG CPLEX [9] and we show that the obtained solutions provide for a more bal- anced energy consumption when we increase a balancing exponent , which increases network lifetime.
Micromultiprocessing: An Approach to Multiprocessing at the Level of Very Small Tasks
Authors: J. L. Rosenfeld
Venue: IEEE Transactions on Computers (1973)

The design and performance evaluation of a multiprocessor system are described. The system consists of processing units sharing the processing of the same instruction stream, where tasks consist of individual instructions. The multiprocessing aspect is completely transparent to the user. The system configuration developed calls for two microprogrammed processing units sharing the same local and control stores.
The inventory management system for automobile spare parts in a central warehouse
Authors: S. G. Li, X. Kuo
Venue: Expert Systems with Applications: An International Journal (2008)

Because of the complex structure of spare parts supply chain, the conventional approaches, which do not consider the relationships between decision factors globally, cannot achieve the optimal performance. Therefore, this paper aims to develop an enhanced fuzzy neural network (EFNN) based decision support system for managing automobile spares inventory in a central warehouse. In this system, the EFNN is utilized for forecasting the demand for spare parts. However, without considering relevant domain knowledge, traditional neural networks are found to be suffered from the problem of low accuracy of forecasting unseen examples. Therefore, in our EFNN, the following improvement is made: First, it assigns connection weights based on the fuzzy analytic hierarchy process (AHP) method without painstakingly turning them. Second, by generating and refining activation functions according to genetic algorithm, our EFNN can provide comprehensive and accurate activation functions and fit a wider range of nonlinear models. Last, but not least, an adaptive input variable is introduced to decrease the impact of the bullwhip effect on the forecasting accuracy. The proposed system is evaluated with the real word data and experimental results indicate that our EFNN outperforms other five models in fill rate and stock cost measures.
Fault Tolerant SoC Architecture Design for JPEG2000 using Partial Reconfigurability
Authors: Abderrahim Doumar, Kentaroh Katoh, Hideo Ito
Venue: Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (2007)

In this paper, we present the design of a new architecture tolerating faults for the Image compression standard JPEG2000. The proposed fault tolerant design is based on adding a new reconfigurable core to the rest of the cores of the SoC. When a fault happens, it is tolerated using this reconfigurable core. The paper explains the hardware architecture allowing this inter-core communication toward fault tolerance. The target is to achieve a good reliability by this fault tolerance strategy and in the same time achieve the required speed allowing to the JPEG2000 to deal with video rather than still Image compression. The high speed is implemented using an optimized data organization and memories arrangement for the computation consuming blocks of the JPEG2000. The operating speed of the proposed architecture is 125 MHz for ALTERA FPGA implementation. The proposed architecture has increased the speed by a factor of 1.5, when compared to similar memory requiring architectures and decreased the memory requirement by a factor of 1.2, when compared to similar speed requiring architectures. Additionally, the proposed architecture achieves 91.45% fault coverage and it requires only 21% hardware overhead. The architecture has an optimum latency of 78.8 seconds corresponding to an optimum test sequence of n=985. The VHDL implementation of the six blocks of JPEG2000, corresponding to the full chain, has been developed and successfully validated on various types of ALTERA FPGA.
Relay OFDMA System for Wireless Multimedia Services in Home Area Networks
Authors: Kyung Min Park, Jong Hyuk Park, Young Yong Kim
Venue: Proceedings of the Third International Conference on Natural Computation - Volume 05 (2007)

We design the wireless multimedia services system using orthogonal frequency division multiple access (OFDMA) schemes allowing cooperative relays in home area networks. The multihop transmission scheme by relay stations provide reliable services to users in dead spots like the cel- lar or the garden. For this system, we propose an adaptive subcarrier and transmit power allocation method that max- imizes the system total data rate in a downlink transmis- sion. We generally formulate the total data rate maximiza- tion problem and develop a resource allocation scheme to solve it. The scheme is derived via two parts: allocating the resource for users and making a decision to relay or not. Since these two works influence each other, the subcarriers and power should be assigned in consideration of whether to relay or not. We compare the performance of the pro- posed method with existing resource allocation schemes, the 1-hop transmission with dynamic resource allocation and 2- hop transmission with fixed resource allocation. By relay- ing and scheduling gain, the total data rate of the proposed scheme is greater than those of other schemes, and grows as the number of users in the system increases due to multiuser diversity effects.
The Computer Science and Engineering Core Curriculum
Authors: J. T. Cain
Venue: Computer (1977)

The guidelines for developing the CSE model curricula presented in the first paper of this issue were (1) to span the entire spectrum of computer science and engineering and provide the opportunity for in-depth study or specailization in any area of the field; (2) to bridge the traditional gap between hardware and software by emphasizing the interrelationship, common concepts, and inseparability of these two aspects of the field; and (3) to provide a blueprint for specific implementations.
TCP Performance in IEEE 802.11-Based Ad Hoc Networks with Multiple Wireless Lossy Links
Authors: Xia Li, Peng-Yong Kong, Kee-Chaing Chua
Venue: IEEE Transactions on Mobile Computing (2007)

We propose a packet level model to investigate the impact of channel error on TCP performance over IEEE 802.11 based multi-hop wireless networks. A Markov renewal approach is used to analyze the behavior of TCP Reno and TCP Impatient NewReno. Compared to previous work, our main contributions are as follows: i) modeling of multiple lossy links; ii) investigating the interactions among TCP, IP and MAC protocol layers, specifically the impact of 802.11 MAC protocol and DSR routing protocol on TCP throughput performance; iii) considering the spatial reuse property of the wireless channel, the model takes into account the different proportions between the interference range and transmission range; iv) adopting more accurate and realistic analysis to fast-recovery process, and showing the dependency of throughput and the risk of experiencing successive fast-retransmits and timeouts on the packet error probability. The analytical results are validated against simulation results using GloMoSim. The results show that the impact of the channel error is reduced significantly due to the packet retransmissions on a per-hop basis and a small bandwidth-delay product of ad hoc networks. The TCP throughput always deteriorates less than ~10% with a packet error rate ranging from 0 to 0.1. Our model also provides a theoretical basis for designing an optimum long retry limit for IEEE 802.11 in ad hoc networks.
Recognition of Fanout-free Functions
Authors: Tsung-Lin Lee, Chun-Yao Wang
Venue: Proceedings of the 2007 Asia and South Pacific Design Automation Conference (2007)

Factoring is a logic minimization technique to represent a Boolean function in an equivalent function with minimum literals. When realizing the circuit, a function represented in a more compact form has smaller area. Some Boolean functions even have equivalent forms where each variable appears exactly once, which are known as fanout-free functions. John P. Hayes (Hayes, 1975) had devised an algorithm to determine if a function can be fanout-free and construct the circuit if fanout-free realization exists. In this paper, we propose a property and an efficient technique to accelerate this algorithm. With our improvements, execution time of this algorithm is more competitive with the state-of-the-art method (Golumbic, 2001).
CTO: concept tree based semantic overlay for pure peer-to-peer information retrieval
Authors: Jianming Lv, Xueqi Cheng
Venue: Proceedings of the sixteenth ACM conference on Conference on information and knowledge management (2007)

Inspired by how search behavior works in human society, we propose CTO, a self-organized semantic overlay based on concept tree for P2P IR infrastructure, which is efficient for full text search in pure P2P environment without any central control or powerful peer as hub node. Especially, CTO performs very well on searching the unpopular resources shared by a few peers. In our experiment, while searching for the scarce documents shared by the peers, CTO achieves about 80% recall rate when the search covers less than 5% peers in the overlay. The search latency of CTO is also very low, which is controlled in the range about 5~12 hops.
On the Selection of an Optimal Set of Indexes
Authors: M. Y. L. Ip
Venue: IEEE Transactions on Software Engineering (1983)

A problem of considerable interest in the design of a database is the selection of indexes. In this paper, we present a probabilistic model of transactions (queries, updates, insertions, and deletions) to a file. An evaluation function, which is based on the cost saving (in terms of the number of page accesses) attributable to the use of an index set, is then developed. The maximization of this function would yield an optimal set of indexes. Unfortunately, algorithms known to solve this maximization problem require an order of time exponential in the total number of attributes in the file. Consequently, we develop the theoretical basis which leads to an algorithm that obtains a near optimal solution to the index selection problem in polynomial time. The theoretical result consists of showing that the index selection problem can be solved by solving a properly chosen instance of the knapsack problem. A theoretical bound for the amount by which the solution obtained by this algorithm deviates from the true optimum is provided. This result is then interpreted in the light of evidence gathered through experiments.
A 2-ps Resolution Wide Range BIST Circuit for Jitter Measurement
Authors: Nai-Chen Daniel Cheng, Yu Lee, Ji-Jan Chen
Venue: Proceedings of the 16th Asian Test Symposium (2007)

In this paper, we propose a novel built-in self-test (BIST) circuit to directly measure cycle-to-cycle jitter. The clock-under-test is under-sampled by this measurement circuit and the jitter values are transformed into digital words. A time-amplified technique is applied to obtain relatively higher resolution with smaller hardware overhead. Experimental results show that our proposed circuit is able to measure the jitter providing the clock frequency up to 2 GHz with resolution of 2 picoseconds.
Using functional independence conditions to optimize the performance of latency-insensitive systems
Authors: Cheng-Hong Li, Luca P. Carloni
Venue: Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design (2007)

In latency-insensitive design shell modules are used to encapsulate system components (pearls) in order to interface them with the given latency-insensitive protocol and dynamically control their operations. In particular, a shell stalls a pearl whenever new valid data are not available on its input channels. We study how functional independence conditions (FIC) can be applied to the performance optimization of a latency-insensitive system by avoiding unnecessary stalling of their pearls. We present a novel circuit design of a generic shell template that can exploit FICs. We describe an automatic procedure for the logic synthesis of a FIC-shell instance that is only based on the analysis of the logic structure of its corresponding pearl and does not require any input from the designers. We implemented the proposed technique within the logic synthesis tool ABC and we use it to complete various experiments that demonstrate its performance benefits and limited overhead. In particular, we completed the semi-custom design of a system-on-chip (SoC), an ultra-wideband baseband transmitter, using a state-of-the-art 90nm technology process. To the best of our knowledge this represents the first report on the complete latency-insensitive design of a real-world SoC.
Adaptive Latency-Insensitive Protocols
Authors: Mario R. Casu, Luca Macchiarulo
Venue: IEEE Design Test (2007)

Latency-insensitive design copes with excessive delays typical of global wires in current and future IC technologies. The goal is achieved through the encapsulation of synchronous logic blocks in wrappers that communicate via a latency-insensitive protocol (LIP) and pipelined interconnects. Previously proposed solutions suffer from excessive performance penalty in terms of throughput, or lack of generality. The authors present an adaptive version of an LIP that outperforms previous "static" implementations, as demonstrated through two relevant study cases: a microprocessor and an MPEG encoder, whose components are made insensitive to the latencies of their interconnections through a newly developed wrapper. This article also features an informal exposition of the theoretical basis of adaptive LIPs as well as implementation details.
A Parameterized Architecture Model in High Level Synthesis for Image Processing Applications
Authors: Yazhuo Dong, Yong Dou
Venue: Proceedings of the 2007 Asia and South Pacific Design Automation Conference (2007)

Most image processing applications are computationally intensive and data intensive. Reconfigurable hardware boards provide a convenient and flexible solution to speed up these algorithms. To get a high performance design without going through the time-consuming hardware design process for each different algorithm, we present a universal parameterized architecture in high level synthesis to generate the hardware frames for all image processing applications automatically. The value of the parameters which decide the target architecture can be obtained from the compiler. The algorithm how to get these parameters is also discussed in this paper.
Test data generation for programming exercises with symbolic execution in Java PathFinder
Authors: Petri Ihantola
Venue: Proceedings of the 6th Baltic Sea conference on Computing education research: Koli Calling 2006 (2006)

Automatic assessment of programming exercises is typically based on testing approach. Most automatic assessment frameworks execute tests and evaluate test results automatically, but the test data generation is not automated. No matter that such test data generation techniques and tools are available. We have researched how the Java PathFinder software model checker can be adopted to the specific needs of test data generation in automatic assessment. Practical problems considered are: How to derive test data directly from students' programs (i.e. without annotation) and how to visualize and how to abstract test data automatically for students? Interesting outcomes of our research are that with minor refinements generalized symbolic execution with lazy initialization (a test data generation algorithm implemented in PathFinder) can be used to construct test data directly from students' programs without annotation, and that intermediate results of the same algorithm can be used to provide novel visualizations of the test data.
Safety and Security-driven Design of Networked Embedded Systems
Authors: Miroslav Sveda, Roman Trchalik
Venue: Proceedings of the 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (2007)

The paper presents a safety and security-driven approach to embedded system design for an industrial class of Internet-based applications. It discusses an integrated networking framework stemming from the IEEE 1451.1 smart transducer interface standard, which is an object-based networking model supporting client-server and publish-subscribe communication patterns in group messaging, and from the IP multicast communication, all together mediating safe and secure access to smart sensors through Internet. The case study demonstrates how clients can access groups of wireless smart pressure and temperature sensors and valves effectively through Internet using developed system architecture while respecting prescribed requirements for application dependent safety and security.
On the Local Behavior of Spaces of Natural Images
Authors: Gunnar Carlsson, Tigran Ishkhanov, Vin Silva, Afra Zomorodian
Venue: International Journal of Computer Vision (2008)

In this study we concentrate on qualitative topological analysis of the local behavior of the space of natural images. To this end, we use a space of 3 by 3 high-contrast patches ¿. We develop a theoretical model for the high-density 2-dimensional submanifold of ¿ showing that it has the topology of the Klein bottle. Using our topological software package PLEX we experimentally verify our theoretical conclusions. We use polynomial representation to give coordinatization to various subspaces of ¿. We find the best-fitting embedding of the Klein bottle into the ambient space of ¿. Our results are currently being used in developing a compression algorithm based on a Klein bottle dictionary.
Compsac78 Wrap-up
Authors: W. Myers
Venue: Computer (1979)

The Second Annual Computer Software and Applications Conference, held November 13-16 in Chicago, drew 715 attendees to consider aspects of software design, quality assurance, and project management. The ACM Portal is published by the Association for Computing Machinery. Copyright © 2010 ACM, Inc. Terms of Usage Privacy Policy Code of Ethics Contact Us Useful downloads: Adobe Acrobat QuickTime Windows Media Player Real Player
Internet Forensics: Legal and Technical Issues
Authors: Maria Karyda, Lilian Mitrou
Venue: Proceedings of the Second International Workshop on Digital Forensics and Incident Analysis (2007)

This paper provides a combined approach on the major issues pertaining to the investigation of cyber crimes and the deployment of Internet forensics techniques. It discusses major issues from a technical and legal perspective and provides general directions on how these issues can be tackled. The paper also discusses the implications of data mining techniques and the issue of privacy protection with regard to the use of forensics methods.
Text/Non-text Ink Stroke Classification in Japanese Handwriting Based on Markov Random Fields
Authors: X.-D. Zhou, C.-L. Liu, S. Quiniou, E. Anquetil
Venue: Proceedings of the Ninth International Conference on Document Analysis and Recognition - Volume 01 (2007)

In this paper, we present an approach for separat- ing text and non-text ink strokes in online handwritten Japanese documents based on Markov random fields (MRFs), which effectively utilize the spatial relation- ship between strokes. Support vector machine (SVM) classifiers are trained for individual stroke and stroke pair classification, and on converting the SVM outputs to probabilities, the likelihood clique potentials of MRF are derived. In experiments on the TUAT Kon- date database, the proposed MRF approach yield su- perior performance compared to individual stroke classification and sequence classification based on hidden Markov models (HMMs).