ppxscal/embedding_network huggingface dataset:
Advanced Wireless Access System
Authors: Keisuke Ogawa, Akira Hashimoto, Kenji Kohiyama
Venue: Wireless Personal Communications: An International Journal (1997)

The key words for the future telecommunications are personalization, multi-media services and high accessibility to the network. These trends naturally lead to radio media application to access links. In this sense, this paper proposes an advanced wireless access system with a capacity supporting broadband video and data services. Concept of the system can be defined as a new radiocommunication category with advantages of both fixed and mobile systems. The system is designed to transport ATM-based signals using SHF (or EHF) bands to wireless terminals, interconnected with optical fibers at the network side. The basic system configuration is presented as well as examples of system parameters. For radio aspects the maximum service coverages of the radio base stations are calculated based on availability consideration. Preferred frequency bands for actual operation are also discussed.
Redundant and On-Line CORDIC for Unitary Transformations
Authors: N. D. Hemkumar, J. R. Cavallaro
Venue: IEEE Transactions on Computers (1994)

Two-sided unitary transformations of arbitrary 2/spl times/2 matrices are needed in parallel algorithms based on Jacobi-like methods for eigenvalue and singular value decompositions of complex matrices. This paper presents a two-sided unitary transformation structured to facilitate the integrated evaluation of parameters and application of the typically required transformations using only the primitives afforded by CORDIC; thus enabling significant speedup in the computation of these transformations on special-purpose processor array architectures implementing Jacobi-like algorithms. We discuss implementation in (nonredundant) CORDIC to motivate and lead up to implementation in the redundant and on-line enhancements to CORDIC. Both variable and constant scale factor redundant (CFR) CORDIC approaches are detailed and it is shown that the transformations may be computed in 10n+/spl delta/ time, where n is the data precision in bits and /spl delta/ is a constant accounting for accumulated on-line delays. A more area-intensive approach using a novel on-line CORDIC encoded angle summation/difference scheme reduces computation time to 6n+/spl delta/. The area/time complexities involved in the various approaches are detailed.
Automated Debugging: Are We Close
Authors: Andreas Zeller
Venue: Computer (2001)

Although software engineers have enjoyed tremendous productivity increases as more of their tasks have become automated, debugging remains as labor-intensive and painful as it was 50 years ago. An engineer or programmer must still set up hypotheses to use in identifying and correcting a failure's root cause. The author describes a new algorithm that promises to relieve programmers of the hit-or- miss approach to debugging. Delta Debugging uses the results of automated testing to systematically narrow the set of failure-inducing circumstances. Programmers supply a test function for each bug and hardcode it into any imperative language. The test function checks a set of changes to determine if the failure is present or if the outcome is unresolved, then feeds that information to the Delta Debugging code. As we discover more about the structure of these circumstances and the resulting causality chain, we come closer to passing much of the boredom and monotony of debugging onto machines. Debugging can be just as disciplined, systematic, and quantifiable as any other area of software engineering--which means that we should eventually be able to automate at least part of it. Ultimately, debugging may become as automated as testing--not only detecting failures, but also revealing how they came to be.
A framework for the development of multimedia systems for use in engineering education
Authors: Jim Carter
Venue: Computers Education (2002)

Multimedia presents a number of challenges and opportunities which must be addressed if it is to be used effectively in an educational context. Engineering education can greatly benefit, if these challenges and opportunities are met. This paper describes a framework for the development of multimedia applications. It then uses this framework to identify how emerging international multimedia standards can be combined with educational objectives to provide guidance for the developers of effective multimedia for engineering education.
Visualizing a Knowledge Domain's Intellectual Structure
Authors: Chaomei Chen, Ray J. Paul
Venue: Computer (2001)

To make knowledge visualizations clear and easy to interpret, the authors have developed a method that extends and transforms traditional author co-citation analysis (ACA) by extracting structural patterns from the scientific literature and representing them in a 3D knowledge landscape. Integrating citation and co-citation patterns provides a rich, ecological representation of a knowledge domain. Users can apply visualizations to discover patterns and make valuable connections among data. The authors' approach extends conventional ACA by integrating structured modeling and information visualization techniques to provide a 3D knowledge landscape based on citation patterns.Their four-step procedure introduces Pathfinder network scaling to replace multidimensional scaling. It also integrates Pathfinder and factor analysis to visualize specialties in the underlying domain knowledge and visualizes the citation frequency of scientists to track changes in their influence over time.This knowledge visualization approach identifies intellectual groupings based on extending the traditional ACA, augmenting the existing document- and concept-centered approaches to knowledge visualization. The 3D knowledge landscape has practical implications in knowledge visualization, digital libraries, domain analysis, and subject domains, providing powerful tools for tracking intuitively scientific knowledge.
An object-oriented interface for the dynamic memory management of sparse discrete mathematical operators in numerical scientific applications
Authors: G. Manzini, S. Mazet
Venue: Software&mdash;Practice Experience (2002)

This paper describes an object-oriented interface for the memory management of sparse discrete mathematical operators in numerical scientific applications. The basic data structure we propose is intended to implement and cope with mathematical vectors in sparse format. This structure allows an effective implementation of more complex data structures, such as matrix and matrix-like objects, to represent the discrete version of differential operators in numerical application codes. A research example concerning adaptive wavelet algorithms illustrates the possible applications.
An efficient abstract interface for multidimensional array I/O
Authors: Kent E. Seamons, Marianne Winslett
Venue: Proceedings of the 1994 ACM/IEEE conference on Supercomputing (1994)

Our research seeks to provide scientific programmers with simpler, more abstract interfaces for accessing persistent multidimensional arrays, and to produce advanced i/o libraries supporting more efficient layout alternatives for these arrays on disk and in main memory. We report on our experience to date applying these techniques to applications in computational fluid dynamics in the areas of checkpoint/restart, output data, and visualization. In the applications we have studied, we find that a simple, abstract interface can be used to insulate programmers from physical storage implementation details, while providing improved i/o performance at the same time. For example, we found that the use of "chunked" physical schemas for arrays gave approximately a factor of 10 improvement in time step output performance on the Intel iPSC/860.
Three-way component analysis with smoothness constraints
Authors: Marieke E. Timmerman, Henk A. L. Kiers
Venue: Computational Statistics Data Analysis (2002)

Tucker3 Analysis and CANDECOMP/PARAFAC (CP) are closely related methods for three-way component analysis. Imposing constraints on the Tucker3 or CP solutions can be useful to improve estimation of the model parameters. In the present paper, a method is proposed for applying smoothness constraints on Tucker3 or CP solutions, which is particularly useful in analysing functional three-way data. The usefulness of smoothness constraints on Tucker3 and CP solutions is examined by means of a simulation experiment. Generally, the results of the experiments indicate better estimations of the model parameters. An empirical example illustrates the use of smoothness constraints. The constrained model is more stable and easier to interpret than the unconstrained model.
GRAPE-4: a one-Tflops special-purpose computer for astrophysical N-body problem
Authors: Junichiro Makino, Makoto Taiji, Toshikazu Ebisuzaki, Daiichiro Sugimoto
Venue: Proceedings of the 1994 ACM/IEEE conference on Supercomputing (1994)

We describe the GRAPE-4 (Gravity Pipe 4) system, a special-purpose computer for astrophysical N-body simulations. In N-body simulations, most of the computing time is spent to calculate the force between particles, since the number of interactions is proportional to the square of the number of particles. For many problems the accuracy of fast algorithms such as the particle-mesh scheme is not sufficient and we have to use the straightforward direct summation.In order to accelerate the force calculation, we have developed a series of hardwares, the GRAPE (Gravity Pipe) systems. The basic idea of our GRAPE systems is to develop a hardware specialized for the force calculation. The rest of the calculation is performed on the general-purpose computer connected to GRAPE.The GRAPE-4 system is our newest hardware, scheduled to be completed in early 1995. Planned peak speed is 1.15 Tflops. This speed is achieved by running 1920 pipeline LSIs, each provides 600 Mflops, in parallel. A prototype system has been completed July 1994, and the full system is now under manufacturing.
Boundary Scan with Built-In Self-Test
Authors: Clay S. Gloster Jr., Franc Brglez
Venue: IEEE Design Test (1989)

The authors propose a way to merge boundary scan with the built-in self-test (BIST) of printed circuit boards. Their boundary-scan structure is based on Version 2.0 of the Joint Task Action Group's recommendations for boundary scan and incorporates BIST using a register based on cellular automata (CA) techniques. They examine test patterns generated from this register and the more conventional linear-feedback shift register. The advantages of the CA register, or CAR, are its modularity, which allows modification without major redesign, its higher stuck-at fault coverage, and its higher transition fault coverage.
Block Scheduling of Iterative Algorithms and Graph-Level Priority Scheduling in a Simulated Data-Flow Multiprocessor
Authors: P. Evripidou, J. L. Gaudiot
Venue: IEEE Transactions on Parallel and Distributed Systems (1993)

Iterative methods for solving linear systems are discussed. Although these methods areinherently highly sequential, it is shown that much parallelism could be exploited in adata-flow system by scheduling the iterative part of the algorithms in blocks and bylooking ahead across several iterations. This approach is general and will apply to otheriterative and loop-based problems. It is also demonstrated by simulation that relyingsolely on data-driven scheduling of parallel and unrolled loops results in low resourceutilization and poor performance. A graph-level priority scheduling mechanism has beendeveloped that greatly improves resource utilization and yields higher performance.
Minimum multiplicities of subgraphs and Hamiltonian cycles
Authors: John Sheehan
Venue: Discrete Mathematics (2002)

Let G be a finite simple graph with automorphism group A(G). Then a spanning subgraph U of G is a fixing subgraph of G if G contains exactly |A(G)|/|A(G) ∩ A(U)| subgraphs isomorphic to U: the graph G must always contain at least this number. If in addition A(U) ⊆ A(G) then U is a strong fixing subgraph. Fixing subgraphs are important in many areas of graph theory. We consider them in the context of hamiltonian graphs.
A logical framework for reasoning about access control models
Authors: Elisa Bertino, Barbara Catania, Elena Ferrari, Paolo Perlasca
Venue: ACM Transactions on Information and System Security (TISSEC) (2003)

The increased awareness of the importance of data protection has made access control a relevant component of current data management systems. Moreover, emerging applications and data models call for flexible and expressive access control models. This has led to an extensive research activity that has resulted in the definition of a variety of access control models that differ greatly with respect to the access control policies they support. Thus, the need arises for developing tools for reasoning about the characteristics of these models. These tools should support users in the tasks of model specification, analysis of model properties, and authorization management. For example, they must be able to identify inconsistencies in the model specification and must support the administrator in comparing the expressive power of different models. In this paper, we make a first step in this direction by proposing a formal framework for reasoning about access control models. The framework we propose is based on a logical formalism and is general enough to model discretionary, mandatory, and role-based access control models. Each instance of the proposed framework corresponds to a C-Datalog program, interpreted according to a stable model semantics. In the paper, besides giving the syntax and the formal semantics of our framework, we show some examples of its application. Additionally, we present a number of dimensions along which access control models can be analyzed and compared. For each dimension, we show decidability results and we present some examples of its application.
Partnering Usability with Development: How Three Organizations Succeeded
Authors: Karla Radle, Sarah Young
Venue: IEEE Software (2001)

Improving product usability enhances an organization's productivity, competitiveness, and profitability. However, integrating usability practice¿or human factors engineering¿into an organization is challenging. These case studies examine how three organizations succeeded.
On the Relationship Between BDI Logics and Standard Logics of Concurrency
Authors: Klaus Schild
Venue: Autonomous Agents and Multi-Agent Systems (2000)

The behavior of an agent is mainly governed by the specific way in which it handles the rational balance between information and deliberation. Rao and Georgeff's BDI theory is most popular among the formalisms capturing this very balance. This formalism has been proposed as a language for specifying agents in an abstract manner or, alternatively, for verifying various properties of agents implemented in some other programming language. In mainstream computer science, there are formalisms designed for a purpose similar to the BDI theory; not specifically aiming at agents, but at concurrency in general. These formalisms are known as logics of concurrent programs. In this paper these two frameworks are compared with each other for the first time. The result shows that the basic BDI theory, BDI_CTL&ast;, can be captured within a standard logic of concurrency. The logic which is relevant here is Kozen's propositional &mu;-calculus. &mu;-calculus turns out to be even strictly stronger in expressive power than BDI_CTL&ast; while enjoying a computational complexity which is not higher than that of BD_CTL&ast;'s small fragment CTL. This correspondence puts us in a position to provide the first axiomatization of Rao and Georgeff's full theory. Immediate consequences for the computational complexity of BDI theory are also explored, both for theorem proving and model checking.
Query Rewriting for SWIFT (First) Answers
Authors: Kian-Lee Tan, Cheng Hian Goh, Beng Chin Ooi
Venue: IEEE Transactions on Knowledge and Data Engineering (2000)

Traditionally, the answer to a database query is construed as the set of all tuples that meet the criteria stated. Strict adherence to this notion in query evaluation is, however, increasingly unsatisfactory because decision makers are more prone to adopting an exploratory strategy for information search which we call ¿getting some answers quickly, and perhaps more later.¿ From a decision-maker's perspective, such a strategy is optimal for coping with information overload and makes economic sense (when used in conjunction with a micropayment mechanism). These new requirements present new opportunities for database query optimization. In this paper, we propose a progressive query processing strategy that exploits this behavior to conserve system resources and to minimize query response time and user waiting time. This is accomplished by the heuristic decomposition of user queries into subqueries that can be evaluated on demand. To illustrate the practicality of the proposed methods, we describe the architecture of a prototype system that provides a nonintrusive implementation of our approach. Finally, we present experimental results obtained from an empirical study conducted using an Oracle Server that demonstrate the benefits of the progressive query processing strategy.
Maintaining Object-Oriented Software
Authors: Norman Wilde, Paul Matthews, Ross Huitt
Venue: IEEE Software (1993)

The maintenance requirements of object-oriented software, including the ability to make changes easily and an in-depth understanding of the software's structure and behavior, are discussed. The problems encountered by a maintainer trying to understand object-oriented software by reading and statically analyzing it are described. The problems caused by dynamic binding, polymorphism, and cooperating object classes in object-oriented software maintenance are reviewed.
Switching window computation for static timing analysis in presence of crosstalk noise
Authors: Pinhong Chen, Desmond A. Kirkpatrick, Kurt Keutzer
Venue: Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design (2000)

Crosstalk effect is crucial for timing analysis in very deep submicron design. In this paper, we present and compare multiple scheduling algorithms to compute switching windows for static timing analysis in presence of crosstalk noise. We also introduce an efficient technique to evaluate the worst case alignment of multiple aggressors.
Design of an Integrated Information Retrieval/Database Management System
Authors: L. V. Saxton, V. V. Raghavan
Venue: IEEE Transactions on Knowledge and Data Engineering (1990)

To increase the semantics available in a database system it is useful to integrate it with the well-understood models, leading to ranked response of queries that characterize information retrieval systems. A novel, unified architecture is presented which provides the flexibility of integrating any information retrieval (IR) model with any type of database management system. More importantly, the approach provides for the ability to use 'aggregation' and 'generalization' operations automatically to provide more meaningful responses. In addition, this framework makes possible the systematic investigation of the potential of using IR models as a general tool for supporting management decisions.
A Generalized Simultaneous Access Dictionary Machine
Authors: Z. Fan, K. H. Cheng
Venue: IEEE Transactions on Parallel and Distributed Systems (1991)

A simultaneous access design of a dictionary machine which supports insert, delete, andsearch operations is presented. The design is able to handle p accesses simultaneouslyand allows redundant accesses to occur. In the design, processors performing insert ordelete operations are free to perform other tasks after submitting their accesses to thedesign; processors that perform search operations get their response in O(log N) time.Compared to all sequential access designs of a dictionary which require O(p) time toprocess p accesses, the presented design provides much higher throughput; specifically,O(p/log p) times better. It also provides a fast mechanism to avoid the sequential accessbottleneck in any large multiprocessor system.
Hardware Generation of Random Single Input Change Test Sequences
Authors: R. David, P. Girard, C. Landrault, S. Pravossoudovitch, A. Virazel
Venue: Journal of Electronic Testing: Theory and Applications (2002)

The combination of higher quality requirements and sensitivity of high performance circuits to delay defects has led to an increasing emphasis on delay testing of VLSI circuits. As delay testing using external testers requires expensive ATE, built-in self test (BIST) is an alternative technique that can significantly reduce the test cost.It has been proven that Single Input Change (SIC) test sequences are more effective than classical Multiple Input Change (MIC) test sequences when a high robust delay fault coverage is targeted. It has also been shown that random SIC (RSIC) test sequences achieve a higher fault coverage than random MIC (RMIC) test sequences when both robust and non robust tests are under consideration&semi; the experimental results were based on a software generation of RSIC sequences that are easily generated.Obviously, a hardware RSIC generation providing similar results can be obtained. However, this hardware generator must be carefully designed. In this paper, it is explained what are the criteria which must be satisfied for this purpose. A solution is proposed and illustrated with an example. Then, it is shown that a bad result may be obtained if one of these criteria is not satisfied.
Methodical Low-Power ASIP Design Space Exploration
Authors: Tilman Glökler, Andreas Hoffmann, Heinrich Meyr
Venue: Journal of VLSI Signal Processing Systems (2003)

Application-specific instruction set processors (ASIPs) are an excellent implementation paradigm for mixed control-/data-flow oriented tasks with medium to low data rate and high complexity. The main advantage of ASIPs is the higher flexibility due to programmability compared to dedicated hardware. This article discusses an ASIP design methodology starting from the instruction set architecture description language LISA, which enables automatic generation of the necessary DSP tools like assembler, linker and simulator as well as generation of large parts of the synthesizable hardware description. The presented methodology has the goal to obtain working silicon in a short amount of time. Furthermore, the classical parameters computational performance and area are jointly considered with the impact of architectural modifications on energy consumption using gate-level estimations. Different pipeline structures from two to four pipeline stages together with several ASIP energy optimization options have been implemented and evaluated. These optimizations include clock-gating, logic netlist restructuring, data-path optimization, instruction memory power reduction by optimized instruction encoding, and implementation of a dedicated coprocessor. The practical applicability of this methodology is demonstrated with the ICORE ASIP for DVB-T acquisition and tracking algorithms. The results of this case study reveal a potential of about one order of magnitude in energy savings. Furthermore a significant decrease in design time was achieved due to the LISA methodology.