ppxscal/embedding_network huggingface dataset:
Coderivatives in parametric optimization
Authors: Adam B. Levy, Boris S. Mordukhovich
Venue: Mathematical Programming: Series A and B (2004)

We consider parametric families of constrained problems in mathematical programming and conduct a local sensitivity analysis for multivalued solution maps. Coderivatives of set-valued mappings are our basic tool to analyze the parametric sensitivity of either stationary points or stationary point-multiplier pairs associated with parameterized optimization problems. An implicit mapping theorem for coderivatives is one key to this analysis for either of these objects, and in addition, a partial coderivative rule is essential for the analysis of stationary points. We develop general results along both of these lines and apply them to study the parametric sensitivity of stationary points alone, as well as stationary point-multiplier pairs. Estimates are computed for the coderivative of the stationary point multifunction associated with a general parametric optimization model, and these estimates are refined and augmented by estimates for the coderivative of the stationary point-multiplier multifunction in the case when the constraints are representable in a special composite form. When combined with existing coderivative formulas, our estimates are entirely computable in terms of the original data of the problem.
An experimental evaluation of continuous testing during development
Authors: David Saff, Michael D. Ernst
Venue: Proceedings of the 2004 ACM SIGSOFT international symposium on Software testing and analysis (2004)

Continuous testing uses excess cycles on a developer's workstation to continuously run regression tests in the background, providing rapid feedback about test failures as source code is edited. It is intended to reduce the time and energy required to keep code well-tested and prevent regression errors from persisting uncaught for long periods of time. This paper reports on a controlled human experiment to evaluate whether students using continuous testing are more successful in completing programming assignments. We also summarize users' subjective impressions and discuss why the results may generalize.The experiment indicates that the tool has a statistically significant effect on success in completing a programming task, but no such effect on time worked. Participants using continuous testing were three times more likely to complete the task before the deadline than those without. Participants using continuous compilation were twice as likely to complete the task, providing empirical support to a common feature in modern development environments. Most participants found continuous testing to be useful and believed that it helped them write better code faster, and 90% would recommend the tool to others. The participants did not find the tool distracting, and intuitively developed ways of incorporating the feedback into their workflow.
Smart Sensor Architecture Customized for Image Processing Applications
Venue: Proceedings of the 10th IEEE Real-Time and Embedded Technology and Applications Symposium (2004)

A system level design methodology is applied to theembedded system design for a typical sensor networkapplication: face detection for security purpose. Thetradeoff analysis is performed for hardware and softwareimplementations of the tasks in this application. Thebest system design is achieved with limited hardware re-sources.
Robust numerical features for description and classification of subcellular location patterns in fluorescence microscope images
Authors: Robert F. Murphy, Meel Velliste, Gregory Porreca
Venue: Journal of VLSI Signal Processing Systems (2003)

The ongoing biotechnology revolution promises a complete understanding of the mechanisms by which cells and tissues carry out their functions. Central to that goal is the determination of the function of each protein that is present in a given cell type, and determining a protein's location within cells is critical to understanding its function. As large amounts of data become available from genome-wide determination of protein subcellular location, automated approaches to categorizing and comparing location patterns are urgently needed. Since sub-cellular location is most often determined using fluorescence microscopy, we have developed automated systems for interpreting the resulting images. We report here improved numeric features for describing such images that are fairly robust to image intensity binning and spatial resolution. We validate these features by using them to train neural networks that accurately recognize all major subcellular patterns with an accuracy higher than any previously reported. Having validated the features by using them for classification, we also demonstrate using them to create Subcellular Location Trees that group similar proteins and provide a systematic framework for describing subcellular location.
Improving menu placement strategies for pen input
Authors: Mark S. Hancock, Kellogg S. Booth
Venue: Proceedings of Graphics Interface 2004 (2004)

We investigate menu selection in circular and rectangular pop-up menus using stylus-driven direct input on horizontal and vertical display surfaces. An experiment measured performance in a target acquisition task in three different conditions: direct input on a horizontal display surface, direct input on a vertical display and indirect input to a vertical display. The third condition allows comparison of direct and indirect techniques commonly used for vertical displays. The results of the study show that both left-handed and right-handed users demonstrate a consistent, but mirrored pattern of selection times that is corroborated by qualitative measures of user preference. We describe a menu placement strategy for a tabletop display that detects the handedness of the user and displays rectangular pop-up menus. This placement is based on the results of our study.
Self-organization in SOI FET
Authors: V. N. Dobrovolsky, L. V. Ishchuk, G. K. Ninidze, S. P. Pavljuk, Y. O. Plichko
Venue: Microelectronic Engineering (2004)

Silicon-on-Insulator Field-Effect Transistors were investigated at extremely high drain currents. These currents heat the silicon film of transistor and cause the generation of thermal electron-hole plasma there. We discovered the red light emission from such plasma. It appears after the extinction of known yellowish-white emission and is of thermal nature. The emitting sections of the film are in the shape of spots. They are regularly arranged in the transistor drain area. The number of spots increases with the current growth. S-shape sections on both the current--voltage and luminous-current characteristics correspond to the appearance of each new spot. Plasma stratification and formation of luminous spots are explained by the occurrence of thermodiffusion autosolitons in the plasma.
Stabilizing Execution Time of User Processes by Bottom Half Scheduler in Linux
Authors: Kyong Jo Jung, Seok Gan Jung, Chanik Park
Venue: Proceedings of the 16th Euromicro Conference on Real-Time Systems (2004)

The CPU time allocated to user processes isrendered inaccurate by an unexpectedly and frequentlyoccurring interrupt and a bottom half thatconsumes most interrupt processing time. Additionally,when the time consumed in the kernelmode greatly fluctuates with interrupt processing,the scheduler cannot distribute CPU time to userprocesses normally. This problem can dramaticallydistort the stable execution time of user processes.In addition, such time-sensitive applicationsas multimedia players cannot provide consistentquality. To overcome this stolen-time problem,we propose a bottom half scheduling approachthat dynamically restricts the maximum time consumedby bottom halves. In this paper, we implementour proposed scheme in Linux 2.4. In addition,we show that the fluctuation of CPU timeallocated to user processes by stolen-time can beshrunk with our proposed scheme by means of experimentsusing a multimedia application.
Imputation of Missing Values in DNA Microarray Gene Expression Data
Authors: Hyunsoo Kim, Gene H. Golub, Haesun Park
Venue: Proceedings of the 2004 IEEE Computational Systems Bioinformatics Conference (2004)

Most multivariate statistical methods for gene expression data require a complete matrix of gene array values. In this paper, a imputation method based on least squares formulation is proposed to estimate missing values. It exploits local similarity structures in the data as well as least squares optimization process. The proposed local least squares imputation method (LLSimpute) represents a target gene that has missing values as a linear combination of similar genes. This algorithm showed better performance than the other imputation methods such as k-nearest neighbor imputation and an imputation method base on Bayesian principal component analysis.
Centered prescribed-order approximations with structured grids and resulting finite-volume schemes
Authors: Andrei I. Tolstykh
Venue: Applied Numerical Mathematics (2004)

A novel arbitrary-order discretization technique based on linear combinations of centered compact operators is outlined. Using finite-volume principle, prescribed-order differencing and interpolation formulas as well as multioperators difference schemes are constructed. Numerical examples showing that the schemes have potential for being extremely accurate are presented.
SCIDIVE: A Stateful and Cross Protocol Intrusion Detection Architecture for Voice-over-IP Environments
Authors: Yu-Sung Wu, Saurabh Bagchi, Sachin Garg, Navjot Singh, Tim Tsai
Venue: Proceedings of the 2004 International Conference on Dependable Systems and Networks (2004)

Voice over IP (VoIP) systems are gaining inpopularity as the technology for transmitting voice trafficover IP networks. As the popularity of VoIP systemsincreases, they are being subjected to different kinds ofintrusions some of which are specific to such systems andsome of which follow a general pattern. VoIP systemspose several new challenges to Intrusion DetectionSystem (IDS) designers. First, these systems employmultiple protocols for call management (e.g., SIP) anddata delivery (e.g., RTP). Second, the systems aredistributed in nature and employ distributed clients,servers and proxies. Third, the attacks to such systemsspan a large class, from denial of service to billing fraudattacks. Finally, the systems are heterogeneous andtypically under several different administrative domains.In this paper, we propose the design of an intrusiondetection system targeted to VoIP systems, called SCIDIVE(pronounced "Skydive"). SCIDIVE is structured to detectdifferent classes of intrusions, including, masquerading,denial of service, and media stream-based attacks. It canoperate with both classes of protocols that compose VoIPsystems - call management protocols (CMP), e.g., SIP,and media delivery protocols (MDP), e.g., RTP. SCIDIVEproposes two abstractions for VoIP IDS .Statefuldetection and Cross-protocol detection. Stateful detectiondenotes assembling state from multiple packets and usingthe aggregated state in the rule matching engine. Crossprotocol detection denotes matching rules that spanmultiple protocols. SCIDIVE is demonstrated on a sampleVoIP system that comprises SIP clients and SIP proxyservers with RTP as the data delivery protocol. Fourattack scenarios are created and the accuracy and theefficiency of the system evaluated with rules meant tocatch these attacks.
Initial Sizing of Analog Integrated Circuits by Centering Within Topology-Given Implicit Specification
Authors: Guido Stehr, Michael Pronath, Frank Schenkel, Helmut Graeb, Kurt Antreich
Venue: Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design (2003)

We present a novel technique to automatically calculate an initialsizing of analog circuits that conforms to good design practice.The method is purely (DC) simulation-based and does not needsymbolic design equations or user design knowledge. It identifiesthe space of feasible design parameters based on implicit specifications, which arise from the circuit topology. A sizing centeredwithin this space is obtained by iteratively solving a maximum volume ellipsoid problem on approximations to the feasible parameter space. The result is well-suited as initial sizing because it safely satisfies all implicit specifications. Experimental results demonstrate the efficiency and reliability of our method.
A Parallel VLSI Architecture for 1-Gb/s, 2048-b, Rate-1/2 Turbo Gallager Code Decoder
Authors: P. Ciao, G. Colavolpe, L. Fanucci
Venue: Proceedings of the Digital System Design, EUROMICRO Systems (2004)

This paper presents a 2048 bit, rate ½ soft decision decoder for a new class of codes known as Turbo Gallager Codes. The decoder can support up to 1 Gbit/s code rate and performs up to 48 decoding iteration ensuring at the same time high throughput and good coding gain. In order to evaluate the performance and the gate complexity of the decoder VLSI architecture, it has been synthesized in a 0.18 µm standard-cell CMOS technology.
The RF-CV method for characterization of leaky gate dielectrics
Authors: J. Schmitz, F. N. Cubaynes, R. de Kort, R. Havens, A. J. Scholten, L. F. Tiemeijer
Venue: Microelectronic Engineering (2004)

This paper presents a new method, developed for the capacitance-voltage (C-V) characterization of leaky dielectrics. The method comprises measurements in the gigahertz range on specially designed RF test structures. The method is verified against high-frequency C-V measurements on NMOS and PMOS structures. It yields reliable results even when the gate leakage is in excess of 100 A/cm2.
Influence of total-dose radiation on the electrical characteristics of SOI MOSFETs
Authors: J. A. Felix, J. R. Schwank, C. R. Cirba, R. D. Schrimpf, M. R. Shaneyfelt, D. M. Fleetwood, P. E. Dodd
Venue: Microelectronic Engineering (2004)

Silicon-on-insulator (SOI) technologies, have been developed for radiation-hardened applications for many years and are rapidly becoming a main-stream commercial technology. The total dose response of SOI devices is more complex than for bulk-silicon devices due to the buried oxide. Radiation-induced trapped charge in the buried oxide can increase the leakage current of partially-depleted transistors and decrease the threshold voltage and increase the leakage current of fully-depleted transistors. We review process and design techniques that have been developed to reduce the net amount of radiation-induced positive charge trapped in the buried oxide or to mitigate the effects of trapped charge in the buried oxide, respectively. We also compare the total dose response of devices operated in single-gate (SO) and double-gate (DG) mode as a function of silicon film thickness. DG-MOSFETs are systematically less sensitive to radiation-induced trapped charge and interface trap.
Functional Modules from Protein Networks of Kinome and Cell Cycle in Saccharomyces Cerevisiae
Authors: Hee Young Kang, Hak Yong Kim
Venue: Proceedings of the 2004 IEEE Computational Systems Bioinformatics Conference (2004)

We have constructed protein networks of kinome and cell cycle from MIPS database. The networks show character of scale free network, in which a few highly connected proteins play a central role in most cells. Protein-protein interaction database obtained from a yeast two hybrid screen or a composite data set includes random false positives. To purify the database, we employed cellular localization and DNA expression profile and then reconstructed kinome and cell cycle networks. The kinome and cell cycle networks constructed from the purified database show characters of scale free network and hierarchical network, in which preserves it's scale-free organization and displays inherent modularity of protein clusters. To find functional modules from the network, we propose a new technique that is based on multi-body correlations in kinome or cell cycle network. From the derived modules, we predicted and estimated tentative functions for unannotated proteins with high certainty.
How Biological Source Capabilities May Affect the Data Collection Process
Authors: Zoe Lacroix, Vidyadhari Edupuganti
Venue: Proceedings of the 2004 IEEE Computational Systems Bioinformatics Conference (2004)

Scientific discovery relies partially on the collection of information related to multiple scientific objects (e.g., "Retrieve all genes involved in brain cancer", "Retrieve all citations related to diabetes"). Scientists are interested in exploring multiple data sources in order to explore relationships between scientific objects. Each data source provides specific capabilities that allow scientists to access, navigate, and analyze the data. This work addresses the impact of resource selection (data source and capability) in the data collection process as it may affect significantly the quality and completeness of the data. We present preliminary research that demonstrates that the data collection process depends on two orthogonal variables: the data sources involved in the process, and the selection of capabilities available at these resources. We report the results for four commonly used biological resources: the NCBI Nucleotide, Protein, PubMed and OMIM databases.
Automata over MV-Algebras
Venue: Proceedings of the 34th International Symposium on Multiple-Valued Logic (2004)

We propose the notion of automata over ¿ukasiewiczmany-valued logic, extending fuzzy automata ([9]).Indeed, MV-algebras, i.e., algebraic structures relatedwith many-valued ¿ukasiewicz logic, are made oftwo semiring reducts obtained considering the supremumoperation together with the ¿ukasiewicz conjunctionand the infimum operation together with¿ukasiewicz disjunction. Vice-versa, given two semiringsover the same domain, and given an isomorphismbetween these two algberas we can set some conditionsin order to have an MV-algebra.Following the tradition of semirings, in this paper weshall study "many-valued automata" and "many-valuedformal languages" interpreted in ¿ukasiewicz logic.
User Validation of Image Quality Assessment Algorithms
Venue: Proceedings of the Theory and Practice of Computer Graphics 2004 (TPCG'04) (2004)

Even with modern graphics hardware, it is still notpossible to achieve high fidelity renderings of complexscenes in real time. However, as these images areproduced for human observers we may exploit the factthat the human eye is good, but not that good. Inparticular, it may be possible to render parts of animage at high quality and the rest of the scene at lowerquality without the user being aware of this difference.Image quality assessment algorithms, such as the Dalymodel, provide a measure of the perceptual qualitydifference between image pairs. This paper presents apsychophysical evaluation of an image quality metricand investigates how such models can be developed torapidly determine the parts of the scene with the mostnoticeable perceptual difference.
SMTp: An Architecture for Next-generation Scalable Multi-threading
Authors: Mainak Chaudhuri, Mark Heinrich
Venue: Proceedings of the 31st annual international symposium on Computer architecture (2004)

We introduce the SMTp architecture-an SMT processoraugmented with a coherence protocol thread context,that together with a standard integrated memory controllercan enable the design of (among other possibilities) scalablecache-coherent hardware distributed shared memory(DSM) machines from commodity nodes. We describe theminor changes needed to a conventional out-of-order multi-threadedcore to realize SMTp, discussing issues related toboth deadlock avoidance and performance. We then compareSMTp performance to that of various conventionalDSM machines with normal SMT processors both with andwithout integrated memory controllers. On configurationsfrom 1 to 32 nodes, with 1 to 4 application threads pernode, we find that SMTp delivers performance comparableto, and sometimes better than, machines with more complexintegrated DSM-specific memory controllers. Our resultsalso show that the protocol thread has extremely lowpipeline overhead. Given the simplicity and the flexibility ofthe SMTp mechanism, we argue that next-generation multi-threadedprocessors with integrated memory controllersshould adopt this mechanism as a way of building less complexhigh-performance DSM multiprocessors.
Diminished-1 Modulo 2^n + 1 Squarer Design
Authors: H. T. Vergos, C. Efstathiou
Venue: Proceedings of the Digital System Design, EUROMICRO Systems (2004)

Squarers modulo M are useful design blocks for digital signal processors that internally use a residue number system and for implementing the exponentiators required in cryptographic algorithms.In these applications, some of the most commonly used moduli are those of the form 2^n + 1. To avoid using (n + 1)-bit circuits, the diminished-1 number system can be effectively used in modulo 2^n + 1 arithmetic applications.In this paper, for the first time in the open literature, we formally derive modulo 2^n + 1 squarers that adopt the diminished-1 number system.The resulting implementations are built using only full- or half-adders and a final diminished-1 adder and can therefore be pipelined straightforwardly.
Solving Equations in the Relational Algebra
Authors: Joachim Biskup, Jan Paredaens, Thomas Schwentick, Jan Van den Bussche
Venue: SIAM Journal on Computing (2004)

Enumerating all solutions of a relational algebra equation is a natural and powerful operation which, when added as a query language primitive to the nested relational algebra, yields a query language for nested relational databases, equivalent to the well-known powerset algebra. We study sparse equations, which are equations with at most polynomially many solutions. We look at their complexity and compare their expressive power with that of similar notions in the powerset algebra.
&#x00d5;(Congestion + Dilation) Hot-Potato Routing on Leveled Networks
Authors: Costas Busch
Venue: Theory of Computing Systems (2004)

We study packet routing problems, in which we are given a set of N packets which will be sent on preselected paths with congestion C and dilation D. For store-and-forward routing, in which nodes have buffers for packets in transit, there are routing algorithms with a performance that matches the lower bound &#x03a9;(C+D). Motivated from optical networks, we study hot-potato routing in which the nodes are bufferless. Due to the lack of buffers, in hot-potato routing the packets may be delayed more than in store-and-forward routing. An interesting question is how much is the performance of routing algorithms affected by the absence of buffers.Here, we answer this question for the class of leveled networks, in which the nodes are partitioned into L+1 distinct levels. We present a randomized hot-potato routing algorithm for leveled networks, which routes the packets in O((C + L) ln9 (LN)) time with high probability. For routing problems with dilation &#x03a9;(L), and where N is a polynonial in L, this bound is within polylogarithmic factors of the lower bound &#x03a9;(C+L). Our algorithm demonstrates that for such routing problems the benefit from using buffers is no more than polylogarithmic; thus, hot-potato routing is an efficient way to route packets in leveled networks.In hot-potato routing, due to the lack of buffers, the packets may not be able to remain on their preselected paths during the course of routing (while in store-and-forward routing the packets remain on their preselected paths). However, in our algorithm the actual path that each packet follows contains its original preselected path; thus the lower bound &#x03a9;(C+L) is also a lower bound for the new paths. Our algorithm is distributed, that is, routing decisions are taken locally at each node while packets are routed in the network. To our knowledge, this is the first hot-potato algorithm designed and analyzed, in terms of congestion and dilation, for leveled networks.
The field of programmers myth
Authors: Peter J. Denning
Venue: Communications of the ACM (2004)

The persistent public image of computing as a field of programmers has become a costly myth. Reversing it is possible but not easy.