ppxscal/embedding_network huggingface dataset:
Comparative for Middleware Video Streaming Services
Authors: Antonio-Javier Garcia-Sanchez, Felipe Garcia-Sanchez, Joan Garcia-Haro
Venue: Proceedings of the International Conference on Software Engineering Advances (2007)

Software technologies to implement distributed multimedia services currently require intensive network and computing resources. In many environments, the design of these services on top of a general-purpose middleware layer is the usual choice. CORBA, Java RMI and .NET are major representatives of this approach. This paper describes and compares the three aforementioned middleware alternatives by evaluating the performance of the implementation of A/V Streaming services on top. From this comparison, several key points and implementation details are highlighted.
Knot invariants and the Bollobás-Riordan polynomial of embedded graphs
Authors: Iain Moffatt
Venue: European Journal of Combinatorics (2008)

For a graph G embedded in an orientable surface @S, we consider associated links L(G) in the thickened surface @SxI. We relate the HOMFLY polynomial of L(G) to the recently defined Bollobas-Riordan polynomial of a ribbon graph. This generalizes celebrated results of Jaeger and Traldi. We use knot theory to prove results about graph polynomials and, after discussing questions of equivalence of the polynomials, we go on to use our formulae to prove a duality relation for the Bollobas-Riordan polynomial. We then consider the specialization to the Jones polynomial and recent results of Chmutov and Pak to relate the Bollobas-Riordan polynomials of an embedded graph and its tensor product with a cycle.
A Balanced Pipelining Approach to Multiprocessing on an Instruction Stream Level
Authors: J. M. Kurtzberg
Venue: IEEE Transactions on Computers (1973)

This paper presents an approach to achieve high central processing unit (CPU) availability with an increase in performance by multiprocessing on an instruction stream level, where instruction fetching/executing is done by closely coupled processing units (PU's). A treatment is given of the necessary control for coordination of the PU's. This processing interaction is accomplished by microcode shared by the units. Either PU can be interchanged in any processing function, and the total processing complex comprises a single CPU as far as the external world (i. e., the operating system and user's programs) is concerned. The results of manual simulation on two sample problems are given along with a comparison of processing with a single PU and with another instruction stream multiprocessing scheme presented in [4].
Hybrid architectures for efficient and secure face authentication in embedded systems
Authors: Najwa Aaraj, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
Venue: IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2007)

In this paper, we propose an efficient and secure embedded processing architecture that addresses various challenges involved in using face-based biometrics for authenticating a user to an embedded system. Our paper considers the use of robust face verifiers (PCA-LDA, Bayesian), and analyzes the computational workload involved in running their software implementations on an embedded processor. We then present a suite of hardware and software enhancements to accelerate these algorithms--fixed-point arithmetic, various code optimizations, generic custom instructions and dedicated coprocessors, and exploitation of parallel processing capabilities in multiprocessor systems-on-chip (SoCs). We also identify attacks targeted against the authentication process, and develop security measures to ensure the integrity of biometric code/data. We evaluated the proposed architectures in the context of popular open-source software implementations of face authentication algorithms running on a commercial embedded processor (Xtensa from Tensilica). Our paper shows that fast, in-system verification is possible even in the context of many resource-constrained embedded systems. We also demonstrate that the security of the authentication process for the given attack model can be achieved with minimum hardware overheads.
Evaluation of distributed cover set algorithms in mobile ad hoc network for simplified multicast forwarding
Authors: Joseph Macker, Ian Downard, Justin Dean, Brian Adamson
Venue: ACM SIGMOBILE Mobile Computing and Communications Review (2007)

This paper presents design issues and performance analysis of optimized cover set algorithms supporting Simplified Multicast Forwarding (SMF) of data plane traffic within mobile ad hoc network (MANET) environments. SMF is presently being developed within the Internet Engineering Task Force (IETF) as an experimental specification to provide simplified multicast data dissemination among multi-hop, wireless nodes within peer MANET routing neighborhoods. The SMF protocol allows for a variety of cover set reduction techniques to optimize the simplified data flooding and relaying process amongst routing peers. A variety of distributed algorithms for forming connected dominating sets (CDS) are being considered as mechanisms to reduce the cover set. This paper presents modeling and analysis work of various CDS relay set algorithms and demonstrates working code within an SMF implementation. We provide a brief problem background, discuss models and scenarios, compare various algorithms, and then summarize observations as well as discuss future work. A main purpose of the paper is to begin examining the robustness of the algorithms to mobility and increasing multicast traffic load. We examine the results against a classical flooding baseline for comparison. We observe similar efficiency and robustness performance for several forwarding algorithms of interest.
A channelized digital receiver design for UWB systems in a multi-path indoor environment
Authors: Mario E. Magaña, Yuhao Chang
Venue: Wireless Personal Communications: An International Journal (2007)

Due to the very wide bandwidth of UWB system, it is hard if not impossible to design high speed and high resolution ADCs with today's technology. This problem can be solved if the received UWB signal is split into a number of subbands by power splitters, analog low-pass filters, mixers and digital filters. By doing this, each of subbands can be sampled at a fraction of effective sampling frequency. In this paper, we present a simpler channelized receiver architecture for UWB systems than previously published work. Moreover, we present a new, though more complex, channelized receiver design for UWB systems in a multipath propagation environment. We also show through simulation that this new receiver achieves very good BER performance.
Design And Test of the 80386
Authors: Patrick Gelsinger
Venue: IEEE Design Test (1987)

A complex design effort, the 80386 was nevertheless one of the company's most successful projects. The work was completedin less time than scheduled and set an Intel record for tapeout to mask fabricator. The strategy incorporated both top-downand bottom-up design approaches. The top-down flow was external architectural definition, internal architecture, internalunit RTL (register transfer logic) and finally detailed logic. The bottom-up flow was detailed transistor and cell circuitdesign and layout, block (ALU, PLA, etc.) circuit design and layout, and finally global circuit design and layout. Testabilityalso played an important part in the design's success. The 80386 combines two forms of designed-in test functions: built-inself-test and test hooks or functions explicitly designed in to aid testing.
Multi-layer neural network analysis of cerebrospinal fluid pressure patterns in idiopathic normal-pressure hydrocephalus
Authors: P. Mazzone, L. Fortuna, P. Arena, R. Pisani
Venue: Technology and Health Care (1996)

The cerebrospinal fluid (CSF) pressure patterns have been reported as one of the most relevant indexes for the diagnosis and treatment of idiopathic normal-pressure hydrocephalus (INPH). Forty consecutive patients coming from our observations with the classic Hakims triad underwent continuous CSF pressure monitoring via lumbar puncture for at least 12 hours. Twenty-eight patients were diagnosed as having INPH and underwent CSF shunt. A multi-layer neural network (perceptron) was employed to study the pressure patterns in order to try an alternative classification to the expert neurosurgeon one. Differences between expert and neural network classifications were indeed observed. Such differences may depend on the small group studied or on the inadequacy of CFS pressure patterns in correctly individuating those INPH patients who benefit from shunt surgery. The authors think that neural network processing of INPH could add relevant information to select the responder patients to surgery: in fact neural networks represent a powerful methodology for aiding the expert to select the proper choice on the basis of what learnt by the networks themselves.
Depth silhouettes for gesture recognition
Authors: Rafael Muñoz-Salinas, R. Medina-Carnicer, F. J. Madrid-Cuevas, A. Carmona-Poyato
Venue: Pattern Recognition Letters (2008)

This paper, evaluates the influence of depth information on the gesture recognition process. We propose depth silhouettes, a natural extension of the binary silhouette concept, as a mechanism to incorporate depth information for gesture recognition. Using depth silhouettes, we define extensions of three classic techniques employed previously for gesture recognition with monocular vision. These include: (a) silhouette compression using PCA and learning with HMM; (b) an exemplar-based gesture recognition using HMM; and (c) temporal templates that in this work are compressed using PCA and learned with SVM. The results obtained show that, independently of the technique employed, the use of depth silhouettes increases the success significantly. Additionally, we show how the best results are obtained through the combined use of PCA and HMM.
A fast CT reconstruction scheme for a general multi-core PC
Authors: Kai Zeng, Erwei Bai, Ge Wang
Venue: Journal of Biomedical Imaging (2007)

Expensive computational cost is a severe limitation in CT reconstruction for clinical applications that need real-time feedback. A primary example is bolus-chasing computed tomography (CT) angiography (BCA) that we have been developing for the past several years. To accelerate the reconstruction process using the filtered backprojection (FBP) method, specialized hardware or graphics cards can be used. However, specialized hardware is expensive and not flexible. The graphics processing unit (GPU) in a current graphic card can only reconstruct images in a reduced precision and is not easy to program. In this paper, an acceleration scheme is proposed based on a multi-core PC. In the proposed scheme, several techniques are integrated, including utilization of geometric symmetry, optimization of data structures, single-instruction multiple-data (SIMD) processing, multithreaded computation, and an Intel C++ compilier. Our scheme maintains the original precision and involves no data exchange between the GPU and CPU. The merits of our scheme are demonstrated in numerical experiments against the traditional implementation. Our scheme achieves a speedup of about 40, which can be further improved by several folds using the latest quad-core processors.
HiFi: a unified architecture for high fan-in systems
Authors: Owen Cooper, Anil Edakkunni, Michael J. Franklin, Wei Hong, Shawn R. Jeffery, Sailesh Krishnamurthy, Fredrick Reiss, Shariq Rizvi, Eugene Wu
Venue: Proceedings of the Thirtieth international conference on Very large data bases - Volume 30 (2004)

Advances in data acquisition and sensor technologies are leading towards the development of "High Fan-in" architectures: widely distributed systems whose edges consist of numerous receptors such as sensor networks and RFID readers and whose interior nodes consist of traditional host computers organized using the principle of successive aggregation. Such architectures pose significant new data management challenges. The HiFi system, under development at UC Berkeley, is aimed at addressing these challenges. We demonstrate an initial prototype of HiFi that uses data stream query processing to acquire, filter, and aggregate data from multiple devices including sensor motes, RFID readers, and low power gateways organized as a High Fan-in system.
Anytime measures for top-k algorithms
Authors: Benjamin Arai, Gautam Das, Dimitrios Gunopulos, Nick Koudas
Venue: Proceedings of the 33rd international conference on Very large data bases (2007)

Top-k queries on large multi-attribute data sets are fundamental operations in information retrieval and ranking applications. In this paper, we initiate research on the anytime behavior of top-k algorithms. In particular, given specific top-k algorithms (TA and TA-Sorted) we are interested in studying their progress toward identification of the correct result at any point during the algorithms' execution. We adopt a probabilistic approach where we seek to report at any point of operation of the algorithm the confidence that the top-k result has been identified. Such a functionality can be a valuable asset when one is interested in reducing the runtime cost of top-k computations. We present a thorough experimental evaluation to validate our techniques using both synthetic and real data sets.
Improving Probabilistic Route Discovery in Mobile Ad Hoc Networks
Authors: J. Abdulai, M. Ould-Khaoua, L. M. Mackenzie
Venue: Proceedings of the 32nd IEEE Conference on Local Computer Networks (2007)

Conventional on-demand route discovery methods in Mobile Ad hoc Networks (MANET) employ blind flooding, where a mobile node blindly rebroadcasts received Route Request (RREQ) packets until a route to a particular destination is established. This can potentially lead to high channel contention, causing redundant retransmissions and thus excessive packet collisions in the network. Such a phenomenon induces what is known as broadcast storm problem, which has been shown to greatly increase the network communication overhead and end-to- end delay. In this paper, we show that the deleterious impact of such a problem can be reduced if measures are taken during the dissemination of RREQ packets. We propose two new probabilistic methods for on-demand route discovery, that is simple to implement and can significantly reduce the overhead involved in the dissemination of RREQs. Our analysis reveals that equipping AODV with probabilistic route discovery can result in significant performance improvements on all the standard metrics.
Cryptol: specification, implementation and verification of high-grade cryptographic applications
Authors: Jeff Lewis
Venue: Proceedings of the 2007 ACM workshop on Formal methods in security engineering (2007)

Communications security is paramount in defense applications. Thus cryptographic algorithms are employed everywhere, from smart cards to hand-held field radios to central servers. The cryptography has to be strong (no-one can break the algorithm), correctly and securely implemented (no-one can hack the code), and efficient (you don't notice it is being used). It can be very expensive to deploy high-grade cryptographic applications. Much of the cost is to meet certification requirements, where evaluators (independent crypto experts) analyze every aspect of the design and implementation, with full access to the source code. As a developer, the on us is on you: unless you can convince the evaluators your crypto-device is correct and secure, it will be rejected. At Galois, we have been developing Cryptol, a domain-specific language and tool set for formally specifying, implementing, and verifying cryptographic algorithms. Cryptol is intended to dramatically reduce the cost of crypto certification and deployment. We have employed a variety of lightweight (i.e. highly automatable)formal methods towards this: Formal Specification. Cryptol has a precise, declarative semantics and a sophisticated type system for describing the exact functional behavior of a cryptographic algorithm. Compilation and Synthesis. The Cryptol toolset includesa reference Cryptol-to-C compiler, and an optimizing Cryptol-to-FPGA synthesizer. Cryptol's type system and stream transformer semantics allows the FPGA synthesizer to perform aggressive optimizations. For example, we have been able to specify a pipelined AES circuit in Cryptol that gets synthesized into an FPGA circuit whose throughput is competitive with the best-known hand-written FPGA implementations of AES. Formal Verification. The Cryptol toolset includes aSAT-based bounded equivalence checker for statically checking that a C, VHDL, or Cryptol implementation of a crypto algorithm has the same behavior as its "golden reference" Cryptol specification(up to a fixed number of clock cycles). We will describe our experiences in applying lightweight formal methods to Cryptol, as well as current research challenges.
A Novel Opposition-Based Particle Swarm Optimization for Noisy Problems
Authors: Lin Han, Xingshi He
Venue: Proceedings of the Third International Conference on Natural Computation - Volume 03 (2007)

Particle Swarm Optimization (PSO) is a simple, reliable, and efficient optimization algorithm. However, it suffers from a weakness, losing the efficiency over optimization of noisy problems. In many real-word optimization problems we are faced with noisy environments. This paper presents a new algorithm to improve the efficiency of PSO to cope with noisy optimization problems. It employs opposition-based learning for swarm initialization, generation jumping, and also improving swarm's best member. A set of commonly used benchmark functions is employed for experimental verification, and the results show clearly the new algorithm outperforms PSO in terms of convergence speed and global search ability.
Securisation of SIP Presence notifications thanks to the Belgian electronic identity card
Authors: Sebastien Gamby, Laurent Schumacher, Jean Ramaekers
Venue: Proceedings of the The 2007 International Conference on Next Generation Mobile Applications, Services and Technologies (2007)

This article is dealing with the use of the Belgian electronic ID card to secure Presence notifications in the Session Initiation Protocol (SIP). More specifically, it addresses the secure authentication to a SIP registrar server thanks to the Belgian electronic ID card. The proposed solution consists in adding an Authenticated Identity Body (AIB) to the REGISTER requests issued by the user's agent, which simultaneously authenticates the user and protects the request header.
Software Design Representation Using Abstract Process Networks
Authors: L. J. Mekly
Venue: IEEE Transactions on Software Engineering (1980)

An approach to software design representation which is consistent with the concept of engineering blueprints is presented. The main criteria for software engineering blueprints are defined and a network scheme of graphical representation is considered through an overview of Petri net techniques. The concept of an abstract process (AP) is introduced as the basic element of system representation. An abstract process network schema of software design representation is developed and supported by an algebraic system of notation. Methods of AP-net construction are presented and illustrated by examples. The advantages of using the proposed approach in different phases of software engineering are pointed out and the main directions for further research have been identified.
On the Impact of Communication Complexity on the Design of Parallel Numerical Algorithms
Authors: D. B. Gannon
Venue: IEEE Transactions on Computers (1984)

This paper describes two models of the cost of data movement in parallel numerical algorithms. One model is a generalization of an approach due to Hockney, and is suitable for shared memory multiprocessors where each processor has vector capabilities. The other model is applicable to highly parallel nonshared memory MIMD systems. In this second model, algorithm performance is characterized in terms of the communication network design. Techniques used in VLSI complexity theory are also brought in, and algorithm-independent upper bounds on system performance are derived for several problems that are important to scientific computation.
A Class of Redundant Path Multistage Interconnection Networks
Authors: K. Padmanabhan
Venue: IEEE Transactions on Computers (1983)

A general class of fault-tolerant multistage interconnection networks is presented, wherein fault-tolerance is achieved by providing multiple disjoint paths between every input and output. These networks are derived from the Omega networks and as such retain all the connection properties of the parent networks in the absence of faults. An R-path network in this class can tolerate (R-1) arbitrary faults in the intermediate stages of the network at a cost that is far less than providing R copies of the original network. Different techniques for constructing such networks are presented and relevant properties and control algorithms are investigated.
Architecting security: a secure implementation of hardware buffer-overflow protection
Authors: Krerk Piromsopa, Richard J. Enbody
Venue: Proceedings of the third conference on IASTED International Conference: Advances in Computer Science and Technology (2007)

Piromsopa and Enbody [1] proposed Secure Bit, a mechanism to protect against buffer overflow attacks on control data (return-addresses and function-pointers). This paper explores the architecture of Secure Bit: its implementation and its performance impact. We consider memory organization, cache organization, and processor modifications. Secure Bit provides a hardware bit and protocol to protect the integrity of addresses for the purpose of preventing buffer-overflow attacks. If an address is corrupted, an exception is raised. By changing only the semantics of the ISA Secure Bit is transparent to user software. An important differentiating aspect is that once an address has been marked as insecure there is no instruction to remark the address as secure. Our study shows that the implementation is straightforward. In particular, we find that cache organization is a critical component to the performance and success of Secure Bit.