ppxscal/embedding_network huggingface dataset:
Computing All Small Cuts in an Undirected Network
Authors: Hiroshi Nagamochi, Kazuhiro Nishimura, Toshihide Ibaraki
Venue: SIAM Journal on Discrete Mathematics (1997)

Let $\lambda({\cal N})$ denote the weight of a minimum cut in an edge-weighted undirected network ${\cal N}$, and $n$ and $m$ denote the numbers of vertices and edges, respectively. It is known that $O(n^{2k})$ is an upper bound on the number of cuts with weights less than $k\lambda({\cal N})$, where $k\geq 1$ is a given constant. This paper first shows that all cuts of weights less than $k\lambda({\cal N})$ can be enumerated in $O(m^2n+n^{2k}m)$ time without using the maximum flow algorithm. The paper then proves for $k
Stubborn Sets for Real-Time Petri Nets
Authors: Robert H. Sloan, Ugo Buy
Venue: Formal Methods in System Design (1997)

The stubborn-set method attempts to reduce the number of states that must be explicitly enumerated during reachability analysis of a concurrent system, while preserving crucial concurrency properties in the reduced state space. Here we extend the method to the analysis of certain timed models. We also prove that timing properties of interest, such as minimum and maximum delays between events, are preserved in the reduced model. Finally, we report on some experimental results that we have obtained with our extension. These results show that real-time stubborn sets can often provide significant reductions in state space size.
Knowledge acquisition in support of artificial intelligence: an example and some lessons learned
Authors: Martin S. Kleiner, Scott A. Carey
Venue: Proceedings of the 28th conference on Winter simulation (1996)

The Defense Advanced Research Projects Agency (DARPA) Command Forces (CFOR) program has under taken the development of intelligent agents to perform the function of command and control within advanced warfighting simulations. While service-related tactics and doctrine publications provide a general description of what a commander must do, they do -not address the cognitive processes that are applied during command decision making. Furthennore, existing material is not in a format that lends itself to knowledge engineering. DARPA instituted a focused knowledge acquisition (KA) effort as a component of its Synthetic Theater of War (STOW) program to support the development of intelligent command entities (CES). This paper presents the methodology and products that have been created to support the development of Army CEs within the STOW CFOR program. Additionally, it provides some insights and lessons learned that may have applicability across a wide field of KA efforts.
Time-Optimal Domain-Specific Querying on Enhanced Meshes
Authors: Venkatavasu Bokka, Himabindu Gurla, Stephan Olariu, James L. Schwing, Larry Wilson
Venue: IEEE Transactions on Parallel and Distributed Systems (1997)

Query processing is a crucial component of various application domains including information retrieval, database design and management, pattern recognition, robotics, and VLSI. Many of these applications involve data stored in a matrix satisfying a number of properties. One property that occurs time and again specifies that the rows and the columns of the matrix are independently sorted. It is customary to refer to such a matrix as sorted. An instance of the Batched Searching and Ranking problem, (BSR, for short) involves a sorted matrix A of items from a totally ordered universe, along with a collection Q of queries. Q is an arbitrary mix of the following query types: For a search query q¿j, one is interested in an item of A that is closest to q¿j; for a rank query q¿j one is interested in the number of items of A that are strictly smaller than q¿j. The BSR problem asks for solving all queries in Q. In this work, we consider the BSR problem in the following context: The matrix A is pretiled, one item per processor, onto an enhanced mesh of size $\sqrt n\times \sqrt n$; the m queries are stored, one per processor, in the first ${{m \over {\sqrt n}}}$ columns of the platform. Our main contribution is twofold. First, we show that any algorithm that solves the BSR problem must take at least $\Omega ({\rm max\{log}n,\sqrt m\})$ time in the worst case. Second, we show that this time lower bound is tight on meshes of size $\sqrt n\times \sqrt n$ enhanced with multiple broadcasting, by exhibiting an algorithm solving the BSR problem in $\Theta ({\rm max\{log}\!\!n,\sqrt m\})$ time on such a platform.
Concurrent Detection of Software and Hardware Data-Access Faults
Authors: Kent D. Wilken, Timothy Kong
Venue: IEEE Transactions on Computers (1997)

A new approach allows low-cost concurrent detection of two important types of faults, software and hardware data-access faults, using an extension of the existing signature monitoring approach. The proposed approach detects data-access faults using a new type of redundant data structure that contains an embedded signature. Low-cost fault detection is achieved using simple architecture support and compiler support that exploit natural redundancies in the data structures, in the instruction set architecture, and in the data-access mechanism. The software data-access faults that the approach can detect include faults that have been shown to cause a high percentage of system failures. Hardware data-access faults that occur in all levels of the data-memory hierarchy are also detectable, including faults in the register file, the data cache, the data-cache TLB, the memory address and data buses, etc. Benchmark results for the MIPS R3000 processor executing code scheduled by a modified GNU C Compiler show that the new approach can concurrently check a high percentage of data accesses, while causing little performance overhead and little memory overhead.
A new algorithm for partial redundancy elimination based on SSA form
Authors: Fred Chow, Sun Chan, Robert Kennedy, Shin-Ming Liu, Raymond Lo, Peng Tu
Venue: Proceedings of the ACM SIGPLAN 1997 conference on Programming language design and implementation (1997)

A new algorithm, SSAPRE, for performing partial redundancy elimination based entirely on SSA form is presented. It achieves optimal code motion similar to lazy code motion [KRS94a, DS93], but is formulated independently and does not involve iterative data flow analysis and bit vectors in its solution. It not only exhibits the characteristics common to other sparse approaches, but also inherits the advantages shared by other SSA-based optimization techniques. SSAPRE also maintains its output in the same SSA form as its input. In describing the algorithm, we state theorems with proofs giving our claims about SSAPRE. We also give additional description about our practical implementation of SSAPRE, and analyze and compare its performance with a bit-vector-based implementation of PRE. We conclude with some discussion of the implications of this work.
COSMOS: a continuous optimization approach for maximum power estimation of CMOS circuits
Authors: Chuan-Yu Wang, Kaushik Roy
Venue: Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design (1997)

Maximum instantaneous power in VLSI circuits has a great impact on circuit's reliability and the design of power and ground lines. To synthesize highly reliable systems, accurate estimates of maximum power must be obtained in various design phases. Unfortunately, determining the input patterns to induce the maximum current (power) is essentially a combinatorial optimization problem. Even for circuits with small number of primary inputs (PI's), it is CPU time intensive to conduct exhaustive search in the input vector space. The only feasible way is to find good upper and lower bounds of the maximum power, and to make the gap between these two bounds as narrow as possible. In this paper, we present a continuous optimization approach to efficiently generate tight lower bounds of the maximum instantaneous power for CMOS circuits. In our approach, each primary input (PI) of the circuit is allowed to assume any real number between 0 and 1. Maximum power estimation for CMOS circuits is then transformed into a continuous optimization problem, in which a smooth function is maximized over a unit hypercube in the Euclidean space. The continuous problem can be solved efficiently to generate good lower bounds of the maximum power. Our experiments with ISCAS and MCNC benchmark circuits demonstrate the superiority of this approach. For all the circuits tested, the mean value of the ratio "CPU time of the continuous optimization approach divided by CPU time of the simulation-based technique" is equal to 0.41. For 60% of the circuits tested, our approach gives a better estimate (1.16 times larger, on an average) than the simulation-based technique does. Compared to the ATPG-based technique, the continuous optimization approach generates a tighter lower bound (1.19 times larger, on an average) of maximum power for 60% of all the circuits tested.
Timely Communication: Diagonal Edge Preconditioners in p-version and Spectral Element Methods
Authors: Mario A. Casarin
Venue: SIAM Journal on Scientific Computing (1997)

Domain decomposition preconditioners for high-order Galerkin methods in two dimensions are often built from modules associated with the decomposition of the discrete space into subspaces of functions related to the interior of elements, individual edges, and vertices. The restriction of the original bilinear form to a particular subspace gives rise to a diagonal block of the preconditioner, and the action of its inverse on a vector has to be evaluated in each iteration. Each block can be replaced by a preconditioner in order to decrease the cost. Knowledge of the quality of this local preconditioner can be used directly in a study of the convergence rate of the overall iterative process.The Schur complement of an edge with respect to the variables interior to two adjacent elements is considered. The assembly and factorization of this block matrix are potentially expensive, especially for polynomials of high degree. It is demonstrated that the diagonal preconditioner of one such block has a condition number that increases approximately linearly with the degree of the polynomials. Numerical results demonstrate that the actual condition numbers are relatively small.
PHDD: an efficient graph representation for floating point circuit verification
Authors: Yirng-An Chen, Randal E. Bryant
Venue: Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design (1997)

Data structures such as *BMDs, HDDs, and K*BMDs provide compact representations for functions which map Boolean vectors into integer values, but not floating point values. In this paper, we propose a new data structure, called Multiplicative Power Hybrid Decision Diagrams (*PHDDs), to provide a compact representation for functions that map Boolean vectors into integer or floating point values. The size of the graph to represent the IEEE floating point encoding is linear with the word size. The complexity of floating point multiplication grows linearly with the word size. The complexity of floating point addition grows exponentially with the size of the exponent part, but linearly with the size of the mantissa part. We applied *PHDDs to verify integer multipliers and floating point multipliers before the rounding stage, based on a hierarchical verification approach. For integer multipliers, our results are at least 6 times faster than *BMDs. Previous attempts at verifying floating point multipliers required manual intervention. We verified floating point multipliers before the rounding stage automatically.
Gender imbalance in computer science programs, etiology and amelioration (panel): views for U.S. campuses and elsewhere
Authors: Elizabeth Freeman, Susanne Hupfer, Catherine Lang, Ralph Morelli, Domenick J. Pinto, Frances L. Van Scoy, Sandra Honda Adams
Venue: Proceedings of the twenty-eighth SIGCSE technical symposium on Computer science education (1997)

As a female computer science educator, I've watched with growing alarm the drop in enrollment in our Computer Science programs from a ratio of 1:1 of males and females in 1983, to a current ratio of 5:1. The lack of interest of female students in Computer Science is still a very serious problem. As educators we should all be watching our own campus and addressing this problem. The panelists assembled from various institutions will address the issues of gender imbalance and relate their experiences in implementing solutions to counter this problem. Two of the panelist will discuss utilization of the World Wide Web addressing reasons for creating both Web sites. As long as this gender imbalance exists in our schools we need to continue our dialog to share and develop new ideas to encourage female participation in Computer Science Programs. The audience will be welcomed to participate in a larger group discussion.
Health Risk Assessment for Diabetes Mellitus Based on Longitudinal Analysis of MHTS Database
Authors: Hiroki Sugimori, Michiko Miyakawa, Katsumi Yoshida, Takashi Izuno, Eiko Takahashi, Chieko Tanaka, Kenichi Nakamura, Shigeaki Hinohara
Venue: Journal of Medical Systems (1998)

This study was designed with a follow up of 16 years to provide the epidemiological model evaluating the risk of developing diabetes mellitus in Japan. A cohort of 2573 subjects (1851 males and 722 females) from a MHTS in Tokyo, who were nondiabetic (fasting blood glucose (FBS) less than 110 mg/dl) in the initial year, were selected. This cohort was followed every year to identify the occurrence of diabetes mellitus. Diabetes Mellitus was defined as fasting blood glucose over 110 mg/dl, or the initiation of diabetic therapy. We compared two prognosis groups (a normal group and a diabetic group) in terms of age, examination findings, and prevalence of health risks (lifestyle, stress, and working form). We also assessed family history of diabetes and past histories including hypertension, hypercholesterolemia, and hyperuricemia. After assessing each variable by univariate analysis (t-test, &chi;2 test), we employed Cox's proportional hazards model analysis. We used stepwise model adopting risk factors. The diabetic group had significant differences compared to the normal group in age, BMI (body mass index), FBS, smoking, drinking, not eating breakfast, dairy intake, hypertension, hypercholesterolemia, hyperuricemia, and family history by univariate analysis. According to proportional hazards model analysis, FBS, age, family history, hypertension, smoking, and BMI were incorporated into significant risk factors for diabetes in males, and not eating breakfast, FBS, age, drinking, and hypertension were incorporated in females. Diabetes seemed to be related to fixed factors (age), or genetic factors (family history and FBS) in males. For females, lifestyle (not eating breakfast and drinking habit) seemed to play an important role. It will be worthwhile to assess the risks of developing diabetes mellitus by this epidemiological model.
Trace processors
Authors: Eric Rotenberg, Quinn Jacobson, Yiannakis Sazeides, Jim Smith
Venue: Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture (1997)

Traces are dynamic instruction sequences constructed and cached by hardware. A microarchitecture organized around traces is presented as a means for efficiently executing many instructions per cycle. Trace processors exploit both control flow and data flow hierarchy to overcome complexity and architectural limitations of conventional superscalar processors by (1) distributing execution resources based on trace boundaries and (2) applying control and data prediction at the trace level rather than individual branches or instructions. Three sets of experiments using the SPECInt95 benchmarks are presented. (i) A detailed evaluation of trace processor configurations: the results affirm that significant instruction-level parallelism can be exploited in integer programs (2 to 6 instructions per cycle). We also isolate the impact of distributed resources, and quantify the value of successively doubling the number of distributed elements. (ii) A trace processor with data prediction applied to inter-trace dependences: potential performance improvement with perfect prediction is around 45% for all benchmarks. With realistic prediction, gcc achieves an actual improvement of 10%. (iii) Evaluation of aggressive control flow: some benchmarks benefit from control independence by as much as 10%.
ATPG for heat dissipation minimization during scan testing
Authors: Seongmoon Wang, Sandeep K. Gupta
Venue: Proceedings of the 34th annual Design Automation Conference (1997)

An ATPG technique is proposed that reduces heat dissipationduring testing of sequential circuits that have full-scan. The objectiveis to permit safe and inexpensive testing of low power circuitsand bare die that would otherwise require expensive heat removalequipment for testing at high speeds. The proposed ATPG exploitsall don't cares that occur during scan shifting, test application, andresponse capture to minimize switching activity in the circuit undertest. Furthermore, an ATPG that maximizes the number of state inputsthat are assigned don't care values, has been developed. Theproposedtechniquehas beenimplemented and usedto generatetestsfor full scan versions of ISCAS 89 benchmark circuits. These testsdecrease the average number of transitions during test by 19% to89%, when comparedwith those generatedby a simple PODEM implementation.
An integrated hierarchical file organization for data selection and retrieval
Authors: Sau-Lan Lee
Venue: Proceedings of the 8th annual international ACM SIGIR conference on Research and development in information retrieval (1985)

This paper presents an approach, the IHF approach, of organising data of a hierarchical structure into one single file, maintaining adequate representation of the relationships among the data. The IHF approach requires each data item be stored in the basic form of name-value pair and consists in assigning each data item with identifier which provides not only the data item identification but also an implicit identification of the hierarchical structural relationships among groups of data items. Data selection and retrieval operations are effectively implemented with the concept of masking of relevant identifier bits, without resorting to any linking devices. Application of the IHF technique on CAFS is examined.
A weighted technique for programmable logic devices minimization
Authors: C. Hwa Chang, Hammad K. Azzam
Venue: Proceedings of the 23rd annual workshop and symposium on Microprogramming and microarchitecture (1990)

A new technique for minimizing the width of Programmable Logic Devices(PLDs) is introduced in this paper. The algorithm starts with the result of the technique introduced by Das Banerji and Chatopadhyay[4]. The solution obtained in [4] will be refined to form the temporary solution, or what is called a preliminary solution. The problem of the preliminary solution is that it does not guarantee a minimum solution, because it does not use redundant classes, that are sometimes essential to the final minimum solution. The weighting technique is introduced, which gives a weight to each micro-order. The micro-orders with the largest weights are stripped from each class to form a stripped set. The stripped micro-orders are tested for compatibility, and a new set of compatibility classes are formed based on the stripped micro-orders, and the reserved classes only. Some factors are taken into consideration before the stripped micro-orders become the final collection. The procedure loops again with the new set of compatibility classes as long as reduction is obtained.
High-performance sorting on networks of workstations
Authors: Andrea C. Arpaci-Dusseau, Remzi H. Arpaci-Dusseau David E. Culler, Joseph M. Hellerstein, David A. Patterson
Venue: ACM SIGMOD Record (1997)

We report the performance of NOW-Sort, a collection of sorting implementations on a Network of Workstations (NOW). We find that parallel sorting on a NOW is competitive to sorting on the large-scale SMPs that have traditionally held the performance records. On a 64-node cluster, we sort 6.0 GB in just under one minute, while a 32-node cluster finishes the Datamation benchmark in 2.41 seconds. Our implementations can be applied to a variety of disk, memory, and processor configurations; we highlight salient issues for tuning each component of the system. We evaluate the use of commodity operating systems and hardware for parallel sorting. We find existing OS primitives for memory management and file access adequate. Due to aggregate communication and disk bandwidth requirements, the bottleneck of our system is the workstation I/O bus.
Compiled Simulation of Programmable DSP Architectures
Authors: Vojin Zivojnović, Steven Tjiang, Heinrich Meyr
Venue: Journal of VLSI Signal Processing Systems (1997)

This paper presents a technique for simulating processors based on the principle of compiled simulation. Unlike existing, commercially available instruction set simulators for DSPs, which are of interpretive character, the proposed technique performs instruction decoding and simulation scheduling at compile time. The technique offers up to three orders of magnitude faster simulation. The high speed allows the user to explore algorithms and hardware/software trade-offs before any hardware implementation. Moreover, the user can tailor the compiled simulation to trade speed for more accuracy. In this paper, the sources of the speedup and the limitations of the technique are analyzed and the realization of the simulation compiler is presented.
Lessons learned with ACME an environment integration experiment
Authors: John W. Gintell
Venue: ACM SIGSOFT Software Engineering Notes (1997)

ACME is an integration experiment with Marvel (a process centered environment) and ConversationBuilder (a CSCW system). Scrutiny, a collaborative software inspection system built with ConversationBuilder, is the subject application that operates in the integrated environment. The integration methodologies used by ACME are control integration, data integration, and tool integration. This paper describes the components and conceptual design of ACME and the effect that ACME has on the operation of Scrutiny. It also describes the lessons learned during this project. These lessons are categorized into those concerned with concept validation, integration issues, system design issues, software agent integration, and implementation and testing issues.
Arena software tutorial
Authors: Nancy A. Markovitch, David M. Profozich
Venue: Proceedings of the 28th conference on Winter simulation (1996)

The Arena modeling system from Systems Modeling Corporation is a flexible and powerful tool that allows analysts to creates animated simulation models that accurately represent virtually any system. First released in 1993, Arena employs an object-oriented design for entirely graphical model development. Simulation analysts place graphical objects--called modules-on a layout in order to define system components such as machines, operators, and material handling devices. Arena is built on the SIMAN simulation language. After creating a simulation model graphically, Arena automatically generates the underlying SIMAN model used to perform simulation runs. The graphical modules used by simulation analysts to create models are provided "off-the-shelf" with Arena. These modules can also be custom designed by the end user to produce a modeling environment that is tailored to a specific application area (e.g., welding, cross-dock, etc.) or a specific vertical market (e.g., semiconductor, textiles, etc.). The resulting collection of user-created modules is contained inside an Application Solution Template (AST) that can be shared by any licensed Arena user.