ppxscal/embedding_network huggingface dataset:
Clustering task graphs for message passing architectures
Authors: Apostolos Gerasoulis, Sesh Venugopal, Tao Yang
Venue: Proceedings of the 4th international conference on Supercomputing (1990)

Clustering is a mapping of the nodes of a task graph onto labeled clusters. We present a unified framework for clustering of directed acyclic graphs (DAGs). Several clustering algorithms from the literature are compared using this framework. For coarse grain DAGs two interesting properties are presented. For every nonlinear clustering there exists a linear clustering whose parallel time is less than the nonlinear one. Furthermore, the parallel time of any linear clustering is within a factor of two of the optimal. Two clustering algorithms are presented with near linear time complexity for coarse grain DAGs. The conclusion is that linear clustering is an efficient and accurate operation.
Perils and pitfalls of parallel discrete-event simulation
Authors: Rajive L. Bagrodia
Venue: Proceedings of the 28th conference on Winter simulation (1996)

The design of efficient parallel discrete-event simulation (PDES) models often appears to be a mysterious art practiced primarily by academic researchers who have been rigorously ordained in this task. This tutorial attempts to unravel some of the mysteries. It describes the process of generating an efficient parallel implementation of a discrete-event simulation (DES) model. Common pitfalls in the parallel execution of the models are described together with suggestions on their avoidance.
Reasoning about implicit invocation
Authors: D. Garlan, S. Jha, D. Notkin, J. Dingel
Venue: Proceedings of the 6th ACM SIGSOFT international symposium on Foundations of software engineering (1998)

Implicit invocation [SN92, GN91] has become an important architectural style for large-scale system design and evolution. This paper addresses the lack of specification and verification formalisms for such systems. Based on standard notions from process algebra and trace semantics, we define a formal computational model for implicit invocation. A verification methodology is presented that supports linear time temporal logic and compositional reasoning. First, the entire system is partioned into groups of components (methods) that behave independently. Then, local properties are proved for each of the groups. A precise description of the cause and the effect of an event supports this step. Using local correctness, independence of groups, and properties of the delivery of events, we infer the desired property of the overall system. Two detailed examples illustrate the use of our framework.
FPGA synthesis with retiming and pipelining for clock period minimization of sequential circuits
Authors: Jason Cong, Chang Wu
Venue: Proceedings of the 34th annual Design Automation Conference (1997)

In this paper, we present a new algorithm, named TurboSYN,for FPGA synthesis with retiming and pipelining to minimizethe clock period for sequential circuits.For a target clockperiod, since pipelining can eliminate all critical I/O paths,but not critical loops, we concentrate on FPGA synthesis toeliminate the critical loops.We combine the combinationalfunctional decomposition technique with retiming to performthe sequential functional decomposition, and incorporate itin the label computation of TurboMap to eliminate allcritical loops.The results show a significant improvementover the state-of-the-art FPGA mapping and resynthesis algorithms(1.7 ~ 2 times reduction on the clock period).Moreover,we develop a novel approach for positive loop detectionwhich leads to over 10 ~ 50 times speedup of the algorithm.As a result, TurboSYN can optimize sequential circuits ofover 10¿ gates and 10{3} flipflops in reasonable time.
The bi-mode branch predictor
Authors: Chih-Chieh Lee, I-Cheng K. Chen, Trevor N. Mudge
Venue: Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture (1997)

Dynamic branch predictors are popular because they can deliver accurate branch prediction without changes to the instruction set architecture or pre-existing binaries. However, to achieve the desired prediction accuracy, existing dynamic branch predictors require considerable amounts of hardware to minimize the interference effects due to aliasing in the prediction tables. We propose a new dynamic predictor, the bi-mode predictor, which divides the prediction tables into two halves and, by dynamically determining the current "mode" of the program, selects the appropriate half of the table for prediction. This approach is shown to preserve the merits of global history based prediction while reducing destructive aliasing and, as a result, improving prediction accuracy. Moreover, it is simple enough that it does not impact a processor's cycle time. We conclude by conducting a comprehensive study into the mechanism underlying two-level dynamic predictors and investigate the criteria for their optimal designs. The analysis presented provides a general framework for studying branch predictors.
Maintenance of data cubes and summary tables in a warehouse
Authors: Inderpal Singh Mumick
Venue: ACM SIGMOD Record (1997)

Data warehouses contain large amounts of information, often collected from a variety of independent sources. Decision-support functions in a warehouse, such as on-line analytical processing (OLAP), involve hundreds of complex aggregate queries over large volumes of data. It is not feasible to compute these queries by scanning the data sets each time. Warehouse applications therefore build a large number of summary tables, or materialized aggregate views, to help them increase the system performance. As changes, most notably new transactional data, are collected at the data sources, all summary tables at the warehouse that depend upon this data need to be updated. Usually, source changes are loaded into the warehouse at regular intervals, usually once a day, in a batch window, and the warehouse is made unavailable for querying while it is updated. Since the number of summary tables that need to be maintained is often large, a critical issue for data warehousing is how to maintain the summary tables efficiently. In this paper we propose a method of maintaining aggregate views (the summary-delta table method), and use it to solve two problems in maintaining summary tables in a warehouse: (1) how to efficiently maintain a summary table while minimizing the batch window needed for maintenance, and (2) how to maintain a large set of summary tables defined over the same base tables. While several papers have addressed the issues relating to choosing and materializing a set of summary tables, this is the first paper to address maintaining summary tables efficiently.
From Centralized Workflow Specification to Distributed WorkflowExecution
Authors: Peter Muth, Dirk Wodtke, Jeanine Weissenfels, Angelika Kotz Dittrich, Gerhard Weikum
Venue: Journal of Intelligent Information Systems (1998)

Current workflow management systems fall short of supporting large-scale distributed, enterprise-wide applications. We present a scalable, rigorously founded approach to enterprise-wide workflow management, based on the distributed execution of state and activity charts. By exploiting the formal semantics of state and activity charts, we develop an algorithm for transforming a centralized state and activity chart into a provably equivalent partitioned one, suitable for distributed execution. A synchronization scheme is developed that guarantees an execution equivalent to a non-distributed one. This basic solution is further refined in order to reduce communication overhead and exploit parallelism between partitions whenever possible. The developed synchronization schemes are compared in terms of the number and size of synchronization messages.
An Analysis of Spectral Envelope Reduction via Quadratic Assignment Problems
Authors: Alan George, Alex Pothen
Venue: SIAM Journal on Matrix Analysis and Applications (1997)

A new spectral algorithm for reordering a sparse symmetric matrix to reduce its envelope size was described in [Barnard, Pothen, and Simon, Numer. Linear Algebra Appl., 2 (1995), pp. 317--334]. The ordering is computed by associating a Laplacian matrix with the given matrix and then sorting the components of a specified eigenvector of the Laplacian. In this paper we provide an analysis of the spectral envelope reduction algorithm. We describe related 1- and 2-sum problems; the former is related to the envelope size, while the latter is related to an upper bound on the work in an envelope Cholesky factorization. We formulate these two problems as quadratic assignment problems and then study the 2-sum problem in more detail. We obtain lower bounds on the 2-sum by considering a relaxation of the problem and then show that the spectral ordering finds a permutation matrix closest to an orthogonal matrix attaining the lower bound. This provides a stronger justification of the spectral envelope reduction algorithm than previously known. The lower bound on the 2-sum is seen to be tight for reasonably "uniform" finite element meshes. We show that problems with bounded separator sizes also have bounded envelope parameters.
Model checking of hierarchical state machines
Authors: Rajeev Alur, Mihalis Yannakakis
Venue: Proceedings of the 6th ACM SIGSOFT international symposium on Foundations of software engineering (1998)

Model checking is emerging as a practical tool for detecting logical errors in early stages of system design. We investigate the model checking of hierarchical (nested) systems, i.e. finite state machines whose states themselves can be other machines. This nesting ability is common in various software design methodologies and is available in several commercial modeling tools. The straightforward way to analyze a hierarchical machine is to flatten it (thus, incurring an exponential blow up) and apply a model checking tool on the resulting ordinary FSM. We show that this flattening can be avoided. We develop algorithms for verifying linear time requirements whose complexity is polynomial in the size of the hierarchical machine. We address also the verification of branching time requirements and provide efficient algorithms and matching lower bounds.
A comparison of methods for accelerating convergence of Newton's method for multiple polynomial roots
Authors: John Michael McNamee
Venue: ACM SIGNUM Newsletter (1998)

Newton's method for solving polynomial equations converges only linearly to a multiple root. The speed of several methods for accelerating the convergence have been compared numerically. The Madsen-Reid method proved to be the fastest, with the Aitken and Ostrowsky methods close behind.
Lightweight object-oriented shared variables for distributed applications on the Internet
Authors: Jacob Harris, Vivek Sarkar
Venue: ACM SIGPLAN Notices (1998)

This paper describes a lightweight yet powerful approach for writing distributed applications using shared variables. Our approach, called SHAREHOLDER, is inspired by the flexible and intuitive model of information access common to the World Wide Web. The distributed applications targeted by our approach all share a weak consistency model and loose transaction semantics, similar to a user's model of accessing email, bulletin boards, chat rooms, etc. on the Internet. The SHAREHOLDER infrastructure has several advantages. Its highly object-oriented view of shared variables simplifies their initialization and configuration. A shared variable's distribution mechanism is specified through an associated configuration object, and the programmer does not need to write any extra code to implement the sharing mechanism. These configuration objects can be initialized at run-time, allowing tremendous flexibility in dynamic control of distribution of shared variables. Finally, the programmer can treat shared variables and local variables interchangeably, thus simplifying conversion of a serial application into a distributed application.
SIMSCRIPT II.5 tutorial
Authors: Edward C. Russell
Venue: Proceedings of the 17th conference on Winter simulation (1985)

This tutorial will present the highlights of the SIMSCRIPT II.5 approach to building discrete event simulation models. The approach will be to construct a small example problem, implement the program in SIMSCRIPT II.5, and then to display the modularity which is possible with SIMSCRIPT II.5 by adding several &ldquo;real-world&rdquo; complexities to the model.
Error tolerant document structure analysis
Authors: Bertin Klein, Peter Fankhauser
Venue: Proceedings of the IEEE international forum on Research and technology advances in digital libraries (1997)

Successful applications of digital libraries require structured access to sources of information. This paper presents an approach to extract the logical structure of text documents. The extracted structure is explicated by means of SGML (Standard Generalized Markup Language). Consequently, the extraction is achieved on the basis of grammars that extend SGML with recognition rules. From these grammars parsing automata are generated. These automata are used to partition a flat text document into its elements, to discard formatting information, and to insert SGML markups. Complex document structures and fallback rules needed for error tolerant parsing make such automata highly ambiguous. A novel parsing strategy has been developed that ranks and prunes ambiguous parsing paths.
Design of Multidimensional Separable-Denominator DigitalFilters in the Spatial Domain
Authors: Takao Hinamoto, Akimitsu Doi, Ken-Ichi Harada
Venue: Multidimensional Systems and Signal Processing (1997)

Based on a concept of minimal decomposition and balanced realization, a novel technique is developed for designing multidimensional (M-D) separable-denominator digital filters in the spatial domain. This is done by decomposing a desired M-D FIR filter into M parts and by representing it by a cascade connection of M 1-D filters. The minimal decomposition treated here can be viewed as an extension of that in 2-D separable-denominator case in some sense. However, the proposed technique differs from the existing one even in 2-D case and is simpler. Two numerical examples are also given to illustrate the utility of the proposed technique. The amount of calculation required here is relatively small and the stability of the filter is always guaranteed.
Efficient coupled noise estimation for on-chip interconnects
Authors: Anirudh Devgan
Venue: Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design (1997)

Noise analysis and avoidance is an increasingly critical step in deep submicron design. Ever increasing requirements on performance have led to widespread use of dynamic logic circuit families and its other derivatives. These aggressive circuit families trade off noise margin for timing performance making them more susceptible to noise failure and increasing the need for noise analysis. Currently, noise analysis is performed either through circuit or timing simulation or through model order reduction. These techniques in use are still inefficient for analyzing massive amount of interconnect data found in present day integrated circuits. This paper presents efficient techniques for estimation of coupled noise in on-chip interconnects. This noise estimation metric is an upper bound for RC circuits, being similar in spirit to Elmore delay in timing analysis. Such an efficient noise metric is especially useful for noise criticality pruning and physical design based noise avoidance techniques.
The multicluster architecture: reducing cycle time through partitioning
Authors: Keith I. Farkas, Paul Chow, Norman P. Jouppi, Zvonko Vranesic
Venue: Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture (1997)

The multicluster architecture that we introduce offers a decentralized, dynamically-scheduled architecture, in which the register files, dispatch queue, and functional units of the architecture are distributed across multiple clusters, and each cluster is assigned a subset of the architectural registers. The motivation for the multicluster architecture is to reduce the clock cycle time, relative to a single-cluster architecture with the same number of hardware resources, by reducing the size and complexity of components on critical timing paths. Resource partitioning, however, introduces instruction-execution overhead and may reduce the number of concurrently executing instructions. To counter these two negative by-products of partitioning, we developed a static instruction scheduling algorithm. We describe this algorithm, and using trace-driven simulations of SPEC92 benchmarks, evaluate its effectiveness. This evaluation indicates that for the configurations considered, the multicluster architecture may have significant performance advantages at feature sizes below 0.35um, and warrants further investigation.
An efficient representation for formal synthesis
Authors: Christian Blumenröhr, Dirk Eisenbiegler
Venue: Proceedings of the 10th international symposium on System synthesis (1997)

In the last years, performing synthesis by logical refinement has become an interesting alternative towards post-synthesis verification. This paper gives a case study about the complexity of formal synthesis programs within a given calculus. For a simple synthesis step, it is discussed, how one can efficiently implement circuit transformations with respect to the complexity of the logical transformations of the underlying calculus.
A barrel shift microsystem for parallel processing
Authors: Reuven Bakalash, Zhong Xu
Venue: Proceedings of the 23rd annual workshop and symposium on Microprogramming and microarchitecture (1990)

A flow-through interconnection network microsystem is described. It is part of a parallel SIMD graphics architecture called Cube in which the network interconnects between n pairs of processors and memories. No two accesses involve the same memory or processor and their is an uniform communication distance among the processors. The interconnection network is based on a modular and VLSI implemented Barrel Switch (BS) unit, which provides modularity and flexibility of the entire network. A rotate distance of up to 16 processor-memory pairs is performed in a flow-through manner in a single machine cycle. Structurally, the BS is organised in a simple and repetitive pattern of junction elements and connection paths, extendable in its overall length and its data width, and suited for VLSI implementation.
Finding Postal Carrier Walk Paths in Mixed Graphs
Authors: Hong Yan, Gerald L. Thompson
Venue: Computational Optimization and Applications (1998)

The postman problem requires finding a lowest cost tour in a connected graph that traverses each edge at least once. In this paper we first give a brief survey of the literature on postman problems including, the original Chinese postman problem on undirected graphs, the windy Chinese postman problem on graphs where the cost of an arc depends on the direction the arc is transversed, the directed postman problem on graphs with directed edges, and the mixed postman problem on graphs in which there are some directed and some undirected arcs.We show how the mixed postman problem can be solved as an integer program, using the formulation of Gendreau, Laporte and Zhao, by a new row addition branch and bound algorithm, which is a modification of the column subtraction algorithm for set partitioning problems of Harche and Thompson. Computational experience shows that a &ldquo;slack variable&rdquo; heuristic is very effective in finding good solutions that are frequently optimal for these problems.
A data structure for circuit net lists
Authors: Steve Meyer
Venue: Proceedings of the 25th ACM/IEEE Design Automation Conference (1988)

A data structure for storing and processing electrical circuit net lists is described. The basic data structure is not new, but the version described here is novel in three specific ways. It adds separate structures (arrays) for cell type and I/O pad specific information, stores net lists defined in terms of primitive elements or cells as two superimposed symmetric incidence list form directed graphs, and separates primitive element input and output lists to allow signal flow traversal. This paper concentrates on computer program level implementation details and on various practical problems arising in circuit net list processing. Finally, the structure's construction cost and algorithmic efficiency is discussed.
Software process modeling and execution within virtual environments
Authors: John C. Doppke, Dennis Heimbigner, Alexander L. Wolf
Venue: ACM Transactions on Software Engineering and Methodology (TOSEM) (1998)

In the past, multiuser virtual environments have been developed as venues for entertainment and social interaction. Recent research focuses instead on their utility in carrying out work in the real world. This research has identified the importance of a mapping between the real and the virtual that permits the representation of real tasks in the virtual environment. We investigate the use of virtual environments&mdash;in particular, MUDs (Multi-User Dimensions)&mdash;in the domain of software process. In so doing, we define a mapping, or metaphor, that permits the representation of software processes within a MUD. The system resulting from this mapping, called Promo, permits the modeling and execution of software processes by geographically dispersed agents.
Issues in designing an information model for application development
Authors: Gary H. Sockut, Helen P. Arzu, Robert W. Matthews, David E. Shough
Venue: ACM SIGSOFT Software Engineering Notes (1997)

IBM's object-oriented information model lets a customer share data among various tools for application development. This paper discusses several issues in designing the information model, namely (1) techniques for diagrams (an essential part of communication between an information model designer and other designers or tool writers), (2) organization of the design of the information model (an essential step when many designers design anything large), and (3) technical content. These discussions of the experience of designing the information model should be valuable for further design of the information model and for other design efforts, e.g., involving other models or other integration of tools.
Similarity and Symmetry Measures for Convex Shapes Using Minkowski Addition
Authors: Henk J.A.M. Heijmans, Alexander V. Tuzikov
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1998)

This paper is devoted to similarity and symmetry measures for convex shapes whose definition is based on Minkowski addition and the Brunn-Minkowski inequality. This means, in particular, that these measures are region-based, in contrast to most of the literature, where one considers contour-based measures. All measures considered in this paper are invariant under translations; furthermore, they can be chosen to be invariant under rotations, multiplications, reflections, or the class of affine transformations. It is shown that the mixed volume of a convex polygon and a rotation of another convex polygon over an angle ¿ is a piecewise concave function of ¿. This and other results of a similar nature form the basis for the development of efficient algorithms for the computation of the given measures. Various results obtained in this paper are illustrated by experimental data. Although the paper deals exclusively with the two-dimensional case, many of the theoretical results carry over almost directly to higher-dimensional spaces.