ppxscal/embedding_network huggingface dataset:
A New Framework for Designing: Built-in Test Multichip Modules with Pipelined Test Strategy
Authors: Ting-Ting Lin, Huoy-Yu Liou
Venue: IEEE Design Test (1993)

A novel test strategy, the Loop Testing Architecture (LTA), is introduced to reduce aliasing probability and testing time for multichip modules. This is accomplished by connecting cascadable built-in testers (CBITs) in neighboring pipelined stages to increase the length of the test suites. Fundamental properties of the LTA supporting randomness in the generated test patterns (state coverage) and the asymptotic aliasing probability are presented. Results on two small-scale multiprocessor configurations show that the aliasing probability in analyzing signatures is comparable to that of an MLFSR but with fairly low area overhead; compared with the circular self-test path technique, less testing time is required by LTA. Further evaluation of the potential capabilities provided by the LTA compared with boundary scan and other pipelined test scheduling approaches confirmed the usefulness of LTA as a framework for designing effective testable systems.
Software requirements validation via task analysis
Authors: Hong Zhu, Lingzi Jin, Dan Diaper, Ganghong Bai
Venue: Journal of Systems and Software (2002)

As a baseline for software development, a correct and complete requirements definition is one foundation of software quality. Previously, a novel approach to static testing of software requirements was proposed in which requirements definitions are tested on a set of task scenarios by examining software behaviour in each scenario described by an activity list. Such descriptions of software behaviour can be generated automatically from requirements models. This paper investigates various testing methods for selecting test scenarios. Data flow, state transition and entity testing methods are studied. A variety of test adequacy criteria and their combinations are formally defined and the subsume relations between the criteria are proved. Empirical studies of the testing methods and the construction of a prototype testing tool are reported.
Cost-Effective Flow Table Designs for High-Speed Routers: Architecture and Performance Evaluation
Authors: Jun Xu, Mukesh Singhal
Venue: IEEE Transactions on Computers (2002)

Provision of QoS-related router functions such as traffic regulation, policy routing, and usage-based accounting requires that a flow table store state information for active flows. The design of such a flow table is not trivial for a high-speed Internet router (e.g., 100+ Gbps) with a large number of active flows (e.g., tens of millions) and a high packet arrival rate (e.g., tens of millions of packets per second). Targeting two different models (centralized and distributed) of router design, we propose a software-based design to be implemented on individual line cards, which is suitable for the distributed model, and a hardware-based design to be implemented in the main forwarding engine of a router, which is suitable for the centralized model. The software-based design, adapted from the hash table data structure, employs a practical and effective technique to solve the garbage collection problem caused by the expired flows. The hardware-based design, adapted from the architecture of an N-way set-associative cache, employs a novel dynamic set-associative scheme to reduce the overflow ratio that a traditional set-associative scheme incurs, by a high percentage, and a pipelined design to achieve a throughput of 100+ Gbps. The performance evaluation results from both trace-driven simulation and statistical analysis demonstrate that both designs are cost-effective for their targeted router models.
Case study: visual debugging of finite element codes
Authors: Patricia Crossno, David H. Rogers, Christopher J. Garasi
Venue: Proceedings of the conference on Visualization '02 (2002)

We present an innovative application developed at Sandia National Laboratories for visual debugging of unstructured finite element physics codes. Our tool automatically locates anomalous regions, such as inverted elements or nodes whose variable values lie outside a prescribed range, then extracts mesh subsets around these features for detailed examination. The subsets are viewed using color coding of variable values superimposed on the mesh structure. This allows the values and their relative spatial locations within the mesh to be correlated at a glance. Both topological irregularities and hot spots within the data stand out visually, allowing the user to explore the exact numeric values of the grid at surrounding points over time. We demonstrate the utility of this approach by debugging a cell inversion in a simulation of an exploding wire.
Dynamically Changing the Logical Behavior of the Microcomputer Interface
Authors: Ioan Dancea
Venue: IEEE Micro (1989)

Industrial programmable controllers and hardware simulators currently use the software method of direct logic simulation. In this method, programs contain the logical functions of several Boolean variables that are encoded directly. Each combinational circuit expressed by a group of Boolean equations requires an independent program. An alternative solution for the software implementation of the Boolean equations, named the product terms method, is presented. This method features the use of a single program to implement any multiple-output combinational circuit. To make the distinction between different circuits, a block of data defines each circuit. The product method is extended to synchronous sequential circuits, for which two tables are used. One table determines the next state of the combinational circuit, and the second table determines the outputs. An expert system has been developed to generate the table used in the product terms by interpreting the symbolic Boolean equations supplied by the user. The implementation and testing of the method are described.
Deadlock-Free Fault-Tolerant Routing in Injured Hypercubes
Authors: J. Kim, K. G. Shin
Venue: IEEE Transactions on Computers (1993)

Wormhole routing with the e-cube algorithm is an excellent solution for deadlock-free interprocess communication in healthy hypercubes. However, it does not work for injured hypercubes where some nodes and/or links are faulty. The authors propose a new deadlock-free routing scheme in an injured hypercube with the wormhole routing capability. All previously proposed schemes suggest the use of virtual channels to avoid the cycle of resource dependency. By contrast, the authors' scheme is based on the re-establishment of a routing path to the destination, but it does not always yield a shortest path between the source and destination. The proposed routing scheme uses either wormhole routing or staged routing, depending on the availability of one or more healthy (n-2)-cubes within an injured n-cube.
Database Reorganization in Parallel Disk Arrays with I/O Service Stealing
Authors: Peter Zabback, Ibrahim Onyuksel, Peter Scheuermann, Gerhard Weikum
Venue: IEEE Transactions on Knowledge and Data Engineering (1998)

We present a model for data reorganization in parallel disk systems that is geared toward load balancing in an environment with periodic access patterns. Data reorganization is performed by disk cooling, i.e., migrating files or extents from the hottest disks to the coldest ones. We develop an approximate queueing model for determining the effective arrival rates of cooling requests and discuss its use in assessing the costs versus benefits of cooling actions.
Fault Analysis for Networks with Concurrent Error Detection
Authors: Cristiana Bolchini, Fabio Salice, Donatella Sciuto
Venue: IEEE Design Test (1998)

Hardware and information redundancy are two among the most widespread strategies for designing circuits with concurrent detection properties. These design approaches guarantee the desired property by partitioning the set of output configurations that a device may produce into two classes: those produced in a fault free situation and those caused by at least a fault within either the network or the checker circuit. This functional property allows the coverage of all faults that produce an error on the outputs such that the generated configuration does not belong to the fault-free output set. Whenever this does not happen, the fault is not detected, either causing no error (fault redundant with respect to the input configuration) or producing a fault-free output different from the correct one (critical situation). To achieve a complete fault coverage a constrained synthesis must support the functional encoding, guaranteeing that each fault produces only detectable errors. If there is a lack, either at functional encoding level or at the structural synthesis level, due to costs and complexity, the device will only be partially self-checking.This paper proposes an approach, supported by a tool the authors developed, for fault analysis and simulation of networks designed to have concurrent detection properties, either partially or completely, to characterize all faults that may affect the device, determining the coverage, when incomplete, extracting test vectors and other parameters for evaluating the quality of the device. The methodology may be used both during the realization of the device, supporting network realization to fulfill the functional encoding, and a-posteriori, when the device is partially o totally self-checking, for an evaluation and possible comparison with different solutions.
Database evaluation using multiple regression techniques
Authors: Jane Fedorowicz
Venue: Proceedings of the 1984 ACM SIGMOD international conference on Management of data (1984)

A model of the inverted file of an automated bibliographic system is constructed using the Zipf distribution of word frequency. By ascertaining the parameters of the Zipfian model of the inverted file system, one can estimate the minimum data storage requirements of the database. In addition, given a few additional system parameters, access time for a specified query can be estimated. The estimation procedures are accomplished using logarithmic transformations and multiple regression techniques. This paper introduces the Zipfian models, their regression formulation, and their results and interpretation for application to database evaluation.
A Search Technique for Pattern Recognition Using Relative Distances
Authors: Thomas E. Portegys
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1995)

A technique for creating and searching a tree of patterns using relative distances is presented. The search is conducted to find patterns which are nearest neighbors of a given test pattern. The structure of the tree is such that the search time is proportional to the distance between the test pattern and its nearest neighbor, which suggests the anomalous possibility that a larger tree, which can be expected on average to contain closer neighbors, can be searched faster than a smaller tree. The technique has been used to recognize OCR digit samples derived from NIST data at an accuracy rate of 97% using a tree of 7,000 patterns.
Concentration of non-Lipschitz functions and applications
Authors: V. H. Vu
Venue: Random Structures Algorithms (2002)

Strong concentration results play a fundamental role in probabilistic combinatorics and theoretical computer science. In this paper, we present several new concentration results developed recently by the author and collaborators. To illustrate the power of these new results, we discuss applications in many different areas of mathematics, from combinatorial number theory to the theory of random graphs.
Critical Analysis of the PIE Testability Technique
Authors: Zuhoor Al-Khanjari, Martin Woodward, Haider Ali Ramadhan
Venue: Software Quality Control (2002)

The work of Voas and colleagues has introduced, refined and applied the propagation, infection and execution (PIE) analysis technique for measuring testability of programs. The purpose of this paper is twofold: (1) to summarize and review the work done by Voas and others, and (2) to lay down a framework for automating the measurement of testability. In doing so, we introduce a prototype system, which uses the mutant schemata approach to calculate the infection estimate. The attempt, reported in this paper, to reproduce the results reported by Voas for one example, have shown that intermediate calculations are quite sensitive to minor variations in the parameters to the process, although the final testability results are in agreement.
A Least Biased Fuzzy Clustering Method
Authors: G. Beni, X. Liu
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1994)

A new operational definition of cluster is proposed, and a fuzzy clustering algorithm with minimal biases is formulated by making use of the maximum entropy principle to maximize the entropy of the centroids with respect to the data points (clustering entropy). The authors make no assumptions on the number of clusters or their initial positions. For each value of an adimensional scale parameter /spl beta/', the clustering algorithm makes each data point iterate towards one of the cluster's centroids, so that both hard and fuzzy partitions are obtained. Since the clustering algorithm can make a multiscale analysis of the given data set one can obtain both hierarchy and partitioning type clustering. The relative stability with respect to /spl beta/' of each cluster structure is defined as the measurement of cluster validity. The authors determine the specific value of /spl beta/' which corresponds to the optimal positions of cluster centroids by minimizing the entropy of the data points with respect to the centroids (clustered entropy). Examples are given to show how this least biased method succeeds in getting perceptually correct clustering results.
Off-Line Handwritten Chinese Character Recognition as a Compound Bayes Decision Problem
Authors: Pak-Kwong Wong, Chorkin Chan
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1998)

A handwritten Chinese character off-line recognizer based on Contextual Vector Quantization (CVQ) of every pixel of an unknown character image has been constructed. Each template character is represented by a codebook. When an unknown image is matched against a template character, each pixel of the image is quantized according to the associated codebook by considering not just the feature vector observed at each pixel, but those observed at its neighbors and their quantizations as well. Structural information such as stroke counts observed at each pixel are captured to form a cellular feature vector. Supporting a vocabulary of 4,616 simplified Chinese characters and alphanumeric and punctuation symbols, the writer-independent recognizer has an average recognition rate of 77.2 percent. Three statistical language models for postprocessing have been studied for their effectiveness in upgrading the recognition rate of the system. Among them, the CVQ-based language model is the most effective one upgrading the recognition rate by 10.4 percent on the average.
Cobol for the Next Millennium
Authors: Don Schricker
Venue: IEEE Software (2000)

Cobol 2002, the new Cobol standard, is expected to be finalized in approximately 18 months. Cobol 2002 builds on Cobol's first-class data handling capabilities and introduces object-oriented features, environmental improvements, and many other modern constructs to the language. The improvements position Cobol as both a business and general-purpose programming language, capable of handling a wide variety of programming tasks.
Average Waiting Time Profiles of Uniform Distributed Queue Dual Bus System Model
Authors: Nageswara S. V. Rao, Kurt J. Maly, Stephan Olariu, Sudheer Dharanikota, Liping Zhang, David E. Game
Venue: IEEE Transactions on Parallel and Distributed Systems (1995)

The Distributed Queue Dual Bus (DQDB) system consists of a linear arrangement of N nodes that communicate with each other using two contra-flowing buses. The nodes use an extremely simple protocol to send messages on these buses. This simple, but elegant, system has been found to be very challenging to analyze. We consider a simple and uniform abstraction of this model to highlight the fairness issues in terms of average waiting time. We introduce a new approximation method to analyze the performance of DQDB system in terms of the average waiting time of a node expressed as a function of its position. Our approach abstracts the intimate relationship between the load of the system and its fairness characteristics, and explains all basic behavior profiles of DQDB observed in previous simulation. For the uniform DQDB with equal distance between adjacent nodes, we show that the system operates under three basic behavior profiles and a finite number of their combinations that depend on the load of the network. Consequently, the system is not fair at any load in terms of the average waiting times. We also show that the main theme of the analysis carries over to the general (nonuniform) DQDB. By suitably choosing the inter-node distances, the DQDB can be made fair around some loads, but such system will become unfair as the load changes. In the vicinity of a critical load, the uniform network runs into a state of instability, where its behavior fluctuates from one extreme to the other with small load variations. Our analysis is supported by simulation results.
Electrical assessment of copper damascene interconnects down to sub-50 nm feature sizes
Authors: G. Steinlesberger, M. Engelhardt, G. Schindler, W. Steinhögl, A. von Glasow, K. Mosig, E. Bertagnolli
Venue: Microelectronic Engineering (2002)

The feasibility of fabrication of sub-50 nm copper interconnects was demonstrated. A process flow to obtain wires with line widths far below the limits given by lithography using a removable spacer technique was developed for copper damascene lines. The behavior of the electrical resistivity of lines with feature sizes down to 43 nm was investigated for temperatures ranging from 80 to 573 K. An increase of the electrical resistivity with shrinking dimensions was observed as a result of size effects. The experimental data will be discussed in detail and can be well described by a contribution of electron surface scattering and grain-boundary scattering. The results clearly demonstrate that cooling of Cu wires will no longer help to maintain low electrical resistivity in the mesoscopic regime, i.e. when feature sizes of metal wires approach the mean free path of the charge carriers. For future technology generations size effects, which are not explicitly addressed in the ITRS, will come into play and will become a significant contributor to wire related delay times.
Concurrent Process Monitoring with No Reference Signatures
Authors: S. J. Upadhyaya, B. Ramamurthy
Venue: IEEE Transactions on Computers (1994)

A simple, inexpensive and time/space efficient signature technique for process monitoring is presented. In this technique, a known signature function is applied to the instruction stream at compilation phase and when the accumulated signature forms an m-out-of-n code, the corresponding instructions are tagged. Error checking is done at run-time by monitoring the signatures accumulated at the tagged locations to determine whether they form m-out-of-n codes. This approach of signature checking does not require the embedding of reference signatures at compilation, thereby leading to savings in memory as well as in execution time. The m-out-of-n code approach offers high error coverage and controllable latency. The results of the experiments conducted to verify the controllability of the latency are discussed. One of the distinguishing features of the proposed scheme is the elimination of reference signatures, which are the main source of memory and time overhead in the existing techniques.
Machine Independent AND and OR Parallel Execution of Logic Programs: Part II-Compiled Execution
Authors: B. Ramkumar, L. V. Kalé
Venue: IEEE Transactions on Parallel and Distributed Systems (1994)

In pt.I, we presented a binding environment for the ANDand OR parallel execution of logic programs. This environment was instrumental inrendering a compiler for the AND and OR parallel execution of logic programs machineindependent. In this paper, we describe a compiler based on the Reduce-OR processmodel (ROPM) for the parallel execution of Prolog programs, and provide performance of the compiler on five parallel machines: the Encore Multimax, the Sequent Symmetry, the NCUBE 2, the Intel i860 hypercube and a network of Sun workstations. The compiler is part of a machine independent parallel Prolog development system built on top of a runtime environment for parallel programming called the Chare kernel, and runs unchanged on these multiprocessors. In keeping with the objectives behind the ROPM, the compilersupports both on and independent AND parallelism in Prolog programs and is suitable forexecution on both shared and nonshared memory machines. We discuss the performanceof the Prolog compiler in some detail and describe how grain size can be used to deliverperformance that is within 10% of the underlying sequential Prolog compiler on oneprocessor, and scale linearly with increasing number of processors on problems exhibiting sufficient parallelism. The loose coupling between parallel and sequential components makes it possible to use the best available sequential compiler as the sequential component of our compiler.
Dialog template description tool
Authors: Kyosuke Saigusa, Yoshinori Saigusa
Venue: ACM SIGAPL APL Quote Quad (2002)

Application end-user interface normally required by industries can be programmed using mainly AP124 and AP145 in IBM APL2 for Windows. AP124, however, does not support Japanese language in Windows environments. This forces us to depend more on AP145. This tool aims at providing APL2 programmers with a better tool than the Dialog Editor provided as a component of the IBM APL2 product to create and maintain AP145 dialog templates.
The LBG-U Method for Vector Quantization &ndash; an Improvement over LBGInspired from Neural Networks
Authors: Bernd Fritzke
Venue: Neural Processing Letters (1997)

A new vector quantization method (LBG-U) closely related to a particular class of neural network models (growing self-organizing networks) is presented. LBG-U consists mainly of repeated runs of the well-known LBG algorithm. Each time LBG converges, however, a novel measure of utility is assigned to each codebook vector. Thereafter, the vector with minimum utility is moved to a new location, LBG is run on the resulting modified codebook until convergence, another vector is moved, and so on. Since a strictly monotonous improvement of the LBG-generated codebooks is enforced, it can be proved that LBG-U terminates in a finite number of steps. Experiments with artificial data demonstrate significant improvements in terms of RMSE over LBG combined with only modestly higher computational costs.
A study on the management of semantic transaction for efficient data retrieval
Authors: Shi Ming Huang, Irene Kwan, Chih He Li
Venue: ACM SIGMOD Record (2002)

Mobile computing technology is developing rapidly due to the advantages of information access through mobile devices and the need to retrieve information at remote locations. However, many obstacles within the discipline of wireless computing are yet to be resolved. One of the most significant of these issues is the speed of data retrieval, which directly affects the performance of mobile database applications. To remedy this problem, we propose here a revised methodology focusing on the management of mobile transactions. This paper investigates an extended semantic-based transaction management mechanism, and applies a model-based approach for developing a simulation model to evaluate the performance of our approach.