ppxscal/embedding_network huggingface dataset:
The Design and Implementation of a Full-Fledged Multiple DBMS
Authors: Shu-Chin Su Chen, Chih-Shing Yu, Yen-Yao Yao, San-Yih Hwang, B. Paul Lin
Venue: Proceedings of the Eleventh International Conference on Data Engineering (1995)

We have described our design of the multiple DBMS (MDBMS). This MDBMS enables users to access data controlled by different DBMSs as if data were managed by a single DBMS. It supports facilities for SQL queries and transactions, and considers security functions. In addition, an ODBC driver at the client site has been realized to ease the development of MDBMS applications. Several popular commercial DBMSs, including Oracle, Informix and Sybase, have been successfully integrated. The MDBMS is in operation now. However, we found the performance to be unsatisfactory. It took about several seconds to process an SQL query with single join on two relations of hundreds of tuples. We have identified the performance bottleneck to be on the retrieval of meta data. The current MDBMS Server employs a commercial DBMS to store meta data, which is necessary for processing a global query. The processing of a query is slow because it needs to retrieve the schema information via an external DBMS several times. We are currently designing a core storage manager and an access manager specifically for maintaining the meta data and the intermediate results of a global query. We expect this design to significantly improve the performance.
Fault-Tolerant Parallel Applications Using Queues and Actions
Authors: J. A. Smith, Santosh K. Shrivastava
Venue: Proceedings of the international Conference on Parallel Processing (1997)

There are many techniques supporting execution of large computations over a network of workstations (NOW) but data intensive computations are usually run on high performance parallel machines. A NOW comprising individual user's machines typically has a low performance interconnect and suffers arbitrary changes of availability. Exploiting such resources to execute data intensive computations is difficult, but even in a more constrained environment there is an unfulfilled need for fault-tolerance. The structuring approach presented fulfills this need. Performance exceeding 100~Mflop/s is demonstrated for large fault-tolerant out of core examples of matrix multiplication and Cholesky factorisation using five 133~MHz Pentium compute machines.
Agent-Based Hierarchical Video Presentation Over Internet
Authors: Linsong Cai, Xiao Liu, Wael M. Badawy
Venue: Proceedings of the 1st IEEE International Conference on Cognitive Informatics (2002)

This paper presents an algorithm for web-based hierarchical video presentation, where a novel Hierarchical Adaptive Optimum Mesh (HAOM) is proposed as the key technique. By using optimum cutsets of HAOM, video contents are coded at different resolution level. The cutset generation algorithm considers a combination of parameters, including frame rate availability, bit rate constrains and Quality-of-Service (QoS) requirements, etc. The performance analysis is also presented and it shows the efficiency of proposed HAOM
Distributed, Scalable, Dependable Real-Time Systems: Middleware Services and Applications
Authors: Lonnie R. Welch, Binoy Ravindran, Paul V. Werme, Michael W. Masters, Behrooz Shirazi, Prashant A. Shirolkar, Robert D. Harrison, D. Wayne Mills, Tuy Do, Judy Lafratta, Shafqat Anwar, Steve Sharp, Terry Sergeant, George Bilowus, Mark Swick, Jim Hoppel, Joseph M. Caruso
Venue: Proceedings of the 13th International Symposium on Parallel Processing and the 10th Symposium on Parallel and Distributed Processing (1999)

Some classes of real-time systems function in environments which cannot be modeled with static approaches. In such environments, the arrival rates of events which drive transient computations may be unknown. Also, the periodic computations may be required to process varying numbers of data elements per period, but the number of data elements to be processed in an arbitrary period cannot be known at the time of system engineering, nor can an upper bound be determined for the number of data items; thus, a worst case execution time cannot be obtained for such periodics. This paper presents middleware services that support such dynamic real-time systems through adaptive resource management. The middleware services have been implemented and employed for components of the experimental Navy system described in [10]. Experimental characterizations show that the services provide timely responses, that they have a low degree of intrusiveness on hardware resources, and that they are scalable.
Tree-Like Counterexamples in Model Checking
Authors: Edmund M. Clarke, Somesh Jha, Yuan Lu, Helmut Veith
Venue: Proceedings of the 17th Annual IEEE Symposium on Logic in Computer Science (2002)

Counterexamples for specification violations provide engineers with important debugging information. Although counterexamples are considered one of the main advantages of model checking, state-of the art model checkers are restricted to relatively simple counterexamples, and surprisingly little research effort has been put into counterexamples. In this paper, we introduce a new general framework for counterexamples. The paper has three main contributions: (i) We determine the general form of ACTL counterexamples. To this end, we investigate the notion of counterexample and show that a large class of temporal logics beyond ACTL admits counterexamples with a simple tree-like transition relation. We show that the existence of tree-like counterexamples is related to a universal fragment of extendedbranching time logic based on !
Expanding an Extended Finite State Machine to aid Testability
Authors: Robert M. Hierons, T.-H. Kim, Hasan Ural
Venue: Proceedings of the 26th International Computer Software and Applications Conference on Prolonging Software Life: Development and Redevelopment (2002)

The problem of testing from an extended finite state machine (EFSM) is complicated by the presence of infeasible paths. This paper considers the problem of expanding an EFSM in order to bypass the infeasible path problem. The approach is developed for the specification language SDL but, in order to aid generality, the rewriting process is broken down into two phases: producing a normal form EFSM (NF-EFSM) from an SDL specification and then expanding this NF-EFSM.
Mobile Internet Usability: What Can 'Mobile Learning' Learn from the Past?
Authors: Maria Uther
Venue: Proceedings IEEE International Workshop on Wireless and Mobile Technologies in Education (2002)

Mobile Learning' is a type of application/service that generally presumes to use mobile Internet technology for learning purposes. This paper focuses on discussing basic usability principles from Mobile Internet technologies in general. It is argued that part of the success of Mobile Learning' will depend on the extent to which current k nowledge about best practice in usability are heeded.
Transparent Threads: Resource Sharing in SMT Processors for High Single-Thread Performance
Authors: Gautham K. Dorai, Donald Yeung
Venue: Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques (2002)

Simultaneous Multithreading (SMT) processors achieve high processor throughput at the expense of single-thread performance. This paper investigates resource allocation policies for SMT processors that preserve, as much as possible, the single-thread performance of designated "foreground" threads, while still permitting other "background" threads to share resources. Since background threads on such an SMT machine have a near-zero performance impact on foreground threads, we refer to the background threads as transparent threads. Transparent threads are ideal for performing low-priority or non-critical computations, with applications in process scheduling, subordinate multithreading, and on-line performance monitoring.To realize transparent threads, we propose three mechanisms for maintaining the transparency of background threads: slot prioritization, background thread instruction-window partitioning, and background thread flushing. In addition, we propose three mechanisms to boost background thread performance without sacrificing transparency: aggressive fetch partitioning, foreground thread instruction-window partitioning, and foreground threadflushing. We implement our mechanisms on a detailed simulator of an SMT processor, and evaluate them using 8 benchmarks, including 7 from the SPEC CPU2000 suite. Our results show when cache and branch predictor interference are factored out, background threads introduce less than 1% performance degradation on the foreground thread. Furthermore, maintaining the transparency of background threads reduces their throughput by only 23% relative to an equal priority scheme.To demonstrate the usefulness of transparent threads, we study Transparent Software Prefetching (TSP), an implementation of software data prefetching using transparent threads. Due to its near-zero overhead, TSP enables prefetch instrumentation for all loads in a program, eliminating the need for profiling. TSP, without any profile information, achieves a 9.52% gain across 6 SPEC benchmarks, whereas conventional software prefetching guided by cache-miss profiles increases performance by only 2.47%.
A Fuzzy Paradigm Approach for the Cognitive Process of Categorization
Authors: Cristina Maria Varachiu, Nicolae Varachiu
Venue: Proceedings of the 1st IEEE International Conference on Cognitive Informatics (2002)

An example of using fuzzy paradigm in categorization/pattern recognition process is presented, emphasizing also that fuzziness is a useful alternative to randomness in dealing with uncertainty. In real world situations many experiences, occurrences, processes are non-deterministic, and the arising uncertainty is a natural and important component of human, social and technical systems. We try to demonstrate that in the cognitive process ofcategorization, to deal with uncertainty -with an important one, the fuzzy uncertainty- is a useful approach, and the uncertainty is an important component of the real word; and we have to cope with it, not to consider it as a "residual" problem.
Dichotomy-based Model for FSM Power Minimization
Authors: Lakshmikant Bhupathi, Liang-Fang Chao
Venue: Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors (1996)

Switching activity and capacitive load both affect power consumption in VLSI circuits. In two-level logic implementations, due to the regular structure, more information about the final implementation is available at an early stage. In order to optimize power during the state encoding step in the synthesis of finite state machines (FSMs), both capacitance and switching activity need to be considered. Most of the previous work does not consider accurate measures of both capacitance and switching activity on all nodes in the circuit simultaneously. We propose a new approach based on the concept of dichotomy, to find accurate measures for both switching activity and capacitive load on all nodes in two-level implementations of FSMs from their symbolic specification. The area of the resulting implementation can also be measured in the proposed model. Experimental results on MCNC benchmarks indicate the effectiveness of our approach in reducing the power consumption. The areas of the resulting implementations are also reduced in almost all the cases, indicating that power and area are strongly related in two-level implementations.
Translation of Object-Oriented Queries to Relational Queries
Authors: Clement T. Yu, Yi Zhang, Weiyi Meng, Won Kim, Gaoming Wang, Tracy Pham, Son Dao
Venue: Proceedings of the Eleventh International Conference on Data Engineering (1995)

Proposes a formal approach for translating OODB queries to equivalent relational queries. The translation is accomplished through the use of relational predicate graphs and OODB predicate graphs. One advantage of using such a graph-based approach is that we can achieve bidirectional translation between relational queries and OODB queries.
Tools for Personalised Annotation and Organisation of Diverse Web Resources
Authors: Annika Wolff, Zdenek Zdráhal, Zdenek Kouba
Venue: Proceedings of the 13th International Workshop on Database and Expert Systems Applications (2002)

The CIPHER project is concerned with developing tools and methodologies to support the exploration of cultural heritage via web-based Cultural Heritage Forums. As part of the project, a Resource Annotation Tool (RAT) is being developed to support the collection, annotation and retrieval of diverse web-resources to provide content for personal or shared spaces within a forum. Interaction with the RAT tool will enable a user to reuse and personalise an official site ontology, based on personal interests and for a group of users to identify overlapping areas of interest. Tools will further be provided to facilitate users in the construction of coherent stories using their personal content, based on narrative principles. This paper describes the existing functionality of the RAT tool and plans for future development.
Automated Generation of Statistical Test Cases from UML State Diagrams
Authors: Philippe Chevalley, Pascale Thévenod-Fosse
Venue: Proceedings of the 25th International Computer Software and Applications Conference on Invigorating Software Development (2001)

The adoption of the object-oriented (OO) technology for the development of critical software raises important testing issues. This paper addresses one of these issues: how to create effective tests from OO specification documents? More precisely, the paper describes a technique that adapts a probabilistic method, called statistical functional testing, to the generation of test cases from UML state diagrams, using transition coverage as the testing criterion. Emphasis is put on defining an automatic way to produce both the input values and the expected outputs. The technique is automated with the aid of the Rational Software Corporation's Rose RealTime tool. An industrial case study from the avionics domain, formally specified and implemented in Java, is used to illustrate the feasibility of the technique at the subsystem level. Results of first test experiments are presented to exemplify the fault revealing power of the created statistical test cases.
Optimally Scaling Permutation Routing on Reconfigurable Linear Arrays with Optical Buses
Authors: Jerry L. Trahan, Anu G. Bourgeois, Ramachandran Vaidyanathan, Yi Pan
Venue: Proceedings of the 13th International Symposium on Parallel Processing and the 10th Symposium on Parallel and Distributed Processing (1999)

We present an optimal and scalable permutation routing algorithm for three reconfigurable models based on linear arrays that allow pipelining of information through an optical bus. Specifically, for any P=N, our algorithm routes any permutation of N elements on a P-processor model optimally in O (N/p) steps. This algorithm extends naturally to one for routing h-relations optimally in O(h) steps. We also establish the equivalence of the three models, LARPBS, LPB, and POB. This implies an automatic translation of algorithms (without loss of speed or efficiency) among these models.
Toward data distribution independent parallel matrix multiplication
Authors: Hyuk-Jae Lee, José A. B. Fortes
Venue: Proceedings of the 9th International Symposium on Parallel Processing (1995)

To eliminate or reduce initial data redistribution overheads for distributed memory parallel computers, this paper considers the problem of writing data distribution independent (DDI) programs whose functionality and execution time are independent of initial data distributions. Relations between time-space mappings and input data distributions are established. These relations are the basis of a systematic approach to the derivation of DDI programs which is illustrated for matrix-matrix multiplication. Conditions on data distributions that correspond to an optimal modular mapping are provided. It is shown that only twelve programs suffice to accomplish redistribution-free execution for the many input data distributions that satisfy the above conditions. When DDI matrix multiplication programs are used in an algorithm with multiple matrix products, half of data redistributions otherwise required can be eliminated.
Automatic Decidability
Authors: Christopher Lynch, Barbara Morawska
Venue: Proceedings of the 17th Annual IEEE Symposium on Logic in Computer Science (2002)

We give a set of inference rules with constant constraints. Then we show how to extend a set of equational clauses, so that if the application of these inference rules halts on these clauses, then the theory is decidable by applying a standard set of Paramodulation inference rules. In addition, we can determine the number of clauses generated in this decision procedure. For some theories, such as the theory of lists, there are O(n × lg(n)) clauses. For others it is polynomial. And for others it is simply exponential such as the theory of (extensional) arrays.
A programmable routing controller for flexible communications in point-to-point networks
Authors: Stuart W. Daniel, Jennifer Rexford, James W. Dolter, Kang G. Shin
Venue: Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors (1995)

Modern parallel and distributed applications have a wide range of communication characteristics and performance requirements. This paper presents programmable routing controller (PRC), a custom ASIC that supports flexible network policies to accommodate diverse application requirements. By dedicating a small programmable processor to each incoming link, the PRC can implement wormhole, virtual cut-through, and packet switching, as well as hybrid schemes, under a variety of unicast and multicast routing algorithms. The PRC can support several applications or traffic types simultaneously by implementing multiple routing-switching microcode routines.
Microarchitectural synthesis of gracefully degradable, dynamically reconfigurable ASICs
Authors: Alex Orailoglu
Venue: Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors (1996)

In this paper, we propose a novel fault-tolerance scheme, band reconfiguration, to handle multiple permanent faults in functional units of general ASIC designs. An associated high-level synthesis procedure that automatically generates such fault-tolerant systems is also presented. The proposed scheme permits multiple levels of graceful degradation. During each reconfiguration the system instantly reconfigures itself through operation rescheduling and hardware rebinding. The design objectives are optimization of resource utilization rate under each configuration, and reduction of hardware and performance overheads. The proposed high-level synthesis approach enables fast and area-effective implementations of gracefully degradable ASICs.
How Much Testing is Enough? Applying Stopping Rules to Behavioral Model Testing
Authors: Tom Chen, Anneliese von Mayrhauser, Amjad Hajjar, Charles Anderson, Mehmet Sahinoglu
Venue: The 4th IEEE International Symposium on High-Assurance Systems Engineering (1999)

Testing behavioral models before they are released to the synthesis and logic design phase is a tedious process, to say the least. A common practice is the "test-it-to-death" approach in which millions or even billions of vectors are applied and the results are checked for possible bugs. The vectors applied to behavioral models include functional vectors, but the significant amount of the vectors are random in nature, including random combinations of instructions. In this paper, we present and evaluate a stopping rule that can be used to determine when to stop the current testing phase using a given testing technique, and move on to the next phase using a different testing technique. We demonstrate the use of the stopping rule on two complex VHDL models that were tested for branch coverage with 4 different testing phases. We compare savings and quality of testing both with and without using the stopping rule.
A Syntactic Approach to Foundational Proof-Carrying Code
Authors: Nadeem A. Hamid, Zhong Shao, Valery Trifonov, Stefan Monnier, Zhaozhong Ni
Venue: Proceedings of the 17th Annual IEEE Symposium on Logic in Computer Science (2002)

Proof-Carrying Code (PCC) is a general framework for verifying the safety properties of machine-language programs. PCC proofs are usually written in a logic extended with language-specific typing rules. In Foundational Proof-Carrying Code (FPCC), on the other hand, proofs are constructed and verified using strictly the foundations of mathematical logic, with no type-specific axioms. FPCC is more flexible and secure because it is not tied to any particular type system and it has a smaller trusted base.Foundational proofs, however, are much harder to construct. Previous efforts on FPCC all required building so-phisticated semantic models for types. In this paper, we present a syntactic approach to FPCC that avoids the difficulties of previous work. Under our newscheme, the foundational proof for a typed machine program simply consists of the typing derivation plus the formalized syntactic soundness proof for the underlying type system. We give a translation from a typed assembly language into FPCC and demonstrate the advantages of our new system via an implementation in the Coq proof assistant.
DynaMICs: An Automated and Independent Software-FaultDetection Approach
Authors: Ann Q. Gates, Patricia J. Teller
Venue: The 4th IEEE International Symposium on High-Assurance Systems Engineering (1999)

Computers are omnipresent in our society, creating a reliance that demands high-assurance systems. Traditional verification and validation approaches may not be sufficient to identify the existence of software faults. Dynamic Monitoring with Integrity Constraints (DynaMICs) augments existing approaches by including: 1) elicitation of constraints from domain experts and developers that capture knowledge about real-world objects, assumptions, and limitations, 2) constraints stored and maintained separate from the program, 3) automatic generation of monitoring code and program instrumentation, 4) performance-friendly monitoring, and 5) tracing among specifications, code, and documentation. The primary motivation for DynaMICs is to facilitate the detection of faults, in particular those that result from insufficient communication, change in intended software use, and errors introduced through external interfaces. After presenting related work and an overview of DynaMICs, this paper outlines the methodology used to provide an automated and independent software-fault detection system.
Load sharing in the training set partition algorithm for parallel neural learning
Authors: Bernard Girau, Hélène Paugam-Moisy
Venue: Proceedings of the 9th International Symposium on Parallel Processing (1995)

A parallel back-propagation algorithm that partitions the training set on a ring of processors has been introduced. In this paper, we study the performance of this algorithm on MIMD machines and develop a new version, based on a heterogeneous load sharing. Algebraic models allow precise comparisons between the different methods, and show great improvements in case of parallel learning.