ppxscal/embedding_network huggingface dataset:
A conceptual and pedagogical framework for teaching ethics and social impact in computer science
Authors: C. D. Martin
Venue: Proceedings of the Frontiers in Education Conference,1997. on 27th Annual Conference. Teaching and Learning in an Era of Change. - Volume 01 (1997)

Computer science as a pedagogical discipline continues to advance rapidly, and this advance necessitates frequent revision of the curriculum. One of the fundamental changes in computer science is the realization that the context and impact of new technologies need to be taken into account in its design, partly because of the ethical implications of its use, and partly because understanding the consequences of use helps to inform and improve the design. Project ImpactCS was funded by the National Science Foundation in 1994 with the goal to define the conceptual framework, core content, and pedagogical objectives for integrating social impact and ethics into the computer science curriculum.
Fast Firmware Implementation of RSA-Like Security Protocol for Mobile Devices
Authors: Ren-Junn Hwang, Feng-Fu Su, Loang-Shing Huang
Venue: Wireless Personal Communications: An International Journal (2007)

In modern mobile communications, personal privacy and security are of top concern to mobile phone subscribers. Yet, owing to the limit of their processing capability, mainstream mobile manufacturers are still unable to apply advanced security protocol to mobile devices. It should be noted that many security protocols are based on RSA algorithm. To implement RSA algorithm and thus apply many advanced security protocols to mobile networks, this paper proposes an efficient and practical method based on the Texas Instruments TMS320C55x family. When the proposed method is employed, it takes only 7.9 milliseconds to perform a 1024-bit RSA encryption operation at the clock frequency of 200 MHz. Our decryption operation is at least 3.5 times faster than the time taken to perform the same operation without employing the proposed method. In addition, the proposed method can stop any power-analysis attack on RSA-based security protocols, thereby enhancing the security of mobile environments.
Government-Enterprise Ecosystem Gateway (G-EEG) for Seamless e-Government
Authors: Elsa Estevez, Tomasz Janowski
Venue: Proceedings of the 40th Annual Hawaii International Conference on System Sciences (2007)

The paper presents some challenges to Seamless e- Government, and proposes a technical solution - Government-Enterprise Ecosystem Gateway (G-EEG) to address them. G-EEG is a framework through which multi-organizational processes and applications can dynamically build, apply and evolve complex communication structures to asynchronously exchange messages in specific application contexts, e.g. to deliver seamless public services. In addition to basic messaging, G-EEG supports high-level messaging functions through dynamically-enabled horizontal (process-independent) or vertical (process-dependent) extensions. A number of extensions are described as solutions to the challenges for seamless e-Government. Currently a research prototype, G-EEG is specified formally and implemented using open standards.
Detection of target speakers in audio databases
Authors: I. Magrin-Chagnolleau
Venue: Proceedings of the Acoustics, Speech, and Signal Processing, 1999. on 1999 IEEE International Conference - Volume 02 (1999)

The problem of speaker detection in audio databases is addressed in this paper. Gaussian mixture modeling is used to build target speaker and background models. A detection algorithm based on a likelihood ratio calculation is applied to estimate target speaker segments. Evaluation procedures are defined in detail for this task. Results are given for different subsets of the HUB4 broadcast news database. For one target speaker, with the data restricted to high quality speech segments, the segment miss rate is approximately 7%. For unrestricted data, the segment miss rate is approximately 27%. In both cases the segment false alarm rate is 4 or 5 per hour. For two target speakers with unrestricted data, the segment miss rate is approximately 63% with about 27 segment false alarms per hour. The decrease in performance for two target speakers is largely associated with short speech segments in the two target speaker test data which are undetectable in the current configuration of the detection algorithm.
End-to-end monitoring service for multicast-based high-quality real-time media delivery
Authors: Ju-Won Park, Sangwoo Han, JongWon Kim
Venue: Proceedings of the End-to-End Monitoring Techniques and Services on 2005. Workshop (2005)

As the demand for high-quality real-time media service through multicast-enabled AG (access grid) increases, the end-to-end QoS (quality of service) provisioning of the media service has become very important. To guarantee the end-to-end QoS, it is essential to monitor the time-varying status of both network (i.e., delay, jitter and loss) and system metrics (i.e., CPU and memory utilization). In this paper, we propose a new service for the AG, to monitor the time-varying conditions of both multicast networks and the AG node systems. When the performance of the AG degrades, the proposed monitoring attempts to pinpoint the cause of performance degradation and explores corresponding reactions to improve the end-to-end performance of the AG. The experimental results show that the proposed monitoring service is really useful in improving the quality of media service for the AG.
On the maximum cardinality search lower bound for treewidth
Authors: Hans L. Bodlaender, Arie M. C. A. Koster
Venue: Discrete Applied Mathematics (2007)

The Maximum Cardinality Search (MCS) algorithm visits the vertices of a graph in some order, such that at each step, an unvisited vertex that has the largest number of visited neighbours becomes visited. A maximum cardinality search ordering (MCS-ordering) of a graph is an ordering of the vertices that can be generated by the MCS algorithm. The visited degree of a vertex v in an MCS-ordering is the number of neighbours of v that are before v in the ordering. The visited degree of an MCS-ordering @j of G is the maximum visited degree over all vertices v in @j. The maximum visited degree over all MCS-orderings of graph G is called its maximum visited degree. Lucena [A new lower bound for tree-width using maximum cardinality search, SIAM J. Discrete Math. 16 (2003) 345-353] showed that the treewidth of a graph G is at least its maximum visited degree. We show that the maximum visited degree is of size O(logn) for planar graphs, and give examples of planar graphs G with maximum visited degree k with O(k!) vertices, for all k@?N. Given a graph G, it is NP-complete to determine if its maximum visited degree is at least k, for any fixed k>=7. Also, this problem does not have a polynomial time approximation algorithm with constant ratio, unless P=NP. Variants of the problem are also shown to be NP-complete. In this paper, we also propose some heuristics for the problem, and report on an experimental analysis of them. Several tiebreakers for the MCS algorithm are proposed and evaluated. We also give heuristics that give upper bounds on the value of the maximum visited degree of a graph, which appear to give results close to optimal on many graphs from real life applications.
Experiences of sparse direct symmetric solvers
Authors: Jennifer A. Scott, Yifan Hu
Venue: ACM Transactions on Mathematical Software (TOMS) (2007)

We recently carried out an extensive comparison of the performance of state-of-the-art sparse direct solvers for the numerical solution of symmetric linear systems of equations. Some of these solvers were written primarily as research codes while others have been developed for commercial use. Our experiences of using the different packages to solve a wide range of problems arising from real applications were mixed. In this paper, we highlight some of these experiences with the aim of providing advice to both software developers and users of sparse direct solvers. We discuss key features that a direct solver should offer and conclude that while performance is an essential factor to consider when choosing a code, there are other features that a user should also consider looking for that vary significantly between packages.
Delay Test Quality Evaluation Using Bounded Gate Delays
Authors: Soumitra Bose, Vishwani D. Agrawal
Venue: Proceedings of the 25th IEEE VLSI Test Symmposium (2007)

Conventionally, path delay tests are derived in a delay-independent manner, which causes most faults to be robustly untestable. Many non-robust tests are invalidated by hazards caused primarily due to non-zero delays of off-path circuit elements. Thus, non-robust tests are of limited value when process variations change gate delays. We propose a bounded gate delay model for test quality evaluation and give a novel simulation algorithm that is less pessimistic than previous approaches. The key idea is that certain time-correlations among the multiple transitions at the inputs of a gate cannot cause hazard at its output. We maintain "ambiguity lists" for gates. These are propagated with events, similar to fault lists in a traditional concurrent fault simulation. They are used to suppress erroneous unknown states. Experimental results for ISCAS benchmarks with gate delay variation of ±14% show a miscorrelation of critical path delay as much as 20%.
Mobile Technology enabling Congestion charging A multi perspective analysis of the Stockholm Trial
Authors: Bjorn Rosengren
Venue: Proceedings of the International Conference on the Management of Mobile Business (2007)

The population of vehicles in the world increases every year and has now reached almost 1 billion. Most large cities have severe congestion and environment problems. Many cities could benefit from implementation of congestion charging systems. The City of Stockholm has done this in a large-scale trial enabled by mobile technology. The analysis of the trial is based on a multi perspective approach where three partly overlapping perspectives are used to get an understanding and overview of the trial solution regarded as a sociotechnical system. The trial has proven that the used mobile technology is mature, reliable, and robust. The personal and organisational elements are more uncertain in their behaviour. These are complex elements and cannot be fully understood by cause-effect analysis. This study has shown that there is a strong interdependence between the elements and the behaviour of the whole system.
Interactive presentation: An FPGA based all-digital transmitter with radio frequency output for software defined radio
Authors: Zhuan Ye, John Grosspietsch, Gokhan Memik
Venue: Proceedings of the conference on Design, automation and test in Europe (2007)

In this paper, we present the architecture and implementation of an all-digital transmitter with radio frequency output targeting an FPGA device. FPGA devices have been widely adopted in the applications of digital signal processing (DSP) and digital communication. They are typically well suited for the evolving technology of software defined radios (SDR) due to their reconfigurability and programmability. However, FPGA devices are mostly used to implement digital baseband and intermediate frequency (IF) functionalities. Therefore, significant analog and RF components are still needed to fulfill the radio communication requirements. The all-digital transmitter presented in this paper directly synthesizes RF signal in the digital domain, therefore eliminates the need for most of the analog and RF components. The all-digital transmitter consists of one QAM modulator and one RF pulse width modulator (RFPWM). The binary output waveform from RFPWM is centered at 800MHz with 64QAM signaling format. The entire transmitter is implemented using Xilinx Virtex2pro device with on chip multi-gigabit transceiver (MGT). The adjacent channel leakage ratio (ACLR) measured in the 20 MHz passband is 45dB, and the measured error vector magnitude (EVM) is less than 1%. Our work extends the digital implementation of communication applications on an FPGA platform to radio frequency, therefore making a significant evolution towards an ideal SDR.
Memorizing What You Did Last Week: Towards Detailed Actigraphy With A Wearable Sensor
Authors: Kristof Van Laerhoven, Andre Kvist Aronsen
Venue: Proceedings of the 27th International Conference on Distributed Computing Systems Workshops (2007)

With sensors becoming smaller and more power efficient, wearable sensors that anyone could wear are becoming a feasible concept. We demonstrate a small lightweight module, called Porcupine, which aims at continuously monitoring human activities as long as possible, and as fine-grained as possible. We present initial analysis of a set of abstraction algorithms that combine and process raw accelerometer data and tilt switch states, to get descriptors of the user's motion-based activities. The algorithms are running locally, and the information they produce is stored in on-board memory for later analysis.
Tendering Process Model (TPM) Implementation for B2B Integration in a Web Services Environment
Authors: Lick Lun Nick Ng, Dickson K. W. Chiu, Patrick C. K. Hung
Venue: Proceedings of the 40th Annual Hawaii International Conference on System Sciences (2007)

Improvements can be made for tendering processes to solve B2B interoperability and integration problem by means of Web services technology. In this paper, we detail our tendering process model (TPM) based on Web services with SOAP messages exchange in XML format to improve inefficient manual or semiautomated tendering process. Adopting TPM, seeking ideal tender-supplier couple (TSC) with a business-to-business (B2B) application is illustrated as a real example to find best tender for suppliers and best quotation for tenders respectively. The approach discussed in this paper is a novel application in tendering process of logistics industry and is beneficial to stake-holders involved.
Metrics for data warehouse conceptual models understandability
Authors: Manuel Serrano, Juan Trujillo, Coral Calero, Mario Piattini
Venue: Information and Software Technology (2007)

Due to the principal role of Data warehouses (DW) in making strategy decisions, data warehouse quality is crucial for organizations. Therefore, we should use methods, models, techniques and tools to help us in designing and maintaining high quality DWs. In the last years, there have been several approaches to design DWs from the conceptual, logical and physical perspectives. However, from our point of view, none of them provides a set of empirically validated metrics (objective indicators) to help the designer in accomplishing an outstanding model that guarantees the quality of the DW. In this paper, we firstly summarise the set of metrics we have defined to measure the understandability (a quality subcharacteristic) of conceptual models for DWs, and present their theoretical validation to assure their correct definition. Then, we focus on deeply describing the empirical validation process we have carried out through a family of experiments performed by students, professionals and experts in DWs. This family of experiments is a very important aspect in the process of validating metrics as it is widely accepted that only after performing a family of experiments, it is possible to build up the cumulative knowledge to extract useful measurement conclusions to be applied in practice. Our whole empirical process showed us that several of the proposed metrics seems to be practical indicators of the understandability of conceptual models for DWs.
Digital Generation of Signals for Low Cost RF BIST
Authors: Marcelo Negreiros, Luigi Carro, Altamiro A. Susin
Venue: Proceedings of the 12th IEEE European Test Symposium (2007)

RF test signals are a requirement for the implementation of effective BIST techniques in transceivers. In this work a method to encode a binary signal with the desired RF frequency is presented. The approach employs high-pass sigma delta modulators, in contrast to conventional low-pass or band-pass approaches, allowing signal generation close to the Nyquist limit of FS/2 (FS=Sampling Frequency). As a digital signal is used, only a 1-bit DAC is needed, reducing test costs. Practical results using a 3Gbps transceiver illustrate the performance achievable by the method.
Computer-aided design of high throughput fully parallel ldpc decoder in 3-dimensional integrated circuits
Authors: C.-J. Richard Shi
Venue:  (2006)

The revolution of VLSI fabrication technologies in the past forty years has led to a constant reduction of transistor feature sizes, and provided faster clock rates and ever-greater densities of transistors. It is now reaching to a "scaling wall", which prohibits further integration of system functionalities to silicon. Three-dimensional (3D) circuit, which takes advantages of the third dimension, is composed of multiple active circuit layers that are vertically stacked to allow shorter interconnection paths, thus promises higher clock rates, less power dissipation, and higher integration density. To support large-scale ASIC designs exploiting this 3D technology, in the first part of this dissertation, CASCADE---a standard super-cell based design methodology, its supporting automated design flow, and associated design tools, are presented for 3D implementations of a class of interconnect-heavy application-specific VLSI circuits. On the other hand, Low Density Parity Check (LDPC) codes are now one of the most intensely studied topics in coding area due to their near Shannon-limit error correction performance. The inherent block-parallel decoding scheme results in the advantage of high-throughput, however, it also introduces the challenge of hard-ware implementation especially the requirement of large amount of interconnection resources. 3D technology, which is capable of achieving shorter wire length and lower routing density, is one of the promising solutions to overcome this challenge. In the second part of this dissertation, a 1024-bit, &half;-rate, 2Gb/s throughput fully parallel LDPC decoder using the state-of-the-art 3D IC process is presented. It is the first large-scale 3D ASIC design. By taking the advantage of 3D IC process with 3-tier integration, it shows an order of magnitude improvement over the corresponding 2D process in terms of power-delay-area product. Moreover, in order to push the envelope of the throughput of the current LDPC decoder, the asynchronous pipelined and C-slow retiming high-throughput fully parallel LDPC decoder is proposed in the third part of this dissertation.
SMP scalability comparisons of linux ® kernels 2.2.14 and 2.3.99
Authors: Ray Bryant, Bill Hartner, Qi He, Ganesh Venkitachalam
Venue: Proceedings of the 4th annual Linux Showcase & Conference - Volume 4 (2000)

The Linux 2.4 kernel should provide significantly better SMP scalability than is available in the 2.2 series. While the development of the 2.4 kernel is still continuing, performance studies on the 2.3.99 kernels can be used as an indicator of what the performance of the 2.4 kernel will be like. In this paper, we compare performance and SMP scalability of Linux 2.2.14 and Linux 2.3.99 on the Intel® 32-bit platform using four benchmarks. Three of these are targeted to specific system components; the fourth is SPECweb99TM. SMP scaling for these benchmarks is shown to be significantly better with 2.3.99 than it is with 2.2.14. This should translate into significantly better SMP scaling (and hence additional raw performance on SMP systems) for applications running under Linux 2.4.
Real-time DSP and FPGA Implementation of Wiener LMS Based Multipath Channel Estimation in 3G CDMA Systems
Authors: Messaoud Ahmed Ouameur, Daniel Massicotte
Venue: Journal of VLSI Signal Processing Systems (2007)

This paper investigates real-time DSP and FPGA implementations of a low complexity technique for asynchronous multiuser delay acquisition and time varying channel tracking for multipath channels in WCDMA and cdma2000 systems. A multiuser-LMS-like structure along with smoothing/prediction filters to improve tracking quality is reviewed. We investigate an efficient implementation based on FFT/IFFT technique, under fixed-point data representation and computation constraint. The measured BER reveals that fixed-point implementation is feasible at possibly no performance degradation. Based on real time execution made on a fixed-point high performance DSP, the maximum number of users is 15 and 17 for the proposed method and correlator, respectively. Due to the inherent parallelism and regular data flow FPGA implementation is suggested wherein a maximum number of users more than 80 can be afforded in Xilinx Virtex¿ II Pro device.
A new fourth year elective unit in electronic manufacturing at RMIT University
Authors: P. C. M. Burton
Venue: Proceedings of the 26th Annual Frontiers in Education - Volume 01 (1996)

In an environment of global competition it is essential to produce high quality products with due consideration of cost and time to market. Since there is a major focus today on concurrent engineering in electronic manufacturing, it is critically important that students understand the relevant principles and skills associated with this engineering approach. This paper describes the development of a new fourth year course entitled Electronic Manufacturing which was introduced in July 1995 by the Department of Communication and Electronic Engineering at RMIT University. The authors believe that this paper will be particularly useful to others wishing to develop a course in Electronic Manufacturing, providing insight into the important issues and innovative learning modes built into this program.
Using the vulnerability information of computer systems to improve the network security
Authors: Yeu-Pong Lai, Po-Lun Hsia
Venue: Computer Communications (2007)

In these years, the security problem becomes more important to everyone using computers. However, vulnerabilities on computers are found so frequently that system managers can not patch up all these vulnerabilities on hosts within the network in no time. They need to perform a risk evaluation in order to determine the priority of patching-up vulnerabilities. Besides, they may not have the administrator right on all hosts in the network, but only have the right on these network devices. To keep these vulnerabilities on hosts from exploitation, system managers can set the ACL scripts on network devices. The solution improves security in the network immediately, since some threatened service ports on hosts are blocked from accessed. This paper introduces a method to improve the network security, which consists of the network management, the vulnerability scan, the risk assessment, the access control, and the incident notification. Companioned to the network topology, the risk evaluation indicates the threatened service ports that should be blocked within ACL scripts. These procedures do not cost any extra hardware equipment. With the proposed method, the network security improves almost 40% with only 8% of threatened ports being blocked in the examined Class-B network. The 40% improvement of network security is evaluated with these two indices, the summary of CVSS values and the number of vulnerabilities in the network.
Comparative evaluation of spoken corpora acquired by presentation of visual scenarios and textual descriptions
Authors: D. Aiello
Venue: Proceedings of the Acoustics, Speech, and Signal Processing, 1999. on 1999 IEEE International Conference - Volume 02 (1999)

The paper describes a system, in JAVA for written and visual scenario generation used to collect speech corpora in the framework of a tourism information system. Experimental evidence shows that the corpus generated with visual scenarios has a higher perplexity and a richer vocabulary than the corpus generated using the same conceptual derivations to produce textual scenarios. Furthermore, there is evidence that textual scenarios influence speakers in the choice of the lexicon used to express the concepts more than visual scenarios.