ppxscal/embedding_network huggingface dataset:
Bounding of Performance Measures for Threshold-Based Queuing Systems: Theory and Application to Dynamic Resource Management in Video-on-Demand Servers
Authors: L. Golubchik, J. C. S. Lui
Venue: IEEE Transactions on Computers (2002)

In this paper, we consider a K-server threshold-based queuing system with hysteresis in which the number of active servers is governed by a forward threshold vector and a reverse threshold vector. There are many applications where a threshold-based queuing system can be of great use. The main motivation for using a threshold-based approach in such applications is that they incur significant server setup, usage, and removal costs. As in most practical situations, an important concern is not only the system performance, but rather its cost/performance ratio. The motivation for use of hysteresis is to control the cost during momentary fluctuations in workload. An important and distinguishing characteristic of our work is that, in our model, we consider the time to add a server to be nonnegligible. This is a more accurate model, for many applications, than previously considered in other works. Our goal in this work is to develop an efficient method for computing the steady state probabilities of a multiserver threshold-based queuing system with hysteresis, which will, in turn, allow computation of various performance measures. We also illustrate how to apply this methodology in evaluation of the performance of a Video-on-Demand (VOD) storage server which dynamically manages its I/O resources.
Support for Recovery in Mobile Systems
Authors: Cris Pedregal-Martin, Krithi Ramamritham
Venue: IEEE Transactions on Computers (2002)

Mobile systems increasingly are being used for production-grade data-centered applications which require system support for transactional properties. For mobile applications, transactions can hide, to some extent, the infrastructure intrinsic to mobile systems, such as disconnection from the network, dozing, and storage limitations. In this paper, we introduce a framework to understand, specify, and reason about recovery support for transactional functionality, based on the notion of guarantees (promises one subsystem makes to another) and protocols (prescriptions for correct behavior). We apply our framework to a simple mobile system scenario, yielding an abstract specification that exposes the role of each component in achieving specific transactional semantics support, such as the redo-ability of committed updates that might be lost due to a failure; it also reveals unstated assumptions necessary for the correctness of recovery support. We also show how to reason about alternative ways of obtaining the desired transactional support and the requirements on the components to support recovery and transactions.
Relaxed Steepest Descent and Cauchy-Barzilai-Borwein Method
Authors: Marcos Raydan, Benar F. Svaiter
Venue: Computational Optimization and Applications (2002)

The negative gradient direction to find local minimizers has been associated with the classical steepest descent method which behaves poorly except for very well conditioned problems. We stress out that the poor behavior of the steepest descent methods is due to the optimal Cauchy choice of steplength and not to the choice of the search direction. We discuss over and under relaxation of the optimal steplength. In fact, we study and extend recent nonmonotone choices of steplength that significantly enhance the behavior of the method. For a new particular case (Cauchy-Barzilai-Borwein method), we present a convergence analysis and encouraging numerical results to illustrate the advantages of using nonmonotone overrelaxations of the gradient method.
Using the Shlaer-Mellor Object-Oriented Analysis Method
Authors: Mohamed E. Fayad, Louis J. Hawn, Mark A. Roberts, Jerry R. Klatt
Venue: IEEE Software (1993)

The adaptation of the Shlaer-Mellor object-oriented analysis method for engineering the requirements of a mission-planning system by a missile-guidance software group is discussed. The Shlaer-Mellor object-oriented analysis method provides a structured means of identifying objects within a system by analyzing abstract data types and uses these objects as a basis for building three formal models: information, state, and process. Several issues concerning the application of this method are discussed, including object selection and constraints, modeling and rotation, training, and CASE tool support.
From information to conversation
Authors: Mike Robinson, Yu You, Samuli Pekkola
Venue: ACM SIGGROUP Bulletin (2000)

We support the calls from many commentators to include human interaction in the web, rather than as an extra outside the web. We suggest a generic model of awareness, and some specific interpretations: action-event couplings to call a receiver; general awareness of known others; and local awareness of all others. We then consider extensions to the web into mobile and domestic appliances, and suggest that an underlying awareness service will be needed there as much, or more than in classic desktop web access.
Storage Efficient and Secure Replicated Distributed Databases
Authors: R. Mukkamala
Venue: IEEE Transactions on Knowledge and Data Engineering (1994)

Data availability and security are two important issues in a distributed database system. Existing schemes achieve high availability at the expense of higher storage cost and data security at the expense of higher processing cost. We develop an integrated methodology that combines the features of some existing schemes dealing with data fragmentation, data encoding, partial replication, and quorum consensus concepts to achieve storage efficient, highly available, and secure distributed database systems.
Improved Bounds for Algorithm-Based Fault Tolerance
Authors: D. J. Rosenkrantz, S. S. Ravi
Venue: IEEE Transactions on Computers (1993)

Lower and upper bounds are established for the combinatorial problem of constructing minimal test sets for error detection in multiprocessor systems. The construction for detecting two errors produces minimal test sets, while that for three errors produces test sets whose size exceeds the lower bound by at most one. Also presented is a divide-and-conquer construction scheme for four or more errors.
Beyond Blaming: Congruence in Large Systems Development Projects
Authors: Jean McLendon, Gerald M. Weinberg
Venue: IEEE Software (1996)

Congruence is a concept that describes the human experience of alignment between the internal and external--what is thought and felt, and what is said and how it is said. These authors show how congruence reinforces congruence in a powerful loop that improves the chances of producing a quality product, on time, and within budget. This atmosphere is contagious-when directed consciously to creating a safe, nurturing, productive environment. On the other hand, the same loop causes incongruence to reinforce incongruence. If a project is allowed to ride such a downward spiral, the integrity of information will be destroyed.
Promoting computer literacy: a search for cost-effective alternatives
Authors: Michael A. Steinberg
Venue: Proceedings of the 7th annual ACM SIGUCCS conference on User services (1979)

The use of computers in society today is growing at a startling rate. Consequently, it is becoming increasingly important that today's well-educated college graduates have knowledge about computing. This knowledge, which not only includes exposure to the use of computing but the ability to manipulate computers for one's own individual needs, is what might be termed computer literacy. It is becoming essential that the educational institutions in this country provide students with the opportunity to become computer literate by promoting the use of computing in education. Unfortunately, this has not been done as rapidly as we would like to see. It then becomes an important responsibility for the computer professional in general and the User Services organization in particular to provide both the environment and the motivation for development of computer literacy.There are a number of reasons why instructional computing has grown slowly in the past. One reason is that faculty either do not have the time or do not receive rewards for developing and implementing instructional materials. Another reason is that there is often very little funding available for the acquisition of computing hardware. Making this problem worse is the trend toward tightening of computing budgets at many academic institutions. Fortunately, within recent years, a number of hardware and software alternatives have been developed and are beginning to address these problems.This session will be an examination of some of the alternatives that are available for providing instructional computing facilities at a reasonable cost, thus paving the way for our efforts to promote computer literacy. The hardware alternatives range from the large to small, centralized to decentralized. While inexpensive technology is now available, there are many factors, including logistical, technical, administrative, and political that prevent us from moving immediately to the most modern equipment. The intent of this paper is to suggest alternatives that are viable despite these constraints, and thereby provide a model for those who are evaluating available alternatives.
Filtering Random Graphs to Synthesize Interconnection Networks with Multiple Objectives
Authors: Vijay Lakamraju, Israel Koren, C. M. Krishna
Venue: IEEE Transactions on Parallel and Distributed Systems (2002)

Synthesizing networks that satisfy multiple requirements, such as high reliability, low diameter, good embeddability, etc., is a difficult problem to which there has been no completely satisfactory solution. In this paper, we present a simple, yet very effective, approach to this problem. The crux of our approach is a filtration process that takes as input a large set of randomly generated graphs and filters out those that do not meet the specified requirements. Our experimental results show that this approach is both practical and powerful. The use of random regular networks as the raw material for the filtration process was motivated by their surprisingly good performance with regard to almost all properties that characterize a good interconnection network. This paper provides results related to the generation of networks that have low diameter, high fault tolerance, and good embeddability. Through this, we show that the generated networks are serious competitors to several traditional well-known networks. We also explore how random networks can be used in a packaging hierarchy and comment on the scope of application of these networks.
Advances in DRAM Interfaces
Authors: Masaki Kumanoya, Toshiyuki Ogawa, Kazunari Inoue
Venue: IEEE Micro (1995)

Various kinds of new advanced architectures have been proposed in DRAM interfaces to close the performance gap between DRAMs and MPUs and to break the bandwidth bottleneck of graphic systems. This article gives an overview to some of these new interfaces including EDO, SDRAM, RDRAM, CDRAM, and 3D RAM. The EDO will soon replace conventional DRAM because it requires minimal changes in existing interfaces. The SDRAM will partly take over it in 66 MHz and higher frequency systems with its standardized synchronous interface. Other new interfaces will initially find some target markets where they can take advantage of their unique features, and then they will seek wider market acceptance. The article also briefly discusses a future trend toward "a system on a chip".
Global stability of neural networks with distributed delays
Authors: Yuming Chen
Venue: Neural Networks (2002)

Using the Lyapunov functional approach, we study the global stability of a class of neural networks with distributed delays. Without assuming the boundedness, monotonicity and differentiability of the activation functions and symmetry of the interconnection matrix, we give some new sufficient conditions on the existence, uniqueness and global asymptotic stability of the equilibrium point. Our results improve, extend and complement some existing ones.
Resistivity of two-dimensional systems with electrostatic and magnetic-field modulations
Authors: Seiji Uryu, Tsuneya Ando
Venue: Microelectronic Engineering (2002)

The resistivity determined by electron-electron scattering is studied in two-dimensional systems with weak periodic electrostatic and magnetic-field modulations. Energy gaps opening up at the boundary of the Brillouin zone play an essential role in determining the modulation dependence of the resistivity. The results of numerical calculations are in good agreement with recent experiments.
Beyond-me site: two-handed interface for 3D drawing in MR
Authors: Tomoki Saso, Takeru Tamayama, Masa Inakage
Venue: Proceedings of the 1st international conference on Computer graphics and interactive techniques in Australasia and South East Asia (2003)

"Beyond-Me Site" is a 3D Mixed Reality (MR) gestural drawing system (Figure 1), for which two hands are used. Unlike other MR systems, the device does not require a Head Mounted Display (HMD). Instead, one hand holds the camera and the other hand holds the drawing pad.The HMD, which is widely employed in MR systems, has several problems for use in daily life, such as its cost and awkwardness. We present, therefore, a camera-based, low-cost solution to replace the HMD interface. In our system, the camera, which provides the optical input, is detached from the user's head and held in his or her hand.This style enables the user to move the viewpoint in real space without moving the whole body. We call this style: a "two-handed interface" (Figure 2). By having the interface "two-handed", two diverse tasks can be executed at the same time. If we were to think of a keyboard as being analogous to a piano, a "two-handed interface" would be analogous to an accordion. The goal of "Beyond-Me Site" is to find a handy and efficient way for 3D drawing in MR that can be widely adopted in daily life.
Comments on "Decomposition of Complex Multipliers Using Polynomial Encoding"
Authors: R. Katti
Venue: IEEE Transactions on Computers (1994)

Presents a better way of decomposition of complex multipliers using polynomial encoding than the method presented in the paper, "Decomposition of Complex Multipliers Using Polynomial Encoding.". The decomposition described in this paper makes use of smaller multipliers which results in smaller ROMs if ROM table look-ups are used to implement multipliers.
Performance of Pruning-Cache Directories for Large-Scale Multiprocessors
Authors: S. L. Scott, J. R. Goodman
Venue: IEEE Transactions on Parallel and Distributed Systems (1993)

Multis, shared-memory multiprocessors that are implemented with single buses andsnooping cache protocols are inherently limited to a small number of processors, and, assystems grow beyond a single bus, the bandwidth requirements of broadcast operationslimit scalability. Hardware support to provide cache coherence without the use ofbroadcast can become very expensive. An approach to maintaining coherence usingapproximate information held in special-purpose caches called pruning-caches thatprovides robust performance over a wide range of workloads is presented. Thepruning-cache approach is compared to the more conventional inclusion cache forproviding multilevel inclusion (MLI) in the cache hierarchy. It is shown thatpruning-caches are more cost-effective and more robust. Using both analysis andsimulation, it is also shown that the k-ary n-cube topology provides scalable,bottleneck-free communication for uniform, point-to-point traffic.
A Large-Area Integrated Multiprocessor System for Video Applications
Authors: Markus Rudack, Michael Redeker, Jörg Hilgenstock, Sören Moch, Jens Castagne
Venue: IEEE Design Test (2002)

This 16.89-cm2 multiprocessor system performs coding of high-resolution video streams in real time. Redundancy and self-reconfiguration techniques ensure high reliability with a suitable yield.
Using Compiled Knowledge to Guide and Focus Abductive Diagnosis
Authors: Luca Console, Luigi Portinale, Daniele Theseider Dupré
Venue: IEEE Transactions on Knowledge and Data Engineering (1996)

Several artificial intelligence architectures and systems based on "deep" models of a domain have been proposed, in particular for the diagnostic task. These systems have several advantages over traditional knowledge based systems, but they have a main limitation in their computational complexity. One of the ways to face this problem is to rely on a knowledge compilation phase, which produces knowledge that can be used more effectively with respect to the original one.In this paper we show how a specific knowledge compilation approach can focus reasoning in abductive diagnosis, and, in particular, can improve the performances of AID, an abductive diagnosis system. The approach aims at focusing the overall diagnostic cycle in two interdependent ways: avoiding the generation of candidate solutions to be discarded a posteriori and integrating the generation of candidate solutions with discrimination among different candidates. Knowledge compilation is used off-line to produce operational (i.e., easily evaluated) conditions that embed the abductive reasoning strategy and are used in addition to the original model, with the goal of ruling out parts of the search space or focusing on parts of it. The conditions are useful to solve most cases using less time for computing the same solutions, yet preserving all the power of the model-based system for dealing with multiple faults and explaining the solutions. Experimental results showing the advantages of the approach are presented.
Collateral ASIC Test
Authors: Al Bailey, Tim Lada, Jim Preston
Venue: IEEE Design Test (1997)

ASIC (Application-Specific Integrated Circuit) testability, troubleshooting access and visibility of internal circuitry are the primary targets of test engineering analysis. The widely applied boundary-scan technique does not solve all problems connected with the PBA (Printed Board Assembly) manufacturing process. This paper presents an extension of the boundary-scan technique currently implemented to provide ASIC testability. The concept of Collateral ASIC Test (method and logic) implemented in a boundary-scan device is described as well as the test process standardization implied by this new approach to ASIC design and testing.
Optimal Hot Spot Allocation on Meshes for Large-Scale Data-Parallel Algorithms
Authors: Soo-Young Lee, Chung-Ming Chen
Venue: IEEE Transactions on Parallel and Distributed Systems (1995)

Hot spots are notorious for degrading the performance of a parallel algorithm. In this paper, we attempt to minimize the hot-spot access time for a class of problems, namely, Large-Scale Data-Parallel (LSDP) algorithms, on a 2D mesh. An LSDP algorithm has rich data parallelism but without exclusive task and data partitioning. Our approach is to allocate the hot spots at the optimal locations such that the hot-spot access time is minimized. Also, we have designed scheduling algorithms which control hot spot access sequences to achieve the minimal access time. Both uniform and nonuniform hot spots have been considered in this study. We have analytically derived the optimal allocations for wrapped-around and non-wrapped-around square meshes. The theoretical results have been verified by parallelizing the EM algorithm for 3D PET image reconstruction on the Intel iPSC/860.
How Quality Fits Into Package Development
Venue: IEEE Software (1993)

The software-package segment of the software market most closely resembles the manufacturing-for-consumption model on which most quality techniques are based. The author reports on observations of the development processes in 15 package companies, specifically how these developers view quality-assurance practices and what they have in place.
ASP: A Cost-Effective Parallel Microcomputer
Authors: R. M. Lea
Venue: IEEE Micro (1988)

The author presents ASP architecture, which offers cost-effective support of a wide range of numerical and nonnumerical computing applications, using state-of-the-art microelectronic technology to achieve processor packing densities that are more usually associated with memory components, ASP is designed to benefit from the inevitable VLSI-to-ULSI-to-WSI (very large, ultra large, and wafer-scale integration) technological trend, with a fully integrated, simply scalable, and defect/fault-tolerant processor interconnection strategy. The author discusses the architectural philosophy, structural organization, operational principles, and VLSI/ULSI/WSI implementation of ASP and indicates its cost-performance potential. ASP microcomputers have the potential to achieve cost-performance targets in the range of 100 to 1000 MOPS (million operations per second) per $1000. This gives ASPs an advantage of two to three orders of magnitude over current parallel computer architectures.
Embedded Tools for a Configurable and Customizable DSP Architecture
Authors: Clifford Liem, Francois Breant, Sarveta Jadhav, Ray O'Farrell, Ray Ryan, Oz Levia
Venue: IEEE Design Test (2002)

This embedded tool suite lets users make architectural changes to a programmable DSP core on three levels and supports designer-defined instructions and computation units. The entire system is based on configurability through a file-based resource description that drives all the design tools.
Nanometer patterning of epitaxial CoSi2 on Silicon-on-insulator substrates
Authors: Q. T. Zhao, P. Kluth, S. Winnerl, S. Lenk, S. Mantl
Venue: Microelectronic Engineering (2002)

Nanometer patterning of thin single crystalline CoSi2 layers on silicon-on-insulator (SOI) by local oxidation was studied. A nitride mask on top of the silicide layer was patterned by optical lithography to create the local stress. During the subsequent oxidation or oxynitridation, the silicide layer is separated at the edges of the nitride mask, where the stress is largest. The nanopatterning of the CoSi2 layers was investigated under different oxidation ambients, and with different mask thicknesses. A feature size as small as 45 nm was obtained for 24 nm epitaxial CoSi2 layers on SOI by this nanopatterning technique.
Experience in Testing the Motif Interface
Authors: Jason Su, Paul R. Ritter
Venue: IEEE Software (1991)

The testing and quality assurance of the Motif 1.0 graphical user-interface software are described. The testing goals, which fell into three general categories (code coverage, defect-density, and defect-arrival rate), and a deliverable formal test suite are examined. The three phases of the testing process-evaluation, test development, and regression testing-and the tools used in testing are discussed.
An RNS Montgomery Modular Multiplication Algorithm
Authors: Jean-Claude Bajard, Laurent-Stéphane Didier, Peter Kornerup
Venue: IEEE Transactions on Computers (1998)

We present a new RNS modular multiplication for very large operands. The algorithm is based on Montgomery's method adapted to mixed radix, and is performed using a Residue Number System. By choosing the moduli of the RNS system reasonably large and implementing the system on a ring of fairly simple processors, an effect corresponding to a redundant high-radix implementation is achieved. The algorithm can be implemented to run in ${\cal O}(n)$ time on ${\cal O}(n)$ processors, where n is the number of moduli in the RNS system, and the unit of time is a simple residue operation, possibly by table look-up. Two different implementations are proposed, one based on processors attached to a broadcast bus, another on an oriented ring structure.