ppxscal/embedding_network huggingface dataset:
BMMC Permutations on a DECmpp 12000/sx 2000
Authors: Kristin Bruhl
Venue:  (1994)

Increasingly, modern computing problems, including many scientific and business applications, require huge amounts of data to be examined, modified, and stored. Parallel computers can be used to decrease the time needed to operate on such large data sets, by allowing computations to be performed on many pieces of data at once. For example, on the DECmpp machine used in our research, there are 2048 processors in the parallel processor array. The DECmpp can read data into each of these processors, perform a computation in parallel on all of it, and write the data out again, theoretically decreasing the execution time by a factor of 2048 over the time required by one of its processors. Often, the computations that occur after the data is in the processors involve rearranging, or permuting, the data within the array of parallel processors. Information moves between processors by means of a network connecting them. Communication through the network can be very expensive, especially if there are many collisions--simultaneous contentions for the same network resource--between items of data moving from one processor to another. When a program performs hundreds or even thousands of these permutations during its execution, a bottleneck can occur, impeding the overall performance of the program. Effective algorithms that decrease the time required to permute the data within a parallel computer can yield a significant speed increase in running programs with large data sets. Cormen has designed algorithms to improve performance when the data movement is defined by certain classes of permutations. This thesis will examine the performance of one of these classes, the bit-matrix-multiply/complement (BMMC) permutation, when implemented on the DECmpp. Although Cormen''s algorithm was designed for parallel disk systems, this thesis adapts it to permutations of data residing in the memory of the parallel processors. The DECmpp network follows the model of an Extended Delta Network (EDN). One characteristic of an EDN is that it has a set of input and output ports to the network, each of which can carry only one item of data at a time. If more than one item needs to travel over a given port, a collision occurs. The data must access the port serially, which slows down the entire operation. Cormen''s algorithm reduces these collisions by computing a schedule for sending the data over the network. For small data sets, it is not worthwhile to perform the extra operations to generate such a schedule, because the overhead associated with computing the schedule outweighs the time gained by preventing collisions at the network ports. As the size of the data set increases, eliminating collisions becomes more and more valuable. On the DECmpp, when the data permutation involves more than 128 elements per processor, our algorithm beats the more naive and obvious method for permuting in the parallel processor array.
Power Supply Noise Suppression via Clock Skew Scheduling
Authors: Chengkok Koh
Venue: Proceedings of the 3rd International Symposium on Quality Electronic Design (2002)

Simultaneous switching events in the clock lines and the signals passing through sequential and combinational logic elements cause large L di/dt and IR voltage variations in the power and ground network. This is known as power supply noise and it affects the performance and reliability of the entire circuit. In this paper, we propose an algorithm that performs clock skew scheduling to minimize the number of simultaneous switching events such that the power supply noise is suppressed. Our approach establishes a direct relationship between current (drawn by a circuit element, sequential or combinational) and skew by the concept of envelope waveforms, using a graphical representation. We provide a graph-based scheduling approach to reduce the peak current and to minimize the difference between the current peaks and valleys so that the current profile of the entire circuit is smoothened. Our approach also guarantees that the resulting clock schedule does not violate setup and hold time constraints. Experimental results on benchmark circuits show an average reduction of 19.6% in the peak current, an average reduction of 38.7% in the current swing, and an average reduction of 47.4% in voltage variations in the power lines using our approach.
Storage-n Sides to Every Story
Venue: Queue (2003)

The term storage sparks a number of ideas in the minds of storage experts—more so than most other topics in the computing field. Any discussion about storage among people in the industry brings to mind the East Indian legend made famous by English poet John Godfrey Saxe about the blind men observing an elephant. As they all reach out and feel that part of the elephant closest to themselves, they all have a different “view.” Each is correct, and yet none fully so, because no one view can take in the whole picture.
Three-Dimensional Circuit Layouts
Authors: Thompson F Leighton, L A Rosenberg
Venue:  (1985)

Recent advances in fabrication technology have rendered imminent the fabrication of multilayer (i.e., three-dimensional) chips, wafers, and packages. In this paper, we examine the savings in material (as measured by Area in a two-dimensional medium and Volume in a three-dimensional one) and in communication time (as measured by the length of the longest uninterrupted run of wire) afforded by this developing technology. We derive close upper and lower bounds on the efficiency with which circuits can be realized in a multilayer medium, based on the sizes of the smallest {\em bifurcators} of the circuit. We find that the smallest Volume of any three-dimensional layout of an $N$-device circuit is no more than (roughly) $(NA)^{1/2}$, where $A$ is the smallest Area of any two-dimensional layout of the circuit. We then refine our layout techniques so that we can deal with multilayer layouts having a fixed number of layers. We find that we can efficiently transform a two-dimensional layout of Area $A$ and Maximum Wire Run $R$ into a three-dimensional layout of Volume (roughly) $V~=~A/H$ and Maximum Wire Run $R^*~=~R/H$ for moderate numbers of layers $H$. Two noteworthy features of the study are: (1) that, within logarithmic factors, the indicated savings can be realized with layouts that use the third dimension only for interconnect; and (2) that the indicated savings can be realized algorithmically: we present polynomial-time algorithms that transform a given two-dimensional layout into a more efficient three-dimensional one.
?-Cubes: Recursive Bused Fat-Hypercubes for Multilevel Snoopy Caches
Authors: Masaru Takesue
Venue: Proceedings of the 1999 International Symposium on Parallel Architectures, Algorithms and Networks (1999)

This paper proposes a Psi-cube network that consists of low-height trees of buses desirable for the coherence directories of multilevel snoopy caches. Since the Psi-cube is organized based on a recurrence of the Hamming codes, it has recursive levels each of bused fat-hypercubes, named psi-cubes. A psi-cube is composed of the clusters that are produced by partitioning the nodes with multiple suits of codewords of a Hamming code. Thus every node is the representative node of a unique cluster, while its other nodes have addresses equal to single-bit or detectable double-bit error words of the node's address. The nodes are connected to a bus in the cluster, so that the Psi-cube configures trees of buses that has the height determined by the recurrence.
A Study on Data Allocation of On-Chip Dual Memory Banks
Authors: Jeonghun Cho, Jinhwan Kim, Yunheung Paek
Venue: Proceedings of the Sixth Annual Workshop on Interaction between Compilers and Computer Architectures (2002)

Efficient utilization of memory space is extremely important in embedded applications. Many DSP vendors provide a dual memory bank system that allows the applications to access two memory banks simultaneously. Unfortunately, we have found that existing vendor-provided compilers cannot generate highly efficient code for dual memory space because current compiler technology is unable to fully exploit this DSP hardware feature. Thus, software developers for an embedded processor have hard time developing software by hand in assembly to exploit the hardware feature efficiently. In this paper, we present a preliminary study of a memory allocation technique for dual memory space. Through there has been some work done for dual memory banks, efficient code was generated but it required so long compilation time. Although the compilation speed is relatively of less importance for embedded processors, it still should have a reasonable upper bound particularly for industry compilers due to ever increasing demands on faster time-to-market embedded software design and implementation. To achieve such reasonable compilation speed, we simplified the dual memory bank allocation problem by decoupling our code generation into five phases: register class allocation, code compaction, memory bank assignment, register assignment and memory offset assignment. The experimental results show that our generated codes perform as good as previous work, yet reducing the compilation time dramatically.
Clone Detection Using Abstract Syntax Trees
Authors: Ira D. Baxter, Andrew Yahin, Leonardo Moura, Marcelo Sant'Anna, Lorraine Bier
Venue: Proceedings of the International Conference on Software Maintenance (1998)

Existing research suggests that a considerable fraction (5-10%) of the source code of large-scale computer programs is duplicate code ("clones"). Detection and removal of such clones promises decreased software maintenance costs of possibly the same magnitude. Previous work was limited to detection of either near-misses differing only in single lexems, or near misses only between complete functions. This paper presents simple and practical methods for detecting exact and near miss clones over arbitrary program fragments in program source code by using abstract syntax trees. Previous work also did not suggest practical means for removing detected clones. Since our methods operate in terms of the program structure, clones could be removed by mechanical methods producing in-lined procedures or standard preprocessor macros.A tool using these techniques is applied to a C production software system of some 400K source lines, and the results confirm detected levels of duplication found by previous work. The tool produces macro bodies needed for clone removal, and macro invocations to replace the clones. The tool uses a variation of the well-known compiler method for detecting common sub-expressions. This method determines exact tree matches; a number of adjustments are needed to detect equivalent statement sequences, commutative operands, and nearly exact matches. We additionally suggest that clone detection could also be useful in producing more structured code, and in reverse engineering to discover domain concepts and their implementations.
Graph drawings with no k pairwise crossing edges
Authors: Pavel Valtr
Venue:  (1997)

A geometric graph is a graph $G=(V,E)$ drawn in the plane so that the vertex set $V$ consists of points in general position and the edge set $E$ consists of straight line segments between points of $V$. It is known that, for any fixed $k$, any geometric graph $G$ on $n$ vertices with no $k$ pairwise crossing edges contains at most $O(n log n)$ edges. In this paper we give a new, simpler proof of this bound, and show that the same bound holds also when the edges of $G$ are represented by $x$-monotone curves (Jordan arcs).
Stochastic Resonance Neural Network and Its Performance
Authors: Tatsuhiko Nobori, Nobuyuki Matsui
Venue: Proceedings of the IEEE-INNS-ENNS International Joint Conference on Neural Networks (IJCNN'00)-Volume 2 - Volume 2 (2000)

We describe the results of computer simulations of the dynamical behavior of a neural network model based on BP learning incorporated with stochastic resonance (SR Neural Network). This model is effective in solving the XOR problem, as reported in our previous work. This network is a small-scale network for practical engineering. In this study, therefore we apply four bits parity problem and investigate learning abilities in the enhanced network to establish our SR method. From the results of experiments, we see the learning abilities of our network are improve more than the limited abilities of the traditional BP learning network. We also observe the stochastic resonance in our network.
The Lambda Loop Transformation Toolkit (User''s Reference Manual)
Authors: Wei Li, Keshav Pingali
Venue:  (1994)

Loop transformations are becoming critical to exploiting parallelism and data locality in parallelizing and optimizing compilers. This document describes the Lambda loop transformation toolkit, an implementation of the non-singular matrix transformation theory, which can represent any linear one-to-one transformation. Lambda has a simple interface, and is independent of any compiler intermediate representation. It has been used in parallelizing compilers for multiprocessor machines as well as optimizing compilers for uniprocessor machines. Keywords: Parallel programming, parallelizing compilers, loop transformations, linear transformations, nonsingular transformations.
The Impact of Smart Disks and Spatial Reuse Property on RAID-5 Storage Systems
Authors: H. Jayaram, Eric Torng, Yong Chen, Stephen Wagner, Lionel M. Ni, Paul Hodges
Venue: Proceedings of the 1998 International Conference on Parallel Processing Workshops (1998)

RAID storage systems using SCSI and traditional diskdrives cannot meet the growing demand of new I/O intensiveapplications. New technologies such as smart disksand SSA are being proposed to improve the performance,scalability, and reliability of RAID systems. The objectiveof this work is to investigate the impact of smart disks andSSA's spatial reuse property on the performance of RAID-5storage systems. In order to perform this work, we haveenhanced CMU's RAIDframe simulator so that it accuratelymodels the overhead of current SCSI and SSA protocols,and we have created smart disk models which includeon-drive XOR logic and on-drive caches. We observethat neither smart disks alone nor spatial reuseproperty alone has much impact on RAID system performance.However, if smart disks and spatial reuseproperty are properly used in combination, RAID-5 systemperformance and scalability can be further enhanced.In particular, we propose a parity caching approach toimprove the performance of small writes.
More on restrictive blind issuing of secret-key certificates in parallel mode
Authors: Stefan A. Brands
Venue:  (1995)

A minimal variation is proposed of a recently described secret-key certificate scheme that is derived from the Schnorr signature scheme.The issuing protocol of the variation is conjectured to be restrictive blind in parallel mode, motivated by a recent argument of Schoenmakers.The variation demonstrates that the double use of a generator is not problematic in any way, contrary to the belief expressed by Schoenmakers. A more profound argument for the conjectured security in parallel mode is provided, and similar variations are described for secret-key certificates based on Brickell-McCurley signatures. To create some order in the variety of restrictive blind certificate schemes that have been proposed to date, their specific merits and limitations are categorized and discussed.
Achieving Fair Bandwidth Allocation without Per-Flow State
Authors: Mingyu Zhai, Guanqun Gu
Venue: Proceedings of the 2001 International Conference on Computer Networks and Mobile Computing (ICCNMC'01) (2001)

Many router mechanisms have been developed to achieve fair bandwidth allocations.Generally, most of these mechanisms need to maintain per-flow stat and therefore are morecomplex and less scalable than simple FIFO queuing when the are used in the interior of ahigh-speed network.Consequently, design of algorithms that can provide per-flow fair ratewithout requiring per-flow functionality in the network core routers had become an active area of research.In this paper, we present Queue Length based Fair Queueing (QLFQ), a scheme to approximate fair bandwidth allocation without per-flow state.Edge routers divide each flow into a set of layers using a linear encoding scheme and insert an appropriate label into each packet header.Core routers maintain a dropping threshold according to the current queue length at each router; packets with a label greater than the threshold are dropped.We have evaluated QLFQ together with CSFQ and RFQ with several different configurations and traffic sources.The simulation results show that QLFQ is able to achieve approximately fair bandwidth sharing in all these scenarios.The performance of QLFQ is comparable to that of CSFQ, and it performs much better than RFQ. The simulations also show that in an environment with bursty traffic sources, QLFQ provides much better fairness than CSFQ.
Energy Recovering ASIC Design
Authors: Conrad H. Ziesler, Joohee Kim, Marios C. Papaefthymiou
Venue: Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03) (2003)

Dissipation in the clock tree and state elements of ASIC designs is often a significant fraction of total energy consumption. We proposemethodology for recovering most of this energy by using a novel energyrecovering flip-flop and a novel single-phase resonant clock generator. As ourstate element has near-zero energy consumption when the input data is notswitching, it provides the savings of clock gating approaches without the additional complexity of implementing clock gating in the design. To complement this near-zero idle energy property of the flip-flop, our resonant clockgenerator includes the capability to decide, on a per-cycle basis, whether ornot the resonant clock needs to be replenished on the next cycle, thus automatically reducing energy consumption when most of the state elements areidling. ASICs designed with our methodology can achieve sub_C_V2\atopdd dissipationson the clock network at frequencies of 200-500MHz and operatingvoltages of 1.0-1.5V in a 0.25µm process. To evaluate our methodology, wesimulated a dual-mode (conventional and energy recovering) ASIC moduleto directly compare energy savings between the energy recovering and conventionalclocking schemes. Our simulations demonstrate savings of overa factor of 4 for the energy-recovering mode versus the conventional modefor low switching activities.
On the Concept of Qualitative Fuzzy Set
Authors: Helmut Thiele
Venue: Proceedings of the Twenty Ninth IEEE International Symposium on Multiple-Valued Logic (1999)

Following T. Y. Lin vague concepts such as "high" or "small" ("amount of money" as linguistic variable) should be described by classes of "equivalent" fuzzy sets on a fixed suitable universe U. Furthermore Lin proposed to generate such classes by factorization of the fuzzy power set of U with respect to a given equivalence relation on this power set. By three examples we show that this approach is not successful if we intend to shift algebraic operations with fuzzy sets to classes generated by equivalence relations. Using a Kripke-style semantics approach we can introduce a sensible concept of a qualitative fuzzy set and, furthermore, sensible algebraic operations with such sets. The concept of multi-fuzzy set introduced by Lin is a special case of our concept of context-depending fuzzy set.
Adaptive multicast routing in single rate loss networks
Authors: Ren-Hung Hwang
Venue: Proceedings of the Fourteenth Annual Joint Conference of the IEEE Computer and Communication Societies (Vol. 2)-Volume - Volume 2 (1995)

Propose a new approach, based on the maximum free circuit routing (MFCR) concept, toward multicast routing in single rate loss networks. Two versions of the multicast routing problems are studied: static and dynamic. In the static version of the multicast routing problem, the identities of all destination nodes are available to the multicast routing algorithm at once. Conversely, in the dynamic version of the multicast problem, the identities of the destination nodes are revealed to the routing algorithm one by one. The authors studied three MFCR-based multicast routing algorithms: one for the static multicast problem and two for the dynamic multicast problem. They also propose a new performance metric, referred to as fractional reward loss, for evaluating these three multicast routing algorithms. The performance of there three multicast routing algorithms are evaluated through simulations.
A Practical Approach for Zero' Downtime in an Operational Information System
Authors: Ada Gavrilovska, Karsten Schwan, Van Oleson
Venue: Proceedings of the 22 nd International Conference on Distributed Computing Systems (ICDCS'02) (2002)

An Operational Information System (OIS) supports a real-time view of an organization's information critical to its logistical business operations. A central component of an OIS is an engine that integrates data events captured from distributed, remote sources in order to derive meaningful real-time views of current operations. This Event Derivation Engine (EDE) continuously updates these views and also publishes them to a potentially large number of remote subscribers. The paper first describes a sample OIS and EDE in the context of an airline's operations. It then defines the performance and availability requirements to be met by this system, specifically focusing on the EDE component. One particular requirement for the EDE is that subscribers to its output events should not experience down-time due to EDE failures, crashes or increased processing loads. Toward this end, we develop and evaluate a practical technique for masking failures and for hiding the costs of recovery from EDE subscribers. This technique utilizes redundant EDEs that coordinate view replicas with a relaxed synchronous fault tolerance protocol. A combination of pre-and post-buffering of replicas is used to attain a solution that offers low response times (i.e., zero' downtime) whilealso preventing system failures in the presence of deterministic faults like ill-formed' messages. Parallelism realized via a cluster machine and application-specific techniques for reducing synchronization across replicas are used to scale a zero' downtime EDE to support the large number of subscribers it must service.
Converting call-by-reference to call-by-value: Fortran and Lisp coexisting
Authors: Richard J. Fateman, Raymond Toy
Venue: Proceedings of the 2003 international symposium on Symbolic and algebraic computation (2003)

Programs written in languages supporting call-by-reference continue to be of interest in functional programming circumstances where call-by-value is standard. In particular, if we can find a neat interface, by converting Fortran to Lisp we allow programmers to take advantage of an interactive functional symbolic system while running legacy numerical code. We show this can be done without unacceptable loss of efficiency. In building a combined symbolic-numeric environment such a conversion and combination may increase the synergy between the two approaches to scientific computing. This paper builds upon earlier reported work on f2cl.
Sams Teach Yourself Macromedia Fireworks MX in 24 Hours
Authors: Jackson West, Lon Coley
Venue:  (2002)

:In just 24 lessons of one hour or less, you will be up and running with Macromedia Fireworks MX. Using a straightforward, step-by-step approach, each lesson builds upon the previous one, allowing you to learn the essentials of Fireworks from the ground up.