ppxscal/embedding_network huggingface dataset:
Real-time primer design for DNA chips: Research Articles
Authors: H. Simmler, H. Singpiel, R. Männer
Venue: Concurrency and Computation: Practice Experience (2004)

The design of PCR or DNA chip experiments is a time-consuming process where bioinformatics is extensively used. The selection of the primers, which are immobilized on the DNA chip, requires a complex algorithm. Based on several parameters an optimized set of primers is automatically determined for a given gene sequence.This paper describes a parallel architecture which performs the optimization of the primer selection on a hardware accelerator. In contrast to the pure software approach, the parallel architecture gains a speedup of factor 500 using a PCI-based hardware accelerator. This approach allows an optimization of a specified primer set in real time. Copyright &copy; 2004 John Wiley & Sons, Ltd.
Robust knowledge discovery from parallel speech and text sources
Authors: F. Jelinek, W. Byrne, S. Khudanpur, B. Hladká, H. Ney, F. J. Och, J. Curǐn, J. Psutka
Venue: Proceedings of the first international conference on Human language technology research (2001)

As a by-product of the recent information explosion, the same basic facts are often available from multiple sources such as the Internet, television, radio and newspapers. We present here a project currently in its early stages that aims to take advantage of the redundancies in parallel sources to achieve robustness in automatic knowledge extraction.
Development of a compact two-sensor directional audio-capturing device
Authors: Koksoon Phua, Jianfeng Chen, Louis Shue, Hanwu Sun
Venue: Signal Processing (2005)

A directional audio-capturing device is highly desirable for normal communication in a noisy environment, and to enhance the quality of speech signal for the hearing impaired. In this paper, we propose a compact directional audio-capturing device which reduces the background noise in relation to speech signal which originates from a desired direction. This device contains three functional units: (1) a differential microphone formed by two omni-directional microphones connected in an endfire orientation, (2) adaptive beamforming and (3) echo shaping of the residual output signals to further improve the signal-to-noise ratio. The adaptation is based on a control scheme using the differences in the spatial responses between the omni-directional and the differential microphone signals. A post-processing scheme using echo-shaping filter is used to further suppress any residual interferences. A real-time implementation of our proposed scheme has been constructed and its performance measured. The experiments indicate a polar pattern with good interference cancellation, with an average interference suppression of as much as 22 dB. Our experiments also indicate lower speech distortion using our proposed system. In term of speech quality, the improvement is indicated by the mean-opinion-score (MOS) scale. The MOS has been obtained from both subjective tests conducted using ten listeners, as well as using the perceptual evaluation of speech quality tool indicated in ITU-T standards document.
On the computation of an arrangement of quadrics in 3D
Authors: Bernard Mourrain, Jean-Pierre Técourt, Monique Teillaud
Venue: Computational Geometry: Theory and Applications (2005)

In this paper, we study a sweeping algorithm for computing the arrangement of a set of quadrics in R3. We define a "trapezoidal" decomposition in the sweeping plane, and we study the evolution of this subdivision during the sweep. A key point of this algorithm is the manipulation of algebraic numbers. In this perspective, we put a large emphasis on the use of algebraic tools, needed to compute the arrangement, including Sturm sequences and Rational Univariate Representation of the roots of a multivariate polynomial system.
Activity-based justification of IT investments
Authors: Eileen Peacock, Mohan Tanniru
Venue: Information and Management (2005)

Ever since investments in IT moved from operational to decision support, academics and practitioners have been looking for ways to justify the costs. Traditional approaches, such as NPV, have been shown inadequate in capturing qualitative and quantitative benefits, and techniques developed to address the issue have proved limited in their ability to link investment justification with impact assessment. Recent literature has called for the use of business processes to assess the impact of IT and the same processes can be used to justify investments in IT. The activity-based costing (ABC) approaches in the field of accounting were developed to relate investments to product profitability by allocating the burden to those that receive the most benefit. Thus, this paper uses the ABC approach to relate investments to activities, so that it can be used to justify IT investment. The paper provides a model to determine when the approach, referred to as activity-based justification, is most appropriate and its value is illustrated using a case study.
Face Recognition with Image Sets Using Manifold Density Divergence
Authors: Ognjen Arandjelovic, Gregory Shakhnarovich, John Fisher, Roberto Cipolla, Trevor Darrell
Venue: Proceedings of the 2005 IEEE Computer Society Conference on Computer Vision and Pattern Recognition (CVPR'05) - Volume 1 - Volume 01 (2005)

In many automatic face recognition applications, a set of a personýs face images is available rather than a single image. In this paper, we describe a novel method for face recognition using image sets. We propose a flexible, semi-parametric model for learning probability densitiesconfined to highly non-linear but intrinsically low-dimensional manifolds. The model leads to a statistical formulation of the recognition problem in terms of minimizing the divergence between densities estimated on these manifolds. The proposed method is evaluated on a large data set, acquired in realistic imaging conditions with severe illumination variation. Our algorithm is shown to match the best and outperform other state-of-the-art algorithms in the literature, achieving 94% recognition rate on average.
A general framework to understand parallel performance in heterogeneous clusters: analysis of a new adaptive parallel genetic algorithm
Authors: Victor E. Bazterra, Martin Cuma, Marta B. Ferraro, Julio C. Facelli
Venue: Journal of Parallel and Distributed Computing (2005)

This paper presents a general model to define, measure and predict the efficiency of applications running on heterogeneous parallel computer systems. Using this framework, it is possible to understand the influence that the heterogeneity of the hardware has on the efficiency of an algorithm. This methodology is used to compare an existing parallel genetic algorithm with a new adaptive parallel model. All the performance measurements were taken in a loosely coupled cluster of processors.
iCheck Series: iCheck Express Microsoft Word 2003, Student Edition, 1 edition
Venue:  (2005)

iCheck Express Word 2003 was written specifically for high school students. It is age-level and interest-level appropriate. Large, color "iCheck" screen shots let students know if they have successfully completed the lesson and can move forward to the next assignment. Step-by-step exercises provide easy-to-follow instructions. An Annotated Teacher’s Edition provides point of use instruction and helpful teaching strategies for all student skill levels. This book covers Microsoft Office Exam objectives for Word 2003 Specialist and Word 2003 Expert.
Optimization of the VT-control method for low-power ultra-thin double-gate SOI logic circuits
Authors: Davood Shahrjerdi, Bahman Hekmatshoar, Ali Khakifirooz, Ali Afzali-Kusha
Venue: Integration, the VLSI Journal (2005)

Application of the VT-control method is studied in ultra-thin double-gate (DG) SOI inverter, as the simplest building block of SOI logic circuits. Two control voltages, VCN and VCP, are applied to the back-gates of the n- and p-type transistors, respectively, to reduce the leakage current when the inverter is in the idle mode. Simulations with DESSIS disclose that both control voltages may be set at an optimum value for a given circuit activity, leading to the lowest possible gate power-delay product. Simulations have been performed for 10 nm gate-length technology at the end of the ITRS roadmap. These results indicate that the optimized VT-control method is a promising way for realizing low-power SOI logic circuits. Furthermore, the scalability of this technique is verified by extending the simulations to other generations of the ITRS roadmap.
3D Reconstruction by Fitting Low-Rank Matrices with Missing Data
Authors: Daniel Martinec, Tomas Pajdla
Venue: Proceedings of the 2005 IEEE Computer Society Conference on Computer Vision and Pattern Recognition (CVPR'05) - Volume 1 - Volume 01 (2005)

A technique for building consistent 3D reconstructions from many views based on fitting a low rank matrix to a matrix with missing data is presented. Rank-four submatrices of minimal, or slightly larger, size are sampled and spans of their columns are combined to constrain a basis of the fitted matrix. The error minimized is expressed in terms of the original subspaces which leads to a better resistance to noise compared to previous methods. More than 90% of the missing data can be handled while finding an acceptable solution efficiently. Applications to 3D reconstruction using both affine and perspective camera models are shown. For the perspective model, a new linear method based on logarithms of positive depths from cheirality is introduced to make the depths consistent with an overdetermined set of epipolar geometries. Results are shown for scenes and sequences of various types. Many images in open and closed sequences in narrow and wide base-line setups are reconstructed with reprojection errors around one pixel. It is shown that reconstructed cameras can be used to obtain dense reconstructions from epipolarly aligned images.
A Stochastic Approach to Estimating Earliest Start Times of Nodes for Scheduling DAGs on Heterogeneous Distributed Computing Systems
Authors: Ankur Kamthe, Soo-Young Lee
Venue: Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 1 - Volume 02 (2005)

Previously, DAG scheduling schemes used the mean (average) of computation or communication time in dealing with temporal heterogeneity. However, it is not optimal to consider only the means of computation and communication times in DAG scheduling on a temporally (and spatially) heterogeneous distributed computing system. In this paper, it is proposed that the second order moments of computation and communication times, such as the standard deviations, be taken into account in addition to their means, in scheduling "stochastic" DAGs. An effective scheduling approach which accurately estimates the earliest start time of each node and derives a schedule leading to a shorter average parallel execution time has been developed. Through an extensive computer simulation, it has been shown that a significant improvement (reduction) in the average parallel execution times of stochastic DAGs can be achieved by the proposed approach.
An Instruction-Level Distributed Processor for Symmetric-Key Cryptography
Authors: Adam J. Elbirt, Christof Paar
Venue: IEEE Transactions on Parallel and Distributed Systems (2005)

Efficient implementation of block ciphers is critical toward achieving both high security and high-speed processing. Numerous block ciphers have been proposed and implemented, using a wide and varied range of functional operations. Existing architectures such as microcontrollers do not provide this broad range of support. Therefore, we will present a hardware architecture that achieves efficient block cipher implementation while maintaining flexibility through reconfiguration. In an effort to achieve such a hardware architecture, a study of a wide range of block ciphers was undertaken to develop an understanding of the functional requirements of each algorithm. This study led to the development of COBRA, a reconfigurable architecture for the efficient implementation of block ciphers. A detailed discussion of the top-level architecture, interconnection scheme, and underlying elements of the architecture will be provided. System configuration and on-the-fly reconfiguration will be analyzed, and from this analysis, it will be demonstrated that the COBRA architecture satisfies the requirements for achieving efficient implementation of a wide range of block ciphers that meet the 622 Mbps ATM network encryption throughput requirement.
The Abstract Task Graph: a methodology for architecture-independent programming of networked sensor systems
Authors: Amol Bakshi, Viktor K. Prasanna, Jim Reich, Daniel Larner
Venue: Proceedings of the 2005 workshop on End-to-end, sense-and-respond systems, applications and services (2005)

The Abstract Task Graph (ATaG) is a data driven programming model for end-to-end application development on networked sensor systems. An ATaG program is a system-level, architecture-independent specification of the application functionality. The application is modeled as a set of abstract tasks that represent types of information processing functions in the system, and a set of abstract data items that represent types of information exchanged between abstract tasks. Input and output relationships between abstract tasks and data items are explicitly indicated as channels. Each abstract task is associated with user-provided code that implements the actual information processing functions in the system. Appropriate numbers and types of tasks can then be instantiated at compile-time or run-time to match the actual hardware and network configuration, with each node incorporating the user-provided code, automatically generated glue code, and a runtime engine that manages all coordination and communication in the network. This paper primarily deals with the key concepts of ATaG and the program syntax and semantics. The end-to-end application development methodology is discussed briefly.
DPE/PAC: decentralized process engine with product access control
Authors: Shih-Chien Chou, Wei-Chuan Hsu, Wei-Kuang Lo
Venue: Journal of Systems and Software (2005)

This paper proposes a process engine called DPE/PAC (decentralized process engine with product access control). It can be embedded in a PSEE (process-centered software engineering environment) to decentralize the PSEE. In a decentralized PSEE, every site can enact process programs and therefore the workload of the PSEE's sites is balanced (i.e., no site will become a bottleneck). Moreover, when a site is down, other sites can enact process programs. Therefore, a decentralized PSEE overcomes the following drawbacks of a traditional client/server PSEEs: (a) the server may become a bottleneck and (b) when the server is down, the entire process should be suspended. In addition to decentralizing PSEEs, DPE/PAC offers an additional function, which is ensuring secure product access (including the enforcement of separation-of-duty constraints). The function is essential for a software process that develops sensitive software systems.
A FPGA Haptics Controller
Authors: Marc Holbein, John S. Zelek
Venue: Proceedings of the First Joint Eurohaptics Conference and Symposium on Haptic Interfaces for Virtual Environment and Teleoperator Systems (2005)

Wearable haptics necessitates using low power, small, inexpensive tactors that are typically used as pager motors in cellular phones. One of their limitations is that it appears that control of their amplitude and frequency of operation is inherently linked. Existing haptics controllers have shortcomings such as limiting the electrical stimulation frequency to a single one or multiples of one, being confined to only a square wave, not being able to change the polarity and duty cycle on the fly to name a few. In order to explore and help define the electrical to mechanical mapping for electromagnetic (and other) tactors, a tighter controller is necessary. We report on such a controller that we developed based on FPGA (Field Programmable Gate Array) technology. The FPGA gate control program is hardware-based and is not limited by micro-controller event handling. The paper reports on our FPGA controller design and provides some examples of its use.
A research framework for analysing eBusiness models
Authors: Adamantia G. Pateli, George M. Giaglis
Venue: European Journal of Information Systems (2004)

As eBusiness is moving towards maturity, research interests shift to the investigation of opportunities for market exploitation of eBusiness technologies. As a result, the debate around business models naturally becomes more topical. However, while many researchers and practitioners are contemplating business models, there is an alarming lack of theoretical tools in the literature to structure and codify knowledge in the area. This paper draws on an extensive review of the literature to propose an analytic framework that decomposes the area of business models into eight research sub-domains. The proposed framework is then applied to organize and critically review existing research under each sub-domain as well as to define an agenda of future challenges on business model research. The framework can benefit future research by allowing researchers to better concentrate their efforts and place their contributions in an overall context, thus assisting in building a coherent body of knowledge in the challenging research domain of business models.
Unisys: MUC-3 test results and analysis
Authors: Carl Weir, Robin McEntire, Barry Silk, Tim Finin
Venue: Proceedings of the 3rd conference on Message understanding (1991)

The Unisys MUC-3 system is based on a three-tiered approach to text processing in which a novel and quite powerful <u>knowledge-based</u> form of information retrieval plays a central role. The main components of this approach are as follows:A Keyword-Based Information Retrieval Component.This component predicts the occurrence of types of events in texts based on the presence of key words and phrases.
Meta IDS Environments: An Event Message Anomaly Detection Approach
Authors: Jens Tolle, Marko Jahnke, Michael Bussmann, Sven Henkel
Venue: Proceedings of the Third IEEE International Workshop on Information Assurance (2005)

This paper presents an anomaly detection approach for application in Meta IDS environments, where locally generated event messages from several domains are centrally processed. The basicapproach has been successfully used for detection of abnormal traffic structures in computer networks. It creates directed graphs from address specifications contained within event messages and generates clusterings of the graphs. Large differences between subsequent clusterings indicate anomalies. This anomaly detection approach is part of an intrusion warning system (IWS) for dynamic coalition environments. It is designed to indicate suspisious actions and tendencies and to provide decision support on how to react on anomalies. Real-world data, mixed with data from a simulated internet worm, is used to analyze the system. The results prove the applicability of our approach.
Towards an intelligent multilingual keyboard system
Authors: Tanapong Potipiti, Virach Sornlertlamvanich, Kanokwut Thanadkran
Venue: Proceedings of the first international conference on Human language technology research (2001)

This paper proposes a practical approach employing n-gram models and error-correction rules for Thai key prediction and Thai-English language identification. The paper also proposes rule-reduction algorithm applying mutual information to reduce the error-correction rules. Our algorithm reported more than 99% accuracy in both language identification and key prediction.
Generic personality and emotion simulation for conversational agents: Research Articles
Authors: Arjan Egges, Sumedha Kshirsagar, Nadia Magnenat-Thalmann
Venue: Computer Animation and Virtual Worlds (2004)

This paper describes a generic model for personality, mood and emotion simulation for conversational virtual humans. We present a generic model for updating the parameters related to emotional behaviour, as well as a linear implementation of the generic update mechanisms. We explore how existing theories for appraisal can be integrated into the framework. Then we describe a prototype system that uses the described models in combination with a dialogue system and a talking head with synchronized speech and facial expressions. Copyright &copy; 2004 John Wiley & Sons, Ltd.
Spectral surface reconstruction from noisy point clouds
Authors: Ravikrishna Kolluri, Jonathan Richard Shewchuk, James F. O'Brien
Venue: Proceedings of the 2004 Eurographics/ACM SIGGRAPH symposium on Geometry processing (2004)

We introduce a noise-resistant algorithm for reconstructing a watertight surface from point cloud data. It forms a Delaunay tetrahedralization, then uses a variant of spectral graph partitioning to decide whether each tetrahedron is inside or outside the original object. The reconstructed surface triangulation is the set of triangular faces where inside and outside tetrahedra meet. Because the spectral partitioner makes local decisions based on a global view of the model, it can ignore outliers, patch holes and undersampled regions, and surmount ambiguity due to measurement errors. Our algorithm can optionally produce a manifold surface. We present empirical evidence that our implementation is substantially more robust than several closely related surface reconstruction programs.
Java(TM) Programming Language, The (4th Edition)
Authors: Ken Arnold, James Gosling, David Holmes
Venue:  (2005)

Direct from the creators of the Java™ programming language, the completely revised fourth edition of The Java™ Programming Language is an indispensable resource for novice and advanced programmers alike.Developers around the world have used previous editions to quickly gain a deep understanding of the Java programming language, its design goals, and how to use it most effectively in real-world development. Now, Ken Arnold, James Gosling, and David Holmes have updated this classic to reflect the major enhancements in Java™ 2 Standard Edition 5.0 (J2SE™ 5.0).The authors systematically cover most classes in Java's main packages, java.lang.*, java.util, and java.io, presenting in-depth explanations of why these classes work as they do, with informative examples. Several new chapters and major sections have been added, and every chapter has been updated to reflect today's best practices for building robust, efficient, and maintainable Java software.Key changes in this edition include New chapters on generics, enums, and annotations, the most powerful new language features introduced in J2SE 5.0 Changes to classes and methods throughout to reflect the addition of generics Major new sections on assertions and regular expressions Coverage of all the new language features, from autoboxing and variable argument methods to the enhanced for-loop and covariant return types Coverage of key new classes, such as Formatter and ScannerThe Java™ Programming Language, Fourth Edition, is the definitive tutorial introduction to the Java language and essential libraries and an indispensable reference for all programmers, including those with extensive experience. It brings together insights you can only get from the creators of Java: insights that will help you write software of exceptional quality.