ppxscal/embedding_network huggingface dataset:
User participation in decision support systems development: influencing system outcomes
Authors: Teresa Lynch, Shirley Gregor
Venue: European Journal of Information Systems (2004)

Despite the widely held view that systems are more likely to be successful if users are involved during systems development, there is uncertainty about the exact nature of the relationship between user participation and system outcomes. There has been considerable research activity in this area but findings are inconclusive. Comparatively little qualitative research has been reported. This paper reports an interpretive study that examined the development process for 38 decision support systems in the Australian agricultural sector. The relationship between user participation and system outcome was explored. The degree of user influence in the design process was found to be an important component of this relationship. Degree of user influence was a result of both the type and depth of user participation. Much previous research has focused on whether users were involved in development without detailed consideration of the degree of influence on design features resulting from this participation. The results from this study are significant in that they yield theoretical insights into the phenomenon of user participation and related system outcomes. In addition, the results have practical significance for practitioners developing decision support software.
Detection of Denial-of-Message Attacks on Sensor Network Broadcasts
Authors: Jonathan M. McCune, Elaine Shi, Adrian Perrig, Michael K. Reiter
Venue: Proceedings of the 2005 IEEE Symposium on Security and Privacy (2005)

So far, sensor network broadcast protocols assume a trustworthy environment. However, in safety and mission-critical sensor networks this assumption may not be valid and some sensor nodes might be adversarial. In these environments, malicious sensor nodes can deprive other nodes from receiving a broadcast message. We call this attack a Denial-of-Message Attack (DoM). In this paper, we model and analyze this attack, and present countermeasures. We present SIS, a Secure Implicit Sampling scheme that permits a broadcasting base station to probabilistically detect the failure of nodes to receive its broadcast, even if these failures result from an attacker motivated to induce these failures undetectably. SIS works by eliciting authenticated acknowledgments from a subset of nodes per broadcast, where the subset is unpredictable to the attacker and tunable so as to mitigate acknowledgment implosion on the base station. We use a game-theoretic approach to evaluate this scheme in the face of an optimal attacker that attempts to maximize the number of nodes it denies the broadcast while remaining undetected by the base station, and show that SIS significantly constrains such an attacker even in sensor networks exhibiting high intrinsic loss rates. We also discuss extensions that permit more targeted detection capabilities.
Energy-aware stage illumination
Authors: Friedrich Eisenbrand, Stefan Funke, Andreas Karrenbauer, Domagoj Matijevic
Venue: Proceedings of the twenty-first annual symposium on Computational geometry (2005)

Consider the following illumination problem: given a stage represented by a line segment L and a set of lightsources represented by a set of points S in the plane, assign powers to the lightsources such that every point on the stage receives a sufficient amount -- let's say one unit -- of light while minimizing the overall power consumption. By assuming that the amount of light arriving from a fixed lightsource decreases rapidly with the distance from the lightsource, this becomes an interesting optimization problem.We propose to reconsider the classical illumination problems as known from computational geometry literature (e.g. [12]) under this light attenuation model. This paper examines the simple problem introduced above and presents different solutions, based on convex optimization, discretization and linear programming, as well as a purely combinatorial approximation algorithm. Some experimental results are also provided.
Performance evaluation of the SX-6 vector architecture for scientific computations: Research Articles
Authors: Leonid Oliker, Andrew Canning, Jonathan Carter, John Shalf, David Skinner, Stéphane Ethier, Rupak Biswas, Jahed Djomehri, Rob Van der Wijngaart
Venue: Concurrency and Computation: Practice Experience (2005)

The growing gap between sustained and peak performance for scientific applications is a well-known problem in high-performance computing. The recent development of parallel vector systems offers the potential to reduce this gap for many computational science codes and deliver a substantial increase in computing capabilities. This paper examines the intranode performance of the NEC SX-6 vector processor, and compares it against the cache-based IBM Power3 and Power4 superscalar architectures, across a number of key scientific computing areas. First, we present the performance of a microbenchmark suite that examines many low-level machine characteristics. Next, we study the behavior of the NAS Parallel Benchmarks. Finally, we evaluate the performance of several scientific computing codes. Overall results demonstrate that the SX-6 achieves high performance on a large fraction of our application suite and often significantly outperforms the cache-based architectures. However, certain classes of applications are not easily amenable to vectorization and would require extensive algorithm and implementation reengineering to utilize the SX-6 effectively. Copyright &copy; 2005 John Wiley & Sons, Ltd.
Hierarchical Multiple Associative Mapping in Cache Memories
Authors: Hamid R. Zarandi, Seyed Ghassem Miremadi
Venue: Proceedings of the 12th IEEE International Conference and Workshops on Engineering of Computer-Based Systems (2005)

In this paper, a new cache placement scheme is proposed to achieve higher hit ratios with respect to the two conventional schemes namely set-associative and direct mapping. Similar to set-associative, in this scheme, cache space is divided into sets of different sizes. Hence, the length of tag fields associated to each set is also variable and depends on the partition it is in. The proposed mapping function has been simulated with some standard trace files and statistics are gathered and analyzed for different cache configurations. The results reveal that the proposed scheme exhibits a higher hit ratio compared to the two well-known mapping schemes, namely set-associative and direct mapping, using LRU replacement policy. Also, its area and power consumption is less than full-associative scheme.
Scheduling for heterogeneous processors in server systems
Authors: Soraya Ghiasi, Tom Keller, Freeman Rawson
Venue: Proceedings of the 2nd conference on Computing frontiers (2005)

Applications on today's high-end systems typically make varying load demands over time. A single application may have many different phases during its lifetime, and workload mixes show interleaved phases. Memory-intensive work or phases may exhibit performance saturation at frequencies below the maximum possible for the processors due to the disparity between processor and memory speeds. Performance saturation is a sign of over-provisioning and leads to energy-inefficient systems. Computers using heterogeneous processors, with the same ISA, but different implementation details, have been proposed as a way of reducing power while avoiding or limiting performance degradation. However, using heterogeneous processors effectively is complicated and requires intelligent schedulingThe research reported here explores the use of a heterogeneous system of processors with identical ISAs and implementation details, but with differing voltages and frequencies. The scheduler uses the execution characteristics of each application to predict its future processing needs and then schedule it to a processor which matches those needs if one is available. The predictions are used to minimize the performance loss to the system as a whole rather than that of a single application. The result limits system power while minimizing total performance loss. A prototype implementation on a Power4 four-processor system is presented. The prototype scheduler is validated using both synthetic and real-world benchmarks. The prototype shows reasonable predictor accuracy and significant power savings for memory-bound applications
Ravenscar-Java: a high-integrity profile for real-time Java: Research Articles
Authors: Jagun Kwon, Andy Wellings, Steve King
Venue: Concurrency and Computation: Practice Experience (2005)

For many, Java is the antithesis of a high-integrity programming language. Its combination of object-oriented programming features, its automatic garbage collection, and its poor support for real-time multi-threading are all seen as particular impediments. The Real-Time Specification for Java has introduced many new features that help in the real-time domain. However, the expressive power of these features means that very complex programming models can be created, necessitating complexity in the supporting real-time virtual machine. Consequently, Java, with the real-time extensions as they stand, seems too complex for confident use in high-integrity systems. This paper presents a Java profile for the development of software-intensive high-integrity real-time systems. This restricted programming model removes language features with high overheads and complex semantics, on which it is hard to perform timing and functional analyses. The profile fits within the J2ME framework and is consistent with well-known guidelines for high-integrity software development, such as those defined by the U.S. Nuclear Regulatory Commission. Copyright &copy; 2005 John Wiley & Sons, Ltd.
Dealing Cards in Poker Games
Authors: Philippe Golle
Venue: Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC'05) - Volume I - Volume 01 (2005)

This paper proposes a new protocol for shuffling and dealing cards, that is designed specifically for games of mental poker. Our protocol takes advantage of two features of poker games that are overlooked by generic card-shuffling protocols: 1) cards in poker games are dealt in rounds, with betting in-between, rather than all at once and 2) the total number of cards dealt in a game of poker is small (it depends on the number of players but is typically less than half the deck). With these observations in mind, we propose a protocol that spreads the computational cost of dealing cards more evenly across rounds. Compared to protocols that shuffle the whole deck upfront, our approach offers a dramatic decrease in latency and overall computational cost. Our protocol is fair, private and robust. It is ideally suited for resource-constrained devices such as PDAs.
I Am an Abstraction Layer
Authors: Edward Grossman
Venue: Queue (2005)

Im not going to "sully" Queue's special report on databases by attempting to talk about them myself. Doing so would be like a sportscaster giving color-commentary to a Dalai Lama sermon: embarrassing. And while I won't go so far as to call this issue of Queue spiritual, read Jim Gray's "A Call to Arms" and you'll see what I mean. And put your hip-waders on.
Animation of curve constrained drawings of planar graphs
Authors: Kim Hansen, Stephen Wismath
Venue: Proceedings of the twenty-first annual symposium on Computational geometry (2005)

We submit an animation of an algorithm for drawing an arbitrary planar graph with vertices located on a semi-circle and edges drawn as straight line segments with at most one bend per edge. The animation,produced in .avi format, is available at:www.cs.uleth.ca/~vpak/socg05 .
Toward Interoperable First Response
Authors: H. Gilbert Miller, Richard P. Granato
Venue: IT Professional (2005)

Wireless services that accommodate disparate federal, state, and local systems are key to acoordinated first response to US public-safety threats.
Dynamic Overlay of Scratchpad Memory for Energy Minimization
Authors: Manish Verma, Lars Wehmeyer, Peter Marwedel
Venue: Proceedings of the international conference on Hardware/Software Codesign and System Synthesis: 2004 (2004)

The memory subsystem accounts for a significant portion of the aggregate energy budget of contemporary embedded systems. Moreover, there exists a large potential for optimizing the energy consumption of the memory subsystem. Consequently, novel memories as well as novel algorithms for their efficient utilization are being designed. Scratchpads are known to perform better than caches in terms of power, performance, area and predictability. However, unlike caches they depend upon software allocation techniques for their utilization. In this paper, we present an allocation technique which analyzes the application and inserts instructions to dynamically copy both code segments and variables onto the scratchpad at runtime. We demonstrate that the problem of dynamically overlaying scratchpad is an extension of the Global Register Allocation problem. The overlay problem is solved optimally using ILP formulation techniques. Our approach improves upon the only previously known allocation technique for statically allocating both variables and code segments onto the scratchpad. Experiments report an average reduction of 34% and 18% in the energy consumption and the runtime of the applications, respectively. A minimal increase in code size is also reported.
How far are we from the definition of a common software performance ontology?
Authors: Vittorio Cortellessa
Venue: Proceedings of the 5th international workshop on Software and performance (2005)

The recent approaches to software performance modeling and validation share the idea of annotating software models with information related to performance (e.g. operational profile) and transforming the annotated model into a performance model (e.g. a Stochastic Petri Net). Up to date, no standard has been defined to represent the information related to performance in software artifacts, although clear advantages in tool interoperability and model transformations would stem from it. This paper is aimed at questioning whether a software performance ontology (i.e. a standard set of concepts and relations) is achievable or not. We consider three meta-models defined for software performance, that are the Schedulability, Performance and Time profile of UML, the Core Scenario Model and the Software Performance Engineering meta-model. We devise two approaches to the creation of an ontology: (i) bottom-up, that extracts common knowledge from the meta-models, (ii) top-down, that is driven from a set of requirements.
Using the KL-Center for Efficient and Accurate Retrieval of Distributions Arising from Texture Images
Authors: Eric Spellman, Baba C. Vemuri, Murali Rao
Venue: Proceedings of the 2005 IEEE Computer Society Conference on Computer Vision and Pattern Recognition (CVPR'05) - Volume 1 - Volume 01 (2005)

Image retrieval is a common problem in many computer vision applications and the literature abounds with techniques with impressive retrieval accuracies. Several of these techniques use probability distributions to represent the "objects" they intend to retrieve. We present a novel approach to search such collections of distributions efficiently. Like many standard data structures, our method uses an "average" to represent a large set (i.e., cluster) of objects, thus allowing the search to disregard an unpromising subset with only one comparison to its average. Our contribution lies in choosing the average: Inspired by information theory, we choose a representative that is optimally "close" in a minimax sense to all members of its set when measured using the Kullback-Liebler (KL) divergence. We present a texture retrieval system and test it on the CUReT database, measuring accuracy and efficiency. We find that using the KL-center yields speed ups of more than a factor of three over an exhaustive search while guarenteeing identical accuracy. The KL-center also out-performs other commonly used representatives such as the arithmetic mean. Although we present results only in texture retrieval, our approach will likely aid image and shape retrieval as well.
JASON: an open platform for discovering and hosting applications in ad hoc networks
Authors: Nicolas Le Sommer, Hervé Roussain
Venue: Proceedings of the 1st French-speaking conference on Mobility and ubiquity computing (2004)

This paper presents a platform called JASON, which allows owners of mobile devices to discover software applications that can be made available to them spontaneously by the other members of their network. It also permits them to announce the applications they wish to provide to the other people, and provides them with facilities to download remote applications and to run these applications locally in a secure environment.
System-on-Chip Validation Using UML and CWL
Authors: Qiang Zhu, Ryosuke Oishi, Takashi Hasegawa, Tsuneo Nakata
Venue: Proceedings of the international conference on Hardware/Software Codesign and System Synthesis: 2004 (2004)

In this paper, a novel method for high-level specification and validation of SoC designs using UML is proposed. UML is introduced as a formal model of specification for SoC design. The consistency and completeness of the specification is validated based on the formal UML model. The implementation is validated by a systematic derivation of test scenarios and specification based coverage metrics from the UML model. The method has been applied to the design of a new media-processing chip for mobile devices. The application of the method shows that it is not only effective for finding logical errors in the implementation, but also eliminates errors due to inconsistency and incompleteness of the specification.
Dynamic memory interval test vs. interprocedural pointer analysis in multimedia applications
Authors: Esther Salamí, Mateo Valero
Venue: ACM Transactions on Architecture and Code Optimization (TACO) (2005)

Techniques to detect aliasing between access patterns of array elements are quite effective for many numeric applications. However, although multimedia codes usually follow very regular memory access patterns, current commercial compilers remain unsuccessful in disambiguating them due mainly to complex pointer references. The Dynamic Memory Interval Test is a runtime memory disambiguation technique that takes advantage of the specific behavior of multimedia memory access patterns. It evaluates whether or not the full loop is disambiguated by analyzing the region domain of each load or store before each invocation of the loop.This paper provides a detailed evaluation of the approach, compares it against an advanced interprocedural pointer analysis framework, and analyzes the possibility of using both techniques at the same time. Both techniques achieve similar speedups separately (1.25X in average for a 8-issue width architecture). Furthermore, they can be used together to improve performance (reaching an average speed-up of 1.32X). Results also confirm that memory disambiguation is a key optimization to exploit the available parallelism in multimedia codes, especially for wide-issue architectures (1.50X average speed-up when scaling from 4- to 12-issue width in contrast to a low 1.10X for the baseline compiler).
A semantic and methodological essence of message sequence charts
Authors: Manfred Broy
Venue: Science of Computer Programming (2005)

Message sequence charts (MSCs) are a technique to describe patterns of interaction between the components of interactive distributed systems by specific interaction diagrams. MSCs have evolved in telecommunication applications, defined as a standard, and have become very popular in the design of software architectures and, generally, of distributed or object-oriented software systems. They are used frequently to describe scenarios of interactions illustrating instances of use cases. Nevertheless, both the semantics of MSCs as a technique of specification and their methodological and technical role in the development process have not been precisely and sufficiently clarified, so far. Also their formalization, although tackled by a number of papers, is not well focused with respect to their methodological usage.In this paper, we suggest a semantic model for MSCs in terms of logical propositions characterizing stream-processing functions. This formalization allows us to apply MSCs as an intuitively clear specification technique with a precisely defined meaning. The MSCs provide, in particular, specifications for the components of a system. Our approach is in contrast to other semantic models for MSCs suggested in the literature (see Ladkin, Leue, in: R. L. Tenney et al. (Eds.), Formal Description Techniques VI, North-Holland, 1994, pp. 301-316, and Formal Aspects of Computing 7 (1995) 473-509) where the meaning of MSCs is explained using state transition machines or traces. We define the meaning of MSCs in a more abstract way by a logical technique specifying the components of a system. By this approach MSCs are used for the decomposition of systems into components. Along these lines, we discuss the systematic application of MSCs in the software development process.
Fast and robust detection of crest lines on meshes
Authors: Shin Yoshizawa, Alexander Belyaev, Hans-Peter Seidel
Venue: Proceedings of the 2005 ACM symposium on Solid and physical modeling (2005)

We propose a fast and robust method for detecting crest lines on surfaces approximated by dense triangle meshes. The crest lines, salient surface features defined via first- and second-order curvature derivatives, are widely used for shape matching and interrogation purposes. Their practical extraction is difficult because it requires good estimation of high-order surface derivatives. Our approach to the crest line detection is based on estimating the curvature tensor and curvature derivatives via local polynomial fitting.Since the crest lines are not defined in the surface regions where the surface focal set (caustic) degenerates, we introduce a new thresholding scheme which exploits interesting relationships between curvature extrema, the so-called MVS functional of Moreton and Sequin, and Dupin cyclides,An application of the crest lines to adaptive mesh simplification is also considered.
On Construction of a Visualization Toolkit for MPI Parallel Programs in Cluster Environments
Authors: Kuan-Ching Li, Hsun-Chang Chang, Chao-Tung Yang, Liria Matsumoto Sato, Chung-Yuan Yang, Yin-Yi Wu, Mao-Yueh Pel, Hsiang-Kai Liao, Min-Chieh Hsieh, Chia-Wen Tsai
Venue: Proceedings of the 19th International Conference on Advanced Information Networking and Applications - Volume 2 (2005)

The low cost and wide availability of PC-based clusters have made them an excellent alternative to access supercomputing. However, while network of workstations may be readily available, there is an increasing need for performance tools that support these platforms, in order to achieve even higher performance. One of possible ways to increase performance is parallel program restructuring. It is introduced in this paper a toolkit to generate graphical charts for visualization of MPI parallel programs, reflecting to its execution over time, with the use of DP*Graph representation, parallel version of timing graph. In other words parallel programs are shown through charts its sequential codes, dependencies and communication structures in a particular cluster system platform. Still in this paper, it is discussed the implementation of this toolkit and present some experimental results obtained.