ppxscal/embedding_network huggingface dataset:
Analytic derivation of processor potential utilization in straight line, ring, square mesh, and hypercube networks
Authors: R. G. Born, J. R. Kenevan
Venue: ACM SIGMETRICS Performance Evaluation Review (1988)

In multicomputer architectures, in which processors communicate through message-passing, the overhead encountered because of the need to relay messages can significantly affect performance. Based upon some simplifying assumptions including the rate at which a processor generates messages being proportional to its current potential utilization, processor utilizations are analytically derived in matrix form for a bidirectional straight line and square mesh. In addition, closed form derivations are provided for a unidirectional ring and an n-dimensional hypercube. Finally, the theoretical results are found to be in close agreement with discrete-event simulations of the four architectures.
On hot-spot contention in interconnection networks
Authors: N. M. Patel, P. G. Harrison
Venue: ACM SIGMETRICS Performance Evaluation Review (1988)

A major component of a parallel machine is its interconnection network, which provides concurrent communication between the processing elements. It is common to use a multi-stage interconnection network (MIN) which is constructed using crossbar switches and introduces not only contention for destination addresses but also additional contention for internal switches. Both types of contention are increased when non-local communication across a MIN becomes concentrated on a certain destination address, for example when a frequently-accessed data structure is stored entirely in one element of a distributed memory. Such an address, often called a hot-spot, affects the blocking probability of paths to other destination addresses because of the shared internal switches. This paper describes an analytical model of hot-spot contention and quantifies its effect on the performance of a MIN with a circuit switching communication protocol. We obtain performance measures for a MIN in which partial paths are held during path building and one destination address is more frequently chosen by incoming traffic than other addresses.
Comments on 'Algorithmic State Machine Design and Automatic Theorem Proving: Dual Approaches to the Same Activity'
Authors: L. Vroomen, P. Zsombor-Murray, P. Baracos, R. Hudson
Venue: IEEE Transactions on Computers (1989)

Although the P-functions of the original paper are an aesthetically pleasing method for optimizing binary decision programs, existing procedures are probably more efficient. Current research applying Prolog to the automatic design of microprograms is outlined.
Optimization, approximation, and complexity classes
Authors: Christos Papadimitriou, Mihalis Yannakakis
Venue: Proceedings of the twentieth annual ACM symposium on Theory of computing (1988)

We define a natural variant of NP, MAX NP, and also a subclass called MAX SNP. These are classes of optimization problems, and in fact contain several natural, well-studied ones. We show that problems in these classes can be approximated with some bounded error. Furthermore, we show that a number of common optimization problems are complete under a kind of careful transformation (called L-reduction) that preserves approximability. It follows that such a complete problem has a polynomial-time approximation scheme iff the whole class does. These results may help explain the lack of progress on the approximability of a host of optimization problems.
The Combination of Evidence in the Transferable Belief Model
Authors: P. Smets
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1990)

A description of the transferable belief model, which is used to quantify degrees of belief based on belief functions, is given. The impact of open- and closed-world assumption on conditioning is discussed. The nature of the frame of discernment on which a degree of belief will be established is discussed. A set of axioms justifying Dempster's rule for the combination of belief functions induced by two distinct evidences is presented.
Randomized distributed shortest paths algorithms
Authors: B. Awerbuch
Venue: Proceedings of the twenty-first annual ACM symposium on Theory of computing (1989)

This paper is concerned with distributed algorithm for finding shortest paths in an asynchronous communication network. For the problem of Breadth First Search, the best previously known algorithms required either &THgr;(V) time, or &THgr; (E + V &middot; D) communication. We present new algorithm, which requires O(D1+&egr;) time, and O(E1+&egr;) messages, for any &egr; > 0. (Here, V is number of nodes, E is number of edges and D is the diameter.) This constitutes a major step towards achieving the lower bounds, which are &OHgr;(E) communication and &OHgr;(D) time. For the general (weighted) shortest paths problem, previously known shortest-paths algorithms required O(k &middot; V2) messages and O(V &middot; logk V) time. Our algorithm requires O(E1 + &egr; &middot; log W) messages and O (V1 + &egr; &middot; log W) time. Our results enable to improve significantly solutions for other basic network problems (e.g. leader election).
Optimization of stochastic systems via simulation
Authors: P. W. Glynn
Venue: Proceedings of the 21st conference on Winter simulation (1989)

In this paper, we discuss some research issues related to the general topic of optimizing a stochastic system via simulation. In particular, we devote extensive attention to finite-difference estimators of objective function gradients and present a number of new limit theorems. We also discuss a new family of orthogonal function approximations to the global behavior of the objective function. We show that if the objective function is sufficiently smooth, the convergence rate can be made arbitrarily close to n-1/2 in the number of observations required. The paper concludes with a brief discussion of how these ideas can be integrated into an optimization algorithm.
Recursive Moving Window DFT Algorithm
Authors: J. L. Aravena
Venue: IEEE Transactions on Computers (1990)

A recursive algorithm is presented for computing the discrete Fourier transform (DFT). The algorithm is developed for a moving-window-type processing. The computational structure is fully concurrent and allows a vectorized updating of the DFT. The total time required for the updating could be as low as that of only one multiplication and two additions, regardless of the number of points. A possible structure for executing the computations is developed, and possible enhancements are analyzed.
Fast interprocedual alias analysis
Authors: K. D. Cooper, K. Kennedy
Venue: Proceedings of the 16th ACM SIGPLAN-SIGACT symposium on Principles of programming languages (1989)

We present a new algorithm for computing interprocedural aliases due to passing parameters by reference. This algorithm runs in O(N2+NE) time and, when combined with algorithms for alias-free, flow-insensitive data-flow problems, yields algorithms for solution of the general flow-insensitive problems that also run in O(N2+NE) time.
Absolute Bounds on Set Intersection and Union Sizes from Distribution Information
Authors: Neil C. Rowe
Venue: IEEE Transactions on Software Engineering (1988)

A catalog of quick closed-form bounds on set intersection and union sizes is presented; they can be expressed as rules, and managed by a rule-based system architecture. These methods use a variety of statistics precomputed on the data, and exploit homomorphisms (onto mappings) of the data items onto distributions that can be more easily analyzed. The methods can be used anytime, but tend to work best when there are strong or complex correlations in the data. This circumstance is poorly handled by the standard independence-assumption and distributional-assumption estimates.
Measuring VAX 8800 performance with a histogram hardware monitor
Authors: D. W. Clark, P. J. Bannon, J. B. Keller
Venue: Proceedings of the 15th Annual International Symposium on Computer architecture (1988)

This paper reports the results of a study of VAX 8800 processor performance using a hardware monitor that collects histograms of the processor's micro-PC and memory bus status. The monitor keeps a count of all machine cycles executed at each micro-PC location, as well as counting all occurrences of each bus transaction. It can measure a running system without interfering with it, and this paper's results are based on measurements of live timesharing. Because the 8800 is a microcoded machine, a great deal of information can be gleaned from these data. The paper reports opcode and operand specifier frequencies, as well as the amount of time spent in instruction execution and various kinds of overhead, such as memory management and cache-wait stalls. The histogram method yields a very detailed picture of the amount of time an average VAX instruction spends in various activities on the 8800.
A transformational approach to the derivation of hardware algorithms from recurrence equations
Authors: N. Yoshida
Venue: Proceedings of the 1988 ACM/IEEE conference on Supercomputing (1988)

Hardware algorithms have a significant impact on the supercomputing of matrix computation and signal processing. In this paper, we propose a new approach to the derivation of hardware algorithms from recurrence equations, which is based on program transformation, and we also introduce a new representation for hardware algorithms, which we call Relational Representation. In our approach, we transform one relational program corresponding to a given recurrence equation (namely a specification) to another relational program corresponding to a hardware algorithm (namely an implementation). Based on the unfold/fold transformation method of logic programs, we have formalized several transformation tactics. We have succeeded in deriving several implementations of hardware algorithms, such as pipelines, orthogonal grids and trees, from their respective specifications in recurrence equations.
An investigation into statistical properties of partitioning and floorplanning problems
Authors: S. Sastry, J.-I. Pi
Venue: Proceedings of the 26th ACM/IEEE Design Automation Conference (1989)

In this paper we examine some statistical properties exhibited by combinatorial optimization problems. Although the paper focuses on two particular problems that arise in chip design, namely circuit partitioning and floorplanning, the results seem valid for a much larger set of such problems. For the partitioning problem, we examine the solutions generated by the well known Kernighan-Lin procedure [5,10] and solutions generated by random search. We find that in both cases, the Type 3 (Weibull) extreme-value distribution provides an excellent model for the distribution of local minima generated. The location parameter of the Weibull provides an estimate of the minimum cost. For the floorplanning problem, we construct a number of test problems, whose optimal value is known. As with the partitioning problem, we find that the Weibull distribution provides an excellent model for estimating the minimum cost.
A document layout system using automatic document architecture extraction
Authors: I. Iwai, M. Doi, K. Yamaguchi, M. Fukui, Y. Takebayashi
Venue: ACM SIGCHI Bulletin (1989)

A document layout system based on automatic extraction of document architecture including logical and reference structures has been developed for reducing users' effort in document preparation, and has been implemented in a practical Japanese word processor. The extracted document architecture is used for both automatic text formatting and layout of text, figures and tables. Automatic text element recognition is performed by morphological analysis using keywords. Through intra-line (one sentence) and inter-line (relations between sentences) analysis, logical and reference structures are obtained. The automatic layout system effectively lays out the document using the extracted document architecture and knowledge about the layout.
Computational Feasibility of Structured Matching
Authors: A. Goel, T. Bylander
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1989)

Structured matching is a task-specific technique for selecting one choice out of a small number of alternatives based on a given set of parameters. In structured matching, the knowledge and control for making a decision are integrated within a hierarchical structure. Each node in the hierarchy corresponds to a different aspect of the decision and contains knowledge for directly mapping the results of its children nodes (or selected parameters) into a choice on the subdecision. The root node selects the final choice for the decision. The authors formally characterize the task and strategy of structured matching and analyze its computational complexity. They believe that structured matching captures the essence of what makes a range of decision-making problems computationally feasible to solve.
Data-Driven Parallel Production Systems
Authors: Jean-Luc Gaudiot, Andrew Sohn
Venue: IEEE Transactions on Software Engineering (1990)

Much effort has been expended on developing special architectures dedicated to the efficient execution of production systems. While data-flow principles of execution offer the promise of high programmability for numerical computations, it is shown that the data-driven principles can also be applied to symbolic computations. In particular, a mapping of the RETE match algorithm along the line of production systems is considered. Bottlenecks of the RETE match algorithm in a multiprocessor environment are identified and possible solutions are suggested. The modifications to the actor set as well as the program graph design are shown for execution on the tagged data-flow computer. The results of a deterministic simulation of this multiprocessor architecture demonstrate that artificial intelligence production systems can be efficiently mapped on data-driven architectures.
Multiple operation memory structures
Authors: M. C. Ertem
Venue: ACM SIGMICRO Newsletter (1989)

This paper describes architectures based on a new memory structure. Memory systems which can perform multiple transfers are described and issues in processor architecture are considered. A general model for memory operations is given, and the classical single transfer memory structures are described. Based on the generalized model, new structures which allow multiple transfers to be performed as a single processor operation are developed. Some architectural considerations at the processor level to support these kinds of memory systems are then discussed. The advantages and disadvantages of these new structures as compared to conventional memories are also discussed and a preliminary performance evaluation is done. This discussion generally refers to the random access, physical, main memory in the system, although many of the results are applicable to other storage devices.
Evidence-Based Recognition of 3-D Objects
Authors: Anil K. Jain, Richard Hoffman
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1988)

An evidence-based recognition technique is defined that identifies 3-D objects by looking for their notable features. This technique makes use of an evidence rule base, which is a set of salient or evidence conditions with corresponding evidence weights for various objects in the database. A measure of similarity between the set of observed features and the set of evidence conditions for a given object in the database is used to determine the identity of an object in the scene or reject the object(s) in the scene as unknown. This procedure has polynomial time complexity and correctly identifies a variety of objects in both synthetic and real range images. A technique for automatically deriving the evidence rule base from training views of objects is shown to generate evidence conditions that successfully identify new views of those objects.
Data dependency graph bracing
Authors: V. H. Allan
Venue: Proceedings of the 21st annual workshop on Microprogramming and microarchitecture (1988)

The Sunburst compiler refined at Utah State University employs a powerful mechanism for management of data anti-dependencies in data dependency graphs, DDG's: the DDG Bracer. The term bracing1 is used to mean the fastening of two or more parts together. There are two major goals in bracing: 1) semantic correctness, and 2) creation of an optimal DDG. Bracing provides necessary joining of code fragments, produced by a divide and conquer code generation algorithm, while yielding multiple code sequences. Since no anti-dependency arcs are present, the input DDG's are said to be in normal form. Because anti-dependency arcs occur only when a resource must be reused, a DDG in normal form represents infinite resources. The output DDG is a merging of the two input DDG's such that data dependency arcs between the two DDG's are inserted and data anti-dependency arcs are added to sequentialize the use of common resources. Vegdahl [Veg82] was one of the first to recognize the importance of live track manipulation. A live track is an ordered pair: the first component is the microoperation node ( MO) in which a resource is born, and the second component is the set of nodes in which the resource dies.
Expected-Outcome: A General Model of Static Evaluation
Authors: B. Abramson
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1990)

The expected-outcome model, in which the proper evaluation of a game-tree node is the expected value of the game's outcome given random play from that node on, is proposed. Expected outcome is considered in its ideal form, where it is shown to be a powerful heuristic. The ability of a simple random sampler that estimates expected outcome to outduel a standard Othello evaluator is demonstrated. The sampler is combined with a linear regression procedure to produce efficient expected-outcome estimators. Overall, the expected-outcome model of two-player games is shown to be precise, accurate, easily estimable, efficiently calculable, and domain-independent.
Programming style authorship analysis
Authors: P. W. Oman, C. R. Cook
Venue: Proceedings of the 17th conference on ACM Annual Computer Science Conference (1989)

Detecting instances of software theft and plagiarism is a difficult problem. The statistical analysis of peculiar words or phrases known to be used by an author is a common method of settling authorship disputes in English literature. This paper presents a similar method for identifying authorship of programs. The method is based on typographic or layout style program characteristics. Our experiments show that these characteristics can be useful in determining authorship. The major benefits of the method are that it is simple, easy to automate, and can be used in conjunction with other program fingerprinting methodologies.
Business instrument panel: a new paradigm for interfacing with financial data
Authors: C. Torben Thomsen
Venue: Proceedings of the SIGCHI conference on Human factors in computing systems: Empowering people (1990)

The business instrument panel uses visualization to present, in a comprehensive and integrated manner, all the important elements found in traditional financial statements. By means of analog representation in a simple computer generated picture, the business instrument panel replaces the four traditional financial statements (balance sheet, income statement, cash flow statement, and retained earnings statement). The business instrument panel also embodies a new paradigm for understanding the business world and empowers the user with an unparalleled quick understanding of any firm.
Applications of computer-aided software engineering tools: survey of current and prospective users
Authors: Donald L. Burkhard, Per V. Jenster
Venue: ACM SIGMIS Database (1989)

Computer-Aided Software Engineering (CASE) tools are a relatively new technology that promises to have a significant impact on the way systems professionals develop and maintain information systems. This article reports on a study of the experience and expectations of current and prospective users of CASE tools. After an introductory discussion of CASE tools and their uses in an organizational context, the article presents the findings of a recent study of 46 organizations. The research focused on three major areas: expectations of CASE technology, reasons for acquiring CASE, and implementation issues. In conclusion, areas in need of further exploration are identified.
The results of simulating a digital imaging network system in Echelon 3 of deployable combat medical facilities
Authors: W. P. Johnson
Venue: Proceedings of the 21st conference on Winter simulation (1989)

The U.S. Army is evaluating the conversion of all of its conventional medical radiological imaging capabilities to a filmless technology using a Digital Imaging Network System (DINS) in both fixed and field hospitals. The latter hospitals are called Deployable Combat Medical Facilities. Using DINS, the photosensitive films presently used to record and display x-ray images would be replaced by digitized images stored on either magnetic or optical devices and displayed on computer workstations (electronic lightboxes). This document describes the use of a simulation model as a tool in estimating the imaging caseload for field hospitals for the purpose of determining the required image storage capacities of the DINS workstations and the required throughput capacity of the inter-workstation local area network. The simulation follows a patient through the five echelons of field hospitals, recording the number of radiological images created in each ward of a hospital and the inter-ward movement of images. The simulation also provides information about the number of images transferred with a patient being evacuated to rear area hospitals. The detail included in the simulation model makes it possible to analyze the utilization of facilities within a hospital and the impact of queuing on patient care when these facilities are overloaded. Three simulation examples are presented that examine the impact on an Echelon 3 EVAC Hospital of the treatment of patients with combat-related injuries.