ppxscal/embedding_network huggingface dataset:
Automatic Thread Extraction with Decoupled Software Pipelining
Authors: Guilherme Ottoni, Ram Rangan, Adam Stoler, David I. August
Venue: Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture (2005)

Until recently, a steadily rising clock rate and other uniprocessor microarchitectural improvements could be relied upon to consistently deliver increasing performance for a wide range of applications. Current difficulties in maintaining this trend have lead microprocessor manufacturers to add value by incorporating multiple processors on a chip. Unfortunately, since decades of compiler research have not succeeded in delivering automatic threading for prevalent code properties, this approach demonstrates no improvement for a large class of existing codes. To find useful work for chip multiprocessors, we propose an automatic approach to thread extraction, called Decoupled Software Pipelining (DSWP). DSWP exploits the finegrained pipeline parallelism lurking in most applications to extract long-running, concurrently executing threads. Use of the non-speculative and truly decoupled threads produced by DSWP can increase execution efficiency and provide significant latency tolerance, mitigating design complexity by reducing inter-core communication and per-core resource requirements. Using our initial fully automatic compiler implementation and a validated processor model, we prove the concept by demonstrating significant gains for dual-core chip multiprocessor models running a variety of codes. We then explore simple opportunities missed by our initial compiler implementation which suggest a promising future for this approach.
Generating Relational Database Transactions From Recursive Functions Defined on EB^3 Traces
Authors: Frederic Gervais, Marc Frappier, Regine Laleau
Venue: Proceedings of the Third IEEE International Conference on Software Engineering and Formal Methods (2005)

EB^3 is a trace-based formal language created for the specification of information systems (IS). Attributes, linked to entities and associations of an IS, are computed in EB^3 by recursive functions on the valid traces of the system. We aim at synthesizing relational database transactions that correspond to EB^3 attribute definitions. Each EB3 action is translated into a transaction. EB^3 attribute definitions are analysed to determine the key values affected by each action. Some key values are retrieved from SELECT statements that correspond to first-order predicates in EB^3 attribute definitions. To avoid problems with the sequencing of SQL statements in the transactions, temporary variables and/or tables are introduced for these key values. Generation of DELETE statements is straightforward, but distinguishing updates from insertions of tuples requires more analysis.
A Single Supply Level Shifter for Multi-Voltage Systems
Authors: Qadeer A. Khan, Sanjay K. Wadhwa, Kulbhushan Misri
Venue: Proceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (2006)

This paper presents design and application of a level shifter circuit which works with a single power supply. Unlike the conventional level shifter circuits, the proposed level shifter can shift any voltage level signal to a desired higher level without any leakage current. Use of single supply level shifter greatly reduces the supply routing and layout congestion within the chip when level shifting is required between different voltage domains. It also reduces pin count if level shifting is required between two or more chips operating at different supply voltages in a multi-voltage system. The proposed circuit is generic in nature and the voltage range at which level shifting can be done is limited by the technology only. The circuits was designed in 90nm CMOS technology and simulated in SPICE. The simulation results show that the proposed level shifter circuit is able to shift the input signal from 1.2V to 2.5V at maximum frequency of 500MHz.
Requirements Abstraction Model
Authors: Tony Gorschek, Claes Wohlin
Venue: Requirements Engineering (2005)

Software requirements arrive in different shapes and forms to development organizations. This is particularly the case in market-driven requirements engineering, where the requirements are on products rather than directed towards projects. This results in challenges related to making different requirements comparable. In particular, this situation was identified in a collaborative effort between academia and industry. A model, with four abstraction levels, was developed as a response to the industrial need. The model allows for placement of requirements on different levels and supports abstraction or break down of requirements to make them comparable to each other. The model was successfully validated in several steps at a company. The results from the industrial validation point to the usefulness of the model. The model will allow companies to ensure comparability between requirements, and hence it generates important input to activities such as prioritization and packaging of requirements before launching a development project.
A compiler infrastructure for compiling assembly and binary programs onto fpgas
Authors: Prithviraj Banerjee
Venue:  (2005)

The unprecedented growth of the Internet, broadband and wireless communications has created an insatiable market for the electronics industry. Increasing demand has provided opportunities for the growth of embedded software, operating systems and development tools. Hardware technology is also evolving faster than ever before. Software developers are under increased pressure to develop a large number of more complex embedded software projects in less time. Field-Programmable Gate Array (FPGA) architectures, with DSP support, provide a new hardware alternative for DSP designers, allowing them to attain greater levels of performance than on common DSP processors. Until now, the design process for this platform has been tedious. This research project aims to provide a framework for a new design methodology that automatically generates hardware designs for these platforms. It investigates the process and considerations for automatically translating software binaries into Register Transfer Level (RTL) VHDL or Verilog code. The techniques are based on compiler theory, behaviour synthesis, and graph theory. They represent novel algorithms and heuristics and have been implemented in a compiler, FREEDOM. The compiler has been used to illustrate the techniques and present performance results. The goal of this research has not been to compete with the best manual implementation of DSP algorithms on an FPGA, but to show that it is possible to seamlessly migrate legacy assembly code for a state-of-the-art DSP processor to hardware and still get 2&ndash;5X improvement in performance. Optimizations have been designed and implemented towards improving performance of the design. Non-profiling based procedure extraction techniques have been designed to extract procedure bodies from assembly code and generate a call graph. This call graph is utilized to partition the design. Most previous work on control and data flow analysis has assumed the presence of a single procedure. This is satisfactory for compilation proceeding from high-level languages. This assumption does not hold for the current decompilation task. Interval and control flow analysis techniques have been modified to handle the new conditions. A new semantic language has been designed. It is used in combination with a syntax description language to fully describe the syntax and semantics of processor Instruction Set Architectures. The descriptions generate a retargetable front-end for the compiler. It is powerful enough to handle CISC and VLIW architectures with parallel and predicated constructs. The compilation tool has allowed us to make some interesting observations and is greatly aiding in the exploration of avenues of further research.
Tree Structure forWord Extraction from Handwritten Text Lines
Authors: Tamas Varga, Horst Bunke
Venue: Proceedings of the Eighth International Conference on Document Analysis and Recognition (2005)

Word extraction from handwritten text lines usually involves the calculation of a line specific threshold which separates the gaps between words from the gaps inside the words in that line. We will show that this approach can be improved if the decision about a gap is not only made in terms of a threshold, but also depends on the context of that gap, i.e. if the relative sizes of the surrounding gaps are taken into consideration. For this purpose, we propose to build a structure tree of the text line, whose nodes represent possible word candidates. Such a tree is traversed in a top-down manner to find the nodes that correspond to words of the text line. Experiments with different gap metrics as well as threshold types show that the new method can yield significant improvements over conventional word extraction methods.
Deobfuscation: Reverse Engineering Obfuscated Code
Authors: Sharath K. Udupa, Saumya K. Debray, Matias Madou
Venue: Proceedings of the 12th Working Conference on Reverse Engineering (2005)

In recent years, code obfuscation has attracted attention as a low cost approach to improving software security by making it difficult for attackers to understand the inner workings of proprietary software systems. This paper examines techniques for automatic de-obfuscation of obfuscated programs, as a step towards reverse engineering such programs. Our results indicate that much of the effects of code obfuscation, designed to increase the difficulty of static analyses, can be defeated using simple combinations of straightforward static and dynamic analyses. Our results have applications to both software engineering and software security. In the context of software engineering, we show how dynamic analyses can be used to enhance reverse engineering, even for code that has been designed to be difficult to reverse engineer. For software security, our results serve as an attack model for code obfuscators, and can help with the development of obfuscation techniques that are more resilient to straightforward reverse engineering.
CLUMP: A Scalable and Robust Framework for Structure Discovery
Authors: Kunal Punera, Joydeep Ghosh
Venue: Proceedings of the Fifth IEEE International Conference on Data Mining (2005)

We introduce a robust and efficient framework called CLUMP (CLustering Using Multiple Prototypes) for unsupervised discovery of structure in data. CLUMP relies on finding multiple prototypes that summarize the data. Clustering the prototypes enables our algorithm to scale up to extremely large and high-dimensional domains such as text data. Other desirable properties include robustness to noise and parameter choices. In this paper, we describe the approach in detail, characterize its performance on a variety of datasets, and compare it to some existing model selection approaches.
Short-term MPEG-4 video traffic prediction using ANFIS
Authors: Adel Abdennour
Venue: International Journal of Network Management (2005)

Multimedia traffic and particularly MPEG-coded video streams are growing to be a major traffic component in high-speed networks. Accurate prediction of such traffic enhances the reliable operation and the quality of service of these networks through a more effective bandwidth allocation and better control strategies. However, MPEG video traffic is characterized by a periodic correlation structure, a highly complex bit rate distribution and very noisy streams. Therefore, it is considered an intractable problem. This paper presents a neuro-fuzzy short-term predictor for MPEG-4-coded videos. The predictor is based on the Adaptive Network Fuzzy Inference System (ANFIS) to perform single-step predictions for the I, P and B frames. Short-term predictions are also examined using smoothed signals of the video sequences. The ANFIS prediction results are evaluated using long entertainment and broadcast video sequences and compared to those obtained using a linear predictor. ANFIS is capable of providing accurate prediction and has the added advantage of being simple to design and to implement.
Cross-layer resource allocation algorithms in wireless networks with antenna arrays
Authors: Tianmin Ren
Venue:  (2005)

The application of antenna array is a promising approach to improving the capacity of a wireless network. In this dissertation, we study the application of antenna arrays at the base stations (BSs) in a wireless cellular network. We focus on the downlink transmission. This application requires the BSs be aware of the locations and channel conditions of the mobile users. Towards this end, we propose a family of MAC layer protocols that enable a base station to learn the locations and channel conditions of a number of intended users. Our simulation results demonstrate that the inter-cell interference significantly degrades the system performance of the previously proposed beamforming algorithms in terms of packet loss probability. (PLP) in a multi-cell environment. To cope with inter-cell interference, we propose beamforming algorithms that achieve target PLP in the presence of random inter-cell interference. The application of antenna array on the physical layer has great impact on the protocols of higher layers. Novel MAC algorithms and protocols need to be designed to take advantage of the capacity enhancement provided by antenna array on the physical layer. In this dissertation, the issue of designing a downlink scheduling policy with base station antenna arrays is studied. We derive an optimal scheduling policy that achieves the throughput region. Then, based on the structure of the derived optimal policy, we propose two heuristic scheduling algorithms. The interference experienced by each node in an ad-hoc network exhibits stochastic nature similar to the inter-cell interference in a cellular network. We propose a power control algorithm in a distributed scheme to achieve target PLP. Further more, the proposed power control algorithm is shown to minimize the aggregate transmission power given the PLP constraint. In the above problems, we mainly consider the non-real-time traffic where throughput is the QoS parameter of concern. On the other hand, delay is an important QoS parameter for real time traffic. In this dissertation, we also consider the scheduling of real time packets by a BS with awareness of physical layer channel conditions of different users.
E-business Software Architecture based on Temporal ECA Rules and Actions Conflicts Management
Authors: WAN Hai, Li Lei
Venue: Proceedings of the IEEE International Conference on e-Business Engineering (2005)

Since business logic is complex and changes frequently, e-business software architecture becomes more complex and difficult to maintain. From the perspective of software architecture design, this paper proposes a Temporal ECA based Architecture for e- Business systems (TECAB) representing business logic in the form of Temporal ECA, sketches a conflictmanaging mechanism based on Meta-action. The TECAB can separate business logic from business processing reasonably and support dynamic e-business logic effectively. TECAB has been applied to develop CRM system application, integrated with the conflictmanagement mechanism and storing TECA rule and action constraint with XML language.
A general framework for multi-resolution visualization
Authors: Matthew Ward, Elke Rundensteiner
Venue:  (2005)

Multi-resolution visualization (MRV) systems are widely used for handling large amounts of information. These systems look different but they share many common features. The visualization research community lacks a general framework that summarizes the common features among the wide variety of MRV systems in order to help in MRV system design, analysis, and enhancement. This dissertation proposes such a general framework. This framework is based on the definition that a MRV system is a visualization system that visually represents perceptions in different levels of detail and allows users to interactively navigate among the representations. The visual representations of a perception are called a view. The framework is composed of two essential components: view simulation and interactive visualization. View simulation means that an MRV system simulates views of non-existing perceptions through simplification on the data structure or the graphics generation process. This is needed when the perceptions provided to the MRV system are not at the user's desired level of detail. The framework identifies classes of view simulation approaches and describes them in terms of simplification operators and operands (spaces). The simplification operators are further divided into four categories, namely sampling operators, aggregation operators, approximation operators, and generalization operators. Techniques in these categories are listed and illustrated via examples. The simplification operands (spaces) are also further divided into categories, namely data space and visualization space. How different simplification operators are applied to these spaces is also illustrated using examples. Interactive visualization means that an MRV system visually presents the views to users and allows users to interactively navigate among different views or within one view. Three types of MRV interface, namely the zoomable interface, the overview + context interface, and the focus + detail interface, are presented with examples. Common interaction tools used in MRV systems, such as zooming and panning, selection, distortion, overlap reduction, previewing, and dynamic simplification are also presented. A large amount of existing MRV systems are used as examples in this dissertation, including several MRV systems developed by the author based on the general framework. In addition, a case study that analyzes and suggests possible improvements for an existing MRV system is described. These examples and the case study reveal that the framework covers the common features of a wide variety of existing MRV systems, and helps users analyze and improve existing MRV systems as well as design new MRV systems.
Examining the effects of caching, compression and popup filtering on internet surfing: Short Communications
Authors: Kevin Curran, Connor Duffy
Venue: International Journal of Communication Systems (2005)

Over the years the number of Web users has increased dramatically unfortunately leading to the inherent problem of congestion. This can affect each user's surfing experience. This paper investigates download times associated with a web request, identifies where delays occur, and provides guidelines which can be followed by web developers to enable a faster and more efficient download and service for their users. We conclude that delays in Internet traffic and congestion can often be attributed to poorly developed sites (e.g. excessive image size). Copyright &copy; 2005 John Wiley & Sons, Ltd.
Multipresence Narrowcasting Operations Comprise a Media Meta-Mixer Exponentiating Interface Value
Authors: Michael Cohen
Venue: Proceedings of the The Fifth International Conference on Computer and Information Technology (2005)

Multipresence allows each human user, in, for example, a distributed groupware system like the internet, to have source and sink presence in multiple spaces at once, by designating an arbitrary number of representatives as "self." Operations which filter information streams by blocking sources or sinks are useful for distributing and focusing attention and presence. Such "narrowcasting" operations can be modeled as an extended "media mixer": source operations apply to first-order mixing; sink operations apply to second-order mixing. The value of such an multipresent interface, articulated with narrowcasting operations, can be characterized as exponential in the number of users, the power set of the number of coteries. Audio windows are, in analogy to graphical windowing systems, an idiom for managing multiple duplex streams of information, as in a teleconference, chatspace, or virtual concert. We are developing audio windowing interfaces to groupware and VR-style applications, deployed on both workstations and mobile devices, and present a multipresenceenabled audio windows media mixer. Keywords: CVEs (collaborative virtual environments), distributed virtual environments, groupware, shared virtual worlds.
State of the art in Monte Carlo global illumination
Authors: Philip Dutré, Henrik Wann Jensen, Jim Arvo, Kavita Bala, Philippe Bekaert, Steve Marschner, Matt Pharr
Venue: ACM SIGGRAPH 2004 Course Notes (2004)

Realistic image synthesis is increasingly important in areas such as entertainment (movies, special effects and games), design, architecture and more. A common trend in all these areas is the quest for more realistic images of increasingly complex models. Monte Carlo global illumination algorithms are the only methods that can handle this complexity. Recent advances in algorithms and compute power has made Monte Carlo algorithms very practical and a natural choice for most problems.The purpose of this course is to impart upon the attendees a thorough understanding of the principles of Monte Carlo path tracing methods, as well as a detailed overview of the most recently developed methods.Part 1 will cover the fundamentals of realistic image synthesis (radiometry, rendering equation). Part 2 focuses on the mathematical tools needed to compute integrals using Monte Carlo sampling. Parts 3 and 4 cover specific algorithms that have proven very useful in global illumination rendering.
A Mechanism for Online Diagnosis of Hard Faults in Microprocessors
Authors: Fred A. Bower, Daniel J. Sorin, Sule Ozev
Venue: Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture (2005)

We develop a microprocessor design that tolerates hard faults, including fabrication defects and in-field faults, by leveraging existing microprocessor redundancy. To do this, we must: detect and correct errors, diagnose hard faults at the field deconfigurable unit (FDU) granularity, and deconfigure FDUs with hard faults. In our reliable microprocessor design, we use DIVA dynamic verification to detect and correct errors. Our new scheme for diagnosing hard faults tracks instructions¿ core structure occupancy from decode until commit. If a DIVA checker detects an error in an instruction, it increments a small saturating error counter for every FDU used by that instruction, including that DIVA checker. A hard fault in an FDU quickly leads to an above-threshold error counter for that FDU and thus diagnoses the fault. For deconfiguration, we use previously developed schemes for functional units and buffers, and we present a scheme for deconfiguring DIVA checkers. Experimental results show that our reliable microprocessor quickly and accurately diagnoses each hard fault that is injected and continues to function, albeit with somewhat degraded performance.