ppxscal/embedding_network huggingface dataset:
Two Barriers on Strong-Stability-Preserving Time Discretization Methods
Authors: Steven J. Ruuth, Raymond J. Spiteri
Venue: Journal of Scientific Computing (2002)

Strong-stability-preserving (SSP) time discretization methods are popular and effective algorithms for the simulation of hyperbolic conservation laws having discontinuous or shock-like solutions. They are (nonlinearly) stable with respect to general convex functionals including norms such as the total-variation norm and hence are often referred to as total-variation-diminishing (TVD) methods. For SSP Runge&ndash;Kutta (SSPRK) methods with positive coefficients, we present results that fundamentally restrict the achievable CFL coefficient for linear, constant-coefficient problems and the overall order of accuracy for general nonlinear problems. Specifically we show that the maximum CFL coefficient of an s-stage, order-p SSPRK method with positive coefficients is s&minus;p+1 for linear, constant-coefficient problems. We also show that it is not possible to have an s-stage SSPRK method with positive coefficients and order p>4 for general nonlinear problems.
Dynamic nuclear-spin polarization induced by scattering between fractional quantum hall edge channels
Authors: T. Machida, T. Yamazaki, S. Komiyama, K. Muraki, Y. Hirayama
Venue: Microelectronic Engineering (2002)

We find spin-dependent enhancement/suppression of scattering between fractional quantum Hall (FQH) edge channels (ECs), which originates from the hyperfine interaction between electron spins and nuclear spins. Nuclear magnetic resonance is detected via the FQH-EC transport, indicating the relevance of dynamic nuclear polarization (DNP). Spin polarizations of FQH ECs are inferred from the DNP.
DSS: A Distributed High-Level Synthesis System
Authors: Jayanta Roy, Nand Kumar, Rajiv Dutta, Ranga Vemuri
Venue: IEEE Design Test (1992)

DSS, a large-scale ongoing exercise in developing parallel algorithms for high-level synthesis and implementing them in an integrated distributed system to evaluate their individual and collective effectiveness, is discussed. Embedded in a very-high-speed integrated circuit hardware description language (VHDL) centered design environment, DSS consists of a collection of parallel algorithms executing on a multiple input, multiple data (MIMD) multiprocessor machine. The system uses coarse-grained parallelism to explore and evaluate many alternative VLSI designs efficiently. DSSs internal organization and its scheduling, register optimization, interconnection formation, and controller generation techniques are described. Results illustrating DSS performance with respect to design quality, and the efficiency of the DSS algorithms in a multiprocessor environment are presented.
Two Fuzzy Approaches for Solving Multiobjective Decision Problems
Authors: Teresa León, Vicente Liern, Enriqueta Vercher
Venue: Computational Economics (2002)

Zimmermann (1978) proposed a fuzzy method for solving multiple objective decision problems whose main difficulty is in specifying the membership functions of the objectives. We have considered two different approaches to construct those membership functions that give rise to two algorithms for solving linear multiobjective decision problems.
Automatic Synthesis of Communication Controller Hardware from Protocol Specifications
Authors: Robert Siegmund, Dietmar Müller
Venue: IEEE Design Test (2002)

Today's Digital Systems, particularly systems on chips, are communication-dominated designs. They contain many functionally complex modules that communicate with one another through high-performance data protocols. The latest methodologies for designing such systems usually start with an executable system behavior specification, which the designer uses for functional and performance simulations to validate the system concept. The designer then incrementally refines the specification to obtain a system implementation that meets given constraints, such as data-processing performance or maximum power dissipation, at the desired abstraction level-for example,the register-transfer level(RTL).At the system level, communication
Recognizing Kn&#x00F6;del graphs
Authors: Johanne Cohen, Pierre Fraigniaud, Cyril Gavoille
Venue: Discrete Mathematics (2002)

Knödel graphs form a class of bipartite incident-graph of circulant digraphs. This class has been extensively studied for the purpose of fast communications in networks, and it has deserved a lot of attention in this context. In this paper, we show that there exists an O(n log5 n)-time algorithm to recognize Knödel graphs of order 2n. The algorithm is based on a characterization of the cycles of length six in these graphs (bipartite incident-graphs of circulant digraphs always have cycles of length six). A consequence of our result is that the circulant digraphs whose chords are the power of two minus one can be recognized in O(n log5 n) time.
Automated software evolution towards design patterns
Authors: Mel Ó Cinnéide, Paddy Nixon
Venue: Proceedings of the 4th International Workshop on Principles of Software Evolution (2001)

During the evolution of a software system, it may be necessary to refactor the software in order to make it more flexible and amenable to new requirements that are being introduced. A typical aim of such a refactoring is to apply a suitable design pattern to the program in order to enhance its flexibility. Performing such a transformation by hand is an error-prone process, so automated support would be useful.We have developed a methodology for the creation of automated transformations that can apply a design pattern to an existing program. In this paper we present a brief description of this methodology, and report on the results of using this methodology to develop program transformations that can apply the Gamma et al design patterns. It is found that in almost 75% of cases a satisfactory transformation is developed, and that much of the commonality between design patterns can be captured in reusable minitransformations.
Stability Properties of Cerebellar Neural Networks: The Purkinje Cell &ndash; Climbing Fiber Dynamic Module
Authors: Witali L. Dunin-Barkowski, Serge L. Shishkin, Donald C. Wunsch
Venue: Neural Processing Letters (1999)

In the last few decades it has been proven, that the cerebellum takes part in learning the bulk of motor control. The mechanisms which provide such properties are still largely unknown, but an involvement of parallel fibers and climbing fibers in this process, as have been proposed decades ago in cerebellar learning theories, is now clear. Among difficulties of the learning theories is an evident necessity for spontaneous activity of the cerebellar climbing fibers [5]. Recently, the group of M. Mauk proposed an elegant explanation of this inconsistency [11, 12]. We present here a stochastic model of a cerebellar module, based on this new approach. Theoretical treatment yields some consequences for experimental verification. Besides an explanation of real cerebellar functions, the analyzed control system presents a new paradigm for neural network memorizing systems.
A Rapid-Prototyping Environment for Digital-Signal Processors
Authors: Richard Hartley, Kenneth Welles II, Michael Hartman, Abhjit Chatterjee, Paul Delano, Barbara Molnar, Colin Rafferty
Venue: IEEE Design Test (1991)

A description is given of the Diodes system, a complete rapid prototyping, debugging, and test environment including both hardware and software, for the design of digital-signal-processing chips. The test circuitry in Diodes differs from that in many systems, including those based on boundary scan, by offering full-speed circuit testing and the observation of internal nodes during real time. Diodes also achieves nearly 100% fault coverage because chips are composed of numerous chunks, each of which is tested exhaustively. The discussion covers the high-density interconnection technology and the concepts on which Diodes is based, two types of chips that have been designed, fabricated, and tested for Diodes: module assembly and fabrication; synthesis software; on-chip testing; Diodes test circuitry; test modes; and hardware and software debugging. Diodes is compared with other testing approaches and other rapid prototyping systems.
On-Chip Clock Faults' Detector
Authors: C. Metra, M. Favalli, S. Di Francescantonio, B. Riccò
Venue: Journal of Electronic Testing: Theory and Applications (2002)

This paper proposes an on-chip detector for the on-line testing of faults affecting clock signals and making them change with incorrect duty-cycle. Our scheme is particularly suitable to be integrated within Systems-On-a-Chip (SOCs), in order to avoid their possible incorrect operation because of faults affecting clock signals, thus solving their extreme criticality in clock faults' testing. In particular, our detector is suitable to be applied to clock signals within each SOC digital core, to the clock signals at the interface between the diverse cores, as well as to those driving the DFT and BIST structures used to perform the SOC test. Our scheme features self-checking ability with respect to its possible internal faults belonging to a realistic set including stuck-ats, transistor stuck-ons, stuck-opens and resistive bridgings.
Performance Analysis of the Communication Architecture of the Connection Machine
Authors: A. K. Ahluwalia, M. Singhal
Venue: IEEE Transactions on Parallel and Distributed Systems (1992)

The performance of the interprocessor communication architecture of the CM-2 isanalyzed. A discrete-time Markov chain model of its network architecture is developed tocompute the message delay introduced by the network architecture. Due to thesynchronous time-division multiplexing nature of the network operation, it is amenable toa discrete-time Markov chain modeling. The analysis yields formulas for response time and several other related performance measures, showing how the performance of thenetwork degrades with the message arrival rate and other parameters. Since thecommunication delays affect interprocess communication, knowledge of the sensitivity ofthe delays to the parameters can be a useful aid in designing a high performance parallelsystem. To keep the analysis tractable, an approximate Markov model is used thatrequires the use of fixed-point iteration for its solution. Validation of the results against asimulation study reveals that the analysis predicts the performance of the network withhigh accuracy.
Structural Fault Based Specification Reduction for Testing Analog Circuits
Authors: Soon-Jyh Chang, Chung Len Lee, Jwu E. Chen
Venue: Journal of Electronic Testing: Theory and Applications (2002)

Specification reduction can reduce test time, consequently, test cost. In this paper, a methodology to reduce specifications during specification testing for analog circuit is proposed and demonstrated. It starts with first deriving relationships between specifications and parameter variations of the circuit-under-test (CUT) and then reduces specifications by considering bounds of parameter variations. A statistical approach by taking into account of circuit fabrication process fluctuation is also employed and the result shows that the specification reduction depends on the testing confidence. A continuous-time state-variable benchmark filter circuit is applied with this methodology to demonstrate the effectiveness of the approach.
The Benchmarking Process: One Team's Experience
Authors: Sam Fogle, Carol Loulis, Bill Neuendorf
Venue: IEEE Software (2001)

Recently, the Software Productivity Consortium conducted a benchmarking study of process asset libraries. The report provided a significant set of ideas for organizations seeking to create new PALs or improve existing ones. Even the participants with the most "best practices" found gems among other participants' best practices for use in their continuous improvement efforts. This article discusses why we chose a benchmarking approach, the process we used in conducting this study, and key lessons we learned for future studies.
DOA Estimation using fast EM and SAGE Algorithms
Authors: Pei Jung Chung, Johann F. Böhme
Venue: Signal Processing (2002)

In this work we study direction of arrival estimation using expectation-maximization (EM) and space alternating generalized EM (SAGE) algorithms. The EM algorithm is a general and popular numerical method for finding maximum-likelihood estimates which is characterized by simple implementation and stable convergence. The SAGE algorithm, a generalized form of the EM algorithm, allows a more flexible optimization scheme and sometimes converges faster than the EM algorithm. Motivated by the componentwise convergence of the EM and SAGE algorithms, we suggest to use smaller search spaces after a few iterations. In this way, the overall computational costs can be reduced drastically. A procedure derived from the convergence properties of the EM and SAGE algorithms is proposed to determine the search spaces adaptively. By numerical experiments we demonstrate that the fast EM and the fast SAGE algorithms are computationally more efficient and have the same statistical performance as the original algorithms.
Collection and Analysis of Microprocessor Design Errors
Authors: David Van Campenhout, Trevor Mudge, John P. Hayes
Venue: IEEE Design Test (2000)

Research on practical design verification techniques has long been impeded by the lack of published, detailed error data. We have systematically collected design error data over the last few years from a number of academic microprocessor design projects. We analyzed this data and report on the lessons learned in the collection effort.
Mixed Signal DFT at GHz Frequencies
Authors: R. Mason, S. Ma
Venue: Journal of Electronic Testing: Theory and Applications (1999)

A high frequency analog IC testing technique using a periodic input stimuli and a sequential undersampling algorithm has been developed. This algorithm overcomes many of the loading problems associated with high speed analog signal testing. The utility of the undersampling technique was shown in previous work using a 1.2 &mu;m CMOS prototype IC. This paper expands that work by improving the performance of the original sampling circuits, investigating the possibility of generating control signals on-chip to reduce test cost, and developing a structured analog Design For Testability (DFT) approach. This approach can be used for high speed testing and is based upon undersampling techniques used in sampling oscilloscopes and mixed-signal testers.
An Optical Navigator for Brain Surgery
Authors: Ludwig Adams, Achim Knepper, Dietrich Meyer-Ebrecht, Rainer Rüger, Willem van der Brug
Venue: Computer (1996)

During the past few years, new surgical techniques have been developed to improve the quality of operations and reduce patient pain. Minimally invasive surgery, robot-assisted hip replacement, and image-guided treatment planning during the actual operation are key developments. Another new procedure, computer-assisted surgery (CAS), helps surgeons find their bearings during operations under difficult visual conditions. These include brain surgery and other head operations. CAS combines coordinate measurements of the operating instruments and superimposes their positions onto images of the operation area so that surgeons can follow instrument movements on a computer screen. Since 1986, the Institute for Measurement Techniques (Lehrstuhl für Meβtechnik) has been working closely with with the Aachen University Hospital to develop CAS systems. Based on this work, an industrial partner, Philips Medical Systems, has developed a commercial system for neurosurgery. This article provides an overview of the development process and an outlook on possible applications.
Benchmarking Mechanical Ventilation Services in Teaching Hospitals
Authors: Pamela V. O'neal, Yasar A. Ozcan, Yanqiang Ma
Venue: Journal of Medical Systems (2002)

The purpose of this investigation was to examine the technical efficiency of mechanical ventilation nonsurgery (DRG 475) among University Hospital Consortium (UHC) hospitals that consists of volunteer, teaching hospitals across the nation. The data for this study was retrieved from the 1997 UHC database that includes charge and discharge information for 69 hospitals. Data on 7961 patients classified with mechanical ventilation were aggregated to the hospital level. We retained data from a total of 62 hospitals, the other seven hospitals had missing data. The research questions were (1) Do UHC hospitals differ significantly in their efficiencies in the treatment of mechanically ventilated patients? (2) What inputs and outputs contribute most to the inefficiencies associated with mechanical ventilation? Of the 62 hospitals analyzed using data envelopment analysis technique, 10 were considered efficient and 52 were inefficient as compared to their benchmark peers. Efficient and inefficient hospitals did significantly differ between the transferred output variable and between the respiratory, laboratory, and radiology input variables. All inputs demonstrated excessive resource utilization among inefficient hospitals as compared to efficient hospitals. A total reduction of about &dollar;19 million dollars in ancillary services would need to occur for inefficient hospitals to approach the frontier of efficient hospitals. This study demonstrates that mechanical ventilation is costly, yet the specified ancillary services are capable of being reduced yielding technical efficiency as demonstrated by 10 efficient hospitals.
Trends in Mobile Satellite Technology
Authors: Gary Comparetto, Rafols Ramirez
Venue: Computer (1997)

Demand for sophisticated personal communication services has changed communications satellite design. Satellites have moved closer to the Earth to improve communication speed and enable personal communication services. But in so doing, they require more computing resources and more sophisticated protocols to handle intersatellite communications. Satellites have been used for decades, for weather forecasting, navigation, reconnaissance, and communications, among other things. Until recently, however, constraints on power, weight, and volume have made a spacecraft's computing resources so minimal that little emphasis has been placed on satellite communications and networking techniques. Now, however, this kind of support is in demand for use in today's sophisticated personal communication services. Increased demand for these services, coupled with advances in technology, has changed approaches to satellite design. The mindset of satellite systems designers over the past 30 years has been to keep complexity on the ground. Among other reasons, this minimizes catastrophic system failures should something happen to the satellite. Today, however, economies of scale have made possible the deployment of larger satellite constellations that can tolerate the failure of one or more satellites. Satellite orbits have also moved closer to the Earth, improving communication speed and enabling PCS services. But in moving to lower orbits, these next-generation systems have increased on-board complexity as satellites must now perform multiple satellite handovers to provide continuous coverage of the Earth. Thus, increased amounts of on-board computing resources and more sophisticated communication protocols must address the resulting increase in complexity. This article examines the trends in communications satellite deployment and the resulting requirements for network protocols that are intended to support space communications. We report the findings of a joint DoD/NASA effort to identify what parts of the seven-layer OSI protocol model can be adapted to support more sophisticated space applications; a global standard based on these findings is now under development.
Superconsistent Discretizations
Authors: Daniele Funaro
Venue: Journal of Scientific Computing (2002)

We say that the approximation of a linear operator is superconsistent when the exact and the discrete operators coincide on a functional space whose dimension is bigger than the number of degrees of freedom needed in the construction of the discretization. By providing several examples, we show how to build up superconsistent schemes. Many open questions will be also rised and partially discussed.
The small model property: how small can it be?
Authors: Amir Pnueli, Yoav Rodeh, Ofer Strichmann, Michael Siegel
Venue: Information and Computation (2002)

Efficient decision procedures for equality logic (quantifier-free predicate calculus + the equality sign) are of major importance when proving logical equivalence between systems. We introduce an efficient decision procedure for the theory of equality based on finite instantiations. The main idea is to analyze the structure of the formula and compute accordingly a small domain to each variable such that the formula is satisfiable iff it can be satisfied over these domains. We show how the problem of finding these small domains can be reduced to an interesting graph theoretic problem. This method enabled us to verify formulas containing hundreds of integer and floating point variables that could not be efficiently handled with previously known techniques.
The Gmicro/300 32-Bit Microprocessor
Authors: Takeshi Kitahara, Taizo Satoh
Venue: IEEE Micro (1990)

A high-end microprocessor, the Gmicro/300, based on the TRON architecture specification is described. In contrast to other RISC (reduced-instruction-set-computer) or CISC (complex-instruction-set-computer) chips, it executes an instruction with a memory operand and a register operand in one clock cycle. Separate cache memories improve performance more than 13.8%. The Gmicro/300's pipeline structure, its other one-cycle structures, and the effects of using internal caches are discussed.
Approximate Fair Dropping for Variable-Length Packets
Authors: Konstantinos Psounis, Rong Pan, Balaji Prabhakar
Venue: IEEE Micro (2001)

The CHOKe router algorithm provides an approximately fair bandwidth allocation at a low implementation cost. The authors consider performance and implementation issues associated with CHOKe, with particular emphasis on variable-length packets.
The Self-Made Tapestry: Pattern Formation in Nature
Authors: Philip Ball
Venue:  (2001)

:Why do similar patterns and forms appear in nature in settings that seem to bear no relation to one another? The Windblown ripples of desert sand follow a sinuous course that resembles the stripes of a zebra or a marine fish. In the trellis-like shells of microscopic sea creatures we see the same geometry as in the bubble walls of foam, Forks of lightning mirror the branches of a river network or a tree. This book explains why these are not coincidences. Nature commonly weaves its tapestry without any master plan or blueprint. Instead, these designs build themselves by self-organization. The interactions between the component parts -- whether they be grains of sand, molecules or living cells -- give rise to spontaneous patterns that are at the same time complex and beautiful. Many of these patterns are universal, recurring again and again in the natural order: spirals, spots, stripes, branches, honeycombs. Philip Ball conducts a profusely illustrated tour of this gallery, and reveals the secrets of how nature's patterns are made.
Runtime Incremental Parallel Scheduling (RIPS) on Distributed Memory Computers
Authors: Wei Shu, Min-You Wu
Venue: IEEE Transactions on Parallel and Distributed Systems (1996)

Runtime Incremental Parallel Scheduling (RIPS) is an alternative strategy to the commonly used dynamic scheduling. In this scheduling strategy, the system scheduling activity alternates with the underlying computation work. RIPS utilizes the advanced parallel scheduling technique to produce a low-overhead, high-quality load balancing, as well as adapting to irregular applications. This paper presents methods for scheduling a single job on a dedicated parallel machine.