ppxscal/embedding_network huggingface dataset:
Full abstraction of a real-time denotational semantics for an OCCAM-like language
Authors: C. Huizing, R. Gerth, W. P. deRoever
Venue: Proceedings of the 14th ACM SIGACT-SIGPLAN symposium on Principles of programming languages (1987)

We present a fully abstract semantics for real-time distributed computing of the Ada and OCCAM kind in a denotational style. This semantics turns termination, communication along channels, and the time communication takes place, into observables. Yet it is the coarsest semantics to do so which is syntax-directed (this is known as full abstraction). It extends the linear history semantics for CSP of Francez, Lehman and Pnueli. Our execution model is based on maximizing concurrent activity as opposed to interleaving (in which only one action occurs at the time and arbitrary delays are incurred between actions). It is a variant of the maximal parallelism model of Salwicki and M&uuml;ldner.
An architecture for the direct execution of the Forth programming language
Authors: John R. Hayes, Martin E. Fraeman, Robert L. Williams, Thomas Zaremba
Venue: ACM SIGARCH Computer Architecture News (1987)

We have developed a simple direct execution architecture for a 32 bit Forth microprocessor. The processor can directly access a linear address space of over 4 gigawords. Two instruction types are defined; a subroutine call, and a user defined microcode instruction. On-chip stack caches allow most Forth primitives to execute in a single cycle.
On an Optimally Fault-Tolerant Multiprocessor Network Architecture
Authors: A. Sengupta, A. Sen, S. Bandyopadhyay
Venue: IEEE Transactions on Computers (1987)

This correspondence presents a class of optimally fault tolerant multiprocessor network architecture, based on the networks proposed earlier by Pradhan [71, where the networks are represented by regular digraphs. Because of optimal fault tolerapce, the number of connections per node is precisely related to the degree of fault tolerance the network is designed to provide. The routing of messgges in presence Qf faults is adaptive and unless the number of faults is equal to the degree of fault tolerance the increase in routing delay in presence of faults is minimal.
Hereford workshop on software reuse
Authors: M Ratcliffe
Venue: ACM SIGSOFT Software Engineering Notes (1987)

It is generally acknowledged that one of the most effective means of improving the productivity of software development staff would be to increase the proportion of software which is reused. Not only should this increase productivity but it should also improve the reliability of software and reduce the elapsed time needed for its development. However, there appear to be major technical and organisational problems to be overcome before significant progress can be made in this direction.
Metaclasses are first class: The ObjVlisp Model
Authors: Pierre Cointe
Venue: ACM SIGPLAN Notices (1987)

This paper shows how an attempt at a uniform and reflective definition resulted in an open-ended system supporting ObjVlisp, which we use to simulate object-oriented language extensions. We propose to unify Smalltalk classes and their terminal instances. This unification allows us to treat a class as a &ldquo;first class citizen&rdquo;, to give a circular definition of the first metaclass, to access to the metaclass level and finally to control the instantiation link. Because each object is an instance of another one and because a metaclass is a real class inheriting from another one, the metaclass links can be created indefinitely. This uniformity allows us to define the class variables at the metalevel thus suppressing the Smalltalk-80 ambiguity between class variables and instance variables: in our model the instance variables of a class are the class variables of its instances.
Fast algorithms for N-dimensional restrictions of hard problems
Authors: Friedhelm Meyer auf der Heide
Venue: Journal of the ACM (JACM) (1988)

Let M be a parallel RAM with p processors and arithmetic operations addition and subtraction recognizing L &sub; Nn in T steps. (Inputs for M are given integer by integer, not bit by bit.) Then L can be recognized by a (sequential) linear search algorithm (LSA) in O(n4(log(n) + T + log(p))) steps. Thus many n-dimensional restrictions of NP-complete problems (binary programming, traveling salesman problem, etc.) and even that of the uniquely optimum traveling salesman problem, which is &Dgr;P2-complete, can be solved in polynomial time by an LSA. This result generalizes the construction of a polynomial LSA for the n-dimensional restriction of the knapsack problem previously shown by the author, and destroys the hope of proving nonpolynomial lower bounds on LSAs for any problem that can be recognized by a PRAM as above with 2poly(n) processors in poly(n) time.
Automated conversion of curvilinear wire-frame models to surface boundary models; a topological approach
Authors: John A. Brewer,  III, S. Mark Courter
Venue: ACM SIGGRAPH Computer Graphics (1986)

An algorithm is presented for automatically converting data representing unambiguous, three-dimensional objects in wire-frame form with curvilinear edges into a boundary representation. The method is an important extension to a previously published algorithm based on graph theory and topology. The new method automatically detects and resolves anomalies, such as necks which may appear to be faces, that formerly required human intervention. The topological basis for the solution to this problem is given along with a description of what topological properties a well defined three-dimensional object should have. An implementation has been coded and examples of results are included.
A geometric view of mutual exclusion and deadlock in computer system
Authors: Behrooz Parhami
Venue: ACM SIGCSE Bulletin (1986)

A set of eight simple diagrams with accompanying explanations has proved quite effective as a tool for teaching the concepts of mutual exclusion and deadlock in an operating systems course. This note presents the diagrams in a manner suitable for direct reproduction as viewgraphs or class handouts and touches upon the major points in explaining the diagrams to students.
A preliminary investigation into parallel routing on a hypercube computer
Authors: O. A. Olukotun, T. N. Mudge
Venue: Proceedings of the 24th ACM/IEEE Design Automation Conference (1987)

This paper describes an experiment in which parallel routing is performed on a medium grained hypercube parallel processor having 64 processing elements. Each node is a complete 32-bit computer with 128 K-bytes of memory and is connected to the other nodes via a direct hypercube interconnection network. A new parallel routing algorithm was developed to exploit this parallel structure. It is a three step algorithm consisting of a global routing step, a boundary crossing placement step, and a detailed routing step. All steps can be performed in parallel. When applied to a standard benchmark it was able to route 95 % of the wires. The algorithm was also executed on a large mainframe computer using the same benchmark. The execution time was compared to that for the hypercube. The hypercube was about three times as fast.
Automatic construction of incremental LR(1)&mdash;parsers
Authors: Dashing Yeh, Uwe Kastens
Venue: ACM SIGPLAN Notices (1988)

An effective method is presented for automatic construction of incremental LR(1) parsers. The resulting parsers allow multiple modifications of the original input as well as epsilon productions in the underlying LR(1) grammar. For parsing a modified input, their space require ment depends linear on the length of the input and their runtime is proportional to the total size of the modifications. The method has been implemented for experimental purposes.
International workshop on real-time Ada issues: summary report
Authors: Benjamin Brosgol
Venue: ACM SIGAda Ada Letters (1988)

This workshop, sponsored by Ada U. K. in cooperation with ACM SIGAda, was held in Devon, England, during 13--15 May 1987. It comprised five main sessions on the broad and overlapping topics of Application Requirements, Tasking, Issues in Distributed Processing, Run-Time System Issues, and Design and Development Techniques. A summary session at the end established a set of conclusions and recommendations.Participants in the workshop were selected on the basis of submitted position papers. There were 37 attendees, with 16 representing organizations that are users/implementors of real-time software, 11 representing academic institutions or research laboratories, 6 representing vendors of Ada compilers, and 4 representing hardware manufacturers. The users were principally concerned with avionics and other "hard" real-time applications, as opposed to plant processing control or similar systems with "soft" real-time constraints. Partitioned by country, there were 20 from the U. S., 7 from the U. K., 4 from France, and 1 each from Denmark, Finland, Germany, Italy, Spain and Sweden. (Five from the U. S. were in fact natives of the U.K., so there were more British accents than might be apparent from these figures.)This paper is a summary of the three-day workshop. Complete proceedings including position papers by the participants have been published as a special issue of Ada Letters (Volume VII, Number 6, Fall 1987).
Experimental testing of transport protocol
Authors: O Rafiq, C Chraïbi, R Castanet
Venue: ACM SIGCOMM Computer Communication Review (1986)

This paper describes the interactive testing of ISO transport protocol we carryed out by using the so-called astride technique. The transport protocol class tested is class 2. So far more than two hundreds testing cases have been designed and applied. The testing design approach is based on empirical principles somewhat similar to those used in compiler validation. Testing results are discussed.
Designing a high performance parallel logic programming system
Authors: M. V. Hermenegildo, R. A. Warren
Venue: ACM SIGARCH Computer Architecture News (1987)

Compilation techniques such as those portrayed by the Warren Abstract Machine (WAM) have greatly improved the speed of execution of logic programs. The research presented herein is geared towards providing additional performance to logic programs through the use of parallelism, while preserving the conventional semantics of logic languages. Two areas to which special attention is given are the preservation of sequential performance and storage efficiency, and the use of low overhead mechanisms for controlling parallel execution. Accordingly, the techniques used for supporting parallelism are efficient extensions of those which have brought high inferencing speeds to sequential implementations. At a lower level, special attention is also given to design and simulation detail and to the architectural implications of the execution model behavior. This paper offers an overview of the basic concepts and techniques used in the parallel design, simulation tools used, and some of the results obtained to date.
Fortran 8X&mdash;the draft Fortran standard revision
Authors: J. Adams, J. Reid
Venue: ACM SIGPLAN Fortran Forum (1987)

A revision (Fortran 8x) of the current Fortran Standard (Fortran 77), has been forwarded by X3J3, the Fortran Standards Committee, to X3, the Committee on Information Processing under the American National Standards Institute (ANSI). At the same time, an international group of Fortran experts (Working Group 5 of Subcommittee 22 under the International Standards Organization (ISO) ) has also approved further processing of the draft revision.
Logic programming in APL2
Authors: James A. Brown, Janice H. Cook, Leo H. Groner, Ed Eusebi
Venue: ACM SIGAPL APL Quote Quad (1986)

The most popular vehicles for logic programming are LISP and PROLOG. APL2 has the important features of these languages and more. On one hand, APL2 has all the expressive power of LISP and implementation of PROLOG in APL2 is not difficult. On the other hand, APL2 includes facilities for full screen management, menus, graphics, access to relational databases, and powerful computational primitives. This paper explores the representation of logic using the nested data structures of APL2 and shows how some standard algorithms of logic programming are expressed in APL2. This includes Unification, Resolution, and a logic programming environment like PROLOG. A discussion of the pertinent APL2 notation, detailed discussion of the algorithms and commented programs appear in (Br1).
Computers' impact on productivity and work life
Authors: Susan Dumais, Robert Kraut, Susan Koch
Venue: Proceedings of the ACM SIGOIS and IEEECS TC-OA 1988 conference on Office information systems (1988)

Rapid spread of computer and telecommunication technologies throughout white-collar work has forced researchers to consider their impacts on the people who use them. The present study uses a multi-method, lagged, time-series design to examine the impact of a computerized record system on the work life of customer service representatives in a large utility company. Results show that the computer technology had mixed effects in terms of both productivity and quality of working life, and that these effects varied depending on local organizational culture, management quality, type of worker and their detailed work tasks. Furthermore, during the year in which the computer system was being introduced, the computer system itself, its methods of use, and the managerial goals that spawned it all evolved in response to workers and other factors. These results are used to illustrate the conceptual and methodological complexities involved in establishing the causal impact of computer technology, and to suggest alternate methods for thinking about and measuring technological impact.
Geometric approaches to nonplanar quadric surface intersection curves
Authors: James R. Miller
Venue: ACM Transactions on Graphics (TOG) (1987)

Quadric surfaces occur frequently in the design of discrete piece parts in mechanical CAD/CAM. Solid modeling systems based on quadric surfaces must be able to represent intersection curves parametrically and in a fashion that allows the underlying surfaces to be partitioned. An algebraic approach originally developed by Levin meets these needs but is numerically sensitive and based on solutions to fourth-degree polynomial equations. In this paper we develop geometric approaches that are robust and efficient, and do not require solutions to polynomials of degree higher than 2.
Manufacturing resource planning on a PC local area network
Authors: H. Clark Kee, Roy L. Post
Venue: Proceedings of the international conference on APL (1986)

This paper details a large APL programming project of 12 man years. An integrated software system structured on the principles of MRP (manufacturing resource planning) was implemented by a Bristol-Myers in house team for use in a new manufacturing facility. The system applies off-the-shelf technology in innovative ways, using STSC APL*PLUS/PC as the only programming language, to build a very sophisticated application on IBM/PCs fully sharing data in a secure environment via the NESTAR Plan 4000 local area network and file server. The paper describes technical, application, and business aspects of the project. It should be of interest to (1) persons contemplating or involved in developing APL applications on a local area network, (2) persons developing or who want to develop an integrated manufacturing system, and (3) anyone interested in large APL applications. The plant at which this system operates is located in Nijimegen, the Netherlands, and produces powdered infant formula and other nutritional beverages. The authors believe that this paper is of value both in its description of technological hurdles and achievements, and in the details of the business application.
Interface design issues for advice-giving expert systems
Authors: John M. Carroll, Jean McKendree
Venue: Communications of the ACM (1987)

Advice giving could become the first successful domain for intelligent interfaces.
An Implementation of an Automated Protocol Synthesizer (APS) and Its Application to the X.21 Protocol
Authors: C. V. Ramamoorthy, Siyi T. Dong, Yutaka Usuda
Venue: IEEE Transactions on Software Engineering (1985)

In the past, a number of methods have been proposed to model and validate communication protocols that have already been designed. However, design criteria and design aids are still lacking for designing correct protocols. The objective of developing automated protocol synthesizers is to provide a systematic way of designing new communication protocols such that their correctness can be ensured.
The orders of equidistribution of subsequences of some asymptotically random sequences
Authors: Raymond F. Koopman
Venue: Communications of the ACM (1986)

The orders of equidistribution of subsequences of every nth term of the asymptotically random sequence given by Tootill, Robinson, and Eagle [5], and of six other asymptotically random sequences, were determined for various values of n and of the number of bits to which each term in the sequence is read. Deficiencies in equidistribution were found to be small enough to qualify the sequences for use in applications with fixed, as well as variable, dimensionality requirements. An improved initialization algorithm is also given.
Discovering machine-specific code improvements
Authors: Peter B. Kessler
Venue: Proceedings of the 1986 SIGPLAN symposium on Compiler construction (1986)

I have designed and built a compiler construction tool that automates much of the case analysis necessary to exploit special purpose instructions on a target machine. Given a suitable description of the target machine, my analysis identifies instruction sequences that are equivalent to single instructions. During code generation, these equivalences can be used to avoid inefficient instruction sequences in favor of more efficient instructions.I present a working prototype of the instruction set analyzer needed in the framework outlined by [Giegerich 83]. In contrast to the work presented in [Davidson and Fraser 80, 84], I analyze machine descriptions during compiler construction, rather than analyzing instruction sequences that occur during code generation. [R Kessler 84] describes a system which analyzes machine descriptions during compiler construction, but which which is limited to discovering instructions that are equivalent to instruction sequences of length 2. The techniques presented here can identify instruction sequences of arbitrary length that are equivalent to single instructions.I have applied this analysis to the descriptions of two machines, and used the results to replace hand-written case analysis routines in an otherwise table-driven code generator [Henry 84].
Symbolic Semantics and Program Reduction
Authors: Vincenzo Ambriola, Fosca Giannotti, Dino Pedreschi, Franco Turini
Venue: IEEE Transactions on Software Engineering (1985)

A class of transformations of functional programs based on symbolic execution and simplification of conditionals is presented. The operational symbolic semantics of a family of functional languages is defined exploiting a set-theoretic notion of symbolic constants. An effective transformation able to simplify a functional program via removal of conditionals is discussed. Finally, it is shown that a structural approach, based on abstract data type specifications, provides a suitable representation for symbolic constants.
An optimal algorithm for constructing the Delaunay triangulation of a set of line segments
Authors: C. Wang, L. Schubert
Venue: Proceedings of the third annual symposium on Computational geometry (1987)

In this paper, we first define a new Voronoi diagram for the endpoints of a set of line segments in the plane which do not intersect (except possibly at their endpoints), which is called a bounded Voronoi diagram. In this Voronoi diagram, the line segments themselves are regarded as obstacles. We present an optimal &THgr;(n log n) algorithm to construct it, where n is the number of input line segments. We then show that the straight-line dual of the bounded Voronoi diagram of a set of non-intersecting line segments is the Delaunay triangulation of that set. And the straight-line dual can be obtained in time proportional to the number of input line segments when the corresponding bounded Voronoi diagram is available. Consequently, we obtain an optimal &THgr;(n log n) algorithm to construct the Delaunay triangulation of a set of n non-intersecting line segments in the plane. Our algorithm improves the time bound &Ogr;(n2) of the previous best algorithm.
Cache design of a sub-micron CMOS system/370
Authors: J. H. Chang, H. Chao, K. So
Venue: Proceedings of the 14th annual international symposium on Computer architecture (1987)

An innovative cache accessing scheme based on high MRU (most recently used) hit ratio [1] is proposed for the design of a one-cycle cache in a CMOS implementation of System/370. It is shown that with this scheme the cache access time is reduced by 30 ~ 35% and the performance is within 4% of a true one-cycle cache. This cache scheme is proposed to be used in a VLSI System/370, which is organized to achieve high performance by taking advantage of the performance and integration level of an advanced CMOS technology with half-micron channel length [2]. Decisions on the system partition are based on technology limitations, performance considerations and future extendability. Design decisions on various aspects of the cache organization are based on trace simulations for both UP (uniprocessor) and MP (multiprocessor) configurations.
Programming considerations for documentation and maintenance
Authors: Stephen C. Fleming
Venue: Proceedings of the international conference on APL: APL in transition (1987)

The intent of this paper is to create, or reinforce among programmers an awareness of some simple measures which can be taken during application system development, which can save valuable time later, when somebody else is called upon to document, fix, enhance, or otherwise read and work with their programs. Although the paper describes several approaches to system documentation, it is not expected that any programmer will henceforth develop his applications exclusively around and according to the needs of the technical writer or maintenance analyst. The hope is that by describing a broad range of techniques, individual programmers can select those which best suit their style and approach, while minimizing the imposition of rigid and burdensome &ldquo;standards&rdquo;. The premise being that some, any, assistance provided to future readers, is better than none.
A robotics course using hero I robots
Authors: James Gips
Venue: ACM SIGCSE Bulletin (1986)

An undergraduate Computer Science course in Robotics has been offered for the past two semesters. Supporting the course is a laboratory with six Hero I robots. Students learn how to program the robots in 6808 assembly language.
A real-time expert system for computer network monitor and control
Authors: Barton B Dunning, John Switlik
Venue: Proceedings of the conference on The 1987 ACM SIGBDP-SIGCPR Conference (1987)

SEMACS, is a continuous, real-time expert monitor and control system that actively and passively monitors a computer network. It detects and diagnoses hardware and software problems with the network and provides advice and solutions to an operator in his domain of influence. It was developed jointly by Sperry and one of its customers during an Expert Systems Apprenticeship with the Sperry Knowledge Systems Center. The prototype system, which includes all major components of the final, operational system, was developed over a period of six weeks, and an operational system was put on-line within 3 months of starting the project.