ppxscal/embedding_network huggingface dataset:
High speed on-line backup when using logical log operations
Authors: David B. Lomet
Venue: ACM SIGMOD Record (2000)

Media recovery protects a database from failures of the stable medium by maintaining an extra copy of the database, called the backup, and a media recovery log. When a failure occurs, the database is &ldquo;restored&rdquo; from the backup, and the media recovery log is used to roll forward the database to the desired time, usually the current time. Backup must be both fast and &ldquo;on-line&rdquo;, i.e. concurrent with on-going update activity. Conventional online backup sequentially copies from the stable database, almost independent of the database cache manager, but requires page-oriented log operations. But results of logical operations must be flushed to a stable database (a backup is a stable database) in a constrained order to guarantee recovery. This order is not naturally achieved for the backup by a cache manager concerned only with crash recovery. We describe a &ldquo;full speed&rdquo; backup, only loosely coupled to the cache manager, and hence similar to current online backups, but effective for general logical log operations. This requires additional logging of cached objects to guarantee media recoverability. We then show how logging can be greatly reduced when log operations have a constrained form which nonetheless provides very useful additional logging efficiency for database systems.
Software-Based Rerouting for Fault-Tolerant Pipelined Communication
Authors: J. (Young-Joo) Suh, Binh Vien Dao, Jose Duato, Sudhakar Yalamanchili
Venue: IEEE Transactions on Parallel and Distributed Systems (2000)

This paper presents a software-based approach to fault-tolerant routing in networks using wormhole or virtual cut-through switching. When a message encounters a faulty output link, it is removed from the network by the local router and delivered to the messaging layer of the local node's operating system. The message passing software can reroute this message, possibly along nonminimal paths. Alternatively, the message may be addressed to an intermediate node, which will forward the message to the destination. A message may encounter multiple faults and pass through multiple intermediate nodes. The proposed techniques are applicable to both obliviously and adaptively routed networks. The techniques are specifically targeted toward commercial multiprocessors where the mean time to repair (MTTR) is much smaller than the mean time between router failures (MTBF), i.e., it is sufficient to tolerate a maximum of three failures.This paper presents requirements for buffer management, deadlock freedom, and livelock freedom. Simulation results are presented to evaluate the degradation in latency and throughput as a function of the number and distribution of faults. There are several advantages of such an approach. Router designs are minimally impacted, and thus remain compact and fast. Only messages that encounter faulty components are affected, while the machine is ensured of continued operation until the faulty components can be replaced. The technique leverages existing network technology, and the concepts are portable across evolving switch and router designs. Therefore, we feel that the technique is a good candidate for incorporation into the next generation of multiprocessor networks.
Factoring logic functions using graph partitioning
Authors: Martin C. Golumbic, Aviad Mintz
Venue: Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design (1999)

Algorithmic logic synthesis is usually carried out in two stages, the independent stage where logic minimization is performed on the Boolean equations with no regard to physical properties and the dependent stage where mapping to a physical cell library is done. The independent stage includes logic operations like Decomposition, Extraction, Factoring, Substitution and Elimination. These operations are done with some kind of division (boolean, algebraic), with the goal being to obtain a logically equivalent factored form which minimizes the number of literals.In this paper, we present an algorithm for factoring that uses graph partitioning rather than division. Central to our approach is to combine this with the use of special classes of boolean functions, such as read-once functions, to devise new combinatorial algorithms for logic minimization. Our method has been implemented in the SIS environment, and an empirical evaluation indicates that we usually get significantly better results than algebraic factoring and are quite competitive with boolean factoring but with lower computation costs.
Efficient diagnosis of path delay faults in digital logic circuits
Authors: Pankaj Pant, Abhijit Chatterjee
Venue: Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design (1999)

A new methodology involving effect-cause analysis has been demonstrated for the diagnosis of path delay faults. We seek to provide an improved understanding of the methods introduced in [6], with the goal of devising efficient representations and algorithms for the diagnosis of path delay faults. Results indicate that the diagnostic resolution obtained is very high and includes all possible causes of the observed delay faults.
Stable set and multiset operations in optimal time and space
Authors: Bing-Chao Huang, Michael A. Langston
Venue: Proceedings of the seventh ACM SIGACT-SIGMOD-SIGART symposium on Principles of database systems (1988)

The focus of this paper is on demonstrating the existence of methods for stably performing set and multiset operations on sorted files of data in both optimal time and optimal extra space. It is already known that stable merging and stable duplicate-key extraction permit such methods. The major new results reported herein are these an asymptotically optimal time and space algorithm is devised for stably selecting matched records from a sorted file, this selection strategy is employed, along with other algorithmic tools, to prove that all of the elementary binary set operations can be stably performed in optimal time and space on sorted files, and after generalizing these operations to multisets in a natural way for file processing, it is proved that each can be stably performed in optimal time and space on sorted files
A fully associative software-managed cache design
Authors: Erik G. Hallnor, Steven K. Reinhardt
Venue: Proceedings of the 27th annual international symposium on Computer architecture (2000)

As DRAM access latencies approach a thousand instruction-execution times and on-chip caches grow to multiple megabytes, it is not clear that conventional cache structures continue to be appropriate. Two key features&mdash;full associativity and software management&mdash;have been used successfully in the virtual-memory domain to cope with disk access latencies. Future systems will need to employ similar techniques to deal with DRAM latencies. This paper presents a practical, fully associative, software-managed secondary cache system that provides performance competitive with or superior to traditional caches without OS or application involvement. We see this structure as the first step toward OS- and application-aware management of large on-chip caches. This paper has two primary contributions: a practical design for a fully associative memory structure, the indirect index cache (IIC), and a novel replacement algorithm, generational replacement, that is specifically designed to work with the IIC. We analyze the behavior of an IIC with generational replacement as a drop-in, transparent substitute for a conventional secondary cache. We achieve miss rate reductions from 8% to 85% relative to a 4-way associative LRU organization, matching or beating a (practically infeasible) fully associative true LRU cache. Incorporating these miss rates into a rudimentary timing model indicates that the IIC/generational replacement cache could be competitive with a conventional cache at today's DRAM latencies, and will outperform a conventional cache as these CPU-relative latencies grow.
Tree Diversity, Landscape Diversity, and Economics of Maple-Birch Forests: Implications of Markovian Models
Authors: Ching-Rong Lin, Joseph Buongiorno
Venue: Management Science (1998)

Markov decision process (MDP) models were effective in analyzing forest management policies. Even the simplest standard results gave useful insights into forest ecology, such as how landscape diversity is shaped by natural catastrophes, and how forests mature through successional phases. The methods were also useful to predict the effects of different management policies on ecological and economic criteria. Optimization augmented the usefulness of the approach, suggesting that income from Wisconsin's maple-birch forests could be increased without ruining their diversity of landscape, tree size, and tree species. It showed that maximizing species diversity, defined by the distribution of trees in shade-tolerance classes, would require some harvest. Instead, maximum tree size diversity occurred in unmanaged forests, but this gave a less diverse landscape and no income. The MDP method allowed for the design of compromise policies that would maximize income while keeping diversity above specified limits. The opportunity cost of increasing tree size diversity was found to be much higher than for species diversity. Comparing the maximum timber income owners could have got with what they actually cut suggested that the amenity value of forests was four times that of timber. Advantages of the methods reside in the ability to model complex ecosystem processes with simple probability matrices, and in the rich MDP theory and algorithms. Limitations include the difficulty of defining a space set large enough for accurate discretization, but small enough for practical application.
Integer Factoring
Authors: Arjen K. Lenstra
Venue: Designs, Codes and Cryptography (2000)

Using simple examples and informal discussions this article surveys the key ideas and major advances of the last quarter century in integer factorization.
Towards a new standard for system-level design
Authors: Stan Y. Liao
Venue: Proceedings of the eighth international workshop on Hardware/software codesign (2000)

Huge new design challenges for system-on-chip (SoC) are the result of decreasing time-to-market coupled with rapidly increasing gate counts and embedded software representing 50-90 percent of the functionality. The exchange of system-level intellectual property (IP) models for creating executable specifications has become a key strategic element for efficient system-to-silicon design flows. Because C and C++ are the dominant languages used by chip architects, systems engineers and software engineers today, we believe that a C-based approach to hardware modeling is necessary. This will enable co-design, providing a more natural solution to partitioning functionality between hardware and software. In this paper we present the design of SystemC, a C++ class library that provides the necessary features for modeling design hierarchy, concurrency, and reactivity in hardware. We will also describe experiences of using SystemC 1) for the co-verification of 8051 processor with a bus-functional model and 2) for the modeling and simulation of an MPEG-2 video decoder.
Priority Scheduling Versus Pre-Run-Time Scheduling
Authors: Jia Xu, David Lorge Parnas
Venue: Real-Time Systems (2000)

Builders of real-time systems often use priority scheduling in their systems without considering alternatives. This paper examines one alternative, pre-run-time scheduling, and show that when it can be applied it has significant advantages when compared to priority scheduling schemes.
Storageless value prediction using prior register values
Authors: Dean M. Tullsen, John S. Seng
Venue: ACM SIGARCH Computer Architecture News (1999)

This paper presents a technique called register value prediction (RVP) which uses a type of locality called register-value reuse. By predicting that an instruction will produce the value that is already stored in the destination register, we eliminate the need for large value buffers to enable value prediction. Even without the large buffers, register-value prediction can be made as or more effective than last-value prediction, particularly with the aid of compiler management of values in the register file.Both static and dynamic register value prediction techniques are demonstrated to exploit register-value reuse, the former requiring minimal instruction set architecture changes and the latter requiring a set of small confidence counters. We show an average gain of 12% with dynamic RVP and moderate compiler assistance on a next generation processor, and 15% on a 16-wide processor.
2M&ndash;T1 Testing: Ensuring That Your Data Makes It Across The Interface
Authors: Doug J. Smith
Venue: International Journal of Network Management (1996)

Service providers and end users need to be sure that a 2M&ndash;T1 network is synchronized and timed correctly.
Large Occlusion Stereo
Authors: Aaron F. Bobick, Stephen S. Intille
Venue: International Journal of Computer Vision (1999)

A method for solving the stereo matching problem in the presence of large occlusion is presented. A data structure&mdash;the disparity space image&mdash;is defined to facilitate the description of the effects of occlusion on the stereo matching process and in particular on dynamic programming (DP) solutions that find matches and occlusions simultaneously. We significantly improve upon existing DP stereo matching methods by showing that while some cost must be assigned to unmatched pixels, sensitivity to occlusion-cost and algorithmic complexity can be significantly reduced when highly-reliable matches, or ground control points, are incorporated into the matching process. The use of ground control points eliminates both the need for biasing the process towards a smooth solution and the task of selecting critical prior probabilities describing image formation. Finally, we describe how the detection of intensity edges can be used to bias the recovered solution such that occlusion boundaries will tend to be proposed along such edges, reflecting the observation that occlusion boundaries usually cause intensity discontinuities.
Optical burst switching (OBS) - a new paradigm for an optical Internet
Authors: Chunming Qiao, Myungsik Yoo
Venue: Journal of High Speed Networks (1999)

To support bursty traffic on the Internet (and especially WWW) efficiently, optical burst switching (OBS) is proposed as a way to streamline both protocols and hardware in building the future generation Optical Internet. By leveraging the attractive properties of optical communications and at the same time, taking into account its limitations, OBS combines the best of optical circuit-switching and packet/cell switching. In this paper, the general concept of OBS protocols and in particular, those based on Just-Enough-Time (JET), is described, along with the applicability of OBS protocols to IP over WDM. Specific issues such as the use of fiber delay-lines (FDLs) for accommodating processing delay and/or resolving conflicts are also discussed. In addition, the performance of JET-based OBS protocols which use an offset time along with delayed reservation to achieve efficient utilization of both bandwidth and FDLs as well as to support priority-based routing is evaluated.
Spherical 7-Designs in 2^n-Dimensional Euclidean Space
Authors: V. M. Sidelnikov
Venue: Journal of Algebraic Combinatorics: An International Journal (1999)

We consider a finite subgroup &Theta;_n of the group O(N) of orthogonal matrices, where N &equals; 2^n, n &equals; 1, 2 &hellip;. This group was defined in [7]. We use it in this paper to construct spherical designs in 2^n-dimensional Euclidean space R. We prove that representations of the group &Theta;_n on spaces of harmonic polynomials of degrees 1, 2 and 3 are irreducible. This and the earlier results [1&ndash;3] imply that the orbit &Theta;_n, 2x of any initial point x on the sphere S_N &minus; 1 is a 7-design in the Euclidean space of dimension 2^n.
Singular Perturbation of a Finite Horizon Problem with State-Space Constraints
Authors: Fabio Bagagiolo, Martino Bardi
Venue: SIAM Journal on Control and Optimization (1998)

We study the singular perturbation of optimal control problems for nonlinear systems with constraints on the fast state variables and a cost functional either of Bolza type or involving the exit time of the system from a given domain. Under a controllability assumption on the fast variables, we show that these variables become controls in the limit problem. Our method consists of passing to the limit in the associated Hamilton--Jacobi--Bellman (HJB) equations by means of some tools in the theory of viscosity solutions.
Report on the 13th Brazilian symposium on database systems (SBBD'98)
Authors: Mario A. Nascimento, Claudia Bauzer Medeiros
Venue: ACM SIGMOD Record (1999)

The Brazilian Symposium on Database Systems (SBBD) is a traditional conference in Brazil, and is sponsored by the Brazilian Computer Society. SBBD's technical program contemplates the following activities: presentation of peer reviewed full technical papers, invited talks, tutorials (either invited and selected from submissions), discussion panels and presentation of tools.
An Adaptation of Krylov Subspace Methods to Path Following Problems
Authors: Homer F. Walker
Venue: SIAM Journal on Scientific Computing (1999)

A procedure is outlined for adapting Krylov subspace methods to solving approximately the underdetermined linear systems that arise in path following (continuation, homotopy) methods. This procedure, in addition to preserving the usual desirable features of Krylov subspace methods, has the advantages of satisfying orthogonality constraints exactly and of not introducing ill-conditioning through poor scaling.
Introducing the Theme in a Qualitative Interview Using a Visual Starter
Authors: Birgitta Lorentzson, Erik Trell
Venue: Journal of Medical Systems (1999)

Community involvement implies conscientious citizen engagement, not as passive recipients but active contributors. Insufficient understanding of concepts of health outcome in a socioeconomic deprived context with unemployment as a major feature was identified as a hindrance to intervention. This communication gives a report of a &ldquo;visual starter&rdquo; used as a cognitive instrument for qualitative research on concepts of joblessness and health. Health education and behavioral change efforts are often insufficient in reaching empowerment on individual or community levels. It is suggested that understanding different categories of thinking using a phenomenographic method could contribute to strategies for community involvement. The &ldquo;visual starter&rdquo; uses pictures to introduce the theme as well as for associative purposes in the interview.
Limits of Data Value Predictability
Authors: Yiannakis Sazeides, James E. Smith
Venue: International Journal of Parallel Programming (1999)

The predictability of data values is studied at a fundamental level. Two basic predictor models are defined: Computational predictors perform an operation on previous values to yield predicted next values. Examples we study are stride value prediction and last value prediction; Context-Based predictors match recent value history (context) with previous value history and predict values based entirely on previously observed patterns. To understand the potential of value prediction we perform simulations with unbounded prediction tables that are immediately updated using correct data values. Simulations of integer SPEC95 benchmarks show that data values can be highly predictable. Best performance is obtained with context-based predictors; overall prediction accuracies are between 56% and 92%. The context based predictor typically has an accuracy about 20% better than the computational predictors (last value and stride). Results with bounded tables suggest the feasibility of context-based predictors that approximate the performance with unbounded tables.
The design of a class mechanism for Moby
Authors: Kathleen Fisher, John Reppy
Venue: ACM SIGPLAN Notices (1999)

Typical class-based languages, such as C++ and JAVA, provide complex class mechanisms but only weak module systems. In fact, classes in these languages incorporate many of the features found in richer module mechanisms. In this paper, we describe an alternative approach to designing a language that has both classes and modules. In our design, we rely on a rich ML-style module system to provide features such as visibility control and parameterization, while providing a minimal class mechanism that includes only those features needed to support inheritance. Programmers can then use the combination of modules and classes to implement the full range of class-based features and idioms. Our approach has the advantage that it provides a full-featured module system (useful in its own right), while keeping the class mechanism quite simple.We have incorporated this design in MOBY, which is an ML-style language that supports class-based object-oriented programming. In this paper, we describe our design via a series of simple examples, show how various class-based features and idioms are realized in MOBY, compare our design with others, and sketch its formal semantics.
Using shape analysis to reduce finite-state models of concurrent Java programs
Authors: James C. Corbett
Venue: ACM Transactions on Software Engineering and Methodology (TOSEM) (2000)

Finite-state verification (e.g., model checking) provides a powerful means to detect concurrency errors, which are often subtle and difficult to reproduce. Nevertheless, widespread use of this technology by developers is unlikely until tools provide automated support for extracting the required finite-state models directly from program source. Unfortunately, the dynamic features of modern languages such as Java complicate the construction of compact finite-state models for verification. In this article, we show how shape analysis, which has traditionally been used for computing alias information in optimizers, can be used to greatly reduce the size of finite-state models of concurrent Java programs by determining which heap-allocated variables are accessible only by a single thread, and which shared variables are protected by locks. We also provide several other state-space reductions based on the semantics of Java monitors. A prototype of the reductions demonstrates their effectiveness.
An RTL Abstraction Technique for Processor MicroarchitectureValidation and Test Generation
Authors: Jian Shen, Jacob A. Abraham
Venue: Journal of Electronic Testing: Theory and Applications (2000)

Design validation is becoming more and more a bottleneck in the microprocessor design process. The difficulty of validation stems from the complexity of the design, which requires searching an enormous space to check correctness. This is exacerbated by features for enhancing performance, such as pipelines, which are becoming common in most microprocessors. This paper describes a new abstraction technique to handle this problem. Our solution is a novel method to identify the control states automatically from the processor HDL description and to extract an abstract finite state machine model which preserves the behaviors of the design accurate to the clock cycle, so that the state space to be analyzed is drastically reduced.This model is used to evaluate microarchitecture-level coverage of validation tests. We also present validation test generation algorithm for traversing state transition paths and covering snapshot and temporal events. These abstract paths with a finite length, along with information about the instruction set, are used to generate system-level tests. Results on example microprocessor models show the technique is efficient in finding bugs that other verification methods miss.