ppxscal/embedding_network huggingface dataset:
The Use of Prediction for Accelerating Upgrade Misses in cc-NUMA Multiprocessors
Authors: Manuel E. Acacio, José González, José M. García, José Duato
Venue: Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques (2002)

This work is focused on accelerating upgrade misses in cc-NUMA multiprocessors. These misses are caused by store instructions for which a read-only copy of the line is found in the L2 cache. Upgrade misses require a message sent from the missing node to the directory, a directory lookup in order to find the set of sharers, invalidation messages being sent to the sharers and responses to the invalidations being sent back. Therefore, the penalty paid by these misses is not negligible, mainly if we consider that they account for a high percentage of the total miss rate. We propose the use of prediction as a means of providing cc-NUMA multiprocessors with a more efficient support for upgrade misses by directly invalidating sharersfrom the missing node. Our proposal comprises an effective prediction scheme achieving high hit rates as well as a coherence protocol extended to support the use of prediction. Our work is motivated by two key observations: first, upgrade misses present a repetitive behavior and, second, the total number of sharers being invalidated is small (one, in some cases). Using execution-driven simulations, we show that the use of prediction can significantly accelerateupgrade misses (latency reductions of more than 40% in some cases). These important improvements translate into speed-ups on application performance up to 14%. Finally, these results can be obtained including a predictor with a total size of less than 48 KB in every node.
Image Decomposition in Morphological Residues: An Approach for Image Filtering and Segmentation
Authors: Silvio Jamil Ferzoli Guimarães, Neucimar Jerônimo Leite
Venue: Proceedings of the 13th Brazilian Symposium on Computer Graphics and Image Processing (2000)

Morphological residues represent an image in a hierarchical way by means of a decomposition of its structures and according to a size parameter /spl lambda/. From this decomposition, we can obtain a relation between the different residual levels associated with the complexity of the image structures. In this work, we introduce a method for filtering of components in gray-scale images based on the morphological residue decomposition which takes into account a size parameter and a certain level of complexity of the different structures we want to be filtered.
A highly parallel algorithm to approximate MaxCut on distributed memory architectures
Authors: Steven Homer, Marcus Peinado
Venue: Proceedings of the 9th International Symposium on Parallel Processing (1995)

We develop and experiment with a new parallel algorithm to approximate the maximum weight cut in a weighted undirected graph. Our implementation is based on the recent new algorithm of Goemans and Williamson for this problem. However, our work aims for an efficient, practical formulation of the algorithm with close to optimal parallelization. Our theoretical analysis and an implementation on the Connection Machine CM5 show that our parallelization achieves linear speedup. We test our implementation on several large graphs (more than 9000 vertices), particularly on large instances of the Ising model.
Automatic Separation of Words in Multi-lingual Multi-script Indian Documents
Authors: U. Pal, B. B. Chaudhuri
Venue: Proceedings of the 4th International Conference on Document Analysis and Recognition (1997)

In a multi-lingual country like India, a document may contain more than one script forms. For such a document it is necessary to separate different script forms before feeding them to OCRs of individual script. In this paper an automatic word segmentation approach is described which can separate Roman, Bangla and Devnagari scripts present in a single document. The approach has a tree structure where at first Roman script words are separated using the `headline' feature. The headline is common in Bangla and Devnagari but absent in Roman. Next, Bangla and Devnagari words are separated using some finer characteristics of the character set although recognition of individual character is avoided. At present, the system has an overall accuracy of 96.09%.
Infrastructure for Building Parallel Database Systems for Multi-Dimensional Data
Authors: Chialin Chang, Renato Ferreira, Alan Sussman, Joel H. Saltz
Venue: Proceedings of the 13th International Symposium on Parallel Processing and the 10th Symposium on Parallel and Distributed Processing (1999)

Our study of a large set of scientific applications over the past three years indicates that the processing for multi-dimensional datasets is often highly stylized. The basic processing step usually consists of mapping the individual input items to the output grid and computing output items by aggregating, in some way, all the input items mapped to the corresponding grid point. In this paper, we discuss the design and performance of T2, an infrastructure for building parallel database systems that integrates storage, retrieval and processing of multi-dimensional datasets. It achieves its primary advantage from the ability to integrate data retrieval and processing for a wide variety of applications and from the ability to maintain and jointly process multiple datasets with different underlying grids. We present preliminary performance results comparing the implementation of two applications using the T2 services with custom-built integrated implementations.
Forbidden Information
Authors: Leonid A. Levin
Venue: Proceedings of the 43rd Symposium on Foundations of Computer Science (2002)

There appears to be a gap between usual interpretations of Godel Theorem and what is actually proven. Closing this gap does not seem obvious and involves complexity theory. (This is unrelated to, well studied before, complexity quantifications of the usual Godel effects.) Similar problems and answers apply to other unsolvability results for tasks where required solutions are not unique, such as, e.g., non-recursive tilings.
The Constraint-Based Knowledge Broker System
Authors: Jean-Marc Andreoli, Uwe M. Borghoff, Pierre-Yves Chevalier, Boris Chidlovskii, Remo Pareschi, Jutta Willamowski
Venue: Proceedings of the Thirteenth International Conference on Data Engineering (1997)

The amount of information available from electronic sources on the World Wide Web and other on-line information repositories is highly heterogeneous and increases dramatically. Tools are needed to extract relevant information from these repositories. The Constraint-Based Knowledge Brokers project (CBKB) at RXRC Grenoble realizes sophisticated facilities for efficient information retrieval, schema integration, and knowledge fusion. The current implementation of the CBKB research prototype involves three kinds of agents: a) users, who input queries and process answers (i.e., ranking, fusion) through a GUI; b) wrappers, capable of interrogating heterogeneous information sources, which can provide answers to elementary queries (essentially various public bibliographic catalogues available on the Web, as well as preprint archives and opera information repositories); c) brokers, which can manage complex queries (i.e., decompose a complex query, recompose the partial answers, synthesize a full answer) and which mediate between the GUI and the different wrappers.
Filtering Techniques to Improve Trace-Cache Efficiency
Authors: Roni Rosner, Avi Mendelson, Ronny Ronen
Venue: Proceedings of the 2001 International Conference on Parallel Architectures and Compilation Techniques (2001)

Abstract: The trace cache is becoming an important building block of modern, wide-issue processors. So far, trace cache related research has been focused on increasing fetch bandwidth. Trace-caches have been shown too effectively increase the number of "useful" instructions that can be fetched into the machine, thus enabling more instructions to be executed each cycle. However, trace cache has another important benefit that got less attention in recent research: especially for variable length ISA, such as Intel's IA-32 architecture (X86), reducing instruction decoding power is particularly attractive. Keeping the instruction traces in decoded format, implies the decoding power is only paid upon the build of a trace, thus reducing the overall power consumption of the system. This paper has three main contributions: it indicates that trace cache optimizations directed to reducing power consumption arc do not necessarily coincide with optimizations directed to increasing fetch bandwidth; it extends our understanding on how well the trace cache utilizes its resources and introduces a new trace-cache organization based on filtering techniques. The knowledge obtained from the analysis of the traces' behavioral patterns motivates the use of filtering techniques. The new trace-cache organization increases the effective instruction-fetch bandwidth in conjunction with reducing the power consumption of the trace-cache system. We observe that (1) the majority of traces that are inserted into the trace-cache are rarely used again before being replaced; (2) the majority of the instructions delivered for execution originate from the fewer traces that are heavily and repeatedly used; and that (3) techniques that aim to improve instruction-fetch bandwidth may increase the number of traces built during program execution. Based on these observations, we propose splitting the trace cache into two components: the filter trace-cache (FTC) and the main trace-cache (MTC). Traces are first inserted into the FTC that is used to filter out the infrequently used traces; traces that prove "useful" are later moved into the MTC itself. The FTC/MTC organization exhibits an important benefit: it decreases the number of traces built, thus reducing power consumption while improving overall performance. For medium-size applications, the FTC/MTC pair reduces the number of trace builds by 16% in average. As extension of the filtering concept that involves adding a second level (L2) trace-cache that stores less frequent traces that are replaced in the FTC or the MTC. The extra level of caching allows for order-of-magnitude reduction in the number of trace builds. Second level trace cache proves particularly useful for applications with large instruction footprints.
Interactive Visual Exploration of Distributed Computations
Authors: Delbert Hart, Eileen Kraemer
Venue: Proceedings of the 11th International Symposium on Parallel Processing (1997)

Program understanding is central to the development of distributed computations, from the initial coding phase, through testing and debugging, to maintenance and support. Our goal is to support programmers unfamiliar with a particular distributed computation in developing a reasonable understanding of the workings of a program, without requireing that they examine the details of the code itself. Toward, this goal, we propose query-based visualization, a novel exploratory approach to understanding distributed computations. The key features of the approach are the use of queries as a device for searching the state space, visual presentation techniques adapted from program animation, and the ability to navigate through the state space using visual interactions. All views correspond to globally consistent snapshots of the computation. A working prototype demonstrates the technical feasibility of the approach.
A novel architecture for an ATM switch
Authors: Jin Li, Chuan-lin Wu
Venue: Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors (1995)

Multicast function is essential for an ATM switch. We propose a novel architecture for an output-buffer ATM switch and a shared-buffer ATM switch to realize the multicast function in a more efficient way. In an output-buffer ATM switch, we dedicate a first-in and first-out (FIFO) shared buffer for all multicast cells to increase buffer utilization. In a shared-buffer ATM switch, we dedicate a FIFO address queue for all multicast cells to simplify the design of the control logic. Performance evaluation of the new switch is also provided. Since each multicast cell occupies only one buffer space, the proposed switch achieves a better cell-loss performance under multicast traffic loads without the need for complicated control circuitry.
Hierarchical Text Classification and Evaluation
Authors: Aixin Sun, Ee-Peng Lim
Venue: Proceedings of the 2001 IEEE International Conference on Data Mining (2001)

Hierarchical Classification refers to assigning of one or more suitable categories from a hierarchical category space to a document. While previous work in hierarchical classification focused on virtual category trees where documents are assigned only to the leaf categories, we propose atop-down level-based classification method that can classify documents to both leaf and internal categories. As the standard performance measures assume independence between categories, they have not considered the documents incorrectly classified into categories that are similar or not far from the correct ones in the category tree. We therefore propose the Category-Similarity Measures and Distance-Based Measures to consider the degree of misclassification in measuring the classification performance. An experiment has been carried out to measure the performance four proposed hierarchical classification method. The results showed that our method performs well for Reuters text collection when enough training documents are given andthe new measures have indeed considered the contributions of misclassified documents.
Recognizing components of handwritten characters by attributed relational graphs with stable features
Authors: Xingyuan Li, Weon-Geun Oh, Jiarong Hong, Wen Gao
Venue: Proceedings of the 4th International Conference on Document Analysis and Recognition (1997)

We present a method for Chinese character component recognition. We use an attributed relational graph model to describe a component. This model allows us to express the knowledge of the component shape and can include stable features of the component in various writing styles and various characters. We then describe a method to extract graph representation of an input character. The graph models are used to recognize components from a whole character by subgraph isomorphism. Our method need not segment component from character and can tolerate links and overlaps between a component and the other part. Experiments for handwritten Chinese characters show its efficiency.
Statistics on concurrent fault and design error simulation
Authors: Brian Grayson, Saghir A. Shaikh, Stephen A. Szygenda
Venue: Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors (1995)

Basic data of the nature presented here on fault and design error simulation processes have not been previously reported. Experiments are performed on c-sim, a gate level concurrent simulator developed at the University of Texas at Austin. Three types of statistics are considered: event based statistics, gate evaluation statistics and memory requirements. These statistics are important for design verification researchers and engineers for numerous reasons. For example, they help simulator developers tune up or optimize their concurrent simulators. They also fulfill the increasing need for experimental data concerning design error simulation. Most importantly, these statistics provide guidance to hardware accelerator designers in evaluating and comparing various design options.
An Efficient Data Mining Technique for Discovering Interesting Sequential Patterns
Authors: Show-Jane Yen, Yue-Shi Lee
Venue: Proceedings of the 2001 IEEE International Conference on Data Mining (2001)

Mining sequential patterns is to discover sequentialpurchasing behaviors of most customers from a largeamount of customer transactions. In this paper, a datamining language is presented. From the data mininglanguage, use s can specify the interested items and thecriteria of the sequential patterns to be discovered. Also,an efficient data mining technique is proposed to ext actthe sequential patterns according to the uses` requests.
Dag-Consistent Distributed Shared Memory
Authors: Robert D. Blumofe, Matteo Frigo, Christopher F. Joerg, Charles E. Leiserson, Keith H. Randall
Venue: Proceedings of the 10th International Parallel Processing Symposium (1996)

We introduce dag consistency, a relaxed consistency model for distributed shared memory which is suitable for multithreaded programming. We have implemented dag consistency in software for the Cilk multithreaded runtime system running on a Connection Machine CM5. Our implementation includes a dag-consistent distributed cactus stack for storage allocation. We provide empirical evidence of the flexibility and efficiency of dag consistency for applications that include blocked matrix multiplication, Strassen's matrix multiplication algorithm, and a Barnes-Hut code. Although Cilk schedules the executions of these programs dynamically, their performances are competitive with statically scheduled implementations in the literature. We also prove that the number F_P of page faults incurred by a user program running on P processors can be related to the number F_1 of page faults running serially by the formula F_P \leq F_1 + 2Cs, where C is the cache size and s is the number of thread migrations executed by Cilk's scheduler.
A superscalar RISC processor with pseudo vector processing feature
Authors: Kotaro Shimamura, Shigeya Tanaka, Tetsuya Shimomura, Takashi Hotta, Eiki Kamada, Hideo Sawamoto, Teruhisa Shimizu, Kisaburo Nakazawa
Venue: Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors (1995)

A novel architectural extension, in which floating-point data are transferred directly from main memory to floating-point registers, has been successfully implemented in a superscalar RISC processor. This extension allows main memory access throughput of 1.2 Gbyte/s, and effective performance reaches 267 MFLOPS (89% of the peak performance) for typical floating-point applications. The processor utilizes 0.3-micron 4-level metal CMOS technology with 2.5 V power supply and contains 3.9 million transistors in 15.7 mm/spl times/15.7 mm die size. Only 4.5% of the die area is used for the extension. Pipeline stage optimization and scoreboard-based dependency check method allow the extension to be realized without affecting the operating frequency.
Time synchronization on SP1 and SP2 parallel systems
Authors: Bülent Abali, Craig B. Stunkel
Venue: Proceedings of the 9th International Symposium on Parallel Processing (1995)

We describe an experimental time utility for synchronizing the operating system clocks on the SP1 and SP2 parallel system nodes. It synchronizes the node clocks typically, within 5 microseconds of each other utilizing the synchronous feature of the SP1 and SP2 interconnection network. This is 2 to 3 orders of magnitude better than what can be achieved by previous methods. Synchronized clocks are useful for parallel program performance measurement and tuning, parallel program tracing and debugging, and gang scheduling of parallel processes, to name a few. We also measure the performance of a widely used time synchronization utility using the SP1 and SP2 interconnection network.
Evaluating Boosting Algorithms to Classify Rare Classes: Comparison and Improvements
Authors: Mahesh V. Joshi, Vipin Kumar, Ramesh C. Agarwal
Venue: Proceedings of the 2001 IEEE International Conference on Data Mining (2001)

Classification of rare vents has many important data mining applications. Boosting is a promising meta-techniquethat improves the classification performance of any weak classifier. So far, no systematic study has been conducted to evaluate how boosting performs for the task of mining rare classes. In this paper, we evaluate three existing categories of boosting algorithms from the single viewpoint of how they update the example weights in eachiteration, and discuss their possible effect on recall andprecision of the rare class. We propose enhanced algorithms in two of the categories, and justify their choice of weightupdating parameters theoretically. Using some specially designed synthetic datasets, we compare the capability of all the algorithms from the rare class perspective. Theresults support our qualitative analysis, and also indicate that our enhancements bring an extra capability for achieving better balance between recall and precision in mining rareclasses.
The Amaranth Framework: Probabilistic, Utility-Based Quality of Service Management for High-Assurance Computing
Authors: Carol L. Hoover, Jeffery P. Hansen, Philip Koopman, Sandeep Tamboli
Venue: The 4th IEEE International Symposium on High-Assurance Systems Engineering (1999)

System resource management for high-assurance applications such as the command and control of a battle group is a complex problem. These applications often require guaranteed computing services that must satisfy both hard and soft deadlines. In addition, their resource demands can vary significantly over time with bursts of high activity amidst periods of inactivity. A traditional solution has been to dedicate resources to critical application tasks and to share resources among non-critical tasks. With the increasing complexity of high-assurance applications and the need to reduce system costs, dedicating resources is not a satisfactory solution. The Amaranth Project at Carnegie Mellon is researching and developing a framework for allocating shared resources to support multiple quality of service (QoS) dimensions and to provide probabilistic assurances of service. This paper is an overview of the Amaranth framework, the current results from applying the framework, and the future research directions for the Amaranth project.
A Content-Based Resource Location Mechanism in PeerIS
Authors: Bo Ling, Zhiguo Lu, Wee Siong Ng, Beng Chin Ooi, Kian-Lee Tan, Aoying Zhou
Venue: Proceedings of the 3rd International Conference on Web Information Systems Engineering (2002)

With the flurry of research on P2P computing, many P2Ptechnical challenges have emerged, one of which is how toefficiently locate desired resources. Advances have beenmade in this hot research field, where the pioneers are Pastry,CAN, Chord, and Tapestry. By using the functionalityof distributed hash table, they have achieved fair effectiveness.However, they have many common limitations, suchas ignoring the autonomous nature of peers, and just supportingweakly semantic functions. In this paper, accord-ingto the reality in the distributed network, we proposea content-based location mechanism, which not only keepthe autonomy of peers, but also support approximate queryand finer granularity of content sharing. Furthermore, thismechanism also facilitates P2P system to evolve dynamically.We have also used PeerIS, a P2P based informationsystem used to verify it and obtained satisfactory results.
Software Systems: Consequence versus Functionality
Authors: Victor L. Winter, Ray Berg
Venue: The 4th IEEE International Symposium on High-Assurance Systems Engineering (1999)

The purpose of this panel is to present different perspectives and opinions regarding the issues surrounding why software should or shouldn't be entrusted with critical (high consequence) functionality.