ppxscal/embedding_network huggingface dataset:
Memory Latency Effects in Decoupled Architectures
Authors: L. Kurian, P. T. Hulina, L. D. Coraor
Venue: IEEE Transactions on Computers (1994)

Decoupled computer architectures partition the memory access and execute functions in a computer program and achieve high-performance by exploiting the fine-grain parallelism between the two. These architectures make use of an access processor to perform the data fetch ahead of demand by the execute process and hence are often less sensitive to memory access delays than conventional architectures. Past performance studies of decoupled computers used memory systems that are interleaved or pipelined, and in those studies, latency effects were partially hidden due to interleaving. A detailed simulation study of the latency effects in decoupled computers is undertaken in this paper. Decoupled architecture performance is compared to single processors with caches. The memory latency sensitivity of cache based uniprocessors and decoupled systems is studied. Simulations are performed to determine the significance of data caches in a decoupled architecture. It is observed that decoupled architectures can reduce the peak memory bandwidth requirement, but not the total bandwidth, whereas data caches can reduce the total bandwidth by capturing locality. It may be concluded that despite their capability to partially mask the effects of memory latency, decoupled architectures still need a data cache.
Knowledge Representation and Control in Computer Vision Systems
Authors: A. Ravishankar Rao, Ramesh Jain
Venue: IEEE Expert: Intelligent Systems and Their Applications (1988)

The authors analyze the roles of knowledge and control in working computer vision systems, describe model-based vision approaches whereby models serve to expedite scene interpretation by providing expectations for what is likely to be seen, and examine context-free approaches wherein image features are matched against a priori specified-object descriptions. They compare knowledge representation schemes of formal logic, semantic nets, production systems, and frames with respect to procedural and descriptive capability. They discuss control strategies, highlighting issues of parallel vs. sequential control, local vs. global control, distributed vs. centralized control, and top-down vs. bottom-up approaches. The authors develop these concepts within the framework of well-known systems such as Acronym, Hearsay, and VISIONS, providing a review of the major issues in computer vision.
Random Pattern Testability of Delay Faults
Authors: J. Savir, W. H. McAnney
Venue: IEEE Transactions on Computers (1988)

In a computer system, the maximum allowable propagation delay of the combinational logic networks between latches is equal to the interval between the system clocks. The objective of delay testing is to guarantee that the delay of the manufactured network falls within specifications. Here, the capability of random patterns to detect slow paths in combinational logic is analyzed. Formulas that relate the length of the test to the desired test quality are derived.
MCSE Exam Notes: Windows 98
Authors: Rick Sawtell
Venue:  (1998)

:Targeting candidates for the MCSE, this book provides complete information onthe exam objectives--what they need to know to pass the exam.
Upper bounds on the automorphism group of a graph
Authors: Ilia Krasikov, Arieh Lev, Bhalachandra D. Thatte
Venue: Discrete Mathematics (2002)

We give upper bounds on the order of the automorphism group of a simple graph.
Design Validation of Embedded Dependable Systems
Authors: Andrea Bondavalli, Alessandro Fantechi, Diego Latella, Luca Simoncini
Venue: IEEE Micro (2001)

Embedded complex systems require an integrated and best-balanced set of components. To use these components requires some sort of verifiable compositionality, a concept that implies the preservation of properties and the ability to verify them.
An Application of Explanation-Based Learning to Protocol Conformance Testing
Authors: C. Geldrez, S. Matwin, J. Morin, R. L. Probert
Venue: IEEE Expert: Intelligent Systems and Their Applications (1990)

A method that employs a machine learning technique for the semiautomatic generation of protocol-conformance test-sequence requirements is described. Given a protocol knowledge representation and some high-level nonexecutable descriptions of protocol behavior, a learning algorithm based on extended explanation-based generalization produces conformance test-sequence requirements for a protocol implementation under test. The role of learning is to compile relevant parts of protocol knowledge into behaviors, consequently inferring executable protocol behaviors. This inference makes explicit constraints that are implicit in both the protocol knowledge and the behaviors. It is shown that the approach facilitates the derivation of new operational constraints on protocol behavior. The new constraints lead to new types of protocol behavior, thereby yielding potentially valuable new conformance test cases. An application of the method to the Alternating Bit Protocol (ABP) (a canonical example in protocols research literature) is described.
An Inherently Parallel Method for Heuristic Problem-Solving: Part II-Example Applications
Authors: Ira Pramanick, Jon G. Kuhl
Venue: IEEE Transactions on Parallel and Distributed Systems (1995)

This paper presents the application of Parallel Dynamic Interaction (PDI) to three real problem domains: the flow-shop scheduling problem, the job-shop scheduling problem and the vertex cover problem. Specific examples are provided as to how the general PDI framework, introduced in Part I of this paper, can be applied to a particular problem. The results of an empirical study of 90 example instances of these problems indicate that PDI consistently out-performs previously published heuristics for the vertex cover problem, and can typically generate solutions within a few percent of optimal for flow-shop and job-shop problems. Out of the 76 examples for which the optimal solution could be determined, PDI was able to produce results averaging within 4% of optimal. In over 30% of the cases, PDI was able to find the optimal solution. In no case did the PDI solution deviate more than 15% from optimal. It is also seen that the time taken by PDI to arrive at these solutions is negligible compared to that taken by conventional search techniques. This provides strong empirical evidence that PDI is capable of generating high quality solutions to exponentially and super-exponentially hard problems in reasonably short periods of time.
Xtensa: A Configurable and Extensible Processor
Authors: Ricardo E. Gonzalez
Venue: IEEE Micro (2000)

System designers can optimize Xtensa for their embedded application by sizing and selecting features and adding new instructions. Xtensa provides an integrated solution that allows easy customization of both hardware and software. This process is simple, fast, and robust.
Guest Editors' Introduction: Hot Topics at This Year's Design Automation Conference
Authors: David Blaauw, Luciano Lavago
Venue: IEEE Design Test (2002)

The design automation conference is the premier forum for members of the electronic design industry to exchange information on products, methodologies, and processes. Its attendees include more than 15,000 developers, designers, researchers, managers, and engineers from leading electronics companies and universities around the world. With more than 50 exhibitors, DAC offers a robust technical program covering the electronics industry's hottest trends.
Evolution of the reduced density matrix: a generalized projection-operator approach
Authors: Irena Knezevic, David K. Ferry
Venue: Microelectronic Engineering (2002)

A convolutionless equation of motion for the reduced density matrix of a system coupled to its environment, where the system + environment is closed, may be obtained using a projection-operator technique. We show that, when both the system and the environment Hilbert spaces are finite-dimensional, it is possible to eliminate the need for the partial trace over the environment states by constructing a simple and transparent basis-induced isomorphism between the system Liouville space and the unit-eigenspace of a special projection operator. Consequently, an equation of motion for the reduced density matrix is derived by a mere basis transformation within the system + environment Hilbert space and the explicit dependence of the reduced density matrix on the matrix elements of the Hamiltonian is uncovered, in a form well suited for numerical calculation.
Board Test and the Product Life Cycle: Get Wise to Board Test Strategies
Authors: Bernard Sutton
Venue: IEEE Design Test (1999)

Many test strategies exist in the board test world. It would be nice to think that each of these has been honed over many years of study and measured performance to yield the optimal balance of cost, quality,and service required by each enterprise. In reality, most strategies evolve in isolation to satisfy current objectives stemming from market demands. When we look across the many markets for electronic assemblies, we see a whole range of test strategies based on the product's end use. We can speculate on the technical justification for these differences in test strategies, but someone looking from outside our industry would quickly suspect that the product test strategy is related more to the selling price the market attracts than its technical content. It could be argued that the highest technology products attract the highest price because they also require extensive testing. But if this were wholly true, why does a PC motherboard production test strategy differ from a telecommunications switching card? Both use similar component packaging styles and assembly technologies. Both have been sold in the millions globally. Of course, this is an oversimplification of a complex set of problems, especially when we consider the requirement to comply with a whole range of regulations, but it raises issues we should not ignore. The ACM Portal is published by the Association for Computing Machinery. Copyright © 2010 ACM, Inc. Terms of Usage Privacy Policy Code of Ethics Contact Us Useful downloads: Adobe Acrobat QuickTime Windows Media Player Real Player
The Effect of Code Expanding Optimizations on Instruction Cache Design
Authors: W. Y. Chen, P. P. Chang, T. M. Conte, W. W. Hwu
Venue: IEEE Transactions on Computers (1993)

Shows that code expanding optimizations have strong and nonintuitive implications on instruction cache design. Three types of code expanding optimizations are studied in this paper: instruction placement, function inline expansion, and superscalar optimizations. Overall, instruction placement reduces the miss ratio of small caches. Function inline expansion improves the performance for small cache sizes, but degrades the performance of medium caches. Superscalar optimizations increase the miss ratio for all cache sizes. However, they also increase the sequentiality of instruction access so that a simple load forwarding scheme effectively cancels the negative effects. Overall, the authors show that with load forwarding, the three types of code expanding optimizations jointly improve the performance of small caches and have little effect on large caches.
MITI's Real World Computing Program
Authors: David Kahaner
Venue: IEEE Micro (1992)

The Real World Computing (RWC) program (also called the New Information Processing Technology program), a 10-year program sponsored by Japan's Ministry of International Trade and Industry (MITI), is described. The goal of the program is to lay the technological foundations for the information society that Japan anticipates in the next century. The RWC program replaces the Fifth Generation project. The author presents a summary of the draft prepared by the RWC program's Feasibility Study Committee as presented in Tokyo, March 2-3, 1992, at what was called RWC92, the Second NIPT Workshop. MITI expects future information systems to be based on a flexible integration of massively parallel computing, optical computing, neural computing, and logic programming. The Real World Computing program aims to establish theoretical foundations for these technologies, explore applications, and study how they can be integrated.
Color Space Analysis of Mutual Illumination
Authors: B. V. Funt, M. S. Drew
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1993)

Mutual illumination occurs when light reflected from one surface impinges on a second one. The resulting additional illumination incident on the second surface affects both the color and intensity of the light reflected from it. As a consequence, the image of a surface in the presence of mutual illumination differs from what it otherwise would have been in the absence of mutual illumination. Unaccounted for mutual illumination can easily confuse methods that rely on intensity or color such as shape-from-shading or color-based object recognition. In this correspondence, we introduce an algorithm that removes mutual illumination effects from images. The domain is that of previously-segmented images of convex surfaces of uniform color and diffuse reflectance where for each surface the interreflection occurs mainly from one other surface and can be accurately accounted for within a one-bounce model. The algorithm is based on a singular value decomposition of the colors coming from each surface. Geometrical information about where on the surface the colors emanate from is not required. The RGB triples from a single convex surface experiencing interreflection fall in a plane; intersecting the planes generated from two interreflecting surfaces results in a unique interreflection color. Each pixel can then be factored into its interreflection and no-interreflection components so that a complete no-interreflection image is produced.
Handwritten Chinese Radical Recognition Using Nonlinear Active Shape Models
Authors: D. Shi, S. R. Gunn, R. I. Damper
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (2003)

Handwritten Chinese characters can be recognized by first extracting the basic shapes (radicals) of which they are composed. Radicals are described by nonlinear active shape models and optimal parameters found using the chamfer distance transform and a dynamic tunneling algorithm. The radical recognition rate is 96.5 percent correct (writer-independent) on 280,000 characters containing 98 radical classes.
ConClass: A Framework for Real-Time Distributed Knowledge-Based Processing
Authors: H. Maegawa
Venue: IEEE Transactions on Knowledge and Data Engineering (1994)

We have developed a problem-solving framework, called ConClass, that is capable of classifying continuous real-time problems dynamically and concurrently on a distributed system. ConClass provides an efficient development environment for describing and decomposing a classification problem and synthesizing solutions. In ConClass, decomposed concurrent subproblems specified by the application developer effectively correspond to the actual distributed hardware elements. This scheme is useful for designing and implementing efficient distributed processing, making it easier to anticipate and evaluate system behavior. The ConClass system provides an object replication feature that prevents any particular object from being overloaded. In order to deal with an indeterminate amount of problem data, ConClass dynamically creates object networks that justify hypothesized solutions, and thus achieves a dynamic load distribution. A number of efficient execution mechanisms that manage a variety of asynchronous aspects of distributed processing have been implemented without using schedulers or synchronization schemes that are liable to develop bottlenecks. We have confirmed the efficiency of parallel distributed processing and load balancing of ConClass with an experimental application.
Deductive Approximate Reasoning Systems
Authors: R. R. Yager
Venue: IEEE Transactions on Knowledge and Data Engineering (1991)

A formal deductive view for the theory of approximate reasoning, called AR-1, is introduced. A central feature of this framework is the view of propositions as statements involving the assignment of possible values to variables. A unified method for managing joint variables is given. AR-2, which allows for the introduction of probability theory into approximate reasoning, is presented. AR-5, a restrictive version of approximate reasoning, is also introduced.
A Compendium of Continuous Lattices in MIZAR
Authors: Grzegorz Bancerek, Piotr Rudnicki
Venue: Journal of Automated Reasoning (2003)

This paper reports on the MIZAR formalization of the theory of continuous lattices as presented in Gierz et al.: A Compendium of Continuous Lattices, 1980. By a MIZAR formalization we mean a formulation of theorems, definitions, and proofs written in the MIZAR language whose correctness is verified by the MIZAR processor. This effort was originally motivated by the question of whether or not the MIZAR system was sufficiently developed for the task of expressing advanced mathematics. The current state of the formalization &ndash; 57 MIZAR articles written by 16 authors &ndash; indicates that in principle the MIZAR system has successfully met the challenge. To our knowledge it is the most sizable effort aimed at mechanically checking some substantial and relatively recent field of advanced mathematics. However, it does not mean that doing mathematics in MIZAR is as simple as doing mathematics traditionally (if doing mathematics is simple at all). The work of formalizing the material of the Gierz et al. compendium has (i) prompted many improvements of the MIZAR proof checking system, (ii) caused numerous revisions of the the MIZAR data base, and (iii) contributed to the &ldquo;to do&rdquo; list of further changes to the MIZAR system.
A Floating-Point VLSI Chip for the TRON Architecture: An Architecture for Reliable Numerical Programming
Authors: Shumpei Kawasaki, Mitsuru Watabe, Shigeki Morinaga
Venue: IEEE Micro (1989)

A description is given of the Gmicro/FPU (floating-point unit), a chip that provides floating-point instructions for both the Gmicro/200 and the Gmicro/300 microprocessors. The VLSI central-processing-unit architecture, for which it is designed, defines 23 coprocessor instructions, some of which are designed to be used in the floating-point instructions. Some background information is given, and the requirements, architecture, implementation, and evaluation of the Gmicro/FPU are discussed.
Finite-Element Methods for Active Contour Models and Balloons for 2-D and 3-D Images
Authors: L. D. Cohen, I. Cohen
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1993)

The use of energy-minimizing curves, known as "snakes" to extract features of interest in images has been introduced by Kass, Witkin and Terzopoulos (1987). A balloon model was introduced by Cohen (1991) as a way to generalize and solve some of the problems encountered with the original method. A 3-D generalization of the balloon model as a 3-D deformable surface, which evolves in 3-D images, is presented. It is deformed under the action of internal and external forces attracting the surface toward detected edgels by means of an attraction potential. We also show properties of energy-minimizing surfaces concerning their relationship with 3-D edge points. To solve the minimization problem for a surface, two simplified approaches are shown first, defining a 3-D surface as a series of 2-D planar curves. Then, after comparing finite-element method and finite-difference method in the 2-D problem, we solve the 3-D model using the finite-element method yielding greater stability and faster convergence. This model is applied for segmenting magnetic resonance images.
A Comparative Study of Topological Properties of Hypercubes and Star Graphs
Authors: K. Day, A. Tripathi
Venue: IEEE Transactions on Parallel and Distributed Systems (1994)

Undertakes a comparative study of two important interconnection network topologies:the star graph and the hypercube, from the graph theory point of view. Topologicalproperties are derived for the star graph and are compared with the correspondingproperties of the hypercube. Among other results, the authors determine necessary andsufficient conditions for shortest path routing and characterize maximum-sized families of parallel paths between any two nodes of the star graph. These parallel paths are provenof minimum length within a small additive constant. They also define greedy andasymptotically balanced spanning trees to support broadcasting and personalizedcommunication on the star graph. These results confirm the already claimed topologicalsuperiority of the star graph over the hypercube.
Toward Automatic Detection of Software Failures
Authors: Tony Savor, Rudolph E. Seviora
Venue: Computer (1998)

Although much research has been devoted to the automatic detection of hardware failures, relatively little has been done in the software arena. To date, no method has explicitly and cost-effectively dealt with failure detection in software systems whose specifications are nondeterministic. In such systems, the specification permits multiple outputs for the same input sequence and system state. Nondeterminism in specifications is advantageous because the specification writer can avoid stating irrelevant behavior as mandatory, freeing the software designer to choose a behavioral alternative that would yield a more desirable implementation. Unfortunately, this flexibility comes at a cost to the failure-detection mechanism. It must accommodate all the target system's legal behavioral alternatives and avoid favoring one of them. This article describes a hierarchical supervisor, whose failure-detection mechanism explicitly addresses systems with nondeterministic specifications. The supervisor, a unit separate from the target system, observes the system's external inputs and outputs and reports any failures. Its hierarchical structure results from splitting the task of identifying the behavioral alternative the target system chooses from the task of checking the details of system behavior. This structure makes it possible to efficiently trade off detection accuracy and computational cost. A key element is a model, derived from the target system's specification, that prunes behavioral alternatives. To evaluate their approach, the authors created a prototype supervisor and used it to supervise the execution of the control program of a small telephone exchange. Results indicate that the hierarchical supervisor can significantly reduce the computational cost of considering the target system's behavioral alternatives. However, although the supervisor's computational cost is significantly reduced, it is still higher than that for the target system.
Efficient algorithms for isomorphisms of simple types
Authors: Yoav Zibin, Joseph (Yossi) Gil, Jeffrey Considine
Venue: ACM SIGPLAN Notices (2003)

The first order isomorphism problem is to decide whether two non-recursive types using product- and function-type constructors, are isomorphic under the axioms of commutative and associative products, and currying and distributivity of functions over products. We show that this problem can be solved in O(n log2 n) time and O(n) space, where is n the input size. This result improves upon the O(n log2 n) time and O(n2) space bounds of the best previous algorithm. We also describe an O(n) time algorithm for the linear isomorphism problem, which does not include the distributive axiom, whereby improving upon the O(n log n) time of the best previous algorithm for this problem.