ppxscal/embedding_network huggingface dataset:
Coming to Grips with RSS Feeds and Standards
Authors: George Semeczko
Venue: IEEE Distributed Systems Online (2007)

A review of Developing Feeds with RSS and Atom by Ben Hammersley
Cost-based scheduling for data-intensive applications on global grids
Authors: S. Venugopal, R. Buyya
Venue: Proceedings of the High Performance Distributed Computing, 2005. HPDC-14. Proceedings. 14th IEEE International Symposium (2005)

We present an algorithm for scheduling distributed data intensive bag-of-task applications on data grids that have costs associated with requesting, transferring and processing datasets. We evaluate the algorithm on a data grid testbed and present the results.
Real-Time Divisible Load Scheduling with Different Processor Available Times
Authors: Xuan Lin, Ying Lu, Jitender Deogun, Steve Goddard
Venue: Proceedings of the 2007 International Conference on Parallel Processing (2007)

Providing QoS and performance guarantees to arbitrarily divisible loads has become a significant problem for many cluster-based research computing facilities. While progress is being made in scheduling arbitrarily divisible loads, some of proposed approaches may cause Inserted Idle Times (IITs) that are detrimental to system performance. In this paper we propose a new approach that utilizes IITs and thus enhances the system performance. The novelty of our approach is that, to simplify the analysis, a homogenous system with IITs is transformed to an equivalent heterogeneous system, and that our algorithms can schedule real-time divisible loads with different processor available times. Intensive simulations show that the new approach outperforms the previous approach in all configurations. We also compare the performance of our algorithm to the current practice of manually splitting workloads by users. Simulation results validate the advantages of our approach.
An Efficient Method of Genetic Algorithm for Text Clustering Based on Singular Value Decomposition
Authors: Wei Song, Soon Cheol Park
Venue: Proceedings of the 7th IEEE International Conference on Computer and Information Technology (2007)

In this paper, we propose a method of genetic algorithm (GA) for text clustering based on singular value decomposition technique. The main difficulty in the application of GA to text clustering is its long string representation in high dimensional space. Because the most straightforward and popular approach represents texts with vector space model (VSM), that is, each unique term in the vocabulary represents one dimension. Singular value decomposition (SVD) is a successful technique arising from numerical linear algebra that is used in latent semantic indexing (LSI). Employing the SVD-based document representation, LSI can overcome the problems by using statistically derived conceptual indices instead of individual words and provide a dimension reduced space. Genetic algorithm belongs to search techniques which could automatically exploit the optimal solution for objective or fitness function of an optimization problem. GA can be used in conjunction with the reduced latent semantic structure and improve clustering efficiency and accuracy. Our algorithm is performed on Reuter documents collection. The results show that the performance of SVD-based GA is significantly superior to that of conventional GA in vector space model.
How robust are gossip-based communication protocols?
Authors: Lorenzo Alvisi, Jeroen Doumen, Rachid Guerraoui, Boris Koldehofe, Harry Li, Robbert van Renesse, Gilles Tredan
Venue: ACM SIGOPS Operating Systems Review (2007)

Gossip-based communication protocols are often touted as being robust. Not surprisingly, such a claim relies on assumptions under which gossip protocols are supposed to operate. In this paper, we discuss and in some cases expose some of these assumptions and discuss how sensitive the robustness of gossip is to these assumptions. This analysis gives rise to a collection of new research challenges.
A Universal Cellular Array
Authors: Jung-Chang Huang
Venue: IEEE Transactions on Computers (1971)

A new type of fixed-cell fixed-interconnection homogeneous cellular array that is capable of realizing any switching network is developed. The array is composed of identical combinational logic cells with three inputs and three outputs. The logic cells are arranged in a rectangular array with uniform interconnection structure. The signal flow is unilateral in the vertical direction and bilateral in the horizontal direction. Each n-column array is capable of realizing any set of n functions of n variables. The functional capabilities of the array can be changed by appropriately setting the parameters on the edges of the array. Algorithms for the realization of a set of n functions of n variables by using this type of array are presented.
Securing More Registers with Reduced Instruction Encoding Architectures
Authors: Je-Hyung Lee, Jinpyo Park, Soo-Mook Moon
Venue: Proceedings of the 13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (2007)

One of the most serious constraints of an embedded system is its limited memory, which requires small code size for embedded software. One popular method to reduce the code size is reducing the instruction encoding, such as the ARM THUMB or the MIPS-16 architectures. They employ shorter instructions by reducing the field width, including those of register operands. This obviously reduces the number of registers available for register allocation than in the original architecture, which can lead to more register spills, negatively affecting the code size. This paper proposes a simple architectural upgrade by reconstructing the original register file into register banks and by providing a bank change instruction. This can allow all of the original registers to be available for register allocation when the bank change instructions are added appropriately. For such a banked register file, we propose an efficient, region-based register bank allocation technique where appropriate regions are chosen first for bank changes, followed by conventional global register allocation. As a case study, we apply the idea to the ARM THUMB architecture and evaluate how the upgrade affects its overall code size. We found that the upgrade results in an average of 5.0% code size reduction for some of MiBench and MediaBench benchmarks, compared to the original THUMB code.
A P2P Architecture for Large-scale VoD Service
Authors: Ai Wu, Lianhai Yuan, Xinsong Liu, Kejian Liu
Venue: Proceedings of the Eighth ACIS International Conference on Software Engineering, Artificial Intelligence, Networking, and Parallel/Distributed Computing - Volume 03 (2007)

Scalability and reliability are essential to VoD, a peer-to-peer based VoD architecture (RSVoD) is proposed in this paper. In the proposed architecture, assignable-size user buffer, algorithms of parents selection and subtree migration are employed to ensure the reliability and scalability of system, finis avalanche problem is discussed also. The attributes and performance of RSVoD are analyzed in theory. Performance studies based on simulations are carried out also, and the results show that the presented architecture outperforms recently proposed similar architectures in a number of important performance metrics, such as the server stress, reliability, service capacity, time of failure, and so on.
A component-based architecture for power-efficient media access control in wireless sensor networks
Authors: Kevin Klues, Gregory Hackmann, Octav Chipara, Chenyang Lu
Venue: Proceedings of the 5th international conference on Embedded networked sensor systems (2007)

The diverse requirements of wireless sensor network applications necessitate the development of multiple media access control (MAC) protocols to meet their varying throughput, latency, and network lifetime needs. Building new MAC protocols has proven to be extremely difficult, however, given the monolithic nature of existing protocol implementations as well as their dependence on a particular radio or processor platform. To address these issues, we propose the MAC Layer Architecture (MLA), a component-based architecture for power-efficient MAC protocol development in wireless sensor networks. MLA consists of optimized, reusable components that implement a common set of features shared by existing MAC protocols, as well as abstractions that encapsulate the intricacies of the hardware platforms they run on. Through an instantiation of MLA in TinyOS 2.0.1, we have implemented five representative MAC protocols. Empirical results show that MLA results in significant code reuse among different protocols, while achieving comparative performance and memory footprints to monolithic implementations of the same protocols.
Using Contour Analysis to Improve Feature Extraction in Thai Handwritten Character Recognition Systems
Authors: Jarernsri L. Mitrpanont, Urairat Limkonglap
Venue: Proceedings of the 7th IEEE International Conference on Computer and Information Technology (2007)

This research proposes an approach to the analysis of contour characteristics for the feature extraction process of an off-line Thai handwritten character recognition system (THW-CR). The system aims at increasing the accuracy of both feature extraction rate and character recognition rate. We introduce the contour to capture the movement of features. The propose modules are the feature representation and the feature conflict resolution rules. With our proposed approach, the experiment shows the results increase reasonably. The maximum Feature Extraction Rate (FER) reached 97.73%. Meanwhile, the highest Character Recognition Rate (CRR) reached 95.35%. Additionally, the result of the overall evaluation showed that the THW-CR system generated reliable results for improving the accuracy of the feature extraction rate and the character recognition rate compared with the previous research by 3.62% and 8.33%, respectively.
The Design and Optimization of H.264 Encoder Based on the Nexperia Platform
Authors: Li Zhengdong, Zeng Xianwen, Yin Zhongcheng, Hu Shaobin, Wang Lei
Venue: Proceedings of the Eighth ACIS International Conference on Software Engineering, Artificial Intelligence, Networking, and Parallel/Distributed Computing - Volume 01 (2007)

The Nexperia PNX1501 Media Processor is a complete Audio/Video/Graphics system on a chip that contains a high-performance 32-bit VLIW processor, capable of high quality software video, audio signal processing. Based on Philips Semiconductor's multimedia processing chip Nexperia PNX1501, designs a new H.264 encoder with high performance for real time signal processing. Chooses the rapid integral discrete cosine translation and the advanced Hexagon searching algorithm, accomplishes the intelligent optimization and comprehensive debugging for codes. The results of experiments indicate that the encoder can encode all kinds of video data rapidly, and can realize the real time processing for all kinds of video signals.
Embedded System Design for Automotive Applications
Authors: Alberto Sangiovanni-Vincentelli, Marco Di Natale
Venue: Computer (2007)

To optimize the system design and allow for plug-and-play of subsystems, automotive electronic system architecture evaluation and development must be supported with a robust design flow based on virtual platforms.
A Novel Time-Delay Recurrent Neural Network and Application for Identifying and Controlling Nonlinear Systems
Authors: Hongwei Ge, Wenli Du, Feng Qian, Yanchun Liang
Venue: Proceedings of the Third International Conference on Natural Computation - Volume 01 (2007)

A time-delay recurrent neural network (TDRNN) model is proposed. TDRNN has a simple structure but far more "depth" and "resolution ratio" in memory by introducing the time-delay and recurrent mechanism. A dynamic recurrent back propagation algorithm is developed. The optimal adaptive learning rates are derived in the sense of discrete-type Lyapunov stability to guarantee the fast convergence of the proposed model. More specifically, a TDRNN identifier and a TDRNN controller are utilized for identifying and controlling nonlinear systems. Numerical experiments show that the TDRNN has good effectiveness in the identification and control for dynamic systems.
Wavelet Packet Transform Based Minimum Risk Denoising Algorithm for Astronomical Spectra
Authors: Jingchang Pan, Qiang Guo, Bin Jiang, Zhenping Yi
Venue: Proceedings of the Fourth International Conference on Fuzzy Systems and Knowledge Discovery - Volume 04 (2007)

The purpose of spectra denoising is to reduce the effect of noise on finding astrophysical information hidden in spectra. Various denoising approaches exist, in which wavelet transform is important. In this paper, denoising algorithms using wavelet transform is discussed and wavelet packet transform based on minimum risk denoising algorithm is presented. Experimental results show that the method produces precise estimation of spectra.
The Specification of Assemblers
Authors: J. M. Spitzen
Venue: IEEE Transactions on Software Engineering (1976)

The problem of applying formal techniques of program specification and verification to large complex programs is considered. It is argued that a practical solution requires a variety of techniques, including both procedural and nonprocedural specifications, hierarchical program organization, and the use of program transformations. In particular, a case is made for flexible problem-oriented choice of specification techniques and languages. These ideas are expanded by specifying a load-and-go assembler in three parts: a transduction grammar describing the correspondence between concrete and abstract syntax for assembly language programs; a set of transformations of the abstract form; and a nonconstructive axiomatic specification of the result of core assembly and loading of transformed abstract programs.
The effect of process variation on device temperature in FinFET circuits
Authors: Jung Hwan Choi, Jayathi Murthy, Kaushik Roy
Venue: Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design (2007)

With technology scaling, devices are increasingly prone to process variations. These variations cause a large spread in leakage power, since it is extremely sensitive to process variations, which in turn results in larger temperature variations across different dies. In this paper, we investigate the temperature variations in FinFET circuits considering variations in following parameters (i) channel length and (ii) body thickness. We estimate temperature variation under process fluctuation by Monte Carlo simulation with thermal models to solve temperature and leakage power self-consistently. The results show that high activity circuits exhibit larger temperature variations since increased temperature increments leakage power and vice versa. It is also shown that under moderate process variation (3&sigma;=10% for channel length and body thickness) and a nominal primary input activity of 0.4, thermal runaway can occur in more than 15% of chips in 28nm FinFET technology, severely degrading manufacturing yield.
Implementation of an Audio Watermarking System Using CDMA Modulations
Authors: Said Ghnimi, Adnen Cherif
Venue: Proceedings of the 7th IEEE International Conference on Computer and Information Technology (2007)

In this paper, we will present an audio watermarking system based on CDMA modulations. After having presented the watermarking structure and the configuration, we will develop the numerical implementation of our interface programmed under Matlab. Validation tests are conducted and affected in real time acquisition for the verification of the watermarking system performances and the robustness.
Workshop Report: Software Quality Assurance Standards Under Development
Authors: P. Rosengard
Venue: Computer (1979)

Definitions and processes related to software quality must be standardized, according to most participants in the recent ACM Software Quality Assurance Workshop. The need for such standards will become even more apparent over the next five to eight years, since the Department of Defense is expected to require their use for software acquisition. The ACM Portal is published by the Association for Computing Machinery. Copyright © 2010 ACM, Inc. Terms of Usage Privacy Policy Code of Ethics Contact Us Useful downloads: Adobe Acrobat QuickTime Windows Media Player Real Player
A markov chain framework for the simple genetic algorithm
Authors: Thomas E. Davis, Jose C. Principe
Venue: Evolutionary Computation (1993)

This paper develops a theoretical framework for the simple genetic algorithm (combinations of the reproduction, mutation, and crossover operators) based on the asymptotic state behavior of a nonstationary Markov chain algorithm model. The methodology borrows heavily from that of simulated annealing. We prove the existence of a unique asymptotic probability distribution (stationary distribution) for the Markov chain when the mutation probability is used with any constant nonzero probability value. We develop a Cramer's Rule representation of the stationary distribution components for all nonzero mutation probability values and then extend the representation to show that the stationary distribution possesses a zero mutation probability limit. Finally, we present a strong ergodicity bound on the mutation probability sequence that ensures that the nonstationary algorithm (which results from varying mutation probability during algorithm execution) achieves the limit distribution asymptotically. Although the focus of this work is on a nonstationary algorithm in which mutation probability is reduced asymptotically to zero via a schedule (in a fashion analogous to simulated annealing), the stationary distribution results (existence, Cramer's Rule representation, and zero mutation probability limit) are directly applicable to conventional, simple genetic algorithm implementations as well.
Multimodal function optimization using minimal representation size clustering and its application to planning multipaths
Authors: Cem Hocaoğlu, Arthur C. Sanderson
Venue: Evolutionary Computation (1997)

A novel genetic algorithm (GA) using minimal representation size cluster (MRSC) analysis is designed and implemented for solving multimodal function optimization problems. The problem of multimodal function optimization is framed within a hypothesize-and-test paradigm using minimal representation size (minimal complexity) for species formation and a GA. A multiple-population GA is developed to identify different species. The number of populations, thus the number of different species, is determined by the minimal representation size criterion. Therefore, the proposed algorithm reveals the unknown structure of the multimodal function when a priori knowledge about the function is unknown. The effectiveness of the algorithm is demonstrated on a number of multimodal test functions. The proposed scheme results in a highly parallel algorithm for finding multiple local minima. In this paper, a path-planning algorithm is also developed based on the MRSC-GA algorithm. The algorithm utilizes MRSC_GA for planning paths for mobile robots, piano-mover problems, and N-link manipulators. The MRSC_GA is used for generating multipaths to provide alternative solutions to the path-planning problem. The generation of alternative solutions is especially important for planning paths in dynamic environments. A novel iterative multiresolution path representation is used as a basis for the GA coding. The effectiveness of the algorithm is demonstrated on a number of two-dimensional path-planning problems.
The generalized dependency degree between attributes
Authors: Haixuan Yang, Irwin King, Michael R. Lyu
Venue: Journal of the American Society for Information Science and Technology (2007)

Inspired by the dependency degree &gamma;, a traditional measure in Rough Set Theory, we propose a generalized dependency degree, &Gamma;, between two given sets of attributes, which counts both deterministic and indeterministic rules while &gamma; counts only deterministic rules. We first give its definition in terms of equivalence relations and then interpret it in terms of minimal rules, and further describe the algorithm for its computation. To understand &Gamma; better, we investigate its various properties. We further extend &Gamma; to incomplete information systems. To show its advantage, we make a comparative study with the conditional entropy and &gamma; in a number of experiments. Experimental results show that the speed of the new C4.5 using &Gamma; is greatly improved when compared with the original C4.5R8 using conditional entropy, while the prediction accuracy and tree size of the new C4.5 are comparable with the original one. Moreover, &Gamma; achieves better results on attribute selection than &gamma;. The study shows that the generalized dependency degree is an informative measure in decision trees and in attribute selection. &copy; 2007 Wiley Periodicals, Inc.
A Rough CP Neural Network Model Based on Rough Set
Authors: Min Dong, HuiYu Jiang, XiangPeng Li
Venue: Proceedings of the Third International Conference on Natural Computation - Volume 01 (2007)

Aiming at the problem that the Counter Propagation Network (CPN) can not make good use of nerve cells, a rough CP Neural Network Model based on Rough Set is proposed. It changes the strategy of winning as the king, and decides output values to use Rough Member Function, which expresses the level of an element subordinated to a set. Experiments show that the approach can solve some problems in other neural Networks, for example, sample size and quality. They would directly influence the accuracy. While reducing training time, the prediction precision of the network can be greatly improved.
Every Finite-State Machine can be Simulated (Realized) by a Synchronous (Asynchronous) Binary Feedback Shift-Register Machine
Authors: L. S. Levy
Venue: IEEE Transactions on Computers (1974)

A theoretical model of a microprogram unit is formulated, and the relationship of this model to a form of feedback shift register is developed. The feedback shift-register machine variant has synchronous and asynchronous prototypes. The asynchronous binary feedback shift-register machines realize every fundamental mode asynchronous sequential (finite-state) machine. The synchronous feedback shift-register machine differs from the standard definition by the addition of transitional states to the usual (nontransitional) states, and a single step in the simulation is a move between nontransitional states. When synchronous feedback shift-register machines are generalized in this way, they also become universal components capable of simulating ali finite-state machines.
User identification based on game-play activity patterns
Authors: Kuan-Ta Chen, Li-Wen Hong
Venue: Proceedings of the 6th ACM SIGCOMM workshop on Network and system support for games (2007)

Account hijacking is considered one of the most serious security problems in online games. A hijacker normally takes away valuable virtual items from the stolen accounts, and trades those items for real money. Even though account hijacking is not uncommon, there is currently no general solutions to determine whether an account has been hijacked. The game company is not aware of a hijack unless it is reported by the victim. However, it is usually too late---usually a hijacker already took away anything valuable when a user finds that his/her account has been stolen. In this paper, we propose a new biometric for human identification based on users' game-play activities. Our main summary are two-fold: 1) we show that the idle time distribution is a representative feature of game players; 2) we propose the RET scheme, which is based on the KullbackLeibler divergence between idle time distributions, for user identification. Our evaluations shows that the RET scheme achieves higher than 90% accuracy with a 20-minute detection time given a 200-minute history size.