ppxscal/embedding_network huggingface dataset:
Hardware protection against software piracy
Authors: Tim Maude, Derwent Maude
Venue: Communications of the ACM (1984)

A system that prevents illicit duplication of proprietary software is suggested. It entails the customization of the programs for each computer by encryption. The use of a public key cryptogram for this purpose means that anyone can customize programs, but neither other programmers nor the people having complete access to the target computer can obtain copies that will run on other machines. A possible implementation of the system is considered in some detail. It is based on a hardware security unit that is attached to the computer and that decrypts and obeys some parts of the program.
Another use of FORTRAN II chaining
Authors: D. G. Drath
Venue: Communications of the ACM (1964)

The letter by Ackermann appearing in the Communications of the ACM of May 1964, presented one of a number of the very interesting uses of the FORTRAN II CHAIN procedure. Another unusual application of this procedure has been used by some at Lockheed Missiles Space Company for realizing a very efficient program library tape. The ACM Portal is published by the Association for Computing Machinery. Copyright © 2010 ACM, Inc. Terms of Usage Privacy Policy Code of Ethics Contact Us Useful downloads: Adobe Acrobat QuickTime Windows Media Player Real Player
Integrating parallel file I/O and database support for high-performance scientific data management
Authors: Jaechun No, Rajeev Thakur, Alok Choudhary
Venue: Proceedings of the 2000 ACM/IEEE conference on Supercomputing (CDROM) (2000)

Many scientific applications have large I/O requirements, in terms of both the size of data and the number of files or data sets. Management, storage, efficient access, and analysis of these data present an extremely challenging task. Traditionally, two different solutions are used for this problem: file I/O or databases. File I/O can provide high performance but is tedious to use with large numbers of files and large and complex data sets. Databases can be convenient, flexible, and powerful but do not perform and scale well for parallel supercomputing applications. We have developed a software system, called Scientific Data Manager (SDM), which aims to combine the good features of both file I/O and databases. SDM provides a high-level API to the user and, internally, uses a parallel file system to store real data and a database to store appreciation-related metadata. SDM takes advantage of various I/O optimizations available in MPI-IO, such as collective I/O and noncontiguous requests, in a manner that is transparent to the user. As a result, users can write and retrieve data with the performance of parallel file I/O, without having to bother with the details of actually performing file I/O. In this paper, we describe the design and implementation of SDM. With the help of two parallel application templates, ASTRO3D and an Euler solver, we illustrate how some of the design criteria affect performance.
A Fast and Accurate Method of Redesigning Analog Subcircuits for Technology Scaling
Authors: Seiji Funaba, Akihiro Kitagawa, Toshiro Tsukada, Goichi Yokomizo
Venue: Analog Integrated Circuits and Signal Processing (2000)

In this paper, we present an efficient approach for technology scaling of MOS analog circuits by using circuit optimization techniques. Our new method is based on matching equivalent circuit parameters between a previously designed circuit and the circuit undergoing redesign. This method has been applied to a MOS operational amplifier. We were able to produce a redesigned circuit with almost the same performance in under 4 h, making this method 5 times more efficient than conventional methods.
Generating spatiotemporal datasets on the WWW
Authors: Yannis Theodoridis, Mario A. Nascimento
Venue: ACM SIGMOD Record (2000)

Efficient storage, indexing and retrieval of time-evolving spatial data are some of the tasks that a Spatiotemporal Database Management System (STDBMS) must support. Aiming at designers of indexing methods and access structures, in this article we review the GSTD algorithm for generating spatiotemporal datasets according to several user-defined parameters, and introduce a WWW-based environment for generating and visualizing such datasets. The GSTD interface is available at two main sites: http://www.cti.gr/RD3/GSTD/ and http://www.cs.ualberta.ca/~mn/GSTD/.
A code for non-numeric information processing applications in online systems
Authors: Edward Morenoff, John B. McLean
Venue: Communications of the ACM (1967)

A code has been specifically designed to simplify the internal information processing operations within an online computer system with respect to non-numeric applications, and to maximize the transfer rate of the information channel linking the system and the system user. The code has direct application to problems in areas such as information retrieval, document classification, computer-aided teaching and text editing. This code, called IPC (Information Processing Code), is an 8-bit code set constructed so that 7, 6, 5 and 4-bit subsets can be easily derived from the basic set. The code set is organized so that simple binary operations can distinguish between the numeric alphabetic, special symbol and control character codes. The number of useable characters within the basic set size may be expanded either by use of escape codes included in the set, or by suitable interpretation of otherwise unassigned codes on the basis of the requirements of local environments.
Security defects in CCITT recommendation X.509: the directory authentication framework
Authors: Collin I'Anson, Chris Mitchell
Venue: ACM SIGCOMM Computer Communication Review (1990)

Security defects to be found in C.C.I.T.T. Recommendation X.509-1988 are described together with possible solutions.
Convex hulls of finite sets of points in two and three dimensions
Authors: F. P. Preparata, S. J. Hong
Venue: Communications of the ACM (1977)

The convex hulls of sets of n points in two and three dimensions can be determined with O(n log n) operations. The presented algorithms use the &ldquo;divide and conquer&rdquo; technique and recursively apply a merge procedure for two nonintersecting convex hulls. Since any convex hull algorithm requires at least O(n log n) operations, the time complexity of the proposed algorithms is optimal within a multiplicative constant.
A Multilinear Singular Value Decomposition
Authors: Lieven De Lathauwer, Bart De Moor, Joos Vandewalle
Venue: SIAM Journal on Matrix Analysis and Applications (2000)

We discuss a multilinear generalization of the singular value decomposition. There is a strong analogy between several properties of the matrix and the higher-order tensor decomposition; uniqueness, link with the matrix eigenvalue decomposition, first-order perturbation effects, etc., are analyzed. We investigate how tensor symmetries affect the decomposition and propose a multilinear generalization of the symmetric eigenvalue decomposition for pair-wise symmetric tensors.
DISCOVERing the impact of reality (poster session)
Authors: Susan Turner, Phil Turner Liisa Dawson, Alan Munro
Venue: Proceedings of the third international conference on Collaborative virtual environments (2000)

In this poster paper, we introduce the DISCOVER project, which is developing a CVE for teams to practice managing emergencies in offshore and maritime domains. Many factors constrain design in such contexts. Here we describe just one of them, the need for a particularly convincing sense of reality, and hence the lack of scope for 'magical' devices to support navigation and awareness. We outline the research and design challenges which this entails.
A practical interprocedural data flow analysis algorithm
Authors: Jeffrey M. Barth
Venue: Communications of the ACM (1978)

A new interprocedural data flow analysis algorithm is presented and analyzed. The algorithm associates with each procedure in a program information about which variables may be modified, which may be used, and which are possibly preserved by a call on the procedure, and all of its subcalls. The algorithm is sufficiently powerful to be used on recursive programs and to deal with the sharing of variables which arises through reference parameters. The algorithm is unique in that it can compute all of this information in a single pass, not requiring a prepass to compute calling relationships or sharing patterns. The algorithm is asymptotically optimal in time complexity. It has been implemented and is practical even on programs which are quite large.
Randomized shared queues
Authors: Hyunyoung Lee, Jennifer L. Welch
Venue: Proceedings of the twentieth annual ACM symposium on Principles of distributed computing (2001)

This paper presents a specification of a randomized shared queue that can lose some elements or return them out of order (not in FIFO), shows that the specification can be implemented over the probabilistic quorum algorithm of [4, 3], and analyzes the behavior of this implementation. Distributed algorithms that can tolerate some lost and out-of-order messages are candidates for replacing the message queues with random queues. The modified algorithms will inherit positive attributes concerning load and availability from the underlying queue implementation. The behavior of an application &mdash; a class of combinatorial optimization algorithms &mdash; when it is implemented using random queues is analyzed.
Teraflops Supercomputer: Architecture and Validation of the Fault Tolerance Mechanisms
Authors: Cristian Constantinescu
Venue: IEEE Transactions on Computers (2000)

Intel Corporation developed the Teraflops supercomputer for the US Department of Energy (DOE) as part of the Accelerated Strategic Computing Initiative (ASCI). This is the most powerful computing machine available today, performing over two trillion floating point operations per second with the aid of more than 9,000 Intel processors. The Teraflops machine employs complex hardware and software fault/error handling mechanisms for complying with DOE's reliability requirements. This paper gives a brief description of the system architecture and presents the validation of the fault tolerance mechanisms. Physical fault injection at the IC pin level was used for validation purposes. An original approach was developed for assessing signal sensitivity to transient faults and the effectiveness of the fault/error handling mechanisms. Dependency between fault/error detection coverage and fault duration was also determined. Fault injection experiments unveiled several malfunctions at the hardware, firmware, and software levels. The supercomputer performed according to the DOE requirements after corrective actions were implemented. The fault injection approach presented in this paper can be used for validation of any fault-tolerant or highly available computing system.
Sublinear time approximate clustering
Authors: Nina Mishra, Dan Oblinger, Leonard Pitt
Venue: Proceedings of the twelfth annual ACM-SIAM symposium on Discrete algorithms (2001)

Clustering is of central importance in a number of disciplines including Machine Learning, Statistics, and Data Mining. This paper has two foci: (1) It describes how existing algorithms for clustering can benefit from simple sampling techniques arising from work in statistics [Pol84]. (2) It motivates and introduces a new model of clustering that is in the spirit of the &ldquo;PAC (probably approximately correct)&rdquo; learning model, and gives examples of efficient PAC-clustering algorithms.
Optimal Processor Mapping for Linear-Complement Communication on Hypercubes
Authors: Yomin Hou, Chien-Min Wang, Chiu-Yu Ku, Lih-Hsing Hsu
Venue: IEEE Transactions on Parallel and Distributed Systems (2001)

In this paper, we address the problem of minimizing channel contention of linear-complement communication on wormhole-routed hypercubes. Our research reveals that, for traditional routing algorithms, the degree of channel contention of a linear-complement communication can be quite large. To solve this problem, we propose an alternative approach, which applies processor reordering mapping at compile time. In this compiler approach, processors are logically reordered according to the given communication(s) so that the new communication(s) can be efficiently realized on the hypercube network. It is proved that, for any linear-complement communication, there exists a reordering mapping such that the new communication has minimum channel contention. An $O(n^3)$ algorithm is proposed to find such a mapping for an $n \hbox {-} {\rm dimensional}$ hypercube. An algorithm based on dynamic programming is also proposed to find an optimal reordering mapping for a set of linear-complement communications. Several computer simulations have been conducted and the results clearly show the advantage of the proposed approach.
An effective low powr design methodology based on interconnect prediction
Authors: Shih-Hsu Huang
Venue: Proceedings of the 2001 international workshop on System-level interconnect prediction (2001)

The demand for low power digital systems has motivated significant research. However, the power estimation at the logic level is a difficult task because interconnect plays a role in determining the total chip power dissipation. As a result, the power optimization at the logic level may be inaccurate due to the lack of physical place and route information. In this paper, we will present an effective low power design methodology based on interconnect prediction at the logic level. The proposed design methodology includes the method to create wire load models and the design procedures to select the appropriate wire load model during synthesis. The main distinction of the proposed approach is that it constructs physical hierarchy during the synthesis stage. By taking advantage of wire load models, the proposed design methodology is able to develop low power digital systems while speeding up the design process. Experimental data shows that this design methodology achieved very good results.
Treating computer science as science as: An experiment with sorting (poster session)
Authors: Cary Laxer
Venue: ACM SIGCSE Bulletin (2001)

When I teach sorting algorithms in our introductory computer science class, I always wonder how I can convince the students of the efficiency of &Ogr; (n log n) sorts, and their complex code, vs. the ease of writing &Ogr; (n2) sorts. With today's personal computers, even bubble sorting an array of a few thousand items appears to occur instantaneously. In addition, most textbooks provide the program code for implementing most of the standard sorting algorithms, such as bubble sort, selection sort, and quick sort. Since our introductory course has a closed lab period each week, I looked for something to do with my students when it came to sorting. Making them type in the code that was in the book seemed a waste of time.
Telehealth in the Pacific: Current Status and Analysis Report (1999&ndash;2000)
Authors: Isao Nakajima
Venue: Journal of Medical Systems (2000)

From the summer of 1999 to the spring of 2000, we undertook an on-site investigation of the management and operational status of telehealth in the Pacific. The writers also gathered additional materials upon returning to Japan to provide as detailed a report as possible on the current status and analysis of telemedicine in the Pacific. Following the collapse of the Soviet Union, various regions around the world has sought a gentler alternative to &ldquo;deterrence by arms.&rdquo; The writers of this paper believe one such means is telemedicine. We believe telemedicine services may help offset the emotional stress and sense of inequality experienced by &ldquo;islanders and civilians living around military bases,&rdquo; which the financial benefits of the so-called &ldquo;base-economy&rdquo; alone has never been able to remedy. There are numerous medical support activities currently operating in the Pacific region, and telecommunications is the most effective tool for connecting and unifying such a vast region. We believe that projects for this region must have a clear focus and objective and be able to demonstrate concrete results in order to win subsidies or aid.
Practical logic synthesis for CPLDs and FPGAs with PLA-style logic blocks
Authors: Kenneth Yan
Venue: Proceedings of the 2001 Asia and South Pacific Design Automation Conference (2001)

In some modern FPGAs and CPLDs, PLA(programmable logic array)-style logic blocks can be used as the storage elements for improved logic density and performance. PLA-style logic blocks were originally deployed in the early PLDs. Due to recent research developments in the FPGA community such as [6] and [4], PLA-style logic blocks are becoming an effective storage alternative in FPGAs. This paper presents an approach with clustering and functional decomposition to implement the circuits using the minimum number of PLA-style logic blocks. One important feature is that it simultaneously considers the routing resource reduction for better circuit performance after place-and-route. In order to effectively use PLA-style logic blocks in large clusters, functional decompositions are used to decompose large clusters so that the encoding functions and base functions can be mapped into PLA-blocks. Furthermore, implicit representation[5] of the crucial steps in the functional decomposition is used to consider 1) number of inputs, 2) number of product terms. 3) number of outputs required for the PLA-block synthesis. We have developed an algorithm called PLA_SynT that can be used in the logic synthesis flow for CPLDs and FPGAs with PLA-blocks. MCNC benchmarks are used to test PLA_SynT and the experimental results are compared with TEMPLA[1]. PLA_SynT shows 10.24% improvement over TEMPLA[1], in terms of the number of PLA-blocks needed to implement the circuit. PLA_SynT also shows 14.41% improvement over EMB_Syn[3] in circuit performances while maintaining comparable circuit areas.
Foreign body sarcoma: effects of foreign DNA, \beta-carotene and paprika applied to the implant surface
Authors: S. M. Lavelle, Maura Mhic Iomhair
Venue: Technology and Health Care (2000)

Sarcoma arises extremely rarely on foreign bodies in man, but is aggressive and often lethal. A coating for implants which would further reduce the risk in man is desirable. The incidence in mice is much greater, and responds to chemical treatment of the implant surface. Coating with histones increases tumour yield. Accordingly, related substances, foreign DNA, DNase and a mixture of the two, were tested for anticancer activity by application to 25 mm nitrocellulose filters in groups of 30--45 BALB/c mice, in comparison with untreated filters. Other substances reported to influence neoplasia, paprika, \beta-carotene, rhodamine and tuftsin; and substances expected to be neutral, oxyprenolol, liquid paraffin, iodine, and adenosine diphosphate were similarly tested against concurrent untreated controls for comparison. Bovine DNA (p=0.01) and DNA/DNase mixture (p=0.04) and DNase fomented tumour growth by 55, 45 and 59% The other substances were inert. None were candidates for an anti-sarcoma coating.
Government, industry, and academia: Teaming to design high confidence information security applications
Authors: W. B. Martin, P. D. White, W. M. Vanfleet
Venue: Proceedings of the third workshop on Formal methods in software practice (2000)

A trusted computing base requires true separation of processes. Modern approaches relegate separation to a component of the operating system called the kernel. Although the kernel represents only a small portion of the code of the entire operating system, it is among the most intensively used portions. With separation as the focus, this paper will describe a kernel that provides strict separation between processes, allowing for the remainder of the operating system, residing outside the kernel, to run only as processes in user mode under control of the kernel. The kernel is therefore tasked with implementing the critical operating system functions of providing access to resources, communications between processes, and scheduling of process threads. Strict separation between processes enables the evaluation of a system to check that the system meets its security policy. It is to this end that the Department of Defense in conjunction with Motorola Space and Systems Technology Group outlined the development of a separation kernel with the use of the correct by construction methodology supported by the Specware system under development at Kestrel Institute. Since the initial prototype of the kernel, Motorola has extended and incorporated this separation kernel design into their smart card and cryptographic processor technologies.
Implementing an on-the-fly garbage collector for Java
Authors: Tamar Domani, Elliot K. Kolodner, Ethan Lewis, Eliot E. Salant, Katherine Barabash, Itai Lahan Yossi Levanoni, Erez Petrank
Venue: Proceedings of the 2nd international symposium on Memory management (2000)

Java uses garbage collection (GC) for the automatic reclamation of computer memory no longer required by a running application. GC implementations for Java Virtual Machines (JVM) are typically designed for single processor machines, and do not necessarily perform well for a server program with many threads running on a multiprocessor. We designed and implemented an on-the-fly GC, based on the algorithm of Doligez, Leroy and Gonthier [13, 12] (DLG), for Java in this environment. An on-the-fly collector, a collector that does not stop the program threads, allows all processors to be utilized during collection and provides uniform response times. We extended and adapted DLG for Java (e.g., adding support for weak references) and for modern multiprocessors without sequential consistency, and added performance improvements (e.g., to keep track of the objects remaining to be traced). We compared the performance of our implementation with stop-the-world mark-sweep GC. Our measurements show that the performance advantage for our collector increases as the number of threads increase and that it provides uniformly low response times.
Hardware support for dynamic activation of compiler-directed computation reuse
Authors: Daniel A. Connors, Hillery C. Hunter, Ben-Chung Cheng, Wen-Mei W. Hwu
Venue: ACM SIGPLAN Notices (2000)

Compiler-directed Computation Reuse (CCR) enhances program execution speed and efficiency by eliminating dynamic computation redundancy. In this approach, the compiler designates large program regions for potential reuse. During run time, the execution results of these reusable regions are recorded into hardware buffers for future reuse. Previous work shows that CCR can result in significant performance enhancements in general applications. A major limitation of the work is that the compiler relies on value profiling to identify reusable regions, making it difficult to deploy the scheme in many software production environments. This paper presents a new hardware model that alleviates the need for value profiling at compile time. The compiler is allowed to designate reusable regions that may prove to be inappropriate. The hardware mechanism monitor the dynamic behavior of compiler-designated regions and selectively activates the profitable ones at run time. Experimental results show that the proposed design makes more effective utilization of hardware buffer resources, achieves repid employment of computation regions, and improves reuse accuracy, all of which promote more flexible compiler methods of identifying reusable computation regions.