ppxscal/embedding_network huggingface dataset:
Identification and Measurement of Convolutions inCotton Fiber Using Image Analysis
Authors: Young J. Han, Yong-Jin Cho, Wade E. Lambert, Charles K. Bragg
Venue: Artificial Intelligence Review (1998)

An image analysis procedure was developed to quantify morphological characteristics of convolutions in individual cotton fibers without pre-tensioning or orientation requirements. The image of each fiber was captured by a PC-based color imaging system using a conventional microscope. Ends of individual cotton fibers were glued on a microscope slide without any tension or straightening. A modified watershed technique was implemented to identify individual convolution segments, which were defined as sections of the fiber bordered by two neighboring convolutions. Length, area and perimeter of each convolution segment were measured directly from the image. Average width, shape factor and number of convolution segments in mm were calculated from the measured parameters. Performance of the image analysis algorithm was compared with visual inspection for number and position of convolution segments in three different varieties of cotton. Image analysis results agreed with visual inspection in 89.6% of the tested images.
Integrating a defect typology with containment metrics
Authors: Robert Bruce Kelsey,  Dr.
Venue: ACM SIGSOFT Software Engineering Notes (1997)

Software metrics are numerous and varied, but they are typically disjoint and seldom directly support defect causal analysis. Diagnosing problems in the development process is certainly possible with disjoint metrics, but the task is greatly simplified if at least a subset of the metrics used are both applicable throughout the development cycle and oriented towards causal analysis of process deficiencies. This paper describes one such set of metrics, the integration of phase containment metrics with a modified defect typology drawn from the traditional inspection checklist. The result is a defect typology that identifies not only coding errors but deficiencies in the procedures used to develop and qualify the product.
Spill code minimization via interference region spilling
Authors: Peter Bergner, Peter Dahl, David Engebretsen, Matthew O'Keefe
Venue: Proceedings of the ACM SIGPLAN 1997 conference on Programming language design and implementation (1997)

Many optimizing compilers perform global register allocation using a Chaitin-style graph coloring algorithm. Live ranges that cannot be allocated to registers are spilled to memory. The amount of code required to spill the live range depends on the spilling heuristic used. Chaitin's spilling heuristic offers some guidance in reducing the amount of spill code produced. However, this heuristic does not allow the partial spilling of live ranges and the reduction in spill code is limited to a local level. In this paper, we present a global technique called interference region spilling that improves the spilling granularity of any local spilling heuristic. Our technique works above the local spilling heuristic, limiting the normal insertion of spill code to a portion of each spilled live range. By partially spilling live ranges, we can achieve large reductions in dynamically executed spill code; up to 75% in some cases and an average of 33.6% across the benchmarks tested.
Block structured object programming
Authors: Charles Rapin
Venue: ACM SIGPLAN Notices (1997)

Most popular object oriented languages have a flat class declaration structure. Providing the possibility of nesting classes gives several interesting properties. Objects may hide their internal representation. Objects may be born within other objects whose structure they know. Meta classes may be implemented as singular, one of its kind, objects in which are nested the classes they control. Languages of the scandinavian school of object oriented programming do offer these possibilities. The author has implemented them and experimented their effects in the Newton language developped at the Compiler Design Laboratory of the Swiss Federal Institute of Technology.
Architectural exploration and optimization of local memory in embedded systems
Authors: Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau
Venue: Proceedings of the 10th international symposium on System synthesis (1997)

Embedded processor-based systems allow for the tailoring of the on-chip memory architecture based on application-specific requirements. We present an analytical strategy for exploring the on-chip memory architecture for a given application, based on a memory performance estimation scheme. The analytical technique has the important advantage of enabling a fast evaluation of candidate memory architectures in the early stages of system design. Our experiments demonstrate that our estimations closely follow the actual simulated performance, at significantly reduced run times.
The DrScheme project: an overview
Authors: Mattias Felleisen, R. B. Findler, M. Flatt, S. Krishnamurthi
Venue: ACM SIGPLAN Notices (1998)

DrScheme provides a graphical user interface for editing and interactively evaluating Scheme programs on all major graphical platforms (Windows 95/nt, MacOs, Unix/X). The environment is especially well-suited to beginning programmers because it supports a tower of Scheme subsets. Each level corresponds to a particular stage in a typical introductory Scheme course and implements a stringent set of syntactic checks. The environment also pinpoints run-time exceptions in a graphical manner and implements a mostly functional read-eval-print loop.Dr. Scheme's most advanced component is a powerful static debugger. It permits programmers to inspect programs for potential safety violations before running them. If the debugger discovers a potential problem, it explains the problem by drawing a value-flow graph over the program text. The value-flow graph shows how an inappropriate value may reach a program operation and trigger a run-time check.The development of Dr. Scheme in Scheme validated the strengths of Scheme, but also revealed several weaknesses. To overcome the latter, the underlying Scheme implementation was extended with a class-based object system, a language of program units, and a sophisticated GUI engine. All of these extensions are available to the programmer, who can thus interactively create fully portable, graphical applications.
Screening tests of pseudorandom number generators on IBM PC's and compatibles
Authors: John M. Gleason
Venue: Proceedings of the 17th conference on Winter simulation (1985)

Two of the more common tests for the statistical properties of pseudorandom number generators are the frequency test and the serial correlation test. This paper reports the results of frequency and serial correlation tests of random number generators available on two classes of microcomputers: the IBM PCs (the IBM PC, the IBM PC-XT, and the IBM portable) and the IBM PC compatible machines (the Compaq, the Olivetti/AT T, the Sperry/Leading Edge, the ITT, and the IBM PC-AT). It is shown that the generators on the IBM compatibles perform better than the IBM generators.
Dynamic patterns as an alternative to conventional text for the partially sighted
Authors: David Veal
Venue: Issue 61 (June 1998) (1998)

When the partially sighted can no longer read even enlarged conventional text then possible aids include Touch Braille and speech synthesis. Touch Braille has proved to be very useful for those with no vision and also for the partially sighted who can only read with difficulty and hence liable to suffer from early fatigue. However, both of these aids lack any visual feedback useful for those with some residual sight. Visual Braille may also be of use but is limited to a given set of standard patterns. It should be noted that many partially sighted people may still be able to see a few areas of different color which maybe sufficient to allow different combinations of colored elements to represent a useful character set.The authors propose a possible alternative reading aid called Dynamic Pattern System (DPS) where each pattern or series of patterns can represent an ASCII character. Each pattern consists of a number of distinct areas, each of which can assume one of a set number of colors. A particular set of patterns representing a character set is known as a patternset. There are many conditions that can lead to partial sight and hence these patternsets may be individualised to each user thereby making full use of their limited vision. This can be regarded as an interface matching solution.The input or output of a DPS can be read as standard text by conventional text-based word processors, web browsers and other standard IT equipment. Using a DPS it may be possible for some partially sighted users to communicate with each other each using their own individualised patternset. Furthermore a fully sighted person may be able to both send and receive conventional text when communicating with a person using a DPS. An extensive literature search has failed to find any comparable work.Hence the advantages of such a system include:- bull; Standard PCs (minimum 386, Windows 3.x, 4M RAM) with no special equipment may be used to encourage the full integration of some partially sighted individuals, who are unable to read even enlarged text, into a standard office environment. bull; A standard PC running DPS may be used by the fully sighted. bull; DPS is a very small (one floppy disk) and easy to use software driven user interface requiring no special hardware and hence offers a low cost solution. bull; Individualized patternsets may allow the most effective use of a user's limited vision.
Concurrent Delay Testing in Totally Self-Checking Systems
Authors: Antonis Paschalis, Dimitris Gizopoulos, Nikolaos Gaitanis
Venue: Journal of Electronic Testing: Theory and Applications (1998)

Prompt detection of even small delay faults, sometimes before causing critical paths to fail, gains importance since stricter test quality requirements for high performance and high density VLSI circuits have to be satisfied in critical applications. This can be achieved by using concurrent delay testing.In this paper a novel idea for concurrent detection of two-rail path delay faults is introduced. It is shown that TSC two-rail code error indicators that monitor pairs of paths with similar propagation delays can be used for concurrent delay testing. Our technique is applied to TSC two-rail code checkers as well as to duplication systems which are the most widely used TSC systems. The design of TSC two-rail code checkers and TSC duplication systems with respect to two-rail path delay faults is achieved for first time in the open literature.
Security issues on the internet
Authors: Carl Stephen Guynes, Richard G. Vedder, Michael T. Vanecek
Venue: ACM SIGSAC Review (1997)

The Internet is a collection of networks originally paid for by the U.S. Department of Defense. Its purpose was to provide a communications infrastructure more resilient to attack than the public communications channels in the event of war. When research became a priority in the 1960s and 1970s, money was given to the National Science Foundation, which became the de facto administrator of the network. The NSF ran the primary arteries of the Internet until the late 1980s. A substantial amount of funding was later added by the U.S. Congress when it decided to include the federal supercomputing facilities in the Internet. As universities tied into the network, they would pay to link a particular network, such as the Bitnet, with the Internet. [2]
Chaos and Neural Network Learning. Some Observations
Authors: K. Bertels, L. Neuberg, S. Vassiliadis, D. G. Pechanek
Venue: Neural Processing Letters (1998)

In this paper, we investigate the impact of chaos on the learning process of the XOR-boolean function by backpropagation neural networks. It has been shown previously that such networks exhibit chaotic behavior but it has never been studied whether chaos enhances or prohibits learning. We show that chaos (when learning the XOR-boolean function) does indeed allow learning but our findings do not indicate any positive role of chaos for learning. In particular, we found that the temperature parameter in the backpropagation algorithm causes the parameter regime, as represented by means of a bifurcation diagram, to shift to the right. We furthermore found that as less chaos appears during the learning process, the faster, on the average, a neural network learned the XOR-function.
An approach to fast hierarchical fault simulation
Authors: Akira Motohara, Motohide Murakami, Miki Urano, Yasuo Masuda, Masahide Sugano
Venue: Proceedings of the 25th ACM/IEEE Design Automation Conference (1988)

We present an approach to hierarchical fault simulation which generates several simulation-models of one circuit and carries out simulation for each. Fault insertion and simulation-model generation is done automatically. Switch-level simulation which utilizes look-up tables is as fast as gate-level simulation. Experimental results show that using behavioral description and switch-level truth tables is effective to improve simulation speed.
Compile-Time Scheduling of Dynamic Constructs in Dataflow Program Graphs
Authors: Soonhoi Ha, Edward A. Lee
Venue: IEEE Transactions on Computers (1997)

Scheduling dataflow graphs onto processors consists of assigning actors to processors, ordering their execution within the processors, and specifying their firing time. While all scheduling decisions can be made at runtime, the overhead is excessive for most real systems. To reduce this overhead, compile-time decisions can be made for assigning and/or ordering actors on processors. Compile-time decisions are based on known profiles available for each actor at compile time. The profile of an actor is the information necessary for scheduling, such as the execution time and the communication patterns. However, a dynamic construct within a macro actor, such as a conditional and a data-dependent iteration, makes the profile of the actor unpredictable at compile time. For those constructs, we propose to assume some profile at compile-time and define a cost to be minimized when deciding on the profile under the assumption that the runtime statistics are available at compile-time. Our decisions on the profiles of dynamic constructs are shown to be optimal under some bold assumptions, and expected to be near-optimal in most cases. The proposed scheduling technique has been implemented as one of the rapid prototyping facilities in Ptolemy. This paper presents the preliminary results on the performance with synthetic examples.
Adaptively Scheduling Parallel Loops in Distributed Shared-Memory Systems
Authors: Yong Yan, Canming Jin, Xiaodong Zhang
Venue: IEEE Transactions on Parallel and Distributed Systems (1997)

Using runtime information of load distributions and processor affinity, we propose an adaptive scheduling algorithm and its variations from different control mechanisms. The proposed algorithm applies different degrees of aggressiveness to adjust loop scheduling granularities, aiming at improving the execution performance of parallel loops by making scheduling decisions that match the real workload distributions at runtime. We experimentally compared the performance of our algorithm and its variations with several existing scheduling algorithms on two parallel machines: the KSR-1 and the Convex Exemplar. The kernel application programs we used for performance evaluation were carefully selected for different classes of parallel loops. Our results show that using runtime information to adaptively adjust scheduling granularity is an effective way to handle loops with a wide range of load distributions when no prior knowledge of the execution can be used. The overhead caused by collecting runtime information is insignificant in comparison with the performance improvement. Our experiments show that the adaptive algorithm and its five variations outperformed the existing scheduling algorithms.
Recycling continuations
Authors: Jonathan Sobel, Daniel P. Friedman
Venue: Proceedings of the third ACM SIGPLAN international conference on Functional programming (1998)

If the continuations in functional data-structure-generating programs are made explicit and represented as records, they can be "recycled." Once they have served their purpose as temporary, intermediate structures for managing program control, the space they occupy can be reused for the structures that the programs produce as their output. To effect this immediate memory reclamation, we use a sequence of correctness-preserving program transformations, demonstrated through a series of simple examples. We then apply the transformations to general anamorphism operators, with the important consequence that all finite-output anamorphisms can now be run without any stack- or continuation-space overhead.
Provably-secure programming languages for remote evaluation
Authors: Dennis Volpano
Venue: ACM SIGPLAN Notices (1997)

Remote evaluation and dynamically-extensible systems pose serious safety and security risks. Programming language design has a major role in overcoming some of these risks. Important research areas include designing suitable languages for remote evaluation, identifying appropriate security and safety properties for them, and developing provably-sound logics for reasoning about the properties in the context of separate compilation and dynamic linking.
A unified framework for enforcing multiple access control policies
Authors: Sushil Jajodia, Pierangela Samarati, V. S. Subrahmanian, Eliza Bertino
Venue: ACM SIGMOD Record (1997)

Although several access control policies can be devised for controlling access to information, all existing authorization models, and the corresponding enforcement mechanisms, are based on a specific policy (usually the closed policy). As a consequence, although different policy choices are possible in theory, in practice only a specific policy can be actually applied within a given system. However, protection requirements within a system can vary dramatically, and no single policy may simultaneously satisfy them all. In this paper we present a flexible authorization manager (FAM) that can enforce multiple access control policies within a single, unified system. FAM is based on a language through which users can specify authorizations and access control policies to be applied in controlling execution of specific actions on given objects. We formally define the language and properties required to hold on the security specifications and prove that this language can express all security specifications. Furthermore, we show that all programs expressed in this language (called FAM/CAM-programs) are also guaranteed to be consistent (i.e., no conflicting access decisions occur) and CAM-programs are complete (i.e., every access is either authorized or denied). We then illustrate how several well-known protection policies proposed in the literature can be expressed in the FAM/CAM language and how users can customize the access control by specifying their own policies. The result is an access control mechanism which is flexible, since different access control policies can all coexist in the same data system, and extensible, since it can be augmented with any new policy a specific application or user may require.
Steps toward a better internal GPSS mechanism
Authors: Ingolf Ståhl
Venue: Proceedings of the 28th conference on Winter simulation (1996)

This paper presents the internal procedures used by the micro-GPSS system. They are quite different from those used by standard GPSS, like GPSS/H. Instead of the Future and Current Events Chain, five different lists are used. The advantages of this approach is that queue statistics, both in front of servers and due to WAIT conditions, can be obtained in a far simpler manner, that programs with long waiting lines are executed more efficiently and that, in the case of equal priority, the transaction having waited the longest time in front of a server will always be the first to be served.
A memory management unit and cache controller for the MARS system
Authors: Feipei Lai, Chyuan-Yow Wu, Tai-Ming Parng
Venue: Proceedings of the 23rd annual workshop and symposium on Microprogramming and microarchitecture (1990)

For large caches, the interaction between cache access and address translation affects the machine cycle time and the access time to memory. The physically addressed caches slow down the cache access due to the virtual address translation. The virtually addressed caches is faster, but the synonym problem is difficult to handle. By some software constraints and hardware support, our virtually addressed physically tagged caches can achieve the same speed as traditional virtually addressed cache and solve the synonym problem. The design of delayed miss signal makes the TLB access depart from the critical path of the cache access. A simple method to solve the TLB coherence is implemented in this chip and only a little hardware is required.
AGENTS: a distributed client-server system for leaf cell generation
Authors: Dilvan de Abreu Moreira, Les T. Walczowski
Venue: ACM Transactions on Design Automation of Electronic Systems (TODAES) (1997)

The AGENTS system is a set of programs designed to generate automatically the mask-level layout of full custom CMOS, BICMOS, and bipolar leaf cells. The system is formed from four sever programs: the placer, router, database, and broker.The placer places components in a cell, the router wires the circuits sent to it, the database stores all the information that is dependent upon the fabrication process, such as the design rules, and the Broker makes the services of the other servers available.These servers communicate over a computer network using the TCP/IP Internet Protocol. The Placer server receives from its client the description and netlist of the circuit to be generated using EDIF (Electronic Design Interchange Format.) The output to its client is the mask layout of the circuit, again codified in EDIF. The comcept of agents as software components which have the ability to communicate and cooperate with each other is at the heart of the AGENTS system. This concept is not only used at the higher level, for the four servers, but at a lower level as well, inside the Router and Placer servers, where small relatively simple agents work together to accomplish complex tasks. These small agents are responsible for all the reasoning carried out by the two servers, as they hold the basic inference routines and the knowledge needed by the servers. The system's philosophy is that competence should emerge out of the collective behavior of a large number of relatively simple agents. In addition and integrated to these small agents, the system uses a genetic algorithm to improve components' placement before routing.
Least-Squares Approximate Solution of Overdetermined Sylvester Equations
Authors: A. Scottedward Hodel, Pradeep Misra
Venue: SIAM Journal on Matrix Analysis and Applications (1997)

We address the problem of computing a low-rank estimate Y of the solution X of the Lyapunov equation A X + X A' + Q = 0 without computing the matrix X itself. This problem has applications in both the reduced-order modeling and the control of large dimensional systems as well as in a hybrid algorithm for the rapid numerical solution of the Lyapunov equation via the alternating direction implicit method. While no known methods for low-rank approximate solution provide the two-norm optimal rank k estimate Xk of the exact solution X of the Lyapunov equation, our iterative algorithms provide an effective method for estimating the matrix Xk by minimizing the error ||A Y + Y A' + Q||F.