ppxscal/embedding_network huggingface dataset:
Integration of CORBA and object relational databases
Authors: Kai-Chih Liang, Daphne Chyan, Yue-Shan Chang, Win-Tsung Lo, Shyan-Ming Yuan
Venue: Computer Standards Interfaces (2003)

CORBA is widely accepted as the open international standard for modelling and building comprehensive distributed systems. In most cases, CORBA architects have adopted relational databases for storage of persistent data. Among the issues that usually face architecture designers considering how to combine CORBA and standard relational database standards are fault tolerance, performance, and the extensibility and scalability of the systems. The research team involved with this paper found that the ODMG object database concept is useful to solve the issues encountered when integrating CORBA and relational database standards. The reference architecture, which the team devises, integrates CORBA and relational databases without compromise on the necessary transactional properties. The CORBA standard object transaction service and concurrency control service are reused. The team also develop an object relational data modelling tool--Latte--that supports the overall design intention as well the development paradigms for the proposed architecture. The implementation of the system is useful to CORBA, ODMG, and relational database architects because it provides a unified modelling and programming paradigm capable of solving the problems of managing mission-critical distributed data. Thus, we present a case study of combining different international standards to build a comprehensive system.
Timeliness via Speculation for Real-Time Databases
Authors: Azer Bestavros, Spyridon Braoudakis
Venue:  (1994)

Abstract Various concurrency control algorithms differ in the time when conflicts are detected, and in the way they are resolved. In that respect, the Pessimistic and Optimistic Concurrency Control (PCC and OCC) alternatives represent two extremes. PCC locking protocols detect conflicts as soon as they occur and resolve them using {\em blocking}. OCC protocols detect conflicts at transaction commit time and resolve them using {\em rollbacks} (restarts). For real-time databases, blockages and rollbacks are hazards that increase the likelihood of transactions missing their deadlines. We propose a {\em Speculative} Concurrency Control (SCC) technique that minimizes the impact of blockages and rollbacks. SCC relies on the use of added system resources to {\em speculate} on potential serialization orders and to ensure that if such serialization orders materialize, the hazards of blockages and roll-backs are minimized. We present a number of SCC-based algorithms that differ in the level of speculation they introduce, and the amount of system resources (mainly memory) they require. We show the performance gains (in terms of number of satisfied timing constraints) to be expected when a representative SCC algorithm (SCC-2S) is adopted.
Image-Based Simulation of Degradation Events
Authors: Laura Moltedo, Ovidio Salvetti
Venue:  (1996)

Some events can be described or supervised using a visual approach, so that a simulation process could assist operations of both image synthesis and analysis. Appearance features can be extracted from source images and then inserted into computational models for analyzing scenes subject to some perturbation functions. Among the different parameters which can be considered, texture is particularly appropriate to characterize surfaces and to be processed for bothimage generation and examination. In this paper a model is proposed able to define a class of simulators useful to study evolving events represented by sequences of images, eventually being degraded by some noise processes. In particular, a simulator has been implemented to evaluate the behaviour of materialsubject to conditions of downgrading or depreciation due to natural and/or artificial agents. This simulator performs texture-based image interpretation and generation. TEL:: +39-50-593455 EMAIL:: salvetti@iei.pi.cnr.it
Processor Capacity Reserves for Multimedia Operating Systems
Authors: Clifford W. Mercer, Stefan Savage, Hideyuki Tokuda
Venue:  (1993)

Multimedia applications have timing requirements that cannot generally be satisfied using time-sharing scheduling algorithms and system structures. To effectively support these types of programs, operating systems must support processor capacity reservation. A capacity reservation and enforcement mechanism isolates programs from the timing and execution characteristics of other programs in the same way that a memory protection system isolates programs from memory access by other programs. In this paper, we characterize the timing requirements and processor capacity reservation requirements for multimedia applications, we describe a scheduling framework to support reservation and admission control, and we introduce a novel reserve abstraction, specifically designed for the microkernel architecture, for controlling processor usage.
Building a Virtually Fault-Tolerant System
Authors: Thomas C. Bressoud
Venue:  (1997)

All schemes for implementing fault-tolerance involve some form of replication. Replicas are assumed to fail independently, and each replica performs the same computation. Replicas may execute in parallel or, in the case of primary-backup protocols, in response to failures. Replication only works, however, if replicas are coordinated. Each replica must receive the same inputs in the same order, and each must be deterministic in its response to these inputs. The key engineering issue that the designer of a fault-tolerant computing system must address is deciding where in the system to implement replica coordination. Some of the alternatives include implementing replica coordination in the processor or network hardware, in the operating system, or in the applications software. A new solution is to implement replica coordination by augmenting the hypervisor of a virtual-machine manager and coordinating a primary virtual machine with its backup. This hypervisor-based fault-tolerance is transparent to the operating system and the applications programs executing above the hypervisor. In addition, this selection allows a single hypervisor design to be used for all processors in an architectural family. In this dissertation, we describe the protocols to implement hypervisor-based fault-tolerance. To assess the practicality of the approach, we constructed a prototype system for HP''s PA-RISC architecture. The prototype hypervisor supports a single HP-UX virtual machine and implements the replica-coordination protocols. The prototype hypervisor has been instrumented to measure the overhead of all hypervisor-based activity. We have measured the performance of CPU-intensive workloads and disk I/O intensive workloads in this architecture and have built models allowing us to predict the performance for some alternative architectures.
Non-Strict Cache Coherence: Exploiting Data-Race Tolerance in Emerging Applications
Authors: Siddhartha V. Tambat, Sriram Vajapeyam
Venue: Proceedings of the Proceedings of the 2000 International Conference on Parallel Processing (2000)

Software distributed shared memory (DSM) platforms on networks of workstations tolerate large network latencies by employing one of several weak memory consistency models. Data-race tolerant applications, such as Genetic Algorithms (GAs), Probabilistic Inference, etc., offer an additional degree of freedom to tolerate network latency: they do not synchronize shared memory references, and behave correctly when supplied outdated shared data. However, these algorithms often have a high communication-to-computation ratio and can flood the network with messages in the presence of large message delays. We study the performance of controlled asynchronous implementations of these algorithms via the use of our previously proposed blocking Global Read memory access primitive. Global Read implements non-strict cache coherence by guaranteeing to return to the reader a shared datum value from within a specified staleness range. Experiments on an IBM SP2 multicomputer with an Ethernet show significant performance improvements for controlled asynchronous implementations. On a lightly loaded Ethernet network, most of the GA benchmarks see 30% to 40% improvement over the best competitor for 2 to 16 processors, while two of the Probabilistic Inference benchmarks see more than 80% improvement for two processors. As the network, load in-creases, the benefits of non-strict cache coherence increase significantly.
On the Dimension of the Set of Rim Perturbations for Optimal Partition Invariance
Authors: H. J. Greenberg, A. G. Holder, C. Roos, T. Terlaky
Venue:  (1996)

Two new dimension results are presented. For linear programs, it is shown that the sum of the dimension of the optimal set and the dimension of the set of objective perturbations for which the optimal partition is invariant equals the number of variables. A decoupling principle shows that the primal and dual results are additive. The main result is then extended to convex quadratic programs, but the dimension relationships are no longer dependent only on problem size. Further, although the decoupling principle does not extend completely, the dimensions are additive, as in the linear case. Futhermore, if a strictly complementary solution exists, all the results are completely analogous to the linear case.
Incremental Graph Parsing
Authors: C. L. McCreary, Susan S. Roth
Venue:  (1994)

A Program Dependence Graph is a useful representation of the dependencies within a code module, with the nodes representing code segments and the edges showing dependency constraints. Through this representation, inherent parallelism in the program structure can be exploited by various heuristics. This paper presents an incremental graph decomposition algorithm which parses the graph into a structure called a Parse Tree that aids in the analysis. The algorithm presented executes in O(n**2) time.
Accurate and Precise Computation using Analog VLSI, with Applications to Computer Graphics and Neural Networks
Authors: David B. Kirk
Venue:  (1993)

This thesis develops an engineering practice and design methodology to enable us to use CMOS analog VLSI chips to perform more accurate and precise computation. These techniques form the basis of an approach that permits us to build computer graphics and neural network applications using analog VLSI. The nature of the design methodology focuses on defining goals for circuit behavior to be met as part of the design process. To increase the accuracy of analog computation, we develop techniques for creating compensated circuit building blocks, where compensation implies the cancellation of device variations, offsets, and nonlinearities. These compensated building blocks can be used as components in larger and more complex circuits, which can then also be compensated. To this end, we develop techniques for automatically determining appropriate parameters for circuits, using constrained optimization. We also fabricate circuits that implement multi-dimensional gradient estimation for a gradient descent optimization technique. The parameter-setting and optimization tools allow us to automatically choose values for compensating our circuit building blocks, based on our goals for the circuit performance. We can also use the techniques to optimize parameters for larger systems, applying the goal-based techniques hierarchically. We also describe a set of thought experiments involving circuit techniques for increasing the precision of analog computation. Our engineering design methodology is a step toward easier use of analog VLSI to solve problems in computer graphics and neural networks. We provide data measured from compensated multipliers built using these design techniques. To demonstrate the feasibility of using analog VLSI for more quantitative computation, we develop small applications using the goal-based design approach and compensated components. Finally, we conclude by discussing the expected significance of this work for the wider use of analog VLSI for quantitative computation, as well as qualitative.
PL/CT A Terminal Version of PL/C Release 2
Authors: Charles G. Moore,  III, Steven L. Worona, Richard W. Conway
Venue:  (1975)

PL/CT is a special version of PL/C designed to permit programs to be run interactively from a typewriter terminal. It is completely compatible with normal PL/C that is, the source languages accepted by PL/C and PL/CT are identical and the results of execution are exactly the same. Hence, a program can be developed and tested under PL/CT and subsequently run under normal PL/C (or vice versa). PL/CT permits the user to interact with the program during its execution. Output will be printed on the terminal and input data may be requested from the terminal. The course and rate of execution can be controlled from the terminal. It is also possible to interrupt execution and display and alter the values of variables. However, the source program itself cannot be changed under PL/CT. PL/CT receives a complete program, compiles it, and then executes it in interactive mode. But to make any change in the program it is necessary to leave PL/CT, make the change under the CMS editor, and then present the modified program to PL/CT for complete recompilation. This Guide provides only minimal information about CMS, perhaps sufficient for very straightforward programming tasks.
On Non-Isomorphic NP Complete Sets
Authors: Juris Hartmanis
Venue:  (1983)

In this note we show that if the satisfiability of Boolean formulas of low Kolmogorov complexity can be determined in polynomial-time then there exist NP complete sets that are not polynomial-time isomorphic. Keywords: NP complete sets, isomorphism, Kolmogorov complexity.
Tight Bound for the Density of Sequences of Integers the Sum of No Two of which is a Perfect Square
Authors: Khalfalah Ayman, Lodha Sachin, Szemeredi Endre
Venue:  (2000)

P. Erd\H{o}s and D. Silverman~\cite{eg-80} proposed the problem of determining the maximal density attainable by a set $S$ of positive integers having the property that no two distinct elements of $S$ sum up to a perfect square. J. P. Massias exhibited such a set consisting of all $x \equiv 1$ (mod $4$) with $x \equiv 14, 26, 30$ (mod $32$) in~\cite{m}. In~\cite{los-82}, J. C. Lagarias, A. M. Odylzko and J. B. Shearer showed that for any positive integer $n$, one cannot find more than $\frac{11}{32} n$ residue classes (mod $n$) such that the sum of any two is never congruent to a square (mod $n$), thus essentially proving that the Massias'' set has the best possible density. They~\cite{los-83} also proved that the density of such a set $S$ is never more than $0.475$ when we allow general sequences. We improve on the lower bound for general sequences, essentially proving that it is not $0.475$, but arbitrarily close to $\frac{11}{32}$, the same as that for sequences made up of only arithmetic progressions.
Selling Online: Canada's Bestselling Guide to Becoming a Successful E-Commerce Merchant, 2 edition
Authors: Jim Carroll, Rick Broadhead
Venue:  (2002)

:Despite some well-publicized hiccups, e-commerce remains an incredibly powerful and lucrative channel for businesses both small and large. Selling Online is the leading authority for Canadians who want to build online retail enterprises that will last. Updated to reflect the most current tools, information, and success strategies, this hands-on book continues to provide everything necessary to launch a successful online storefront solution, including improved security, innovative marketing strategies, and critical mistakes to avoid.E-commerce success is not as easy as was once thought, but the information in Selling Online makes it possible.
Efficient Strategies for Integration and Regression Testing of OO Systems
Authors: Thierry Jéron, Jean-Marc Jézéquel, Yves Le Traon, Pierre Morel
Venue: Proceedings of the 10th International Symposium on Software Reliability Engineering (1999)

In this paper, we present a model, a strategy and a methodology for planning integration and regression testing from an OO model. We show how to produce a model of structural system test dependencies which evolves with the refinement process of the OO design. The model, that is the test dependency graph, serves as a basis for ordering classes and methods to be tested for regression and integration purposes (minimization of test stubs. The mapping from UML to the defined model is detailed as well as the test methodology. While the complexity of optimal stub minimization is exponential with the size of the model, an algorithm which computes a strategy for integration testing with a quadratic complexity is detailed This algorithm provides an efficient testing order for minimizing the number of stubs. A comparison is given of various integration strategies with the proposed optimized algorithm (a real-world case study illustrates this comparison). The results of the experiments seem to give nearly optimal stubs with a low cost despite the exponential complexity of getting optimal stubs.
Performance Evaluation of Hierarchical Ring-Based Shared Memory Multiprocessors
Authors: Mark Holliday, Michael Stumm
Venue:  (1992)

This paper investigates the performance of word-packet, slotted unidirectional ring-based hierarchical direct networks in the context of large-scale shared memory multiprocessors. Slotted unidirectional rings are attractive because their electrical characteristics and simple interfaces allow for fast cycle times and large bandwidths. For large-scale systems, it is necessary to use multiple rings for increased aggregate bandwidth. Hierarchies are attractive because the topology ensures unique paths between nodes, simple node interfaces and simple inter-ring connections. To ensure that a realistic region of the design space is examined, the architecture of the network used in the Hector prototype is adopted as the initial design point. A simulator of that architecture has been developed and validated with measurements from the prototype. The system and workload parameterization reflects conditions expected in the near future. The results of our study show the importance of system balance on performance. Large-scale systems inherently have large communication delays for distant accesses, so processor efficiency will be low, unless the processors can operate with multiple outstanding transactions using techniques such as prefetching, asynchronous writes and multiple hardware contexts. However with multiple outstanding transactions and only one memory bank per processing module, memory quickly saturates. Memory saturation can be alleviated by having multiple memory banks per processing module, but this shifts the bottleneck to the ring subsystem. While the topology of the ring hierarchy affects performance --- we show that topologies with a similar branching factor at all levels, except, possibly, for slightly smaller rings at the root of the hierarchy tend to perform best --- the ring subsystem will inherently limit the throughput of the system. Hence increasing the number of outstanding transactions per processor beyond a certain point only has a limiting effect on performance, since it causes some of the rings to become congested. An adaptive maximum number of outstanding transactions appears necessary to adjust for the appropriate tradeoff between concurrency and contention as the communication locality changes. We show the relationships between processor, ring and memory speeds, and their effects on performance. Using block transfers for prefetching seems unlikely to be advantageous in that the improvement in the cache hit ratio needed to compensate for the increased network utilization is substantial.
Practical Approaches for Connection Admission Control in Multiservice Networks
Authors: TeckKiong Lee, Moshe Zukerman
Venue: Proceedings of the 7th IEEE International Conference on Networks (1999)

In this paper, we test and compare the effectiveness of various Connection Admission Control (CAC) schemes when confronted by heavy arrivals of new connection requests in a link with different server rates. Four CAC schemes are use for this study. The first two schemes are base on the use of a priori traffic information and a model-based approach of computing the desired service bandwidth. For the remaining two schemes, a measurement-based alternative is implemented instead, and hence the desired service bandwidth is estimated by online measurements of the aggregated traffic behavior. Simulation results have shown that the measurement-based schemes are efficient CAC procedures because of the inclusions of a conservative link occupancy-based threshold and an adaptive weight factor that maintain the procedures around the desired link utilization, whilst meeting the QoS.
An Efficient Parallel Algorithm for High Resolution Color Image Reconstruction
Authors: Michael. K. Ng
Venue: Proceedings of the Seventh International Conference on Parallel and Distributed Systems: Workshops (2000)

This paper studies the application of preconditioned conjugate gradient methods in high-resolution color image reconstruction problems. The high-resolution color images are reconstructed from multiple undersampled, shifted, and degraded color frames with subpixel displacements. The resulting de gradation matrices are spatially variant. Taking the cosine transform approximation of the degradation matrices derives the preconditioners. The resulting preconditioning matrices allow the use of fast transform methods. We show how the methods can be implemented on parallel computers, and we demonstrate their parallel efficiency using experiments on a sixteen processor IBM SP-2.
Performance Improvement for High Speed Devices Using E-tests and the SPICE Model
Authors: Hoe-Jin Lee
Venue: Proceedings of the 2nd International Symposium on Quality Electronic Design (2001)

In order to improve the chip performance, a design or a process optimization occurs occasionally at the manufacturing stage. However, modifying the design and the process through the real wafer processing of fabrication increases the time to market. This paper describes an efficient simulation approach for a new IC process centering method based on the SPICE model and E-tests (i.e., threshold voltage and saturation current). This methodology enables obtaining the optimal E-tests for improving the performance of high speed devices, before changing the real process conditions. In addition, the Response Surface Method (RSM) is used as a significant statistical tool for this new procedure. The validity and efficiency of this approach are proven by applying it to an IC process design centering problem for ALPHA CPU. The ACM Portal is published by the Association for Computing Machinery. Copyright © 2010 ACM, Inc. Terms of Usage Privacy Policy Code of Ethics Contact Us Useful downloads: Adobe Acrobat QuickTime Windows Media Player Real Player
Radiation Effects Facility RADEF
Authors: Ari Virtanen
Venue: Proceedings of the Proceedings of The Eighth IEEE International On-Line Testing Workshop (IOLTW'02) (2002)

Since the first days of the space conquest, electronic components have changed remarkably. In the seventies, Single Event Effects (SEE), caused by heavy ions and protons, were unknown. The increase in integration density led first to Single Event Upsets and later, withthe CMOS technology, Single Event Latchups etc... The end of the cold war crashed the military market and, since that, the growing acceptance of Commercial Off-The-Shelf (COTS) components in space systems has encouraged the major manufacturers to withdraw from the RadHard component production. Therefore, one had to start testing of the SEE durability of COTS components with particle accelerators. The ACM Portal is published by the Association for Computing Machinery. Copyright © 2010 ACM, Inc. Terms of Usage Privacy Policy Code of Ethics Contact Us Useful downloads: Adobe Acrobat QuickTime Windows Media Player Real Player