ppxscal/embedding_network huggingface dataset:
An Efficient k-Means Clustering Algorithm: Analysis and Implementation
Authors: Tapas Kanungo, David M. Mount, Nathan S. Netanyahu, Christine D. Piatko, Ruth Silverman, Angela Y. Wu
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (2002)

In k\hbox{-}{\rm{means}} clustering, we are given a set of n data points in d\hbox{-}{\rm{dimensional}} space {\bf{R}}^d and an integer k and the problem is to determine a set of k points in {\bf{R}}^d, called centers, so as to minimize the mean squared distance from each data point to its nearest center. A popular heuristic for k\hbox{-}{\rm{means}} clustering is Lloyd's algorithm. In this paper, we present a simple and efficient implementation of Lloyd's k\hbox{-}{\rm{means}} clustering algorithm, which we call the filtering algorithm. This algorithm is easy to implement, requiring a kd-tree as the only major data structure. We establish the practical efficiency of the filtering algorithm in two ways. First, we present a data-sensitive analysis of the algorithm's running time, which shows that the algorithm runs faster as the separation between clusters increases. Second, we present a number of empirical studies both on synthetically generated data and on real data sets from applications in color quantization, data compression, and image segmentation.
Routing Protocols: RIP and BGP Rbsw05e
Authors: Smartforce
Venue:  (1998)

:Duration: 4 hours. Audience: Operational and networking support staff. Prerequisites: An understanding of routing technologies as delivered in the course Routing Fundamentals. Course aim: To provide the student with a detailed knowledge of RIP, EGP, and BGP. Learning objectives: After taking this course, the student should be able to: Explain RIP operation Describe RIP routing tables and RIP packets Outline how RIPv2 overcomes some of the shortcomings of RIP Contrast the operation and structure of EGP and BGP Compare internal and external BGP Course incorporates: Test. Course structure: .Unit nameTopics 1. RIP operationRouting with RIP RIP routing tables RIP packets 2. Comparing RIP and RIPv2Overcoming RIP limitations RIPv2 enhancements RIPv2 implementation criteria 3. EGP and BGPEGP operation Using BGP BGP operation The ACM Portal is published by the Association for Computing Machinery. Copyright © 2010 ACM, Inc. Terms of Usage Privacy Policy Code of Ethics Contact Us Useful downloads: Adobe Acrobat QuickTime Windows Media Player Real Player
Probability measures with reflection coefficients {an} ε ζ4and {an+1- an} ε ζ2 are Erd&ohuml;s measures
Authors: Sergey A. Denisov
Venue: Journal of Approximation Theory (2002)

In this article, we consider the system of polynomials orthogonal on the unit circle. It is proved that the conditions {<i>a<inf>n</inf></i>} ∈ <i>l</i><sup>4</sup> and {<i>a<inf>n+1</inf> - a<inf>n</inf></i>} ∈ <i>l</i><sup>2</sup> imposed on the reflection parameters {<i>a<inf>n</inf></i>} are sufficient for the associated measure to be Erdös one.
On-line video media for continuing professional development in dentistry
Authors: Patricia A. Reynolds, Robin Mason
Venue: Computers Education (2002)

This project investigated the exploitation of on-line video media for the Continuing Professional Development (CPD) of dentists. More specifically it focused on the evolution of the video media from video-conferencing to simple and complex webcasting. The study aimed to establish models of best practice for the use of both videoconferencing and webcasting in the training of dentists. The three phases in the investigation progressed from a single screen presentation to three frame webcasting. • Phase 1 consisted of videoconferencing and one-frame webcasting across the local area network (LAN). • Phase 2 was a two-frame webcast across the LAN. • Phase 3 a three-frame webcast across the Internet.In each phase three different teaching scenarios were compared the lecture, seminar and one-to-one delivery. The same presenter and teaching material (Medical Emergencies) were used in each setting. The majority of participants were about to qualify as dental surgeons. A qualitative analysis was employed using questionnaires with a 5-point Likert scale, interviews and observational techniques. In the questionnaire, presentational, technical and educational issues were investigated. What clearly emerged was the very positive reaction towards the video media which were considered a most acceptable mode of delivering CPD (rated very good and good more than 80% of the time). Similarly, the presenter and teaching material scored highly in all phases and scenarios (good to very good, 4-5 on the Likert scale). Video-conferencing was deemed more suitable to special occasions such as major lectures, and webcasting was preferred in a one-to-one setting. Technically, webcasting did not make extra demands on the presenter, audio was more reliable and set up times were minimal compared to videoconferencing. However, sufficient webcasting bandwidth was necessary to prevent web-congestion. 'Interactivity' was essential to both recipient and presenter. It was appreciated most in Phase 3 webcasting where the chat box gave time to reflect before responding. A 'learning line' was proposed with videoconferencing and webcasting as part of the spectrum between face-to-face and on-line learning, respectively.
Parallel Architecture for Fast Transforms with Trigonometric Kernel
Authors: F. Argüello, J. D. Bruguera, R. Doallo, E. L. Zapata
Venue: IEEE Transactions on Parallel and Distributed Systems (1994)

We present an unified parallel architecture for four of the most important fast orthogonal transforms with trigonometric kernel: Complex Valued Fourier (CFFT), Real Valued Fourier (RFFT), Hartley (FHT), and Cosine (FCT). Out of these, only the CFFT has a data flow coinciding with the one generated by the successive doubling method, which can be transformed on a constant geometry flow using perfect unshuffle or shuffle permutations. The other three require some type of hardware modification to guarantee the constant geometry of the successive doubling method. We have defined a generalized processing section (PS), based on a circular CORDIC rotator, for the four transforms. This PS section permits the evaluation of the CFFT and FCT transforms in n data recirculations and the RFFT and FHT transforms in n-1 data recirculations, with n being the number of stages of a transform of length N=r/sup n/. Also, the efficiency of the partitioned parallel architecture is optimum because there is no cycle loss in the systolic computation of all the butterflies for each of the four transforms.
Passive tracking in underwater acoustic
Authors: Bernard Xerri, Jean-François Cavassilas, Bruno Borloz
Venue: Signal Processing (2002)

This paper provides a novel passive underwater acoustic method to track a moving object called source or target, with the following constraints: the sensors location is fixed and imposed, and classical array processing techniques cannot be applied. The method proposed has been successfully used to track a surface vessel (2D problem) or an underwater target (3D problem). All the results presented have been obtained with real signals. The localization of the target requires the estimation of propagation delays, that means the duration between the instant of the signal emission and its reception on each receiver. The cross-correlation function is a suitable tool when the target is motionless, but needs to be extended to the ambiguity function when it is moving. The signal to noise ratio, the uniformity of power spectral density and the integration time are determining factors for the accuracy of the localization. We show that a whitening method and a Doppler compensation are necessary, and we propose a way to eliminate the significant problem of the reflected signals. Furthermore, a new configuration of the receivers is proposed, based on the idea of coupling receivers whose distance is chosen from experiment derived results. Furthermore, the algorithm proposed is susceptible to parallel implementation, thereby facilitating real-time uses. Experimental results with real time domain data are presented and compared to trajectories obtained by an active method.
Partition-based decision heuristics for image computation using SAT and BDDs
Authors: Aarti Gupta, Zijiang Yang, Pranav Ashar, Lintao Zhang, Sharad Malik
Venue: Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design (2001)

Methods based on Boolean satisfiability (SAT) typically use a Conjunctive Normal Form (CNF) representation of the Boolean formula, and exploit the structure of the given problem through use of various decision heuristics and implication methods. In this paper, we propose a new decision heuristic based on separator-set induced partitioning of the underlying CNF graph. It targets those variables whose choice generates clause partitions with disjoint variable supports. This can potentially improve performance of SAT applications by decomposing the problem dynamically within the search. In the context of a recently proposed image computation method combining SAT and BDDs, this results in simpler BDD subproblems. We provide algorithms for CNF partitioning -- one based on a clause-variable dependency matrix, and another based on standard hypergraph partitioning techniques, and also for the use of partitioning information in decision heuristics for SAT. We demonstrate the effectiveness of our proposed partition-based heuristic with practical results for reachability analysis of benchmark sequential circuits.
Radio Frequency Identification and the Electronic Product Code
Authors: Sanjay Sarma, David Brock, Daniel Engels
Venue: IEEE Micro (2001)

Remotely scannable IC chips that can access vast amounts of constantly updated information and cost only pennies could be close to reality. New technological developments and a decline in chip cost hold the promise of an automatic data and identification system that uses the Internet.
Using high speed networks to enable distributed parallel image server systems
Authors: Brian L. Tierney, William E. Johnston, Hanan Herzog, Gary Hoo, Guojun Jin, Jason Lee, Ling Tony Chen, Doron Rotem
Venue: Proceedings of the 1994 ACM/IEEE conference on Supercomputing (1994)

We describe the design and implementation of a distributed parallel storage system that uses high-speed ATM networks as a key element of the architecture. Other elements include a collection of network-based disk block servers, and an associated name server that provides some file system functionality. The implementation is based on user level software that runs on UNIX workstations. Both the architecture and the implementation are intended to provide for easy and economical scalability. This approach has yielded a data source that scales economically to very high speed. Target applications include online storage for both very large images and video sequences. This paper describes the architecture, and explores the performance issues of the current implementation.
Introduction to Functional Programming, 2nd edition
Authors: Richard Bird
Venue:  (1998)

:This is a thorough introduction to the fundamental concepts of functional programming.The book clearly expounds the construction of functional programming as a process of mathematical calculation, but restricts itself to the mathematics relevant to actual program construction. It covers simple and abstract datatypes, numbers, lists, examples, trees, and efficiency. It includes a simple, yet coherent treatment of the Haskell class; a calculus of time complexity; and new coverage of monadic input-output.
Power-conscious joint scheduling of periodic task graphs and aperiodic tasks in distributed real-time embedded systems
Authors: Jiong Luo, Niraj K. Jha
Venue: Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design (2000)

In this paper, we present a power-conscious algorithm for jointly scheduling multi-rate periodic task graphs and aperiodic tasks in distributed real-time embedded systems. While the periodic task graphs have hard deadlines, the aperiodic tasks can have either hard or soft deadlines. Periodic task graphs are first scheduled statically. Slots are created in this static schedule to accommodate hard aperiodic tasks. Soft aperiodic tasks are scheduled dynamically with an on-line scheduler. Flexibility is introduced into the static schedule and optimized to allow the on-line scheduler to make dynamic modifications to the static schedule. This helps minimize the response times of soft aperiodic tasks through both resource reclaiming and slack stealing. Of course, the validity of the static schedule is maintained. The on-line scheduler also employs dynamic voltage scaling and power management to obtain a power-efficient schedule. Experimental results show that the flexibility introduced into the static schedule helps improve the response times of soft aperiodic tasks by up to 43%. Dynamic voltage scaling and power management reduce power by up to 68%. The scheme in which the static schedule is allowed to be flexible achieves up to 32% more power saving compared to the scheme in which no flexibility is allowed, when both schemes are power-conscious. Our work gives an average architecture price saving of 30% over a previous approach for embedded system architectures synthesized with execution slots for hard aperiodic tasks present.
On the Performance of Synchronized Programs in Distributed Networks with Random Processing Times and Transmission Delays
Authors: S. Rajsbaum, M. Sidi
Venue: IEEE Transactions on Parallel and Distributed Systems (1994)

A synchronizer is a compiler that transforms a program designed to run in a synchronousnetwork into a program that runs in an asynchronous network. The behavior of a simplesynchronizer, which also represents a basic mechanism for distributed computing and forthe analysis of marked graphs, was studied by S. Even and S. Rajsbaum (1990) under theassumption that message transmission delays and processing times are constant. Westudy the behavior of the simple synchronizer when processing times and transmissiondelays are random. The main performance measure is the rate of a network, i.e., theaverage number of computational steps executed by a processor in the network per unittime. We analyze the effect of the topology and the probability distributions of therandom variables on the behavior of the network. For random variables with exponentialdistribution, we provide tight (i.e., attainable) bounds and study the effect of abottleneck processor on the rate.
Collaborations: Closing the Industry-Academia Gap
Authors: Kathy Beckman, Neal Coulter, Soheil Khajenoori, Nancy R. Mead
Venue: IEEE Software (1997)

When it comes to software engineering education, there is a gap between what industry needs and what universities offer. To close this gap, the authors propose a comprehensive collaboration between academic software engineering programs and industry. They offer a model for this collaboration and highlight three real-world ventures.
Cost and Time-Cost Effectiveness of Multiprocessing
Authors: D. Sarkar
Venue: IEEE Transactions on Parallel and Distributed Systems (1993)

Speedup and efficiency, two measures for performance of pipelined computers, are nowused to evaluate performance of parallel algorithms for multiprocessor systems. However, these measures consider only the computation time and number of processors used and do not include the number of the communication links in the system. The author defines two new measures, cost effectiveness and time-cost effectiveness, for evaluatingperformance of a parallel algorithm for a multiprocessor system. From these two measures two characterization factors for multiprocessor systems are defined and used to analyze some well-known multiprocessor systems. It is found that for a given penalty function, every multiprocessor architecture has an optimal number of processors that produces maximum profit. If too many processors are used, the higher cost of the system reduces the profit obtained from the faster solution. On the other hand, if too few processors are used, the penalty paid for taking a longer time to obtain the solution reduces the profit.
Built-In Test for RAMs
Authors: Paul H. Bardell Jr., William H. McAnney
Venue: IEEE Design Test (1988)

A built-in test structure is described that is based on the ATS algorithmic test sequence, which provides the shortest possible test for stuck-at faults in a random-access memory (RAM). An initialization step has been added to ATS that allows the modified procedure to detect bit-rail faults. In the test mode, the memory address register is converted to a count-by-three circuit controlled by a four-latch test sequencer. A simple data-compare circuit is placed on the RAM outputs to detect faults.
On generalized van der Waerden triples
Authors: Bruce Landman, Aaron Robertson
Venue: Discrete Mathematics (2002)

Van der Waerden's classical theorem on arithmetic progressions states that for any positive integers k and r, there exists a least positive integer, w(k,r), such that any r-coloring of {1,2 .... ,w(k,r)} must contain a monochromatic k-term arithmetic progression {x,x + d, x + 2d,...,x + (k - 1)d}. We investigate the following generalization of w(3,r). For fixed positive integers a and b with a ≤ b, define N(a,b;r) to be the least positive integer, if it exists, such that any r-coloring of {1,2,...,N(a,b;r)} must contain a monochromatic set of the form {x, ax + d, bx + 2d}. We show that N(a, b; 2) exists if and only if b ≠ 2a, and provide upper and lower bounds for it. We then show that for a large class of pairs (a,b), N(a,b;r) does not exist for r sufficiently large. We also give a result on sets of the form {x,ax + d,ax + 2d ..... ax + (k - 1 )d}.
Conceptual Transaction Modeling
Authors: A. H. H. Ngu
Venue: IEEE Transactions on Knowledge and Data Engineering (1989)

Transaction modeling, which involves capturing the dynamic properties of an organization, is seen as a necessary component in data modeling. A specification language-transaction schema based on the ACM/PCM specification language-is implemented as the transaction modeling tool. The benefit of such a modeling tool is discussed and, in particular, illustrated by its capability to extend the static schema automatically in order to support the intended transactions.
Seeking Solutions in Configurable Computing
Authors: William H. Mangione-Smith, Brad Hutchings, David Andrews, André DeHon, Carl Ebeling, Reiner Hartenstein, Oskar Mencer, John Morris, Krishna Palem, Viktor K. Prasanna, Henk A. E. Spaanenburg
Venue: Computer (1997)

Configurable computing systems combine programmable hardware with programmable processors to capitalize on the strengths of hardware and software. They have the potential for achieving high performance for a range of applications, including image filtering, convolution, morphology, feature extraction, and object tracking. Researchers have developed prototype systems that achieve performance an order of magnitude higher than more conventional approaches. However, realizing this potential outside of the laboratory has proven difficult. No system to date has yet proven attractive or competitive enough to establish a commercial presence. Ample opportunity exists for work in a broad range of areas. Not surprisingly, many of the most pressing needs can be lumped into the category of FPGA-related technology, because so many configurable computing systems are based on FPGAs.
VLSI Architectures for High-Speed Range Estimation
Authors: Raghu Sastry, N. Ranganathan, Ramesh C. Jain
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1995)

Depth recovery from gray-scale images is an important topic in the field of computer and robot vision. Intensity gradient analysis (IGA) is a robust technique for inferring depth information from a sequence of images acquired by a sensor undergoing translational motion. IGA obviates the need for explicitly solving the correspondence problem and hence is an efficient technique for range estimation. Many applications require real time processing at very high frame rates. The design of special purpose hardware could significantly speed up the computations in IGA. In this paper, we propose two VLSI architectures for high-speed range estimation based on IGA. The architectures fully utilize the principles of pipelining and parallelism in order to obtain high speed and throughput. The designs are conceptually simple and suitable for implementation in VLSI.
Case-Based Reasoning Systems: From Automation to Decision-Aiding and Stimulation
Authors: Soumitra Dutta, Berend Wierenga, Arco Dalebout
Venue: IEEE Transactions on Knowledge and Data Engineering (1997)

Over the past decade, case-based reasoning (CBR) has emerged as a major research area within the artificial intelligence research field due to both its widespread usage by humans and its appeal as a methodology for building intelligent systems. Conventional CBR systems have been largely designed as automated problem-solvers for producing a solution to a given problem by adapting the solution to a similar, previously solved problem. Such systems have had limited success in real-world applications. More recently, there has been a search for new paradigms and directions for increasing the utility of CBR systems for decision support. This paper focuses on the synergism between the research areas of CBR and decision support systems (DSSs). A conceptual framework for DSSs is presented and used to develop a taxonomy of three different types of CBR systems: 1) conventional, 2) decision-aiding, and 3) stimulative. The major characteristics of each type of CBR system are explained with a particular focus on decision-aiding and stimulative CBR systems. The research implications of the evolution in the design of CBR systems from automation toward decision-aiding and stimulation are also explored.
On the Equivalence of Fanout-Point Faults
Authors: A. Lioy
Venue: IEEE Transactions on Computers (1993)

Test-equivalent faults are commonly used in test generation and fault simulation to reduce the number of explicitly addressed faults. At the gate level, practical equivalence rules are confined to faults on the input and output terminals of Boolean gates and those related to fanout-free wires. It is shown that under some conditions equivalence may also be stated between faults on a fanout stem and its branches. A modification of the standard fault folding algorithm is proposed, which leads to reducing the number of target faults and occasionally identifying logic redundancies. Application to real designs shows that the added computational complexity is negligible, while for some classes of CMOS circuits hard-to-simulate faults are eliminated and hence their fault simulation time is drastically reduced.