ppxscal/embedding_network huggingface dataset:
An exact algorithm for coupling-free routing
Authors: Ryan Kastner, Elaheh Bozorgzadeh, Majid Sarrafzadeh
Venue: Proceedings of the 2001 international symposium on Physical design (2001)

In this wrok, we develop methods to reduce interconnect delay and noise caused by coupling. First, we explain the Coupling-Free Routing (CFR) problem. CFR takes a set of nets and tries to find a one-bend couple-free routing for a subset of nets. A routed net must not couple with any other routed net. We define coupling as a boolean variable which is true when the coupling of two nets is greater than some threshold. Any pair-wise coupling definition can be used. We argue that this problem is useful in both global and detailed routingWe develop an exact algorithm for the CFR decision problem via a transformation to 2-satisfiability. This algorithm runs in linear time. The decision problem determines whether the given set of nets is coupling-free routable. Next, we present the implication graph which models the dependencies associated with CFR. Also, we look at some of the properties associated with the graph.Finally, we develop a new algorithm for the Maximum Coupling-Free Layout (MAX-CFL) problem. Given a set of nets, the MAX-CFL is defined as finding a subset of nets that are coupling-free routable. The subset should have maximum size and/or critically. The new algorithm, called implication algorithm, uses properties assoicated with the implication graph and experiments show that it consistently finds the best solution in terms of number of nets routed as compared to previous algorithms
Learning to Recognize Visual Dynamic Events from Examples
Authors: Massimiliano Pittore, Marco Campani, Alessandro Verri
Venue: International Journal of Computer Vision (2000)

This paper describes a trainable and flexible system able to recognize visual dynamic events, e.g. movements performed by different people, from a stream of images taken by a fixed camera. Each event is represented by a feature vector built from the spatio-temporal changes detected in the observed image sequence. The system neither attempts to recover the 3D structure nor assumes a prior model of the observed dynamic events. During training a supervisor identifies and labels the events of interest among those automatically detected by the system. At run time, previously unseen events are detected and classified on the basis of the available examples. Several experiments on real images are reported and the benefits of using Support Vector Machines for performing effective classification from a relatively small number of labeled examples and for building noise tolerant representations are discussed. Preliminary results indicate that the proposed system can also be applied with equally good results to the case in which the dynamic events are gestures performed by different people.
Memory occupancy patterns in garbage collection systems
Authors: D. Julia. M. Davies
Venue: Communications of the ACM (1984)

Some programming languages and computer systems use dynamic memory allocation with garbage collection. It would be useful to understand how the utilization of memory depends on the stochastic parameters describing the size and life distributions of the cells. We consider a class of dynamic storage allocation systems which use a first-fit strategy to allocate cells and perform noncompacting garbage collections to recover free memory space when memory becomes fully occupied. A formula is derived for the expected number of holes (available cells) in memory immediately following a garbage collection which specializes to an analogue of Knuth's 'Fifty Percent' rule for nongarbage-collection systems. Simulations confirm the rule for exponentially distributed cell lifetimes. Other lifetime distributions are discussed. The memory-size requirements for noncompacting garbage collection are also analyzed.
A practical tool box for system level communication synthesis
Authors: Denis Hommais, Frédéric Pétrot, Ivan Augé
Venue: Proceedings of the ninth international symposium on Hardware/software codesign (2001)

This paper presents a practical approach to communication synthesis for hardware/software system specified as tasks communicating through lossless blocking channels. It relies on a limited set of templates that characterize the way data are exchanged between tasks realized either in software or in hardware. The templates are highly portable because their software part is implemented using the POSIX thread functions, and their hardware part is a hand crafted synthesizable module with a System VCI interface. These Interface Modules allow simple Virtual Component reuse since they not only implement protocol compatibility through the use of the System VCI/OCB standard but also system level communications through semantics widely accepted in the design community.
A user authentication scheme not requiring secrecy in the computer
Authors: Arthur Evans,  Jr., William Kantrowitz, Edwin Weiss
Venue: Communications of the ACM (1974)

In many computer operating systems a user authenticates himself by entering a secret password known solely to himself and the system. The system compares this password with one recorded in a Password Table which is available to only the authentication program. The integrity of the system depends on keeping the table secret. In this paper a password scheme is presented which does not require secrecy in the computer. All aspects of the system, including all relevant code and data bases, may be known by anyone attempting to intrude. The scheme is based on using a function H which the would-be intruder is unable to invert. This function is applied to the user's password and the result compared to a table entry, a match being interpreted as authentication of the user. The intruder may know all about H and have access to the table, but he can penetrate the system only if he can invert H to determine an input that produces a given output. This paper discusses issues surrounding selection of a suitable H. Two different plausible arguments are given that penetration would be exceedingly difficult, and it is then argued that more rigorous results are unlikely. Finally, some human engineering problems relating to the scheme are discussed.
A unified technique for PCB/MCM design by combining electromagnetic field analysis with circuit simulator
Authors: H. Kimura, N. Iyenaga
Venue: Proceedings of the conference on Design, automation and test in Europe (1998)

This paper proposed the unified design technique which combines electromagnetic field analysis [FDTD technique] with circuit simulator [HSPICE]. Proposed technique can analyze the integrated circuits [ICs], multi-chip-module [MCM], and printed circuit board [PCB] design in high-efficiency and high-accuracy including the rounding noise throughout the substrate. Furthermore, this technique can not only analyze the small signal operation but also large signal operation.
Input Feature Extraction for Multilayered Perceptrons Using Supervised Principal Component Analysis
Authors: Stavros J. Perantonis, Vassilis Virvilis
Venue: Neural Processing Letters (1999)

A method is proposed for constructing salient features from a set of features that are given as input to a feedforward neural network used for supervised learning. Combinations of the original features are formed that maximize the sensitivity of the network&lsquo;s outputs with respect to variations of its inputs. The method exhibits some similarity to Principal Component Analysis, but also takes into account supervised character of the learning task. It is applied to classification problems leading to improved generalization ability originating from the alleviation of the curse of dimensionality problem.
Improved approximation bounds for the group Steiner problem
Authors: C. S. Helvig, G. Robins, A. Zelikovsky
Venue: Proceedings of the conference on Design, automation and test in Europe (1998)

Given a weighted graph and a family of k disjoint groups of nodes, the Group Steiner Problem asks for a minimum-cost routing tree that contains at least one node from each group. We give polynomial-time O(k^e)-approximation algorithms for arbitrarily small values of e>0, improving on the previously known O(k^0.5)-approximation. Our techniques also solve the graph Steiner arborescence problem with an O(k^e) approximation bound. These results are directly applicable to a practical problem in VLSI layout, namely the routing of nets with multi-port terminals. Our Java implementation is available on the Web.
Is automatic &ldquo;folding&rdquo; of programs efficient enough to displace manual?
Authors: D. Sayre
Venue: Communications of the ACM (1969)

The operation of &ldquo;folding&rdquo; a program into the available memory is discussed. Measurements by Brawn et al. and by Nelson on an automatic folding mechanism of simple design, a demand paging unit built at the IBM Research Center by Belady, Nelson, O'Neill, and others, permitting its quality to be compared with that of manual folding, are discussed, and it is shown that given some care in use the unit performs satisfactorily under the conditions tested, even though it is operating across a memory-to-storage interface with a very large speed difference. The disadvantages of prefolding, which is required when the folding is manual, are examined, and a number of the important troubles which beset computing today are shown to arise from, or be aggravated by, this source. It is concluded that a folding mechanism will probably become a normal part of most computing systems.
A variant method of file searching
Authors: M. D. Mc Ilroy
Venue: Communications of the ACM (1963)

Trapping an instruction which cannot normally be trapped can be worthwhile, particularly when an existing program is to be revised. However, under those circumstances one would desire to replace instructions on a one-for-one basis.
Hierarchical physical design methodology for multi-million gate chips
Authors: Wei-Jin Dai
Venue: Proceedings of the 2001 international symposium on Physical design (2001)

In this paper, a design methodology for the implementation of multi-million gate system-on-chip designs is described.
Combinatorial routing analysis and design of universal switch blocks
Authors: Hongbing Fan, Jiping Liu, Yu-Liang Wu
Venue: Proceedings of the 2001 Asia and South Pacific Design Automation Conference (2001)

A switch block with k sides and W terminals per side ((k; W)-SB) is said to be universal if every set of 2-pin nets satisfying the dimension constraint is simultaneously routable through the switch block. It has been shown that the universal switch blocks (USB) outperform the XC4000-typed switch blocks in routability. In this paper, we present a new combinatorial model and routing requirement decomposition theory for analyzing and designing generalized USB models. As a result, we obtain optimum (k,W)-USBs for k&leq;6 with all W's, k = 7,8 with even W's; and nearly optimum (k,W)-UBSs for k = 7; 8 with odd W's, which is a revised result on the previously published.
The motivation of students of programming
Authors: Tony Jenkins
Venue: ACM SIGCSE Bulletin (2001)

Students approach the study of computing in Higher Education in increasing numbers from an increasingly wide variety of backgrounds. In most degree level courses one of the first modules students will encounter is intended to teach them to program.As the students become more diverse, so do their motivations for taking their degree. Anecdotal evidence from many institutions is that students are becoming more tactical, and will engage only in those activities that they see as contributing to an eventual highly paid job.This paper describes an investigation into the motivations of students for taking a degree in computing, and for studying programming in particular. The results raise a number of issues for the teaching of programming.
Computing Global Functions in Asynchronous Distributed Systems with Perfect Failure Detectors
Authors: J.-M. Hélary, M. Hurfin, A. Mostefaoui, M. Raynal, F. Tronel
Venue: IEEE Transactions on Parallel and Distributed Systems (2000)

A Global Data is a vector with one entry per process. Each entry must be filled with an appropriate value provided by the corresponding process. Several distributed computing problems amount to compute a function on a global data. This paper proposes a protocol to solve such problems in the context of asynchronous distributed systems where processes may fail by crashing. The main problem that has to be solved lies in computing the global data and in providing each noncrashed process with a copy of it, despite the possible crash of some processes. To be consistent, the global data must contain, at least, all the values provided by the processes that do not crash. This defines the Global Data Computation (GDC) problem. To solve this problem, processes execute a sequence of asynchronous rounds during which they construct, in a decentralized way, the value of the global data and eventually each process gets a copy of it. To cope with process crashes, the protocol uses a perfect failure detector. The proposed protocol has been designed to be time efficient: it allows early decision. Let $t$ be the maximum number of processes that may crash, $t
Operating Systems: Program overlay techniques
Authors: R. J. Pankhurst
Venue: Communications of the ACM (1968)

The general features of program overlay systems are described. Three main types&mdash;automatic, semiautomatic and non-automatic&mdash;are classified, and the programming techniques are explained as a function of machine hardware and other system features. The implementation of a semiautomatic overlay facility in a multiprogrammed system on the CDC 6600 is described in detail, with special reference to real time applications.
A comprehensive curriculum for IT education and workforce development: an engineering approach
Authors: F. Golshani, S. Panchanathan, O. Friesen, Y. C. Park, J. J. Song
Venue: ACM SIGCSE Bulletin (2001)

Noting the shortage of IT professionals nationally [1], we propose a comprehensive curriculum that supports a variety of programs geared to all ages from early school years to retirement and beyond. Current IT workforce development efforts are limited to training, and have not as yet focused on education and professional development. Largely, this is due to a lack of a science underpinning for IT related curricula. Without such a unified science component, a structured organization of information related concepts cannot be derived.Our proposal includes the development of a number of programs addressing the needs of a variety of learners ranging from elementary school through college and beyond. Seven programs, each with a specific emphasis for various groups, are being developed. Such essential issues as industrial-academic liaisons, workforce (re)training, promotional and awareness programs, teacher training, and IT professional role redefinition, are integral pieces of this project. All developments will be firmly founded on the scientific framework of information science and engineering [2].This work is supported by NSF grant DUE-9950168.
Krylov Subspace Acceleration of Nonlinear Multigrid with Application to Recirculating Flows
Authors: C. W. Oosterlee, T. Washio
Venue: SIAM Journal on Scientific Computing (1999)

This paper deals with the combination of two solution methods: multigrid and GMRES [SIAM J. Sci. Comput., 14 (1993), pp. 856--869]. The generality and parallelizabili nonlinear PDEs. As the "preconditioner" for a nonlinear Krylov subspace method, we use the full approximation storage (FAS) scheme [ Math. Comp., 31 (1977), pp. 333--390], a nonlinear multigrid method. The nonlinear Krylov acceleration is applied also on coarse grids, so that recirculating incompressible flow problems discretized with a higher order upwind scheme can be solved efficiently.
Semicoarsening Multigrid on Distributed Memory Machines
Authors: Peter N. Brown, Robert D. Falgout, Jim E. Jones
Venue: SIAM Journal on Scientific Computing (1999)

This paper presents the results of a scalability study for a three-dimensional semicoarsening multigrid solver on a distributed memory computer. In particular, we are interested in the scalability of the solver---how the solution time varies as both problem size and number of processors are increased. For an iterative linear solver, scalability involves both algorithmic issues and implementation issues. We examine the scalability of the solver theoretically by constructing a simple parallel model and experimentally by results obtained on an IBM SP. The results are compared with those obtained for other solvers on the same computer.
A pedagogical framework for introducing Java I/O in CS1
Authors: Scott Grissom
Venue: ACM SIGCSE Bulletin (2000)

The role of Java for teaching CS1 has received considerable attention. A common concern of many educators is that the Java I/O paradigm is too challenging for novice programmers and that significant time must be devoted to the subject. This additional time may take away from the traditional CS1 content. Four strategies for teaching Java I/O in CS1 are reviewed herein. Text-based versus GUI-based applications represent the two extremes. Advantages and disadvantages are provided for each approach. A description of preliminary work to develop a Java package that makes implementing GUI applications simple is given, with the objective of preparing students for the eventual transition to the Java AWT.
Power minization in LUT-based FPGA technology mapping
Authors: Zhi-Hong Wang
Venue: Proceedings of the 2001 Asia and South Pacific Design Automation Conference (2001)

In this paper, we consider the problem of lookup table (LUT) based FPGA technology mapping for power minimization in combinational circuits. The problem has been previously proved to be NP-hard, and hence we present an efficient heuristic algorithm for it. The main idea of our algorithm is to exploit the "cut enumeration" technique to generate possible mapping solutions for the sub-circuit rooted at each node. However, for the consideration of both run time and memory space, only a fixed-number of solutions are selected and stored by our algorithm. To facilitate the selection process, a method that correctly calculates the estimated power consumption for each mapped sub-circuit is developed. The experimental results indicate that our algorithm reduces the average power consumption by up to 14.18%, and the average number of LUTs by up to 6.99% over an existing method.
A simple entropy-based algorithm for planar point location
Authors: Sunil Arya, Theocharis Malamatos, David M. Mount
Venue: Proceedings of the twelfth annual ACM-SIAM symposium on Discrete algorithms (2001)

Given a planar polygonal subdivision S, point location involves preprocessing this subdivision into a data structure so that given any query point q, the cell of the subdivision containing q can be determined efficiently. Suppose that for each cell z in the subdivision, the probability pz that a query point lies within this cell is also given. The goal is to design the data structure to minimize the average search time. It has long been known that the entropy H of the probability distribution is the dominant term in the lower bound on the average-case search time. This problem has been considered before, but existing data structures are all quite complicated. In this paper, we show that a very simple modification of a well-known randomized incremental algorithm can be applied to produce a data structure of expected linear size that can answer point location queries in &Ogr;(H) average time. We also present empirical evidence for the practical efficiency of this approach.
The Impact of the Prospective Payment System on the Technical Efficiency of Hospitals
Authors: Jin-Yuan Chern, Thomas T. H. Wan
Venue: Journal of Medical Systems (2000)

In a longitudinal panel study design, 80 hospitals in Virginia were selected for analysis to test the hypothesis that the introduction of the prospective payment system (PPS) in October 1983 had helped hospitals enhance their operational performance in technical efficiency. A non-parametric method called Data Envelopment Analysis (DEA) was used to calculate and compare the efficiency scores for each peer group of hospitals (by bed size) between the year 1984 and the year 1993. Contrary to expectations, no significant difference in technical efficiency was found in each hospital peer group over the study period. Nevertheless, the case study demonstrates that if hospital managers use this analytical tool appropriately, they may spot where any organizational weakness lies and how they can improve it.
Description of FORMAT, a text-processing program
Authors: Gerald M. Berns
Venue: Communications of the ACM (1969)

FORMAT is a production program which facilitates the editing and printing of &ldquo;finished&rdquo; documents directly on the printer of a relatively small (64k) computer system. It features good performance, totally free-form input, very flexible formatting capabilities including up to eight columns per page, automatic capitalization, aids for index construction, and a minimum of nontext items. It is written entirely in FORTRAN IV.
Computational challenges in large-scale air pollution modelling
Authors: Tzvetan Ostromsky, Wojciech Owczarz, Zahari Zlatev
Venue: Proceedings of the 15th international conference on Supercomputing (2001)

Many difficulties must be overcome when large-scale air pollution models are treated numerically, because the physical and chemical processes in the atmosphere are very fast. This is why it is necessary to use a large space domain in order to be able to study long-range transport, of pollutants in the atmosphere, to describe adequately all important processes when an air pollution model is developed and to use fine grids in the discretization of the model. If all these conditions are taken in to account, then the resulting computational tasks are huge and the computer treatment of the model is very difficult even when powerful modern computers are in use. Therefore, the following two major tasks must be solved: fast and sufficiently accurate numerical methods are to be selected and the selected numerical methods should be efficiently implemented on the available high-speed computers. The solution of these two important tasks in connection with a particular large-scale air pollution model, the Danish Eulerian Model, will be discussed in this paper. The use of standard parallelization tools allows us to achieve good performance when the model is run on different parallel computers. This will be illustrated in the paper by many numerical examples.
Performance analysis using the MIPS R10000 performance counters
Authors: Marco Zagha, Brond Larson, Steve Turner, Marty Itzkowitz
Venue: Proceedings of the 1996 ACM/IEEE conference on Supercomputing (CDROM) (1996)

Tuning supercomputer application performance often requires analyzing the interaction of the application and the underlying architecture. In this paper, we describe support in the MIPS R10000 for non-intrusively monitoring a variety of processor events -- support that is particularly useful for characterizing the dynamic behavior of multi-level memory hierarchies, hardware-based cache coherence, and speculative execution. We first explain how performance data is collected using an integrated set of hardware mechanisms, operating system abstractions, and performance tools. We then describe several examples drawn from scientific applications that illustrate how the counters and profiling tools provide information that helps developers analyze and tune applications.
The translator from SMP-description of algorithm to VHDL-model of ASIC23
Authors: Dunets Bohdan, Anatoly Melnyk
Venue: Proceedings of the symposium on Contemporary computing in Ukraine (2000)

The ASIC design flow from high-level language algorithm description to RTL level are presented. The main part of the design flow is translator from SMP-description of algorithm to RTL VHDL-model of ASIC. In the paper the design flow and structure of translator are considered.