ppxscal/embedding_network huggingface dataset:
A Communication Latency Hiding Parallelization of a Traffic Flow Simulation
Authors: Charles Michael Johnston, Anthony T. Chronopoulos
Venue: Proceedings of the 13th International Symposium on Parallel Processing and the 10th Symposium on Parallel and Distributed Processing (1999)

This work implements and analyses a highway traffic flow simulation based on continuum modeling of traffic dynamics. A traffic-flow simulation was developed and mapped onto a parallel computer architecture. Two algorithms (the 1-step and 2-step algorithms) to solve the simulation equations were developed and implemented. They were then tested on an nCUBE2, a 1024 node hypercube with very slow inter-processor communication (IPC) times. Tests with real traffic data collected from the freeway network in the metropolitan area of Minneapolis, Minnesota were used to validate the accuracy and computation rate of the parallel simulation system. The execution time for a 24-hour traffic-flow simulation over a 15.5-mile freeway, which takes 65.7 minutes on a typical single processor computer, took only 88.51 seconds on the nCUBE2. The 2-step algorithm, whose goal is to trade off extra computation for fewer IPC's, was shown to save more than 19% on total execution time.
Design and Implementation of a new Synchronization Method for High-Speed Cell-based Network Interfaces
Authors: A. Maniatopoulos, Theodore Antonakopoulos, Vassilios Makios
Venue: Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors (1996)

This paper presents the coding and timing recovery issues of an interface for high-speed cell-based communication networks. The synchronization technique used in this interface is based on the functionality resulting from combining functions of Fibre Channel with the basic features of pure ATM. The line coding properties, along with a pseudo-framing structure, are used to simplify the cell delineation process, thus resulting to lower hardware complexity than existing ATM interfaces, and implementability at high transmission rates. The paper describes also the architecture of a prototyped interface and its implementation using commercially available and custom ICs at 1 Gbps.
Transactions in the Client-Server EOS Object Store
Authors: Alexandros Biliris, Euthimios Panagos
Venue: Proceedings of the Eleventh International Conference on Data Engineering (1995)

The paper describes the client-server software architecture of the EOS storage manager and the concurrency control and recovery mechanisms it employs. Unlike most client-server storage systems that use the standard two-phase locking protocol, EOS offers a semi-optimistic locking scheme based on a multigranularity two-version two-phase locking protocol. Under this scheme, many readers are allowed to access a data item while it is being updated by a single writer. For recovery, EOS maintains a write-ahead redo-only log because of the potential benefits it offers in a client-server environment. First, there are no undo records, as log records of aborted transactions are never inserted in the log; this minimizes the I/O and network transfer costs associated with logging during normal transaction execution. Secondly, it reduces the space required for the log. Thirdly, it facilitates fast recovery from system crashes because only one forward scan of the log is required for installing the updates performed by transactions that committed prior to the crash. Performance results of the EOS recovery subsystem are also presented.
A Practical Algorithm for Retiming Level-Clocked Circuits
Authors: Naresh Maheshwari, Sachin S. Sapatnekar
Venue: Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors (1996)

A new approach for fast retiming of level-clocked circuits is presented here. The method relies on the relation between clock skew and retiming, and computes the optimal skew solution to translate it to a retiming. Since clock skew optimization operates on the latches (rather than the gates as in conventional retiming), it is much faster because of a smaller problem size; the translation to the retiming solution is computationally cheap. The minimum period retiming for each of the ISCAS89 circuits was obtained within minutes by this algorithm.
Semantic Interoperability in the Securities Industry: Context Interchange Mediation of Semantic Differences in Enumerated Data Types
Authors: Allen Moulton, Stuart E. Madnick, Michael D. Siegel
Venue: Proceedings of the 13th International Workshop on Database and Expert Systems Applications (2002)

Using securities industry examples, the context interchange mediation knowledge architecture is applied to interoperability problems for enumerated data types, such as codes and other symbols used to represent conceptual distinctions. Ongoing efforts in the securities industry to develop new XML-based standards for information interchange are examined. Using components representing similar securities information, drawn from different but complementary securities standards and sources, example problems of information interoperability are examined. We show that transforming data representation into an autonomously specified context model and thence into a general domain ontology allows successful interoperability in several ways depending on how each context is explained to the mediator.
Presentation Layer Framework of Web Application Systems with Server-Side Java Technology
Authors: Akihiro Saimi, Tsutomu Syomura, Hiroshi Suganuma, Itaru Ishida
Venue: 24th International Computer Software and Applications Conference (2000)

Demands for web application systems with server-side Java technologies force the application service providers (ASPs) to deliver solutions in timely manner. There are a number of major concerns, however, for ASPs in developing such systems, including the shortage of Java experts with experiences, and the reduction of development time. To cope with these issues, we developed a framework mainly focused on the presentation layer of web application systems - PlayFwas. PlayFwas provides (1) a set of processes for design and implementation with documentation formats, (2) abstract classes for both Java servlet components and JavaBeans components, and (3) a template source code for JSP. Preliminary case study shows that PlayFwas enables less-experienced programmers to develop web application systems efficiently without sacrificing either maintainability or extensibility. This paper discusses the architecture of PlayFwas and its impact on web application development.
Efficient Processing of Outer Joins and Aggregate Functions
Authors: Gautam Bhargava, Piyush Goel, Balakrishna R. Iyer
Venue: Proceedings of the Twelfth International Conference on Data Engineering (1996)

Removal of redundant outer joins is essential for the reassociation of outer joins with other binary operations. In this paper we present a set of comprehensive algorithms that employ the properties of strong predicates along with the properties of aggregation, intersection, union, and except operations to remove redundant outer joins from a query. For the purpose of query simplification, we generate additional projections by determining the keys. Our algorithm for generating keys is based on a novel concept of weak bindings that is essential for queries containing outer joins. Our algorithm for converting outer joins to joins is based on a novel concept of join-reducibility.
Architecture-Dependent Tuning of the Parameterized Communication Model for Optimal Multicasting
Authors: Natawut Nupairoj, Lionel M. Ni, Ju-Young Lee Park, Hyeong-Ah Choi
Venue: Proceedings of the 11th International Symposium on Parallel Processing (1997)

A key issue in designing software multicast algorithms is to consider the trade-off between performance and portability. Portable software multicast algorithms which base on generic communication models cannot capture some architecture-specific features. Without considering the underlying network architecture, these multicast algorithms may not achieve the truly optimal performance when implemented in real networks. The objective of this research is to investigate architecture-dependent tuning on performance of multicast algorithms developed based on architecture-independent models. Specifically, we intend to optimize the mulitcast algorithm based on the parameterized communication model. We propose two multicast algorithms, OPT-mesh and OPT-min which are the optimized versions of the parameterized multicast algorithm for wormhole-switched mesh networks and BMIN networks, respectively. Using our flit-level simulator, the performance of both algorithms are compared with the architecture-independent version of the parameterized multicast algorithm and two other well-known network-dependent algorithms based on the binomial tree.
Character Recognition in Practice Today and Tomorrow
Authors: Udo Miletzki
Venue: Proceedings of the 4th International Conference on Document Analysis and Recognition (1997)

An outline of today's state of the art OCR-Technology is given with its most important approaches from single character recognition to holistic word recognition and the co-evolution of hardware technology and pattern recognition capabilities is shown. The relation between font design and the design of an omnifont recognition system is illustrated. The economic relevance of todays's OCR technology is discussed. The article concludes with reflections about future trends in the OCR-field such as growing complexity of patterns and knowledge bases in OCR applications.
A Cooperative Workflow Management System with the Meta-Object Facility
Authors: Le Pallec Xavier, Vantroys Thomas
Venue: Proceedings of the 5th IEEE International Conference on Enterprise Distributed Object Computing (2001)

Abstract: In order to be completely adopted by industry, the Workflow Management Systems (WFMS) have to provide a more complete support to organisational processes. The cooperation is part of the missing features. In this paper, we propose to integrate a Computer Supported Cooperative Work system in a WFMS to solve the cooperation problem. This integration consists in an interoperability between the two systems thanks to the Meta-Object Facility and the inheritance. By describing the construction scenario of the bridge between the two systems, this paper shows the benefits in using the MOF for achieving interoperability.Keywords. Meta-modelling, interoperability, workflow.
Reducing Overheads of Local Communications in Fine-grain Parallel Computation
Authors: Jin-Soo Kim, Soonhoi Ha, Chu Shik Jhon
Venue: Proceedings of the international Conference on Parallel Processing (1997)

For fine-grain computation to be effective, the cost of communications between the large number of subtasks should be minimized. In this paper, we present an optimization technique which reduces overheads of communications between local subtasks by bypassing the network interface and transferring data directly from memory or registers to memory. On average, the optimization results in 35.6% improvement in total execution time on instruction-level simulations with six benchmark programs from 1 to 32 nodes.
Off Line Arabic Character Recognition - A Survey
Authors: Adnan Amin
Venue: Proceedings of the 4th International Conference on Document Analysis and Recognition (1997)

Machine simulation of human reading has been the subject of intensive research for almost three decades. A large number of research papers and reports have already been published on Latin, Chinese and Japanese characters. However, little work has been conducted on the automatic recognition of Arabic characters because of the complexity pf printed and handwritten text, and this problem is still an open research field. The main objective of this paper is to present the state of Arabic character recognition research throughout the last two decades.
Fault-Tolerant Deadline-Monotonic Algorithm for Scheduling Hard-Real-Time Tasks
Authors: Alan A. Bertossi, Andrea Fusiello, Luigi V. Mancini
Venue: Proceedings of the 11th International Symposium on Parallel Processing (1997)

This paper presents a new fault-tolerant scheduling algorithm for multiprocessor hard-real-time systems. The so called partitioning method is used to schedule a set of tasks in a multiprocessor system. Fault-tolerance is achieved by using a combined duplication technique where each task scheduled on a processor has either an active or a passive copy scheduled on a different processor. Simulation experiments reveal a saving of processors with respect to those needed by the usual approach of duplicating the schedule of the non-fault-tolerant case.
Exploring the Design Space of Future CMPs
Authors: Jaehyuk Huh, Doug Burger, Stephen W. Keckler
Venue: Proceedings of the 2001 International Conference on Parallel Architectures and Compilation Techniques (2001)

Abstract: In this paper, we study the space of chip multiprocessor (CMP) organizations. We compare the area and performance trade-offs for CMP implementations to determine how many processing cores future server CMPs should have, whether the cores should have in-order or out-of-order issue, and how big the per-processor on-chip caches should be. We find that, contrary to some conventional wisdom, out-of-order processing cores will maximize job throughput on future CMPs. As technology shrinks, limited off-chip bandwidth will begin to curtail the number of cores that can be effective on a single die. Current projections show that the transistor/signal pin ratio will increase by a factor of 45 between 180 and 35 nanometer technologies. That disparity will force increases in per-processor cache capacities as technology shrinks, from 128KB at 100nm, to 256KB at 70nm, and to 1MB at 50 and 35nm, reducing the number of cores that would otherwise be possible.
Predicting Queue Times on Space-Sharing Parallel Computers
Authors: Allen B. Downey
Venue: Proceedings of the 11th International Symposium on Parallel Processing (1997)

We present statistical techniques for predicting the queue times experienced by jobs submitted to a space-sharing parallel machine with first-come-first-served (FCFS) scheduling. We apply these techniques to trace data from the Intel Paragon at the San Diego Supercomputer Center and the IBM SP2 at the Cornell Theory Center. We show that it is possible to predict queue times with accuracy that is acceptable for several intended applications. The coefficient of correlation between our predicted queue times and the actual queue times from simulated schedules is between 0.65 and 0.72.
Multiple Templates Access of Trees in Parallel Memory Systems
Authors: Vincenzo Auletta, Amelia De Vivo, Vottorio Scarano
Venue: Proceedings of the 11th International Symposium on Parallel Processing (1997)

Studies the problem of mapping the N nodes of a data structure onto M memory modules so that they can be accessed in parallel by templates, i.e. distinct sets of nodes. In the literature, several algorithms are available for arrays (accessed by rows, columns, diagonals and subarrays) and trees (accessed by subtrees, root-to-leaf paths, etc.). Although some mapping algorithms for arrays allow conflict-free access to several templates at once (e.g. rows and columns), no mapping algorithm is known for efficiently accessing both subtree and root-to-leaf path templates in complete binary trees. We prove that any mapping algorithm that is conflict-free for one of these two templates has /spl Omega/(M/log M) conflicts on the other. Therefore, no mapping algorithm can be found that is conflict-free on both templates. We give an algorithm for mapping complete binary trees with N=2/sup M/-1 nodes on M memory modules in such a way that: (a) the number of conflicts for accessing a subtree template or a root-to-leaf path template is O[/spl radic/(M/logM)], (b) the load (i.e. the ratio between the maximum and minimum number of data items mapped on each module) is 1+o(1), and (c) the time complexity for retrieving the module where a given data item is stored is O(1) if a preprocessing phase of space and time complexity O(log N) is executed, or O(log log N) if no preprocessing is allowed.
Recovering the Structure of Software Systems Using Tube Graph Interconnection Clustering
Authors: Spiros Mancoridis, Richard C. Holt
Venue: Proceedings of the 1996 International Conference on Software Maintenance (1996)

An important product of the software design phase is the specification of the software structure at various levels of detail. Without reliable design documentation, significant software systems become less accessible to software engineers because structural information is buried in the intricate implementation source code. Reverse engineering techniques aim at recovering the structure of software systems, from the source code and mental models of developers, in order to make these systems more understandable to those maintaining them. Many reverse engineering techniques rely on creating a decomposition hierarchy by recursively clustering related software components (e.g., variables, procedures, classes, modules) into composite components (e.g., subsystems). Component clustering is necessary for managing complexity, and therefore is an important step in the reverse engineering process. In this paper, we argue that the clustering of interconnections is also necessary during reverse engineering. We propose an approach, based on a formalism called tube graphs, to specifying system structure that considers both composite software components and composite interconnections between these components. We present efficient algorithms for software interconnection clustering, which nicely complement existing software component clustering algorithms.
Effects of Decomposition Techniques on Knowledge-Based Program Understanding
Authors: Salwa K. Abd-El-Hafiz
Venue: Proceedings of the International Conference on Software Maintenance (1997)

This paper studies the effects of two different program decomposition techniques on knowledge-based program understanding. The first technique generates events which encapsulate program parts that are interdependent with respect to data flow. The second technique is program slicing. Both techniques are briefly described and the resulting slices and events are compared. An understanding of a program is formed by matching its events or slices against previously designed knowledge base plans. In order to have a detailed insight into the design and utilization of the knowledge base, we perform a two-phase case study. The first phase uses the decomposition results of a set of 65 loops to construct two different knowledge bases; one for recognizing loop events and the other for recognizing loop slices. This phase of the case study demonstrates the different design decisions made during the construction of the two knowledge bases. The second phase of the case study utilizes the previously designed plans in analyzing a set of 92 loops extracted from five randomly selected programs. Finally, the results of comparing the two decomposition techniques are summarized.
Characterization of Linear and Morphological Operators
Authors: Gerald J. F. Banon
Venue: Proceedings of the XII Brazilian Symposium on Computer Graphics and Image Processing (1999)

In image processing, the transformations of an image to another one are obtained through operators. Among the most important operators we have the linear operators and the morphological ones (dilations and erosions). In this talk we recall the definition of these operators and we present an algebraic characterization of them for the case of spatial invariance. The importance of this characterization is that it shows the differences and what are similar between the linear and morphological operators. It helps to understand how these operators are built.
Predicting Fault-Prone Software Modules in Embedded Systems with Classification Trees
Authors: Taghi M. Khoshgoftaar, Edward B. Allen
Venue: The 4th IEEE International Symposium on High-Assurance Systems Engineering (1999)

Embedded-computer systems have become essential elements of the modern world. For example, telecommunications systems are the backbone of society's information infrastructure. Embedded systems must have highly reliable software. The consequences of failures may be severe; down-time may not be tolerable; and repairs in remote locations are often expensive. Moreover, today's fast-moving technology marketplace mandates that embedded systems evolve, resulting in multiple software releases embedded in multiple products.Software quality models can be valuable tools for software engineering of embedded systems, because some software-enhancement techniques are so expensive or time-consuming that it is not practical to apply them to all modules. Targeting such enhancement techniques is an effective way to reduce the likelihood of faults discovered in the field. Research has shown software metrics to be useful predictors of software faults. A software quality model is developed using measurements and fault data from a past release. The calibrated model is then applied to modules currently under development. Such models yield predictions on a module-by-module basis.This paper examines the Classification And Regression Trees ( cart ) algorithm for predicting which software modules have high risk of faults to be discovered during operations. Cart is attractive because it emphasizes pruning to achieve robust models. This paper presents details on the cart algorithm in the context of software engineering of embedded systems. We illustrate this approach with a case study of four consecutive releases of software embedded in a large telecommunications system. The level of accuracy achieved in the case study would be useful to developers of an embedded system. The case study indicated that this model would continue to be useful over several releases as the system evolves.
Here, There and Everywhere: The Future of Software Engineering Education
Authors: J. Barrie Thompson
Venue: 23rd International Computer Software and Applications Conference (1999)

As the millennium comes to an end, we can step back and look at engineering in general. We can assess what has been achieved and look forward, perhaps with trepidation, to what the future holds. In traditional fields such as: civil, mechanical, electrical, and electronic engineering we can celebrate the successes that have been made. Mechanical engineering shaped the 19th century and electrical and electronic engineering the 20th . I personally have no doubts that it will be the products of Software Engineering (SE) that will shape the 21st century.