ppxscal/embedding_network huggingface dataset:
Modeling word occurrences for the compression of concordances
Authors: A. Bookstein, S. T. Klein, T. Raita
Venue: ACM Transactions on Information Systems (TOIS) (1997)

An earlier paper developed a procedure for compressing concordances, assuming that all alements occurred independently. The models introduced in that paper are extended here to take the possiblity of clustering into account. The concordance is conceptualized as a set of bitmaps, in which the bit locations reporesent documents, and the one-bits represent the occurrence of given terms. Hidden Markov Models (HMM's) are used to describe the clustering of the one-bits. However, for computational reasons, the HMM is approximated by traditional Markov models. A set of criteria is developed to constrain the allowable set of n-state models, and a full inventory is given for n &le; 4. Graph-theoretic reduction and complementation operations are defined among the various models and are used to provide a structure relating the models studied. Finally, the new methods were tested on the concordances of the English Bible and of two of the world's largest full-text retrieval systems: the Tre&acute;sor de la Langue Franc&cedil;aise and the Responsa Project.
Optimal L1-Rate of Convergence for The Viscosity Method and Monotone Scheme to Piecewise Constant Solutions with Shocks
Authors: Zhen-huan Teng, Pingwen Zhang
Venue: SIAM Journal on Numerical Analysis (1997)

We derive optimal error bounds for the viscosity method and monotone difference schemes to an initial-value problem of scalar conservation laws with initial data being a finite number of piecewise constants, subject to the initial discontinuities satisfying the entropy conditions. It is known that the entropy solution of the problem is piecewise constant with a finite number of interacting shocks satisfying the entropy conditions. A rigorous analysis shows that both the viscosity method and monotone schemes to approach the initial-value problem have uniform $L^1$-error bounds of $O(\epsilon)$ and $O(\Delta x)$ for the time $+\infty>t>0$, respectively, where $\epsilon$ and $\Delta x $ are their corresponding viscosity coefficient and discrete mesh length. The results are improvements over the half-order rates of $L^1$-convergence. Numerical experiments for the Lax--Friedrichs scheme are presented and numerical results justify the theoretical analysis.
Towards a Perfect CMOS CCII
Authors: Arie Arbel
Venue: Analog Integrated Circuits and Signal Processing (1997)

DC offset and inaccurate voltage follower action between terminals Y and X, the relatively high impedance seen at terminal X and inaccurate current follower action between terminals X and Z plague simple circuit realizations of the CCII. This paper summarizes the methods employed and compares the improvement of the CCII characteristics achieved by a variety of published circuits, with emphasis laid on CMOS realizations. In these comparisons, the conventionally employed but inaccurate current mirror output stages were replaced by a circuit employing current isolation and thereby providing accurate current follower action between terminals X and Z. Furthermore, two novel realizations of a differential CCII &ndash; based transconductance amplifier are described, which can also be employed as input stage of an instrumentation voltage amplifier exhibiting an exceptionally high CMRR and excellent frequency response. Finally, a current fan out circuit for cascode CCII &ndash;&lsquo;s will be introduced, whose transfer function value is electronically adjustable.
Consistent overhead byte stuffing
Authors: Stuart Cheshire, Mary Baker
Venue: ACM SIGCOMM Computer Communication Review (1997)

Byte stuffing is a process that transforms a sequence of data bytes that may contain 'illegal' or 'reserved' values into a potentially longer sequence that contains no occurrences of those values. The extra length is referred to in this paper as the overhead of the algorithm.To date, byte stuffing algorithms, such as those used by SLIP [RFC1055], PPP [RFC1662] and AX.25 [ARRL84], have been designed to incur low average overhead but have made little effort to minimize worst case overhead.Some increasingly popular network devices, however, care more about the worst case. For example, the transmission time for ISM-band packet radio transmitters is strictly limited by FCC regulation. To adhere to this regulation, the practice is to set the maximum packet size artificially low so that no packet, even after worst case overhead, can exceed the transmission time limit.This paper presents a new byte stuffing algorithm, called Consistent Overhead Byte Stuffing (COBS), that tightly bounds the worst case overhead. It guarantees in the worst case to add no more than one byte in 254 to any packet. Furthermore, the algorithm is computationally cheap, and its average overhead is very competitive with that of existing algorithms.
On path selection in combinational logic circuits
Authors: Wing Ning Li, Sudhakar M. Reddy, Sartaj Sahni
Venue: Proceedings of the 25th ACM/IEEE Design Automation Conference (1988)

In order to ascertain correct operation of digital logic circuits it is necessary to verify correct functional operation as well as correct operation at desired clock rates. To ascertain correct operation at desired clock rates signal propagation delays along a set of selected paths are verified to fall within allowed limits by applying appropriate stimuli. Earlier it was suggested that an appropriate set of paths to test would be the one that includes at least one path, with maximum modeled delay, for each circuit lead or gate input. In this paper, algorithms to select such sets of paths with minimum cardinality are given.
Test Generation for Multiple State-Table Faults in Finite-State Machines
Authors: Irith Pomeranz, Sudhakar M. Reddy
Venue: IEEE Transactions on Computers (1997)

A test generation procedure to detect multiple state-table faults in finite-state machines is proposed. The importance of multiple state-table faults and their advantages as test generation objectives to avoid the need for checking experiments are considered. The proposed procedure is based on a new method for implicit enumeration of large numbers of multiple faults by using incompletely specified faulty machines. Experimental results are presented to demonstrate the effectiveness of implicit fault enumeration in detecting large numbers of multiple faults and in guaranteeing detection of all the faults or all the faults up to a specific multiplicity.
Efficient Invariant Representations
Authors: Peter Meer, Reiner Lenz, Sudhir Ramakrishna
Venue: International Journal of Computer Vision (1998)

Invariant representations are frequently used in computer vision algorithms to eliminate the effect of an unknown transformation of the data. These representations, however, depend on the order in which the features are considered in the computations. We introduce the class of projective/permutation p^2-invariants which are insensitive to the labeling of the feature set. A general method to compute the p^2-invariant of a point set (or of its dual) in the n-dimensional projective space is given. The one-to-one mapping between n + 3 points and the components of their p^2-invariant representation makes it possible to design correspondence algorithms with superior tolerance to positional errors. An algorithm for coplanar points in projective correspondence is described as an application, and its performance is investigated. The use of p^2-invariants as an indexing tool in object recognition systems may also be of interest.
Increasing throughput in ATM/B-ISDN using simple buffer management and selective discarding
Authors: Samir Chatterjee, Wen Xiao
Venue: ACM SIGCOMM Computer Communication Review (1997)

If the reliability provided by the network is lower than that requested by the application, the error and flow control systems in the end-nodes must make up for the difference. While most applications use retransmission based schemes to recover lost data, ARQ based closed loop techniques may not be suitable for many new applications. Time sensitive information requiring no-loss of data would constitute a major segment of the emerging traffic (interactive web, videophones, CSCW) that typically employ Forward Error Correction (FEC) codes. Such codes send redundant information which help to recover lost data without retransmission. This paper shows that just plain FEC is not enough when one considers the fragmentation effects that takes place when legacy networks interwork with ATM. Simple yet powerful buffer management techniques can yield higher throughput thereby reducing block loss rates. A combination of a gatekeeping operation along with janitor routine that cleans up the buffer to preserve frames on an end-to-end basis is proposed. A simulation study demonstrates positive results. The proposed schemes even point towards efficient sizing of ATM switch buffers which guarantee no-loss transport of real-time information.
On-Line Fault Resilience Through Gracefully Degradable ASICs
Authors: Alex Orailoğlu
Venue: Journal of Electronic Testing: Theory and Applications (1998)

We present two novel reconfiguration schemes, L/U reconfiguration and its generalization, band reconfiguration, to achieve graceful degradation for general microarchitecture datapaths. Upon detection of a datapath fault, hardware and algorithmic reconfigurations are performed dynamically through operation rescheduling and hardware rebinding. Instead of a complete shuffling, the proposed scheme perturbs the original schedule and binding in a systematic fashion. This regularity of the scheme allows well-structured design planning for the controller and the datapath. The underlying microarchitecture supporting such reconfiguration schemes is briefly outlined. Experimental evidence indicates negligible performance and small hardware overheads.
Post-route optimization for improved yield using a rubber-band wiring model
Authors: Jeffrey Z. Su, Wayne W. Dai
Venue: Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design (1997)

This paper presents a unique approach to improve yield given a routed layout. Currently after routing has been completed and compacted, it generally proceeds to verification without further modifications. However, to improve manufacturability, we introduce a concept called even wire distribution, a key element of the SURF physical design tool. To alleviate congestion, we first move vias and wires torwards less dense areas in a manner which preserves the existing wiring paths. Depending on locally available area, we then increase wire spacing to reduce defect sensitivity, without changing the area of the design. Carafe, an inductive fault analysis tool is used to evaluate the new layout.
Hardware/software partitioning and pipelining
Authors: Smita Bakshi, Daniel D. Gajski
Venue: Proceedings of the 34th annual Design Automation Conference (1997)

For a given throughput constrained system-level specification,we present a design flow and an algorithm to select software(general purpose processors) and hardware components,and then partition and pipeline the specification amongstthe selected components.This is done so as to beat satisfythe throughput constraint at minimal hardware cost.Ourability to pipeline the design at several levels, enables us toattain high throughput designs, and also distinguishes ourwork from previously proposed hardware/software partitioning algorithms.
Efficient Region Tracking With Parametric Models of Geometry and Illumination
Authors: Gregory D. Hager, Peter N. Belhumeur
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1998)

As an object moves through the field of view of a camera, the images of the object may change dramatically. This is not simply due to the translation of the object across the image plane. Rather, complications arise due to the fact that the object undergoes changes in pose relative to the viewing camera, changes in illumination relative to light sources, and may even become partially or fully occluded. In this paper, we develop an efficient, general framework for object tracking¿one which addresses each of these complications. We first develop a computationally efficient method for handling the geometric distortions produced by changes in pose. We then combine geometry and illumination into an algorithm that tracks large image regions using no more computation than would be required to track with no accommodation for illumination changes. Finally, we augment these methods with techniques from robust statistics and treat occluded regions on the object as statistical outliers. Throughout, we present experimental results performed on live video sequences demonstrating the effectiveness and efficiency of our methods.
Efficient Hardware Hashing Functions for High Performance Computers
Authors: M. V. Ramakrishna, E. Fu, E. Bahcekapili
Venue: IEEE Transactions on Computers (1997)

Hashing is critical for high performance computer architecture. Hashing is used extensively in hardware applications, such as page tables, for address translation. Bit extraction and exclusive ORing hashing "methods" are two commonly used hashing functions for hardware applications. There is no study of the performance of these functions and no mention anywhere of the practical performance of the hashing functions in comparison with the theoretical performance prediction of hashing schemes. In this paper, we show that, by choosing hashing functions at random from a particular class, called H3, of hashing functions, the analytical performance of hashing can be achieved in practice on real-life data. Our results about the expected worst case performance of hashing are of special significance, as they provide evidence for earlier theoretical predictions.
The Number of Independent Sets in a Grid Graph
Authors: Neil J. Calkin, Herbert S. Wilf
Venue: SIAM Journal on Discrete Mathematics (1998)

If f(m,n) is the (vertex) independence number of the $m\times n$ grid graph, then we show that the double limit $\eta\eqdef\lim_{m,n\to\infty}f(m,n)^{1\over {mn}}$ exists, thereby refining earlier results of Weber [Rostock. Math. Kolloq., 34 (1988), pp. 28--36] and Engel [Fibonacci Quart.,, 28 (1990), pp. 72--78]. We establish upper and lower bounds for $\eta$ and {\it prove} that $1.503047782... \le \eta \le 1.5035148\ldots $. Numerical computations suggest that the true value of $\eta$ (the "hard square constant") is around 1.5030480824753323... .
Scheduling techniques for variable voltage low power designs
Authors: Yann-Rue Lin, Cheng-Tsung Hwang, Allen C.-H. Wu
Venue: ACM Transactions on Design Automation of Electronic Systems (TODAES) (1997)

This paper presents an integer linear programming (ILP) model and a heuristic for the variable voltage scheduling problem. We present the variable voltage scheduling techniques that consider in turn timing constraints alone, resource constraints alone, and timing and resource constraints together for design space exploration. Experimental results show that our heuristic produces results competitive with those of the ILP method in a fraction of the run-time. The results also show that a wide range of design alternatives can be generated using our design space exploration method. Using different cost/delay combinations, power consumption in a single design can differ by as much as a factor of 6 when using mixed 3.3V and 5V supply voltages.
Compiler-directed data prefetching in multiprocessors with memory hierarchies
Authors: Edward H. Gornish, Elana D. Granston, Alexander V. Veidenbaum
Venue: Proceedings of the 4th international conference on Supercomputing (1990)

Memory hierarchies are used by multiprocessor systems to reduce large memory access times. It is necessary to automatically manage such a hierarchy, to obtain effective memory utilization. In this paper, we discuss the various issues involved in obtaining an optimal memory management strategy for a memory hierarchy. We present an algorithm for finding the earliest point in a program that a block of data can be prefetched. This determination is based on the control and data dependencies in the program. Such a method is an integral part of more general memory management algorithms. We demonstrate our method's potential by using static analysis to estimate the performance improvement afforded by our prefetching strategy and to analyze the reference patterns in a set of Fortran benchmarks. We also study the effectiveness of prefetching in a realistic shared-memory system using an RTL-level simulator and real codes. This differs from previous studies by considering prefetching benefits in the presence of network contention.
CORAL II: linking behavior and structure in an IC design system
Authors: Robert L. Blackburn, Donald E. Thomas, Patti M. Koenig
Venue: Proceedings of the 25th ACM/IEEE Design Automation Conference (1988)

This paper describes a technique for maintaining very fine grained links between a behavioral specification and an automatically generated VLSI structural implementation. CORAL II execedes previous systems in the scope of design representations involved and the complexity of the relationships handled. The design representations used are described, as are the behavioral transformations that may be applied and the types of design choices that may be made. The complications introduced by these transformations and design decisions are discussed. Some possible applications of this work are outlined and an existing graphical interface for examining the synthesized design and its relationship to the behavioral specification is described.
Slicing real-time programs for enhanced schedulability
Authors: Richard Gerber, Seongsoo Hong
Venue: ACM Transactions on Programming Languages and Systems (TOPLAS) (1997)

In this article we present a compiler-based technique to help develop correct real-time systems. The domain we consider is that of multiprogrammed real-time applications, in which periodic tasks control physical systems via interacting with external sensors and actuators. While a system is up and running, these operations must be performed as specified&mdash;otherwise the system may fail. Correctness depends not only on each program individually, but also on the time-multiplexed behavior of all of the programs running together. Errors due to overloaded resources are exposed very late in a development process, and often at runtime. They are usually remedied by human-intensive activities such as instrumentation, measurement, code tuning and redesign. We describe a static alternative to this process, which relies on well-accepted technologies from optimizing compilers and fixed-priority scheduling. Specifically, when a set of tasks are found to be overloaded, a scheduling analyzer determines candidate tasks to be transformed via program slicing. The slicing engine decomposes each of the selected tasks into two fragments: one that is &ldquo;time critical&rdquo; and the other &ldquo;unobservable.&rdquo; The unobservable part is then spliced to the end of the time-critical code, with the external semantics being maintained. The benefit is that the scheduler may postpone the unobservable code beyond its original deadline, which can enhance overall schedulability. While the optimization is completely local, the improvement is realized globally, for the entire task set.
Browsing in chip design database
Authors: David Gedye, Randy Katz
Venue: Proceedings of the 25th ACM/IEEE Design Automation Conference (1988)

A design browser is a tool for exploring the interconnected web of design objects managed by a CAD database. The browser described in this paper is the first such tool to present this information graphically&mdash;directed graphs are drawn to show the relationships that exist between objects in the database. Since graphs can become very large, techniques referred to as rectangular and hourglass pruning have been developed to reduce the information displayed to a manageable level. This browser allows designers to visualize the rich, multidimensional structure of their designs.
Load distribution and balancing support in a workstation-based distributed system
Authors: D. Arredondo, M. Errecalde, F. Piccoli, M. Printista, R. Gallard, s. Flores
Venue: ACM SIGOPS Operating Systems Review (1997)

In distributed systems, load distribution and balancing are primary functions addressed to improvements on system performance and additional user comfort. Incoming task allocation and remote process execution are main responsibilities of a well designed system to achieve such performance improvements. Both aspects involve a number of non trivial tasks.As a basement for further automatic system decision in a distributed environment, this paper propose a user-supervised processor allocation scheduler, shows which information should be collected and when and how to collect and disseminate it to support the user decision.The main problems to be considered when implementing remote process execution are discussed and a design for an alternative system attempting to solve these problems is also shown.
Overview of standardized time series
Authors: Lee Schruben
Venue: Proceedings of the 17th conference on Winter simulation (1985)

This paper presents the basic concepts and motivation for standardized time series analysis. Various applications to the analysis of simulation output are mentioned.
Improved Compressions of Cube-Connected Cycles Networks
Authors: Ralf Klasing
Venue: IEEE Transactions on Parallel and Distributed Systems (1998)

We present a new technique for the embedding of large cube-connected cycles networks (CCC) into smaller ones, a problem that arises when algorithms designed for an architecture of an ideal size are to be executed on an existing architecture of a fixed size. Using the new embedding strategy, we show that the CCC of dimension l can be embedded into the CCC of dimension k with dilation 1 and optimum load for any k, $l \in {\hbox{\sl{\rlap{N}\kern1.5pt{\hbox{N}}}}},$k¿ 8, such ${\textstyle{5 \over 3}}+c_k
Pragmatic subtyping in polymorphic languages
Authors: Johan Nordlander
Venue: ACM SIGPLAN Notices (1999)

We present a subtyping extension to the Hindley/Milner type system that is based on name inequivalence. This approach allows the subtype relation to be defined by incremental construction of polymorphic records and datatypes, in a way that subsumes the basic type systems of both languages like ML and Java. As the main contribution of the paper, we describe a partial type inference algorithm for the extended system which favours succinctness over generality, in the sense that it never infers types with subtype constraints. The algorithm is based on an efficient approximating constraint solver, and is able to type a wide range of programs that utilize subtyping and polymorphism in a non-trivial way. Since constrained types are not inferred, the algorithm cannot be complete; however, we provide a completeness result w.r.t. the Hindley/Milner type system as a form of characterizing lower bound.