ppxscal/embedding_network huggingface dataset:
Message Extraction from Printed Documents - A Complete Solution
Authors: Stephan Baumann, M. Ben Hadj Ali, Andreas Dengel, Thorsten Jäger, Michael Malburg, Achim Weigel, Claudia Wenzel
Venue: Proceedings of the 4th International Conference on Document Analysis and Recognition (1997)

The task to be solved within our core research was the design and development of a document analysis toolbox covering typical document analysis tasks such as document understanding, information extraction and textrecognition. In order to prove feasibility of our concepts, we have developed the prototypical analysis system OfficeMAID. The system analyzes documents, as used in the daily work of a purchasing department, by a-priori knowledge about workflows and document features. In this way the system provides goal-directed information extraction, shallow understanding and process identification for given documents (paper,fax,e-mail).
Low power and high speed multiplication design through mixed number representations
Authors: Menghui Zheng, Alexander Albicki
Venue: Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors (1995)

A low power multiplication algorithm and its VLSI architecture using a mixed number representation is proposed. The reduced switching activity and low power dissipation are achieved through the Sign-Magnitude (SM) notation for the multiplicand and through a novel design of the Redundant Binary (RB) adder and Booth decoder. The high speed operation is achieved through the Carry-Propagation-Free (CPF) accumulation of the Partial Products (PP) by using the RB notation. Analysis showed that the switching activity in the PP generation process can be reduced on average by 90%. Compared to the same type of multipliers, the proposed design dissipates much less power and is 18% faster on average.
FPGA global routing based on a new congestion metric
Authors: Yao-Wen Chang, D. F. Wong, C. K. Wong
Venue: Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors (1995)

Unlike traditional ASIC routing, the feasibility of routing in FPGAs is constrained not only by the available space within a routing region, but also by the routing capacity of a switch block. Recent work has established the switch-block capacity as a superior congestion-control metric for FPGA global routing. However, the work has two deficiencies: (1) its algorithm for computing the switch-block capacity is not efficient, and (2) it, as well as the other recent works only modeled one type of routing segments-single-length lines. To remedy the deficiencies, we present in this paper efficient algorithms for obtaining the switch-block capacity and a graph modeling for routing on the new generation FPGAs with a versatile set of segment lengths. Experiments show that our algorithms dramatically reduce the run times for obtaining the switch-block capacities. Experiments with a global router based on the switch-block and channel densities for congestion control show a significant improvement in the area performance, compared with one based on the traditional congestion metric.
A Graph Based Framework to Detect Optimal Memory Layouts for Improving Data Locality
Authors: Mahmut T. Kandemir, Alok N. Choudhary, J. Ramanujam, Prithviraj Banerjee
Venue: Proceedings of the 13th International Symposium on Parallel Processing and the 10th Symposium on Parallel and Distributed Processing (1999)

In order to extract high levels of performance from modern parallel architectures, the effective management of deep memory hierarchies is very important. While architectural advances in caches help in better utilization of the memory hierarchy, compiler-directed locality enhancement techniques are also important. In this paper we propose a locality improvement technique that uses data space (array layout) transformations in contrast to most of the previous work based on iteration space (loop) transformations. In other words, rather than changing the order of loop iterations, our technique modifies the memory layouts of multi-dimensional arrays. In comparison with previous work on data transformations it brings two novelties. First, we formulate the problem on a special graph structure called the layout graph (LG) and use integer linear programming (ILP) methods to determine optimal layouts. Second, in addition to static layout detection, our approach also enables the compiler to determine optimal dynamic layouts; that is, the layouts that can be changed across loop nest boundaries. We believe that this is the first attempt to determine optimal dynamic memory layouts. We also present preliminary experimental results on the SGI Origin 2000 distributed shared memory multiprocessor. Our results so far are encouraging and indicate that the additional compilation time taken by the solver is tolerable
Web for Data Mining Applications
Authors: Bing Liu, Yiming Ma, Ching Kian Wong
Venue: 24th International Computer Software and Applications Conference (2000)

The Web not only contains a huge amount of information, but also provides a powerful infrastructure for communication and information sharing. While mining for valuable information or resources from the Web is an active research area, in this paper, we focus on discussing the use of the Web for data mining applications. In particular, we show that the Web can be used to facilitate delivering and interpreting a set of discovered rules.
Active Artefact Management for Distributed Software Engineerin
Authors: Cornelia Boldyreff, David Nutter, Stephen Rank
Venue: Proceedings of the 26th International Computer Software and Applications Conference on Prolonging Software Life: Development and Redevelopment (2002)

We describe a software artefact repository that provides its contents with some awareness of their own creation. "Active" artefacts are distinguished from their passive counterparts by their enriched meta-data model which reflects the work-flow process that created them, the actors responsible, the actions taken to change the artefact, and various other pieces of organisational knowledge. This enriched view of an artefact is intended to support re-use ofboth software and the expertise gained when creating the software. Unlike other organisational knowledge systems, the meta-data is intrinsically part of the artefact and maybe populated automatically from sources including existing data-format specific information, user supplied data and records of communication.Such a system is of increased importance in the world of "virtual teams" where transmission of vital organisational knowledge, at best difficult, is further constrained by thelack of direct contact between engineers and differing development cultures.
COM: what makes it work, black-box encapsulation through multiple, immutable interfaces
Authors: Charles Kindel
Venue: Proceedings of the 1st International Conference on Enterprise Distributed Object Computing (1997)

The Component Object Model (COM) (and by definition, DCOM) is the only component system where there is a significant market for commercially available components. This paper discusses the elements of COM's design that have all contributed to making COM such a viable commercial reality: black box-encapsulation, interfaces, interface immutability, multiple interfaces, and location transparency.
FLORID: A Prototype for F-Logic
Authors: Jürgen Frohn, Rainer Himmeröder, Paul-Thomas Kandzia, Georg Lausen, Christian Schlepphorst
Venue: Proceedings of the Thirteenth International Conference on Data Engineering (1997)

FLORID - F-LOgic Reasoning In Databases - is a deductive object-oriented database system incorporating F-logic as data definition and query language and combining the advantages of deductive databases with the rich modelling capabilities of object oriented concepts. F-logic provides complex objects, uniform handling of data and metadata, rule-defined class hierarchy and signatures, non-monotonic multiple inheritance, equating of objects by rules and variables ranging over methods and classes. Moreover, FLORID extends F-logic by path expressions to facilitate object navigation.
Intra-agent modality and nonmonotonic epistemic logic
Authors: Richmond H. Thomason
Venue: Proceedings of the 7th conference on Theoretical aspects of rationality and knowledge (1998)

It is plausible to think that simulation is perhaps the most important reasoning tool that we have for user modeling. This is behind what we mean when we say that a superlative fisherman can "think like a fish." The fisherman decides where the fish must be by imaging where <i>he</i> would be in this river if he were a fish.
A self-timed redundant-binary number to binary number converter for digital arithmetic processors
Authors: Chin-Long Wey, Haiyan Wang, Cheng-Ping Wang
Venue: Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors (1995)

This paper presents a self-timed converter circuit which converts an n-digit redundant binary number to an (n+1)-bit binary number. Self-timed refers to the fact that the conversion is problem-dependent and requires variable conversion time to complete the operation. The propagation delay of the proposed converter circuit does not increase with the number of digits to be converted, but it is determined by the maximum number of consecutive 0's in that number. This study shows that the statistical upper bound of the average maximum number of consecutive 0's is log/sub 3/n, or 3.78 for 64-digits. This implies that the proposed self-time circuit can be approximately 17 times faster than the ripple-type converter. Thus the proposed converter is well-suited to high-speed, long-word digital arithmetic processors.
A general purpose sparse matrix parallel solvers package
Authors: Hong Q. Ding, Robert D. Ferraro
Venue: Proceedings of the 9th International Symposium on Parallel Processing (1995)

A package of three parallel solvers with a unified user interface is developed for sparse symmetric complex linear systems arising from the discretization of partial differential equations on unstructured meshes. Once the data interface is set up, the package constructs the sparse symmetric complex matrix, and solves the linear system using one of the following methods: a bi-conjugate gradient solver, a two-stage Cholesky LDL/sup T/ factorization, or a hybrid solver combining the above two methods. The user deals only with local matrices on local mesh partitions in each processor. Scaling problem size N with the number of processors P with N/P fixed, test runs on Intel Delta up to 28 processors show that the bi-conjugate gradient method scales linearly with N whereas the hybrid method scales as /spl radic/N.
An Integrated Solution for Creating Dependable Software
Authors: W. Eric Wong
Venue: 24th International Computer Software and Applications Conference (2000)

Software testing and maintenance are the two most expensive phases of the software life cycle. Why? And why, in general, are customers not satisfied with the quality of software? Studies have shown that approximately 20% of a software system is responsible for 80% of the faults; and over the lifetime of an average software system, as much as 70% of the cost is estimated to be dedicated to testing and maintenance. Clearly, an appropriate methodology ought to be employed to address these high-leverage concerns. With the increased emphasis on software quality and the pressure to deliver software faster and cheaper, such a methodology should encompass software design, architecture, development, testing, and maintenance as a whole, and provide an integrated solution that leads to the creation of more dependable software. In addition, it is also crucial to have a set of effective tools with user-friendly interfaces available to software practitioners to apply this methodology in real-life contexts. In this presentation, we will explain how to take advantage of sophisticated analysis of the dynamic behavior of the software being developed to help programmers, as well as testers, accomplish their assignments more effectively and efficiently. The ACM Portal is published by the Association for Computing Machinery. Copyright © 2010 ACM, Inc. Terms of Usage Privacy Policy Code of Ethics Contact Us Useful downloads: Adobe Acrobat QuickTime Windows Media Player Real Player
Architectural Integration Styles for Large-Scale Enterprise Software Systems
Authors: Jonas Andersson, Pontus Johnson
Venue: Proceedings of the 5th IEEE International Conference on Enterprise Distributed Object Computing (2001)

Abstract: A predominant problem in the management of large-scale enterprise software systems is application integration. Despite the considerable efforts spent on the development of new standards and technologies for software interoperation, the integration of systems that originally were not designed to interact with each other is a major undertaking, requiring in-depth knowledge of existing systems, incorporation of integration products, and development and/or parameterization of various kinds of adapters and gateways. This article presents the concept of architectural integration styles, i.e. architectural styles describing software structures of integration solutions for enterprise software systems. The article further proposes an approach for selection of styles based on the characteristics of the existing software applications and the desired quality attributes of the integrated system. A number of architectural integration styles for enterprise systems are presented in the article, and a case study of the style selection process applied to a mid-sized Swedish electricity retailer is described.
Classifying Images Collected on the World Wide Web
Authors: Camillo Jorge Santos Oliveira, Arnaldo de Albuquerque Araújo, Carlos Alberto Severiano,  Jr., Daniel Ribeiro Gomes
Venue: Proceedings of the 15th Brazilian Symposium on Computer Graphics and Image Processing (2002)

This work presents the classification of images collected on the World Wide Web, using a supervised classification method, called ID3 (Itemized Dichotomizer 3). The classification consists in separating the images into two semantic classes: graphics and photographs. Photographs include natural scenes, like people, faces, animals, flowers, landscapes and cities. Graphics are logos, drawings, icons, maps, and backgrounds, usually generated by computer. To validate the classifier we used the k-fold cross-validation method. In the experimental tests 95.6% of the images were correctly classified.
On QOS Mapping in Multimedia Networks
Authors: Jean-Francois Huard, Aurel A. Lazar
Venue: Proceedings of the 21st International Computer Software and Applications Conference (1997)

A framework for studying QOS mapping between various levels in the information transport protocol stack and a platform for evaluating the mapping rules by performing concurrent network and application level measurements of QOS are presented. An empirical loss mapping rule between the application (frame) level and network (cell) level is given. The rule was tested using two 10 minutes motion JPEG video clips and a 30 minutes MPEG-2 VBR video clip under 55 different network load conditions and gives results within a 3% error margin.
Load Balancing and Workload Minimization Of Overlapping Parallel Tasks
Authors: Venkatram Krishnaswamy, Gagan Hasteer, Prithviraj Banerjee
Venue: Proceedings of the international Conference on Parallel Processing (1997)

In this paper, we propose a unique problem in the assignment of overlapping tasks to processors on a parallel machine, with the twin objectives of minimizing workloads while maintaining good load balance. This problem arises in some applications in VLSI CAD, e.g. parallel compiled VHDL simulation. We assume that the parallel application can be decomposed into a set of tasks, each in turn comprising a finite number of subtasks. Overlapped computations arise as a result of replication of subtasks across tasks in order to reduce the amount of communication performed in fine grained parallel applications. The uniqueness of the problem stems from the fact that overlapping computation on tasks assigned to the same processor is only performed once. Theoretical results on NP-hardness and bounds on the utilization of overlap are provided. A heuristic solution is also proposed. An important application area in VLSI-CAD, parallel compiled event driven VHDL simulation is introduced. Results of the application of our heuristics to this problem are reported on a SUN Sparcserver 1000 multiprocessor.
A Reliable Hardware Barrier Synchronization Scheme
Authors: Rajeev Sivaram, Craig B. Stunkel, Dhabaleswar K. Panda
Venue: Proceedings of the 11th International Symposium on Parallel Processing (1997)

Barrier synchronization is a crucial operation for parallel systems. Many schemes have been proposed in the literature to achieve fast barrier synchronization through software, hardware, or a combination of these mechanisms. However, few of these schemes emphasize fault-tolerant barrier operations. In this paper, we describe inexpensive support that can be added to network switches for achieving reliable hardware-based barrier synchronization while recovering from lost or corrupted messages. Necessary modifications to the switch architecture and the associated fault-tolerant message-passing protocols are presented. The protocols are optimized for the no-fault case while providing means to detect the failure of any step of the operation and to recover from it. The proposed scheme shows significant potential for use in parallel systems, especially the emerging systems based on networks of workstations.
A Parallel Algorithm for Bound-Smoothing
Authors: Kumar Rajan, Narsingh Deo
Venue: Proceedings of the 13th International Symposium on Parallel Processing and the 10th Symposium on Parallel and Distributed Processing (1999)

Determining molecular structure from interatomic distances is an important and challenging problem. Given a molecule with n atoms, lower and upper bounds on interatomic distances can usually be obtained only for a small subset of the n(n - 1/2) atom pairs, using NMR. Given the bounds so obtained on the distances between some of the atom pairs, it is often useful to compute tight bounds on all the n(n - 1/2) pairwise distances. This process is referred to as bound-smoothing. The initial lower and upper bounds for the pairwise distances not measured are usually assumed to be 0 and 1.One method for bound-smoothing is to use the limits imposed by the triangle inequality. The distance bounds so obtained can often be tightened further by applying the tetrangle inequality - the limits imposed on the six pairwise distances among a set of four atoms (instead of three for the triangle inequalities). The tetrangle inequality is expressed by the Cayley-Menger determinants. For every quadruple of atoms, each pass of the tetrangle-inequality bound-smoothing procedure finds upper and lower limits on each of the six distances in the quadruple. Applying the tetrangle inequalities to each of the (n/4) quadruples requires T (n4) time. Here, we propose a parallel algorithm for bound-smoothing employing the tetrangle inequality. Each pass of our algorithm requires T (n3 log n) time on a CREW PRAM with T (n/log n) processors. An implementation of this parallel algorithm on the Intel Paragon XP/S and its performance are also discussed.
A Hybrid Time Synchronization Implemented Through Special Ring Array for Mesh or Torus
Authors: Yuzhong Sun, Zhiwei Xu, Mingfa Zhu
Venue: Proceedings of the 11th International Symposium on Parallel Processing (1997)

In this paper, we present a new efficient hybrid time synchronization scheme for a mesh or torus interconnection networks, called ROCTS. ROCTS comprises two levels, one for the lower level that is implemented over a special high-speed ring array, one for the mesh or torus network. In ROCTS, the second network we construct is different from the past, which is a ring array with each ring not connected to any other. So, we can implement ROCTS in a distributed and fault-tolerant way. On the other hand, we combine the advantages of hardware and linear-envelope methods so that we can improve the performance of time synchronization even if the work load on a mesh or torus network is not uniform or even the blocked nodes occur. In this paper, we also analyze the performance of ROCTS and present the maximum clock skew and the successful time synchronization probability so that we prove that ROCTS can guarantee a much smaller bound on the clock skew, e.g. 10us for 300*300 mesh or torus networks, than most existing time synchronization schemes.
Subquery Elimination: A Complete Unnesting Algorithm for an Extended Relational Algebra
Authors: Pedro Celis, Hansjörg Zeller
Venue: Proceedings of the Thirteenth International Conference on Data Engineering (1997)

Summary form only given, as follows. Research in the area of subquery unnesting algorithms has mostly focused on the problem of making queries more efficient at run-time by transforming subqueries into joins. Unnesting rules describe a transformation of a nested query tree or a nested SQL query into an equivalent tree or SQL query that is no longer nested. However, it is not possible to express all nested queries in a non-nested form, unless the used language (relational algebra or ISO/ANSI SQL) is extended. This means that a database system must continue to have the ability to process subqueries. When working on a new optimizer and executor design for NonStop SQL, our development team was faced with a slightly different problem: we wanted to eliminate the need for optimization and execution of nested queries altogether and were looking for a complete subquery unnesting process. Such a process would allow us to develop a query optimizer and executor that do not need to process subqueries. Our goal was to make use of the existing unnesting algorithms and to extend them in a way that does not necessarily improve or change the execution characteristics of nested queries, but that leads to complete unnesting of all forms of nested queries, as defined by the "full" level of the ISO/ANSI SQL92 standard. To indicate this different approach we call it "subquery elimination" rather than "subquery unnesting".
SuperWeb: Towards a Global Web-Based Parallel Computing Infrastructure
Authors: Klaus E. Schauser, Chris J. Scheiman, Gyung-Leen Park, Behrooz Shirazi, Jeff Marquis
Venue: Proceedings of the 11th International Symposium on Parallel Processing (1997)

The Internet, best known by most users as the World-Wide-Web, continues to expand at an amazing pace. We propose a new infrastructure to harness the combined resources, such as CPU cycles or disk storage, and make them available to everyone interested. This infrastructure has the potential for solving parallel supercomputing applications involving thousands of cooperating components. Our approach is based on recent advances in Internet connectivity and the implementation of safe distributed computing embodied in languages such as Java.
Fault-Tolerant Multiple Bus Networks for Fan-In Algorithms
Authors: Ramachandran Vaidyanathan, Sudharani Nadella
Venue: Proceedings of the 10th International Parallel Processing Symposium (1996)

We consider a large class of algorithms called "Fan-in algorithms'' that are useful for problems involving semigroup operations. This paper deals with the design of fault-tolerant multiple bus networks (MBNs) suited to run Fan-in algorithms. We present two methods for constructing Fan-in MBNs with tolerance to bus faults, that have nearly optimal performance and processor fan-out. We also present a general framework that converts any Fan-in MBN (including those resilient to bus faults) into one with tolerance to processor faults, and for which faulty processors slow the original algorithm (for fault-free processors) by only one step. Keywords: Fault-tolerance, Interconnection networks, Multiple bus networks, Fan-in algorithms, Parallel processing