ppxscal/embedding_network huggingface dataset:
A comparison of architectural support for messaging in the TMC CM-5 and the Cray T3D
Authors: Vijay Karamcheti, Andrew A. Chien
Venue: ACM SIGARCH Computer Architecture News (1995)

Programming models based on messaging continue to be an important programming model for parallel machines. Messaging costs are strongly influenced by a machine's network interface architecture. We examine the impact of architectural support for messaging in two machines --- the TMC CM-5 and the Cray T3D --- by exploring the design and performance of several messaging implementations. The additional features in the T3D support remote operations: memory access, fetch-and-increment, atomic swaps, and prefetch.Experiments on the CM-5 show that requiring processor involvement for message reception can increase the communication overheads from 60% to 300% for moderate variations in computation grain size at the destination. In contrast, the T3D hardware for remote operations decouples message reception from processor activity, producing high-performance messaging independent of computation grain size or variability.In addition, hardware support for a shared address space in the T3D can be used to solve the output contention problem (output hot spots), producing messaging implementations that are robust over a wide variety of traffic patterns. Atomic swap hardware can be used to build a distributed message queue, enabling a "pull" messaging scheme where the destination requests data transfer upon receive. This scheme uses prefetches to mask receive latency. While this yields performance robust over output contention, its base cost is competitive only for small messages (up to 64 bytes) because of the high cost of issuing and resolving prefetches in the T3D. Emulation shows that if the interaction costs can be reduced by a factor of eight (250ns to 31ns), perhaps by moving the prefetch queue on chip, and there is a corresponding increase in the prefetch queue size, the pull scheme can give superior performance in all eases.
Near-optimality of distributed load-adaptive dynamic channel allocation strategies for cellular mobile networks
Authors: Andrea Baiocchi, Fabrizio Sestini
Venue: Wireless Networks (1996)

In this paper we focus on the so-called load-adaptive Dynamic Channel Allocation (DCA) strategies for cellular mobile networks. Such strategies envisage the dynamic assignment of radio resources with the constraint that the outage probability (i.e. the probability that the carrier-to-interference power ratio be less than a given threshold) be less than a specified value, even in the worst foreseen propagation scenario. We identify a set of constraints to be satisfied in order that a DCA strategy belongs to the load-adaptive class. This provides a tight lower bound on traffic blocking and dropping performance such that: (i) it implies a dramatically lower computational effort than the known optimum strategy (based on the Maximum Packing algorithm); (ii) it is much tighter than the bound provided by the simple Erlang-B formula. A performance evaluation is carried out to compare the call blocking and dropping probabilities resulting from the tight bound above with those relevant to the Fixed Channel Allocation and to some recently proposed DCA strategies, including the Geometric DCA. The simulations exploit a mobility model that provides different degrees of offered traffic peakedness. It emerges that the Geometric DCA yields a practical way to attain near optimal performance in the load-adaptive class, leading a viable pathway to enhance the capacity of nowadays 2nd generation cellular networks in the short-medium term.
Taking steps: the influence of a walking technique on presence in virtual reality
Authors: Mel Slater, Martin Usoh, Anthony Steed
Venue: ACM Transactions on Computer-Human Interaction (TOCHI) (1995)

This article presents an interactive technique for moving through an immersive virtual environment (or &ldquo;virtual reality&rdquo;). The technique is suitable for applications where locomotion is restricted to ground level. The technique is derived from the idea that presence in virtual environments may be enhanced the stronger the match between proprioceptive information from human body movements and sensory feedback from the computer-generated displays. The technique is an attempt to simulate body movements associated with walking. The participant &ldquo;walks in place&rdquo; to move through the virtual environment across distances greater than the physical limitations imposed by the electromagnetic tracking devices. A neural network is used to analyze the stream of coordinates from the head-mounted display, to determine whether or not the participant is walking on the spot. Whenever it determines the walking behavior, the participant is moved through virtual space in the direction of his or her gaze. We discuss two experimental studies to assess the impact on presence of this method in comparison to the usual hand-pointing method of navigation in virtual reality. The studies suggest that subjective rating of presence is enhanced by the walking method provided that participants associate subjectively with the virtual body provided in the environment. An application of the technique to climbing steps and ladders is also presented.
Simplifying subtyping constraints
Authors: François Pottier
Venue: Proceedings of the first ACM SIGPLAN international conference on Functional programming (1996)

This paper studies type inference for a functional, ML-style language with subtyping, and focuses on the issue of simplifying inferred constraint sets. We propose a powerful notion of entailment between constraint sets, as well as an algorithm to check it, which we prove to be sound. The algorithm, although very powerful in practice, is not complete. We also introduce two new typing rules which allow simplifying constraint sets. These rules give very good practical results.
View maintenance in a warehousing environment
Authors: Yue Zhuge, Héctor García-Molina, Joachim Hammer, Jennifer Widom
Venue: Proceedings of the 1995 ACM SIGMOD international conference on Management of data (1995)

A warehouse is a repository of integrated information drawn from remote data sources. Since a warehouse effectively implements materialized views, we must maintain the views as the data sources are updated. This view maintenance problem differs from the traditional one in that the view definition and the base data are now decoupled. We show that this decoupling can result in anomalies if traditional algorithms are applied. We introduce a new algorithm, ECA (for "Eager Compensating Algorithm"), that eliminates the anomalies. ECA is based on previous incremental view maintenance algorithms, but extra "compensating" queries are used to eliminate anomalies. We also introduce two streamlined versions of ECA for special cases of views and updates, and we present an initial performance study that compares ECA to a view recomputation algorithm in terms of messages transmitted, data transferred, and I/O costs.
A Sweeping Line Approach to Interconnect Testing
Authors: Jose Salinas, Yinan Shen, Fabrizio Lombardi
Venue: IEEE Transactions on Computers (1996)

This paper presents a new structural approach for test generation and diagnosis of interconnects (such as wiring networks). The proposed technique is based on computational geometry by considering the physical adjacencies of the nets in the layout. This information is used by a sweeping line technique for generating the test vectors. A realistic fault model in which nets can be bridged only if they are physically adjacent, is proposed. The proposed approach generates a set of initial local vectors for testing all the nets at the inputs. A different set of local vectors is then, generated by sweeping the layout at every point where two nets may intersect. The set of local vectors is generally sparse. So, a compaction algorithm is proposed for generating the final set. The proposed approach has an execution time of O((p + k) log p) for generating the local tests, where p is the maximum number of segments in the nets and k is the number of possible intersection points. It is proved that the problem of generating the minimum number of test vectors by compaction is NP-complete, but simulation results show that the proposed heuristic criteria are very efficient for a practical application. The extension of the proposed approach to other fault models and to other routing schemes (as applicable to PCB and VLSI) is presented.
Interprocedural partial redundancy elimination and its application to distributed memory compilation
Authors: Gagan Agrawal, Joel Saltz, Raja Das
Venue: ACM SIGPLAN Notices (1995)

Partial Redundancy Elimination (PRE) is a general scheme for suppressing partial redundancies which encompasses traditional optimizations like loop invariant code motion and redundant code elimination. In this paper we address the problem of performing this optimization interprocedurally. We use interprocedural partial redundancy elimination for placement of communication and communication preprocessing statements while compiling for distributed memory parallel machines.
Object-oriented cosynthesis of distributed embedded systems
Authors: Wayne Wolf
Venue: ACM Transactions on Design Automation of Electronic Systems (TODAES) (1996)

This article describes a new hardware-software cosynthesis algorithm that takes advantage of the structure inherent in an object-oriented specification. The algorithm creates a distributed system implementation with arbitrary topology, using the object-oriented structure to partition functionality in addition to scheduling and allocating processes. Process partitioning is an especially important optimization for such systems because the specification will not, in general, take into account the process structure required for efficient execution on the distributed engine. The object-oriented specification naturally provides both coarse-grained and fine-grained partitions of the system. Our algorithm uses that multilevel structure to guide synthesis. Experimental results show that our algorithm takes advantage of the object-oriented specification to quickly converge on high-quality implementations.
Address space sparsity and fine granularity
Authors: Jochen Liedtke
Venue: ACM SIGOPS Operating Systems Review (1995)

To fully exploit the potential of large address spaces, e.g. 264-byte, the sparsity problem has to be solved in an efficient manner. Current address translation schemes either cause enormous space overhead (page table trees) or do not support address space structuring, object grouping and mixed page sizes (inverted page tables). Furthermore, an essential handicap of current virtual address spaces is their coarse granularity. It restricts the concept's relevance to low level OS technology. Without this constraint, mapping could be a vertically integrating paradigm, useful on all levels from hardware up to application programming.Guarded page tables help solving both problems. They permit significant extensions of the current programming model without performance degradation: sparse occupation and coarse-grain (4K) pages can be handled by purely conventional hardware; fine-grain (down to 16-byte) pages without fine-grain aliasing become also possible using conventional cache and TLB technology combined with stochastically colored allocation. Unrestricted aliasing and unlimited user level mapping without performance degradation may become possible by hardware innovation.
VAXcluster: a closely-coupled distributed system
Authors: Nancy P. Kronenberg, Henry M. Levy, William D. Strecker
Venue: ACM Transactions on Computer Systems (TOCS) (1986)

A VAXcluster is a highly available and extensible configuration of VAX computers that operate as a single system. To achieve performance in a multicomputer environment, a new communications architecture, communications hardware, and distributed software were jointly designed. The software is a distributed version of the VAX/VMS operating system that uses a distributed lock manager to synchronize access to shared resources. The communications hardware includes a 70 megabit per second message-oriented interconnect and an interconnect port that performs communications tasks traditionally handled by software. Performance measurements show this structure to be highly efficient, for example, capable of sending and receiving 3000 messages per second on a VAX-11/780.
High-density reachability analysis
Authors: Kavita Ravi, Fabio Somenzi
Venue: Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design (1995)

We address the problem of reachability analysis for large finite state systems. Symbolic techniques have revolutionized reachability analysis but still have limitations in traversing large systems. We present techniques to improve the symbolic breadth-first traversal and compute a lower bound on the reachable states. We identify the problem as one of density during traversal and our techniques seek to improve the same. Our results show a marked improvement on the existing breadth-first traversal methods.
On grey relational mapping
Authors: Shuze Wang, Xiqiang Liu
Venue: ACM SIGICE Bulletin (1995)

This paper discusses the operation of grey relational mapping. We define the equivalent characteristics of relational mapping and the generating relational order. We prove that if the relational mappings are finite, then their maximum, minimum value, weighted average and product function are also relational mappings. The necessary and sufficient condition that two relational mappings are equivalent is that they can be generated by each other by monotonic increasing functions. We put forward the principle of optimum relational order to obtain a better method to carry out the relational analysis.
Random number generators are chaotic
Authors: Charles Herring, Julian I. Palmore
Venue: Communications of the ACM (1995)

The study of highly unstable nonlinear dynamical systems&mdash;chaotic systems&mdash;has emerged recently as an area of major interest and applicability across the mathematical, physical and social sciences. This interest has been triggered by advances in the past decade, particularly in the mathematical understanding of complex systems. An important insight that has become widely recognized in recent years is that deterministic systems can give rise to chaotic behavior. Surprisingly, many of these systems are extremely simple, yet they exhibit complex chaotic behavior.
Combinational logic synthesis for LUT based field programmable gate arrays
Authors: Jason Cong, Yuzheng Ding
Venue: ACM Transactions on Design Automation of Electronic Systems (TODAES) (1996)

The increasing popularity of the field programmable gate-array (FPGA) technology has generated a great deal of interest in the algorithmic study and tool development for FPGA-specific design automation problems. The most widely used FPGAs are LUT based FPGAs, in which the basic logic element is a K-input one-output lookup-table (LUT) that can implement any Boolean function of up to K variables. This unique feature of the LUT has brought new challenges to logic synthesis and optimization, resulting in many new techniques reported in recent years. This article summarizes the research results on combinational logic synthesis for LUT based FPGAs under a coherent framework. These results were dispersed in various conference proceedings and journals and under various formulations and terminologies. We first present general problem formulations, various optimization objectives and measurements, then focus on a set of commonly used basic concepts and techniques, and finally summarize existing synthesis algorithms and systems. We classify and summarize the basic techniques into two categories, namely, logic optimization and technology mapping, and describe the existing algorithms and systems in terms of how they use the classified basic techniques. A comprehensive list of references is compiled in the attached bibliography.
Hypertext links in Lotus Notes and the World Wide Web
Authors: Kate Ehrlich, Alex Lee, Phillip Ritari
Venue: ACM SIGWEB Newsletter (1995)

At the Digital Libraries conference in Texas in 1994 we presented a paper describing an ethnographic study of information access in a customer support organization [1]. That study revealed the highly collaborative nature of information filtering and retrieval. In particular, support analysts relied on each other to fill in anecdotal and experiential information missing from written documentation and reason through that information to solve customer problems. Colleagues also routinely shared references to relevant sources of information. This behavior is very similar to what we have observed informally in which people will spontaneously share references to interesting documents with friends and colleagues. In fact, we found that workgroups often include at least one person who is especially skilled at browsing through large amounts of often diverse information and then making his or her findings available to others generally with some commentary on its relevance and/or intrinsic value. Based on these data and observations we developed a system in Lotus Notes to let people share references to on-line documents. The system automatically encoded contextual information such as the name of the document, its date and its source along with the hypertext link, and provided space for the person to add comments of any length [3]. The resulting "pointer" could be sent to colleagues in email or saved in a Notes database as a personal bookmark. These pointers were more useful than just sending doc links because the recipient would get some context that would help him/her decide whether to follow the link to the document. We also enhanced the basic doc link technology in Notes to automatically open or add and open the referenced database if the user did not have that database on their workspace. This enhancement meant that location and availability of the database was transparent to the user.
Generating test cases for real-time systems from logic specifications
Authors: Dino Mandrioli, Sandro Morasca, Angelo Morzenti
Venue: ACM Transactions on Computer Systems (TOCS) (1995)

We address the problem of automated derivation of functional test cases for real-time systems, by introducing techniques for generating test cases from formal specifications written in TRIO, a language that extends classical temporal logic to deal explicitly with time measures. We describe an interactive tool that has been built to implement these techniques, based on interpretation algorithms of the TRIO language. Several heuristic criteria are suggested to reduce drastically the size of the test cases that are generated. Experience in the use of the tool on real-life cases is reported.
Application of the Smith Normal Form to the Structure of Lattice Rules
Authors: J. N. Lyness, P. Keast
Venue: SIAM Journal on Matrix Analysis and Applications (1995)

Two independent approaches to the theory of the lattice rule have been exploited at length in the literature. One is based on the generator matrix $A$ of the lattice $\Lambda$ whose elements provide the abscissas of $Q$. The other, based on the $t$-cycle form $Q(\Lambda )f$ of Sloan and Lyness [Math. Comput., 52 (1989), pp.~81--94], leads to a canonical form for $Q$. In this paper, a close connection between these approaches is demonstrated. This connection reflects the close relation between the Kronecker decomposition theorem for Abelian groups and the Smith normal form of an integer matrix. It is shown that the invariants of the canonical form of $Q(\Lambda)f$ coincide with the elements of the Smith normal form of $B = (A^T)^{-1}$, the reciprocal lattice generator matrix. This fact may be used to provide a straightforward solution to the previously intransigent problem of identifying and removing a repetition in the general $t$-cycle form.
Using hybrid branch predictors to improve branch prediction accuracy in the presence of context switches
Authors: Marius Evers, Po-Yung Chang, Yale N. Patt
Venue: Proceedings of the 23rd annual international symposium on Computer architecture (1996)

Pipeline stalls due to conditional branches represent one of the most significant impediments to realizing the performance potential of deeply pipelined, superscalar processors. Many branch predictors have been proposed to help alleviate this problem, including the Two-Level Adaptive Branch Predictor, and more recently, two-component hybrid branch predictors.In a less idealized environment, such as a time-shared system, code of interest involves context switches. Context switches, even at fairly large intervals, can seriously degrade the performance of many of the most accurate branch prediction schemes. In this paper, we introduce a new hybrid branch predictor and show that it is more accurate (for a given cost) than any previously published scheme, especially if the branch histories are periodically flushed due to the presence of context switches.
IDEA: interactive data exploration and analysis
Authors: Peter G. Selfridge, Divesh Srivastava, Lynn O. Wilson
Venue: ACM SIGMOD Record (1996)

The analysis of business data is often an ill-defined task characterized by large amounts of noisy data. Because of this, business data analysis must combine two kinds of intertwined tasks: exploration and analysis. Exploration is the process of finding the appropriate subset of data to analyze, and analysis is the process of measuring the data to provide the business answer. While there are many tools available both for exploration and for analysis, a single tool or set of tools may not provide full support for these intertwined tasks. We report here on a project that set out to understand a specific business data analysis problem and build an environment to support it. The results of this understanding are, first of all, a detailed list of requirements of this task; second, a set of capabilities that meet these requirements; and third, an implemented client-server solution that addresses many of these requirements and identifies others for future work. Our solution incorporates several novel perspectives on data analysis and combines a history mechanism with a graphical, re-usable representation of the analysis and exploration process. Our approach emphasizes using the database itself to represent as many of these functions as possible.
Tree insertion grammar: a cubic-time, parsable formalism that lexicalizes context-free grammar without changing the trees produced
Authors: Yves Schabes, Richard C. Waters
Venue: Fuzzy Sets and Systems (1995)

Tree insertion grammar (TIG) is a tree-based formalism that makes use of tree substitution and tree adjunction. TIG is related to tree adjoining grammar. However, the adjunction permitted in TIG is sufficiently restricted that TIGs only derive context-free languages and TIGs have the same cubic-time worst-case complexity bounds for recognition and parsing as context-free grammars. An efficient Earley-style parser for TIGs is presented.Any context-free grammar (CFG) can be converted into a lexicalized tree insertion grammar (LTIG) that generates the same trees. A constructive procedure is presented for converting a CFG into a left anchored (i.e., word initial) LTIG that preserves ambiguity and generates the same trees. The LTIG created can be represented compactly by taking advantage of sharing between the elementary trees in it. Methods of converting CFGs into left anchored CFGs, e.g., the methods of Greibach and Rosenkrantz, do not preserve the trees produced and result in very large output grammars.For the purpose of experimental evaluation, the LTIG lexicalization procedure was applied to eight different CFGs for subsets of English. The LTIGs created were smaller than the original CFGs. Using an implementation of the Earley-style TIG parser that was specialized for left anchored LTIGs, it was possible to parse more quickly with the LTIGs than with the original CFGs.