ppxscal/embedding_network huggingface dataset:
On compiling algorithms for arithmetic expressions
Authors: Ikuo Nakata
Venue: Communications of the ACM (1967)

This paper deals with algorithms concerning arithmetic expressions used in a FORTRAN IV compiler for a HITAC-5020 computer having n accumulators. The algorithms generate an object code which minimizes the frequency of storing and recovering the partial results of the arithmetic expressions in cases where there are several accumulators.
Temporal summaries of new topics
Authors: James Allan, Rahul Gupta, Vikas Khandelwal
Venue: Proceedings of the 24th annual international ACM SIGIR conference on Research and development in information retrieval (2001)

We discuss technology to help a person monitor changes in news coverage over time. We define temporal summaries of news stories as extracting a single sentence from each event within a news topic, where the stories are presented one at a time and sentences from a story must be ranked before the next story can be considered. We explain a method for evaluation, and describe an evaluation corpus that we have built. We also propose several methods for constructing temporal summaries and evaluate their effectiveness in comparison to degenerate cases. We show that simple approaches are effective, but that the problem is far from solved.
The cyclical majority problem
Authors: John E. Pomeranz, Roman L. Weil,  Jr.
Venue: Communications of the ACM (1970)

The problem of the cyclical majority is presented and some new, simulated results for 3, 4, 5, &hellip; , 40 issues and 3, 5, 7, &hellip; , 37 judges are reported.
A methodology for the design of distributed information systems
Authors: Giacomo Bucci, Donald N. Streeter
Venue: Communications of the ACM (1979)

A macro model of a distributed information system in presented. The model describes the major costs of using an information system from the perspective of the end-user. The model is intended to provide guidance to the system designer by making evident the effect of various design and operating parameters on overall cost per transaction. The technique is illustrated by application to the design of an interactive transaction processing system.
Local versus comprehensive assignments: two complementary approaches
Authors: Cristóbal Pareja-Flores, J. Ángel Velázquez-Iturbide
Venue: ACM SIGCSE Bulletin (2000)

Two complementary classes of assignments, local and comprehensive, are advocated with different goals and features. The aim of describing both classes of assignments provides guidance to teachers in their design. Local assignments ideally provide an in-depth coverage of only one concept, whereas global ones ideally provide a breadth coverage of most of the concepts studied in a period of time. Both classes of assignments are illustrated with two motivating programming examples: "rolling dice" and "lights out," respectively.
Using Constraint Satisfaction for View Update
Authors: Hua Shu
Venue: Journal of Intelligent Information Systems (2000)

View update is the problem of translating update requests against a view into update requests against the base data. In this article, we present a novel approach to generating alternative translations of view updates in relational databases. Using conditional tables to represent relational views, we transform a view update problem into constraint satisfaction problems (CSPs). Solutions to the CSPs correspond to possible translations of the view update. Semantic information to resolve ambiguity can be incrementally added as constraints in the CSPs. The connection between view update and constraint satisfaction makes it possible to apply the rich results of the CSP research to analyze and solve the important problem of view management.
101 optimal PDB structure alignments: a branch-and-cut algorithm for the maximum contact map overlap problem
Authors: Giuseppe Lancia, Robert Carr, Brian Walenz, Sorin Istrail
Venue: Proceedings of the fifth annual international conference on Computational biology (2001)

Structure comparison is a fundamental problem for structural genomics. A variety of structure comparison methods were proposed and several protein structure classification servers e.g., SCOP, DALI, CATH, were designed based on them, and are extensively used in practice. This area of research continues to be very active, being energized bi-annually by the CASP folding competitions, but despite the extraordinary international research effort devoted to it, progress is slow. A fundamental dimension of this bottleneck is the absence of rigorous algorithmic methods. A recent excellent survey on structure comparison by Taylor et.al. [23] records the state of the art of the area: In structure comparison, we do not even have an algorithm that guarantees an optimal answer for pairs of structures &hellip; In this paper we provide the first rigorous algorithm for structure comparison. Our method is based on developing an effective integer linear programming (IP) formulation of protein structure contact maps overlap (CMO), and a branch-and-cut strategy that employs lower-bounding heuristics at the branch nodes. Our algorithms identified a gallery of optimal and near-optimal structure alignments for pairs of proteins from the Protein Data Bank with up to 80 amino acids and about 150 contacts each &mdash; problems of instance size of about 300. Although these sizes also reflect our current limitations, these are the first provable optimal and near-optimal algorithms in the literature for a measure of structure similarity which sees extensive practical use. At the heart of our success in finding optimal alignments is a reduction of the CMO optimization to the maximum independent set (MIS) problem on special graphs. For CMO instances of size 300, the corresponding MIS graph instance contains about 10,000 nodes. While our algorithms are able to solve to optimality MIS problem of these sizes, the known optimal algorithms for the MIS on general graphs can at present only solve instances with up to a few hundred nodes. This is the first effective use of IP methods in protein structure comparison; the biomolecular structure literature contains only one other effective IP method devoted to RNA comparison, due to Lenhof et.al. [18]. The hybrid heuristic approach that worked well for providing lower bounds in the branch and cut algorithm was tried on large proteins in a test set suggested by Jeffrey Skolnick. It involved 33 proteins classified into four families: Flavodoxin-like fold CheY-related, Plastocyanin, TIM Barrel, and Ferratin. Out of the set of all 528 pairwise structure alignments, we have validated the clustering with a 98.7% accuracy (1.3% false negatives and 0% false positives).
Monitoring deployed agent teams
Authors: Gal A. Kaminka, David V. Pynadath, Milind Tambe
Venue: Proceedings of the fifth international conference on Autonomous agents (2001)

Recent years are seeing an increasing need for on-line monitoring of deployed distributed teams of cooperating agents, e.g., for visualization, or performance tracking. However, in deployed systems, we often cannot rely on the agents to communicate their state to the monitoring system: (a) we rarely can change the behavior of already-deployed agents to communicate the required information (e.g., in legacy or proprietary systems); (b) different monitoring goals require different information to be communicated (e.g., agents' beliefs vs. plans); and (c) communications may be expensive, unreliable, or insecure. This paper presents a non-intrusive approach based on plan-recognition, in which the monitored agents' state is inferred from observations of their routine actions. In particular, we focus on inference of the team state based on its observed \emph{routine} communications, exchanged as part of coordinated task execution. The paper includes the following key novel contributions: (i) a \emph{linear time} probabilistic plan-recognition algorithm, well-suited for processing communications as observations; (ii) an approach to exploiting general knowledge of teamwork to predict agent responses during normal execution, to reduce monitoring uncertainty; and (iii) a monitoring algorithm that trades expressivity for scalability, representing only certain useful monitoring hypotheses, but allowing for any number of agents and their different activities, to be represented in a single coherent entity. Our empirical evaluation illustrates that monitoring based on observed routine communications enables significant monitoring accuracy, while not being intrusive. The results also demonstrate a key lesson: A combination of complementary low-quality techniques is cheaper, and better, than a single, highly-optimized monitoring approach.
Logical analysis of programs
Authors: Shmuel Katz, Zohar Manna
Venue: Communications of the ACM (1976)

Most present systems for verification of computer programs are incomplete in that intermediate inductive assertions must be provided manually by the user, termination is not proven, and incorrect programs are not treated. As a unified solution to these problems, this paper suggests conducting a logical analysis of programs by using invariants which express what is actually occurring in the program. The first part of the paper is devoted to techniques for the automatic generation of invariants. The second part provides criteria for using the invariants to check simultaneously for correctness (including termination) or incorrectness. A third part examines the implications of the approach for the automatic diagnosis and correction of logical errors.
Hierarchical Diagnosis of Identical Units in a System
Authors: Sasidhar Koppolu, Abhijit Chatterjee
Venue: IEEE Transactions on Computers (2001)

A hierarchical diagnosis algorithm is presented for testing identical units in a system. As all units are similar, it is essential that the test process be parallelized to enable test of multiple units for the cost of testing one unit. With this objective in mind, we propose a novel test architecture consisting of a hierarchy of testers in a system to test all the units simultaneously. In this approach, special test chips are placed at strategic locations in a system to compute a ¿golden response¿ by analyzing the responses of all units. The responses are propagated up the hierarchy of testers. At each level, the testers analyze the data and pass golden response computation data to testers at higher level. The tester at the top of the hierarchy computes the golden response and the test result is percolated down to the testers at the lowest level that identify faulty and fault-free units. Using this diagnosis approach, almost all units are correctly diagnosed, even when yields are as low as 40 percent. The hardware architecture of all test chips is identical and simple. This approach can be used for testing massively parallel multiprocessor systems, MCMs fabricated on a large area panel, and integrated circuits on silicon wafers.
Combining subsumption and binary methods: an object calculus with views
Authors: Jérôme Vouillon
Venue: ACM SIGPLAN Notices (2001)

We presen t an object-oriented calculus whic hallows arbitrary hiding of methods in protot ypes, even in the presence of binary methods and friend functions. This combination of features permits complete control of the in terface a class exposes to the remainder of a program (which is of key importance for program readability, security and ease of maintenance), while still allowing complex in teractions with other classes belonging to the same module or softw are component.This result is made possible by the use of views. A view is a name that specifies an in terface to an object. A set of views is attached to each object and a method can be invoked either directly or via a view of the object.
Solutions of combinatorial problems using generating functions on a variable-field computer
Authors: G. M. Weinberg
Venue: Communications of the ACM (1964)

The utility of generating functions in solving combinatoria problems is discussed. Particular implementation results are presented and evaluated.
Organization and structure of data on disk file memory systems for efficient sorting and other data processing programs
Authors: Martin A. Goetz
Venue: Communications of the ACM (1963)

An approach to the organization and structure of data on Bryant Disc File Memory Systems for sorting and performing other data processing functions is presented. The following areas are covered: characteristics of Bryant Disc File Systems on the Bendix G-20 and RCA 301; two proposed &ldquo;chaining&rdquo; structures for data; and functions of a Disk File Executive Routine. The concepts for sorting and performing file maintenance processing using the proposed structure and executive routine are discussed. Additionally, it is shown that sorting can be accomplished without the use of disk storage work areas.
Design of C++ classes and functions to model non-game interfacing applications of the inputs of a joy port (tutorial presentation)
Authors: Lee R. Clendenning
Venue: Proceedings of the second annual CCSC on Computing in Small Colleges Northwestern conference (2000)

A summary and demonstration of the synthesis of C++ classes and functions which would model non-game applications of a traditional joy port of the IBM compatible personal computer. A classic security alarm system with multiple zones circuits hardwired to the port will be used as an application example. The generic physical/electrical provisions and characteristics of the port for digital and analog inputs are reviewed with schematic diagrams. Applicable functions from the C++ libraries, conio.h and math.h, are identified and explained. These functions provide access and bit level logic to isolate logic states at individual joy port pins. The hardware port supports four (4) sink mode digital switch inputs which are used as the basis for security zones. The declarations and definitions of member functions for a security zone class which can monitor and control alarms and screen reports for each zone is presented. Additionally, one of the joy port analog inputs will be interfaced to an LED-photo-transistor pair setting up a disable function by breaking a light beam. A 2 ft. &times; 4 ft. display/demo board, interfaced to a laptop computer joy port and accompanied with prints of source code and diagrams will clarify understanding.
Algorithm 492: Generation of all the cycles of a graph from a set of basic cycles [H]
Authors: Norman E. Gibbs
Venue: Communications of the ACM (1975)

The PL/I procedure CYCLE_GENERATOR is an implementation of Gibbs' algorithm [1] for finding all the cycles in a graph from a set of basic cycles.
Building partitioned architectures based on the Ravenscar profile
Authors: Brian Dobbing
Venue: ACM SIGAda Ada Letters (2000)

The requirement to support software partitioning is a recurring theme within High Integrity and Safety Critical systems. The partition concept is used to implement differing access protection levels for applications of varying criticality levels executing on the same processor. Partitions can also be used in fault tolerant systems that require high availability, redundancy or dynamic re-configuration.The Ravenscar Profile was a major output of the 8th International Real-Time Ada Workshop. The profile defines a subset of the Ada95 tasking constructs that matches the requirements of Safety Critical, High Integrity and Hard Real-Time systems by eliminating constructs with high overhead or non-deterministic behavior (semantically or temporally) whilst retaining those elements that form the basic building blocks for constructing analyzable and deterministic real-time software.This paper describes how a COTS Ada95 compilation system that implements the Ravenscar Profile can be used in the implementation of a partitioned architecture in an Integrated Modular Avionics context based on the ARINC 653 Application Executive (APEX) standard.
Mixing buffers and pass transistors in FPGA routing architectures
Authors: Mike Sheng, Jonathan Rose
Venue: Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays (2001)

The routing architecture of an FPGA consists of the length of the wires, the type of switch used to connect wires (buffered, unbuffered, fast or slow) and the topology of the interconnection of the switches and wires. FPGA routing architecture has a major influence on the logic density and speed of FPGA devices. Previðous work [] based on a 0.35um CMOS process has suggested that an architecture consisting of length 4 wires (where the length of a wire is measured in terms of the number of logic blocks it passes before being switched) and half of the programmable switches are active buffers, and half are pass transistors. In that work, however, the topology of the routing architecture prevented buffered tracks from connecting to pass-transistor tracks. This restriction prevents the creation of interconnection trees for high fanout nets that have a mixture of buffers and pass transistors. Electrical simulations sugðgest that connections closer to the leaves on interconnection trees are faster using pass transistors, but it is essential to buffer closer to the source. This latter effect is well known in regular ASIC routing [2].In this work we propose a new routing architecture that allows liberal switching between buffered and pass transistor tracks. We explore various versions of the architecture to determine the denðsity-speed trade-off. We show that one version of the new architecðture results in FPGAs with 10% faster critical path delay yet uses the same area as the previous architecture that does not allow such switching. We also show that the new architecture allows a useful area-speed trade off and several versions of the new architecture result in FPGAs with 8% gain in area-delay product than the previðous architecture that does not allow the switching.
A programmmer training project
Authors: Arthur J. Bernstein
Venue: Communications of the ACM (1971)

A project is described whose purpose is to train selected black residents of the Albany-Schenectady area in computer programming and arrange for jobs for them in the computer field. Both the organization and curriculum of the course are discussed.
Scientific Applications: An algorithm for identifying the ergodic subchains and transient states of a stochastic matrix
Authors: B. L. Fox, D. M. Landi
Venue: Communications of the ACM (1968)

An algorithm for identifying the ergodic subchains and transient states of a stochastic matrix is presented. Applications in Markov renewal programming and in the construction of variable length codes are reviewed, and an updating procedure for dealing with certain sequences of stochastic matrices is discussed. Computation times are investigated experimentally and compared with those of another recently proposed method.
Architectural design of a multi-agent system for handling metadata streams
Authors: Don Cruickshank, Luc Moreau, David De Roure
Venue: Proceedings of the fifth international conference on Autonomous agents (2001)

We have designed a multi-agent architecture to deliver metadata streams synchronously with multimedia streams over a wide-area network. To this end, we have devised a simple protocol for synchronising agents to a media clock. This protocol defines the concept of a deadline, after which servers can drop data because it can no longer reach clients in time. We also introduce a new concept of a contract as a first-class entity representing a successful subscription; a contract is used by agents as a session identifier during the navigation of streams. Quality of service is a vital element of this architecture because of the need to deliver metadata on time. As a result, our architecture supports various communication protocols, including \udp, \rmi, \ssl, or multicast. This resulted in a return to a more declarative form of speech acts, totally orthogonal to a notion of virtual communication channel used to manage the quality of service of communication.
A method using procedural parameters and callback functions to create a generic exchange-sorting module
Authors: Robin M. Snyder
Venue: Journal of Computing Sciences in Colleges (2001)

A generic exchange-sorting module obviates the need for duplicating sort code in a program, thus promoting module reuse. This paper presents a method for using procedural parameters and callback functions to create a generic exchange-sorting module. Based on techniques with roots in functional programming using higher order functions, the method is fairly easy to understand. More importantly it is easy to use, even for beginning programmers. Using the rapid application development system Delphi and it's Object Pascal programming language, the method is presented in a way that highlights some useful features of Object Pascal that might not be well known to readers more familiar with the now-outdated standard Pascal or the currently popular C++.
Characteristics of application software maintenance
Authors: B. P. Lientz, E. B. Swanson, G. E. Tompkins
Venue: Communications of the ACM (1978)

Maintenance and enhancement of application software consume a major portion of the total life cycle cost of a system. Rough estimates of the total systems and programming resources consumed range as high as 75-80 percent in each category. However, the area has been given little attention in the literature. To analyze the problems in this area a questionnaire was developed and pretested. It was then submitted to 120 organizations. Respondents totaled 69. Responses were analyzed with the SPSS statistical package. The results of the analysis indicate that: (1) maintenance and enhancement do consume much of the total resources of systems and programming groups; (2) maintenance and enhancement tend to be viewed by management as at least somewhat more important than new application software development; (3) in maintenance and enhancement, problems of a management orientation tend to be more significant than those of a technical orientation; and (4) user demands for enhancements and extension constitute the most important management problem area.
Using lab practica to evaluate programming ability
Authors: A. T. Chamillard, Jay K. Joiner
Venue: ACM SIGCSE Bulletin (2001)

One of the largest challenges facing educators teaching courses with a significant programming component is deciding how to evaluate each student's programming ability. In this paper we discuss how we have addressed this challenge in an introductory computer science course and statistically analyze the results to examine potential inequities in our approach.
RAM-based FPGA's: a test approach for the configurable logic
Authors: M. Renovell, J. M. Portal, J. Figueras, Y. Zorian
Venue: Proceedings of the conference on Design, automation and test in Europe (1998)

This paper proposes a methodology for testing the configurable logic of RAM-based FPGAs taking into account the configurability of such flexible devices. The methodology is illustrated using the XILINX 4000 family. On this example of FPGA, we obtain only 8 basic Test Configurations to fully test the whole matrix of CLBs. In the proposed Test Configurations, all the CLBs have exactly the same configuration forming a set of one-dimensional iterative arrays. The iterative arrays present a C-testability property in such a way that the number of Test Configurations 8 is fixed and independent of the FPGA size.