ppxscal/embedding_network huggingface dataset:
Blackwell Optimality in Borelian Continuous-in-Action Markov Decision Processes
Authors: Alexander A. Yushkevich
Venue: SIAM Journal on Control and Optimization (1997)

We prove the existence of stationary Blackwell optimal policies in Markov decision processes with a Borel state space, compact action sets, and continuous-in-action and bounded transition densities and rewards, satisfying a simultaneous Doeblin-type condition. The proof is based on a compactification of the randomized stationary policy space in a weak-strong topology, on the continuity of Laurent coefficients of the discounted rewards in this topology, and on a lexicographical policy improvement. Until now similar results were obtained for the models with a denumerable state space or with a Borel state space and finite action sets.
A Convergence Analysis of an H-Version Finite-Element Method with High-Order Elements for Two-Dimensional Elasto-Plasticity Problems
Authors: Yiwei Li, Ivo Babuska
Venue: SIAM Journal on Numerical Analysis (1997)

In this paper, we will give an h-version finite-element method for a two-dimensional nonlinear elasto-plasticity problem. A family of admissible constitutive laws based on the so-called gauge-function method is introduced first, and then a high-order h-version semidiscretization scheme is presented. The existence and uniqueness of the solution for the semidiscrete problem are guaranteed by using some special properties of the constitutive law, and finally we will show that as the maximum element size ${h}\longrightarrow 0$, the solution of the semidiscrete problem will converge to the solution of the continuous problem. The high-order h-version discretization scheme introduced here is unusual. If the partition of the spatial space only has rectangles or parallelograms involved, then there would not be any limit on the element degree. However, if the partition of the spatial space has some triangular elements, then only certain combinations of finite-element spaces for displacement and stress functions can be used. The discretization scheme also provides a useful idea for applications of hp-version or high-order h-version finite-element methods for two-dimensional problems where the elasto-plastic body is not a polygon, such as a disk or an annulus.
Classification Using Adaptive Wavelets for Feature Extraction
Authors: Yvette Mallet, Danny Coomans, Jerry Kautsky, Olivier De Vel
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1997)

A major concern arising from the classification of spectral data is that the number of variables or dimensionality often exceeds the number of available spectra. This leads to a substantial deterioration in performance of traditionally favored classifiers. It becomes necessary to decrease the number of variables to a manageable size, whilst, at the same time, retaining as much discriminatory information as possible. A new and innovative technique based on adaptive wavelets, which aims to reduce the dimensionality and optimize the discriminatory information is presented. The discrete wavelet transform is utilized to produce wavelet coefficients which are used for classification. Rather than using one of the standard wavelet bases, we generate the wavelet which optimizes specified discriminant criteria.
An output encoding problem and a solution technique
Authors: Subhasish Mitra, LaNae J. Avra, Edward J. McCluskey
Venue: Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design (1997)

We present a new output encoding problem as follows: Given a specification table, such as a truth table or a finite state machine state table, where some of the outputs are specified in terms of 1's, 0's and don't cares, and others are specified symbolically, and assuming that the minimum number of bits are used to encode the symbolic outputs (ceiling(log_2_(n)) bits for n symbolic outputs), determine a binary code for each symbol of the symbolically specified output column such that the total number of output functions to be implemented after encoding the symbolic outputs and compacting the columns is minimum. There are several applications of this output encoding problem, one of which is to reduce the area overhead while implementing scan or pseudo-random BIST in a circuit with one-hot signals. We develop an exact algorithm to solve the above problem and present experimental data to validate the claim that our encoding strategy helps to reduce the area of a synthesized circuit.
Unconstrained Automatic Image Matching Using Multiresolutional Critical-Point Filters
Authors: Yoshihisa Shinagawa, Tosiyasu L. Kunii
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1998)

This paper proposes a novel method for matching images. The results can be used for a variety of applications: fully automatic morphing, object recognition, stereo photogrammetry, and volume rendering. Optimal mappings between the given images are computed automatically using multiresolutional nonlinear filters that extract the critical points of the images of each resolution. Parameters are set completely automatically by dynamical computation analogous to human visual systems. No prior knowledge about the objects is necessary. The matching results can be used to generate intermediate views when given two different views of objects. When used for morphing, our method automatically transforms the given images. There is no need for manually specifying the correspondence between the two images. When used for volume rendering, our method reconstructs the intermediate images between cross-sections accurately, even when the distance between them is long and the cross-sections vary widely in shape. A large number of experiments has been carried out to show the usefulness and capability of our method.
Leader Election in Complete Networks
Authors: Gurdip Singh
Venue: SIAM Journal on Computing (1997)

Leader election is a fundamental problem in distributed computing and has a number of applications. This paper studies the problem of leader election in complete asynchronous networks. We present a message-optimal protocol that requires $O(N\log{N})$ messages and $O(N/\log{N})$ time, where $N$ is the number of nodes in the system. The time complexity of this protocol is a significant improvement over currently known protocols for this problem. We also give a family of protocols with message and time complexities $O(N k)$ and $O(N/k)$, respectively, where $\log{N} \leq k \leq N$. Many problems such as spanning-tree construction and computing a global function are equivalent to leader election in terms of their message and time complexities, and therefore our result improves the time complexity of these problems as well.
All Highest Scoring Paths in Weighted Grid Graphs and Their Application to Finding All Approximate Repeats in Strings
Authors: Jeanette P. Schmidt
Venue: SIAM Journal on Computing (1998)

Weighted paths in directed grid graphs of dimension (m X n) can be used to model the string edit problem, which consists of obtaining optimal (weighted) alignments between substrings of A, |A|=m, and substrings of B, |B|=n. We build a data structure (in O(mn log m) time) that supports O(log m) time queries about the weight of any of the O(m2n) best paths from the vertices in column 0 of the graph to all other vertices. Using these techniques we present a simple O(n2 log n) time and $\Theta(n^2)$ space algorithm to find all (the locally optimal) approximate tandem (or nontandem) repeats xy within a string of size n. This improves (by a factor of log n) upon several previous algorithms for this problem and is the first algorithm to find all locally optimal repeats. For edit graphs with weights in {0, -1, 1}, a slight modification of our techniques yields an O(n2) algorithm for the cyclic string comparison problem, as compared to O(n2 log n) for the case of general weights.
Simulator based programmable signal generator for EW system evaluation
Authors: Saul Fast
Venue: Proceedings of the 17th conference on Winter simulation (1985)

A test range that generates signals at RF capable of evaluating EW systems capability for operation in a dense signal environment is excessively costly in terms of equipment and range maintenance personnel. The required test equipment complement is reduced by two orders of magnitude through use of a programmable signal source operating at IF. Design methodology/technology for a generic programmable signal source is discussed. Detailed modeling of antenna/receiver front end components of each candidate EW system is required to generate a simulation of the worst case frequency step that yields data for programming the signal source control sequence. The ACM Portal is published by the Association for Computing Machinery. Copyright © 2010 ACM, Inc. Terms of Usage Privacy Policy Code of Ethics Contact Us Useful downloads: Adobe Acrobat QuickTime Windows Media Player Real Player
Architecture issues and solutions for a high-capacity FPGA
Authors: Steve Trimberger, Khue Duong, Bob Conn
Venue: Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays (1997)

High-capacity FPGAs pose device architects with a variety of problems.The most obvious of theseproblems is interconnect capacity. Others include interconnect performance, clock distribution and IO capacity. This paper describes these problems and the solutions to these problems chosen in the Xilinx XC4000EX family architecture.
Simple translation of goal-directed evaluation
Authors: Todd A. Proebsting
Venue: Proceedings of the ACM SIGPLAN 1997 conference on Programming language design and implementation (1997)

This paper presents a simple, powerful and flexible technique for reasoning about and translating the goal-directed evaluation of programming language constructs that either succeed (and generate sequences of values) or fail. The technique generalizes the Byrd Box, a well-known device for describing Prolog backtracking.
Mobile power management for wireless communication networks
Authors: John M. Rulnick, Nicholas Bambos
Venue: Wireless Networks (1997)

For fixed quality-of-service constraints and varying channel interference, how should a mobile node in a wireless network adjust its transmitter power so that energy consumption is minimized? Several transmission schemes are considered, and optimal solutions are obtained for channels with stationary, extraneous interference. A simple dynamic power management algorithm based on these solutions is developed. The algorithm is tested by a series of simulations, including the extraneous-interference case and the more general case where multiple, mutually interfering transmitters operate in a therefore highly responsive interference environment. Power management is compared with conventional power control for models based on FDMA/TDMA and CDMA cellular networks. Results show improved network capacity and stability in addition to substantially improved battery life at the mobile terminals.
From eavesdropping to security on the cellular telephone system GSM
Authors: Daniel Guinier
Venue: ACM SIGSAC Review (1997)

Nowadays, mobile cellular communications concern multi-millions of people, many enterprises and national interests. Because of the few illegal interceptions, by habit or by belief, the majority of users have an angelic confidence in the privacy of their conversations. Nevertheless, a doubt subsists when the news unveils the existence of unfair, excessive or uncontrolled interceptions. Meanwhile, legislation is evolving and the technology is capable of protecting personal and sensitive information. What are the judicial and investigative tools for legal surveillance, that are apt to guarantee the ordinary citizen or an enterprise against assault? What is behind the mobile GSM telephone on this subject?
Cache sensitive modulo scheduling
Authors: F. Jesús Sánchez, Antonio González
Venue: Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture (1997)

This paper focuses on the interaction between software prefetching (both binding and nonbinding) and software pipelining for VLIW machines. First, it is shown that evaluating software pipelined schedules without considering memory effects can be rather inaccurate due to stalls caused by dependences with memory instructions (even if a lockup-free cache is considered). It is also shown that the penalty of the stalls is in general higher than the effect of spill code. Second, we show that in general binding schemes are more powerful than nonbinding ones for software pipelined schedules. Finally, the main contribution of this paper is an heuristic scheme that schedules some memory operations according to the locality estimated at compile time and other attributes of the dependence graph. The proposed scheme is shown to outperform other heuristic approaches since it achieves a better trade-off between compute and stall time than the others.
Computing, diversity and community: fostering the computing culture
Authors: Danielle R. Bernstein
Venue: Proceedings of the twenty-eighth SIGCSE technical symposium on Computer science education (1997)

How do we attract and retain women in mathematics and science and specifically in computing? Women drop out of every bend of the pipeline and thus lose the opportunity to seek good, appealing and high-paying jobs. Funded by an eight-semester long National Science Foundation grant1, the University of Wisconsin (UW) Women and Science program aims to reverse this attrition from the sciences at a point where it is most acute: the introductory courses in the undergraduate science curriculum.This paper focusses on one particular innovation in the computing curriculum: extending the content of a traditional first term computer science course in program design and development to include the culture of computing. The paper gives specific examples of computing artifacts and their uses in any computing classroom. It also shows the connection between teaching the culture of computing and the objectives of the Women and Science project.
An automated BIST approach for general sequential logic synthesis
Authors: C. E. Stroud
Venue: Proceedings of the 25th ACM/IEEE Design Automation Conference (1988)

An automated Built-In Self-Test (BIST) technique for general sequential logic is described. This BIST approach has been incorporated in a behavioral model synthesis system providing automated implementation of BIST in Very Large Scale Integration (VLSI) devices as well as Programmable Logic used at all levels of testing from device testing through system diagnostics. The BIST approach is based on selective replacement of existing system memory elements with BIST flip-flop cells that are connected to form a circular chain, performing data compaction and test pattern generation simultaneously. Two production VLSI devices have been implemented with this automated BIST approach. In each case, the total fault coverage was in excess of 96 percent and the logic overhead incurred was between 9.7 and 18.9 percent.
Fault simulation of interconnect opens in digital CMOS circuits
Authors: Haluk Konuk
Venue: Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design (1997)

We describe a highly accurate but efficient fault simulator for interconnect opens, based on characterizing the standard cell library with SPICE; using transistor charge equations for the site of the open; using logic simulation for the rest of the circuit; taking four different factors, that can affect the voltage of an open, into account; and considering the oscillation and sequential behavior potential of opens. A novel test technique based on controlling the die surface voltage is also described. We present our simulation results of ISCAS85 layouts using stuck-at and IDDQ test sets.
Scaleable CMOS Current-Mode Preamplifier Design for anOptical Receiver
Authors: Myunghee Lee, Olivier Vendier, Martin A. Brooke, Nan Marie Jokerst
Venue: Analog Integrated Circuits and Signal Processing (1997)

We have designed a process-insensitive preamplifier for an optical receiver, fabricated it in several different minimum feature sizes of standard digital CMOS, and demonstrated design scaleability of this analog integrated circuit design. The same amplifier was fabricated in a 1.2 &micro;m and two different 0.8 &micro;m processes through the MOSIS foundry [1]. The amplifier uses a multi-stage, low-gain-per-stage approach. It has a total of 5 identical cascaded stages. Each stage is essentially a current mirror with a current gain of 3. Three of these preamplifiers have been integrated with a GaAs Metal-Semiconductor-Metal (MSM) photodetector and one with an InGaAs MSM detector by using a thin-film epilayer device separation and bonding technology [2]. This quasi-monolithic front-end of an optical receiver virtually eliminates the parasitics between the photodetector and the silicon CMOS preamplifier. We have demonstrated speed and power dissipation improvement as the minimum feature size of the transistors shrink.
Large scale circuit partitioning with loose/stable net removal and signal flow based clustering
Authors: Jason Cong, Honching Peter Li, Sung Kyu Lim, Toshiyuki Shibuya, Dongmin Xu
Venue: Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design (1997)

In this paper, we present an efficient Iterative Improvement based Partitioning (IIP) algorithm called LSR/MFFS, that combines signal flow based Maximum Fanout Free Subgraph (MFFS) clustering algorithm with Loose and Stable net Removal (LSR) partitioning algorithm. The MFFS algorithm generalizes existing MFFC decomposition method from combinational circuits to general sequential circuits in order to handle cycles naturally. We also study the properties of the nets that straddle the cutline carefully, and introduce the concepts of the loose and stable nets as well as effective ways to remove them out of the cutset. The LSR/MFFS algorithm first applies LSR algorithm to clustered netlist generated by MFFS algorithm for global-level cutsize optimization and then declusters netlist for further cutsize refinement. As a result, the LSR/MFFS algorithm has achieved the best cutsize result among all the bipartitioning algorithms published in the literatures with very promising runtime performance. In particular, it outperforms the recent state-of-the-art IIP algorithms LA3-CDIP, CLIP-PROPf, Strawman, hMetis-FM, and MLc by 17.4%, 12.1%, 5.9%, 3.1%, and 1.9%, respectively. It also outperforms the state-of-the-art non-IIP algorithms Paraboli, FBB, and PANZA by 32.0%, 21.4%, and 1.4%, respectively.
Geometry and Diameter Bounds of Directed Cayley Graphs of Abelian Groups
Authors: Charles M. Fiduccia, Rodney W. Forcade, Jennifer S. Zito input
Venue: SIAM Journal on Discrete Mathematics (1998)

Many popular interconnection network topologies, such as hypercubes and toroidal meshes, are based on Cayley graphs of Abelian groups. The symmetry and algebraic structure of these graphs result in many nice physical properties of the network concerning layout, routing algorithms, and load balancing. There has been interest in low-diameter Abelian--Cayley graphs because of their smaller communication delay and reduced congestion. For any fixed number of nodes n, and any fixed out-degree k, we are interested in how small the diameter of directed Cayley graphs of Abelian groups can be and what these low-diameter graphs look like. We give an upper bound of $n \leq \frac{3(d + 3)^3}{25}$ for the size of directed Abelian--Cayley graphs with k = 3 and diameter d, correcting a previously published result by Hsu and Jia [SIAM J. Discrete Math., 7 (1994), pp. 57--71].Our method is based on translational tiling techniques and is a generalization of Wong and Coppersmith's method for k = 2 [J. Assoc. Comput. Mach., 21 (1974), pp. 392--402]. Moreover, our method works for all Abelian groups, not just the cyclic case. For k = 3 we give computational results for the largest Abelian--Cayley graph as a function of diameter. When n = 84 m3, for integer m, there is a network with $n = \frac{(d + 3)^3}{11.95}$ whose diameter is approximately three-fourths of that of a three-dimensional toroidal cube.
Parallel Image Correlation: Case Study to Examine Trade-Offs in Algorithm-to-Machine Mappings
Authors: James B. Armstrong, Muthucumaru Maheswaran, Mitchell D. Theys, Howard Jay Siegel, Mark A. Nichols, Kenneth H. Casey
Venue: The Journal of Supercomputing (1998)

Performance of a parallel algorithm on a parallel machine depends not only on the time complexity of the algorithm, but also on how the underlying machine supports the fundamental operations used by the algorithm. This study analyzes various mappings of image correlation algorithms in SIMD, MIMD, and mixed-mode environments. Experiments were conducted on the Intel Paragon, MasPar MP-1, nCUBE 2, and PASM prototype. The machine features considered in this study include: modes of parallelism, communication/computation ratio, network topology and implementation, SIMD CU/PE overlap, and communication/computation overlap. Performance of an implementation can be enhanced by using algorithmic techniques that match the machine features. Some algorithmic techniques discussed here are additional communication versus redundant computation, data block transfers, and communication/computation overlap. The results presented are applicable to a large class of image processing tasks. Case studies, such as the one presented here, are a necessary step in developing software tools for mapping an application task onto a single parallel machine and for mapping the subtasks of an application task, or a set of independent application tasks, onto a heterogeneous suite of parallel machines.
Reducing "Structure From Motion": A General Framework for Dynamic Vision Part 1: Modeling
Authors: Stefano Soatto, Pietro Perona
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1998)

The literature on recursive estimation of structure and motion from monocular image sequences comprises a large number of apparently unrelated models and estimation techniques. We propose a framework that allows us to derive and compare all models by following the idea of dynamical system reduction. The "natural" dynamic model, derived from the rigidity constraint and the projection model, is first reduced by explicitly decoupling structure (depth) from motion. Then, implicit decoupling techniques are explored, which consist of imposing that some function of the unknown parameters is held constant. By appropriately choosing such a function, not only can we account for models seen so far in the literature, but we can also derive novel ones.
Data collection in field combat simulation
Authors: R. Kathman
Venue: Proceedings of the 17th conference on Winter simulation (1985)

The US Army's Combat Developments Experimentation Center has a &ldquo;field laboratory&rdquo; at Fort Hunter Liggett, California. Force-on-force field experiments are conducted in which soldiers engage in simulated combat with representative opposition forces. Computers and instrumentation are employed for real time casualty assessment and automatic recording of the results of engagements. Nonlethal surrogates of future weapon systems have been developed and utilized to bring realism to the experiment. A multi-computer system is used to control the simulated battle. It consists of a mainframe Central Processing Unit and sixteen mini-computers in four stems. Four basic types of instrumentation have been developed to assist data collection in field combat simulation. A position location system keeps track of the location of all players. A timing system tags all events with accurate time for comparative analysis. Sensor systems are used to detect the occurrence of an event, and a data collection system is used to store all the telemetered data. Analyzed data are then provided to other Army agencies responsible for computer modeling, war-gaming, or procurement decisions. The ACM Portal is published by the Association for Computing Machinery. Copyright © 2010 ACM, Inc. Terms of Usage Privacy Policy Code of Ethics Contact Us Useful downloads: Adobe Acrobat QuickTime Windows Media Player Real Player