ppxscal/embedding_network huggingface dataset:
Designing Vector-Based Ontologies: Can Technology Empower Open Interpretation of Culture Heritage Objects?
Authors: Lily Díaz-Kommonen, Mauri Kaipainen
Venue: Proceedings of the 13th International Workshop on Database and Expert Systems Applications (2002)

The goal of this essay is to present our investigation of how a vector-based ontology can account for the idiosyncrasy of interpreting multifaceted information, such as is typical to cultural heritage resources and traces of human activity in general. In this study we model individual classifications of cultural heritage material in terms of the metaphor of projection from a space of properties onto a classificatory layer. We assume each artifact to be defined by a large, virtually infinite number of descriptive features that can be depicted as vectors These vectors define the position of the artifact in the multidimensional space of properties. An individual understanding of the material is described as a nonlinear projection of positions in the space of properties onto a layer of classifications. Implications of this approach are anticipated in the light of applying it to an example of data, derived from a 16th Centurycorpus of work.
On-Demand Multicast Routing Scheme and its Algorithms
Authors: Te-Chou Su, Ia-Shung Wang
Venue: Proceedings of the 13th International Symposium on Parallel Processing and the 10th Symposium on Parallel and Distributed Processing (1999)

Multicast communication is one of the major techniques to share the transmission cost. However, in the typical multicast service, all destinations are expected to receive the same multicast stream from the source at the same time. Unfortunately, this is a severe restriction for some on demand multimedia applications, such as video-on-demand (VOD), in which customers' requests are expected at various time. Therefore, only few customers can be served in the same multicast group; thus additional bandwidth is required. In this paper, we propose a new multicast communication scheme to allow the destinations accessing the same multicast stream at different time by buffering technique and hence tremendously reduce the communication bandwidth. We call this type of communications as the on-demandmulticast communications. We also define the optimization problems of the on-demand multicast routing and give a theoretical analysis. A greedyalgorithm for this problem is also presented and had been implemented on our VOD systems.
Modeling and Rendering of Individual Feathers
Authors: Cristiano G. Franco, Marcelo Walter
Venue: Proceedings of the 15th Brazilian Symposium on Computer Graphics and Image Processing (2002)

We present a model for geometric modeling and rendering of individual feathers for computer graphics purposes. The model represents the feather structure with a collection of parameterized Bézier curves. This parametrization allows easy generation of the existent types of feather structures with biologically-motivated parameters. Once the feather structure is defined, the feathers can be rendered either in a non-photorealistic renderingstyle or using texture mapping to achieve a more natural look.
Accurate and efficient layout-to-circuit extraction for high-speed MOS and bipolar/BiCMOS integrated circuits
Authors: Frederik Beeftink, A. J. Van Genderen, N. P. Van Der Meijs
Venue: Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors (1995)

In this paper, we describe how we have exploited the advantages of various methods for device recognition and modeling in a layout-to-circuit extractor, called Space. Hence, we have obtained a program that, for different technologies, can quickly translate a large layout into an equivalent network. The network includes layout parasitics of the interconnects and can directly be simulated by various simulation packages, such as Spice. The efficiency and accuracy of the extractor are confirmed by experimental results and enable a fast and reliable layout verification for both MOS and bipolar/BiCMOS technologies.
Visualization of Three-Dimensional Maps
Authors: Luis A. P. Lozada, Candido Ferreira Xavier de Mendonça Neto, Jorge Stolfi
Venue: Proceedings of the 13th Brazilian Symposium on Computer Graphics and Image Processing (2000)

A three-dimensional map is a partition of a 3D manifold into topological polyhedra. We consider the problem of visualizing the topology of a three-dimensional map given only its combinatorial description. Our solution starts by automatically constructing a "nice" geometric realization of the map in R/sup m/, for some m/spl ges/4. The geometric realization is chosen by optimizing certain aesthetic criteria, measured by energy functions. We then project this model to R/sup 3/, and display the resulting multi-celled solid object with a variety of specialized rendering techniques.
Algorithmic Analysis of the Impact of Changes to Object-Oriented Software
Authors: Li Li, A. Jefferson Offutt
Venue: Proceedings of the 1996 International Conference on Software Maintenance (1996)

As the software industry has matured, we have shifted our resources from being primarily devoted to developing new software systems to primarily making modifications in evolving software systems. A major problem for developers in an evolutionary environment is that seemingly small changes can ripple throughout the system to have major unintended impacts elsewhere. As a result, software developers need mechanisms to understand how a change to a software system will affect the rest of the system. Although the effects of changes in object-oriented are restricted, they are also more subtle and more difficult to detect. This paper presents algorithms to analyze the potential impacts of changes to object-oriented software, taking into account encapsulation, inheritance, and polymorphism. This technique allows software developers to perform "what if" analysis on the effect of proposed changes, and thereby choose the change that has the least influence on the rest of the system. The analysis also adds valuable information to regression testing, by suggesting what classes and methods need to be retested, and to project managers, who can use the results for cost estimation and schedule planning.
Reliable Transaction Design Using MTS
Authors: Il-Chul Yoon, Hyung-Ho Kim, Doo-Hwan Bae, Cheong Youn
Venue: 24th International Computer Software and Applications Conference (2000)

Component-based development is an emerging discipline of software development. Recently, the growth of middleware technologies brings the notion of server-side component into CBD for developing mission-critical applications. In this paper, we propose the method for designing reliable component systems for mission-critical tasks. To this end, we formulate the MTS system and develop the framework fro describing the specification and design of component-based systems and reasoning about them. For illustrating our framework, we show that the design of a simple bank example violates its specification. We strongly believe that the refactoring of transaction boundaries is common practice for improving scaliability and, thus, the developed framework is useful when evaluating refactorings.
O(log log N) Time Algorithms for Hamiltonian-Suffix and Min-Max-Pair Heap Operations on Hypercube Multicomputers
Authors: Sajal K. Das, Maria Cristina Pinotti
Venue: Proceedings of the 11th International Symposium on Parallel Processing (1997)

We present an efficient mapping of a min-max-pair heap of size N on a hypercube multicomputer of p processors in such a way the load on each processor's local memory is balanced and no additional communication overhead is incurred for implementation of the single insertion, deletemin and deletemax operations. Our novel approach is based on an optimal mapping of the paths of a binary heap into a hypercube such that in O((log N)/p + log p) time we can compute the Hamiltonian-Suffix, which is defined as a pipelined suffix-minima computation on an O(log N)-length heap path embedded into the Hamiltonian path of the hypercube according to the binary reflected Gray codes. However, the binary tree underlying the heap data structure is not altered by the mapping process.
Metamorphic Testing of Programs on Partial Differential Equations: A Case Study
Authors: T. Y. Chen, Jianqiang Feng, T. H. Tse
Venue: Proceedings of the 26th International Computer Software and Applications Conference on Prolonging Software Life: Development and Redevelopment (2002)

We study the effect of applying metamorphic testing to alleviate the oracle problem for numerical programs. We discuss a case study on the testing of a program that solves an elliptic partial differential equation with Dirichlet boundary conditions. We identify a metamorphic relation for the equation and demonstrate the effectiveness of metamorphic testing in identifying the error. The relation identified in the paper should also be applicable to other numerical methods that yield better approximations on the refinement of grid points or step sizes.
Software Architecture Analysis-A Case Study
Authors: Wen-Li Wang, Mei-Huei Tang, Mei-Hwa Chen
Venue: 23rd International Computer Software and Applications Conference (1999)

We present a case study that evaluates two quality attributes: performance and availability. We use three programs based on two architectural styles: pipe-filter and batch-sequential. The objective of this study is to identify the crucial factors that might have an influence on these quality attributes from the software architecture perspective. The benefit of this study is that early quality prediction can be facilitated by an analysis of the software architecture. The results from this study show that it is feasible to select a better architectural style based on variations in the execution environment to at-tain higher availability and/or better performance. More-over, we demonstrate the effects of these variations on the quality measurements.
Recovery Mechanism for Latency Misprediction
Authors: Enric Morancho, José María Llabería, Àngel Olivé
Venue: Proceedings of the 2001 International Conference on Parallel Architectures and Compilation Techniques (2001)

Abstract: Signalling result availability from the functional units to the instruction scheduler can increase the cycle time and/or the effective latency of the instructions. The knowledge of all instruction latencies would allow the instruction scheduler to operate without the need of external signalling. However, the latency of some instructions is unknown; but, the scheduler can optimistically predict the latency of these instructions and issue speculatively their dependent instructions. Although prediction techniques have great performance potential, their gain can vanish due to misprediction handling. For instance, holding speculatively scheduled instructions in the issue queue reduces its capacity to look-ahead for independent instructions. This paper evaluates a recovery mechanism for latency mispredictions that retains the speculatively issued instructions in a structure apart from the issue queue: the recovery buffer. When data becomes available after a latency misprediction, the dependent instructions will be re-issued from the recovery buffer. Moreover, in order to simplify the re-issue logic of the recovery buffer, the instructions will be recorded in issue order. On mispredictions, the recovery buffer increases the effective capacity of the issue queue to hold instructions waiting for operands. Our evaluations in integer benchmarks show that the recovery-buffer mechanism reduces issue-queue size requirements about 20-25%. Also, this mechanism is less sensitive to the verification delay than the recovery mechanism that retains the instructions in the issue queue.
Jacobi-like Algorithms for Eigenvalue Decomposition of a Real Normal Matrix Using Real Arithmetic
Authors: Bing Bing Zhou, Richard P. Brent
Venue: Proceedings of the 10th International Parallel Processing Symposium (1996)

In this paper we introduce a method for designing efficient Jacobi-like algorithms for eigenvalue decomposition of a real normal matrix. The algorithms use only real arithmetic and achieve ultimate quadratic convergence. A theoretical analysis is conducted and some experimental results are presented.
A Strategy for On-line Interpretation of Sketched Engineering Drawings
Authors: G. Hutton, M. Cripps, Dave Elliman, C. A. Higgins
Venue: Proceedings of the 4th International Conference on Document Analysis and Recognition (1997)

This paper describes a strategy for on-line interpretation of sketched engineering drawings. It represents the design for The Designer's Apprentice - a pen-based system for producing detailed mechanical engineering drawings on a realistic electronic drawing board. The paper examines the problems of interpreting scanned drawings and assesses how such problems affect on-line systems. It is therefore relevant to on-line and off-line systems. The strategy is enhanced by making an early distinction between annotation and the object outline. This discrimination shapes the subsequent processing: the object outline is subjected to node connecting, face-finding and beautification whereas annotation is classified according to the BS308 engineering standard.
On generalized fat trees
Authors: Sabine R. Öhring, Maximilian Ibel, Sajal K. Das, Mohan J. Kumar
Venue: Proceedings of the 9th International Symposium on Parallel Processing (1995)

We introduce and analyze a new family of multiprocesser interconnection networks, called generalized fat trees, which include as special cases the fat trees used for the connection machine architecture CM-5, pruned butterflies, and various other fat trees proposed in the literature. The generalized fat trees provide a formal unifying concept to design and analyse a fat tree based architecture. The extended generalized fat tree network XGFT(h; m/sub 1/, ..., m/sub h/; w/sub 1/, ..., w/sub h/) of height h has /spl Pi//sub i=1//sup h/ m/sub i/ leaf processors and the inner nodes serve only as switches or routers. Each non-leaf node in level i has m/sub i/ children and each non-root has w/sub i+1/ parent nodes. The generalized fat trees provide regularity, symmetry, recursive scalability, maximal fault-tolerance, logarithmic diameter bisection scalability, and permit simple algorithms for fault tolerant self-routing and broadcasting. These networks are also versatile, since they can efficiently embed rings, meshes and tori, trees, pyramids and hypercubes.
Translating hierarchical predicate transition nets to CC++ program skeletons
Authors: Xudong He, Weili Yao
Venue: Proceedings of the 21st International Computer Software and Applications Conference (1997)

The paper presents an approach to translate hierarchical predicate transition nets into CC++ (a concurrent object oriented language) program skeletons. The approach consists of an overall translation architecture and a set of translation rules based on the syntax and semantics of hierarchical predicate transition nets. The results have established a link between hierarchical predicate transition nets and concurrent object-oriented programming, and provided some building blocks for a hierarchical predicate transition net based transformational software development methodology.
Tailoring E-Commerce Sites to Ease Recovery after Disruptions
Authors: Karen Renaud, Tobias van Dyk
Venue: Proceedings of the 25th International Computer Software and Applications Conference on Invigorating Software Development (2001)

Developers of e-commerce applications are often unrealistic about how their site will be used, and about possible outcomes during site usage. The most commonly considered outcomes of a user's visit to a site are firstly that the visit culminates in a sale, and secondly that the user leaves the site without buying anything - perhaps to return later. In the second case sites often "remember" any accumulated items so that a shopper can return at a later stage to resume shopping.In this paper we consider certain disruptions, such as breakdowns, problems caused by human errors, and interruptions, which could affect the outcome of the e-commerce shopping experience. These events have definite and possibly long-lasting effects on users, and applications should therefore be developed to cater for these eventualities so as to enhance the usability of the site and encourage further usage.We develop a model for analysing e-commerce application usage, and using this model, propose an evaluation strategy for determining whether an e-commerce site will be resistant to such factors. The proposed evaluation mechanism is applied to three sites to arrive at what we shall call a disruption-resistance score.
Visual Impact Analysis
Authors: Keith Gallagher
Venue: Proceedings of the 1996 International Conference on Software Maintenance (1996)

The Surgeon's Assistant is a CASE tool for software maintainers and developers of ANSI C programs. It is based on the premises that maintainers need to be able to limit the scope of changes and that (most) development starts from some existing, similar systems. The Decomposition Slice Display System (DSDS_XVCG), a component of the Surgeon's Assistant, automates and visualizes impact analysis by displaying the relationships among a program's decomposition slices. It allows the software maintainer to visually comprehend the relationships between the decomposition slices. DSDS_XVCG uses the interface of a tool for Visualizing Compiler Graphs, VCG, to present the lattice of the decomposition slices for the user's perusal. It allows the user to manipulate the graph by deleting and coloring nodes, and by collapsing regions. The software maintainer is provided with an visualization of the impact of proposed changes and can plan maintenance accordingly.
Type Management: A Key to Software Reuse in Open Distributed Systems
Authors: Malte Münke, Winfried Lamersdorf, Bernd O. Christiansen, Kay Müller-Jones
Venue: Proceedings of the 1st International Conference on Enterprise Distributed Object Computing (1997)

Reuse of software components available in open distributed systems is a promising approach for efficient development of complex distributed applications. In open distributed systems, type mechanisms are used both to find appropriate external software components and also to guarantee that their respective interfaces match. Furthermore, a type manager allows application developers to interactively browse existing functionality and enables the automatic mediation of compatible software components at run-time. This paper presents a uniform view for handling the functionality offered by software components regardless of context-specific aspects and a framework that allows for the automatic deduction of different flavors of compatibility relations. Finally, we describe our current type management prototype implementation.
Message Encoding Techniques for Efficient Arrary Redistribution
Authors: Yeh-Ching Chung, Ching-Hsien Hsu
Venue: Proceedings of the international Conference on Parallel Processing (1997)

In this paper, we present message encoding techniques to improve the performance of BLOCK-CYCLIC(kr) to BLOCK-CYCLIC(r) (and vice versa) array redistribution algorithms. The message encoding techniques are machine independent and could be used with different algorithms. By incorporating the techniques in array redistribution algorithms, one can reduce the computation overheads and improve the overall performance of array redistribution algorithms. To evaluate the performance of the techniques, we have implemented the message encoding techniques into some array redistribution algorithms on an IBM SP2 parallel machine. The experimental results show that the execution time of array redistribution algorithms with the message encoding techniques is 3% to 22% faster than those without the message encoding techniques.
Breaking the O(n1/(2k-1)) Barrier for Information-Theoretic Private Information Retrieval
Authors: Amos Beimel, Yuval Ishai, Eyal Kushilevitz, Jean-François Raymond
Venue: Proceedings of the 43rd Symposium on Foundations of Computer Science (2002)

Private Information Retrieval (PIR) protocols allow a user to retrieve a data item from a database while hiding the identity of the item being retrieved. Specifically, in information-theoretic, k-server PIR protocols the database is replicated among k servers, and each server learns nothing about the item the user retrieves. The cost of such protocols is measured by the communication complexity of retrieving one out of n bits of data. For any fixed k, the complexity of the best protocols prior to our work was 0(n^{\frac{1}{{2k - 1}}}) (Ambainis, 1997). Since then several methods were developed in an attempt to beat this bound, but all these methods yielded the same asymptotic bound.In this work, this barrier is finally broken and the complexity of information-theoretic k-server PIR is improved to n^{0(\frac{{\log \log k}}{{k\log k}})}. The new PIR protocols can also be used to construct k-query binary locally decodable codes of length exp (n^{0(\frac{{\log \log k}}{{k\log k}})}), compared to exp(n^{\frac{1}{{k - 1}}}) in previous constructions. The improvements presented in this paper apply even for small values of k: the PIR protocols are more efficient than previous ones for every k \geqslant 3, and the locally decodable codes are shorter for every k \geqslant 4.
Logic synthesis for a single large look-up table
Authors: Rajeev Murgai, Masahiro Fujita, Fumiyasu Hirose
Venue: Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors (1995)

Logic synthesis for look-up tables (LUTs) has received much attention in the past few years, since Xilinx introduced its LUT-based field-programmable gate array (FPGA) architectures. An m-input LUT can implement any Boolean function of up to m inputs. So the goal of synthesis for such architectures has been to synthesize a circuit in which each function can be implemented by one m-LUT such that either the total number of functions or the number of levels of the circuit is minimized. In this work, we focus on a different though related problem: synthesize the given circuit on a single memory or LUT L, which has a capacity of M bits. In addition to satisfying the memory constraint M, we also wish to minimize the total number of functions to be implemented. The main motivation for the problem comes from the problem of minimizing the simulation time on a hardware accelerator for logic simulation. This accelerator uses memory as a logic primitive. In fact, the problem is also relevant in the context of compile-code or software simulation. Another situation where the problem arises is in synthesis for the FPGA architectures being proposed that have on-chip memory for storing programs and data. The unused memory locations can be used to store logic functions. We show that the existing LUT synthesis methods are inadequate to solve this problem. We propose techniques to solve the problem and present experimental evidence to demonstrate their effectiveness.
Visualization and Performance Prediction of Multithreaded Solaris Programs by Tracing Kernel Threads
Authors: Magnus Broberg, Lars Lundberg, Håkan Grahn
Venue: Proceedings of the 13th International Symposium on Parallel Processing and the 10th Symposium on Parallel and Distributed Processing (1999)

Efficient performance tuning of parallel programs is often hard. We present a performance prediction and visualization tool called VPPB. Based on a monitored uni-processor execution, VPPB shows the (predicted) behaviour of a multithreaded program using any number of processors and the program behaviour is visualized as a graph.The first version of VPPB was unable to handle I/O operations. This version has, by an improved tracing technique, added the possibility to trace activities at the kernel level as well. Thus, VPPB is now able to trace various I/O activities, e.g., manipulation of OS internal buffers, physical disk I/O, socket I/O, and RPC. VPPB allows flexible performance tuning of parallel programs developed for shared memory multiprocessors using a standardized environment; C/C++ programs that uses the thread package in Solaris 2.X