ppxscal/embedding_network huggingface dataset:
FX!32: A Profile-Directed Binary Translator
Authors: Anton Chernoff, Mark Herdeg, Ray Hookway, Chris Reeve, Norman Rubin, Tony Tye, S. Bharadwaj Yadavalli, John Yates
Venue: IEEE Micro (1998)

Because the DIGITAL Alpha architecture provides the world's fastest processors, many applications, especially those that require very high performance, have been ported to that architecture. However, many other applications are available only under the x86 architecture. DIGITAL FX!32ý was designed to make the complete set of applications, both native and x86, available to Alpha. The goal for DIGITAL FX!32 is to provide fast and transparent execution of x86 Win32 applications on Windows NT Alpha. DIGITAL FX!32 achieves its goal by transparently running those applications at speeds that are comparable to high-performance x86 platforms. Before the introduction of DIGITAL FX!32, there were two technologies for running an application on a different architecture than the one for which it was originally compiled: emulation and binary translation. Each technology has an advantage, but also a drawback. Emulation is transparent and robust, but delivers only modest performance. Binary translation[11] is fast, but not transparent. For the first time, DIGITAL FX!32 combines these technologies to provide both fast and transparent execution. DIGITAL FX!32 consists of three interoperating components. There is a run-time environment that provides the transparent execution, a binary translator (the background optimizer) that provides the high performance, and a server that coordinates them. Although DIGITAL FX!32 is transparent and does not require user intervention, it includes a graphical interface for monitoring status and managing system resources. The first time an x86 application is run, all of the application is emulated. Together with transparently running the application, the emulator generates an execution profile that describes the application's execution history. The profile shows which parts of the application are heavily used (for this user) and which parts are unimportant or rarely used. While the first run may be slow, it "primes the pump" for additional processing. Later, after the application exits, the profile data directs the background optimizer to generate native Alpha code as replacement for all the frequently executed procedures. When the application is next run, the native Alpha code is used and the application executes much faster. This process is repeated whenever a sufficiently enlarged profile shows that it is warranted. This article provides an overview of DIGITAL FX!32 and describes in depth the three most significant innovations: Transparent operation, Interface to the native APIs, Profile-driven binary translation.
The Challenges of Designing Groupware: A Case Study
Authors: Mark Davies, Kris Pettersen, Shankar Srinivasen, Katherine Kinsman
Venue: Computer (1994)

Designing a commercial software program is a study in market need and technological feasibility. This case study traces the development of a groupware product for managing scientific projects and data.
Software Development for Engineers with C, Pascal, C++, Assembly Language, Visual Basic, HTML, Javascript and Java, 1st edition
Authors: William J. Buchanan
Venue:  (1997)

:With the move toward s graphic user interface programming, engineers require a sound knowledge of several programming languages. This book introduces most of the main technical languages in a single volume. Using C++ and Pascal to provide a basic grounding in software development the author then goes on to introduce more advanced concepts such as object-oriented design through the development of C++. Sections on Visual Basic and 80X86 Assembly Language follow before Java, Windows NT and DOS are introduced, finishing with an overview of the UNIX system. All the example programs included relate to real life applications.
Failure Analysis of High-Density CMOS SRAMs: Using Realistic Defect Modeling and I/Sub DDQ/ Testing
Authors: Samir Naik, Frank Agricola, Wojciech Maly
Venue: IEEE Design Test (1993)

A rapid failure analysis method for high-density CMOS static RAMs (SRAMs) that uses realistic defect modeling and the results of functional and I/sub DDQ/ testing is presented. The key to the method is the development of a defect-to-signature vocabulary through inductive fault analysis. Results indicate that the method can efficiently debug the multimegabit-memory manufacturing process.
Test Challenges in Nanometer Technologies
Authors: Sandip Kundu, Sujit T. Zachariah, Sanjay Sengupta, Rajesh Galivanche
Venue: Journal of Electronic Testing: Theory and Applications (2001)

Device scaling has led to the blurring of the boundary between design and test: marginalities introduced by design tool approximations can cause failures when aggressive designs are subjected to process variation. Larger die sizes are more vulnerable to intra-die variations, invalidating analyses based on a number of given process corners. These trends are eroding the predictability of test quality based on stuck-at fault coverage. Industry studies have shown that an at-speed functional test with poor stuck-at fault coverage can be a better DPM screen than a set of scan tests with very high stuck-at fault coverage. Contrary to conventional wisdom, we have observed that a high stuck-at fault test set is not necessarily good at detecting faults that model actual failure mechanisms. One approach to address the test quality crisis is to rethink the fault model that is at the core of these tests. Targeting realistic fault models is a challenge that spans the design, test and manufacturing domains: the extraction of realistic faults has to analyze the design at the physical and circuit levels of abstraction while taking into account the failure modes observed during manufacture. Practical fault models need to be defined that adequately model failing behavior while remaining amenable to automatic test generation. The addition of these fault models place increasing performance and capacity demands on already stressed test generation and fault simulation tools. A new generation of analysis and test generation tools is needed to address the challenge of defect-based test. We provide a detailed discussion of process technology trends that are responsible for next generation test problems, and present a test automation infrastructure being developed at Intel to meet the challenge.
Linear phase-correction in synchronization: predictions, parameter estimation, and simulations
Authors: Dirk Vorberg, Hans-Henning Schulze
Venue: Journal of Mathematical Psychology (2002)

A stochastic model for synchronization with a metronome is analyzed which generalizes Wing and Kristofferson's (1973a, 1973b) two-level model for tapping. The model includes a motor component, a timekeeper component, and a linear phase error correction mechanism. The model's predictions of the asymptotic dependence structure of the synchronization errors and interresponse intervals are derived. Problems of identifiability and estimation of parameters are discussed.
Statistical Edge Detection: Learning and Evaluating Edge Cues
Authors: Scott Konishi, Alan L. Yuille, James M. Coughlan, Song Chun Zhu
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (2003)

We formulate edge detection as statistical inference. This statistical edge detection is data driven, unlike standard methods for edge detection which are model based. For any set of edge detection filters (implementing local edge cues), we use presegmented images to learn the probability distributions of filter responses conditioned on whether they are evaluated on or off an edge. Edge detection is formulated as a discrimination task specified by a likelihood ratio test on the filter responses. This approach emphasizes the necessity of modeling the image background (the off-edges). We represent the conditional probability distributions nonparametrically and illustrate them on two different data sets of 100 (Sowerby) and 50 (South Florida) images. Multiple edges cues, including chrominance and multiple-scale, are combined by using their joint distributions. Hence, this cue combination is optimal in the statistical sense. We evaluate the effectiveness of different visual cues using the Chernoff information and Receiver Operator Characteristic (ROC) curves. This shows that our approach gives quantitatively better results than the Canny edge detector when the image background contains significant clutter. In addition, it enables us to determine the effectiveness of different edge cues and gives quantitative measures for the advantages of multilevel processing, for the use of chrominance, and for the relative effectiveness of different detectors. Furthermore, we show that we can learn these conditional distributions on one data set and adapt them to the other with only slight degradation of performance without knowing the ground truth on the second data set. This shows that our results are not purely domain specific. We apply the same approach to the spatial grouping of edge cues and obtain analogies to nonmaximal suppression and hysteresis.
The IA-64 Itanium Processor Cartridge
Authors: William A. Samaras, Naveen Cherukuri, Srinivas Venkataraman
Venue: IEEE Micro (2001)

The driving force behind the Itanium processor cartridge is electrical bus performance for the external system bus and the internal L3 backside bus.
Control and Observation Structures for Analog Circuits
Authors: Yeong-Ruey Shieh, Cheng-Wen Wu
Venue: IEEE Design Test (1998)

As the complexity of electronic circuits and systems increases, so does the complexity of testing them. The level-sensitive scan-design (LSSD) structure used in a digital circuit enhances the controllability and observability of the circuit under test. For analog circuits, there also have been several approaches proposed to improve their observability based on the LSSD concept. However, none of these approaches provide control and observation capability for all test points simultaneously. In this article, we propose two control and observation structures for analog circuits. Using our approach, one is able to observe and control the DC voltage levels of all test points simultaneously, which is the basic diagnosis capability required for analog circuits. A calibration process is presented to ensure the accuracy of the excitation and read-out voltage levels. A second-order bandpass filter is used as an example showing the feasibility of our approach.
Optimal L1${\cal L}_1$ Approximation of the Gaussian Kernel With Application to Scale-Space Construction
Authors: Xiaoping Li, Tongwen Chen
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1995)

Scale-space construction based on Gaussian filtering requires convolving signals with a large bank of Gaussian filters with different widths. In this paper we propose an efficient way for this purpose by ${\cal L}_1$ optimal approximation of the Gaussian kernel in terms of linear combinations of a small number of basis functions. Exploring total positivity of the Gaussian kernel, the method has the following properties: 1) the optimal basis functions are still Gaussian and can be obtained analytically; 2) scale-spaces for a continuum of scales can be computed easily; 3) a significant reduction in computation and storage costs is possible. Moreover, this work sheds light on some issues related to use of Gaussian models for multiscale image processing.
Index
Venue: IEEE Transactions on Knowledge and Data Engineering (2001)

No abstract available.
Leakage and Process Variation Effects in Current Testing on Future CMOS Circuits
Authors: Ali Keshavarzi, James W. Tschanz, Siva Narendra, Vivek De, W. Robert Daasch, Kaushik Roy, Manoj Sachdev, Charles F. Hawkins
Venue: IEEE Design Test (2002)

Barriers to technology scaling, such as leakage and parameter variations, challenge the effectiveness of current-based test techniques. This correlative multi-parameter test approach improves current testing sensitivity, exploiting dependencies of transistor and circuit leakage on operating frequency, temperature, and body bias to discriminate fast but intrinsically leaky ICs from defective ones.
Integration challenges of porous ultra low-k spin-on dielectrics
Authors: K. Mosig, T. Jacobs, K. Brennan, M. Rasco, J. Wolf, R. Augur
Venue: Microelectronic Engineering (2002)

In the latest edition of the International Technology Roadmap for Semiconductors (ITRS), the predicted time for the introduction of porous ultra low-k materials with a dielectric constant of 2.2 has slipped significantly against earlier predictions. This is largely due to greater-than-expected problems with the integration of these fragile materials, which generally exhibit weak mechanical properties and low resistance against chemical attack, requiring great care during the integration process. This paper discusses some of the challenges encountered and improvements made at International Sematech and elsewhere regarding the integration of spin-on porous ultra low-k dielectrics into a copper dual damascene process.
Default Logic as a Query Language
Authors: Marco Cadoli, Thomas Eiter, Georg Gottlob
Venue: IEEE Transactions on Knowledge and Data Engineering (1997)

Research in nonmonotonic reasoning has focused largely on the idea of representing knowledge about the world via rules that are generally true but can be defeated. Even if relational databases are nowadays the main tool for storing very large sets of data, the approach of using nonmonotonic AI formalisms as relational database query languages has been investigated to a much smaller extent. In this work, we propose a novel application of Reiter's default logic by introducing a default query language (DQL) for finite relational databases, which is based on default rules. The main result of this paper is that DQL is as expressive as SO¿¿, the existential-universal fragment of second-order logic. This result is not only of theoretical importance: We exhibit queries¿which are useful in practice¿that can be expressed with DQL and cannot with other query languages based on nonmonotonic logics such as DATALOG with negation under the stable model semantics. In particular, we show that DQL is well-suited for diagnostic reasoning.
Information and Dynamics: Sequences of Call Markets
Authors: Jasmina Arifovic, John Ledyard
Venue: Information Systems Frontiers (2003)

This paper is part of a wider research project with the objective of creating computational testbeds for designing and testing new mechanisms&mdash;new economic and political institutions. Here we illustrate the power of such an approach by testing two call market designs in a repeated demand-supply environment. We find there to be significant differences in performance depending on the information provided to the traders between calls. In particular, we find that both dynamic and static performance is better, less volitility and higher gains from trade, if traders receive less information between calls.
A Highly OR-Parallel Inference Machine (Multi-ASCA) and its Performance Evaluation: An Architecture and its Load Balancing Algorithms
Authors: J. Naganuma, T. Ogura
Venue: IEEE Transactions on Computers (1994)

An architecture and its four load balancing algorithms for a highly OR-parallel inference machine are proposed, and its performance is evaluated in a trace-driven simulation study. This inference machine consists of a large number of processing elements (PEs) with serial I/O links directly connected to each other in a simply modified mesh network. Each PE is a high-speed sequential Prolog processor with its own local memory. The activity of all PEs is locally controlled by four new load balancing algorithms based on purely local communication. Communication is allowed only between directly connected PEs. These load balancing algorithms reduce communication overhead in a load balancing and make it possible to accomplish highly OR-parallel execution. A software simulator using a trace-driven simulation technique based on an inference tree has been developed, and some typical OR-parallel benchmarks such as the n-queens problem have been simulated on it. The average communication per load balancing is reduced by a factor ranging from 1/30 to 1/100 by the interaction of these load balancing algorithms as compared with a conventional copying method. The inference machine (1024 PEs; 32/spl times/32 array) attains 300-600 times parallel speedup, assuming 1 MLIPS (mega logical inferences per second) PE and a 20 MBPS (mega bits per second) each serial I/O link, which could be easily integrated on a single chip using current VLSI technology. This highly OR-parallel inference machine promises to be an important step towards the realization of a high-performance artificial intelligence system.
Knowledge-Based Decision Support in Business: Issues and a Solution
Authors: Vasant Dhar, Albert Croker
Venue: IEEE Expert: Intelligent Systems and Their Applications (1988)

The authors describe an implemented system supporting the maintenance of evolving symbolic models and the spreadsheet-like algebraic models based on them. The system's primitives are knowledge fragments that are instantiated into symbolic models; these fragments can be modified in response to changes in the task environment, and appropriate changes induced in the algebraic model to reflect changes in the symbolic model. They analyze model features for problem-solving in domains with three levels of structuredness: highly formalized problems. The authors define data structures used for representing choice sets and constraints and describe the system's procedural knowledge component, which allows knowledge represented in the structures to be used in an integrated way.
Doubling the Degree of Precision Without Doubling the Grid When Solving a Differential Equation with a Pseudo-Spectral Collocation Method
Authors: D. Dijkstra
Venue: Journal of Scientific Computing (2002)

In the conventional pseudo-spectral collocation method to solve an ordinary first order differential equation, the derivative is obtained from Lagrange interpolation and has degree of precision N for a grid of (N+1) points. In the present, novel method Hermite interpolation is used as point of departure. From this the second order derivative is obtained with degree of precision (2N+1) for the same grid as above. The associated theorem constitutes the main result of this paper. Based on that theorem a method in put forward in which the differential equation and the differentiated differential equation are simultaneously collocated. In this method every grid point counts for two. The double collocation leads to a solution accuracy which is superior to the precision obtained with the conventional method for the same grid. This superiority is demonstrated by 3 examples, 2 linear problems and a non-linear one. In the examples it is shown that the accuracy obtained with the present method is comparable to the solution accuracy of the standard method with twice the number of grid points. However, the condition number of the present method grows like N3 as compared to N2 in the standard method.
Low-Latency, Concurrent Checkpointing for Parallel Programs
Authors: K. Li, J. F. Naughton, J. S. Plank
Venue: IEEE Transactions on Parallel and Distributed Systems (1994)

Presents the results of an implementation of several algorithms for checkpointing andrestarting parallel programs on shared-memory multiprocessors. The algorithms arecompared according to the metrics of overall checkpointing time, overhead imposed bythe checkpointer on the target program, and amount of time during which thecheckpointer interrupts the target program. The best algorithm measured achieves itsefficiency through a variation of copy-on-write, which allows the most time-consumingoperations of the checkpoint to be overlapped with the running of the program beingcheckpointed.
VLSI Technologies for Artificial Neural Networks
Authors: Karl Goser, Ulrich Hilleringmann, Ulrich Rueckert, Klaus Schumacher
Venue: IEEE Micro (1989)

VLSI systems, basic integrated circuits, and silicon technologies are discussed. Novel circuit and design principles that provide a foundation for the implementation of a wide variety of neural network models in silicon are described. The key issues for a successful integration of neural systems are identified. The realization of algorithms in silicon is examined. Special-purpose hardware for carrying out the activation and transfer function and for the connection elements is discussed. A brief overview of the current silicon technologies is provided.
An Alternative Paradigm for Scalable On-Demand Applications: Evaluating and Deploying the Interactive Multimedia Jukebox
Authors: Kevin C. Almeroth, Mostafa H. Ammar
Venue: IEEE Transactions on Knowledge and Data Engineering (1999)

Straightforward, one-way delivery of audio/video through television sets has existed for many decades. In the 1980s, new services like pay-per-view and video-on-demand were touted as the ¿killer applications¿ for interactive TV. However, the hype quickly died away, leaving only hard technical problems and costly systems. As an alternative, we propose a new jukebox paradigm offering flexibility in how programs are requested and scheduled for playout. The jukebox scheduling paradigm offers flexibility ranging from complete viewer control (true video-on-demand), to complete service provider control (traditional broadcast TV). In this paper, we first describe our proposed jukebox paradigm and relate it to other on-demand paradigms. We also describe several critical research issues, including the one-to-many delivery of content, program scheduling policies, server location, and the provision of advanced services like VCR-style interactivity and advanced reservations. In addition, we present our implementation of a jukebox-based service called the Interactive Multimedia Jukebox(IMJ). The IMJ provides scheduling via the World Wide Web (WWW) and content delivery via the Multicast Backbone (MBone). For the IMJ, we present usage statistics collected during the past couple of years. Furthermore, using this data and a simulation environment, we show that jukebox systems have the potential to scale to very large numbers of viewers.
Priority and Collision Detection with Active Signaling - The Channel Access Mechanism of HIPERLAN
Authors: Philippe Jacquet, Pascale Minet, Paul Mühlethaler, Nicolas Rivierre
Venue: Wireless Personal Communications: An International Journal (1997)

HIPERLAN will provide a 23.5 Mbps data rate transmission to radio channel user. The medium access control is based on carrier sense (CSMA) and on active signaling. Active signaling is an original feature which makes it possible to merge priority contention and collision detection into an elegant and efficient channel access mechanism. In particular it is expected to boost the performance of HIPERLAN above the level of IEEE 8802.3 standard (Ethernet). It also gives the opportunity to mix time constraint traffics (like voice) with non-time constraint traffics (data) by making use of access priorities.
Pulse Arithmetic in VLSI Neural Networks
Authors: Alan F. Murray
Venue: IEEE Micro (1989)

This review explores the use of biological signaling methods to build silicon networks. Recent designs using a technique called 'pulse stream', which employs fully analog, dynamic weight storage, are described. The pulse-stream concept is explained, and a comparison is made with conventional analog neural networks. An analog synapse based on the pulse-stream approach is presented. Chip details and simulation results are given.