ppxscal/embedding_network huggingface dataset:
A cache coherence scheme with fast selective invalidation
Authors: H. Cheong, A. V. Vaidenbaum
Venue: ACM SIGARCH Computer Architecture News (1988)

Software-assisted cache coherence enforcement schemes for large multiprocessor systems with shared global memory and interconnection network have gained increasing attention. Proposed software-assisted approaches rely on either indiscriminate invalidation or selective invalidation to invalidate stale cache lines. The indiscriminate approach combined with advanced memory hardware can quickly invalidate the entire cache but may result in lower hit ratios. The selective approach may achieve a better hit ratio. However, sequential selection and invalidation of cache or TLB entries is time consuming. We propose a new solution that offers the fast operation of the indiscriminate invalidation approach and can selectively invalidate cache items without extensive run-time book-keeping and checking. The solution relies on the combination of compile-time reference tagging and individual invalidation of potentially stale cache lines only when referenced. Performance improvement over an indiscriminate invalidation approach is presented.
Multi-level logic simplification using don't cares and filters
Authors: A. Saldanha, A. R. Wang, R. K. Brayton, A. L. Sangiovanni-Vincentelli
Venue: Proceedings of the 26th ACM/IEEE Design Automation Conference (1989)

Simplication of a multi-level network is used to perform transformations on parts of the network to obtain an alternate structure that is optimal with respect to area. A technique for obtaining such an optimal structure involves the use of two-level logic minimization on the components of the multi-level logic network. At each component, the structure of the network is captured by intermediate and fan-out don't care sets, which are utilized in the two-level minimization. However, the generation of all the don't cares yield very large sets for most networks and consequently the complete minimization of the components of the circuits require a very large amount of computer time. In this paper we describe algorithms to reduce the size of the don't care sets, so that only the portions that will be useful in minimization at each component of the circuit are retained. We develop both an exact filter and a heuristic filter that prove to be very effective for a large set of benchmark examples. Results show that our technique achieves the same quality as that obtained by doing complete minimizations at each component of the circuits but in much shorter time. This new approach to simplification of multi-level networks has been incorporated into the MIS (version 2.1) logic synthesis system.
Ray tracing on a connection machine
Authors: H. C. Delany
Venue: Proceedings of the 2nd international conference on Supercomputing (1988)

A new ray-tracing algorithm designed specifically for massively parallel hypercube connected processors is introduced. World space is subdivided according to a fixed size 3-D orthogonal grid. Rays are traced using ray-points which move along the rays, referencing the voxels intersected. One processor is assigned per ray, as well as one processor per object fragment. A pointerless data structure called an induced octree is used. This structure exists only as an ordering of the data in processor-address space, yet with it, all processors can determine the jump-distance to the nearest non-empty voxel in parallel to within a power of two. Ray-points move by large jumps whenever possible, and ray-object intersection proceeds in log time in the average ray length. Sorting via the network is the parallel analogue to octree-traversal. A code-scheduling mechanism is introduced which improves processor usage for SIMD architectures. Preliminary results are presented for an implementation using a CM-1 CPU equipped with 16k processors.
SAIRVO: a temporal planning system
Authors: M. Lizotte, B. Moulin
Venue: Proceedings of the 2nd international conference on Industrial and engineering applications of artificial intelligence and expert systems - Volume 1 (1989)

Our approach of planification which derives from both expert systems and planning systems design techniques (MOU 86)(MOU 88), is based on several principles dealing with time management and the planner's universe modelling, the representation of its motivations and behavioural knowledge, the dynamic construction of its planning knowledge, as well as the use of metaplanning techniques to coordinate the planners reasoning activities. We will present a brief outline of research works related to planning systems. We will describe the knowledge structures implemented in SAIRVO and present the general architecture of the system.
Elimination of bottlenecks in dynamic dataflow processors
Authors: K. B. Irani, K. Q. Luc
Venue: Proceedings of the 1988 ACM/IEEE conference on Supercomputing (1988)

A key component of a dynamic dataflow processor, the matching unit, has been identified as a major bottleneck. An alternate implementation for the matching unit is presented. This implementation increases the operating bandwidth of the unit by allowing token matching operations to be done concurrently. The adoption of the proposed implementation also reveals throughput limitations of other units within the processor. As a result, a new configuration for a dynamic dataflow processor is proposed. We believe that the proposed processor is cost-effective, gives high performance, and is capable of incremental performance improvement.
Renormalisation group, function iterations and computer algebra
Authors: H. Caprasse
Venue: Journal of Symbolic Computation (1990)

The set of perturbative solutions of the renormalisation group equation relative to the coupling constant known in quantum field theory is studied. It is shown that it is generated by the continuous iteration of a particular solution. The iteration parameter, which may be complex, is the parameter of an abelian group whose generator is proportional to @b. Two new lemmas are derived. They are useful to construct a simple algorithm to find the continuous iteration of various functions and to deduce trivially, from the already known iteration of a function, the continuous iteration of a whole family of functions. It is pointed out how one can find iterations of functions which do not satisfy the perturbative boundary condition. The algorithm has been implemented in REDUCE and several examples are discussed.
A New Technique to Extract Range Information From Stereo Images
Authors: Y. C. Shah, R. Chapman, R. B. Mahani
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1989)

Results are described for an algorithm that automatically registers two stereo images. An exact area registration process which automatically removes all residual distortion due to the geometry of the stereo imaging system is demonstrated. This process allows the match judgement to be based upon an analysis of the residual differences of structure and intensity existing after all differences due to geometrical distortion have been corrected. The accuracy in general seems to be of the order of 1% of range, since the average distance to the model was about 600 mm and the RMS error in range was about 6 mm. The fact that the maximum error was greater by a factor of five indicates that there were still some mismatched points and the procedures followed in the stereo ranging algorithm were not sufficient. Further modifications to the algorithm are needed.
Fault Injection for Dependability Validation: A Methodology and Some Applications
Authors: Jean Arlat, Martine Aguera, Louis Amat, Yves Crouzet, Jean-Charles Fabre, Jean-Claude Laprie, Eliane Martins, David Powell
Venue: IEEE Transactions on Software Engineering (1990)

The authors address the problem of validating the dependability of fault-tolerant computing systems, in particular, the validation of the fault-tolerance mechanisms. The proposed approach is based on the use of fault injection at the physical level on a hardware/software prototype of the system considered. The place of this approach in a validation-directed design process and with respect to related work on fault injection is clearly identified. The major requirements and problems related to the development and application of a validation methodology based on fault injection are presented and discussed. Emphasis is put on the definition, analysis, and use of the experimental dependability measures that can be obtained. The proposed methodology has been implemented through the realization of a general pin-level fault injection tool (MESSALINE), and its usefulness is demonstrated by the application of MESSALINE to the experimental validation of two systems: a subsystem of a centralized computerized interlocking system for railway control applications and a distributed system corresponding to the current implementation of the dependable communication system of the ESPRIT Delta-4 Project.
The symptom-component approach to knowledge acquisition
Authors: J. Bradley, K. Harbison-Briggs
Venue: Issue 108 (April 1989) (1989)

Knowledge acquisition is a critical aspect of the knowledge engineering approaches that are used in complex diagnostic problem-solving. Experience with a machine diagnostic problem pointed to difficulties in mapping the acquired knowledge to the fault tree representation and with obtaining an overall picture of the system. We also found that use of the prototype for interactive knowledge elicitation required extremely structured interviews to allow the knowledge engineer time for on-line changes. A knowledge acquisition methodology was developed that works in conjunction with a fault-tree diagnostic tool. The methodology employs task analysis, process analysis, structured interviews, and analogies in a process that focuses on the relationships between symptoms and faults.To correct the problems encountered during task analysis of the fault tree, we used a systems approach to modify the original knowledge acquisition methodology. In the modified methodology, knowledge comprising the symptom and component trees is acquired independently in an almost mechanical fashion. Information to link the symptoms to the components is then obtained from the most capable experts using standard knowledge acquisition techniques. This process has the advantage of providing a framework of symptoms and components that focus the knowledge acquisition activities toward identifying the relationships between these objects as well as assisting in verification and validation during later knowledge acquisition sessions. The new methodology also helps to structure the placement of faults, and questions about faults, to avoid replication and to fit easily into the tool logic. We believe that the symptom-component approach to knowledge acquisition for component diagnostic problems is a significant improvement on our original approach and that it can have general applicability to fault-tree diagnosis.
Placing the largest similar copy of a convex polygon among polygonal obstacles
Authors: L. P. Chew, K. Kedem
Venue: Proceedings of the fifth annual symposium on Computational geometry (1989)

Given a convex polygon P and an environment consisting of polygonal obstacles, we find the largest similar copy of P that does not intersect any of the obstacles. Allowing translation, rotation, and change-of-size, our method combines a new notion of Delaunay triangulation for points and edges with the well-known functions based on Davenport-Schinzel sequences producing an almost quadratic algorithm for the problem. Namely, if P is a convex k-gon and if Q has n corners and edges then we can find the placement of the largest similar copy of P in the environment Q in time &Ogr;(k4n &lgr;4(kn) log n), where &lgr;4 is one of the almost-linear functions related to Davenport-Schinzel sequences. If the environment consists only of points then we can find the placement of the largest similar copy of P in time &Ogr;(k2n &lgr;3(kn) log n).
DVPP: a VLSI dynamic-graph ensemble machine
Authors: Hancu, K. C. Smith
Venue: Proceedings of the 2nd international conference on Supercomputing (1988)

In a previous paper, we proposed a special environment and techniques for the implementation of highly parallel processing. A new VLSI supercomputer architecture, DYPP (DYnamically Programmable multi-Processor), was introduced, with the unique property of being able to embed, and execute directly, program graphs both statically and dynamically. Either asynchronous (dataflow) or synchronous implementations of program graphs can be realized in DYPP. In the present paper, we provide further insight in its operation. In the proposed ensemble architecture, we separate processing and communication into two distinct, though overlapping and interacting layers. Separate, simpler (and thus more reliable), processors are assigned to the connectivity layer, which becomes active and self-adaptive, thus being able to detect and compensate for malfunctions in the underlying layer of main processing elements. There is no global control at either level. Rather in a first, static, version, the program graph (incorporating both connectivity information and operators, that is instructions), is &ldquo;injected&rdquo; in a preliminary, separate, phase via the connectivity-layer processors. In this phase, the connectivity graph is embedded between live (operational) main processing elements. In the second phase, processing takes place. A more advanced option makes the connectivity layer fully dynamic. In this case, the program graph is continuously injected (embedded) in a flow fashion to interact with the flow of data and intermediate results, which flow is said to become leviating. This can greatly reduce the need for local program memory and large numbers of PEs, and correspondingly the required VLSI area. As well, it can dispel the need for (large) resident, localized, static programs characteristically present in von Neumann architectures. Based on data levitation, the generalization of systolic arrays becomes feasible.
Typed representation of objects by functions
Authors: J. Steensgaard-Madsen
Venue: ACM Transactions on Programming Languages and Systems (TOPLAS) (1989)

A systematic representation of objects grouped into types by constructions similar to the composition of sets in mathematics is proposed. The representation is by lambda expressions, which supports the representation of objects from function spaces. The representation is related to a rather conventional language of type descriptions in a way that is believed to be new. Ordinary control-expressions (i.e.,case- and let-expressions) are derived from the proposed representation.
A general architecture for factory-based diagnosis of electronics
Authors: Scott L. Kaplin, George D. Hadden, Lina Volovik, Rick Swanson
Venue: Proceedings of the 1st international conference on Industrial and engineering applications of artificial intelligence and expert systems - Volume 1 (1988)

This paper describes an architecture, IFADS (Integrated Factory-based Automatic Diagnostic System), that is well suited for performing diagnosis of electronic assemblies that fail factory-based quality assurance testing. Diagnostics in a manufacturing setting differ in several ways from that in an end-user setting. These differences are noted and the motivation for the IFADS design is shown. The purpose of modern Automatic Test Equipment (ATE) is to indicate whether a piece of equipment is operating within specifications. &ldquo;Diagnosis&rdquo;, on the other hand goes beyond this to identify the cause of the problem as well. ATE usually contains most of the functionality required to extend this to diagnosis, e.g., the ability to stimulate the inputs in a variety of ways and to measure the outputs and testpoints. Lacking is the ability to analyze the data and determine the probable cause of the fault or the ability to control the tests applied based on the results of previous tests. One of the most interesting characteristics of the IFADS architecture is that it fuses several reasoning techniques to arrive at a diagnosis. Some of these are topological methods, including backtracing from &ldquo;bad&rdquo; testpoints and backtracing from &ldquo;good&rdquo; Testpoints. A new topological technique is presented which is able to assemble a first approximation of an ordered list of the device's components such that components earlier in the list are more likely to be the cause of the problem than components later in the list. Other techniques use causal information to explain abnormal testpoint data. Still other methods are heuristically based. (Our goal is to minimize the amount of heuristic knowledge required and, for generality, evolve our system toward one which can reason from circuit information alone.) Each of these techniques is fully discussed. In order to make full use of these reasoning methods, the IFADS architecture utilizes several types of domain knowledge. For a particular piece of equipment the following information is represented: the physical hierarchy (how the equipment is assembled), the functional hierarchy (how the equipment is broken down according to function &mdash; usually not the same as the physical hierarchy), a mapping between the physical and functional hierarchies, function names and cause-effect relations, and statistical failure probabilities. We built a working prototype of the IFADS architecture to diagnose a torpedo sonar receiver.
On determining the solvability of polynomials
Authors: K. Yokoyama, M. Noro, T. Takeshima
Venue: Proceedings of the international symposium on Symbolic and algebraic computation (1990)

Landau and Miller presented a method for determining the solvability of a monic irreducible polynomial over integers in polynomial time. In their method, a series of polynomials is constructed so that the original problem is reduced to determining the solvability of new polynomials. Here, we present an improved method for finding such a series of polynomials efficiently. More precisely, we introduce a new notion on a series of blocks in the set of all roots of the original polynomial under the action of its Galois group, and then present an efficient method for finding such a series of blocks by modifying Landau and Miller's method for finding minimal imprimitive blocks.
Video and design
Authors: Austin Henderson
Venue: ACM SIGCHI Bulletin (1989)

Four relations between video and design are identified. One, the role of video in support of the activity of design, is explored in some detail. It is asserted that more than one of these relations is present in the usual situation.
Perspectives on algorithm animation
Authors: M. H. Brown
Venue: Proceedings of the SIGCHI conference on Human factors in computing systems (1988)

Systems for animating algorithms have received considerable interest of late as effective means for understanding computer programs. Thus far, nothing has been reported in the literature concerning nature of the displays nor to what extent displays can be created automatically. This paper addresses these two issues. The first part presents a taxonomy of displays prevalent in algorithm animation systems; the second part uses the taxonomy to analyze those types of displays that can and cannot be created automatically from unmodified source code.
The multifrontal method and paging in sparse Cholesky factorization
Authors: Joseph W. H. Liu
Venue: ACM Transactions on Mathematical Software (TOMS) (1989)

In this paper, we show that the multifrontal method can have significant advantage over the conventional sparse column-Cholesky scheme on a paged virtual memory system. A more than tenfold reduction in paging activities can be achieved, which saves as much as 20 percent in factorization time. We also introduce a hybrid sparse factorization method, which uses a mixture of column-Cholesky and submatrix-Cholesky operations. By switching to the use of frontal matrices from column-Cholesky operations at appropriate columns, we demonstrate that the proposed hybrid scheme has an advantage over the sparse column-Cholesky method in reducing paging activities and over the multifrontal method in its adaptability to the amount of available working storage.
Minimal and complete word unification
Authors: Joxan Jaffar
Venue: Journal of the ACM (JACM) (1990)

The fundamental satisfiability problem for word equations has been solved recently by Makanin. However, this algorithm is purely a decision algorithm. The main result of this paper solves the complementary problem of generating the set of all solutions. Specifically, the algorithm in this paper generates, given a word equation, a minimal and complete set of unifiers. It stops if this set is finite.
Automatic failure analysis of VLSI circuits using E-beam
Authors: D. Savart, B. Courtois
Venue: Microelectronic Engineering (1988)

The aim of this paper is to describe a new strategy for failure analysis in random logic devices such as microprocessors and other VLSI chips when the electrical scheme is not known. This strategy is based upon the use of a test tool composed of a Scanning Electron Microscope (SEM) allied to voltage contrast, an exerciser, an image processing system and a control and data processing system. Such a tool has been developed since 1982 and it is described in this paper. Data processing already implemented is given. First results of the method application, based upon image comparisons, are shown. Finally future working directions are mentioned.
A polynomial time algorithm for testing implications of a join dependency and embodied functional dependencies
Authors: J. Leuchner, L. Miller, G. Slutzki
Venue: Proceedings of the 1988 ACM SIGMOD international conference on Management of data (1988)

The problem of deciding whether a full join dependency (JD) &bowtie; [R] and a set of functional dependencies (FDs) F imply an embedded join dependency (EJD) &bowtie; [S] is known to be NP-complete. We show that the problem can be decided in polynomial time if S &sube; R and F is embedded in R. Our work uses arguments based on an extension of complete intersection graphs rather than tableaus. This approach has facilitated our results and should prove useful for future research.
Incremental data flow analysis via dominator and attribute update
Authors: M. D. Carroll, B. G. Ryder
Venue: Proceedings of the 15th ACM SIGPLAN-SIGACT symposium on Principles of programming languages (1988)

We present an algorithm for updating data flow information derived from a program, in response to program edits. Our algorithm, applicable to intraprocedural or interprocedural data flow problems, is more general than previous methods because it can update any monotone data flow problem defined on a reducible flow graph and can handle arbitrary program edits. Rather than design yet another special-purpose data flow update algorithm, we show how to reduce the class of data flow problems to another class of problems which already has a fast update algorithm. More specifically, we reduce a monotone data flow problem formulated for solution using Graham-Wegman elimination [12] to the problem of constructing and decorating an attributed tree structurally isomorphic to the dominator tree of the program flow graph. To update this dominator tree in response to program changes, we first show how to express domination in terms of two local properties of nodes and edges in the flow graph &mdash; niceness and deepness. Domination is then updated in response to an edge addition or deletion by repeatedly performing two local operations on the dominator tree, each operation restoring the local properties violated by the edge change. Second, we extend Reps' attributed tree update techniques [19,21,20] and his complexity analysis, to update attribute values in response to changes in this structure.