ppxscal/embedding_network huggingface dataset:
A Fast Modified CORDIC&mdash;Implementation of Radial Basis Neural Networks
Authors: U. Meyer-Bäse, A. Meyer-Bäse, J. Mellott, F. Taylor
Venue: Journal of VLSI Signal Processing Systems (1998)

This paper describes how the real-time bandwidth of a radial basis neural network (RBNN) can be improved by the use of a field programmable gate array (FPGA). Accelerated performance is gained by moving the time-consuming RBNN exponential calculations from a general purpose processor to a dedicated FPGA that implements an optimized CORDIC-algorithm. The design methodology is presented and illustrated with a speech recognition application.
The Solution to a Structured Matrix Approximation Problem Using Grassman Coordinates
Authors: Craig S. MacInnes
Venue: SIAM Journal on Matrix Analysis and Applications (1999)

A method for finding the best approximation of a matrix A by a full rank Hankel matrix is given. The initial problem of best approximation of one matrix by another is transformed to a problem involving best approximation of a given vector by a second vector whose elements are constrained so that its inverse image is a Hankel matrix. The map from a matrix to a vector is the invertible map between a subspace represented as the row space of the matrix A and the Grassman vector representing that subspace. The relation between the principle angles associated with a pair of subspaces and the angle between the Grassman vectors associated with the subspaces is established.
Design and Implementation of the MorphoSys Reconfigurable ComputingProcessor
Authors: Ming-Hau Lee, Hartej Singh, Guangming Lu, Nader Bagherzadeh, Fadi J. Kurdahi, Eliseu M. C. Filho, Vladimir Castro Alves
Venue: Journal of VLSI Signal Processing Systems (2000)

In this paper, we describe the implementation of MorphoSys, a reconfigurable processing system targeted at data-parallel and computation-intensive applications. The MorphoSys architecture consists of a reconfigurable component (an array of reconfigurable cells) combined with a RISC control processor and a high bandwidth memory interface. We briefly discuss the system-level model, array architecture, and control processor. Next, we present the detailed design implementation and the various aspects of physical layout of different sub-blocks of MorphoSys. The physical layout was constrained for 100 MHz operation, with low power consumption, and was implemented using 0.35 &mu;m, four metal layer CMOS (3.3 Volts) technology. We provide simulation results for the MorphoSys architecture (based on VHDL model) for some typical data-parallel applications (video compression and automatic target recognition). The results indicate that the MorphoSys system can achieve significantly better performance for most of these applications in comparison with other systems and processors.
Long-Run Abstinence After Narcotics Abuse: What Are the Odds?
Authors: Marnik G. Dekimpe, Linda M. Van De Gucht, Dominique M. Hanssens, Keiko I. Powers
Venue: Management Science (1998)

We consider the long-run odds that narcotics users remain abstinent after methadone treatment. A flexible split-hazard specification that allows for individual-level differences inboth the long-run probability of eventual relapse and the short-run timing of relapse is developed. The model is applied to a comprehensive data set involving individual drug abuse and treatment histories for over 800 addicts. Our findings indicate (1) that the short-run success of methadone programs does not automatically translate into long-run abstinence, which suggests the need for aftercare, (2) the value of preventing a teenager or young adult from initiating, and (3) the possibility of identifying high-risk groups, both in terms of age of first daily use and interms of ethnicity.
Structuring the student research experience
Authors: Andrew Bernat, Patricia J. Teller, Ann Gates, Nellie Delgado
Venue: Proceedings of the 5th annual SIGCSE/SIGCUE ITiCSEconference on Innovation and technology in computer science education (2000)

The benefits of working in a research group are clear: students develop domain expertise, gain an understanding and appreciation of the research process and its practice, and acquire team, communication, problem-solving, and higher-level thinking skills. Students with this experience are better equipped to make informed judgments about technical matters and to communicate and work in teams to solve complex problems. However, it is difficult to provide a quality experience to large numbers of students, particularly to students of differing abilities.The Systems and Software Engineering Affinity Research Group model provides a socialization mechanism and infrastructure that supports the development and management of large research groups that engage undergraduate and graduate students, who have a wide range of skill levels and experiences, in research and projects. This non-hierarchical model integrates students into both small research groups and an encompassing large research group, and uses structured activities to develop their research, technical, communication, and group skills.In this paper we introduce the model and report how the model meets independently developed Best Practice guidelines for student research experiences and we provide indicators of success for use by other projects.
Dynamic Reconfiguration to Support Concurrent Applications
Authors: Jack S. N. Jean, Karen Tomko, Vikram Yavagal, Jignesh Shah, Robert Cook
Venue: IEEE Transactions on Computers (1999)

This paper describes the development of a dynamically reconfigurable system that can support multiple applications running concurrently. A dynamically reconfigurable system allows hardware reconfiguration while part of the reconfigurable hardware is busy computing. An FPGA resource manager (RM) is developed to allocate and de-allocate FPGA resources and to preload FPGA configuration files. For each individual application, different tasks that require FPGA resources are represented as a flow graph which is made available to the RM so as to enable efficient resource management and preloading. The performance of using the RM to support several applications is summarized. The impact of supporting concurrency and preloading in reducing application execution time is demonstrated.
Clarifying straight replays and forced delays
Authors: Taekyoung Kwon, Jooseok Song
Venue: ACM SIGOPS Operating Systems Review (1999)

This paper clarifies straight replays which are one of replay attacks but have been somewhat misunderstood. There are various kinds of replay attacks on authentication protocols but most of the formal methods are not capable of detecting them because a replayed message may have appropriate data and structure for the protocols. [1] classified them and proposed their taxonomy that is useful for readily determining the effectiveness of some replay countermeasures and the appropriateness of analysis techniques for replays. [1] urges that any kinds of replay attacks are classified in the taxonomy. Among those classified attacks, however, straight replay attacks are ambiguous to be distinguished from forced delays which are really not regarded as replays.
Analysis of an Upwind-Mixed Finite Element Method for Nonlinear contaminant Transport Equations
Authors: Clint Dawson
Venue: SIAM Journal on Numerical Analysis (1998)

In this paper, the numerical approximation of a nonlinear diffusion equation arising in contaminant transport is studied. The equation is characterized by advection, diffusion, and adsorption. Assuming the adsorption term is modeled by a Freundlich isotherm, it can be nonlinear in concentration and nondifferentiable as the concentration approaches zero. We consider the approximation of this equation by a method which upwinds the advection and incorporates diffusion using a mixed finite element method. Error estimates for a semidiscrete formulation are derived, and numerical results for a fully discrete formulation are given.
Computation of Battle&ndash;Lemarie Wavelets Using an FFT-Based Algorithm
Authors: Jeng-Fan Leu, Jyh-Cheng Jang, Chyi Hwang
Venue: Journal of Scientific Computing (1998)

Battle and Lemarie derived independently wavelets by orthonormalizing B-splines. The scaling function &Phi;m(t) corresponding to Battle&ndash;Lemarie's wavelet &psi;m(t) is given by \phi_m(t)=\sum_{k \in {\bf Z}} \alpha_{m,k}\,B_m(t-k), where Bm(t) is the mth-order central B-spline and the coefficients &alpha;m, k satisfy \sum_{k \in {\bf Z}}\alpha_{m,k} e^{-jk\omega}=1/ \sqrt{\sum_{k \in {\bf Z}}B_{2m}(k)e^{-jk\omega}}. In this paper, we propose an FFT-based algorithm for computing the expansion coefficients &alpha;m, k and the two-scale relations of the scaling functions and wavelets. The algorithm is very simple and it can be easily implemented. Moreover, the expansion coefficients can be efficiently and accurately obtained via multiple sets of FFT computations. The computational approach presented in this paper here is noniterative and is more efficient than the matrix approach recently proposed in the literature.
Memory bank customization and assignment in behavioral synthesis
Authors: Preeti Ranjan Panda
Venue: Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design (1999)

With increasing design complexity and chip area, on-chip memory has become an important component whose integration needs to be addressed during system design. Modern embedded DRAM technology allows for large amounts of on-chip memory space. However, in order to utilize the available memory intelligently, the memory has to be appropriately customized for the specific application. We address the topic of incorporating the application-specific customization of memory bank configuration into behavioral synthesis. The strategy involves a partitioning of behavioral arrays into memory banks based on a cost function that estimates the performance implications. For a given candidate partition, we present a heuristic for determining the access sequence that minimizes page misses in a bank while respecting data dependences. The output of the exploration is a graph displaying the variation of delay and memory area with the bank configuration. Our experiments on several memory-intensive examples confirm that the exploration results can provide critical feedback to the designer about the optimal memory configuration for a given application.
Data compression methods for EEG
Authors: Jyri Ylöstalo
Venue: Technology and Health Care (1999)

Modern brain research experiments require the recording of large amounts of high-accuracy EEG data. Sampling frequency, bit resolution and number of channels are significantly larger than in routine clinical measurements. Because of this, the need of efficient signal compression has emerged. This paper presents a survey of available methods and explores some techniques, both lossy and lossless, for compressing EEG signals.
Preconditioning on Element Interfaces for the p-Version Finite Element Method and Spectral Element Method
Authors: Weiming Cao, Benqi Guo
Venue: SIAM Journal on Scientific Computing (1999)

In the preconditioned iterative method based on nonoverlapping domain decompositions, the preconditioner is usually of block diagonal type. To calculate its action on a residual vector, it is required to solve a linear system of algebraic equations with the coefficient matrix being the Schur complement block corresponding to the interface. To reduce the computational cost, the Schur complement blocks in the preconditioners can be replaced with other simpler matrices, which are called the interface preconditioners. In this paper, we discuss various interface preconditioners for the p-version finite element method and spectral element method in R2 and R3. Emphases are placed on (1) the lower and upper bounds of the condition numbers for the preconditioned Schur complement blocks using the interface preconditioners, which characterize the enlargement of the overall condition numbers, and (2) the algorithms to efficiently implement the interface preconditioners. Numerical results are presented for the condition numbers using various interface preconditioners.
Design of Communication Networks with Survivability Constraints
Authors: Young-Soo Myung, Hyun-Joon Kim, Dong-Wan Tcha
Venue: Management Science (1999)

The rapid growth of telecommunication capacity, driven in part by the wide-ranging deployment of fiber-optic technology has led to increasing concern regarding the survivability of such networks. In communication networks, survivability is usually defined as the percentage of total traffic surviving some network failures in the worst case. Most of the survivable network design models proposed to date indirectly ensure network survivability by invoking a connectivity constraint, which calls for a prespecified number of paths between every distinct pair of nodes in the network. In this paper, we introduce a new network design model which directly addresses survivability in terms of a survivability constraint which specifies the allowable level of lost traffic during a network failure under prescribed conditions. The new model enables a network designer to consider a richer set of alternative network topologies than the existing connectivity models, and encompasses the connectivity models as special cases. The paper presents a procedure to compute link survivability, develops an integer programming formulation of the proposed su rvivability model, and discusses a special case of practical interest and its associated heuristic procedure. The proposed heuristic is tested on data from real-world problems as well as randomly generated problems.
A Local Regularization Operator for Triangular and Quadrilateral Finite Elements
Authors: C. Bernardi, V. Girault
Venue: SIAM Journal on Numerical Analysis (1998)

This paper develops a local regularization operator on triangular or quadrilateral finite elements built on structured or unstructured meshes. This operator is a variant of the regularization operator of Clément; however, ours is constructed via a local projection in a reference domain. We prove in this paper that it has the same optimal approximation properties as the standard interpolation operator, and we present some applications.
Repeater insertion in tree structured inductive interconnect
Authors: Yehea I. Ismail, Eby G. Friedman, Jose L. Neves
Venue: Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design (1999)

The effects of inductance on repeater insertion in RLC trees is the focus of this paper. An algorithm is introduced to insert and size repeaters within an RLC tree to optimize a variety of possible cost functions such as minimizing the maximum path delay, the skew between branches, or a combination of area, power, and delay. The algorithm has a complexity proportional to the square of the number of possible repeater positions, permitting a repeater solution to be chosen that is close to the global minimum. The repeater insertion algorithm is used to insert repeaters within several copper-based interconnect trees to minimize the maximum path delay based on both an RC model and an RLC model. The two buffering solutions are compared using the AS/X dynamic circuit simulator. It is shown that as inductance effects increase, the area and power consumed by the inserted repeaters to minimize the path delays of an RLC tree decreases. By including inductance in the repeater insertion methodology, the interconnect is modeled more accurately as compared to an RC model, permitting average savings in area, power, and delay of 40.8%, 15.6%, and 6.7%, respectively, for a variety of copper-based interconnect trees from a 0.25 &mgr;m CMOS technology. The average savings in area, power, and delay increases to 62.2%, 57.2%, and 9.4%, respectively, when using five times faster devices with the same interconnect trees.
Fractional Splines and Wavelets
Authors: Michael Unser, Thierry Blu
Venue: SIAM Review (2000)

We extend Schoenberg's family of polynomial splines with uniform knots to all fractional degrees $\alpha>-1$. These splines, which involve linear combinations of the one-sided power functions $x_{+}^{\alpha}=\max(0,x)^{\alpha}$, are $\alpha$-H&ouml;lder continuous for $\alpha>0$. We construct the corresponding B-splines by taking fractional finite differences and provide an explicit characterization in both time and frequency domains. We show that these functions satisfy most of the properties of the traditional B-splines, including the convolution property, and a generalized fractional differentiation rule that involves finite differences only. We characterize the decay of the B-splines that are not compactly supported for nonintegral $\alpha$'s. Their most astonishing feature (in reference to the Strang--Fix theory) is that they have a fractional order of approximation $\alpha+1$ while they reproduce the polynomials of degree $\lceil\alpha\rceil$. For $\alpha>-\frac{1}{2}$, they satisfy all the requirements for a multiresolution analysis of $\LL^{2}$ (Riesz bounds, two-scale relation) and may therefore be used to build new families of wavelet bases with a continuously varying order parameter. Our construction also yields symmetrized fractional B-splines which provide the connection with Duchon's general theory of radial $(m,s)$-splines (including thin-plate splines). In particular, we show that the symmetric version of our splines can be obtained as the solution of a variational problem involving the norm of a fractional derivative.
Jit Manufacturing: a Survey of Implementations in Small and Large U.S. Manufacturers
Authors: Richard E. White, John N. Pearson, Jeffrey R. Wilson
Venue: Management Science (1999)

Since the early 1980s, the diffusion of Just-In-Time (JIT) manufacturing from Japanese manufacturers to U.S. manufacturers has progressed at an accelerated rate. At this stage of the diffusion process, JIT implementations are more common and more advanced in large U.S. manufacturers than in small; consequently, U.S. businessmen's understanding of issues associated with JIT implementations in large manufacturers is more developed than that of small manufacturers. When small manufacturers represent about 96 percent of all U.S. manufacturers, investigation of JIT impleme ntations in small, as well as large, manufacturers is warranted. This survey study investigates JIT implementation differences between small and large U.S. manufacturers. Ten management practices that constitute the JIT concept are used to examine implementation of JIT manufacturing systems. Odds ratio were constructed to determine if an association exists between implemented versus not implemented and manufacturer size for each JIT practice. Ten changes in performance attributed to JIT implementation are also assessed and examined in the study. Logistic regression models are used to examine the relationships between implementation status of each of the JIT practices and of each of the changes in performance in small and large manufacturers. The results of the study show that the frequencies of the 10 JIT management practices implemented differ between the two groups of manufacturer size, and an association exists between the JIT practices implemented and manufacturer size. Moreover, the changes in performance attributed to JIT implementation vary, depending on implementation status of specific JIT management practices and manufacturer size.
The Theory of Fexprs is Trivial
Authors: Mitchell Wand
Venue: Lisp and Symbolic Computation (1998)

We provide a very simple model of a reflective facility based on the pure &lambda;-calculus, and we show that its theory of contextual equivalence is trivial: two terms in the language are contextually equivalent iff they are &alpha;-congruent.
Automatic Vector Generation Using Constraints and Biasing
Authors: Jun Yuan, Kurt Shultz, Carl Pixley, Hillel Miller, Adnan Aziz
Venue: Journal of Electronic Testing: Theory and Applications (2000)

Constraining and biasing are frequently used techniques to enhance the quality of randomized vector generation. In this paper, we present a novel method that combines constraints and input biasing in automatic bit-vector generation for block-level functional verification of digital designs, which is implemented in a tool called SimGen. Vector generation in SimGen is confined to a legal input space that is defined by constraints symbolically represented in Binary Decision Diagrams (BDDs). A constraint involving state variables in the design defines a state-dependent legal input space. Input biasing can also depend on the state of the design. The effect of constraints and input biasing are combined to form what we called the constrained probabilities of input vectors. An algorithm is developed to efficiently generate input vectors on-the-fly during simulation. The vector generation is a one-pass process, i.e., no backtracking or retry is needed. Also, we describe methods of minimizing the constraint BDDs in an effort to reduce the simulation-time overhead of SimGen. Furthermore we discuss the application of SimGen to a set of commercial design blocks.
Modeling and performance of MEMS-based storage devices
Authors: John Linwood Griffin, Steven W. Schlosser, Gregory R. Ganger, David F. Nagle
Venue: ACM SIGMETRICS Performance Evaluation Review (2000)

MEMS-based storage devices are seen by many as promising alternatives to disk drives. Fabricated using conventional CMOS processes, MEMS-based storage consists of thousands of small, mechanical probe tips that access gigabytes of high-density, nonvolatile magnetic storage. This paper takes a first step towards understanding the performance characteristics of these devices by mapping them onto a disk-like metaphor. Using simulation models based on the mechanics equations governing the devices' operation, this work explores how different physical characteristics (e.g., actuator forces and per-tip data rates) impact the design trade-offs and performance of MEMS-based storage. Overall results indicate that average access times for MEMS-based storage are 6.5 times faster than for a modern disk (1.5 ms vs. 9.7 ms). Results from filesystem and database bench-marks show that this improvement reduces application I/O stall times up to 70%, resulting in overall performance improvements of 3X.
An international student/faculty collaboration: the Runestone project
Authors: Mary Z. Last, Mats Daniels, Vicki L. Almstrum, Carl Erickson, Bruce Klein
Venue: ACM SIGCSE Bulletin (2000)

Students of today need to be prepared to work in globally distributed organizations. Part of that preparation involves teaching students to work effectively in teams to solve problems. Students also must be able to work with individuals located at distant sites where there is no or very little face-to-face interaction. The Runestone project, an international collaboration between two universities, adds new dimensions to student teamwork, requiring students to handle collaboration that is remote, cross-cultural, and technically challenging. Runestone is a three-year project funded by the Swedish Council for the Renewal of Undergraduate Education. A pilot study in 1998 was followed by a full-scale implementation in 1999 with another implementation ongoing in 2000.Each time this global cooperation project is run, both students and faculty learn important lessons in how to work with each other in a virtual environment. This paper discusses both student and faculty learning outcomes for Runestone 1999.