ppxscal/embedding_network huggingface dataset:
Technical Section: Variational Bayesian noise estimation of point sets
Authors: Mincheol Yoon, Ioannis Ivrissimtzis, Seungyong Lee
Venue: Computers and Graphics (2009)

Scanning devices acquire geometric information from the surface of an object in the form of a 3D point set. Such point sets, as any data obtained by means of physical measurement, contain some noise. To create an accurate model of the scanned object, this noise should be resolved before or during the process of surface reconstruction. In this paper, we develop a statistical technique to estimate the noise in a scanned point set. The noise is represented as normal distributions with zero mean and their variances determine the amount of the noise. These distributions are estimated with a variational Bayesian method, which is known to provide more robust estimations than point estimate methods, such as maximum likelihood and maximum a posteriori. Validation experiments and further tests with real scan data show that the proposed technique can accurately estimate the noise in a 3D point set.
Beef quality risk identification and optimization in beef cattle breeding
Authors: Hui Li, Jian Zhang, Lingxian Zhang, Daoliang Li, Zetian Fu
Venue: Proceedings of the 13th WSEAS international conference on Applied mathematics (2008)

The meat industry is seeking to establish reassurance on traceability and production techniques that may help to promote confidence in the integrity and origin of the products. The overall tracing of beef quality is actually the risk identification and control along the supply chains of beef production. This study focused on the identification and control methods of quality risks in China traditional beef cattle breeding with optimization approaches concerned. The quality risks in beef cattle breeding were classified by features to develop the disseminated model of these risks and its algorithms. Then the theory of quality traceability was used and a concept model of quality risk control was proposed. Tracing units were divided and tracing nodes were set through optimization. The proposed risk identification and control models were capable of identifying and handling a product and the information attached to it throughout the whole production process to retail packs.
Cache design for low power and yield enhancement
Authors: Jacob A. Abraham
Venue:  (2008)

One of the major limiters to computer systems and systems on chip (SOC) designs is accessing the main memory, which is typically two orders of magnitude slower than the processor. To bridge this gap, modern processors already devote more than half of the on-chip transistors to the last-level cache. Caches have negative impact on area, power, and yield. This research goal is to design caches that operate at lower voltages while enhancing yield. Our strategy is to improve the static noise margin (SNM) and the writability of the conventional six-transistor SRAM cell by reducing the effect of parametric variations on the cell. This is done using a novel circuit that reduces the voltage swing on the word line during read operations and reduces the memory supply voltage during write operations. The proposed circuit increases the SRAM's SNM and write margin using a single voltage supply that has minimal impacts on chip area, complexity, and timing. A test chip with an 8-kilobyte SRAM block manufactured in 45-nm technology is used to verify the practicality of the contribution and demonstrate the effectiveness of the new circuit's implementation. Cache organization is one of the most important factors that affect cache design complexity, performance, area, and power. The main architectural choice for caches is whether to implement the tag array using a standard SRAM or using a content addressable memory (CAM). The choice made has far-reaching consequences on several aspects of the cache design, and in particular on power consumption. Our contribution in this area is an in-depth study of the complex tradeoffs of area, timing, power, and design complexity between an SRAM-based tag and a CAM-based one. Our results indicate that an SRAM-based tag design often provides a better overall design point and is superior with respect to energy, especially for interleaved multi-threading processors. Being able to test and screen chips is a key factor in achieving high yield. Most industry standard CAD tools used to analyze fault coverage and generate test vectors require gate level models. However, since caches are typically designed using a transistor-level flow, there is a need for an abstraction step to generate the gate models, which must be equivalent to the actual design (transistor level). The third contribution of the research is a framework to verify that the gate level representation of custom designs is equivalent to the transistor-level design.
Generalized model learning for reinforcement learning in factored domains
Authors: Todd Hester, Peter Stone
Venue: Proceedings of The 8th International Conference on Autonomous Agents and Multiagent Systems - Volume 2 (2009)

Improving the sample efficiency of reinforcement learning algorithms to scale up to larger and more realistic domains is a current research challenge in machine learning. Model-based methods use experiential data more efficiently than model-free approaches but often require exhaustive exploration to learn an accurate model of the domain. We present an algorithm, Reinforcement Learning with Decision Trees (rl-dt), that uses supervised learning techniques to learn the model by generalizing the relative effect of actions across states. Specifically, rl-dt uses decision trees to model the relative effects of actions in the domain. The agent explores the environment exhaustively in early episodes when its model is inaccurate. Once it believes it has developed an accurate model, it exploits its model, taking the optimal action at each step. The combination of the learning approach with the targeted exploration policy enables fast learning of the model. The sample efficiency of the algorithm is evaluated empirically in comparison to five other algorithms across three domains. rl-dt consistently accrues high cumulative rewards in comparison with the other algorithms tested.
Optimal Extension of Error Correcting Output Codes
Authors: Sergio Escalera, Oriol Pujol, Petia Radeva
Venue: Proceeding of the 2006 conference on Artificial Intelligence Research and Development (2006)

Error correcting output codes (ECOC) represent a successful extension of binary classifiers to address the multiclass problem. In this paper, we propose a novel technique called ECOC-ONE (Optimal Node Embedding) to improve an initial ECOC configuration defining a strategy to create new dichotomies and im-prove optimally the performance. The process of searching for new dichotomies is guided by the confusion matrices over two exclusive training subsets. A weighted methodology is proposed to take into account the different relevance between dichotomies. We validate our extension technique on well-known UCI databases. The results show significant improvement to the traditional coding techniques with far few extra cost.
System-on-chip design by proof-based refinement
Authors: Dominique Cansell, Dominique M&#x00e9;ry, Cyril Proch
Venue: International Journal on Software Tools for Technology Transfer (STTT) (2009)

Systems-on-chip (SoCs) and SoC architectures provide a collection of challenging problems related to specification, modelling techniques, security issues and structuring questions. We describe a design methodology integrating the event B method and characterized by the incremental and proof-controlled construction of SoC models. The essence of the methodology is the refinement of models, starting from system requirements and producing event B models for characterizing the system under development. The refinement is a unifying concept that ensures the consistency of the different models produced and our contribution is an illustration through a case study, namely a system for measuring the parameters of audio/video quality in the digital video broadcasting (DVB) set of digital TV standards. The first part is the derivation of an architecture of parameters from the document ETSI TR 101 290 and the validation of the architecture using invariants of B models. The second part is the proposal of B models of the SystemC scheduler and an instantiation of these abstract models of the simulation semantics by parameters of the SystemC codes automatically translated from the B models of the DVB system. Finally, the third part relies upon a proof-based methodology for deriving an operational semantics of a given system that is expressed by an event B model including invariant properties.
VAST: a visualization-based educational tool for language processors courses
Authors: Francisco J. Almeida-Martínez, Jaime Urquiza-Fuentes, J. Ángel Velázquez-Iturbide
Venue: ACM SIGCSE Bulletin (2009)

In this demonstration we present VAST, a visualization tool to support teaching language processors. On the one hand, VAST provides an API that allows generating visualizations of syntax trees independently of the parser generator. On the other hand, VAST provides a GUI with multiple views: the source code, the stack and the syntax tree.
Minimum Bayes Risk decoding for BLEU
Authors: Nicola Ehling, Richard Zens, Hermann Ney
Venue: Proceedings of the 45th Annual Meeting of the ACL on Interactive Poster and Demonstration Sessions (2007)

We present a Minimum Bayes Risk (MBR) decoder for statistical machine translation. The approach aims to minimize the expected loss of translation errors with regard to the BLEU score. We show that MBR decoding on N-best lists leads to an improvement of translation quality. We report the performance of the MBR decoder on four different tasks: the TC-STAR EPPS Spanish-English task 2006, the NIST Chinese-English task 2005 and the GALE Arabic-English and Chinese-English task 2006. The absolute improvement of the BLEU score is between 0.2% for the TC-STAR task and 1.1% for the GALE Chinese-English task.
Problematic Internet and mobile phone use and clinical symptoms in college students: The role of emotional intelligence
Authors: Marta Beranuy, Ursula Oberst, Xavier Carbonell, Ander Chamarro
Venue: Computers in Human Behavior (2009)

This study deals with maladaptive use of the Internet and the mobile phone and its relationship to symptoms of psychological distress and mental disorder, as well as to the possible role of Perceived Emotional Intelligence in this relationship. Three hundred and sixty-five undergraduate university freshmen at Ramon Llull University, Barcelona (Spain), majoring in four different studies (Psychology, Education, Journalism and Broadcasting, and Health Studies) replied to scales assessing the negative consequences of maladaptive use of both the Internet (CERI) and the mobile phone (CERM), a self-report scale on Perceived Emotional Intelligence (TMMS-24), and a clinical instrument to check for complaints related to the presence of psychological distress (Symptom Checklist-90-R; SCL-90-R). Results indicate that psychological distress is related to maladaptive use of both the Internet and the mobile phone; females scored higher than males on the mobile phone questionnaire, showing more negative consequences of its maladaptive use. With respect to major study, students of Journalism and Broadcasting showed a more maladaptive pattern of Internet use than students of other majors. The components of Perceived Emotional Intelligence contributed to the explanation of the variance of the general indicators of psychological distress, but to a lesser degree than maladaptive use of Internet and mobile phone.
An optimal lower bound for anonymous scheduling mechanisms
Authors: Itai Ashlagi, Shahar Dobzinski, Ron Lavi
Venue: Proceedings of the tenth ACM conference on Electronic commerce (2009)

We consider the problem of designing truthful mechanisms to minimize the makespan on m unrelated machines. In their seminal paper, Nisan and Ronen [14] showed a lower bound of 2, and an upper bound of m, thus leaving a large gap. They conjectured that their upper bound is tight, but were unable to prove it. Despite many attempts that yield positive results for several special cases, the conjecture is far from being solved: the lower bound was only recently slightly increased to 2.61 [5,10], while the best upper bound remained unchanged. In this paper we show the optimal lower bound on truthful anonymous mechanisms: no such mechanism can guarantee an approximation ratio better than m. This is the first concrete evidence to the correctness of the Nisan-Ronen conjecture, especially given that the classic scheduling algorithms are anonymous, and all state-of-the-art mechanisms for special cases of the problem are anonymous as well.
Local policies for resource usage analysis
Authors: Massimo Bartoletti, Pierpaolo Degano, Gian-Luigi Ferrari, Roberto Zunino
Venue: ACM Transactions on Programming Languages and Systems (TOPLAS) (2009)

An extension of the &lambda;-calculus is proposed, to study resource usage analysis and verification. It features usage policies with a possibly nested, local scope, and dynamic creation of resources. We define a type and effect system that, given a program, extracts a history expression, that is, a sound overapproximation to the set of histories obtainable at runtime. After a suitable transformation, history expressions are model-checked for validity. A program is resource-safe if its history expression is verified valid: If such, no runtime monitor is needed to safely drive its executions.
The Task Sharing Framework: A Generic Approach to Scaffolding Collaboration and Meta-Collaboration in Educational Software
Authors: Darren Pearce, Lucinda Kerawalla, Rose Luckin, Nicola Yuill, Amanda Harris
Venue: Proceeding of the 2005 conference on Towards Sustainable and Scalable Educational Innovations Informed by the Learning Sciences: Sharing Good Practices of Research, Experimentation and Innovation (2005)

This paper introduces a novel and general framework which operationalises the sharing of collaborative tasks between multiple users. In contrast to the majority of existing software used in a collaborative context, software developed under this framework provides each user with their own identical yet independent copy of the task which, by default, only they themselves can manipulate. This represents a departure from traditional turn-taking and dual control collaborative interaction styles and is intended to reduce the domination of one user over others as well as to provide the space for effective collaboration. The visual representation of agreement and disagreement is particularly emphasised since this has the potential to constructively mediate the resolution of collaborative disputes, especially if agreement is required at various points during the task. Under the framework, it is also possible to emulate traditional collaborative interaction styles and, more importantly, dynamically vary between them, thus manipulating the collaborative affordances of the user interface. This is likely to scaffold conversation between the users about how they are working together to complete the task; users would be collaborating about their own collaborative process. The framework therefore holds significant potential to scaffold not only collaboration but also meta-collaboration.
An energy-efficient instruction scheduler design with two-level shelving and adaptive banking
Authors: Yu-Lai Zhao, Xian-Feng Li, Dong Tong, Xu Cheng
Venue: Journal of Computer Science and Technology (2007)

Mainstream processors implement the instruction scheduler using a monolithic CAM-based issue queue (IQ), which consumes increasingly high energy as its size scales. In particular, its instruction wakeup logic accounts for a major portion of the consumed energy. Our study shows that instructions with 2 non-ready operands (called 2OP instructions) are in small percentage, but tend to spend long latencies in the IQ. They can be effectively shelved in a small RAM-based waiting instruction buffer (WIB) and steered into the IQ at appropriate time. With this two-level shelving ability, half of the CAM tag comparators are eliminated in the IQ, which significantly reduces the energy of wakeup operation. In addition, we propose an adaptive banking scheme to downsize the IQ and reduce the bit-width of tag comparators. Experiments indicate that for an 8-wide issue superscalar or SMT processor, the energy consumption of the instruction scheduler can be reduced by 67%. Furthermore, the new design has potentially faster scheduler clock speed while maintaining close IPC to the monolithic scheduler design. Compared with the previous work on eliminating tags through prediction, our design is superior in terms of both energy reduction and SMT support.
Experimental and theoretical thermal performance of double pass solar air heater with porous media
Authors: M. Yahya, K. Sopian, M. Y. Theeran, M. Y. Othman, M. A. Alghoul, M. Hafidz, A. Zaharim
Venue: Proceedings of the 7th WSEAS international conference on System science and simulation in engineering (2008)

A theoretical model has been developed to predict the thermal performance of double pass solar air heater with porous media. It is composed of five-coupled unsteady nonlinear partial differential equations which are solved by using numerical scheme. Instead of solving the simultaneous equations for temperature at each element, a matrix inversion was employed. An experimental setup has been designed and constructed. The thermal performance testing was conducted indoor by using a solar simulator. Comparisons of the theoretical and experimental results have been conducted and it was found the theoretical and the experimental results show a good agreement.
Self-Organizing Maps with Non-cooperative Strategies (SOM-NC)
Authors: Antonio Neme, Sergio Hernández, Omar Neme, Leticia Hernández
Venue: Proceedings of the 7th International Workshop on Advances in Self-Organizing Maps (2009)

The training scheme in self-organizing maps consists of two phases: i) competition, in which all units intend to become the best matching unit (BMU), and ii) cooperation, in which the BMU allows its neighbor units to adapt their weight vector. In order to study the relevance of cooperation, we present a model in which units do not necessarily cooperate with their neighbors, but follow some strategy. The strategy concept is inherited from game theory, and it establishes whether the BMU will allow or not their neighbors to learn the input stimulus. Different strategies are studied, including unconditional cooperation as in the original model, unconditional defection, and several history-based schemes. Each unit is allowed to change its strategy in accordance with some heuristics. We give evidence of the relevance of non-permanent cooperators units in order to achieve good maps, and we show that self-organization is possible when cooperation is not a constraint.
Mediated Web information retrieval for a complex searching task
Authors: Hyuk-Jin Lee, Gheorghe Muresan
Venue: Journal of the American Society for Information Science and Technology (2009)

The goal of this study is to understand whether providing a search intermediary familiar with a problem domain and its topical structure would support a user's Web searching tasks, especially complicated tasks with multifaceted topics, and whether the order of searching tasks or system usage influences their successful completion. This study investigates the effect of two factors, the interaction mode and the display layout, on the three main measures of the user's Web searching behaviors: effectiveness, efficiency, and usability. Two interaction modes are compared, mediation via a domain-specific document collection versus nonmediated search, and two display layouts, a combination of browsing-supporting hierarchic display and ranked list of results versus the simple linear list of search results. The results are analyzed in the Flow theory point of view; they were analyzed by order of the tasks and system usage order. The findings of this study contribute to a better understanding of how the mediation system and-or the combined display support a Web information user. &copy; 2009 Wiley Periodicals, Inc.
Visibility queries in a polygonal region
Authors: Rajasekhar Inkulu, Sanjiv Kapoor
Venue: Computational Geometry: Theory and Applications (2009)

In this paper, we consider the problem of computing the region visible to a query point located in a given polygonal domain. The polygonal domain is specified by a simple polygon with m holes and a total of n vertices. We provide two bounds on the complexity of this problem. One approach constructs a data structure with space complexity O(n^2) in time O(n^2lgn) and yields a query time of O((1+min(m,|V(q)|))lg^2n+m+|V(q)|). Here, V(q) represents the set of vertices of the visibility polygon of a query point q, and |E| denotes the number of edges in the visibility graph. The other approach provides a data structure with space complexity O(min(|E|,mn)+n) in time O(T+|E|+nlgn) with the query time of O(|V(q)|lgn+m). Here, T is the time to triangulate the given polygonal region (which is O(n+mlg^1^+^@em) for a small positive constant @e>0). In both of these approaches, O(m) additive factor in the query time is eliminated with an additional O((min(|E|,mn))^2) space and an additional O(m(min(|E|,mn))^2) preprocessing time.
Debugging support for security properties of software architectures
Authors: Kyungsoo Im, John D. McGregor
Venue: Proceedings of the 5th Annual Workshop on Cyber Security and Information Intelligence Research: Cyber Security and Information Intelligence Challenges and Strategies (2009)

Determining whether a software architecture meets its security requirements is an early step in assuring the security of the products developed from the architecture. In this paper, we propose a tool-based technique using an authorization scheme to analyze the security of software architectures. Such technique will serve as debugging support for software architectures to identify the portion in the software architecture that fails to meet the required level. Security is analyzed in terms of its aggregate attributes: availability, confidentiality, and integrity. In this paper, we address confidentiality and show that integrity is measured in a complementary manner to confidentiality. A scenario based approach is taken to analyze security in a software architecture. Our work is implemented in the OSATE environment and analyzes software architectures modeled using AADL (Architecture Analysis and Design Language).
Edge noise in document images
Authors: Craig McGillivary, Chris Hale, Elisa H. Barney Smith
Venue: Proceedings of The Third Workshop on Analytics for Noisy Unstructured Text Data (2009)

A degradation model that describes many image degradations produced by desktop scanning is used to study the edge noise that is present in bilevel document images. The standard deviation of the additive noise does not adequately describe the noise present after the image is converted to a bilevel image. A measure of noise called Noise Spread is developed which describes the edge noise and is a function of the scanner parameters. If phase effects are removed this Noise Spread quantity is directly proportional to the expected value of the Hamming distance between scans with and without edge noise. The Noise Spread has also been correlated with the ability to accurately estimate edge locations. A simple method to estimate this quantity is proposed.