ppxscal/embedding_network huggingface dataset:
Study of platinum thin films deposited by MOCVD as electrodes for oxide applications
Authors: O. Valet, P. Doppelt, P. K. Baumann, M. Schumacher, E. Balnois, F. Bonnet, H. Guillon
Venue: Microelectronic Engineering (2002)

Platinum thin films are suitable candidates as electrodes for high permittivity and ferroelectric oxides. Pt films were prepared by metal organic chemical vapor deposition (MOCVD) using a direct liquid delivery system. This method is based on the oxidative decomposition of (methylcyclopentadienyl)trimethylplatinum (MeCpPtMe3), as a precursor, diluted in cyclohexane solvent. Different deposition conditions were used to grow high purity platinum films on TiO2/SiO2/Si and SiO2 substrates. Adhesion properties of the Pt CVD films on TiO2 were found to be better than directly on SiO2 since TiO2 acts as a 'glue layer'. Platinum films deposited exhibit a roughness ranged from 3.1 to 4.5 nm and a thickness between 60 and 100 nm.
A personal history of the NSF digital government program
Authors: Melvyn Ciment
Venue: Communications of the ACM (2003)

The NSF Digital Government Program has its roots (circa 1993) in the NSF High-Performance Computing and Communications Program, and NSF's National Center for Supercomputing Applications (NCSA) at the University of Illinois. It was the creation of NCSA's Mosaic software suite of browsers and servers that prompted Larry Brandt, then a Program Manager for the NSF Supercomputer Centers Program, to start promoting a concept of driving innovative IT into government functions and services. At the time, I was Deputy Assistant Director for Computer Information Sciences and Engineering (CISE)1 and Brandt invited me to look at a demo of Mosaic. I was amazed and felt privileged to gaze into the future of a new software paradigm---the genesis of the Web.
Automatically characterizing large scale program behavior
Authors: Timothy Sherwood, Erez Perelman, Greg Hamerly, Brad Calder
Venue: Proceedings of the 10th international conference on Architectural support for programming languages and operating systems (2002)

Understanding program behavior is at the foundation of computer architecture and program optimization. Many programs have wildly different behavior on even the very largest of scales (over the complete execution of the program). This realization has ramifications for many architectural and compiler techniques, from thread scheduling, to feedback directed optimizations, to the way programs are simulated. However, in order to take advantage of time-varying behavior, we must first develop the analytical tools necessary to automatically and efficiently analyze program behavior over large sections of execution.Our goal is to develop automatic techniques that are capable of finding and exploiting the Large Scale Behavior of programs (behavior seen over billions of instructions). The first step towards this goal is the development of a hardware independent metric that can concisely summarize the behavior of an arbitrary section of execution in a program. To this end we examine the use of Basic Block Vectors. We quantify the effectiveness of Basic Block Vectors in capturing program behavior across several different architectural metrics, explore the large scale behavior of several programs, and develop a set of algorithms based on clustering capable of analyzing this behavior. We then demonstrate an application of this technology to automatically determine where to simulate for a program to help guide computer architecture research.
On-the-Fly Reseeding: A New Reseeding Technique for Test-Per-Clock BIST
Authors: Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos
Venue: Journal of Electronic Testing: Theory and Applications (2002)

In this paper we present a new reseeding technique for test-per-clock test pattern generation suitable for at-speed testing of circuits with random-pattern resistant faults. Our technique eliminates the need of a ROM for storing the seeds since the reseeding is performed on-the-fly by inverting the logic value of some of the bits of the next state of the Test Pattern Generator (TPG). The proposed reseeding technique is generic and can be applied to TPGs based on both Linear Feedback Shift Registers (LFSRs) and accumulators. An efficient algorithm for selecting reseeding points is also presented, which targets complete fault coverage and allows to well exploiting the trade-off between hardware overhead and test length. Using experimental results we show that the proposed method compares favorably to the other already known techniques with respect to test length and the hardware implementation cost.
Analyzing Packaging Trade-Offs During System Design
Authors: Peter A. Sandborn, Mike Vertal
Venue: IEEE Design Test (1998)

The primary drivers behind today's high-density electronic systems are time-to-market and cost. The very existence of many commercial products depends on finding quick design solutions that meet increasingly challenging performance and cost requirements. Central to the success of these products are highly developed design methodologies and tools that facilitate first pass success.The earliest stages of the design process provide the best opportunity to significantly impact a system's characteristics. This notion has lead to the concept of virtual prototyping, which allows system attributes to be defined and tested prior to large investments in design or fabrication. The integration of packaging tradeoff analysis with functional verification and architectural design, results in a complete virtual prototyping solution that can be used to optimize complex electronic systems. This paper discusses the role of packaging tradeoff analysis within the system design methodology.One key to minimizing the cost of a system without adversely effecting the time-to-market, is combining manufacturing information with application specific design information as early in the design process as possible. Including an analysis of the manufacturing costs associated with the implementation of systems, within the system design methodology avoids leaving money on the table at the end of development, without increasing the design time. Methods of estimating system economics are introduced and several design examples that highlight packaging design tradeoffs involving system cost and manufacturability are presented.
Debatable Development: What Should We Believe?
Authors: Stephen J. Andriole
Venue: IEEE Software (1995)

There is an enormous disconnection between what academicians and consultants think will revolutionize development and what actually works in the trenches. We have much to learn about what really works, what works a little, and what doesn't work at all. Debating issues over time can help us accumulate knowledge and reach a consensus on the most promising solutions.
SUAVE: Extending VHDL to Improve Data Modeling Support
Authors: Peter J. Ashenden, Philip A. Wilsey, Dale E. Martin
Venue: IEEE Design Test (1998)

Designers are increasingly using VHDL for high-level modeling. However, their task is hindered by the lack of object-oriented and genericity features in the language. Experience in programming languages shows that these features significantly aid management of complexity in large designs and promote re-use of modules. SUAVE extends VHDL by adapting several object-oriented and genericity features from Ada-95. The extensions improve support for modeling in VHDL from system level down to gate level. This article describes the extensions and illustrates their use with examples.
Structured Evaluation of Computer Systems
Authors: Günter Böckle, Hermann Hellwagner, Roland Lepold, Gerd Sandweg, Burghardt Schallenberger, Raimar Thudt, Stefan Wallstab
Venue: Computer (1996)

System development involves deciding which configuration and characteristics will determine a successful design. Suppose you must evaluate cache designs for a new computer system. The project manager might say something like "Determine the best cache for our new computer." You know that you have to evaluate cache systems, but what does "best" really mean? High performance? Low heat? Low cost? Minimum space? Even if you learn that performance is the goal, what technical properties must your evaluation consider? Which architectures must you consider? What kind of workload will this computer system have to handle? Evaluating how well a system will perform is difficult because it is seldom done systematically. An approach developed at Siemens makes decisions explicit and the process reproducible. We have used this method to evaluate mainly computer systems and communication systems design, including multiprocessor systems, a parallel file system, and an ATM network. Now we are disseminating the method within Siemens. You can use the method for evaluating all kinds of technical systems, and we believe you could adapt it to the analysis of social systems and organizations as well.
Response Time Analysis of OPS5 Production Systems
Authors: Albert Mo Kim Cheng, Jeng-Rung Chen
Venue: IEEE Transactions on Knowledge and Data Engineering (2000)

This paper focuses on the problem of determining a priori the maximal response time of rule-based programs. The response time analysis problem is an important problem, especially for real-time systems. We study this problem in the context of OPS5 production systems. Two aspects of the response time of a program are investigated, the maximal number of rule firings and the maximal number of basic comparisons made by the Rete network during the execution of the program. The response time analysis problem is in general undecidable. However, a program terminates in a finite time if the rule triggering pattern of this program satisfies certain conditions. In this paper, we present four such termination conditions for OPS5 production systems. An algorithm for computing an upper bound on the number of rule firings is then given. To have a better idea of the time required during execution, we present an algorithm that computes the maximal time required during the match phase in terms of the number of comparisons made by the Rete network. This measurement is sufficient since the match phase consumes about 90 percent of the execution time.
The Sun Fireplane Interconnect
Authors: Alan Charlesworth
Venue: IEEE Micro (2002)

A computing system's internal interconnect is a key determiner of its cost, performance, and reliability. The Sun Fireplane interconnect, used inside the Sun Microsystems UltraSPARC III generation of servers and workstations, builds on three generations of interconnects, and provides a significant increase in performance and system bandwidth.
Orthogonal matchings
Authors: Richard Stong
Venue: Discrete Mathematics (2002)

If a graph G is decomposed into m 2-factors, then an orthogonal matching is a matching M in G which contains exactly one edge from each 2-factor. It has been conjectured that any 2-factorization of any graph has an orthogonal matching. We prove this conjecture under the additional assumption that G has at least 3m - 2 vertices.
On cyclic k-arcs of Singer type in PG (2,q)
Authors: Massimo Giulietti
Venue: Discrete Mathematics (2002)

Let K be a k-arc in PG(2, q), q = pl, p prime, consisting of the points of a point orbit under a cyclic collineation group G. We show that if G is a subgroup of a Singer group of PG(2,q), if p is greater than 5, and if 2k is different from -2,1,2,4(mod p), then k ≤ (44/45)q+ 8/9.
Metkit: Toolkit for Metrics Education
Authors: Martin Bush, Nicholas Ashley
Venue: IEEE Software (1993)

Metkit, one of the ESPRIT II, information-processing system and software projects, is described. The organization of Metkit, the teaching packages, and the prototype CAI system are discussed. Metkit responded to the need for more material with which to teach measurement techniques as they apply to software engineering.
Applying the Minimum Risk Criterion in Stochastic Recourse Programs
Authors: Morten Riis, Rüdiger Schultz
Venue: Computational Optimization and Applications (2003)

In the setting of stochastic recourse programs, we consider the problem of minimizing the probability of total costs exceeding a certain threshold value. The problem is referred to as the minimum risk problem and is posed in order to obtain a more adequate description of risk aversion than that of the accustomed expected value problem. We establish continuity properties of the recourse function as a function of the first-stage decision, as well as of the underlying probability distribution of random parameters. This leads to stability results for the optimal solution of the minimum risk problem when the underlying probability distribution is subjected to perturbations. Furthermore, an algorithm for the minimum risk problem is elaborated and we present results of some preliminary computational experiments.
Order preservation of PEST determined certainty equivalents: a test based on lotteries with a fixed preference strength
Authors: Robert Sneddon
Venue: Journal of Mathematical Psychology (2002)

A major assumption of many utility theories is that preferences over lotteries are monotonic in consequences. Under additional reasonable conditions, this means that the choice certainty equivalent (CE) of a lottery should be substitutable for the lottery, but some empirical evidence has suggested otherwise. So several reasonable conditions need to be studied. They are monotonicity of consequences, order preservation of CEs, and bias in estimates of CEs. This paper addresses the second assumption. To do this an algorithm is devised that generates pairs of lotteries with exactly the same preference probability of choice. This permits one to average over both subjects and lotteries. With a sample size of 102, there was no evidence that order preservation of CEs is violated.
The Architecture of ALADIN: A Knowledge-Based Approach to Alloy Design
Authors: Ingemar Hulthage, Mark S. Fox, Michael D. Rychener, Martha L. Farinacci
Venue: IEEE Expert: Intelligent Systems and Their Applications (1990)

ALADIN, a knowledge-based system to aid aluminum alloy design for aerospace applications, is examined. Issues of interest in the ALADIN project are what the appropriate architecture is for the explicit representation and utilization of multiple alternative models, and how search in this space of multiple interacting models is to be focused. How ALADIN was designed to deal with these issues is briefly described. A discussion is presented of the structure of ALADIN's knowledge base, which captures complex technical concepts as well as data in symbolic, frame-based terms; a multilevel planning search architecture; and the integration of symbolic and numerical approaches. ALADIN's accomplishments are illustrated by examining one fragment of an interactive design session with the system.
Definitional Interpreters Revisited
Authors: John C. Reynolds
Venue: Higher-Order and Symbolic Computation (1998)

To introduce the republication of &ldquo;Definitional Interpreters for Higher-Order Programming Languages&rdquo;, the author recounts the circumstances of its creation, clarifies several obscurities, corrects a few mistakes, and briefly summarizes some more recent developments.
Bused Hypercubes and Other Pin-Optimal Networks
Authors: C. M. Fiduccia
Venue: IEEE Transactions on Parallel and Distributed Systems (1992)

Pin minimization is an important issue for massively parallel architectures because the number of processing elements that can be placed on a chip, board, or chassis is often pin limited. A d-dimensional bused hypercube interconnection network is presented that allows nodes to simultaneously (in one clock tick) exchange data across any dimension using only d+1 ports per node rather than 2d. Despite this near two-to-one reduction, the network also allows nodes that are two dimensions apart to simultaneously exchange data; as a result, certain routings can be performed in nearly half the time. The network is shown to be a special case of a general construction in which any set of d permutations can be performed, in one clock tick, using only d+1 ports per node. A lower-bound technique is also presented and used to establish the optimality of the network, as well as that of several other new bused networks.
KADBASE: Interfacing Expert Systems with Databases
Authors: H. Craig Howard, Daniel R. Rehak
Venue: IEEE Expert: Intelligent Systems and Their Applications (1989)

KADBASE, a knowledge-aided database management system prototype, is a flexible interface in which multiple databases and knowledge-aided database systems can communicate as independent, self-descriptive components within a loosely coupled distributed engineering computer system. The authors describe the final architecture of their working prototype, demonstrate its use in engineering applications, and provide examples from two civil engineering knowledge-based systems: SPEX, a structural component design system, and HICOST, a building-cost estimator.
Men's health: sports and exercise on the internet
Authors: David Howse
Venue: Health Care on the Internet (2002)

On both a general and sport-specific level, there are many Internet sites that can provide both the novice and advanced male athlete with an abundance of valuable information. Recent hospital emergency room statistics reveal that sports injuries are increasing dramatically across adult age groups, and this coincides with an explosion in new health and fitness related Web sites during the same period. Furthermore, studies suggest that public interest in visiting health and fitness Web sites has been correspondingly high. The author reviews several general and sport specific Web sites, covering areas such as general training and technique, diet, as well as rehabilitation of sports injuries.
A Nonblocking Quorum Consensus Protocol for Replicated Data
Authors: D. Agrawal, A. J. Bernstein
Venue: IEEE Transactions on Parallel and Distributed Systems (1991)

A nonblocking quorum protocol for replica control which guarantees one-copyserializability is developed. The effects of a nonblocking protocol are analyzed, and it isshown that the gains can be substantial under certain conditions. It is demonstrated thatin order for the protocol to be useful, it must be integrated with a propagationmechanism. It is also shown that the access latency can be reduced significantly in areplicated environment. An interesting aspect of the quorum protocol is that it essentiallyuses a read quorom/write-quorom approach for concurrency control but uses aread-one/write-all approach for replica control. It is shown that the nonblocking quoromprotocol provides the same level of availability and fault tolerance as the quorum protocol proposed by D.K. Gifford (1979).
Layoffs in the Computer Industry
Authors: John Keaton
Venue: Computer (1993)

The worldwide recession in the computer industry has resulted in substantial layoffs among computer professionals. Even more critical than the current slump is the permanent restructuring underway in the industry. Many jobs lost during this global downturn are likely to be gone from corporate organization charts forever. The changes in industry employment in the US are outlined, and the long-term employment outlook in the US is discussed.
Recovering from Multiple Process Failures in the Time Warp Mechanism
Authors: D. Agrawal, J. R. Agre
Venue: IEEE Transactions on Computers (1992)

A recovery protocol for distributed systems using the time warp control mechanism is described. The proposed protocol is fault tolerant to multiple process failures. Time warp is an optimistic execution technique in which synchronization is achieved using rollback. The recovery protocol exploits the redundancy already available to implement process rollback in the time warp mechanism. Thus, the protocol has little additional bookkeeping overhead, which contrasts with many other recovery protocols.
Fuzzy Clustering Using A Compensated Fuzzy Hopfield Network
Authors: Jzau-Sheng Lin
Venue: Neural Processing Letters (1999)

Hopfield neural networks are well known for cluster analysis with an unsupervised learning scheme. This class of networks is a set of heuristic procedures that suffers from several problems such as not guaranteed convergence and output depending on the sequence of input data. In this paper, a Compensated Fuzzy Hopfield Neural Network (CFHNN) is proposed which integrates a Compensated Fuzzy C-Means (CFCM) model into the learning scheme and updating strategies of the Hopfield neural network. The CFCM, modified from Penalized Fuzzy C-Means algorithm (PFCM), is embedded into a Hopfield net to avoid the NP-hard problem and to speed up the convergence rate for the clustering procedure. The proposed network also avoids determining values for the weighting factors in the energy function. In addition, its training scheme enables the network to learn more rapidly and more effectively than FCM and PFCM. In experimental results, the CFHNN method shows promising results in comparison with FCM and PFCM methods.
An HIPPI Interconnection System
Authors: I. Chlamtac, A. Ganz, M. G. Kienzle
Venue: IEEE Transactions on Computers (1993)

The proposed HIPPI standard, a connection-oriented communication standard for very-high-speed interconnection systems connecting high-end computing systems, is discussed. The problems of managing connections and of configuring the interconnection system as either a single crossbar switch or as a clique of crossbar switches are considered. Three connection management policies are introduced: a centralized policy, a broadcast policy, and a distributed policy. To compare these policies for different system configurations, a set of models is introduced and used to evaluate a range of interconnection system configurations. The results of these models and the use of a cost measure make it possible to compare the cost and performance of different configurations and alternative connection management policies.
Concurrent Checking of Clock Signal Correctness
Authors: Cecilia Metra, Michele Favalli, Bruno Riccò
Venue: IEEE Design Test (1998)

This paper presents a novel concept for concurrently checking the correctness of signals of clock distribution networks of synchronous systems. A VLSI circuitry is then proposed that, based on such a concept, performs the concurrent checking of such signals with respect to permanent and temporary (i.e., transient and intermittent) faults (permanently or temporary) changing their waveforms with respect to those expected in the fault-free case. Such a circuitry is in turn self-checking with respect to its possible permanent, as well as temporary, internal, realistic faults.