ppxscal/embedding_network huggingface dataset:
Theory-based Analysis of Cognitive Support in Software Comprehension Tools
Authors: Andrew Walenstein
Venue: Proceedings of the 10th International Workshop on Program Comprehension (2002)

Past research on software comprehension tools has produced a wealth of lessons in building good tools. However our explanations of these tools tends to be weakly grounded in existing theories of cognition and human-computer interaction. As a result, the interesting rationales underlying their design are poorly articulated, leaving the lessons primarily implicit. This paper describes a way of using existing program comprehension theories to rationalize tool designs. To illustrate the technique, key design rationales underlying a prominent reverse engineering tool (Reflexion Model Tool) are reconstructed. The reconstruction shows that theories of cognitive support can be applied to existing cognitive models of developer behaviour. The method for constructing the rationales is described, and implications are drawn for codifying existing design knowledge, evaluating tools, and improving design reasoning.
Boundary-type quadrature and boundary element method
Authors: T.-X. He, R. Zhang, Y. S. Zhou
Venue: Journal of Computational and Applied Mathematics (2003)

In this paper, we apply a boundary-type quadrature technique to derive a type of boundary element scheme, which is used to solve the boundary-value problems of partial differential equations. Numerical examples for solving the exterior boundary-value problem of Helmholtz equation by using the spline approximation and the spline wavelet approximation are given.
Towards Task Level Robot Programming
Authors: Bruce R Donald
Venue:  (1987)

This paper summarizes our research efforts in robotics. The primary goal is to bring robotics science closer to its goal of task-level planning. We approach this goal through blend of theory, implementation, and experimentation. We have identified several key problem areas on which to concentrate, and are undertaking research on generating assembly strategies from task-level descriptions. Our projects focus on: Algorithmic techniques for modelling geometric constraints, and the planning of robot motions using these constraints. The synthesis of compliant motion programs using the geometric constraints imposed by the task. The explicit modelling of uncertainty and error in sensing, control, and the shape of the manipulated parts. The development of a precise theory of Error Diagnosis and Recovery, and a method for generating sensor-based plans with built-in error detection and recovery. The heart of this research lies in a geometrical planning theory, for reasoning about and manipulating physical systems. We will develop this underlying theory, implement and test the theory in simulation, and conduct robotics laboratory experiments.
A Case Study on Construction of Groupware: Yuitori Network for Health, Welfare and Medical Works on Home Care
Authors: Takashi Mitsuishi, Yukihiro Kimura, Akiko Ogawa, Hiroyuki Kamata, Jun Sasaki, Yutaka Funyu
Venue: Proceedings of the Seventh International Conference on Parallel and Distributed Systems: Workshops (2000)

In order to perform efficient and affective home care works, we developed a collaboration system: ¿Yuitori Network¿ for health, welfare and medical works on home care. It is a groupware for workers on home care; public health nurses, helpers, nurses and doctors. It facilitates collaboration among workers by providing functions to plan a visiting schedule of workers, to store their visits records and share them including image data, and to manage some information of different facilities. We implemented the system on the computer network in a client-server style using data base system, experimented it practically in Iwate Prefecture and confirmed its effectiveness for collaboration among health, welfare and medical works.
Figures of Merit for Best-First Probabilistic Chart Parsing
Authors: Sharon A. Caraballo, Eugene Charniak
Venue:  (1996)

Best-first parsing methods for natural language try to parse efficiently by considering the most likely constituents first. Some figure of merit is needed by which to compare the likelihood of constituents, and the choice of this figure has a substantial impact on the efficiency of the parser. While several parsers described in the literature have used such techniques, there is no published data on their efficacy, much less attempts to judge their relative merits. We propose and evaluate several figures of merit for best-first parsing.
An analysis of multicast forwarding state scalability
Authors: Tina Wong, R. Katz
Venue: Proceedings of the 2000 International Conference on Network Protocols (2000)

Scalability of multicast forwarding state is likely to be a major issue facing inter-domain multicast deployment. We present a comprehensive analysis of the multicast forwarding state problem. Our goal is to understand the scaling trends of multicast forwarding state in the Internet, and to explore the intuitions that have motivated state reduction research. We conducted simulation experiments on both real and generated network topologies, with a range of parameters driven by multicast application characteristics. We found that the increase in peering among Internet backbone networks has led to more multicast forwarding state at a handful of core domains, but less state in the rest of the domains. We observed that scalability of multicast forwarding state with respect to session size follows a power law. Our findings show that distribution and concentration of multicast forwarding state in the Internet is significantly, impacted by the application characteristics. We investigated the proposals on non-branching multicast forwarding state elimination, and found substantial reduction is attainable even with very dense multicast sessions.
Some convergence theorems for mappings of asymptotically quasi-nonexpansive type in Banach spaces
Authors: S. S. Chang, Y. Y. Zhou
Venue: The Korean Journal of Computational Applied Mathematics (2003)

The purpose of this paper is to study the necessary and sufficient conditions for the sequences of Ishikawa iterative sequences with mixed errors of asymptotically quasi-nonexpansive type mappings in Banach spaces to converge to a fixed point in Banach spaces. The results presented in this paper extend and improve the corresponding results of [1-4, 7-9].
Energy Benefits of a Configurable Line Size Cache for Embedded Systems
Authors: Chuanjun Zhang, Frank Vahid, Walid Najjar
Venue: Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03) (2003)

Previous work has shown that cache line sizes impactperformance differently for different desktop programs -some programs work better with small line sizes, otherswith arger line sizes. Typical processors come with aline size that is a compromise, working best on theaverage for a variety of programs. We analyze theenergy impact of different line sizes, for 19 embeddedsystem benchmarks, and we show that tuning the linesize to a particular program can reduce memory accessenergy by 50% in some examples. Our data arguesstrongly for the need for embedded microprocessors tohave configurable line size caches, and for embeddedsystem designers to put effort into choosing the best linesize for their programs.
A two-level approach to automated conformance testing of VHDL designs
Authors: Jean R. Moonen, Judi M.T. Romijn, Olaf Sies, Jan G. Springintveld, Loe G.M. Feijs, Ronald L.C. Koymans
Venue:  (1997)

For manufacturers of consumer electronics, conformance testing of embedded software is a vital issue. To improve performance, parts of this software are implemented in hardware, often designed in the Hardware Description Language VHDL. Conformance testing is a time consuming and error-prone process. Thus automating (parts of) this process is essential.
Properties and applications of unified complex Hadamard transforms
Authors: B. J. Falkowski, S. Rahardja
Venue: Proceedings of the 27th International Symposium on Multiple-Valued Logic (1997)

A family of Unified Complex Hadamard Transforms derived from Walsh functions is defined. Newly developed direct matrix operator is introduced which is able to generate different types of Complex Hadamard matrices. Higher dimension matrices of the transforms may also be generated recursively by means of Kronecker product from basic matrices. Sparse matrix factorization or matrix partitioning of the Complex Hadamard matrices leads to the fast algorithms with complexity Nlog/sub 2/N. One of the shown fast algorithms may be implemented as in-place architecture which reduces memory requirements and allows on simple implementation in software or in hardware. Finally, different properties of the new transforms are shown and the performance of the transforms for Wiener filtering is evaluated and compared with the known discrete orthogonal transforms.
Self-Stabilizing Algorithms in DAG Structured Networks
Authors: Sajal K. Das, Ajoy K. Datta, Sebastien Tixeuil
Venue: Proceedings of the 1999 International Symposium on Parallel Architectures, Algorithms and Networks (1999)

This paper describes a parameterized protocol applicable to directed acyclic graph (DAG) topologies. The function parameter of the protocol is instantiated twice to design two protocols: (i) The topological sorting of the successor list at every node, and (ii) A shortest path routing table construction. Both protocols are self-stabilizing and thus they are resilient to transient failures and guarantee system recovery in a finite time linear in the network diameter. From the fact that a DAG topology can be imposed on a more general topology through graph labeling protocols, the solutions presented in this paper are expected to be quite useful for a large class of distributed systems, where an optimal routing along with the robustness and fault tolerance are key factors.
A Computational Method for Fuzzy Optimization
Authors: David Jamison
Venue:  (1997)

In this paper we develop a method to solve unconstrained and constrained fuzzy optimization problems for a class of fuzzy function. The class of fuzzy functions we consider for the optimization problems is the set of real-valued functions where one or more parameters or coefficients are fuzzy numbers. The focus of this research is to explore some theorectical results that lead to a practical computational method to solve fuzzy optimization problems. The ACM Portal is published by the Association for Computing Machinery. Copyright © 2010 ACM, Inc. Terms of Usage Privacy Policy Code of Ethics Contact Us Useful downloads: Adobe Acrobat QuickTime Windows Media Player Real Player
Design principles of policy languages for path vector protocols
Authors: Timothy G. Griffin, Aaron D. Jaggard, Vijay Ramachandran
Venue: Proceedings of the 2003 conference on Applications, technologies, architectures, and protocols for computer communications (2003)

BGP is unique among IP-routing protocols in that routing is determined using semantically rich routing policies. However, this expressiveness has come with hidden risks. The interaction of locally defined routing policies can lead to unexpected global routing anomalies, which can be very difficult to identify and correct in the decentralized and competitive Internet environment. These risks increase as the complexity of local policies increase, which is precisely the current trend. BGP policy languages have evolved in a rather organic fashion with little effort to avoid policy-interaction problems. We believe that researchers should start to consider how to emphdesign policy languages for path-vector protocols that avoid such risks and yet retain other desirable features. We take a few steps in this direction by identifying the important dimensions of this design space and characterizing some of the inherent design trade-offs. We attempt to do this in a general way that is not constrained by the details of BGP.
Performance of packet video with combined error recovery and concealment
Authors: G. Ramamurthy, D Raychaudhuri
Venue: Proceedings of the Fourteenth Annual Joint Conference of the IEEE Computer and Communication Societies (Vol. 2)-Volume - Volume 2 (1995)

In this paper we analyze the performance of a video transport across an ATM network that uses both retransmission and concealment to recover from errors due to cell loss resulting from congestion. We limit the number of retransmission attempts to one. If a frame is still in error after one retransmission attempt, the remaining errors are concealed. We obtain analytic expressions for the peak signal to noise ratio (PSNR) with combined retransmission and concealment. The analysis shows that significant improvement in the signal to noise ratio of the reconstructed picture can be achieved if retransmission and concealment are used together.
An Analysis of Instruction-Cached SIMD Computer Architecture
Authors: Todd E. Rockoff
Venue:  (2001)

In a single instruction-stream/multiple data-stream (SIMD) computer, calculations are performed by simple processing elements (PEs) that are not independently capable of program-control operations. In lock-step, the PEs execute one program that is sequenced by a single system controller. Large numbers of these simple PEs are obtained through replication of a PE chip containing many identical PEs. A state-of-the-art SIMD computer is regulated by a single system clock that is distributed throughout the computer. On each system clock cycle, the system controller broadcasts the next instruction to be executed by the PEs. The system clock interval allows time to distribute a PE instruction throughout the computer, an action that typically requires more time than the minimum interval of a clock regulating the PEs themselves within the PE chips. The disparity between the highest rate of PE operation and the rate of global instruction broadcast gives rise to a heretofore un-compensated clock-rate limitation. To overcome this limitation, instruction-cached SIMD computer architecture provides for a small instruction buffer to be placed within the replicated PE chip. This buffer stores repeated instruction sequences for subsequent retrieval at the relatively high rate attainable within the PE chip. The instruction buffer and its control mechanism comprise a SIMD instruction cache, or I-cache. Throughput measures computer performance, while total chip area is a primitive measure of a computer''s monetary cost that is most appropriate for high-PE-count multiprocessors. The ratio of throughput to area is a figure of merit expressing a multiprocessor''s ratio of performance to hardware cost. My thesis is that even the simplest I-cache variants increase throughput-to-area ratios significantly. I-cache increases the rate at which instructions are delivered to the PEs. However, I-cache takes up space in the PE chip that would otherwise have been used for PEs themselves. If the total chip area of the computer is fixed, then I-cache reduces the chip area used for PEs. For scalable data-parallel problems, reducing the number of PEs reduces the throughput. Therefore, the magnitude of the throughput-to-area ratio impact of I-cache depends on the balance between the competing factors of instruction execution-rate increase and displacement of PEs from the PE chip. In analyzing SIMD instruction cache, the dissertation considers the interacting characteristics of data-parallel program properties and SIMD computer electrical characteristics in I-cache design. Designs of two simple I-cache variants are presented and their chip area costs are estimated. For a diversity of data-parallel problems, these I-caches are evaluated over a range of underlying PE architecture and system characteristics. The evaluations are performed using register-transfer-level simulations of SIMD computations on a clock-phase by clock-phase basis. The simple I-cache variants occupy negligible chip area
Reasonning on Aspectual-Temporal Information in French within Conceptual Graphs
Authors: Tassadit Amghar, Delphine Battistelli, Thierry Charnois
Venue: Proceedings of the 14th IEEE International Conference on Tools with Artificial Intelligence (2002)

This paper presents a modeling of time, aspect and verbal meanings in natural language processing within Simple Conceptual Graphs (SCG) by way of Semantico-Cognitive Schemes (SCS) and the aspectual-temporal theory. Our system translates a semantico-cognitive representation in terms of SCGs. The SCS allows us to build a representation of a text taking into account fine subtleties of natural language as the information about time and aspect. TheConceptual Graphs formalism provides a powerful inferential mechanism which makes it possible to reason from texts. Our work bears on French texts. A text is represented by two different structures both represented within the SCG model. The first structure models the semantico-cognitive representation while the second one is the temporal diagram representing the temporal constraints between the situations described in the text. Linking these structuresentails an expansion of the original SCG model.
Refactoring test code
Authors: Arie Deursen, Leon M.F. Moonen, A. Bergh, Gerard Kok
Venue:  (2001)

Two key aspects of extreme programming (XP) are unit testing and merciless refactoring. Given the fact that the ideal test code / production code ratio approaches 1:1, it is not surprising that unit tests are being refactored. We found that refactoring test code is different from refactoring production code in two ways: (1) there is a distinct set of bad smells involved, and (2) improving test code involves additional test-specific refactorings. To share our experiences with other XP practitioners, we describe a set of bad smells that indicate trouble in test code, and a collection of test refactorings to remove these smells.
Comparative Performance of a Commodity Alpha Cluster Running Linux and Windows NT
Authors: David Lancaster, Kenji Takeda
Venue: Proceedings of the 1st IEEE Computer Society International Workshop on Cluster Computing (1999)

Using a cluster of commodity Alpha processors we compare two software platforms based on Linux and Windows NT and intended to support intensive scientific computations. Networking and compiler performance are separately analyzed and then results for NAS parallel benchmarks are given. We find that a compiler able to make good use of the cache is more important than low network latency in obtaining high performance. We argue that for all types of cluster, the choice of compiler is critical in selecting a cost effective platform for computationally intensive scientific applications.
Patterns and performance of distributed real-time and embedded publisher/subscriber architectures
Authors: Douglas C. Schmidt, Carlos O'Ryan
Venue: Journal of Systems and Software (2003)

This paper makes four contributions to the design and evaluation of publisher/subscriber architectures for distributed real-time and embedded (DRE) applications. First, it illustrates how a flexible publisher/subscriber architecture can be implemented using standard CORBA middleware. Second, it shows how to extend the standard CORBA publisher/subscriber architecture so it is suitable for DRE applications that require low latency and jitter, periodic rate-based event processing, and event filtering and correlation. Third, it explains how to address key performance-related design challenges faced when implementing a publisher/ subscriber architecture suitable for DRE applications. Finally, the paper presents benchmarks that empirically demonstrate the predictability, latency, and utilization of a widely used real-time CORBA publisher/subscriber architecture. Our results demonstrate that it is possible to strike an effective balance between architectural flexibility and real-time quality of service for important classes of DRE applications.
VTun
Authors: Ryan Breen
Venue: Linux Journal (2003)

Need to make a secure connection from home? Set up a simple virtual private network? The ACM Portal is published by the Association for Computing Machinery. Copyright © 2010 ACM, Inc. Terms of Usage Privacy Policy Code of Ethics Contact Us Useful downloads: Adobe Acrobat QuickTime Windows Media Player Real Player
Demand Routing and Slotting on Ring Networks
Authors: Tamra Carpenter, Steven Cosares, Iraj Saniee
Venue:  (1997)

We describe an important class of problems that arise in the economic design of "survivable" networks. Such networks are capable of accommodating all of the traffic between pairs of locations, even if some arbitrary link or node in the network is rendered unusable. Cycles play an important role in the design of survivable networks because they represent two-connected subnetworks of minimal size. To cost-effectively utilize cycles, we must determine the minimum capacity required for the links in the cycle, subject to constraints on how traffic must be routed and how capacity must be utilized. Depending upon the situation being modeled, different versions of the problem arise. The least restrictive versions are solvable in polynomial time, while the more restrictive (and more realistic) versions are NP-hard. This paper focuses on variants of the problem in which time-slot assignment constraints are enforced to model the operation of the equipment placed at the nodes of a SONET ring. We present several simple heuristic methods for addressing the problem, and we show that they are 2-approximation algorithms.
Fault-tolerant distributed match-making with weights
Authors: A. Nakajima
Venue: Proceedings of the 1996 International Conference on Parallel and Distributed Systems (1996)

Protocols to solve several distributed issues, such as name service, mutual exclusion, and creation of an atomic shared register, require two types of subsets with intersection property. Distributed match-making provides a method of creating the subsets, and the lower bound of the number of messages to solve the issues. This paper discusses the fault-tolerant and weighted case, in which a protocol is fault-tolerant regarding node failures, and in which weights of subsets are different. The paper first provides the lower bound of the number of messages required for a protocol in a general form. Then, it concentrates a symmetric case and shows the lower bound in a simpler form. The paper also provides a method of constructing the two types of subsets, which realize the lower bound. It first shows a method for a fully symmetric case, and extends it for other cases. The extended method is practical. It creates a cyclic communication structure, and is valid for any degree of fault-tolerance and weights.
Simultaneous Subthreshold and Gate-Oxide Tunneling Leakage Current Analysis in Nanometer CMOS Design
Authors: Dongwoo Lee, Wesley Kwong, David Blaauw, Dennis Sylvester
Venue: Proceedings of the 4th International Symposium on Quality Electronic Design (2003)

In this paper we develop a fast approach to analyze the total leakagepower of a large circuit block, considering both gate leakage,Igate, and subthreshold leakage, Isub. The interaction between Isuband Igate complicates analysis in arbitrary CMOS topologies. Wepropose simple and accurate heuristics to quickly estimate the state-dependenttotal leakage current considering the interaction betweenIsub and Igate. We apply this method to ISCAS benchmark circuits ina projected 100nm technology and demonstrate excellent accuracycompared to SPICE simulation with a 20,000X speedup on average.