ppxscal/embedding_network huggingface dataset:
Linear-translate constrained storage VQ for VSPIHT wavelet image compression
Authors: D. Mukherjee
Venue: Proceedings of the Acoustics, Speech, and Signal Processing, 2001. on IEEE International Conference - Volume 03 (2001)

A new constrained storage VQ (CSVQ) structure based on linear transforms and translates of a common root codebook is proposed. The new VQ structure, named LT-CSVQ (linear translate CSVQ) acts as a building block for multistage VQ implementations (LT-CS-MSVQ), and significantly reduces storage requirements from that required in tree-multistage VQ implementations. LT-CS-MSVQ is most appropriate for medium rate multistage VQ implementations, and is applied to the previously proposed vector enhancement of Said and Pearlman's (1996) set partitioning in hierarchical trees (SPIHT) image coder named VSPIHT.
Adjacent Vertex Distinguishing Edge-Colorings
Authors: P. N. Balister, E. Gyo&dblac;ri, J. Lehel, R. H. Schelp
Venue: SIAM Journal on Discrete Mathematics (2007)

An adjacent vertex distinguishing edge-coloring of a simple graph $G$ is a proper edge-coloring of $G$ such that no pair of adjacent vertices meets the same set of colors. The minimum number of colors $\chi^\prime_a(G)$ required to give $G$ an adjacent vertex distinguishing coloring is studied for graphs with no isolated edge. We prove $\chi^\prime_a(G)\le5$ for such graphs with maximum degree $\Delta(G)=3$ and prove $\chi^\prime_a(G)\le\Delta(G)+2$ for bipartite graphs. These bounds are tight. For $k$-chromatic graphs $G$ without isolated edges we prove a weaker result of the form $\chi^\prime_a(G)=\Delta(G)+O(\log k)$.
PSPICE as a simulation tool in teaching electrodynamics
Authors: W. M. Portnoy
Venue: Proceedings of the 26th Annual Frontiers in Education - Volume 01 (1996)

An experimental course in electromagnetic theory has been developed in which the student version of PSPICE can be used to illustrate a large class of theoretical principles. The course material is based an the argument that many interesting problem in electrodynamics can be addressed using TEM waves normally incident on a dielectric or reflecting interface. The relationship between a normally incident propagating TEM wave and a voltage (or current) wave propagating down a transmission line are shown to be mathematically equivalent, as are the constitutive parameters of a material and the inductance and capacitance per unit length in a transmission line. Once these relationships have been established, the transmission line models available in PSPICE can be used to solve interesting physical problems. The ACM Portal is published by the Association for Computing Machinery. Copyright © 2010 ACM, Inc. Terms of Usage Privacy Policy Code of Ethics Contact Us Useful downloads: Adobe Acrobat QuickTime Windows Media Player Real Player
An Architectural Strategy for Self-Adapting Systems
Authors: Danny Weyns, Tom Holvoet
Venue: Proceedings of the 29th International Conference on Software Engineering Workshops (2007)

Self-adaptation is the ability of a software system to adapt to dynamic and changing operating conditions autonomously. In this paper, we present an architectural strategy for self-adapting systems. An architectural strategy embodies architectural knowledge about a particular solution approach. The architectural strategy for self-adapting systems structures the software into a number of interacting autonomous entities (agents) that are situated in an environment. It integrates a set of architectural patterns that have proved to be valuable in the design of various selfadapting applications. The self-adapting properties of the approach are based on the agents' abilities to adapt their behavior to dynamic and changing circumstances. The architectural strategy provides an asset base architects can draw from when developing new self-adapting applications that share its common base.
An Energy-Efficient Mechanism using CLMAC Protocol for Wireless Sensor Networks
Authors: Jaejoon Cho, Sungho Kim, Heungwoo Nam, Sunshin An
Venue: Proceedings of the Third International Conference on Networking and Services (2007)

Energy efficiency is a key issue because most wireless sensor networks use battery-oriented computing and sensing devices. A network of these devices will collaborate for a common application such as environment monitoring. Thus, energy-efficient MAC protocols have focused on minimizing idle listening time at sensor nodes. Recently, energy-efficient protocols such as S-MAC, B-MAC and EA-ALPL proposed to reduce energy consumption. Here, we propose a cross-layer mechanism called Cross Layer Medium Access Control (CLMAC) protocol that designed for wireless sensor networks. To meet energy-efficient routing, the CLMAC includes routing distance in the preamble field of the B-MAC. Because the CLMAC unified network layer and link layer uses routing distance without big routing table, it enables nodes to reduce control traffic routing overhead. Also, the CLMAC makes it possible to extend the lifetime of the wireless sensor networks that contain a number of nodes. The analytical results show that CLMAC protocol reduces routing overhead of the sensor nodes in wireless sensor networks.
Time-frequency strip filters
Authors: B. A. Weisburn
Venue: Proceedings of the Acoustics, Speech, and Signal Processing, 1996. on Conference Proceedings., 1996 IEEE International Conference - Volume 03 (1996)

A strip filter, which is a time-varying generalization of linear time-invariant filters, selects signals having energy in a strip-shaped region in the time-frequency plane. Its eigenfunctions are a set of chirps oriented parallel to the strip in time-frequency. Properties of the strip filter are reviewed and related to earlier work on time-varying filters in the time-frequency plane. It is a special case of a Weyl filter, where the time-frequency symbol is restricted to a strip shape. When the time-frequency symbol is an indicator function, the resulting filter is a projection operator. A derivation of a fast implementation of the strip filter results from its group-theoretic origins.
Scale and Scope Externalities in Growth of IT Industries in India: An Agglomeration Perspective
Authors: Robert J. Kauffman, Ajay Kumar
Venue: Proceedings of the 40th Annual Hawaii International Conference on System Sciences (2007)

Externalities occur among agglomerated firms. Scale externalities occur between firms in an industry with similar activities. Scope externalities occur when heterogeneous activities are placed in proximity. Combined scale-and-scope externalities exist when the scale of one industry is beneficial to the growth of another collocated industry. We use the agglomeration perspective to explain the growth of IT industries in India. We study growth patterns of four IT industries: computer and peripheral equipment manufacturing, semiconductor and other electronic components manufacturing, software and IT-enabled services. Our analysis suggests the existence of scale, scope and combined scale-and-scope externalities in IT industry growth. We also find that the growth of IT industries has had a significant positive effect on national development.
Phase-based image motion estimation and registration
Authors: M. Hemmendorff
Venue: Proceedings of the Acoustics, Speech, and Signal Processing, 1999. on 1999 IEEE International Conference - Volume 06 (1999)

Conventional gradient methods (optical flow), for motion estimation assume intensity conservation between frames. This assumption is often violated in real applications. The remedy is a novel method that computes constraints on the local motion. These constraint are given on the same form as in conventional methods. Thus, it can directly substitute the gradient method in most applications. Experiments indicate a superior accuracy, even on synthetic images where the intensity conservation assumption is valid. The conventional gradient methods seem obsolete.
On fuzzy isomorphism theorems of hypermodules
Authors: Jianming Zhan, Bijan Davvaz, K. P. Shum
Venue: Soft Computing - A Fusion of Foundations, Methodologies and Applications (2007)

We introduce the concept of normal fuzzy subhypermodules of hypermodules and establish three isomorphism theorems of hypermodules by using normal fuzzy subhypermodules.
From the Editor in Chief: Pet Peeves
Authors: Fred Douglis
Venue: IEEE Internet Computing (2007)

From spam to bad security, Internet pet peeves are common. EIC Fred Douglis shares some of his, and invites readers to share some of their own - as well as any solutions they've come up with.
Letters: A novel hysteretic chaotic neural network and its applications
Authors: Xiangdong Liu, Chunbo Xiu
Venue: Neurocomputing (2007)

A model of single neuron with chaotic and hysteretic characteristics is proposed. Neural network coupled by such neurons exhibits complex dynamic behaviors. The network is also studied from the viewpoint of optimization. Chaos and hysteresis phenomena make the network have the characteristic of escaping from a local minimum of the energy function, so it can find a global minimum more easily as compared with others. The experimental results show that it has a higher average success rate of obtaining a global optimization solution.
Lower bounds for randomized read/write stream algorithms
Authors: Paul Beame, T. S. Jayram, Atri Rudra
Venue: Proceedings of the thirty-ninth annual ACM symposium on Theory of computing (2007)

Motivated by the capabilities of modern storage architectures, we consider the following generalization of the data stream model where the algorithm has sequential access to multiple streams. Unlike the data stream model, where the stream is read only, in this new model (introduced in [8,9]) the algorithms can also write onto streams. There is no limit on the size of the streams but the number of passes made on the streams is restricted. On the other hand, the amount of internal memory used by the algorithm is scarce, similar to data stream model. We resolve the main open problem in [7] of proving lower bounds in this model for algorithms that are allowed to have 2-sided error. Previously, such lower bounds were shown only for deterministic and 1-sided error randomized algorithms [9,7]. We consider the classical set disjointness problemthat has proved to be invaluable for deriving lower bounds for many other problems involving data streams and other randomized models of computation. For this problem, we show a near-linear lower bound on the size of the internal memory used by a randomized algorithm with 2-sided error that is allowed to have o(log N/log log N) passes over the streams. This bound is almost optimal sincethere is a simple algorithm that can solve this problem using logarithmic memory if the number of passes over the streams. Applications include near-linear lower bounds onthe internal memory for well-known problems in the literature:(1) approximately counting the number of distinct elements in the input (F0);(2) approximating the frequency of the mod of an input sequence(F*∞);(3) computing the join of two relations; and (4) deciding if some node of an XML document matches an XQuery (or XPath) query. Our techniques involve a novel direct-sum type of argument that yields lower bounds for many other problems. Our results asymptotically improve previously known bounds for any problem even in deterministic and 1-sided error models of computation.
A programmable processor with multiple functional units and banked registers for general purpose numerical processing
Authors: T. Morifuji
Venue: Proceedings of the Acoustics, Speech, and Signal Processing, 1999. on 1999 IEEE International Conference - Volume 04 (1999)

We present an architecture of a general purpose numerical processor (GPNP). The processor with this architecture is capable of running a wide variety of numerical processing and digital signal processing with its programmability. Flexibility and high-performance are achieved by multiple functional units and their data transfer parallelism. The prototype of a GPNP with five functional units can operate with a 33-MHz clock frequency by simulation and its size corresponds with 230-kTr and 34.5-kbytes on-chip memory.
Software design for installability
Authors: Steve Simmons
Venue: Proceedings of the USENIX Applications Development Symposium Proceedings on USENIX Applications Development Symposium Proceedings (1994)

In classic software design, little or no consideration is given to the issue of installing the resulting package on the customer machine(s). This is complicated by the rich variety of administrative policies and styles used in UNIX installations. This paper will not attempt to prescribe a specific method for software installation. Instead, it will focus on (a) issues which make a package installable into highly customized sites such that the package can be installed with minimal disruption to both the site and the package and (b) the reprogramming of system configurations in a style designed to minimize the impact of that reprogramming.
Interactive presentation: System-level process variation driven throughput analysis for single and multiple voltage-frequency island designs
Authors: Siddharth Garg, Diana Marculescu
Venue: Proceedings of the conference on Design, automation and test in Europe (2007)

Manufacturing process variations are the primary cause of timing yield loss in aggressively scaled technologies. In this paper, we analyze the impact of process variations on the throughput (rate) characteristics of embedded systems comprised of multiple voltage-frequency islands (VFIs) represented as component graphs. We provide an efficient, yet accurate method to compute the throughput of an application in a probabilistic scenario and show that systems implemented with multiple VFIs are more likely to meet throughput constraints than their fully synchronous counterparts. The proposed framework allows designers to investigate the impact of architectural decisions such as the granularity of VFI partitioning on their designs, while determining the likelihood of a system meeting specified throughput constraints. An implementation of the proposed framework is accurate within 1.2% of Monte Carlo simulation while yielding speed-ups ranging from 78X-260X, for a set of synthetic benchmarks. Results on a real benchmark (MPEG-2 encoder) show that a nine clock domain implementation gives 100% yield for a throughput constraint for which a fully synchronous design only yields 25%. For the same throughput constraint, a three clock domain architecture yields 78%.
PATRAM: A Unified Word Processing System for Handwritten Characters in Indian Languages
Authors: M. Kasirajan, V. S. Chakravarthy
Venue: Proceedings of the International Conference on Computing: Theory and Applications (2007)

In this paper, we describe the design and implementation of a unified word processing system to handle handwritten characters for Indian languages.It uses XML [1] based document format to store the strokes written by the user.It provides filters to export the native document into other standards like InkML (Ink Markup Language) [2] and LDF (Lekhak Data Format). It integrates shape feature based recognition engine to recognise the whole document and spell checker to correct the wrongly recognised words. It includes the support to send the document as an attachment with E-mail without the need for recognition.
FiST: a language for stackable file systems
Authors: Erez Zadok, Jason Nieh
Venue: Proceedings of the annual conference on USENIX Annual Technical Conference (2000)

Traditional file system development is difficult. Stackable file systems promise to ease the development of file systems by offering a mechanism for incremental development. Unfortunately, existing methods often require writing complex low-level kernel code that is specific to a single operating system platform and also difficult to port. We propose a new language, FiST, to describe stackable file systems. FiST uses operations common to file system interfaces. From a single description, FiST's compiler produces file system modules for multiple platforms. The generated code handles many kernel details, freeing developers to concentrate on the main issues of their file systems. This paper describes the design, implementation, and evaluation of FiST. We extended file system functionality in a portable way without changing existing kernels. We built several file systems using FiST on Solaris, FreeBSD, and Linux. Our experiences with these examples shows the following benefits of FiST: average code size over other stackable file systems is reduced ten × average development time is reduced seven × performance overhead of stacking is 1-2%.
Flexible Architectures and Agents for Adaptive Autonomic Systems
Authors: Sebastien Leriche, Jean-Paul Arcangeli
Venue: Proceedings of the Fourth IEEE International Workshop on Engineering of Autonomic and Autonomous Systems (2007)

In order to simplify the development of autonomic and autonomous systems, we propose a model of adaptive agent built from fine-grained reusable components which implement non-functional mechanisms such as communication, mobility or adaptation skills. Each agent can dynamically and autonomously change its components to fit its runtime context, improving safety and performance in particular for open, pervasive or large-scale distributed applications. We describe a tool called Agent' for adaptive agent modeling and we present the design of an embedded agent.
Kalman-Mesarovic nonstationary realization in terms of Rayleigh-Ritz operator
Authors: A. V. Daneev, V. A. Rusanov, D. Yu. Sharpinskii
Venue: Cybernetics and Systems Analysis (2007)

The paper outlines the methodology underlying the Kalman-Mesarovic realization for dynamic systems with equations of state in the class of linear nonstationary ordinary differential equations. In this sense, the key approaches to solving problems of realization theory in terms of the Rayleigh-Ritz operator are defined.
Asteroid Exploration with Autonomic Systems A Biologically-Inspired Approach based on the Immunological System
Authors: Omar Florez-Choque, Michael G. Hinchey
Venue: Proceedings of the Fourth IEEE International Workshop on Engineering of Autonomic and Autonomous Systems (2007)

We outline a potential approach to the development of future autonomic NASA Space Exploration Missions. The approach is quite different from other efforts to date, and is inspired by the Human Immunological System and exploits agent-based technologies to support autonomic features such as: self-managing, self-configuring, self-healing, self-optimizing, self-protecting, and finally two novel features of future NASA swarm-based missions: self-predicting and self-learning, which may help in extending levels of autonomy in future missions. The approach offers several detection mechanisms for recognizing Self and non-Self patterns. This sense of Self of the Immunological System is related to the ability to learn to recognize new kinds of threats. The hierarchical architecture based on agents offers a high flexibility for repairing, maintaining, configuring, and optimizing functions of the spacecraft in real time.
A low-power programmable DSP core architecture for 3G mobile terminals
Authors: T. Kumura
Venue: Proceedings of the Acoustics, Speech, and Signal Processing, 200. on IEEE International Conference - Volume 02 (2001)

We have developed a new-generation, general-purpose digital signal processor (DSP) core with low power dissipation for use in third-generation (3G) mobile terminals. The DSP core employs a 4-way VLIW (very long instruction word) approach, as well as a dual-multiply-accumulate (dual-MAC) architecture with good orthogonality. It is able to perform both video and speech codec for 3G wireless communications at 384 k bit/sec with a power consumption of approximately 50 mW. This paper presents an overview of both the DSP core architecture and a DSP instruction set, and it also gives some application benchmarks.
Stochastic and Robust Approaches to Optimization Problems under Uncertainty
Authors: Masao Fukushima
Venue: Proceedings of the Second International Conference on Informatics Research for Development of Knowledge Society Infrastructure (2007)

In the last decade, optimization models under uncertainty have drawn much attention and efficient algorithms have been developed for solving those problems. This article presents the author's recent attempts conducted in collaboration with a number of co-authors to deal with uncertainty in various optimization problems including complementarity problems, mathematical programs with equilibrium constraints, as well as applications in data mining, mathematical finance, and game theory.
String matching architectures for network security on reconfigurable computers
Authors: Viktor K. Prasanna
Venue:  (2006)

Network-connected devices often have vulnerabilities susceptible to exploitation. In order to protect individual systems and the entire network, network operators must ensure that attacks do not traverse their network links. One method for understanding the attacks on a network is an Intrusion Detection System (IDS). Intrusion Detection Systems use sophisticated rules utilizing string matching to detect potential malicious packets. Due to the high string matching rates required, this filtering requires significant computational resources. Fortunately, the computational requirements can be met by Field Programmable Gate Array (FPGA) devices. This thesis describes two efficient hardware string matching architectures developed to provide high levels of time and area performance. The Knuth-Morris-Pratt (KMP) algorithm is an efficient string matching technique that requires a minimum of comparisons through the use of a pre-computed transition table. This thesis presents a modification of the basic algorithm that allows its use in an efficient hardware architecture, allowing the system to accept at least one character in each cycle. The memory-based units allow runtime pattern reconfiguration. A major contribution is a proof of the worst-case buffer size requirement such that throughput is maintained with no chance of a false negative. The buffered KMP algorithm reduces the overall work done, and thereby the area required is lower as well. In another approach, a set of tools was developed for automatic synthesis of highly efficient intrusion detection systems. This approach uses a high-level, graph-based partitioning methodology to produce "hardwired" architectures compiled to the FPGA device. The automated design techniques and architecture allows faster clock rates and extensive reuse of hardware components for dramatic increases in area-time performance. Through design-time compilation, the methodology yields designs that take advantage of pattern redundancy. To extend the capabilities of the hardwired architectures, extensions were developed that provide support for rules requiring string literal extensions including wild-card separated patterns with bounding restrictions. By combining the two techniques into a hybrid system, improvements in terms of area, memory efficiency, and frequency performance are achieved, while providing on-the-fly reprogramming.
Parallel Implementations of a Scalable Consistent Labeling Technique on Distributed Memory Multi-Processor Systems
Authors: Wei-Ming Lin, Zhenhong Lu
Venue: Proceedings of the 1993 International Conference on Parallel Processing - Volume 03 (1993)

An efficient implementation of a consistent labeling technique can lead to a fast solution in solving all kinds of tree search problems by reducing the search space from a potentially exponential size to a much smaller size. In this paper a scalable parallel algorithm is presented in achieving labeling consistency. This algorithm is optimal in execution time as well as in processor-time product. It is suitable for implementation on most distributed memory multiprocessor system.