ppxscal/embedding_network huggingface dataset:
Value-at-Risk in IT Services Contracts
Authors: Robert J. Kauffman, Ryan Sougstad
Venue: Proceedings of the 40th Annual Hawaii International Conference on System Sciences (2007)

As information systems (IS) and technology solutions become increasingly service-driven, managers are faced with the task of choosing parameters such as servicelevels, pricing, and contract duration. Information technology (IT) services vendors manage portfolios of contracts in which parameters, decided at inception, are often subject to future risks. The contract profit maximization decision may adversely affect the risk position of the firm's portfolio of services contracts. We propose a model to inform vendors on setting optimal parameters for IS contracts subject to acceptable levels of risk. The analytic model presented draws from IS economics research and the principles of value-atrisk (VaR) from financial economics. We provide examples which illustrate the trade-offs of profit maximizing contractual decisions to portfolio profit-at-risk (PaR). The contribution of this research is the application of VaR analysis to IS contractual decisions and the conceptualization of an economic model of IS service contracts which embeds value-atrisk constraints.
ABET Engineering Criteria 2000
Authors: J. Yeargan, D. Aldridge, I. Jacobson, J. White
Venue: Proceedings of the Frontiers in Education Conference, on 1995. Proceedings., 1995 - Volume 02 (1995)

The Synthesis Coalition and NEEDS are at the forefront of courseware creation, delivery and evaluation. NEEDS is the architecture developed by the Synthesis Coalition to enable new pedagogical models based on Internet-mediated environments for learning. The NEEDS database provides an access mechanism for students and faculty to a diverse range of engineering educational materials. The database consists of collections of modular digital courseware and courseware elements. The user is able to access and use courseware developed nationwide. In addition, the existing courseware and courseware elements can be adapted to local use in whole or by distilling several modules and joining them together to create a new customized module. The Synthesis Coalition has the directive of making the NEEDS database available to other NSF undergraduate engineering education coalitions and other universities. The requirements for and the feasibility of making courseware available on the NEEDS database are discussed. Critical issues facing courseware developers are identified. The NEEDS Editorial Board is being established to develop a comprehensive review procedure that will result in three tiers of courseware on the NEEDS database: non-reviewed, endorsed and premier courseware. The process of reviewing the courseware on NEEDS will not only benefit the users of the NEEDS database, but it will also benefit authors by recognizing the scholarly and creative efforts that they have expended in developing effective, high-quality courseware. Both the Editorial Board and the review procedures are discussed.
How To Split Antichains In Infinite Posets*
Authors: P&#x00e9;ter L. Erd&#x0151;s, Lajos Soukup
Venue: Combinatorica (2007)

A maximal antichain A of poset P splits if and only if there is a set B &#x2282; A such that for each p &#x2208; P either b &#x2264; p for some b &#x2208; B or p &#x2264; c for some c &#x2208; A\B. The poset P is cut-free if and only if there are no x < y < z in P such that [x,z]P = [x,y]P &#x222a; [y,z]P . By [1] every maximal antichain in a finite cut-free poset splits. Although this statement for infinite posets fails (see [2])) we prove here that if a maximal antichain in a cut-free poset &#x201c;resembles&#x201d; to a finite set then it splits. We also show that a version of this theorem is just equivalent to Axiom of Choice. We also investigate possible strengthening of the statements that &#x201c;A does not split&#x201d; and we could find a maximal strengthening.
Development of a school wide assessment plan-questions answered and questions raised
Authors: C. F. Yokomoto
Venue: Proceedings of the 28th Annual Frontiers in Education - Volume 01 (1998)

In this paper, the authors describe the process that has transformed the attitudes of their faculty toward outcomes assessment from one of resistance to one of cooperation and action, an important precursor to buy in. They describe the questions that they have had to answer, the arguments that faculty used to defend their initial resistance, the transformation process and the organization structure of the school-wide committee that made the transformation possible. In addition, they discuss some of the questions that they have yet to answer, and give suggestions of ways that deans and chairpersons of school-wide committees can influence faculty buy in.
Implementing security and mobility functions in kernel drivers
Authors: Yoshiyuki Tsuda, Masahiro Ishiyama, Atsushi Fukumoto, Atsushi Inoue, Ken-ichi Yokoyama
Venue: Proceedings of the USENIX Windows NT Workshop on The USENIX Windows NT Workshop 1997 (1997)

We are developing a secure, mobile network system, named "Network CryptoGate (NCG)", which provides a secure Virtual Private Network (VPN) environment for mobile users seamlessly, even if they move to an insecure network. NCG is designed upon IETF standards, that is IP security (IPSEC) and Mobile IP (MobileIP), in order to make the whole system interoperable with other implementations. Currently, we have developed an NCG client software on Windows NT. At the poster/demonstration session, we will demonstrate how an NCG client works.
Local Action and Abstract Separation Logic
Authors: Cristiano Calcagno, Peter W. O'Hearn, Hongseok Yang
Venue: Proceedings of the 22nd Annual IEEE Symposium on Logic in Computer Science (2007)

Separation logic is an extension of Hoare's logic which supports a local way of reasoning about programs that mutate memory. We present a study of the semantic structures lying behind the logic. The core idea is of a local action, a state transformer that mutates the state in a local way. We formulate local actions for a class of models called separation algebras, abstracting from the RAM and other specific concrete models used in work on separation logic. Local actions provide a semantics for a generalized form of (sequential) separation logic. We also show that our conditions on local actions allow a general soundness proof for a separation logic for concurrency, interpreted over arbitrary separation algebras.
Gradient Coils Temperature Controller in a Gradient System for MR Tomography
Authors: Karel Bartusek, Zdenek Dokoupil, Eva Gescheidtova, Zdenek Smekal
Venue: Proceedings of the Second International Conference on Systems (2007)

A simple gradient coils temperature controller for a gradient magnetic field system has been developed. In the application of modern fast magnetic resonance experiments it can maintain the temperature of gradient coils at a value of 21.2ºC with a precision of 0.5ºC and protect the gradient system against overloading by excessive short-circuit power. When the temperature and the maximum power are exceeded, it will disconnect all gradients and, simultaneously, signal this state to the operator. A gradient system complemented like this has been experimentally verified on a home-built 200 MHz Magnetic Resonance (MR) Tomography system with a 120 mm bore (with room temperature) in the Institute of Scientific Instruments, Academy of Sciences of the Czech Republic.
Population variation in genetic programming
Authors: Peyman Kouchakpour, Anthony Zaknich, Thomas Bräunl
Venue: Information Sciences: an International Journal (2007)

A new population variation approach is proposed, whereby the size of the population is systematically varied during the execution of the genetic programming process with the aim of reducing the computational effort compared with standard genetic programming (SGP). Various schemes for altering population size under this proposal are investigated using a comprehensive range of standard problems to determine whether the nature of the ''population variation'', i.e. the way the population is varied during the search, has any significant impact on GP performance. The initial population size is varied in relation to the initial population size of the SGP such that the worst case computational effort is never greater than that of the SGP. It is subsequently shown that the proposed population variation schemes do have the capacity to provide solutions at a lower computational cost compared with the SGP.
2007 Special Issue: Optimization and applications of echo state networks with leaky- integrator neurons
Authors: Herbert Jaeger, Mantas Lukoševičius, Dan Popovici, Udo Siewert
Venue: Neural Networks (2007)

Standard echo state networks (ESNs) are built from simple additive units with a sigmoid activation function. Here we investigate ESNs whose reservoir units are leaky integrator units. Units of this type have individual state dynamics, which can be exploited in various ways to accommodate the network to the temporal characteristics of a learning task. We present stability conditions, introduce and investigate a stochastic gradient descent method for the optimization of the global learning parameters (input and output feedback scalings, leaking rate, spectral radius) and demonstrate the usefulness of leaky-integrator ESNs for (i) learning very slow dynamic systems and replaying the learnt system at different speeds, (ii) classifying relatively slow and noisy time series (the Japanese Vowel dataset - here we obtain a zero test error rate), and (iii) recognizing strongly time-warped dynamic patterns.
Operating system support for multi-user, remote, graphical interaction
Authors: Alexander Ya-Li Wong, Margo Seltzer
Venue: Proceedings of the annual conference on USENIX Annual Technical Conference (2000)

The emergence of thin client computing and multi-user, remote, graphical interaction revives a range of operating system research issues long dormant, and introduces new directions as well. This paper investigates the effect of operating system design and implementation on the performance of thin client service and interactive applications. We contend that the key performance metric for this type of system and its applications is user-perceived latency and we give a structured approach for investigating operating system design with this criterion in mind. In particular, we apply our approach to a quantitative comparison and analysis of Windows NT, Terminal Server Edition (TSE), and Linux with the X Windows System, two popular implementations of thin client service. We find that the processor and memory scheduling algorithms in both operating systems are not tuned for thin client service. Under heavy CPU and memory load, we observed user-perceived latencies up to 100 times beyond the threshold of human perception. Even in the idle state, these systems induce unnecessary latency. TSE performs particularly poorly despite scheduler modifications to improve interactive responsiveness. We also show that TSE's network protocol outperforms X by up to six times, and also makes use of a bitmap cache which is essential for handling dynamic elements of modern user interfaces and can reduce network load in these cases by up to 2000%.
DSPS education: an industry leader's experiences and expectations
Authors: C. R. Hewes
Venue: Proceedings of the Acoustics, Speech, and Signal Processing, 1999. on 1999 IEEE International Conference - Volume 04 (1999)

Texas Instruments is the industry leader in providing digital signal processing solutions to a variety of system applications including wireless communications, modems, hard disk drives, and many others. In this paper, the key roles of university research and education are described. The relationship of TI to the university community is reviewed. TI's expectations from university programs are also outlined.
QCA Circuits for Robust Coplanar Crossing
Authors: Sanjukta Bhanja, Marco Ottavi, Fabrizio Lombardi, Salvatore Pontarelli
Venue: Journal of Electronic Testing: Theory and Applications (2007)

In this paper, different circuits of Quantum-dot Cellular Automata (QCA) are proposed for the so-called coplanar crossing. Coplanar crossing is one of the most interesting features of QCA because it allows for mono-layered interconnected circuits, whereas CMOS technology needs different levels of metalization. However, the characteristics of the coplanar crossing make it prone to malfunction due to thermal noise or defects. The proposed circuits exploit the majority voting properties of QCA to allow a robust crossing of wires on the Cartesian plane. This is accomplished using enlarged lines and voting. A Bayesian Network (BN) based simulator is utilized for evaluation; results are provided to assess robustness in the presence of cell defects and thermal effects. The BN simulator provides fast and reliable computation of the signal polarization versus normalized temperature. Simulation of the wire crossing circuits at different operating temperatures is provided with respect to defects and a quantitative metric for performance under temperature variations is proposed and assessed.
A field programmable gate array architecture for two-dimensional partial reconfiguration
Authors: Jack Jean
Venue:  (2006)

Reconfigurable machines can accelerate many applications by adapting to their needs through hardware reconfiguration. Partial reconfiguration allows the reconfiguration of a portion of a chip while the rest of the chip is busy working on tasks. Operating system models have been proposed for partially reconfigurable machines to handle the scheduling and placement of tasks. They are called OS4RC in this dissertation. The main goal of this research is to address some problems that come from the gap between OS4RC and existing chip architectures and the gap between OS4RC models and practical applications. Some existing OS4RC models are based on an impractical assumption that there is no data exchange channel between IP (Intellectual Property) circuits residing on a Field Programmable Gate Array (FPGA) chip and between an IP circuit and FPGA I/O pins. For models that do not have such an assumption, their inter-IP communication channels have severe drawbacks. Those channels do not work well with 2-D partial reconfiguration. They are not suitable for intensive data stream processing. And frequently they are very complicated to design and very expensive. To address these problems, a new chip architecture that can better support inter-IP and IP-I/O communication is proposed and a corresponding OS4RC kernel is then specified. The proposed FPGA architecture is based on an array of clusters of configurable logic blocks, with each cluster serving as a partial reconfiguration unit, and a mesh of segmented buses that provides inter-IP and IP-I/O communication channels. The proposed OS4RC kernel takes care of the scheduling, placement, and routing of circuits under the constraints of the proposed architecture. Features of the new architecture in turns reduce the kernel execution times and enable the runtime scheduling, placement and routing. The area cost and the configuration memory size of the new chip architecture are calculated and analyzed. And the efficiency of the OS4RC kernel is evaluated via simulation using three different task models.
The convex dimension of a graph
Authors: Nir Halman, Shmuel Onn, Uriel G. Rothblum
Venue: Discrete Applied Mathematics (2007)

The convex dimension of a graph G=(V,E) is the smallest dimension d for which G admits an injective map f:V@?R^d of its vertices into d-space, such that the barycenters of the images of the edges of G are in convex position. The strong convex dimension of G is the smallest d for which G admits a map as above such that the images of the vertices of G are also in convex position. In this paper we study the convex and strong convex dimensions of graphs.
Algorithm Design and Side Channel Vulnerability on the Example of DPA Attack
Authors: Jens Rudinger, Adolf Finger
Venue: Proceedings of the Sixth International Conference on Networking (2007)

This paper deals with the question of the influence of the design of cryptographic algorithm on their side channel vulnerability. On the example of the DPA attack by Kocher the complexity of the attack and their dependency on algorithmic parameters is analyzed. It is shown that the careful selection or design of algorithms can increase the security of implementations of algorithms in addition to and independent from conventional DPA attack countermeasures.
Ameliorating mental mistakes in tradeoff studies
Authors: Eric D. Smith, Young Jun Son, Massimo Piattelli-Palmarini, A. Terry Bahill
Venue: Systems Engineering (2007)

Tradeoff studies are broadly recognized and mandated as the method for simultaneously considering multiple alternatives with many criteria, and as such are recommended in the Capability Maturity Model Integration (CMMI) Decision Analysis and Resolution (DAR) process. Tradeoff studies, which involve human numerical judgment, calibration, and data updating, are often approached with under confidence by analysts and are often distrusted by decision makers. The decision-making fields of Judgment and Decision Making, Cognitive Science and Experimental Economics have built up a large body of research on human biases and errors in considering numerical and criteria-based choices. Relationships between experiments in these fields and the elements of tradeoff studies show that tradeoff studies are susceptible to human mental mistakes: This paper indicates ways to eliminate the presence, or ameliorate the effects of mental mistakes on tradeoff studies. &copy; 2007 Wiley Periodicals, Inc. Syst Eng 10: 222&ndash;240, 2007 This work was supported by the Air Force Office of Scientific Research under AFOSR&#x002F;MURI F49620-03-1-0377.
Pathway to functional studies: pipeline linking phylogenetic footprinting and transcription-factor binding analysis
Authors: Nagesh Chakka, Jill E. Gready
Venue: Proceedings of the 2006 workshop on Intelligent systems for bioinformatics - Volume 73 (2006)

Identification of transcription-factor binding sites is a critical first step in studying transcriptional regulation of genes. The comparative genomics method of phylogenetic footprinting is based on identifying sequence elements that are conserved across multiple genomes, and, thus, likely to be functional. We have developed a systematic high throughput screening pipeline to first search for conserved motifs using two different phylogenetic footprinting methods (motif-discovery and alignment-based), and then rapid evaluate the motifs as potential transcription-factor binding sites. The results are displayed in an interactive graphical user interface, FactorScan, which integrates three separate complementary databases (conserved-sequence motifs, transcription-factor binding site motifs, TRANSFAC). We applied this pipeline for transcription-factor binding site analysis to the orthologous gene regions of prion-protein family genes from vertebrate lineages, taking account of the gene annotations.
Scalable reconfigurable channel decoder architecture for future wireless handsets
Authors: Gummidipudi Krishnaiah, Nur Engin, Sergei Sawitzki
Venue: Proceedings of the conference on Design, automation and test in Europe (2007)

The current trend in the consumer devices and communication service provider market is the integration of different communication standards within a single device (e.g. GSM phone with Bluetooth, WLAN and infrared interface) requiring tight integration of mobile broadcast, networking and cellular technologies within one product. Channel decoder is traditionally one of the most computationally intensive building block within digital receivers. The aim of this paper is to investigate the feasibility of a programmable channel decoder that can be dynamically reconfigured for decoding turbo and convolutionally encoded streams from various wireless standards. The architecture options are presented and the area costs and flexibility compared between the options. The resulting decoder architecture supports hardware resource sharing and reconfiguration between different standards and decoders and is more efficient in terms of silicon area than independent implementation of every decoder on the same IC.
MOTE-VIEW: a sensor network monitoring and management tool
Authors: M. Turon
Venue: Proceedings of the 2nd IEEE workshop on Embedded Networked Sensors (2005)

This paper presents a scalable software framework for managing, monitoring, and visualizing sensor network deployments called MOTE-VIEW. In this paper, we conduct a comprehensive review of typical problems encountered when deploying and administering wireless sensor networks. Then we address these issues by outlining a monitoring tool architecture using an extensible set of user interface components specifically targeted towards improving manageability and easing deployment of wireless sensor networks. We describe specific visualization modules for intuitively characterizing data represented in instantaneous, time span, and spatial form. Next, we analyze and optimize the database requirements of the proposed visualization modules for performance. Finally, we describe a mechanism for analyzing the health of the individual nodes and the network as a whole.
A de-rotation approach to the blind separation of synchronous co-channel BPSK signals
Authors: M. Meng
Venue: Proceedings of the Acoustics, Speech, and Signal Processing, 1999. on 1999 IEEE International Conference - Volume 05 (1999)

We propose a simple algorithm for the blind separation of m synchronous co-channel BPSK signals by an array of n receiving antennas. We exploit the geometric implications of the finite alphabet property of BPSK signals. After a standard channel whitening step, the noiseless received data vectors describe an m-cube, which is a rotated version of the hypercube defined by the 2/sup m/ distinct vectors of /spl plusmn/1s corresponding to all the possible combinations of the states of the sources. We provide a simple procedure to estimate the vertices of this rotated hypercube in the noisy case and then show how the rotation matrix can be determined up to a sign and permutation of its columns. De-rotation of the channel-whitened data results in source separation. Simulations show the good performance of our proposed technique.
Online diagnosis of hard faults in microprocessors
Authors: Fred A. Bower, Daniel J. Sorin, Sule Ozev
Venue: ACM Transactions on Architecture and Code Optimization (TACO) (2007)

We develop a microprocessor design that tolerates hard faults, including fabrication defects and in-field faults, by leveraging existing microprocessor redundancy. To do this, we must: detect and correct errors, diagnose hard faults at the field deconfigurable unit (FDU) granularity, and deconfigure FDUs with hard faults. In our reliable microprocessor design, we use DIVA dynamic verification to detect and correct errors. Our new scheme for diagnosing hard faults tracks instructions' core structure occupancy from decode until commit. If a DIVA checker detects an error in an instruction, it increments a small saturating error counter for every FDU used by that instruction, including that DIVA checker. A hard fault in an FDU quickly leads to an above-threshold error counter for that FDU and thus diagnoses the fault. For deconfiguration, we use previously developed schemes for functional units and buffers and present a scheme for deconfiguring DIVA checkers. Experimental results show that our reliable microprocessor quickly and accurately diagnoses each hard fault that is injected and continues to function, albeit with somewhat degraded performance.
A PPPoE implementation for linux
Authors: David F. Skoll
Venue: Proceedings of the 4th annual Linux Showcase & Conference - Volume 4 (2000)

Many DSL service providers use PPPoE for residential broadband Internet access. This paper briefly describes the PPPoE protocol, presents strategies for implementing it under Linux and describes in detail a user-space implementation of a PPPoE client.