ppxscal/embedding_network huggingface dataset:
Testing the Interconnect of RAM-Based FPGAs
Authors: Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian
Venue: IEEE Design Test (1998)

Programmable logic in the form of field-programmable gate arrays has become a widely accepted design approach for low- and medium-volume computing applications. Low development costs and inherent functional flexibility have spurred the spectacular growth of this technology. FPGAs are regular structures of logic modules communicating via an interconnect architecture of lines and switches. Users program the logic modules and interconnect structures to perform particular functions and realize the FPGA's global function.Manufacturers provide programmability in their FPGA architectures in various ways. They may use RAM to store configuration information, EPROM switches based on FAMOS (floating-gate avalanche-injection metal oxide semiconductor) transistors and fuses, or antifuses that permanently open or close connections. Of these alternatives, we have focused our work on RAM-based FPGAs. Their simplicity and flexibility for user changes in the field make this type of FPGA a very popular choice among designers. The architecture and design of these devices have been widely investigated during the last decade, but their test challenges have received less attention. Only recently have researchers addressed the problem of testing after manufacture-in other words, before user programming of specific functions. Testing before programming presents a wide spectrum of problems, for which a number of researchers have proposed innovative solutions.Testing an FPGA chip poses a challenging problem for test engineers. It requires implementing various configurations (programmings) of the FPGA. But changing configurations incurs reprogramming costs. So the question arises: How can we determine the minimum number of test configurations and corresponding vector test sequences that will cover all the faults of an FPGA's structural fault model? Dealing with this question in an earlier work, we proposed a general methodology for test configuration and test pattern generation. 5 Here, we apply this methodology to the interconnect structure. We propose a manufacturing test procedure for RAM- based FPGA interconnect structures.
Some Properties of Methods of Centers
Authors: Ahmed Roubi
Venue: Computational Optimization and Applications (2001)

Huard's method of centers is a method that solves constrained convex problems by means of unconstrained problems. In this paper we give some properties of this method, we analyse its convergence and rate of convergence and suggest some other variants and techniques to improve the speed of convergence.
Volume warping for adaptive isosurface extraction
Authors: Laurent Balmelli, Christopher J. Morris, Gabriel Taubin, Fausto Bernardini
Venue: Proceedings of the conference on Visualization '02 (2002)

Polygonal approximations of isosurfaces extracted from uniformly sampled volumes are increasing in size due to the availability of higher resolution imaging techniques. The large number of primitives represented hinders the interactive exploration of the dataset. Though many solutions have been proposed to this problem, many require the creation of isosurfaces at multiple resolutions or the use of additional data structures, often hierarchical, to represent the volume.We propose a technique for adaptive isosurface extraction that is easy to implement and allows the user to decide the degree of adaptivity as well as the choice of isosurface extraction algorithm. Our method optimizes the extraction of the isosurface by warping the volume. In a warped volume, areas of importance (e.g. containing significant details) are inflated while unimportant ones are contracted. Once the volume is warped, any extraction algorithm can be applied. The extracted mesh is subsequently unwarped such that the warped areas are rescaled to their initial proportions. The resulting isosurface is represented by a mesh that is more densely sampled in regions decided as important.
Frobenius groups with many involutions
Authors: Hubert Kiechle
Venue: Discrete Mathematics (2002)

We consider a special class of Frobenius Groups, which generalizes the class of sharply 2-transitive groups in such a way that the construction of a neardomain can be generalized to the construction of a K-loop. The group then is shown to be a quasidirect product of that K-loop by a suitable automorphism group. The major advantage of this point of view is the existence of examples which are hoped to shed some light on the still open problem of the existence of proper neardomains.
Maintaining Data-Driven Rules in Databases
Authors: Avigdor Gal, Opher Etzion
Venue: Computer (1995)

A new model with invariant-based language effectively handles data-driven rules in databases and uses the rules' inherent semantic properties and supporting mechanisms to meet high-level language requirements. It is an extension of the basic PARDES model developed by Opher Etzion in 1990 to support derivations and integrity constraints in databases. The model's invariant-based language, unlike other programming languages, can follow data- driven rules' semantic properties. Such rules are activated by modifications of data items in a database, and they play an important role in many applications that maintain complex relationships between data items or interdependencies between parts of the database. Applications include expert systems, real- time databases, simulations, and decision-support systems. The authors present requirements for choosing an adequate programming style that uses data-driven rules. These requirements are based on software-engineering criteria such as compatibility with a high-level language and verifiability of the rule language. The authors show that contemporary database programming styles fail to meet these requirements, and they present the invariant- based language as a viable solution.
Embedding Binary Trees into Crossed Cubes
Authors: Saïd Bettayeb, Priyalal Kulasinghe
Venue: IEEE Transactions on Computers (1995)

The recently introduced interconnection network, crossed cube, has attracted much attention in the parallel processing area due to its many attractive features. Like the ordinary hypercube, the n-dimensional crossed cube is a regular graph with 2n vertices and n2n¿1 edges. The diameter of the crossed cube is approximately half that of the ordinary hypercube. These advantages of the crossed cube motivated the study of how well it can simulate other networks such as the complete binary tree. In this paper, we show that the (2n¿ 1)-node complete binary tree can be embedded into the n-dimensional crossed cube with dilation 1.
Hyperlog: A Graph-Based System for Database Browsing, Querying, and Update
Authors: Alexandra Poulovassilis, Stefan G. Hild
Venue: IEEE Transactions on Knowledge and Data Engineering (2001)

Hyperlog is a declarative, graph-based language that supports database querying and update. It visualizes schema information, data, and query output as sets of nested graphs, which can be stored, browsed, and queried in a uniform way. Thus, the user need only be familiar with a very small set of syntactic constructs. Hyperlog queries consist of a set of graphs that are matched against the database. Database updates are supported by means of programs consisting of a set of rules. This paper discusses the formulation, evaluation, expressiveness, and optimization of Hyperlog queries and programs. We also describe a prototype implementation of the language and we compare and contrast our approach with work in a number of related areas, including visual database languages, graph-based data models, database update languages, and production rule systems.
Management of Partially Safe Buffers
Authors: Kenneth Salem, Sedat Akyürek
Venue: IEEE Transactions on Computers (1995)

Safe RAM is RAM which has been made as reliable as a disk. We consider the problem of buffer management in partially safe buffers, i.e., buffers which contain both safe RAM and volatile RAM. Buffer management techniques for partially safe buffers explicitly consider the safety of memory in deciding which data to place in the buffer, where to place it, and when to copy updates back to the disk. We present techniques for managing such buffers and study their performance using trace-driven simulations.
A Virtual Bus Architecture for Dynamic Parallel Processing
Authors: K. C. Lee
Venue: IEEE Transactions on Parallel and Distributed Systems (1993)

To support parallel processing of data-intensive applications, the interconnection networkof a parallel/distributed machine must provide high end-to-end communication bandwidth and handle the bursty and concentrated communication patterns generated by dynamic load balancing and data collection operations. A large-scale interconnection network architecture called a virtual bus is proposed. The virtual bus can scale toterabits-per-second end-to-end communication bandwidth with low queuing delay fornonuniform traffic. A terabit virtual bus architecture can be efficiently implemented forless than 5% of the total cost of an eight-thousand-node system. In addition, the virtualbus has an open system parallel interface that is flexible enough to support up togigabytes per second data transfer rates, different grades of services, and broadcastoperation. Such flexibility makes the virtual bus a plausible open system communicationbackbone for a broad range of applications.
Generating Tests for Delay Faults in Nonscan Circuits
Authors: Prathima Agrawal, Vishwani Agrawal, Sharad Seth
Venue: IEEE Design Test (1993)

A delay test method that allows any sequential-circuit test generation program to produce path delay tests for nonscan circuits is presented. Using this method, a given path is tested by augmenting the netlist model of the circuit with a logic block, in which testing for a certain single stuck-at fault is equivalent to testing for a path delay fault. The test sequence for the stuck-at fault performs all the necessary delay fault test functions: initialization, path activation, and fault propagation. Results on benchmarks are presented for nonscan and scan/hold modes of testing.
Computation of Normalized Edit Distance and Applications
Authors: A. Marzal, E. Vidal
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1993)

Given two strings X and Y over a finite alphabet, the normalized edit distance between X and Y, d(X,Y) is defined as the minimum of W(P)/L(P), where P is an editing path between X and Y, W(P) is the sum of the weights of the elementary edit operations of P, and L(P) is the number of these operations (length of P). It is shown that in general, d(X,Y) cannot be computed by first obtaining the conventional (unnormalized) edit distance between X and Y and then normalizing this value by the length of the corresponding editing path. In order to compute normalized edit distances, an algorithm that can be implemented to work in O(m*n/sup 2/) time and O(n/sup 2/) memory space is proposed, where m and n are the lengths of the strings under consideration. Experiments in hand-written digit recognition are presented, revealing that the normalized edit distance consistently provides better results than both unnormalized or post-normalized classical edit distances.
An efficient local search method guided by gradient information for discrete coefficient FIR filter design
Authors: Tolga Çiloglu
Venue: Signal Processing (2002)

A new local search method for the design of linear phase FIR filters with discrete valued coefficients is introduced in this paper. Conventional minimax criterion and normalized peak ripple magnitude (NPRM) are taken as objective functions. The principle is to search along low gradient routes with priority and to direct the search toward steeper sides as improved solutions cease to appear. The characteristics of the objective functions have been explained and used to devise the method. The method is novel in the way it generates the gradient information and makes use of it. At each step, a number of filter coefficients are picked according to the gradient information and perturbed to look for improved solutions. A specific neighborhood definition is proposed and used in perturbing the coefficients. The method has very low computational demand and is suitable for the design of long filters. The results of design examples demonstrate that the performance of the method can compete with those of optimal methods. Along the way, a closed form expression for the "filter gain" that minimizes NPRM is also given. Furthermore, it is shown that a previously proposed local search method unintentionally implements the ideas of this paper in an opposite order.
Multiple Fault Diagnosis by Sensitizing Input Pairs
Authors: Nobuhiro Yanagida, Hiroshi Takahashi, Yuzo Takamatsu
Venue: IEEE Design Test (1995)

This article presents an efficient method for multiple fault diagnosis of combinational circuits by sensitizing input-pairs. The diagnostic process uses five deduction rules and a progressive deduction procedure to deduce suspected multiple faults in a circuit without probing internal lines, based on the responses observed at primary outputs by sensitizing input-pairs. The authors present a detailed example to demonstrate their method and experimental results to show the efficiency of the method.
Linear Spiral Hashing for Expansible Files
Authors: Ye-In Chang, Chien-I. Lee, Wann-Bay ChangLiaw
Venue: IEEE Transactions on Knowledge and Data Engineering (1999)

The goal of dynamic hashing is to design a function and a file structure that allow the address space allocated to the file to be increased and reduced without reorganizing the whole file. In this paper, we propose a new scheme for dynamic hashing in which the growth of a file occurs at a rate of $\frac{n+k}{n}$ per full expansion, where $n$ is the number of pages of the file and $k$ is a given integer constant which is smaller than $n$, as compared to a rate of two in linear hashing. Like linear hashing, the proposed scheme (called linear spiral hashing) requires no index; however, the proposed scheme may or may not add one more physical page, instead of always adding one more page in linear hashing, when a split occurs. Therefore, linear spiral hashing can maintain a more stable performance through the file expansions and have much better storage utilization than linear hashing. From our performance analysis, linear spiral hashing can achieve nearly 97 percent storage utilization as compared to 78 percent storage utilization by using linear hashing, which is also verified by a simulation study.
Better Software Through Operational Dynamics
Authors: Lawrence Bernstein
Venue: IEEE Software (1996)

New views of mature ideas on software and quality productivity.As we develop code, we tend to think of it as static and sequential. This month, Larry Bernstein explains how phone companies evaluate a system's dynamic behavior to ensure that it is robust and reliable.¿Shari Lawrence Pfleeger
Power4 System Design for High Reliability
Authors: Douglas C. Bossen, Joel M. Tendler, Kevin Reick
Venue: IEEE Micro (2002)

To achieve reliability goals, Power4 system design incorporates fault tolerance throughout the hardware, firmware, and operating system. Together, these system components provide concurrent and deferred maintenance, multilevel recovery from error, and runtime diagnostics.
Logical/Linear Operators for Image Curves
Authors: Lee A. Iverson, Steven W. Zucker
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1995)

We propose a language for designing image measurement operators suitable for early vision. We refer to them as logical/linear (L/L) operators, since they unify aspects of linear operator theory and Boolean logic. A family of these operators appropriate for measuring the low-order differential structure of image curves is developed. These L/L operators are derived by decomposing a linear model into logical components to ensure that certain structural preconditions for the existence of an image curve are upheld. Tangential conditions guarantee continuity, while normal conditions select and categorize contrast profiles. The resulting operators allow for coarse measurement of curvilinear differential structure (orientation and curvature) while successfully segregating edge-and line-like features. By thus reducing the incidence of false-positive responses, these operators are a substantial improvement over (thresholded) linear operators which attempt to resolve the same class of features.
Automatic Recognition of Handwritten Numerical Strings: A Recognition and Verification Strategy
Authors: Luiz S. Oliveira, Robert Sabourin, Flávio Bortolozzi, Ching Y. Suen
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (2002)

A modular system to recognize handwritten numerical strings is proposed. It uses a segmentation-based recognition approach and a Recognition and Verification strategy. The approach combines the outputs from different levels such as segmentation, recognition, and postprocessing in a probabilistic model. A new verification scheme which contains two verifiers to deal with the problems of oversegmentation and undersegmentation is presented. A new feature set is also introduced to feed the oversegmentation verifier. A postprocessor based on a deterministic automaton is used and the global decision module makes an accept/reject decision. Finally, experimental results on two databases are presented: numerical amounts on Brazilian bank checks and NIST SD19. The latter aims at validating the concept of modular system and showing the robustness of the system using a well-known database.
Floating-Point Processors Join Forces in Parallel Processing Architectures
Authors: Ray Simar,  Jr., Peter Koeppen, Jerald Leach, Steve Marshall, Dave Francis, Greg Mekras, Jeffrey Rosenstrauch, Scott Anderson
Venue: IEEE Micro (1992)

The hardware architecture and software capabilities of the TMS320C40 floating-point digital signal processor are described. The C40 operates at 275 million operations per second (MOPS) and transfers data at a rate of 320 Mbytes/s with a 40-ns cycle time. A key architectural feature of the C40 for parallel computing is the six parallel bidirectional communication ports that permit direct connection and communication between processors in a parallel system. Examples illustrating the use of the C40 in a parallel processing environment are discussed.
Approximate Controllability for Semilinear Retarded Functional Differential Equations
Authors: J. M. Jeong, Y. C. Kwun, J. Y. Park
Venue: Journal of Dynamical and Control Systems (1999)

This paper deals with the approximate controllability of the semilinear functional differential equations with unbounded delays. We will also establish the regularity of the solution of the given system. It is shown the relation between the reachable set of the semilinear system and that of its corresponding linear system by using degree theory. Finally, a simple example to which our main result can be applied is given.
Uncalibrated Motion Capture Exploiting Articulated Structure Constraints
Authors: David Liebowitz, Stefan Carlsson
Venue: International Journal of Computer Vision (2003)

We present an algorithm for 3D reconstruction of dynamic articulated structures, such as humans, from uncalibrated multiple views. The reconstruction exploits constraints associated with a dynamic articulated structure, specifically the conservation over time of length between rotational joints. These constraints admit reconstruction of metric structure from at least two different images in each of two uncalibrated parallel projection cameras. As a by product, the calibration of the cameras can also be computed. The algorithm is based on a stratified approach, starting with affine reconstruction from factorization, followed by rectification to metric structure using the articulated structure constraints. The exploitation of these specific constraints admits reconstruction and self-calibration with fewer feature points and views compared to standard self-calibration. The method is extended to pairs of cameras that are zooming, where calibration of the cameras allows compensation for the changing scale factor in a scaled orthographic camera. Results are presented in the form of stick figures and animated 3D reconstructions using pairs of sequences from broadcast television. The technique shows promise as a means of creating 3D animations of dynamic activities such as sports events.
Optimal Representations of Polymorphic Types with Subtyping
Authors: Alexander Aiken, Edward L. Wimmers, Jens Palsberg
Venue: Higher-Order and Symbolic Computation (1999)

Many type inference and program analysis systems include notions of subtyping and parametric polymorphism. When used together, these two features induce equivalences that allow types to be simplified by eliminating quantified variables. Eliminating variables both improves the readability of types and the performance of algorithms whose complexity depends on the number of type variables. We present an algorithm for simplifying quantified types in the presence of subtyping and prove it is sound and complete for non-recursive and recursive types. We also show that an extension of the algorithm is sound but not complete for a type language with intersection and union types, as well as for a language of constrained types.
Multimedia Pedagogues
Authors: Beverly Park Woolf, Wendy Hall
Venue: Computer (1995)

Audio-visual material can provide useful aids for learning when integrated into computer-based teaching systems. However, a teaching system is only useful if the learner remains active and motivated. It is well-known that page turning or browsing does not ensure effective learning. To learn, students must want to learn and must be involved and active. They must be challenged to reason about the material presented. Flashy graphics and simulations are not enough; the experience must be authentic and relevant to the learner's life. Multimedia, when coupled with other improvements in educational software design, can support effective and quality instruction. We propose a model for instruction which moves beyond the 'Tyranny of the Button' and includes use of intelligent simulation, dynamic links (on-line generation of links based on a student's behavior), and multimedia composition and creation. We discuss technological barriers which prevent the widespread development of effective systems along with ways in which these barriers can be broken down. Finally we suggest that truly interactive systems can evolve into multimedia pedagogues and can facilitate a shift in teaching and learning.
How To Make Intuitive Testing More Systematic
Authors: Wieger Cornelissen, Ad Klaassen, Aart Matsinger, Gerhard van Wee
Venue: IEEE Software (1995)

Textbooks on testing often assume that you have unlimited time and resources to remove the faults from your software. So it is instructive to read how real organizations adjust their testing strategies to the time and resource pressures that affect almost all of us. In this issue¿s column, four practitioners from Philips describe their customized approach.¿ Shari Lawrence Pfleeger
On two determinants with interesting factorizations
Authors: Alina Copeland, Frank Schmidt, Rodica Simion
Venue: Discrete Mathematics (2002)

We show that two determinants arising in different mathematical contexts, both exhibiting striking factorization properties, are in fact related. These are the determinants of the matrix of chromatic joins and of the matrix associated with Lickorish's bilinear form in the study of invariants for 3-manifolds. We show that the two determinants are essentially equal up to a change of variable and that they are related to a determinant arising in the representation theory for type A Hecke algebras.