ppxscal/embedding_network huggingface dataset:
An Advanced Optimizer for the IA-64 Architecture
Authors: Rakesh Krishnaiyer, Dattatraya Kulkarni, Daniel Lavery, Wei Li, Chu-cheow Lim, John Ng, David Sehr
Venue: IEEE Micro (2000)

The IA-64 architecture has a rich set of features including control and data speculation, predication, large register files, and an advanced branch architecture, which allow the compiler to exploit instruction-level parallelism (ILP) and optimize applications in many new ways. The Intel IA-64 compiler incorporates i) state-of-the-art optimization techniques known in the compiler community, ii) optimization techniques that are extended to exploit the resources and features in IA-64, and iii) new optimization techniques designed for IA-64.
Concurrent Runtime Monitoring of Formally Specified Programs
Authors: Sriram Sankar, Manas Mandal
Venue: Computer (1993)

A methodology for continuously monitoring a program for specification consistency during program execution is described. Prior development of the formal specification and program is assumed. The program is annotated with constructs from a formal specification language, and the formal specification constructs are transformed into checking code, which is then inserted into the underlying program. Calls to this checking code are inserted into underlying program wherever it can potentially become inconsistent with its specification. If an inconsistency does in fact occur, diagnostic information is provided. The implementation of such a system for Anna (annotated Ada) subtype annotations is presented.
Toward a More Secure Internet
Authors: Randall J. Atkinson
Venue: Computer (1997)

Lack of widely available Internet security has discouraged some commercial users. The author describes efforts to make cryptographic security more widely available and looks at efforts to secure the Internet infrastructure. Commercial and government enterprises have been reluctant to use the Internet because cryptographic security mechanisms are not widely available. The Internet continues to grow rapidly, but it is becoming increasingly segmented as companies resort to firewalls and intranets. If this continues, the concept of a global network will give way to many islands of private intranets only partially connected to a global structure. This would limit the usefulness of Internet technology in connecting people and hence would impede the rapid dissemination of information-one of the main reasons the Internet was created. During the past few years, significant progress has been made within the Internet Engineering Task Force, the Internet standards body, in adding cryptographic security to standards for the Internet infrastructure. This progress offers hope in restoring the vision of a global Internet, but some obstacles remain. This article describes efforts to address security in the five areas of the Internet infrastructure: the Internet Protocol itself, routing of the Internet Protocol packets, name and address resolution using the Domain Name System, network management, and the key management used in the preceding four areas. For each area, the article describes the current technology, outlines the security risks addressed, and discusses likely future directions. As the description underlines, the technology is largely here, but nontechnical issues also influence progress: the avoidance of patented technologies where feasible, commercial concerns about the timely availability of standards, and community mistrust of some technologies (like key escrow) can delay the adoption of new technologies. The good news is that despite these obstacles, the Internet of the next century should have significantly stronger and more widely available security mechanisms. The bad news is that, at least for the foreseeable future, we are in a race with the parties attacking the Internet, so the Internet's security technologies must continue to evolve as attacks grow more sophisticated.
A Study of Achievable Speedup in Distributed Simulation via NULL Messages
Authors: D. Kumar, S. Harous
Venue: IEEE Transactions on Parallel and Distributed Systems (1993)

The results of an experimental study on distributed simulation of three open queuingnetworks are reported. The distributed simulation scheme considered is a simple variationof the scheme given by K.M. Chandy and J. Misra (1979) using NULL messages. A newapproach is used to study the relationship between the overhead and performance of adistributed simulator, and the approach is illustrated by studying these three examplenetworks. Two measures of ideal speedup of distributed simulation over sequentialsimulation are defined and measured. These values of ideal speedup are much less thansimply the number of processors, and hence provide a more realistic value for the ideal speedup.
Global Scheduling for Flexible Transactions in Heterogeneous Distributed Database Systems
Authors: Aidong Zhang, Marian Nodine, Bharat Bhargava
Venue: IEEE Transactions on Knowledge and Data Engineering (2001)

A heterogeneous distributed database environment integrates a set of autonomous database systems to provide global database functions. A flexible transaction approach has been proposed for the heterogeneous distributed database environments. In such an environment, flexible transactions can increase the failure resilience of global transactions by allowing alternate (but in some sense equivalent) executions to be attempted when a local database system fails or some subtransactions of the global transaction abort. In this paper, we study the impact of compensation, retry, and switching to alternative executions on global concurrency control for the execution of flexible transactions. We propose a new concurrency control criterion for the execution of flexible and local transactions, termed F-serializability, in the error-prone heterogeneous distributed database environments. We then present a scheduling protocol that ensures F-serializability on global schedules. We also demonstrate that this scheduler avoids unnecessary aborts and compensation.
Establishing the Relevancy of the Bookkeeping Libraries to the Functional Testing of Computer Implementations
Authors: Stamatis Vassiliadis, George Triantafyllos, Walid Kobrosly
Venue: IEEE Transactions on Knowledge and Data Engineering (1997)

In this paper, we address issues related to the definition of "faults," "errors," and "failures" and their separability, and attribution to the different development processes of computing systems. In particular, we deal with historical databases, which presumably contain certain data (i.e., test failure data) and describe the methodology that can be used to analyze the database and obtain the pertinent information. The validation method may be of particular importance, especially when information from the database needs to be extrapolated for a purpose other than the one for which the database was developed. Our methodology was used to evaluate the historical data collected during the development of the IBM 4381 and 9370 family of computers, and to extrapolate the faults found during the function testing.
Design for Consecutive Testability of System-on-a-Chip with Built-In Self Testable Cores
Authors: Tomokazu Yoneda, Hideo Fujiwara
Venue: Journal of Electronic Testing: Theory and Applications (2002)

This paper introduces a new concept of testability called consecutive testability and proposes a design-for-testability method for making a given SoC consecutively testable based on integer linear programming problem. For a consecutively testable SoC, testing can be performed as follows. Test patterns of a core are propagated to the core inputs from test pattern sources (implemented either off-chip or on-chip) consecutively at the speed of system clock. Similarly the test responses are propagated to test response sinks (implemented either off-chip or on-chip) from the core outputs consecutively at the speed of system clock. The propagation of test patterns and responses is achieved by using interconnects and consecutive transparency properties of surrounding cores. All interconnects can be tested in a similar fashion. Therefore, it is possible to test not only logic faults but also timing faults that require consecutive application of test patterns at the speed of system clock since the consecutively testable SoC can achieve consecutive application of any test sequence at the speed of system clock.
Object-Oriented Design of Telecommunication Software
Authors: Seiichi Yamazaki, Kiyohiko Kajihara, Mitsutaka Ito, Ryuichi Yasuhara
Venue: IEEE Software (1993)

A real-time object-oriented method, ROOD, that is specially designed to handle the complexity inherent in telecommunication systems is discussed. ROOD comprises an extended object-oriented modeling technique, called multiview modeling and a hierarchical system model, both tailored to the special needs of large real-time systems, especially telecommunication systems. The application of ROOD to the design of radio-controller software for a cellular phone system is described.
The Case for Continued Cobol Education
Authors: Donald Carr, Ronald J. Kizior
Venue: IEEE Software (2000)

In accessing the IS manager's view and the academic's view of Cobol's future, this survey found that 95% of its academic respondents and 90% of the IS managers polled want the IS curricula to continue offering Cobol instruction. Also, nearly 90% of IS managers indicate that Cobol instruction in colleges should cover both Cobol's OO and Web-based features.
Communication-Free Data Allocation Techniques for Parallelizing Compilers on Multicomputers
Authors: T. S. Chen, J. P. Sheu
Venue: IEEE Transactions on Parallel and Distributed Systems (1994)

In distributed memory multicomputers, local memory accesses are much faster than thoseinvolving interprocessor communication. For the sake of reducing or even eliminating theinterprocessor communication, the array elements in programs must be carefullydistributed to local memory of processors for parallel execution. We devote our efforts tothe techniques of allocating array elements of nested loops onto multicomputers in acommunication-free fashion for parallelizing compilers. We first analyze the pattern ofreferences among all arrays referenced by a nested loop, and then partition the iterationspace into blocks without interblock communication. The arrays can be partitioned underthe communication-free criteria with nonduplicate or duplicate data. Finally, a heuristicmethod for mapping the partitioned array elements and iterations onto the fixed-sizemulticomputers under the consideration of load balancing is proposed. Based on thesemethods, the nested loops can execute without any communication overhead on thedistributed memory multicomputers. Moreover, the performance of the strategies withnonduplicate and duplicate data for matrix multiplication is studied.
Hybrid Fault Diagnosability with Unreliable Communication Links
Authors: C. -L. Yang, G. M. Masson
Venue: IEEE Transactions on Computers (1988)

Hybrid fault diagnosability in distributed multiprocessor systems is considered for the case in which, in addition to units being faulty, communication links among units can also be faulty. A hybrid fault situation is a (bounded) combination of hard and soft failing units. A novel hybrid fault diagnosability, denoted (t/t/sub s/-unit: sigma -link)-diagnosability is introduced (a total of t or fewer units can be faulty with at most t/sub s/ of them soft-failing; sigma is the number of incorrect test outcomes caused by unreliable links)., This diagnosability is compatible with the previously known t/t/sub s/-diagnosability and can additionally tolerate up to sigma incorrect test outcomes to give always-correct diagnosis for any hybrid-fault (HF)-compatible syndrome from a hybrid fault situation. It is shown that an O( mod E mod ) algorithm, proposed originally by the authors for faulty unit identification in t/sub s/-diagnosable systems, can be used to analyze a syndrome from a (t/sub s/-unit sigma -link)-diagnosable system efficiently without any preclassification of the syndrome in terms of HF-compatibility. It is shown that this algorithm not only identifies all the faulty units associated with an HF-compatible syndrome but also produces nonempty, always-correct diagnosis for many HF-incompatible syndromes.
Enhancing the Fault Tolerance of Workflow Management Systems
Authors: Gustavo Alonso, Claus Hagen, Divyakant Agrawal, Amr El Abbadi, C. Mohan
Venue: IEEE Concurrency (2000)

Workflow systems hold the promise of facilitating the everyday operation of many enterprises and work environments. As a result, many commercial workflow management systems have been developed. These systems, although useful, do not scale well, have limited fault tolerance, and don't interoperate well with other workflow systems. This article discusses the limitations of WFMSs and various research directions and potential future extensions to their design and modeling. By adapting solutions from other areas of computing such as database systems and programming languages, workflow services might be able to improve enough to meet the needs of mission-critical applications. If WFMSs are to become a commodity (which many practitioners and researchers believe), such concepts must make their way into commercial products.
Visual Servoing for Online Facilities
Authors: Bahram Parvin, John R. Taylor, Daniel E. Callahan, William E. Johnston, Ulrich Dahmen
Venue: Computer (1997)

Scientists who want to share microscopes over the Internet need systems that can provide the exact look and feel available to the local operator and that can hide unpredictable network delays. Providing the look and feel is achieved through the user interface. Hiding network latency is achieved through visual servoing. Visual servoing for online facilities interprets a visual scene and then automatically manipulates an instrument on the basis of control parameters. The authors' approach revolves around a set of visual routines implemented in a client-server architecture. The applications are two labor-intensive experiments: the microdissection of DNA molecules and in-situ examination of crystal formation. Micro-dissection and subsequent amplification of DNA molecules allow for rapid closure of gaps in the genomic library. In-situ experiments reveal information about the thermal and morphological properties of crystal structures. The authors demonstrate that intelligent visual interpretation and the use of this information for control can compensate for the Internet's latency and make it possible for many scientists to share scarce resources. Here, the result is easier use of an electron microscope, a centralized and complicated instrument.
Visualization in Teleimmersive Environments
Authors: Jason Leigh, Andrew E. Johnson, Maxine Brown, Daniel J. Sandin, Thomas A. DeFanti
Venue: Computer (1999)

In collaborative virtual reality (VR), the goal is to reproduce a face-to-face meeting in minute detail. Teleimmersion moves beyond this idea, integrating collaborative VR with audio- and video- conferencing that may involve data mining and heavy computation. In teleimmersion, collaborators at remote sites share the details of a virtual world that can autonomously control computation, query databases, and gather results. They don't meet in a room to discuss a car engine; they meet in the engine itself. The University of Illinois at Chicago's Electronic Visualization Laboratory (EVL) has hosted several applications that demonstrate rudimentary teleimmersion. All users are members of Cavern--the CAVE Research Network (www.evl.uic.edu/cavern)--a collection of participating industrial and research institutions equipped with CAVE (Cave Automated Virtual Environment), ImmersaDesk VR systems, and high-performance computing resources, including high-speed networks. There are more than 100 CAVE and ImmersaDesk installations worldwide. The pressing challenge now, as this article illustrates, is how to support collaborative work among Cavern users without having them worry about the details of sustaining a collaboration. Another problem is providing both synchronous and asynchronous collaboration. The authors detail how they've built new display devices to serve as more convenient teleimmersion end points and to support their international networking infrastructure with sufficient bandwidth to support the needs of teleimmersive applications.
A Ramsey theorem for countable homogeneous directed graphs
Authors: N. W. Sauer
Venue: Discrete Mathematics (2002)

Let T be a finite set of finite tournaments and HT the countable homogeneous directed graph which does not embed any of the tournaments in T. We will completely describe the vertex partition property HT.
Information processing in dendrites-II.: information theoretic complexity
Authors: Kevin N. Gurney
Venue: Neural Networks (2001)

In the companion paper, we established a rationale for exploring the general principles of dendritic processing using a class of Boolean functions--the Multi-Cube Units (MCUs). Here, we use this approach to further characterise dendritic processing using ideas from information theory and studies in complexity. The starting point is a novel decomposition of a Boolean function's total mutual information (between input variables and the output). Each component of the decomposition is a mutual information measure with respect to a single input, conditioned on a subset of the remaining inputs. We call this decomposition the information spectrum and conceive of it as a re-representation of the function in the information domain. Furthermore, the information spectrum of a Boolean function may be assigned a complexity value using the approximate entropy introduced by Pincus (Pincus, S. M. (1991). Approximate entropy as a measure of system complexity. Proc. Natl. Acad. Sci. USA, 88, 2297-2301). Using Monte Carlo methods, we provide evidence that the information spectral complexity of MCUs is larger than that of any other class of Boolean function. we explain this phenomenon in terms of information flow through the 2-stage MCU architecture. Under our modelling assumptions, the implication for biological neural processing is that dendrites implement functions that have maximal information spectral complexity with respect to the class of multivariate functions from which they are drawn.
Designing Efficient Parallel Algorithms on Mech-Connected Computers with Multiple Broadcasting
Authors: Y. C. Chen, W. T. Chen, G. H. Chen, J. P. Sheu
Venue: IEEE Transactions on Parallel and Distributed Systems (1990)

Semigroup and prefix computations on two-dimensional mesh-connected computers with multiple broadcasting (2-MCCMBs) are studied. Previously, only square 2-MCCMBs with N processing elements were considered for semigroup computations of N data items, andO(N/sup 1/6/) time was required. It is found that square machines are not the best form for semigroup computations, and an O(N/sup 1/8/)-time algorithm is derived on an N/sup 5/8/*N/sup 3/8/ rectangular 2-MCCMB. This time complexity can be further reduced toO(N/sup 1/9/) if fewer processing elements are used. Parallel algorithms for prefix computations with the same time complexities are derived.
Developing the Distributed-Computing OS
Authors: Steven J. Vaughan-Nichols
Venue: Computer (2002)

Researchers are exploring the world of distributed computing, in which users in various locations can work with the same set of geographically dispersed resources. These efforts haveled to such high-profile technologies as peer-to-peer (P2P), pervasive, and nomadic computing.
Parallel Implementations of the Selection Problem: A Case Study
Authors: Marc Daumas, Paraskevas Evripidou
Venue: International Journal of Parallel Programming (2000)

The selection problem has been studied extensively on sequential machines. A linear average time solution and a linear worst-case solution are considered as the standard by most researchers. Theoretical work is also available on parallel models, but it has not been widely implemented on parallel machines. This paper presents an in-depth analysis of the implementation of the standard algorithms, on a number of multiprocessors and supercomputers from the entire spectrum of Flynn's classification, using both an imperative (C based languages with vendor specific parallel extensions) and a functional (SISAL) language. Very interesting results were obtained for all of the experiments performed, leading us to the conclusion that the selection problem has very efficient parallel implementations. Hand-tuned C programs with parallel extensions provided good efficiency but were time-consuming in terms of development. On the other hand, the SISAL code is fully portable and the same program was used on all the machines. The performances of SISAL implementations were comparable to the ones of the hand-tuned C implementations. On all the tests, the routines were able to sustain good speed-up and reasonable efficiency, even with a large number of processors. In two cases (one machine using SISAL, and one using a C-based language), we were able to obtain an efficiency higher than 80% with a configuration close or equal to the maximum number of processors.
An Efficient Evaluation of a Fuzzy Equi-Join Using Fuzzy Equality Indicators
Authors: Weining Zhang, Ke Wang
Venue: IEEE Transactions on Knowledge and Data Engineering (2000)

We propose a new measure of fuzzy equality comparison based on the similarity of possibility distributions. we define a type of fuzzy equi¿join based on the new fuzzy equality comparison, and allow threshold values to be associated with predicates of the join condition. A sort¿merge join algorithm based on a partial order of intervals is used to evaluate the fuzzy equi-join. In order for the evaluation to be efficient, we identify various mappings, called fuzzy equality (FE) indicators, that will determine appropriate intervals for fuzzy data with different characteristics. Experiment results from our preliminary simulation of the algorithm show a significant improvement of efficiency when FE indicators are used with the sort¿merge join algorithm.
Optimizing Sinusoidal Histogram Test for Low Cost ADC BIST
Authors: F. Azaïs, S. Bernard, Y. Bertrand, M. Renovell
Venue: Journal of Electronic Testing: Theory and Applications (2001)

The histogram method is a very classical test technique for Analog to Digital Converters (ADCs), but only used for external testing because of the large amount of required hardware resources. This paper discusses the viability of a BIST implementation for this technique. An original approach is developed that permits to extract the ADC parameters with a reduced area overhead. This approach involves (i) the calculation of the parameters using approximations and (ii) the decomposition of the global test in a code-after-code test procedure. These two features allow a significant reduction of the required operative resources and memory dedicated to the storage of experimental data. In addition, the use of a piece-wise approximation for computing the ideal histogram also permits to minimize the memory dedicated to the storage of reference data.