ppxscal/embedding_network huggingface dataset:
O2 ABA: a novel high-performance predictable circuit architecture for the deep submicron era
Authors: Yonghee Im, Kaushik Roy
Venue: IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2002)

Current VLSI design techniques focus on four major goals: higher integration, faster speed, lower power, and shorter time-to-market. These goals have been accomplished mainly by deep submicron (DSM) technology along with voltage scaling. However, scaling down of feature size causes larger interwire capacitance which results in large crosstalk between interconnects. In this paper, we propose a novel predictable circuit architecture, named "optimized overlaying array-based architecture" (O2 ABA), especially suited for the deep submicron regime. O2 ABA achieves reduction in crosstalk by considering the current directions and by reducing interwire capacitance. The introduction of "unit cell" leads to regularity, which makes the performance predictable even before layout, and shortens design time. O2 ABA is compared with other design styles, such as custom design and standard cell approach, in terms of coupling capacitance, area, and delay.
External Rewriting for Skeptical Proof Assistants
Authors: Quang Huy Nguyen, Claude Kirchner, Hélène Kirchner
Venue: Journal of Automated Reasoning (2003)

This paper presents the design, the implementation, and experiments of the integration of syntactic, conditional possibly associative-commutative term rewriting into proof assistants based on constructive type theory. Our approach is called external because it consists in performing term rewriting in a specific and efficient environment and checking the computations later in a proof assistant. Two typical systems are considered in this work: ELAN, based on the rewriting calculus, as the term rewriting-based environment, and Coq, based on the calculus of inductive constructions as the proof assistant. We first formalize the proof terms for deduction by rewriting and strategies in ELAN using the rewriting calculus with explicit substitutions. We then show how these proof terms can soundly be translated into Coq syntax where they can be directly type checked. For the method to be applicable for rewriting modulo associativity and commutativity, we provide an effective method to prove equalities modulo these axioms in Coq using ELAN. These results have been integrated into an ELAN-based rewriting tactic in Coq.
Virtual-Address Caches Part 1: Problems and Solutions in Uniprocessors
Authors: Michel Cekleov, Michel Dubois
Venue: IEEE Micro (1997)

In order to support virtual memory, virtual addresses must be efficiently translated into physical addresses. Traditionally, this dynamic translation has been done in a Translation Lookaside Buffer (TLB) before or in parallel with the cache access, so that the cache is indexed and tagged with physical addresses. However, physical-address caches are either slow or limited in size. To solve this bottleneck, caches can be accessed directly with virtual addresses. Unfortunately, consistency problems add complexity to virtual-address caches. These problems are mostly caused by synonyms and address-mapping changes. In this first part, we introduce the problems and discuss solutions in the context of single-processor systems. In Part 2 of this two-part series, we will address multiprocessor issues.
Some Trading Strategies on the Securities Market
Authors: P. S. Knopov, T. V. Pepelyaeva
Venue: Cybernetics and Systems Analysis (2002)

Trading strategies and utility functions on securities market are considered. It is shown how to find an optimal strategy when the theory of controlled homogeneous Markov chains is used. A corresponding theorem is proved.
Exponentiation Using Division Chains
Authors: Colin D. Walter
Venue: IEEE Transactions on Computers (1998)

Exponentiation may be performed faster than the traditional square and multiply method by iteratively reducing the exponent modulo numbers which, as exponents themselves, require few multiplications. This mainly includes those with few nonzero bits. For a suitable choice of such divisors, the resulting mixed basis representation of the exponent reduces the expected number of nonsquaring multiplications by over half at the cost of a single extra register. Preprocessing effort depends entirely on the exponent and can be kept down to the work saved in a single exponentiation. Moreover, no precomputed look-up tables are required, so the method is especially applicable where space is at a premium. In particular, it outperforms the instance of the m-ary method which uses the same space. However, for 512-bit exponents, it beats every instance of the m-ary method, achieving well under 635 multiplications on average. Both hardware and software implementations of the RSA crypto-system can benefit from this algorithm.
Coordinated Approach to Telecommunications Management
Authors: James Callaghan, Terry Turner
Venue: IEEE Software (1993)

The RACE (research and development in advanced communications in Europe) program embraces all the issues surrounding the development and deployment of integrated broadband communications in Europe. In the RACE program, the domain of network management encompasses the concept of using a separate network to manage the telecommunications network itself. This separate network is called a telecommunications-management network (TMN). Guideline, a project created to coordinate all the TMN work done in RACE, develop a common approach to TMN architecture, and recommend which AIP techniques would be appropriate, is described. Guideline provides an interface to RACE projects outside the TMN area and to international standards organizations and other trade groups. It also provides an interface to the TMN specifications projects, Netman and Terrace.
Decomposing Banyan Networks for Performance Analysis
Authors: U. Garg, Y. -P. Huang
Venue: IEEE Transactions on Computers (1988)

A general form of input-destination distribution matrix increases state space exorbitantly, thus making any buffer at every state statistically different from another. Certain specific forms of input-destination distribution matrix to which many real-life cases may conform, are analyzed. The idea called decomposition is applied here for specific nonhomogeneous flows. State space is not allowed to increase significantly; also the reduction in network size at successive stages is utilized to increase the computational efficiency.
Miller factor for gate-level coupling delay calculation
Authors: Pinhong Chen, Desmond A. Kirkpatrick, Kurt Keutzer
Venue: Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design (2000)

In coupling delay computation, a Miller factor of more than 2X may be necessary to account for active coupling capacitance when modeling the delay of deep submicron circuitry in the presence of active coupling capacitance. We propose an efficient method to estimate this factor such that the delay response of a decoupling circuit model can emulate the original coupling circuit. Under the assumptions of zero initial voltage, equal charge transfer, and 0.5VDD as the switching threshold voltage, an upper bound of 3X for maximum delay and a lower bound of -1X for minimum delay can be proven. Efficient Newton-Raphson iteration is also proposed as a technique for computing the Miller factor or effective capacitance. This result is highly applicable to crosstalk coupling delay calculation in deep submicron gate-level static timing analysis. Detailed analysis and approximation are presented. SPICE simulations are demonstrated to show high correlation with these approximations.
Interactive Simulation and Visualization
Authors: Christopher Johnson, Steven G. Parker, Charles Hansen, Gordon L. Kindlmann, Yarden Livnat
Venue: Computer (1999)

Most researchers who perform data analysis and visualization do so only after everything else is finished, which often means that they don't discover errors invalidating the results of their simulation until postprocessing. A better approach would be to improve the integration of simulation and visualization into the entire process so that they can make adjustments along the way. This approach, called computational steering, is the capacity to control all aspects of the computational science pipeline. Recently, several tools and environments for computational steering have begun to emerge. These tools range from those that modify an application's performance characteristics, either by automated means or by user interaction, to those that modify the underlying computational application. A refined problem-solving environment should facilitate everything from algorithm development to application steering. The authors discuss some tools that provide a mechanism to integrate modeling, simulation, data analysis, and visualization.
Lie Representations and an Algebra Containing Solomon's
Authors: Frédéric Patras, Christophe Reutenauer
Venue: Journal of Algebraic Combinatorics: An International Journal (2002)

We introduce and study a Hopf algebra containing the descent algebra as a sub-Hopf-algebra. It has the main algebraic properties of the descent algebra, and more: it is a sub-Hopf-algebra of the direct sum of the symmetric group algebras&semi; it is closed under the corresponding inner product&semi; it is cocommutative, so it is an enveloping algebra&semi; it contains all Lie idempotents of the symmetric group algebras. Moreover, its primitive elements are exactly the Lie elements which lie in the symmetric group algebras.
Computing Display Conflicts in String Visualization
Authors: D. P. Mehta, S. Sahni
Venue: IEEE Transactions on Computers (1994)

Strings are used to represent a variety of objects such as DNA sequences, text, and numerical sequences. A model for a system for the visualization and analysis of strings was proposed by D. Mehta and S. Sahni (1992). The problem of display conflicts that arise in this model was identified and methods to overcome it were suggested. These methods require the computation of display conflicts. We present efficient algorithms to compute display conflicts.
An Optimal Strategy for Comparing File Copies
Authors: K. A. S. Abdel-Ghaffar, A. El Abbadi
Venue: IEEE Transactions on Parallel and Distributed Systems (1994)

We study the problem of identifying corrupted pages between two remotely locatedcopies of a file in a distributed system. An efficient deterministic algorithm is presented to identify up to any given number of differing pages. The algorithm requires a singleexchange of messages and is based on the structure of the Reed-Solomon code. In orderto identify up to f corrupted pages, 2f signatures are transmitted. The algorithm requiresless communication costs than previously proposed solutions. In fact, we prove that ouralgorithm is optimal, in the sense that no other algorithm is guaranteed to identify withprobability 1 the corrupted pages by exchanging less information.
Scaling Up Agent Coordination Strategies
Authors: Edmund H. Durfee
Venue: Computer (2001)

Exactly what an intelligent agent is and in what sense a computational agent can behave intelligently remain the subjects of considerable debate. However, most researchers and developers would agree that coordination is an intelligent agent's central concern. Without coordination, agents can unintentionally waste their efforts, squander resources, or fail to accomplish objectives that require collective effort. Advances in agent-oriented software engineering make it possible to develop complex, distributed systems, but the component agents must be able to act and interact flexibly. Characterizing agent population properties, their task environments, and their collective behavior are key to understanding the capabilities and limitations of coordination strategies that support flexible component agent interaction. Researchers face the challenge of developing a better-- preferably quantifiable--understanding of exactly how far different strategies can scale along the dimensions required to apply intelligent agent systems to increasingly challenging problems.
Enumeration of Test Sequences in Increasing Chronological Order to Improve the Levels of Compaction Achieved by Vector Omission
Authors: Irith Pomeranz, Sudhakar M. Reddy
Venue: IEEE Transactions on Computers (2002)

We describe a method to improve the levels of compaction achievable by static compaction procedures based on vector omission. Such procedures are used to reduce the lengths of test sequences for synchronous sequential circuits without reducing the fault coverage. The proposed procedure enumerates, in increasing chronological order, test sequences consisting of subsets of the vectors included in a given test sequence that needs to be compacted. The unique feature of this approach is that test vectors omitted from the test sequence at an earlier iteration can be reintroduced at a later iteration. This results in a less greedy procedure and helps reduce the compacted test sequence length beyond the length that can be achieved if vectors are omitted permanently as in earlier procedures.
Predicting Client/Server Availability
Authors: Alan Wood
Venue: Computer (1995)

This paper contains an analysis of client/server outage data and presents a list of outage causes extracted from the data. The outage causes include hardware, software, operations, and environmental failures, as well as outages due to planned reconfigurations. The study spans all client, server, and network devices in a typical client/server environment. The paper illustrates how to use the data to predict client/server availability and evaluate potential availability improvements. The results are stated in terms of annual user outage minutes and have been validated by comparison with other outage surveys and data in the literature. The major results from the outage data study are:
An Architectural Framework for CKBS Applications
Authors: S. m. Deen
Venue: IEEE Transactions on Knowledge and Data Engineering (1996)

This paper presents an architectural framework for cooperating knowledge based systems (CKBSs) with parallels drawn from the multiagent systems of DAI. A CKBS is distinguished from a multiagent system by its need to provide a workable approach for real-world distributed applications. The framework proposed considers only interagent activities in what is called transaction-oriented processing. The framework, based largely on well-tested computer science concepts, provides for a multilayered edifice with information transparency, and a multilevel schema to suit different user expertise. It permits dynamic definition of cooperation strategies for different tasks as required, in a high-level language providing relative ease of use. A particular novelty is the interpretation of actions as side-effects of update operations on action tuples transmitted among agents via what are called shadows. This provides the generality needed. Effectiveness, flexibility, and ease of use are some of the key considerations.
Your Favorite Parallel Algorithms Might Not Be as Fast as You Think
Authors: D. C. Fisher
Venue: IEEE Transactions on Computers (1988)

A problem that requires I inputs, K outputs and I computations is to be solved on a d-dimensional parallel processing machine (usually d>or=3). Finite transmission speed and other real-world conditions are assumed. It is proved that the time needed to solve the problem is t= Omega /sub max/ (I/sup 1/d/, K/sup 1/d/, T/sup 1/(d+1)/). This result is demonstrated for the standard algorithm for multiplying two n*n matrices.
Occam Algorithms for Computing Visual Motion
Authors: Haim (Shvaytser) Schweitzer
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1995)

The standard approach to computing motion relies on pixel correspondence. Computational schemes impose additional constraints, such as smoothness and continuity of the motion vector field, even though these are not directly related to pixel correspondence. This paper proposes an alternative to the multiple constraints approach. By drawing analogy with machine learning, motion is computed as a function that accurately predicts frames. The Occam-Razor principle suggests that among all functions that accurately predict the second frame from the first frame, the best predictor is the ¿simplest,¿ and simplicity can be rigorously defined in terms of encoding length. An implementation of a practical algorithm is described. Experiments with real video sequences verify the algorithm assumptions by showing that motion in typical sequences can be accurately described in terms of a few parameters. Our particular choice of predictors produces results that compare very favorably with other image flow algorithms in terms of accuracy and compactness. It may, however, be too constrained to enable accurate recovery of 3D motion and structure.
An assembly-level execution-time model for pipelined architectures
Authors: G. Beltrame, C. Brandolese, W. Fornaciari, F. Salice, D. Sciuto, V. Trianni
Venue: Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design (2001)

The aim of this work is to provide an elegant and accurate static execution timing model for 32-bit microprocessor instruction sets, covering also inter-instruction effects. Such effects depend on the processor state and the pipeline behavior, and are related to the dynamic execution of assembly code. The paper proposes a mathematical model of the delays deriving from instruction dependencies and gives a statistical characterization of such timing overheads. The model has been validated on a commercial architecture, the Intel486, by means of timing analysis of a set of benchmarks, obtaining an error within 5%. This model can be seamlessly integrated with a static energy consumption model in order to obtain precise software power and energy estimations.
Motion Estimation Via Cluster Matching
Authors: D. P. Kottke, Y. Sun
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1994)

A new method for estimating displacements in computer imagery through cluster matching is presented. Without reliance on any object model, the algorithm clusters two successive frames of an image sequence based on position and intensity. After clustering, displacement estimates are obtained by matching the cluster centers between the two frames using cluster features such as position, intensity, shape and average gray-scale difference. The performance of the algorithm was compared to that of a gradient method and a block matching method. The cluster matching approach showed the best performance over a broad range of motion, illumination change and object deformation.
Sync: A Java Framework for Mobile Collaborative Applications
Authors: Jonathan P. Munson, Prasun Dewan
Venue: Computer (1997)

Introducing the factors of wireless mobile systems into the development of collaborative applications complicates developers' lives significantly. Application frameworks targeted for coordinating wireless mobile applications simplify development. The authors describe Sync, a development framework that provides high-level primitives that enable programmers to create arbitrarily complex, synchronized, replicated data objects. Designed for wireless networks, Sync enables applications to share changes at a granularity as small as updates to basic types and so enables better performance on low-bandwidth connections.
Lotus Notes and Domino 4.5 Answers! Certified Tech Support, 1st edition
Authors: Polly Russell Kornblith
Venue:  (1997)

:In this handy reference and troubleshooting guide,we will cover all the new mail,scheduling,and web features of Domino,powered by Notes 4. 5. Issues include security,access,and web page creation and design. In addition to the existing chapters,we will add coverage of: Domino and the Internet; Calendaring and Scheduling; LotusScript; Actions; Agents; Mobile Computing.
Automaton theory approach for solving modified PNS Problems
Authors: B. Imreh
Venue: Acta Cybernetica (2002)

In this paper a modified version of the Process Network Synthesis (PNS) problem is studied. By using an automaton theoretical approach, a procedure for finding an optimal solution of this modified PNS problem is presented.
New BIST Schemes for Structural Testing of Pipelined Analog to Digital Converters
Authors: Eduardo J. Peralías, Adoración Rueda, José L. Huertas
Venue: Journal of Electronic Testing: Theory and Applications (2001)

Two alternative BIST schemes are proposed for structural testing of pipelined Analog-to-Digital Converters (ADC). They are oriented to fault detection in the converter stages rather than to measure the whole ADC electrical performance parameters. The operational principle of both strategies relies on testing every ADC stage reconfigured as an A/D-D/A block and applying as input a simple DC stimuli set which is easily obtained, without strong precision requirements, by a resistive network. The main differences between both strategies relate to the way the output response is evaluated. In the BIST&num;1 scheme, analog and digital outputs are compared with reference levels generated with a reference D/A converter and a counter. In the BIST&num;2 strategy, only digital outputs are available and they are compared with fault-free values previously stored in an on-chip register. The new techniques are intended to be used in pipelined converters of an arbitrary number of conversion stages and with a digital self-correction mechanism.
An Analog VLSI Implementation of Hopfield's Neural Network
Authors: Michel Verleysen, Paul G. A. Jespers
Venue: IEEE Micro (1989)

The basic requirements for electronic implementations of the fully connected Hopfield network are examined, highlighting the reasons why the authors regard analog implementations as more appropriate. Analog VLSI networks are then discussed, with particular reference to the selection of memory points and the design of the synapse, and experimental results are given. A test chip containing 14 neurons and 196 synapses is described.
A State Assignment Approach to Asynchronous CMOS Circuit Design
Authors: V. Kantabutra, A. G. Andreou
Venue: IEEE Transactions on Computers (1994)

Present a new algorithm for state assignment in asynchronous circuits so that for each circuit state transition, only one (secondary) state variable switches. No intermediate unstable states are used. The resultant circuits operate at optimum speed in terms of the number of transitions made and use only static CMOS gates. By reducing the number of switching events per state transition, noise due to the switching events is reduced and dynamic power dissipation may also be reduced. This approach is suitable for asynchronous sequential circuits that are designed from flow tables or state transition diagrams. The proposed approach may also be useful for designing synchronous circuits, but explorations into the subject of clock power would be necessary to determine its usefulness.
Error Analysis of CORDIC-Based Jacobi Algorithms
Authors: Jürgen Götze, Steffen Paul, Matthias Sauer
Venue: IEEE Transactions on Computers (1995)

The Jacobi algorithm for eigenvalue calculation of symmetric matrices can be performed with a CORDIC algorithm as its basic module. Recently, a simplified Jacobi algorithm, by employing approximate rotations based on CORDIC rotations, was proposed. It fully exploits the binary data structure and reduces the overall computational cost significantly.In this paper an error analysis of the approximate CORDIC-based Jacobi algorithm and the conventional CORDIC-based Jacobi algorithm is performed. The new algorithm behaves numerically better than the conventional CORDIC-based Jacobi algorithm for fixed as well as floating point arithmetic.