ppxscal/embedding_network huggingface dataset:
A Class of Interconnection Networks for Multicasting
Authors: Yuanyuan Yang
Venue: Proceedings of the 10th International Parallel Processing Symposium (1996)

Multicast or one-to-many communications arise frequently in parallel computing applications and in other communication environments. Multicast networks can simultaneously support multiple multicast connections between the network inputs and network outputs. However, due to the much more complex communication patterns and routing control in multicast networks, there is still a considerably large gap in network cost between even the currently best known multicast networks and permutation networks. In this paper, we will present a class of interconnection networks which can support a substantial amount of well-defined multiple multicast connections in a nonblocking fashion and yet have a comparable low cost to permutation networks. We will also provide an efficient routing algorithm for satisfying multicast connection requests in such networks. Moreover, the multicast connecting capability of the networks will be represented as a function of fundamental network structural parameters so that the trade-off between the network multicast capability and the network cost can be determined. This enables different system designers to choose the multicast networks which fit in their particular application needs. By utilizing a network with well-defined multicast capability in a parallel computing system, software or algorithm designers of the system will be able to make full use of the multicast capability provided by the network, and substantial improvements in the performance of the system can be achieved due to significantly shortened delays in data transfer and simplified synchronization mechanisms for shared data. The ACM Portal is published by the Association for Computing Machinery. Copyright © 2010 ACM, Inc. Terms of Usage Privacy Policy Code of Ethics Contact Us Useful downloads: Adobe Acrobat QuickTime Windows Media Player Real Player
Hyperplane Partitioning: An Approach to Global Data Partitioning for Distributed Memory Machines
Authors: S. R. Prakash, Y. N. Srikant
Venue: Proceedings of the 13th International Symposium on Parallel Processing and the 10th Symposium on Parallel and Distributed Processing (1999)

Automatic Global Data Partitioning for Distributed Memory Machines (DMMs) is a difficult problem. Researchers have given varied solutions to this problem, most of which work for uniform dependences in loops and they suggest HPF-like distributions only. For non-uniform dependences, the loop was made to run sequentially. In this work, we present a partitioning strategy called 'Hyperplane Partitioning' which works well with such loops also. The technique also has been extended to complete programs, to do Global Data Partitioning with a tool to estimate communication cost at compile time. Space optimizations, uniform scheduling and message optimizations are also studied. The implementation of the scheme (on SP2) shows encouraging results when compared to standard HPF partitionings.
Decidable and Undecidable Fragments of First-Order Branching Temporal Logics
Authors: Ian M. Hodkinson, Frank Wolter, Michael Zakharyaschev
Venue: Proceedings of the 17th Annual IEEE Symposium on Logic in Computer Science (2002)

In this paper we analyze the decision problem for fragments of first-order extensions of branching time temporal logics such as computational tree logics CTL and CTL * or Prior's Ockhamist logic of historical necessity. On the one hand, we show that the one-variable fragments of logics like first-order CTL * ¿ such as the product of propositional CTL * with simple propositional modal logic S5, or even the one-variable bundled first-order temporal logic with sole temporal operator some time in the future' ¿ are undecidable. On the other hand, it is proved that by restricting applications of first-order quantifiers to state (i.e.,path-independent) formulas, and applications of temporal operators and path quantifiers to formulas with at most one free variable, we can obtain decidable fragments. The positive decidability results can serve as a unifying framework for devising expressive and effective time-dependent knowledge representation formalisms, e.g., temporal description or spatio-temporal logics.
Rule and Matroid Theory
Authors: Shusaku Tsumoto
Venue: Proceedings of the 26th International Computer Software and Applications Conference on Prolonging Software Life: Development and Redevelopment (2002)

In order to acquire knowledge from databases, there have been proposed several methods of inductive learning, such as decision tree and rule induction. These methods are applied to discover meaningful knowledge from large databases, which shows they are useful. However, since there has been no formal approach proposed to treat these methods, efficiency of each method is only compared empirically. In this paper, we introduce matroid theory and rough sets to construct a common framework for empirical machine learning methods which induce the combination of attribute-value pairs from databases. Combination of the concepts of rough sets and matroid theory gives us an excellent set-theoretical framework and enables us to understand the differences and the similarities between these methods from the viewpoint of partitions of the universe.
The Parameterized Complexity of Counting Problems
Authors: Jörg Flum, Martin Grohe
Venue: Proceedings of the 43rd Symposium on Foundations of Computer Science (2002)

We develop a parameterized complexity theory for counting problems. As the basis of this theory, we introduce a hierarchy of parameterized counting complexity classes #W[t], for t \geqslant 1 , that corresponds to Downey and Fellows's W-hierarchy [12] and show that a few central W-completeness results for decision problems translate to #W-completeness results for the corresponding counting problems.Counting complexity gets interesting with problems whose decision version is tractable, but whose counting version is hard. Our main result states that counting cycles and paths of length k in both directed and undirected graphs, parameterized by k , is#W[1]-complete. This makes it highly unlikely that any of these problems is fixed-parameter tractable, even though their decision versions are fixed-parameter tractable. More explicitly, our result shows that most likely there is no f(k) \cdot n^c-algorithm for counting cycles or paths of length k in a graph of size n for any computable function f: \mathbb{N} \to \mathbb{N} and constant c , even though there is a 2^{0(k)}\cdot n^{2.376}algorithm for finding a cycle or path of length k [2].
The parameterized Round-Robin partitioned algorithm for parallel external sort
Authors: Honesty C. Young, Arun N. Swami
Venue: Proceedings of the 9th International Symposium on Parallel Processing (1995)

In this paper, we present a new parameterized parallel sort algorithm, called Round-Robin Partitioned (or RRP), for the message passing (shared-nothing) architecture. This is a parameterized sort algorithm because a parameter is provided which can be used to determine the amount of memory used and to allocate differing amounts of work to different sets of sites. We utilize pipelining to hide disk I/O time, exploit high degrees of parallelism at all phases, apply sampling to determine the partition key values and use less memory than previous known methods while repairing the minimum number of physical I/Os. The basic version of the RRP algorithm is simple in terms of coding and complexity. It does not require disk I/O parallelism or data prefetch within a single process. We develop an analytical model for our algorithm and compare our sort algorithm with four other classes of external parallel sort algorithms. The RRP algorithm are shown to be superior to the other algorithms for almost all configurations.
Lazy Logging and Prefetch-Based Crash Recovery in Software Distributed Shared Memory Systems
Authors: Angkul Kongmunvattana, Nian-Feng Tzeng
Venue: Proceedings of the 13th International Symposium on Parallel Processing and the 10th Symposium on Parallel and Distributed Processing (1999)

In this paper, we propose a new, efficient logging protocol, called lazy logging, and a fast crash recovery protocol, called prefetch-based crash recovery (PCR), for software distributed shared memory (SDSM). Our lazy logging protocol minimizes failure-free overhead by logging only data indispensable for correct recovery, while our PCR protocol reduces the recovery time by prefetching data according to the future memory access patterns, thus eliminating memory miss penalty during the recovery process.We have performed experiments on workstation clusters, comparing our protocols against the earlier reduced-stable logging (RSL) protocol by actually implementing both protocols in TreadMarks, a state-of-the-art SDSM system. The experimental results show that our lazy logging protocol consistently outperforms the RSL protocol. Our protocol increases the execution time slightly by 1% to 4% during failure-free execution, while the RSL protocol results in the execution time overhead of 6% to 21% due to its larger log size and higher disk access frequency. Our PCR protocol also outperforms the widely used simple crash recovery protocol by 18% to 57% under all applications examined.
Design Methodologies for Tolerating Cell and Interconnect Faults in FPGAs
Authors: Fran Hancheck, Shantanu Dutt
Venue: Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors (1996)

Significant increases in chip yield can result if faulty logic cells and wiring in Field Programmable Gate Arrays (FPGAs) can be isolated from the remainder of the circuitry to retain a completely usable chip. Utilizing the principle of node-covering, a routing discipline has been developed that allows each logic cell in an FPGA to cover -- to be able to replace -- its neighbor in a row. An FPGA is factory-reconfigured such that a faulty cell is replaced by its cover, which in turn is replaced by its own cover, and so on until a spare cell in the row is reached. Since wiring channel area is a major portion of chip area in an FPGA, new techniques are also proposed for tolerating wiring faults. As with faulty logic cells, faulty wiring portions are replaced by adjacent ones, until eventually a spare wiring portion is reached. Compared to other techniques for fault tolerance in FPGAs, these methods are shown to provide significantly greater yield improvement.
Enhancing FSM Traversal by Temporary Re-Encoding
Authors: Gianpiero Cabodi, Luciano Lavagno, Enrico Macii, Massimo Poncino, Stefano Quer, Paolo Camurati, Ellen Sentovicha
Venue: Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors (1996)

Synthesis and optimization of large finite--state machines has improved dramatically over the last few years with the introduction and rapid improvement of symbolic--state manipulation techniques. The algorithms efficiently visit each reachable state in the machine while computing and storing information about these states. We propose a new technique for improving the efficacy of traversal algorithms: re-encoding the states of the machine to more efficiently represent state sets or state transitions, or to more efficiently compute the next set of states. Our technique can be embedded in existing traversal algorithms. Experiments reveal that re-encoding can indeed reduce the time and/or space required for traversal.
Considerations on the Application of Object-Oriented Reuse Technology to the Computer-Supported Cooperative Learning Domain
Authors: Karin Becker, Ana P. T. Bacelo Blois
Venue: Proceedings of the Seventh International Workshop on Groupware (2001)

Abstract: In the software engineering field, reuse is considered the key for achieving quality, reducing costs and increasing productivity. Such expectations motivate the proposition of generic, reusable solutions for the development of applications in various domains. In this paper, we address some initial considerations on the potentials of object-oriented (OO) reuse technology, particularly frameworks, in the Computer-supported cooperative learning (CSCL) domain. The paper discusses the striking aspects of such technology, the difficulties for defining expected functionality for CSCL applications, and describes some of the existing customizable solutions for the CSCL domain. Two of them, namely TOP and Habanero, are analyzed in more detail.
Integration of Domain-Specific Elements into Visual Language Based Collaborative Environments
Authors: Niels Pinkwart, Heinz Ulrich Hoppe, Katrin Gaßner
Venue: Proceedings of the Seventh International Workshop on Groupware (2001)

Abstract: This paper presents an approach for the integration of domain related elements and operational semantics into collaborative environments based on visual languages. This integration allows for supporting domain specific collaborative tasks, e.g. in the area of "collaborative discovery learning" in science education, by integrating data modelling with generic discussion support. A special focus is set on flexibility and parameterisation of the system which is achieved through providing the syntax definition of the visual language as a separate resource file.
JBOORET: an Automated Tool to Recover OO Design and Source Models
Authors: Hong Mei, Tao Xie, Fuqing Yang
Venue: Proceedings of the 25th International Computer Software and Applications Conference on Invigorating Software Development (2001)

This paper introduces a reverse engineering tool, JBOORET (Jade Bird Object-Oriented Reverse Engineering Tool). This tool is developed by adopting a parser-based approach to assist the activity of extracting the higher-level design and source models from system artifacts. A conceptual model is formulated as the knowledge representation. Multi-perspective design and source models are recovered by JBOORET based on the comprehensive program information extracted from source code. Its flexible user interface can assist users to browse the detailed information of design and source models by using the selection and compaction mechanism. This paper discusses the design principles and decisions of JBOORET and describes its implementation.
Virtual Reality Cultural Heritage Information Portal
Authors: Nicholas J. Webb, John P. Brotherhood
Venue: Proceedings of the 13th International Workshop on Database and Expert Systems Applications (2002)

VRCHIP (Virtual Reality Cultural and Heritage Information Portal) is a trial project implemented under the European Commission 5 th Framework Programme. The project aims to combine a virtual reality model of a small English town, stepped in history, with a databasecontaining information on the towns history and culture, to provide a new and stimulating way to carry out researchThe project is being carried out by NNC Ltd. and Cheshire County Council Libraries, with NNC creating the application and the libraries providing the historical information. The project aims to address the significant number of enquiries received by the local libraries for information about Knutsford and its history.The result of this project is an application which is deliverable across local networks and the Internet and which successfully provides access to a wealth of information through a dynamic virtual environment, representative of the town both past and present, providing an enriched research experience.
Hybrid Analytical-Statistical Modeling for Efficiently Exploring Architecture and Workload Design Spaces
Authors: Lieven Eeckhout, Koenraad De Bosschere
Venue: Proceedings of the 2001 International Conference on Parallel Architectures and Compilation Techniques (2001)

Abstract: Microprocessor design time and effort are getting impractical due to the huge number of simulations that need to be done to evaluate various processor configurations for various workloads. An early design stage methodology could be useful to efficiently cull huge design spaces to identify regions of interest to be further explored using more accurate simulations. In this paper, we present an early design stage method that bridges the gap between analytical and statistical modeling. The hybrid analytical-statistical method presented here is based on the observation that register traffic characteristics exhibit power law properties which allows us to fully characterize a workload with just a few parameters which is much more efficient than the collection of distributions that need to be specified in classical statistical modeling. We evaluate the applicability and the usefulness of this hybrid analytical-statistical modeling technique to efficiently and accurately cull huge architectural design spaces. In addition, we demonstrate that this hybrid analytical-statistical modeling technique can be used to explore the entire workload space by varying just a few workload parameters.
Interaction in Networked Virtual Environments as Communicative Action: Social Theory and Multi-Player Games
Authors: Tony Manninen
Venue: Proceedings of the 6th International Workshop on Groupware (2000)

The ambiguous and highly subjective meanings assigned to the word "interaction" makes it difficult for researchers and practitioners, who work in the area of virtual environments and applications, to communicate and join their research efforts. The aim of this work is to provide more understanding on the interaction occurring inside networked virtual environments (Net-VE) by analysing the communicative and social aspects of computer-mediated interaction in multi-player games. The work is conducted using conceptual analysis by applying communicative action theory as a scientific framework. The main contribution of this work is the proposed interaction taxonomy which is analysed in the light of social theory. The successful application of social theory framework as a tool to analyse interaction indicates the importance of joining the research effort of various disciplines in order to achieve better results in the area of Net-VE interactions.
Expressive Equivalence of Least and Inflationary Fixed-Point Logic
Authors: Stephan Kreutzer
Venue: Proceedings of the 17th Annual IEEE Symposium on Logic in Computer Science (2002)

We study the relationship between least and inflationary fixed-point logic. By results of Gurevich and Shelah from 1986, it has been known that on finite structures both logics have the same expressive power. On infinite structures however, the question whether there is a formula in IFP not equivalent to any LFP-formula was still open.In this paper, we settle the question by showing that both logics are equally expressive on arbitrary structures. The proof will also establish the strictness of the nesting-depth hierarchy for IFP on some infinite structures. Finally, we show that the alternation hierarchy for IFP collapses to the first level on all structures, i.e. the complement of an inflationary fixed-point is an inflationary fixed-point itself.
Effective Compilation Support for Variable Instruction Set Architecture
Authors: Jack Liu, Timothy Kong, Fred C. Chow
Venue: Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques (2002)

Traditional compilers perform their code generation tasks based on a fixed, pre-determined instruction set. This paper describes the implementation of a compiler that determines the best instruction set to use for a given program and generates efficient code sequence based on it. We first give an overview of the VISC Architecture pioneered at Cognigine that exemplifies a Variable Instruction Set Architecture. We then present three compilation techniques that, when combined, enable us to provide effective compilation and optimization support for such an architecture. The first technique involves the use of an abstract operation representation that enables the code generator to optimize towards the core architecture of the processor without committing to any specific instruction format. The second technique uses an enumeration approach to scheduling that yields near-optimal instruction schedules while stilladhering to the irregular constraints imposed by the architecture. We then derive the dictionary and the instruction output based on this schedule. The third technique superimposes dictionary re-use on the enumeration algorithm to provide trade-off between program performance and dictionary budget. This enables us to make maximal use of the dictionary space without exceeding its limit. Finally, we provide measurements to show the effectiveness of these techniques.
Software Asset Management and Domain Engineering
Authors: Satish Subramanian
Venue: Proceedings of the 21st International Computer Software and Applications Conference (1997)

Promoting reusability by managing software assets can greatly benefit companies that develop a family of similar products, where products are evolving from one another. One of the main goals of domain engineering is to identify and document the commonalties across the various products in a particular domain. Managing these common products or assets will keep the development cycle short for future products and help tame the large divergence seen in the development of different products. Guidant Corporation has been involved in the development of medical devices, such as cardiac rhythm management systems at CPI, which are complex real-time safety-critical systems. Cardiac rhythm management systems include implantable medical devices used to monitor human hearts and to provide appropriate therapy when needed [1, 2, 3]. These devices and related products are constantly evolving as technology and market needs change. The systems being developed at CPI are thus a family of products and share many functionalities among them. There are several issues that need to be addressed in the domain analysis of a family of products. The ACM Portal is published by the Association for Computing Machinery. Copyright © 2010 ACM, Inc. Terms of Usage Privacy Policy Code of Ethics Contact Us Useful downloads: Adobe Acrobat QuickTime Windows Media Player Real Player
Schemes for Reducing Communication Latency in Regular Computations on DSM Multiprocessors
Authors: Masaru Takesue
Venue: Proceedings of the 1998 International Conference on Parallel Processing (1998)

This paper proposes two schemes for reducing the communication latency in the computations with local and regular communication patterns. The primary scheme is the local protocol for enhancing spatial locality of the coherence actions, and the second is for the communication via stream data. The local protocol is a subsidiary of a traditional coherence protocol and activated on a memory-block basis. If activated on a memory block, the domain of coherence actions is confined into the caches that are currently sharing that block. Otherwise, the domain involves the memory as well as those caches. It is easy to efficiently communicate via stream data in the local coherence domain. Our experimental results show that one of the three proposed local protocols, the tampering protocol, significantly improves the performance as compared with the conventional protocol. The communication via stream data contributes to a further performance improvement.