Proceedings of the 2002 international workshop on System-level interconnect prediction
Venue: International Workshop on System-Level Interconnect Prediction (2002)

It is well-known that complex integrated wire systems consisting of signal, power, and clock distribution will place significant limits on performance, power dissipation, design complexity, and manufacturing cost of billion transistor systems. It is the assumption of this workshop that sophisticated system-level models for wire connectivity, demand, noise, and delay are needed to predict and optimize computer architectures, physical designs, and implementation technologies in order to maintain the exponential improvements in integration density, clock frequency, and cost per function as projected by the International Technology Roadmap for Semiconductor (ITRS).Wiring systems of complex digital circuits have certain collective properties that can be predicted with a minimal set of parameters. An engineer at IBM in the 1960's took only a few weeks to catalog data and observe that a power law relationship exists between the number of input/output pins and the number of basic circuit elements in digital systems. These rentian properties of netlists have been investigated and extended over the past thirty years -- presentations at this workshop reveal the latest discoveries for both rentian and non-rentian properties of complex wiring systems.Due to non-localized inductive coupling in multilevel wiring stacks, the collective electromagnetic properties of signal, power, and clock distribution must, in part, be considered at the system-level. The complex behavior of signal transients in IC wiring systems is exacerbated by the lack of smooth ground planes in a multilevel wiring stack and the emergence of multi-gigahertz clock frequencies. Part of the agenda of this workshop is to provide physical insight into the impact that inductance will have on multilevel wire systems over the next fifteen years.Primary applications of SLIP theory include early architectural planning, advanced interconnect timing analysis, FPGA architecture design, synthetic benchmark circuit generation, advanced placement and routing congestion metrics, a priori multilevel wire sizing and repeater insertion estimation, enhanced technology roadmap planning (e.g. low k-dielectrics, 3-D integration, integrated photonics, etc.), and early yield analysis. Over the years, system level simulators such as SUSPENS (Stanford), RIPE (RPI), BACPAC (Berkeley), GENESYS (Georgia Tech), and GTX (UCLA), have been developed to help estimate clock frequency, IPC, dynamic and static power dissipation, die size, number of required metal levels, and yield estimates for future VLSI systems. This year the workshop will discuss opportunities to enhance cycle time estimation, wire net length models, noise distribution predictions, and multilevel wiring network design, which are at the core of these comprehensive simulators.The program committee has chosen the content of SLIP2002 to provide a workshop with both tutorial information and cutting edge research in system-level interconnect prediction. We feel that this two day workshop will provide an exciting forum to help advance the field of system-level interconnect prediction so that its applications to the design of billion transistor systems can be rapidly developed.