ppxscal/embedding_network huggingface dataset:
Logic simulation system using simulation processor (SP)
Authors: Minoru Saitoh, Kenji Iwata, Akiko Nokamura, Makoto Kakegawa, Junichi Masuda, Hirofumi Hamamura, Fumiyasu Hirose, Nobuaki Kawato
Venue: Proceedings of the 25th ACM/IEEE Design Automation Conference (1988)

This paper describes a (special-purpose) logic simulation processor (SP) and a software system for the SP for use in verifying the design of computers and other logic devices. Our system can evaluate a logic circuit containing 4 million logic primitives and 32M bytes of memory at a maximum speed of 800 million active primitive evaluations per second. This paper outlines the hardware architecture, then discusses a software system that optimizes hardware performance. It presents the results of system use and evaluates the system.
Imperative streams&mdash;a monadic combinator library for synchronous programming
Authors: Enno Scholz
Venue: Proceedings of the third ACM SIGPLAN international conference on Functional programming (1998)

The paper presents a generalization of Haskell's IO monad suitable for synchronous concurrent programming. The new monad integrates the deterministic concurrency paradigm of synchronous programming with the powerful abstraction features of functional languages and with full support for imperative programming. For event-driven applications, it offers an alternative to the use of existing, thread-based concurrency extensions of functional languages. The concepts presented have been applied in practice in a framework for programming interactive graphics.
A digit-serial silicon compiler
Authors: Richard I. Hartley, Peter F. Corbett
Venue: Proceedings of the 25th ACM/IEEE Design Automation Conference (1988)

A new silicon compiler is described, called PARSIFAL (not an acronym). It constructs chips with a data flow architecture in which data is passed in a digit-wide pipeline from one computational element to the next. The size of a digit may be specified by the user to be any value between one and the full word size of the chip. A digit size of one gives bit-serial chips whereas a digit-size equal to the word-size gives fully parallel computation. It is shown that an intermediate value of digit-size usually gives the most efficient chips in terms of throughput per unit area.
The evolution of standards for accrediting computer science teacher preparation programs
Authors: Harriet Taylor
Venue: Proceedings of the twenty-eighth SIGCSE technical symposium on Computer science education (1997)

In 1992, the National Council for the Accreditation of Teacher Education (NCATE) adopted guidelines for computer science education teacher preparation programs. The endorsement signaled the emergence of computer science education as a distinct discipline and computer science as a formal secondary subject area. The guidelines were developed through an intense program of research and review by the International Society for Technology and Education (ISTE). Since the passage of the standards, numerous computer science and education professionals have been involved in the process of preparing program folios for review and developing the actual review process. This real experience with the standards helped to identify issues and problems that are common to most programs and that need examination in the current five year review. In this paper, an overview of the guidelines is presented, the review process is described, issues and problems are discussed, and future initiatives are identified.
Challenges in CAD for the one million gate FPGA
Authors: Kurt Keutzer
Venue: Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays (1997)

FPGA and CPLD densities have typically lagged their gate-array and standard-cell counterparts in effective density by a factor of 10. This means that the design problems encountered by ASIC designers will typically be encountered by FPGA designers 5-6 years later and tools used in the ASIC market to address them will ultimately be adopted by FPGA designers. Thus anyone familiar with the evolution of ASIC design tools can amaze and impress their FPGA-focussed friends with their ability to predict the future of FPGA design tools. In this short abstract we will outline the probable evolution of FPGA devices as they grow to one million gate-equivalents and then will chart the evolution of FPGA tool needs as they grow to meet the challenges of the million gate FPGA.
On the complexity of set-based analysis
Authors: Nevin Heintze, David McAllester
Venue: Proceedings of the second ACM SIGPLAN international conference on Functional programming (1997)

We define a general notion of set-based analysis --- any language whose operational semantics is defined by environment evaluation has a well defined set-based abstraction. This general definition covers both Aiken and Wimmers' type system and Heintze' set-based analysis. Aiken and Wimmers give a nondeterministic exponential time algorithm for their analysis. Heintze gives an O(n3) procedure. We show that this discrepancy is due to the complexity of the case statements analyzed. For polymorphic programs with deep patterns in case statements (as in the Aiken-Wimmers language) we show that the problem of determining type-safety under set-based abstraction is complete for deterministic exponential time. The problem remains complete for deterministic exponential time for programs without let (monovariant programs). However, for monovariant programs in which all patterns in case statements are shallow, as in the Heintze language, type-safety under set-based abstraction is decidable in cubic time. We give five additional theorems which (nearly exhaustively) characterize the time complexity of set-based analysis as a function of the complexity of case statements.
Control Strategies for the Iterative Solution of Nonlinear Equations in ODE Solvers
Authors: Kjell Gustafsson, Gustaf Söderlind
Venue: SIAM Journal on Scientific Computing (1997)

In the numerical solution of ODEs by implicit time-stepping methods, a system of (nonlinear) equations has to be solved each step. It is common practice to use fixed-point iterations or, in the stiff case, some modified Newton iteration. The convergence rate of such methods depends on the stepsize. Similarly, a stepsize change may force a refactorization of the iteration matrix in the Newton solver. This paper develops new strategies for handling the iterative solution of nonlinear equations in ODE solvers. These include automatic switching between fixed-point and Newton iterations, investigating the "optimal" convergence rate with respect to total work per unit step, a strategy for when to reevaluate the Jacobian, a strategy for when to refactorize the iteration matrix, coordination with stepsize control. Examples will be given, showing that the new overall strategy works efficiently. In particular, the new strategy admits a restrained stepsize variation without refactorizations, thus permitting the use of a smoother stepsize sequence. The strategy is of equal importance for Runge--Kutta and multistep methods.
The locker metaphor to teach dynamic memory
Authors: Richardo Jiménez-Peris, Cristóbal Pareja-Flores, Marta Patiño-Martínez, J. Ángel Velázquez-Iturbide
Venue: ACM SIGCSE Bulletin (1997)

Some students experience difficulties when first introduced to dynamic memory. The goal of this paper is to present an analogy between dynamic memory programming and a real-world example that will help students in understanding the underlying concepts behind dynamic memory: a left-luggage room with lockers.
On Translation Invariant Subspaces and Critically SampledWavelet Transforms
Authors: Steven A. Benno, José M. F. Moura
Venue: Multidimensional Systems and Signal Processing (1997)

The discrete wavelet transform (DWT) is attractive for many reasons. Its sparse sampling grid eliminates redundancy and is very efficient. Its localized basis functions are well suited for processing non&ndash;stationary signals such as transients. On the other hand, its lack of translation invariance is a major pitfall for applications such as radar and sonar, particularly in a multipath environment where numerous signal components arrive with arbitrary delays. The paper proposes the use of robust representations as a solution to the translation invariance problem. We measure robustness in terms of a mean square error for which we derive an expression that describes this translation error in the Zak domain. We develop an iterative algorithm in the Zak domain for designing increasingly robust representations. The result is an approach for generating multiresolution subspaces that retain most of their coefficient energy as the input signal is shifted. A typical robust subspace retains 98\% of its energy, a significant improvement over more traditional wavelet representations.
Strategies for effective integration of software engineering concepts and techniques into the undergraduate computer science curriculum
Authors: Ursula Jackson, Bill Z. Manaris, Renée A. McCauley
Venue: ACM SIGCSE Bulletin (1997)

This paper discusses various strategies for introducing and reinforcing software engineering principles in the undergraduate Computer Science curriculum. These strategies are based on a set of standards for internal/external documentation and organization of software which may be implemented quickly and inexpensively without a complete overhaul of courses. This provides a flexible framework for the development of a wide variety of carefully-planned programming assignments/projects.
A computer aided design automation system for developing microprogrammed processors: a design approach through HDLs
Authors: W. J. Chen, G. N. Reddy
Venue: Proceedings of the 20th annual workshop on Microprogramming (1987)

This paper presents an approach that provides a total computer aided design environment for developing microprogrammed processors using hardware description languages. This includes the behavioral description, micro-coding, and testing of the integrated microprogrammed processors. To illustrate the design procedure a functionally equivalent micro-coded version of the Motorola's MC6809 processor was modeled, and tested. The results indicate that it is a valid design approach. The micro control unit described through the hardware description language AHPL not only replaces the required microprogram simulator but also emulates its exact hardware. Here the micro control unit and the microcode are emulated and tested as a unit; in much the same way a real processor's micro control unit functions with its stored microcode. The emulated micro-simulator here is used for verifying the MC6809 microcode. It can, however, be used as a general purpose testbed for testing any microcode. The design procedure presented here is for the MC6809 microprogrammed processor, however, the procedure can be used to design any processor with user defined instruction set.
Simulation-based learning tool for facilities design
Authors: Bala Ram, Rajiv Girdhar
Venue: Proceedings of the 28th conference on Winter simulation (1996)

This paper describes a tool, LAYSIM, to emphasize to the students the important role of material handling cost in choosing the type of layout; i.e., Product, Jobshop or Group Technology-based layout for a certain set of products. It addresses how through experimentation with LAYSIM students understand and appreciate the manufacturing costs associated with each type of layout. The paper describes the underlying learning model, development of the LAYSIM, the features of LAYSIM and the proposed dissemination technique.
Codes with a Disparity Property
Authors: Stephanie Perkins
Venue: Designs, Codes and Cryptography (1997)

Kth order zero disparity codes have been considered in several recent papers. In the first part of this paper we remove the zero disparity condition and consider the larger class of codes, Kth order disparity D codes. We establish properties of disparity D codes showing that they have many of the properties of zero disparity codes. We give existence criteria for them, and discuss how new codewords may be formed from ones already known. We then discuss Kth order disparity D codes that have the same number of codewords. We discuss the minimum distance properties of these new codes and present a decoding algorithm for them. In the second part of the paper we look at how the minimum distance of disparity D codes can be improved. We consider subsets of a very specialised subclass, namely first order zero disparity codes over alphabet Aq of size q. These particular subsets have q codewords of length n and minimum Hamming distance n. We show that such a subset exists when q is even and nis a multiple of 4, and also when q is odd and n is even. These subsets have the best error correction capabilities of any subset of q first order zero disparity codewords.
PRIMA: passive reduced-order interconnect macromodeling algorithm
Authors: Altan Odabasioglu, Mustafa Celik, Lawrence T. Pileggi
Venue: Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design (1997)

This paper describes PRIMA, an algorithm for generating provably passive reduced order N-port models for RLC interconnect circuits. It is demonstrated that, in addition to requiring macromodel stability, macromodel passivity is needed to guarantee the overall circuit stability once the active and passive driver/load models are connected. PRIMA extends the block Arnoldi technique to include guaranteed passivity. Moreover, it is empirically observed that the accuracy is superior to existing block Arnoldi methods. While the same passivity extension is not possible for MPVL, we observed comparable accuracy in the frequency domain for all examples considered. Additionally a path tracing algorithm is used to calculate the reduced order macromodel with the utmost efficiency for generalized RLC interconnects.
Modeling disease processes for drug development: bridging the gap between quantitative and heuristic models
Authors: Pamela K. Fink, L. Tandy Herren
Venue: Proceedings of the 28th conference on Winter simulation (1996)

Drug development is a complex and extremely risky process. It involves developing knowledge of the relevant biology at a variety of levels of detail in order to piece together a coherent model of the disease process and the potential point(s) of intervention. Ultimately, this model must be complete enough to support the prediction of effects and the explanation of clinical trial results. Unfortunately, such models of a disease process have been primarily developed and maintained in human minds. Consequently, such models are limited by a human's ability to store all of the needed information, structure it properly, and reason about its consequences involving both complex feedback and time dependencies. The following paper describes a knowledge-centered approach to the development of biological models that support the drug development process. This technique focuses on a multi-level, hierarchical approach that models various levels of the related biology using appropriate representation techniques based on both the type and availability of the knowledge.
A High-Order Godunov-Type Scheme for Shock Interactions in Ideal Magnetohydrodynamics
Authors: Wenlong Dai, Paul R. Woodward
Venue: SIAM Journal on Scientific Computing (1997)

A high-order Godunov-type scheme is developed for the shock interactions in ideal magnetohydrodynamics (MHD). The scheme is based on a nonlinear Riemann solver and follows the basic procedure in the piecewise parabolic method. The scheme takes into account all the discontinuities in ideal MHD and is in a strict conservation form. The scheme is applied to numerical examples, which include shock-tube problems in ideal MHD and various interactions between strong MHD shocks. All the waves involved in the corresponding Riemann problems are resolved and are correctly displayed in the simulation results. The correctness of the scheme is shown by the comparison between the simulation results and the solutions of the Riemann problems. The robustness of the scheme is demonstrated through the numerical examples. It is shown that the scheme offers the principle advantages of a high-order Godunov-type scheme: robust operation in the presence of very strong waves, thin shock fronts, and thin contact and slip surface discontinuities.
Code placement techniques for cache miss rate reduction
Authors: Hiroyuki Tomiyama, Hiroto Yasuura
Venue: ACM Transactions on Design Automation of Electronic Systems (TODAES) (1997)

In the design of embedded systems with cache memories, it is important to minimize the cache miss rates to reduce power consumption of the systems as well as improve the performance. In this article, we propose two code placement methods ( a simplified method and a refined one) to reduce miss rates of instruction caches. We first define a simplified code placement problem without an attempt to minimize the code size. The problem is formulated as an integer linear programming (ILP) problem, by which an optimal placement can be found. Experimental results show that the simplified method reduces cache misses by an average of 30% (max. 77%). However, the code size obtained by the simplified method tends to be large, which inevitably leads to a larger memory size. In order to overcome this limitation, we further propose a refined code placement method in which the code size provided by the system designers must be satisfied. The effectiveness of the refined method is also demonstrated.
Cross-Correlations of Quadratic Form Sequences in OddCharacteristic
Authors: A. Klapper
Venue: Designs, Codes and Cryptography (1997)

Cross-correlation functions are determined for a large class of geometric sequences based on m-sequences in odd characteristic. These sequences are shown to have low cross-correlation values in certain cases. They also have significantly higher linear spans than previously studied geometric sequences. These results show that geometric sequences are candidates for use in spread-spectrum communications systems in which cryptographic security is a factor.
Typed cross-module compilation
Authors: Zhong Shao
Venue: Proceedings of the third ACM SIGPLAN international conference on Functional programming (1998)

Higher-order modules are very effective in structuring large programs and defining generic, reusable software components. Unfortunately, many compilation techniques for the core languages do not work across the module boundaries. As a result, few optimizing compilers support these module facilities well.This paper exploits the semantic property of ML-style modules to support efficient cross-module compilation. More specifically, we present a type-directed translation of the MacQueen-Tofte higher-order modules into a predicative variant of the polymorphic lambda;-calculus F omega;. Because modules can be compiled in the same way as ordinary polymorphic functions, standard type-based optimizations such as representation analysis immediately carry over to the module languages.We further show that the full-transparency property of the MacQueen-Tofte system yields a near optimal cross-module compilation framework. By propagating various static information through the module boundaries, many static program analyses for the core languages can be extended to work across higher-order modules.
Steiner 2-Edge Connected Subgraph Polytopes on Series-Parallel Graphs
Authors: Mourad Baïou, Ali Ridha Mahjoub
Venue: SIAM Journal on Discrete Mathematics (1997)

Given a graph G=(V,E) with weights on its edges and a set of specified nodes $S\subseteq V$, the Steiner 2-edge survivable network problem is to find a minimum weight subgraph of G such that between every two nodes of S there are at least two edge-disjoint paths. This problem has applications to the design of reliable communication and transportation networks. In this paper, we give a complete linear description of the polytope associated with the solutions to this problem when the underlying graph is series-parallel. We also discuss related polyhedra.
Finite-Dimensional Filters. Part I: The Wei--Norman Technique
Authors: M. Cohende Lara
Venue: SIAM Journal on Control and Optimization (1997)

This two-part paper deals with necessary or sufficient conditions for the existence of finite-dimensional filters. In this first part, we set the problem and propose a construction of such filters by the Wei--Norman technique. After having formulated the problem of finite-dimensional filters in terms of finite-dimensional realizations of input-output mappings, we specify the dependence with respect to the initial measure. We show how different notions of dependence imply different properties of the so-called estimation algebra $\cal E$: $\cal E$ is homomorphic to a Lie algebra of vector fields; $\cal E$ contains only operators of order less than or equal to two; $\cal E$ is finite dimensional and contains only operators of order less than or equal to two. These results depend on a precise definition of a finite-dimensional realization, especially on what concerns the domain of the output function. The last (and most stringent) condition on ${\cal E}$ will be shown to be almost sufficient to recover a family of finite-dimensional realizations thanks to the proof of a Baker--Campbell--Hausdorff formula which allows us to apply the Wei--Norman technique in a quite general setting.
A method of delay fault test generation
Authors: C. Thomas Glover, M. Ray Mercer
Venue: Proceedings of the 25th ACM/IEEE Design Automation Conference (1988)

It has been observed that random testing for delay faults can result in test sets of excessive length and high simulation costs. Consequently, we propose an efficient deterministic method of delay fault test generation. For most common circuits, our proposed technique has a time complexity which is polynomial in the size of the circuit, as opposed to existing deterministic methods which, for nearly all circuits, are exponential. We define a type of transition path, the fully transitional path, FTP, and demonstrate that it has several useful properties. An FTP can be created by applying a vector pair derived from a stuck-at test for a primary input, a technique introduced in [1]. We extend this method by using an alternate representation for switching functions, the binary decision diagram, to generate graphs representing stuck-at tests. The concept of free variables is defined as a tool for deriving several FTPs from one stuck-at test. Preliminary results are presented which indicate that our method provides a higher robust delay fault coverage than psuedorandom patterns at less than one-fifth the cost. Also, since vector pairs cannot be applied to combinational circuits using standard scan design, a simple scannable latch is introduced to facilitate this task.