ppxscal/embedding_network huggingface dataset:
Maintaining credibility in user education
Authors: Lois J. Secrist
Venue: Proceedings of the 5th annual ACM SIGUCCS conference on User services (1977)

Credibility in user education? Yes, it's an essential element in developing user education programs&mdash;and aren't we muffing it? Unless we see the level of sophistication in computer usage rising at our computer centers; unless we have good attendance and good evaluations at our workshops and short courses; unless user requirements for specialty consulting assistance stay at reasonable levels&mdash;we are in trouble!
Digital network design aids - an integrated approach
Authors: Edward K. Bowdon,  Sr.
Venue: Proceedings of the 7th Design Automation Workshop (1970)

The extension of human capabilities in procedural tasks by use of computer processing is well established. Significant effort has been expended within the past decade to apply this processing capability to the tasks within engineering design.1 This paper describes the integrated approach adopted by Collins Radio Company in the development and application of computer aids to the design of digital networks. The digital networks include those networks, systems, or circuits which exhibit discrete logic states and have waveforms that may be assumed idealized with zero rise and fall times. The design aids include simulation, production test generation, and layout. The simulation algorithms provide design verification, computation of production test input/output data, trade-off analysis and timing and loading analysis. The test generation algorithms determine a set of inputs to a unit and the associated outputs for these inputs which can be used for production test of the unit. The layout algorithms provide parts placement, partitioning, pin assignment and interconnect solutions for physical implementation of the circuitry. The simulation, test generation and layout algorithms operate on a common set of data which is inputted to the processor system by the designer. This set of data is added to as simulation, test generation and layout are completed. The resultant evolved set can then comprise a functional specification of the unit.
Adaptive library documentation for APL
Authors: Naomi Kleid, Gerald M. Weinberg
Venue: Proceedings of the eighth international conference on APL (1976)

For many years, to many people, &ldquo;APL&rdquo; has meant &ldquo;A Personal Language&rdquo; &mdash; a superior tool for an individual working on problems arising out of his own work. But success breeds expansion, and successful APL users have naturally tried to spread the word. Now, APL application has been broadened to include &ldquo;non-personal&rdquo; uses too. While personal uses of an APL system place few demands on documentation &mdash; most of what is needed can be kept in the user's head, supplemented by a few clues in the workspace and program &mdash; what is adequate for personal use becomes inadequate and finally detrimental for public use. Thus, when it comes to documentation, APL is in the same boat as other languages &mdash; but this is not a familiar place for APL to be. APL users have come to expect a freshness and innovation in their APL systems, but at present these attributes are conspicuously absent in APL support for documentation. This paper proposes an adaptive documentation system which, although not limited in concept to APL systems, is the kind of innovation most likely to find quick implementation and acceptance in the APL community.
An automatic system approach to the problem of memory circuit testing fault diagnosis
Authors: Peter S. Bottorff, Mitchel E. Schwass, Francis J. Villante
Venue: Proceedings of the 7th Design Automation Workshop (1970)

High product volume, diverse packaging configurations, and high-speed functional operation make memory circuit testing a difficult manufacturing problem. One solution to this problem is provided by the computer-controlled test system described here. Modular design of hardware, microprogram, and programming subsystems has met production requirements for speed, quality, and repair of assembly defects.
Computer modules - an architecture for a modular multi-microprocessor
Authors: S. Fuller, D. Siewiorek, R. Swan
Venue: Proceedings of the 1975 annual conference (1975)

Computer Modules are microcomputer based modules which can be interconnected to form large multiprocessor systems. This paper briefly discusses some of the major design considerations and presents an outline of the current Computer Module design.
Simulated execution of dataflow programs on processors having finite resources
Authors: David D. Langan, Bruce D. Shriver
Venue: Proceedings of the 1979 ACM SIGMETRICS conference on Simulation, measurement and modeling of computer systems (1979)

Dataflow languages and processors are currently being extensively studied because they provide for the specification and realization of processes exhibiting a high degree of parallel and/or asynchronous activity [12, 8]. Several researchers have developed simulators for specific candidate dataflow architectures in which there are essentially an infinite number of resources available to the nost machine [9, 1]. This is done to study the degree of parallelism which is achievable with a given version of an algorithm. However, it is an equally important (and neglected) area to study the behavior of programs executing in candidate computer systems having a finite amount of resources. This paper presents results which have been obtained from such modeling. It is shown that in such a system certain &ldquo;critical nodes&rdquo; must be given priority of execution when competing with other nodes for the same resources in order to achieve the maximum system throughput. It is suggested that the abstract dataflow model be modified to accommodate such situations. Various design trade-offs associated with the implementation of the simulator are discussed along with a description of available features. A companion paper [6] describes the general dataflow simulation facility which provided the basis of this work.
Why a ring?
Authors: Jerome H. Saltzer, David D. Clark, Kenneth T. Pogran
Venue: Proceedings of the seventh symposium on Data communications (1981)

In a world increasingly populated with Ethernets and Ethernet-like nets a few sites continue to experiment with rings of active repeaters for local data communication. This paper explores some of the engineering problems involved in designing a ring that has no central control, and then compared the M.I.T.-designed ring with Ethernet on a variety of operational and subtle technical grounds, on each of which the ring may possess important or interesting advantages.
Are current approaches sufficient for measuring software quality?
Authors: John B. Bowen
Venue: ACM SIGSOFT Software Engineering Notes (1978)

Numerous software quality studies have been performed over the past three years-mostly sponsored by the Rome Air Development Center. It is proposed by the author that more emphasis should be placed on devising and validating quantitative metrics that are indicative of the quality of software when it is being designed and coded. Such measures could be applied effectively, as relative guidelines without formal validation. However for such measures to be predictive of the quality of the delivered software, they must be validated with actual operational error data or data gathered in a simulated operational environment. This paper includes a review of proposed metrics from the literature a report of a Hughes intramodule metric study, and recommendations for refining proposed software quality assurance criteria.
A comparative study of the k nearest neighbour, threshold and neural network classifiers for handwritten signature verification using an enhanced directional PDF
Authors: J.-P. Drouhard, R. Sabourin, M. Godbout
Venue: Proceedings of the Third International Conference on Document Analysis and Recognition (Volume 2) - Volume 2 (1995)

A neural network approach is proposed to build the first stage of an automatic handwritten signature verification system that will eliminate random and simple forgeries rapidly. The directional probability density function was used as a global shape factor, and its discriminatory power was enhanced by reducing its cardinality. The choice of the best pretreatment was made by means of a k nearest neighbour classifier. This study has shown that the cardinality of the PDF can be reduced by a factor of ten while doubling its discriminatory power. The backpropagation model was retained to build the neural network classifier. An experimental protocol was used to find the best configuration of the BPN classifier whose performance was compared on the same database and with the same decision rule (without rejection criteria), to those of the kNN and threshold classifiers. This comparison shows that the BPN classifier is clearly better than the T classifier, and compares favourably with the kNN classifier.
APL in operating systems research
Authors: Greg Johnson
Venue: ACM SIGAPL APL Quote Quad (1981)

This paper will discuss three extensions to APL which will improve its usefulness for research in operating systems and systems programming. They are the introduction of processor variables, encased and bound statement fragments, and pointer or referent variables. APL has demonstrated capabilities in free-wheeling research environments. In an experimental operating system written in APL, much superfluous detail would be suppressed, and the essentials of various algorithms used would be brought to the fore.
The computation of connected regions in interactive graphics
Authors: Janice R. Lourie
Venue: Proceedings of the 1969 24th national conference (1969)

This paper addresses the problem of automatically identifying and labeling the connected regions formed by sets of closed curves. This is a general problem encountered in interactive computer graphics, where an arbitrary pattern is transmitted via a digitizing device such as a data tablet and a stylus, or CRT and light pen. Area calculations for these connected regions are also briefly discussed. Two programmed algorithms are presented which accomplish these functions. The first operates on a completed pattern and is most efficiently applied to small patterns. The second is a dynamic generalization of the first. It permits segmentation of the original pattern and does identification and labeling of connected regions of any part of the pattern. It also permits modification of isolated parts of the pattern and accomplishes the necessary reidentification and relabeling. It is applicable to patterns which are many times the size of the original data tablet or screen. The paper also presents a specific application of this generalized algorithm to a problem requiring dynamic data handling.
Data abstraction, controlled iteration, and communicating processes
Authors: Alfs T. Berztiss
Venue: Proceedings of the ACM 1980 annual conference (1980)

Iterators provide access to elements of an abstract structured object in some sequence. It is argued that parallel composition of iterators should be achieved implicitly by means of a generalized for loop rather than by use of mutually interacting coroutines. The generalized for loop employs controlled iteration, which is shown to be a powerful yet inexpensive construct. The generalized for loop is consistent with block structure, and, for program proof purposes, is much more tractable than an unrestricted loop. Concrete programming examples are used extensively.
Time flow mechanisms for use in digital logic simulation
Authors: Stephen A. Szygenda, Cliff W. Hemming, John M. Hemphill
Venue: Proceedings of the 5th conference on Winter simulation (1971)

Implementation of a system for the simulation of the time domain operation of a deterministic digital logic net involves consideration of problems different from those encountered simulation of the time domain operation of a stochastic system. Examination of two different simulation time flow mechanisms illustrates how each technique may be applied to the simulation of logic nets. The design goals for a general purpose logic simulator are examined and the implementation techniques used in TEGAS2 are illustrated.
Design of a Lisp machine - FLATS
Authors: E. Goto, T. Soma, N. Inada, T. Ida, M. Idesawa, K. Hiraki, M. Suzuki, K. Shimizu, B. Philipov
Venue: Proceedings of the 1982 ACM symposium on LISP and functional programming (1982)

Design of a 10 MIPS Lisp machine used for symbolic algebra is presented. Besides incorporating the hardware mechanisms which greatly speed up primitive Lisp operations, the machine is equipped with parallel hashing hardware for content addressed associative tabulation and a very fast multiplier for speeding up both arithmetic operations and fast hash address generation.
Restart and recovery in a transaction-oriented information processing system
Authors: Hasan H. Sayani
Venue: Proceedings of the 1974 ACM SIGFIDET (now SIGMOD) workshop on Data description, access and control (1974)

We identify the performance aspects of restart and recovery. We present a model describing the relationships between the errors in information processing systems, the procedures needed to recover from the errors and the actions necessary to make the recovery procedures feasible. We define restart and recovery policies and discuss some of the important criteria that may be used to evaluate these policies. We present some results obtained by the application of a particular objective function and show the feasibility of marginal cost analysis that can be made by an operations manager.
A new test pattern generation system
Authors: Yacoub M. El-ziq
Venue: Proceedings of the 17th Design Automation Conference (1980)

This paper discusses the main shortcomings of existing software test pattern generation systems and describes the development of a new system. The new system will be developed in two phases. The first phase is called the scan-in/scan-out test generation sub-system. This sub-system will be used for testing designs which have 100% scan-in/scan-out (reading or writing of every register from external world is possible). The second phase will include the development of efficient general functional models. The test generation system to be developed in the first phase will be updated to incorporate the capability of handling such models. The functional models include general-combinational, register, counter, ROM, RAM, and microprocessor. In this paper, only, an outline of some of the distinct features of the system will be described.
Edge Inference with Applications to Antialiasing
Authors: Jules Bloomenthal
Venue: ACM SIGGRAPH Computer Graphics (1983)

An edge, when point-sampled for display by a raster device and not aligned with a display axis, appears as a stair-case.This common aliasing artifact often occurs in computer images generated by two- and three-dimensional algorithms. The precise edge information often is no longer available but, from the set of vertical and horizontal segments which form the staircase, an approximation to the original edge with a precision beyond that of the raster may be inferred. This constitutes a smoothing of the staircase edge. Among other applications, the inferred edges may be used to reshade the pixels they intersect, thereby antialiasing the inferred edges. The antialiased inferred edges prove a more attractive approximation to the real edges than their aliased counterparts. Presented here are algorithms for the detection and smoothing of edges and the filtering of an image in accordance with the inferred edges.
Gate array layout automation: A tutorial
Authors: Robert J. Smith
Venue: Proceedings of the ACM '81 conference (1981)

Gate array layout is becoming an increasingly important topic in design automation, as utilization of these components expands. In this tutorial a model of gate array physical design is first presented, introducing nomenclature used thereafter. The architecture of a typical gate array layout system is briefly discussed, establishing the environmental setting for more detailed examination of placement and routing techniques. The placement problem is next defined, along with evaluation metrics and practical considerations related to placement. Constructive initial placement techniques based on cluster growth and mincut algorithms are next presented in some detail. Iterative improvement algorithms based on pairwise exchange, force-relaxation and unconnected set relocation are then presented. Coverage of gate array placement concludes with a comparison of results achieved with these methods, a brief exploration of the proper role of graphics placement, and enumeration of some promising topics for research in placement.
An experimental input system of hand-drawn logic circuit diagram for LSI CAD
Authors: Mitsuo Ishii, Masanari Yamamoto, Michiko Iwasaki, Hiroshi Shiraishi
Venue: Proceedings of the 16th Design Automation Conference (1979)

This paper outlines a computer input system that reads hand-drawn LSI logic circuit diagrams. The system discriminates between connection lines and gate symbols and identifies the gate type. The input device can read diagrams drawn on sheets of paper up to size A2 (40 &times; 55 cm). Simple algorithms for discriminating between connection lines and gate symbols are also presented. These algorithms enable rapid processing of input data because there is no preliminary processing such as thinning or smoothing of lines. A performance test was made using a circuit diagram drawn on a size A4 (18 &times; 25 cm) sheet of paper. The results show that the input device can be put into practical use and, when combined with an interactive graphic system, can contribute to more efficient LSI circuit design.
A modular memory scheme for array processing
Authors: S. R. Ahuja, J. R. Jump
Venue: ACM SIGARCH Computer Architecture News (1977)

This paper presents a parallel memory scheme suited for pipelined processing units. The scheme is shown to be modular, relatively low cost and flexible. The scheme allows an arbitrary number of variables in the vector operations. It is shown that data alignment is handled by a simple interconnection scheme and that the interconnection scheme can be implemented in the memory modules. It is shown that the scheme facilitates efficient implementation of the Perfect Shuffle interconnection, hence the implementation of parallel algorithms using that interconnection scheme.
Simulation analysis of an emergency care facility
Authors: E. C. Garcia, W. F. Hamilton, J. W. Thomas
Venue: Proceedings of the 6th conference on Winter simulation (1973)

A GPSS model has been developed to assist in the planning and evaluation of emergency medical facilities. This paper describes the ERSIM Model and its use in the analysis of design and operating alternatives. Applications of the model to date have included analysis of triaging policies and physician staffing patterns. The results of these studies and opportunities for future applications are discussed.
Algebraic factoring and rational function integration
Authors: Barry M. Trager
Venue: Proceedings of the third ACM symposium on Symbolic and algebraic computation (1976)

This paper presents a new, simple, and efficient algorithm for factoring polynomials in several variables over an algebraic number field. The algorithm is then used iteratively, to construct the splitting field of a polynomial over the integers. Finally the factorization and splitting field algorithms are applied to the problem of determining the transcendental part of the integral of a rational function. In particular, a constructive procedure is given for finding the least degree extension field in which the integral can be expressed.
Framework for a taxonomy of fault-tolerance attributes in computer systems
Authors: Algirdas Avižienis
Venue: Proceedings of the 10th annual international symposium on Computer architecture (1983)

A conceptual framework is presented that relates various aspects of fault-tolerance in the context of system structure and architecture. Such a framework is an essential first step for the construction of a taxonomy of fault-tolerance. A design methodology for fault-tolerant systems is used as the means to identify and classify the major aspects of fault-tolerance: system pathology, fault detection and recovery algorithms, and methods of modeling and evaluation. A computing system is described in terms of four universes of observation and interpretation, ordered in the following sequence: physical, logic, information, and interface, or user's. The description is used to present a classification of faults, i.e., the causes of undesired behavior of computing systems.
Relevance of computer science education to industry and government needs - A critique of the proposed update to curriculum '68
Authors: Russell Armstrong, Paul Oliver, Robert Orchard, John Shoosmith
Venue: ACM SIGCSE Bulletin (1976)

It is frequently suggested that computer science curricula are generated in a vacuum with little or no regard for the &ldquo;real-world needs&rdquo; of the student's ultimate employer. Furthermore, the question has recently been raised whether computer science programs should prepare their graduates to be &ldquo;tool users&rdquo; or &ldquo;tool builders.&rdquo; The panel, composed of distinguished representatives from industry and Government, will relate their past experience with computer science graduates and will address their immediate personnel needs (i.e., areas of required expertise for new employees). Each panel member will then present his candid view of the proposed updates to &ldquo;Curriculum '68&rdquo; currently being prepared by ACM's Curriculum Committee on Computer Science.
The general problem of computing languages: Their nature, function and translation.
Authors: W. Orchard-Hays
Venue: Proceedings of the 1961 16th ACM national meeting (1961)

The increasing use of expensive computing equipment has, as nearly everyone now knows, led to equally or even more expensive programming requirements. Several powerful systems of &ldquo;software&rdquo; are now available which attempt to bridge the gap between man and machine. However, the development time and cost, the complexity and the relative inflexibility of systems as currently implemented have reached a critical level. Not inconsiderable attempts at standardizations of wide utility have been made but we seem unable to apply even standardized equipment to a wide spectrum of problems efficiently. The expense, difficulty and time involved in major projects&mdash;no matter how worthwhile&mdash;are demanding that simplifying principles be discovered and applied.
Contingency planning and disaster recovery
Authors: Ken Fong
Venue: Proceedings of the 1984 annual conference of the ACM on The fifth generation challenge (1984)

The ability to provide uninterruptable access to automated informational resources will be profoundly different in the Fifth Generation. The types of changes that we can expect are already being reflected in the emerging building blocks for the Fifth Generation. As our dependency on the computerized environment, as well as our need for easy access to informational resources increases, there is a corresponding increase in tools and mechanisms designed to allow us to quickly and easily recover from many types of natural and man-made disasters. Today, we are just beginning to address the need for uninterruptable access. By the Fifth Generation, we will have solved problems which today appear to be so complex as to be impossible to solve.