ppxscal/embedding_network huggingface dataset:
Studydesk: semi-immersive volumetric data analysis
Authors: Peter Stephenson, L. Miguel Encarnação, Pedro Branco, Joachim Tesch, David Zeltzer
Venue: Proceedings of the 1st international conference on Computer graphics and interactive techniques in Australasia and South East Asia (2003)

The StudyDesk system provides a workbench environment that is well suited to work with multi-dimensional volumetric data in a semi-immersive virtual-reality setting. Using the StudyDesk system, we have implemented two example volume-rendering applications. The first visualises medical volumetric data using its implicit correspondence to physical space. The second is used to visualise and analyse sonar data described by time, range, bearing and frequency dimensions, in which correlations between sub-volumes is important. Therefore an abstract representation of the dataset is used to identify important regions in the data, which are then analysed using more traditional volume visualisation techniques. Interaction is implemented through the use of personal interaction props based on a pen and pad metaphor. Props include a transparent pen and pad that carry virtual shapes and a PDA system that is also used to transfer data and contexts between various systems.
Modeling the Reliability of a Class of Fault-Tolerant VLSI/WSI Systems Based on Multiple-Level Redundancy
Authors: Y. -Y. Chen, S. J. Upadhyaya
Venue: IEEE Transactions on Computers (1994)

A class of fault-tolerant Very Large Scale Integration (VLSI) and Wafer Scale Integration (WSI) schemes, called the multiple-level redundancy, which incorporates both hierarchical and element level redundancy has been proposed for the design of high yield and high reliability large area array processors. The residual redundancy left unused after successfully reconfiguring and eliminating the manufacturing defects can be used to improve the operational reliability of a system. Since existing techniques for the analysis of the effect of residual redundancy on reliability improvement are not applicable, we present a new hierarchical model to estimate the reliability of the systems designed by our approach. Our model emphasizes the effect of support circuit (interconnection) failures on system reliability, leading to more accurate analysis. We discuss two area prediction models, one based on the regular WSI process, another based on the advanced WSI process, to estimate the area-related parameters. This analysis gives an insight into the practical implementations of fault-tolerant schemes in VLSI/WSI technology. Results of a computer experiment conducted to validate our models are also discussed.
OPSILA: A Vector and Parallel Processor
Authors: F. Boeri, M. Auguin
Venue: IEEE Transactions on Computers (1993)

A multiprocessor machine with two operating modes and simple synchronization mechanisms is discussed. The operating modes are the vector single-instruction multiple-data (SIMD) mode and the parallel single program stream, multiple data stream (SPMD) mode. Synchronizations are reduced to the switching between these two modes. Mixing these two operating modes offers the programmer a comfortable programming environment: vector parallelization is performed by the compiler and the hardware, and, since SPMD parallelization requires mainly the partitioning of the entire set of data, the synchronizations are then often obvious.
Identifying Obstacles in the Path to More
Authors: Yale N. Patt
Venue: Computer (1997)

Our industry continually wants more-more performance, more functionality, lower power requirements, and cheaper cost. In many aspects of computing, however, providing more is not without obstacles. In the six articles in this issue, researchers attempt to summarize the current state of their respective fields and then answer the question: In order to make major improvements in our field, what fundamental research problems need to be addressed, and how should we go about addressing them?
Network Visualization with Nam, the VINT Network Animator
Authors: Deborah Estrin, Mark Handley, John Heidemann, Steven McCanne, Ya Xu, Haobo Yu
Venue: Computer (2000)

Network protocol designers face difficult tasks, including simultaneously monitoring state in a potentially large number of nodes, understanding and analyzing complex message exchanges, and characterizing dynamic interactions with competing traffic.Researchers have explored network protocol visualization in many contexts, beginning with static protocol graphs and visualization of large-scale traffic, and more recently including simulation visualizations and editors. Network visualization tools allow designers to take in large amounts of information quickly, visually identify patterns in communication, and better understand causality and interaction.Nam is a network animator that provides packet-level animation, protocol graphs, traditional time-event plots of protocol actions, and scenario editing capabilities. Nam benefits from a close relationship with ns, which can collect detailed protocol information from a simulation. The authors describe how nam uses preprocessing to visualize data taken directly from real network traces. They also feel that visualization tools such as nam make protocol design and debugging easier.
3-D Object Recognition with Symmetric Models: Symmetry Extraction and Encoding
Authors: P. J. Flynn
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1994)

Object recognition systems which employ solid models and range data have been a topic of interest for several years. Model databases have the potential to become large in some environments. This paper proposes a pair of techniques for incorporating knowledge of the symmetries of object models into the recognition process. The effects of symmetric models on the speed of an object recognition system is examined in the context of an implemented system employing invariant feature indexing as a correspondence-building mechanism. Groups of model surfaces are enumerated and examined to yield a list of segment label permutations which summarize the model's symmetry. This symmetry extraction process is followed by a symmetry encoding procedure which replaces groups of features which are indistinguishable because of symmetry with a single prototype feature group. Experiments with a large model database demonstrate the utility of these symmetry extraction and encoding techniques.
Scheduling GEN_BLOCK Array Redistribution
Authors: Hyun-Gyoo Yook, Myong-Soon Park
Venue: The Journal of Supercomputing (2002)

This article is devoted to the redistribution of arrays that are distributed in a GEN_BLOCK fashion over a processor grid. While GEN_BLOCK redistribution is essential for load balancing, prior research about redistribution has been focused on block-cyclic redistribution. The proposed scheduling algorithm exploits a spatial locality in message passing from a seemingly irregular array redistribution. The algorithm attempts to obtain near optimal scheduling by trying to minimize communication step size and the number of steps. According to experiments on CRAY T3E and IBM SP2, the algorithm shows good performance in typical distributed memory machines.
How Computer Systems Embody Values
Authors: Helen Nissenbaum
Venue: Computer (2001)

The author calls for engineering activism to intelligently guide the inevitable incorporation of values into computer systems and devices.
Guest Editor's Introduction: Software Engineering on Internet Time
Authors: Michael J. Lutz
Venue: Computer (2001)

For Internet-style software development to succeed, developers must adapt and apply classical software engineering principles and practices to the Web environment.
Java classes for nonprocedural variogram modeling
Authors: Barton R. Faulkner
Venue: Computers Geosciences (2002)

A set of JavaTM classes was written for variogram modeling to support research for US EPA's Regional Vulnerability Assessment Program (ReVA). The modeling objectives of this research program are to use conceptual programming tools for numerical analysis for regional risk assessment. The classes presented use of object-oriented design elements, and their use is described for the benefit of programmers. To help facilitate their use, class diagrams and standard JavaDoc commenting were employed. Java's support for polymorphism and inheritance is used and these are described as ways to promote extension of these classes for other geostatistical applications. Among the advantages is the ease of programming, code reuse, and conceptual, rather than procedural implementation.A graphical application for variogram modeling that uses the classes is also provided and described. It can also be used by non-programmers. This application uses a generalized least-squares fitting algorithm for robust parametric variogram model fitting through the variogram cloud. This feature makes this program unique from other freely available variogram modeling programs, though the classes are presented primarily so they may be extended for use in other Java programs. More traditional variogram plotting and fitting utilities are also provided. This application is graphical and platform-neutral. It uses classes of the recently proposed Java API for linear algebra, called the JAMA package.
Processor reconfiguration through instruction-set metamorphosis
Authors: Peter M. Athanas, Harvey F. Silverman
Venue: Computer (1993)

The processor reconfiguration through instruction-set metamorphosis (PRISM) general-purpose architecture, which speeds up computationally intensive tasks by augmenting the core processor's functionality with new operations, is described. The PRISM approach adapts the configuration and fundamental operations of a core processing system to the computationally intensive portions of a targeted application. PRISM-1, an initial prototype system, is described, and experimental results that demonstrate the benefits of the PRISM concept are presented.
System Reduction and Solution Algorithms for Singular Linear Difference Systems under Rational Expectations
Authors: Robert G. King, Mark W. Watson
Venue: Computational Economics (2002)

A first-order linear difference system under rational expectations is, AEyt+1|It=Byt+C(F)Ext| It , where yt is a vector of endogenous variables; xt is a vector of exogenous variables; Eyt+1|It is the expectation of yt+1 given date t information; and C(F)Ext|It = C0xt+C1Ext+1|It+&mid;dot;s +CnExt+n|It. If the model is solvable, then yt can be decomposed into two sets of variables: dynamic variables dt that evolve according to Edt+1|It = Wdt + &para;si d(F)Ext|It and other variables that obey the dynamic identities ft =&minus;Kdt&minus;&para;si f(F)Ext|It. We develop an algorithm for carrying out this decomposition and for constructing the implied dynamic system. We also provide algorithms for (i) computing perfect foresight solutions and Markov decision rules; and (ii) solutions to related models that involve informational subperiods.
The Cooler the Better: New Directions in the Nomadic Age
Authors: Tsugio Makimoto, Kazuhiko Eguchi, Mitsugu Yoneyama
Venue: Computer (2001)

In this historic view of the cool chip's impact on today's mobile lifestyle, the authors describe how the cool chip will play an integral role in building a better future society. The high-performance, reduced-power-consumption cool chip will inaugurate the nomadic age, leading to smaller and lighter electronic devices, with higher intelligence and lower cost. Emphasizing energy conservation in semiconductor devices, the authors assert that "the cooler the better" will become a catch phrase.Cool-chip technological advances will break the language barrier. Hitachi has demonstrated a prototype portable-translation machine, which enables communication among people who speak different languages. The advanced cool chip will play a crucial role in realizing Dick Tracy's watch, potentially the ultimate nomadic tool provided the price is affordable. Combining communication networks and digital consumer products, based on cool chips, will provide temporal and spatial freedom and contribute to reducing urban congestion, pollution, and energy consumption.
A Robust Multigrid Algorithm for the Simulation of a Yawed Flat Plate
Authors: Ruben S. Montero, Ignacio M. Llorente, Manuel D. Salas
Venue: Journal of Scientific Computing (2002)

This paper presents a full multigrid solver for the simulation of a flow over a yawed flat plate. The two problems associated with this simulation; boundary layers and entering flows with non-aligned characteristics, have been successfully overcome through the combination of a plane-implicit solver and semicoarsening. In fact, this multigrid algorithm exhibits a textbook multigrid convergence rate, i.e., the solution of the discrete system of equations is obtained in a fixed amount of computational work, independently of the grid size, grid stretching factor and non-alignment parameter. Also, a parallel variant of the smoother based on a four-color ordering of planes is investigated.
EasyRide: Active Transponders for a Fare Collection System
Authors: Thomas Gyger, Olivier Desjeux
Venue: IEEE Micro (2001)

The EasyRide ticketing system relies on radio frequency identification cards or tags to monitor passenger access to public transportation. Cards equipped with a miniature radio communication module identify passengers and record the information necessary to collect fares.
Five Ways to Destroy a Development Project
Authors: David R. Lindstrom
Venue: IEEE Software (1993)

The author discusses five problems that can contribute to a software project's failure. The five pitfalls are: inadequate system engineering during the proposal and during front-end development; inadequate tracing, tracking, and management of system and software requirements; improper sizing of the target hardware; selection of design, production, and integration and test methodologies that are inappropriate to a large software development; and failure to provide a metrics program that would let managers track the progress of software production and test.
VLSI Accelerators for Large Database Systems
Authors: Kuo Chi Lee, Takako Matoba Hickey, Victor W. Mak, Gary E. Herman
Venue: IEEE Micro (1991)

An experimental VLSI accelerator research prototype designed and fabricated for relational data filtering is described. It performs high-speed associative search and aggregation operations for formatted databases. For unformatted databases, an experimental fast string search VLSI accelerator that provides a few orders-of-magnitude improvement in text search speed has been developed. The VLSI accelerators have precise instruction sets and hardware interfaces that facilitate their integration into general-purpose computer systems and dedicated systems. Application of the accelerators to both general-purpose and dedicated computer systems is discussed. Related work is examined.
Declustering and Load-Balancing Methods for Parallelizing Geographic Information Systems
Authors: Shashi Shekhar, Sivakumar Ravada, Vipin Kumar, Douglas Chubb, Greg Turner
Venue: IEEE Transactions on Knowledge and Data Engineering (1998)

Declustering and load-balancing are important issues in designing a high-performance geographic information system (HPGIS), which is a central component of many interactive applications(such as real-time terrain visualization. The current literature provides efficient methods for declustering spatial point-data. However, there has been little work toward developing efficient declustering methods for collections of extended objects, like chains of line-segments and polygons. In this paper, we focus on the data-partitioning approach to parallelizing GIS operations. We provide a framework for declustering collections of extended spatial objects by identifying the following key issues: 1) the work-load metric, 2) the spatial-extent of the work-load, 3) the distribution of the work-load over the spatial-extent, and 4) the declustering method. We identify and experimentally evaluate alternatives for each of these issues. In addition, we also provide a framework for dynamically balancing the load between different processors. We experimentally evaluate the proposed declustering and load-balancing methods on a distributed memory MIMD machine (Cray T3D). Experimental results show that the spatial-extent and the work-load metric are important issues in developing a declustering method. Experiments also show that the replication of data is usually needed to facilitate dynamic load-balancing, since the cost of local processing is often less than the cost of data transfer for extended spatial objects. In addition, we also show that the effectiveness of dynamic load-balancing techniques can be improved by using declustering methods to determine the subsets of spatial objects to be transferred during runtime.
Is There a Silicon Way to Intelligence?
Authors: Eduardo R. Caianiello
Venue: IEEE Micro (1989)

The author expresses his opinion on the future of silicon in neural network hardware. He expresses a lack of confidence in silicon and similar techniques for the long run, but he argues that we are not likely to dispense with silicon in the near future.
On halving line arrangements
Authors: Alina Beygelzimer, Stanislaw Radziszowski
Venue: Discrete Mathematics (2002)

Given a set of n points in general position in the plane, where n is even, a halving line is a line going through two of the points and cutting the remaining set of n - 2 points in half. Let h(n) denote the maximum number of halving lines that can be realized by a planar set of n points. The problem naturally generalizes to pseudoconfigurations; denote the maximum number of halving pseudolines over all pseudoconfigurations of size n by h(n). We prove that h(12)= 18 and that the pseudoconfiguration on 12 points with the largest number of halving pseudolines is unique up to isomorphism; this pseudoconfiguration is realizable, implying h(12)= 18. We show several structural results that substantially reduce the computational effort needed to obtain the exact value of h(n) for larger n. Using these techniques, we enumerate all topologically distinct, simple arrangements of 10 pseudolines with a marked cell. We also prove that h(14)= 22 using certain properties of degree sequences of halving edges graphs.
A Partition Model Approach to Updating Universal Scheme Interfaces
Authors: D. Laurent, N. Spyratos
Venue: IEEE Transactions on Knowledge and Data Engineering (1994)

The updating of relational databases has received extensive attention in the past few years. However, the various methods proposed present two main drawbacks: either the method cannot perform some update because of nondeterminism, or the method is deterministic but leads to counterintuitive results. In this paper, we use partition semantics to study updating in universal scheme interfaces. It is shown that, contrary to other approaches, the main difficulties are due to nondeterminism of deletions. We characterize when a deletion is deterministic or not, and we show how partition semantics allow for choices in certain cases of nondeterminism.
Diagnostic Data Compression Techniques for Embedded Memories with Built-In Self-Test
Authors: Jin-Fu Li, Ruey-Shing Tzeng, Cheng-Wen Wu
Venue: Journal of Electronic Testing: Theory and Applications (2002)

A system-on-chip (SOC) usually consists of many memory cores with different sizes and functionality, and they typically represent a significant portion of the SOC and therefore dominate its yield. Diagnostics for yield enhancement of the memory cores thus is a very important issue. In this paper we present two data compression techniques that can be used to speed up the transmission of diagnostic data from the embedded RAM built-in self-test (BIST) circuit that has diagnostic support to the external tester. The proposed syndrome-accumulation approach compresses the faulty-cell address and March syndrome to about 28% of the original size on average under the March-17N diagnostic test algorithm. The key component of the compressor is a novel syndrome-accumulation circuit, which can be realized by a content-addressable memory. Experimental results show that the area overhead is about 0.9% for a 1Mb SRAM with 164 faults. A tree-based compression technique for word-oriented memories is also presented. By using a simplified Huffman coding scheme and partitioning each 256-bit Hamming syndrome into fixed-size symbols, the average compression ratio (size of original data to that of compressed data) is about 10, assuming 16-bit symbols. Also, the additional hardware to implement the tree-based compressor is very small. The proposed compression techniques effectively reduce the memory diagnosis time as well as the tester storage requirement.
On the fuzzy difference equation xn+1 = A+ xn/x n-m
Authors: G. Papaschinopoulos, Basil K. Papadopoulos
Venue: Fuzzy Sets and Systems (2002)

In this paper we study the existence the boundedness and the asymptotic behavior of the positive solutions of the fuzzy equation xn÷1 = A+xn/xn-m, n=0,1... where xn is a sequence of fuzzy numbers, A is a fuzzy number and m ∈ {1,2,...}.
Synthesizing Fast, Online-Testable Control Units
Authors: Sybille Hellebrand, Hans-Joachim Wunderlich, Andre Hertwig
Venue: IEEE Design Test (1998)

A target structure for implementing fast online testable control units for data-dominated applications is presented. In many cases, the proposed controller structure leads to a performance improvement of more than 30% for a standard benchmark set whereas the area overhead is less than 15% compared with conventional on-line testable finite state machines (FSM). The proposed approach is compatible with the state-of-the-art methods for FSM decomposition, state encoding and logic synthesis.
Connectionist Expert System with Adaptive Learning Capability
Authors: B. T. Low, H. C. Lui, A. H. Tan, H. H. Teh
Venue: IEEE Transactions on Knowledge and Data Engineering (1991)

A neural network expert system called adaptive connectionist expert system (ACES) which will learn adaptively from past experience is described. ACES is based on the neural logic network, which is capable of doing both pattern processing and logical inferencing. The authors discuss two strategies, pattern matching ACES and rule inferencing ACES. The pattern matching ACES makes use of past examples to construct its neural logic network and fine-tunes itself adaptively during its use by further examples supplied. The rule inferencing ACES conceptualizes new rules based on the frequencies of use on the rule-based neural logic network. A new rule could be considered as a pattern matching example and be incorporated into pattern matching ACES.
An Ultra High Speed Test System
Authors: Francois Henley
Venue: IEEE Design Test (1989)

The test-head subsystem presented uses gallium arsenide pin electronics to provide nonrepeating zero data rates up to 1.2 Gb/s. The device under test is connected to laser-scanned optical sensors, and the test system receivers use an electrooptic measurement method to capture the pin information. The receiver has a 4.5-GHz bandwidth and can perform functional test at the emitter-coupled logic level with one sampling pulse per vector. The device environment supports signals bandwidths near 5 GHz. The ACM Portal is published by the Association for Computing Machinery. Copyright © 2010 ACM, Inc. Terms of Usage Privacy Policy Code of Ethics Contact Us Useful downloads: Adobe Acrobat QuickTime Windows Media Player Real Player