ppxscal/embedding_network huggingface dataset:
Problem complexity
Authors: M. Jackson
Venue: Proceedings of the Third IEEE International Conference on Engineering of Complex Computer Systems (1997)

An approach to problem analysis is described, based on the notion of a problem frame. Problem frames are intended to capture classes of recognisable and soluble problems. Because problems are located in the environment, not in the machine to be built, problem frames are characterised by environment properties and structures. Useful frames are necessarily very narrow: realistic problems are regarded as parallel superimpositions of subproblems. Problem complexity arises from the interactions of these subproblems and of their solutions.
Implications for High Capacity Data Hiding in Presence of Lossy Compression
Authors: Deepa Kundur
Venue: Proceedings of the The International Conference on Information Technology: Coding and Computing (ITCC'00) (2000)

We derive capacity bounds for watermarking and data hiding in the presence of JND perceptual coding for a class of techniques that do not suffer from host signal interference. By modeling the lossy compression distortions on the hidden data using non-Gaussian statistics, we demonstrate that binary antipodal channel codes achieve capacity. It is shown that the data hiding capacity is at most equal to the loss in storage efficiency bit rate if watermarking and quantization for lossy compression occur in the same domain.
Protocol synthesis from timed and structured specifications
Authors: A. Nakata, T. Higashino, K. Taniguchi
Venue: Proceedings of the 1995 International Conference on Network Protocols (1995)

In this paper, we propose a method to synthesize protocol specifications automatically from service specifications written in a time-extended LOTOS called LOTOS/T+. In LOTOS/T+, structured descriptions, such as parallelism and interruption are allowed to describe service specifications, and time-constraints among non-adjacent actions can be described using Presburger formulas. Here we assume that there is a reliable communication channel between any two nodes and the maximum communication delay for each channel is bounded by a constant. Moreover we assume service specifications have no deadlocks. Under our simulation policy, a specification S' is derived from a given service specification S and a given maximum communication delay of each channel. In S', time-constraints necessary for exchanging synchronization messages are added. If S and S' can carry out the same behaviour, i.e., if S and S' are bisimulation equivalent when time is ignored, then a correct protocol specification for simulating S is derived from S' automatically
Protocols for an optical star interconnect for high speed mesh networks
Authors: M. Gerla, B. Kannan, P. Palnati
Venue: Proceedings of the Fourteenth Annual Joint Conference of the IEEE Computer and Communication Societies (Vol. 1)-Volume - Volume 1 (1995)

Optical networks can provide higher throughputs while high speed electronic networks possess the intelligence for network control and management. We present a two level high speed network architecture that combines the throughput advantage of optical networks and the intelligence of electronic processing. One level is a high speed mesh LAN which uses wormhole routing, source routing and hop-by-hop flow control mechanisms with mesh routers (asynchronous pipelined crossbar switches) to provide a high speed electronic network. The second level is an optical star network interconnecting high speed mesh networks distributed across metropolitan area distances. We obtain analytical expressions for the average message (worm) delays for the GTDM (group time division multiplexing) multi-access protocol (which includes as special cases TDM and DAS) for single-hop packet switching in the optical network of such an architecture. We use a two state discrete time Markov chain to model the arrival of messages to the optical network. Results for both uniform traffic and non-uniform traffic are presented. Finally, a modified dynamic allocation scheme is presented for single-hop packet switching which handles the message as a unit rather than sending a message as several fixed sized packets.
A Multicast Flow Control Protocol
Authors: Mark Hayden, Zhen Xiao
Venue:  (1999)

This paper describes the goals, approach, implementation, and performance of Mflow, a multicast flow control protocol. Our work focuses on the issues that arise from the increase in acknowledgments that occur as the size of the group grows. Mflow makes use of bulk acknowledgments to substantially reduce the number of acknowledgments per multicast message. It also staggers acknowledgments from different destinations to avoid storms of messages. We demonstrate that staggering can both decrease the number of acknowledgments needed for effective flow control as well as increase the robustness of the protocol to changes in the environment. We analyze both message and computation efficiency of Mflow. The protocol is computationally efficient and performs well in our experiments.
On the specification of complex software systems
Authors: F. I. Moxley
Venue: Proceedings of the 2nd IEEE International Conference on Engineering of Complex Computer Systems (1996)

The requirements specification and design specification of complex software systems has been a continual problem for the past three decades. This paper suggests an integrated approach for these two areas and provides the rationale on why this approach has been proposed for the Defense Information Infrastructure (DII) Common Operating Environment (COE). The DII is the most complex Department of Defense initiative undertaken to date. When fully implemented, it will operate as a collection of distributed heterogeneous information systems that will directly benefit the entire US Department of Defense. However, unlike other complex systems such as the "starwars" missile defence system of the past, most of individual components of the system are fairly well understood. In addition, the DII COE does not require software or hardware technology that does not currently exist. The challenge lies in the extensive scope of the system, and the level of integration and interoperability required.
Using Your PC (B&N Basics Series)
Authors: Matthew James
Venue:  (2003)

:Congratulations on getting your new computer! If you only knew how to set it up and use it, things would be perfect. But, the manual that came along with your purchase is less than helpful, with techie terms that give you a headache and diagrams that you can't make heads or tails of. Now what do you do? Help is at your fingertips with the real answers to the real questions a beginner asks. In plain English, you'll get advice on everything from how to set up your computer equipment, load software, use the internet, do some personal e-finance, even play games. Detailed illustrations on every page make it even easier to understand. Updated to include Microsoft XP.
Three Dimensional Analysis of Thermal Degradation Effects in FDSOI MOSFET's
Authors: Kwan-Do Kim, Young-Kwan Park, Jun-Ha Lee, Jeong-Taek Kong, Hee-Sung Kang, Young-Wug Kim, Seok-Jin Kim
Venue: Proceedings of the 1st International Symposium on Quality of Electronic Design (2000)

Fully Depleted Silicon-on-Insulator (SOI) devices lead to better electrical characteristics (e.g., reduced junction depth, increased channel mobility, suppressed short channel effect, excellent latchup immunity, and improved subthreshold characteristics) than bulk CMOS devices. However, the presence of a thin top silicon layer and a buried SiO2 layer causes self-heating due to the low thermal conductivity of the buried oxide. The electrical characteristics of FDSOI devices strongly depend on the path of heat dissipation.In this paper, we present a new three dimensional (3D) analysis technique for the self-heating effect of the finger-type and bar-type transistors. The 3D analysis results show that The drain current of the finger-type transistor is 14.7% smaller than that of the bar-type transistor due to the 3D self-heating effect.We have learned that the rate of current degradation increases significantly when the width of a transistor is smaller than a critical value in a finger-type layout. The current degradation for the 3D structures of the finger-type and bar-type transistors is investigated and the design issues are also discussed.
An Architectural Leakage Power Simulator for VHDL Structural Datapaths
Authors: Chandramouli Gopalakrishnan, Srinivas Katkoori
Venue: Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03) (2003)

We present a fast RTL leakage power simulator fordatapaths described hierarchically in VHDL. Only the leaf-cells such as full adder, NAND gate etc., are characterizedfor leakage power. At the bit-slice level, exhaustive characterization can be performed in reasonable time. We observed that in the transient state, the leakage power is dependent on the previous input as well. This dependence isalso incorporated into the leakage model. Using the char-acterized bit-slice cell library and a given set of inputs, thetotal leakage energy dissipated in a given datapath is estimated. Compared to HSPICE estimates, the average percentage error for three datapath-intensive designs is 1.38%.The estimation times are reduced by 4-5 orders of magnitude.
Pipelining Router Design Improves Parallel System Performance
Authors: C. Carrion, J. Gregorio, R. Beivide
Venue: Proceedings of the 2000 International Symposium on Parallel Architectures, Algorithms and Networks (2000)

Abstract-Efficient communication on fetching remote data is a criticalparameter in distributed shared-memory multiprocessors (DSM) in orderto achieve high performance. Message-passing techniques are used in manymodern communication systems and routers are essential building blocksfor these communication systems. Hence, in this paper emphasis is placedon the design of routers for 2-ary n-cube networks. Based on a simple dead-lock free algorithm, we analyze the influence of the router structure. Tobe more precise, the parameters considered were the clock frequency andthe number of pipeline stages of the router. The performance evaluationfor DSM applications shows there are significant gains in using segmentedrouters designs. In our evaluations, results show an improvement of up to12% in the execution time of some applications. This improvement occurseven though the base latency of the router has increased by 40%.
Characterization of Associative Operations with Prefix Circuits of Constant Depth and Linear Size
Authors: Gianfranco Bilardi, Franco P. Preparata
Venue:  (1988)

The prefix problem consists of computing all the products $x_{0}x_{1} \ldots x_{j} (j = 0, \ldots,N 1)$, given a sequence $x =(x_{0},x_{1},\ldots, x_{N-1})$ of elements in a semigroup. It is shown that there are unbounded fan-in and fan-out boolean circuits for the prefix problem with constant depth and linear size if and only if the Cayley graph of the semigroup does not contain a special type of cycle called monoidal cycle.
Sams Teach Yourself MySQL in 21 Days, 2 edition
Authors: Anthony Butcher, Mark Maslakowski
Venue:  (2002)

:MySQL is the most widely installed open-source database. Approximately 3.5 million MySQL servers are in use and more than 45% of databases used on Linux worldwide are MySQL databases.Its latest version, MySQL 4.1 closes the gap between MySQL and other, more sophisticated databases. Version 4.1 permits the use of MySQL as an embedded database, which means it can be compiled into another application and used in a range of devices.The second edition of Sams Teach Yourself MySQL in 21 Days has been completely rewritten by a new author. The book enables a reader to create powerful databases using MySQL. He willnot only learn how to integrate MySQL into a database-driven Web site, but also how to embed MySQL into other compiled applications.
Sun Cluster(tm) Architecture: A White Paper
Authors: Sun Microsystems
Venue: Proceedings of the 1st IEEE Computer Society International Workshop on Cluster Computing (1999)

A well designed cluster system can provide highly available access to applications, system resources and data, together with other features such as scalability and single system image. This paper describes Sun Cluster(tm), a clustering solution from Sun Microsystems that is designed to provide these features. The focus of the paper is on the architectural components of Sun Cluster that enable its single-system image capability, namely, its global networking, cluster file system and global devices components. As will be seen in the paper, single-system image is a key feature that enables many of the other goals of a good cluster design, and various components of a clustering infrastructure need to be architected to work together to provide a single-system image.
Crane Scheduling Using Tabu Search
Authors: Andrew Lim, Brian Rodrigues, Fei Xiao, Yi Zhu
Venue: Proceedings of the 14th IEEE International Conference on Tools with Artificial Intelligence (2002)

In this paper, we examine crane scheduling for ports. This important component of port operations management is studied when certain spatial constraints, which are common to crane operations, are considered. Although there has been some work on crane scheduling, such spatial constraints have not been previously developed. We assume that ships can be divided into holds and that cranes can move from hold to hold but that only one crane can work on one hold or job at any one time. The objective is to find a crane-to-job matching which will maximize throughput for such operations under these basic spatial constraints. Wepropose two dynamic programming algorithms, prove NP-completeness of the problem and provide heuristics to solve the crane scheduling problem with spatial constraints. We develop Probabilistic Tabu Search techniques for application to the problem which are easy to implement. In experiments, we compare the performance of tabu search with other algorithms applied to the crane scheduling problem.
Heuristic Techniques: Scheduling Partially Ordered Tasks in a Multi-Processor Environment with Tabu Search and Genetic Algorithms
Authors: Man Lin, Lars Karlsson, Laurence Tianruo Yang
Venue: Proceedings of the Seventh International Conference on Parallel and Distributed Systems: Workshops (2000)

Scheduling real-time computation is an extremely important activity in real-time systems, since it is the phase in which we assign the final temporal properties of the computations. The problem of allocating the resources in real-time systems creates an additional dimension within the conventional allocation problem, that of time constraints.The scheduling problem has been extensively examined in the literature. But optimization of valid schedules is an NP-hard problem, even for simple cases [2]. Therefore, heuristic approaches seem appropriate to these classes of problems. In this paper, we investigate scheduling problems with certain kinds of temporal constraints and how these problems can be solved with the techniques of taboo search [1] and genetic algorithms [3].
Programming Microsoft Outlook and Microsoft Exchange, 3 edition
Authors: Thomas Rizzo
Venue:  (2003)

:Build and run core business services across the enterprise using Microsoft's powerful massaging and collaboration tools -Outlook 98, Outlook 2000, and Exchange Server 5.5. This book offers detailed guidance - plus a full cache of code and other resources on CD - to help you build open, extensible solutions for tracking, messaging, workflow, knowledge management, and real-time collaboration.
An Integrated Architecture for the Scalable Delivery of
Authors: Dolev Danny, Mokryn Osnat, Shavitt Yuval, Sukhov Innocenty
Venue:  (2000)

The competition on clients attention requires sites to update their content frequently. As a result, a large percentage of web pages are semi-dynamic, i.e., change quite often and stay static between changes. The cost of maintaining consistency for such pages discourages caching solutions. We suggest here an integrated architecture for the scalable delivery of frequently changing hot pages. Our scheme enables sites to dynamically select whether to cyclically multicast a hot page or to unicast it, and to switch between multicast and unicast mechanisms in a transparent way. Our scheme defines a new protocol, called HTTPM. In addition, it uses currently deployed protocols, and dynamically directs browsers seeking for a URL to multicast channels, while using existing DNS mechanisms. Thus, we enable sites to deliver content to a growing amount of users at less cost and during denial of service attacks, while reducing load on core links. We report simulation results that demonstrate the advantages of the Integrated architecture, and its significant impact on server and network load, as well as clients delay.
A minimal-model based horizontal fragmentation algorithm for disjunctive deductive databases
Authors: A. Seetharaman, Yiu-Kai Ng
Venue: Proceedings of the 1997 International Symposium on Database Engineering & Applications (1997)

Disjunctive deductive databases (DDDBs) capture indefinite information, i.e., imprecise or partial knowledge of the real world, and are more general than definite deductive databases that can only represent unconditionally true facts. Formal approaches for fragmenting a DDDB, with a view to distribute the DDDB and then design a query optimization strategy for the distributed DDDB, are lacking. We present a formal approach for fragmenting a DDDB based on the minimal-model semantics. Fragments generated by the proposed algorithm facilitate query evaluation against the DDDB in a distributed system.
Performance measurement and comparison of a set of parallel periodic and non-periodic tridiagonal solvers
Venue: Proceedings of the 1996 International Symposium on Parallel Architectures, Algorithms and Networks (1996)

Various traditional solvers have been proposed in recent years for different parallel platforms. In this paper, the performance of three tridiagonal solvers, namely, the parallel partition LU algorithm, the parallel diagonal dominant algorithm, and the reduced diagonal dominant algorithm, is studied. These algorithms are designed for distributed-memory machines and are tested on an Intel Paragon and an IBM SP2 machines. Measured results are reported in terms of execution time and speedup. The measured results match analytical results closely. In addition to address implementation issues, performance considerations such as problem sizes and models of speedup are also discussed.
Optimal Deterministic Sorting on Parallel Disks
Authors: Mark H. Nodine, Jeffrey S Vitter
Venue:  (1992)

We present an optimal deterministic algorithm called Balance Sort for external sorting on multiple disks. Our measure of performance is the number of input/output (I/O) operations. In each I/O, each disk can simultaneously transfer a block of data. Our algorithm improves upon the randomized optimal algorithm of Vitter and Shriver as well as the (non-optimal) commonly-used technique of disk striping. It also improves upon our earlier merge-based sorting algorithm in that it has smaller constants hidden in the big~oh notation, it is possible to implement using only striped writes (but independent reads), and it has application to parallel memory hierarchies.
Counting Mal'tsev clones on small sets
Authors: Andrei A. Bulatov, Paweł M. Idziak
Venue: Discrete Mathematics (2003)

Idziak (Int. J. Algebra Comput. 9 (1999) 213) has shown that there are only 14 Mal'tsev polynomial clones on a 3 element set and constructed infinitely many such clones on a 4 element set. Here we improve this result by showing that there are, in fact, only countably many Mal'tsev polynomial clones on a 4 element set. A description of all such clones is included.
Saddle Point Techniques in Asymptotic Coding Theory
Authors: Daniele Gardy, Patrick Sole
Venue:  (1991)

Asymptotic estimates on coefficients of generating functions are derived by contour integration. In particular, we obtain Lee analogues of the entropy function both for small and large alphabets. An estimate on the central mements of the Binomial Law allows us to derive an asymptotic upper bound on the covering radius of binary codes of given dual distance.
On Minimizing Hardware Overhead for Exhaustive Circuit Testability
Authors: Dimitrios Kagaris, Fillia Makedon
Venue:  (1991)

Exhaustive built-in self testing is given much attention as a viable technique in the context of VLSI technology. In this paper, we present heuristic in order to make exhaustive testing of combinational circuits practical. The goal is to place a small number of register cells on the nets of the input circuit so that the input dependency of combinational elements in the circuit is less than a small given integer k. Our heuristic guarantees that each output can be individually tested with 2k test patterns and can be used as a subroutine to generat efficient test patterns to test all the outputs of the circuit simultaneously. For example, we can connect the register cells in a Linear Feedback Shift Register(LFSR). Minimizing the number of the inserted register cells reduces the hardware overhead as well as the upper bound on the number of test patterns generated. A heuristic approach has been proposed only for the case when an element in the circuit schematic denotes a boolean gate. An element may, however, also be used to represent a combinatorial circuit model. Our heuristic applies to this case as well. Extensive experimentation indicates that the proposed technique is very efficient.
Improving the Efficiency of Nuprl Proofs
Authors: Aleksey Nogin
Venue:  (1997)

In order to use Nuprl system as a programming language with built-in verification one has to improve the efficiency of the programs extracted from the Nuprl proofs. In the current paper we consider proofs from the Nuprl automata library. In some of these proofs (pigeon-hole principle, decidability of the state reachability, decidability of the equivalence relation on words induced by the automata language) sources of exponential-time complexity have been detected and replaced by new complexity cautious proofs. The new proofs now lead to polynomial-time algorithms extracted by the same Nuprl extractor, thus eliminating all known unnecessary exponentials from the Nuprl automata library. General principles of efficient programming on Nuprl are also discussed. Key Words and Phrases: automata, constructivity, Myhill-Nerode theorem, Nuprl, program extraction, program verification, state minimization.
Probabilistic Abduction for Plan Recognition
Authors: Eugene Charniak, Robert Goldman
Venue:  (1991)

Plan recognition requires the construction of possible plans that could explain a set of observed actions, and the selection of one or more of them as providing the {\em best} explanation. In this paper we present a formal model of the latter process based upon probability theory. Our model consists of a knowledge-base of facts about the world expressed in a first-order language, and rules for using that knowledge base to construct a Bayesian network. The network is then evaluated, to find the plans with the highest probability.
PREMO: an emerging standard for multimedia presentation
Authors: Ivan Herman, Graham J. Reynolds, James Loo
Venue:  (1995)

ISO/IEC JTC1/SC24 are developing a standard for the presentation of multimedia objects, called PREMO (Presentation Environments for Multimedia Objects). PREMO is aimed at application developers who want to include multimedia effects into the applications, but do not want to restrict themselves to model of multimedia documents, which is prevalent in multimedia applications today. This report gives an overview of the current status of PREMO.