ppxscal/embedding_network huggingface dataset:
Autonomous Data Synchronization in Heterogeneous Systems to Assure the Transaction
Authors: Isao Kaji, Yongdong Tan, Kinji Mori
Venue: The 4th IEEE International Symposium on High-Assurance Systems Engineering (1999)

Many companies have been enforced to quickly respond to changing user needs. To provide more convenient services to consumers, the cooperation within a company or across companies have been requested. As the result, the heterogeneous information systems are also requested to be integrated together. By utilizing the heterogeneity among systems and by cooperating between systems, it becomes possible to draw out new values from them without violating each system's characteristic. In the heterogeneous systems, such as the data generation timings or frequencies are different, the data synchronization itself should be done by each system without relying on the single coordinator, because the system configurations are always changing, and members of application group which use synchronous data combination are also changing. In this paper we propose the autonomous data synchronization technique in the heterogeneous systems. The application objects which requires the synchronous combination of the data in each system can locally judge which combination of data is most adequate as the synchronous combination by comparing the synchronous information with others. Thus all systems can use the consistent combination as the synchronous data only by collecting the data locally and exchanging the synchronous information. In addition, the cost of synchronization in each system, which is measured by the synchronization waiting time (SWT) and backward data utilization (BDU) becomes even. As this proposed method is not relying on the single coordinator, it works correctly even if the system configuration is dynamically changed, or even if members of SyncApps are changed. The simulation results show the cost fairness when three systems are interconnected in straight line.
Dataflow Frequency Analysis Based on Whole Program Paths
Authors: Bernhard Scholz, Eduard Mehofer
Venue: Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques (2002)

Efficient use of machine resources in high-performance computer systems requires highly optimizing compilers with sophisticated analyses. Static analysis often fails to identify frequently executed portions of a program which are the places where optimizations achieve the greatest benefit.This paper introduces a novel data flow frequency analysis framework that computes the frequency with which a data flow fact will hold at some program point based on profiling information. Several approaches which approximate the frequencies based on k-edge profiling have been presented. However, no feasible approach for obtaining the accurate solution exists so far. Recently, efficient techniques for recording whole program paths (WPPs) have been developed. Our approach for computing data flow frequencies results in an accurate solution and utilizes WPPs to obtain the solution in reasonable time. In our experiments we show that the execution time of WPP-based frequency analysis is in case of the SPEC benchmark suite only a fraction of the overall compilation time.
Finding Components in a Hierarchy of Modules: a Step towards Architectural Understanding
Authors: Jean-Francois Girard, Rainer Koschke
Venue: Proceedings of the International Conference on Software Maintenance (1997)

This paper presents a method to view a system as a hierarchy of modules according to information hiding concepts and to identify architectural component candidates in this hierarchy. The result of the method eases the understanding of a system's underlying software architecture. A prototype tool implementing this method was applied to three systems written in C (each over 30 Kloc). For one of these systems, an author of the system created an architectural description. The components generated by our method correspond to those of this architectural description in almost all cases. For the other two systems, most of the components resulting from the method correspond to meaningful system abstractions.
A Telecooperation Framework Based on Broker and Trading Services
Authors: Siegfried Höck, Michael Weber
Venue: Proceedings of the 1st International Conference on Enterprise Distributed Object Computing (1997)

Telecooperation receives increasing importance in a globalized information and work infrastructure. Among others, teleconferencing and workflow management are technological areas being studied and developed to support telecooperation scenarios. I.e. real-time collaboration tasks are being supported by teleconferencing systems, asynchronous tasks are being supported by workflow management systems. An integrated telecooperation framework for both approaches is described which uses a conference broker to couple both system types. The close coupling, however, is not transparent with respect to the actual instances of used systems. This lack in service selection transparency also results in a lack of location transparency. Thus, we extend our framework by a trading service. Workflow modules act as the importers of teleconferencing services being exported by conference modules. A distributed trading service mediates between service offers and service requests. The trader is self-sufficient as it does not require any distributed platform, such as CORBA or DCE. It may be deployed in a standard internet infrastructure.
DART - A Software Architecture for the Creation of a Distributed Asynchronous Recognition Toolbox
Authors: A. Hennig, E. Marongiu, N. Sherkat, R. J. Whitrow
Venue: Proceedings of the 4th International Conference on Document Analysis and Recognition (1997)

Automatic analysis and recognition of documents is a complex task. Substantial research effort has therefore been spent addressing sub-tasks of manageable size. The solutions, however, have to be integrated into a comprehensive engine. Following the idea of a toolbox, a software architecture has been developed that enables various tools to be combined into a network of co-operating recognition algorithms. Distributing the tools on a number of processors improves overall performance by parallel execution. The configuration of the tools as well as the connections between them can easily be modified, even at run-time. Simple, interactive access to the various parameters and intermediate results of an algorithm aids the development and evaluation of experimental systems. The modular approach also facilitates extension of existing systems by the integration of novel methods. DART, the Distributed Asynchronous Recognition Toolbox architecture, realises these features.
Ubiquitous Message Passing Interface Implementation in Java: jmpi
Authors: Kivanc Dincer
Venue: Proceedings of the 13th International Symposium on Parallel Processing and the 10th Symposium on Parallel and Distributed Processing (1999)

jmpi is a 100% Java-based implementation of the Message-Passing Interface (MPI-1) standard. jmpi comes with an efficient and effective MPI implementation in Java and supports a user-friendly Java Application Programming Interface (API) for MPI. We present the implementation details and give some early communication benchmark performance results on a cluster of SUN UltraSparc workstations.
A distributed algorithm for the detection of local cycles and knots
Authors: Azzedine Boukerche, Carl Tropper
Venue: Proceedings of the 9th International Symposium on Parallel Processing (1995)

The purpose of this paper is to present an efficient distributed cycle/knot detection, algorithm for general graphs which will determine whether a given node is a member of a knot or a cycle. This is relevant to an application such as parallel simulation in which (1) cycles and knots can arise frequently, (2) the size of the graph is very large and (3) it is necessary to know if a given node is in a cycle or a knot. The algorithm is based on a diffusing computation. It requires less communication cost than preceding algorithms and is the first algorithm capable of detecting both cycles and knots. The algorithm differs from the classical diffusing computation methods through its use of incomplete search messages to speed up the computation. The algorithm requires a total of at most 2m messages, where m is the number of links. This is compared to Chandy-Misra's algorithm (1982) which requires at least (3m+n), where n is a number of nodes and m is the number of links. The algorithm. Requires O(log(n)) bits of memory. Various applications for the cycle/knot detection algorithm are presented. In particular, we demonstrate its importance to deadlock detection to algorithms for parallel simulation which employ a blocking paradigm and a deadlock breaking technique known as TNE/DLTNE.
Incas: a cycle accurate model of UltraSPARC
Authors: Guillermo Maturana, James L. Ball, Jeffery Gee, Amaresh Iyer, J. Michael O'Connor
Venue: Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors (1995)

This paper describes a cycle accurate model of the UltraSPARC processor. The model is written in C++, and is built on top of a powerful programming framework with a built-in message-passing mechanism and a timing discipline for simulating concurrent modules. The goal was to help verify the processor by cross checking the RTL model at run time, as well as to provide accurate performance estimates. Because of Incas' much faster execution rate than the RTL, it was also used to model the UItraSPARC module in RTL simulations of the full system, for compiler and library tuning, and for diagnostics development.
An Image Consulting Framework for Document Analysis of Internet Graphics
Authors: Mario Köppen, Lutz Lohmann, Bertram Nickolay
Venue: Proceedings of the 4th International Conference on Document Analysis and Recognition (1997)

A new system approach for image understanding, the image consulting framework, is proposed. It allows for the validation of image properties. Kinds of image properties considered are textual, textural, hierarchically, color and symbolically. Its main application field is information filtering from images used in world wide web documents. The image consulting framework consists of four stages, the color separation stage, the information granulation-verification modules (GVMs), the task stage and the recognition stage. On the base of the framework are the GVMs, which are designed to solve very special tasks. They consists of three parts, a method maintainer, a parameter chooser and a tester. The parameter chooser uses a given set of parameter settings for different runs of the maintained method on the input images of the GPM. The resulting images are tested for the occurrence of the propertyfor which the GVM is designed. All succesfull images are put into a queue. The task stages calls new GVMs due to the filling of the queue and it also assigns input images to the GVMs. All fully treated images are passed to the recognition stage, where the information extraction is performed.
Locking in OODBMS Client Supported Nestd Transactions
Authors: Laurent Daynès, Olivier Gruber, Patrick Valduriez
Venue: Proceedings of the Eleventh International Conference on Data Engineering (1995)

Nested transactions facilitate the control of complex persistent applications by enabling both fine-tuning of the scope of rollback and safe intra-transaction parallelism. We are concerned with supporting concurrent nested transactions on client workstations of an OODBMS. Use of the traditional design and implementation of a lock manager results in a high CPU overhead: in-cache traversals of the 007 benchmark perform, at best, 4.5 times slower than the same traversal achieved in virtual memory by a nonpersistent programming language. We propose a new design and implementation of a lock manager which cuts that factor down to 1.8. This lock manager supports nested transactions with both sibling and parent/child parallelisms, and provides object locking at a cost comparable to page locking. Object locking is therefore a better alternative due to its higher functionality.
Performance estimation for real-time distributed embedded systems
Authors: Ti-Yen Yen, Wayne Wolf
Venue: Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors (1995)

Many embedded computing systems are distributed systems: communicating processes executing on several CPUs/ASICs connected by communication links. This paper describes a new, efficient analysis algorithm to derive tight bounds on the execution time required for an application task executing on a distributed system. Tight bounds are essential to cosynthesis algorithms. Our bounding algorithms are valid for a general problem model: the system can contain several tasks with different periods; each task is partitioned into a set of processes related by data dependencies; the periods and the computation times of processes are bounded but not necessarily constant. Experimental results show that our algorithm can find tight bounds in small amounts of CPU time.
Effects of Dynamic Task Distributions on the Performance of a Class of Irregular Computations
Authors: Hemal V. Shah, José A. B. Fortes
Venue: Proceedings of the international Conference on Parallel Processing (1997)

In this paper, a modified version of previously proposed quasi-barrier technique is developed. On distributed memory machines, relaxation with modified quasi-barriers can be used to perform basis computations that arise in symbolic polynomial manipulation. In this type of synchronous computation, the set of tasks is distributed across the processors. Each nonzero result of a task reduction dynamically generates a set of new tasks. The distribution of these newly generated tasks can have a significant impact on the overall execution time of the parallel computation. In this paper, four task distribution strategies, named modified block, modified sorted block, modified cyclic, and modified sorted cyclic are developed and their performances are comparatively evaluated. For the experiments performed on an 18-node IBM SP2, the modified cyclic distribution provides the best performance overall.
Assessing the impact of changes at the architectural level: a case study on graphical debuggers
Authors: D. Scott McCrickard, Gregory D. Abowd
Venue: Proceedings of the 1996 International Conference on Software Maintenance (1996)

Understanding the high level structure of a software system is useful for determining the impact of proposed changes. We investigate techniques for recovering the high level structure, or software architecture, for cases in which no trusted architectural description exists. We then demonstrate how a scenario based approach to architectural evaluation can be used to document the impact of proposed changes on a software system. Architectural recovery and impact analysis are demonstrated using a case study comparing two graphical debuggers, xdbx and ups.
Battlefield Visualization and Intelligent Agents Decision Support
Authors: Flávio Mello, Edilberto Strauss, Antonio A. F. Oliveira
Venue: Proceedings of the 15th Brazilian Symposium on Computer Graphics and Image Processing (2002)

This paper describes a decision support system for military operations based on intelligent agents dedicated to the planning and shaping activities. The system has a 3D visualization toolkit for the modeling of the war virtual scenario, which is represented by a 3D mesh using a height map of the actual battle space. The intelligent agents approach is used to support the commanders' decisions in conformity with a known combat doctrine. Each troop is designed as an agent, where its actions are described as a set of prefixed action-rules.
Aurora: Scoped Behavior for Per-Context Optimized Distributed Data Sharing
Authors: Paul Lu
Venue: Proceedings of the 11th International Symposium on Parallel Processing (1997)

We introduce the all-software, standard C++-based Aurora distributed shared data system. As with related systems, it provides a shared data abstraction on distributed memory hardware. An innovation in Aurora is the use of scoped behaviour for per-context data sharing optimizations (i.e., portion of source code, such as a loop or phase). With scoped behaviour a new language scope (e.g., nested braces) can be used to optimize the data sharing behaviour of the selected source code. Different scopes and different shared data can be optimized in different ways. Thus, scoped behaviour provides a novel level of flexibility to incrementally tune the parallel performance of an application.
Modeling the Difficulty of Sequential Automatic Test Pattern Generation
Authors: Thomas E. Marchok, Wojciech Maly
Venue: Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors (1996)

This paper introduces a model which describes the cost of automatic test pattern generation for (non-scan) sequential logic in terms of attributes of the circuit under test. This model addresses a core issue involved in integrated circuit design and test trade-offs, and can be used to evaluate the cost effectiveness of potential design-for-testability (DFT) techniques. This knowledge can also be used to identify hard-to-test portions of designs, and therefore to devise more cost-effective DFT techniques.
Improving the Performance of Out-of-Core Computations
Authors: Mahmut T. Kandemir, J. Ramanujam, Alok N. Choudhary
Venue: Proceedings of the international Conference on Parallel Processing (1997)

The difficulty of handling out-of-core data limits the potential of parallel machines and high-end supercomputers. Since writing an efficient out-of-core version of a program is a difficult task and since virtual memory systems do not perform well on scientific computations, we believe that there is a clear need for compiler-directed explicit I/O approach for out-of-core computations. In this paper, we present a compiler algorithm to optimize locality of disk accesses in out-of-core codes by choosing a good combination of file layouts on disks and loop transformations. The transformations change the access order of array data. Experimental results obtained on IBM SP-2 and Intel Paragon provide encouraging evidence that our approach is successful at optimizing programs which depend on disk-resident data in distributed-memory machines.
Integrating Heterogeneous Data Sources with XML and XQuery
Authors: Georges Gardarin, Antoine Mensch, Tuyet-Tram Dang-Ngoc, L. Smit
Venue: Proceedings of the 13th International Workshop on Database and Expert Systems Applications (2002)

XML has emerged as the leading language for representing and exchanging data not only on the Web, but also in general in the enterprise. XQuery is emerging as the standard query language for XML. Thus, tools are required to mediate between XML queries and heterogeneous data sources to integrate data in XML. This paper presents the e-XMLMedia mediator, a unique tool for integrating and querying disparate heterogeneous information as unified XML views. It describes the mediator architecture and focuses on the unique distributed query processing technology implemented in this component. Further, we evoke the various applications that are currently being experimented with the e-XMLMedia Mediator.
Testability analysis and insertion for RTL circuits based on pseudorandom BIST
Authors: Joan Carletta, Christos A. Papachristou
Venue: Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors (1995)

A testability analysis technique for built-in self-test (BIST) at the system level is presented. While based on previous approaches, the model has several significant new features, including an iterative technique for modeling indirect feedback and an extension to the circular BIST methodology. Additionally, a new preprocessing transformation enables the correct modeling of word-level correlation. Examples validate the model, and demonstrate its applicability to test point insertion.
A Comparative Study of Methods for Time-Deterministic Message Delivery in a Multiprocessor Architecture
Authors: Jan Jonsson, Jonas Vasell
Venue: Proceedings of the 10th International Parallel Processing Symposium (1996)

In this paper we present a method, called TDC, for time-deterministic delivery of fine-grain messages in multiprocessor architectures with point-to-point interconnection networks. Other methods for scheduling predictable communication in such networks are flexible and efficient but suffer from a high cost when hardware-only implementations are required. Using results from a comparative study, we argue that efficiency in the scheduling technique can be traded for simplicity in the implementation. In particular, we show that if the simpler techniques of TDC are used instead of more complex methods, the implementation cost for communication mechanisms can be reduced by as much as 40% at the price of an overall performance degradation of no more than 15% in the application. In addition, the lower hardware requirements of TDC reduce the message processing delay by 33%.
The Electronic Guidebook: A Study of User Experiences Using Mobile Web Content in a Museum Setting
Authors: Sherry Hsi
Venue: Proceedings IEEE International Workshop on Wireless and Mobile Technologies in Education (2002)

A study of fifteen is reported as part of a larger research project, The Electronic Guidebook, whose aims are to understand how the introduction of wireless technologies changes and augments user experiences at the Exploratorium, an interactive science museum. The main questions being addressed in this study are: How do users respond to a mobile web resource designed to improve and transform user experiences in a hands-on museum? This paper shares results from interviews with three categories of users: teachers, staff explainers', andvisitors. Several recurring issues and themes emerged from our analyses such as users' sense of isolation and user attempts to make a seamless experience between real-place and virtual contexts. Teachers, in particular, felt the mobile web content would be more useful as learning activities before and after museum visits. While majority of users expressed a concern that the handheld would interfere with exhibit play, these users also reported positive feedback about the mobile web content and demonstrated new ways in which this resource motivated new ways to think and play with exhibits. Additional insights are provided regarding the role ofmobile web content in mediating user interactions including a framework under development for organizing interactions with handhelds.
A case study in low-power system-level design
Authors: Andrew Wolfe
Venue: Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors (1995)

A case study in low-power system-level design is presented. We detail the design of a typical low-power embedded system, a touchscreen interface device for a personal computer. This device is designed to operate only on excess power provided by unused RS232 communication lines. We focus on the design and measurement procedures used to reduce the power requirements of this system to less than 50 mW. Furthermore, we highlight opportunities to use system-level design and analysis tools for low-power design. Finally, we identify, key issues in low-power system design that are not currently being explored by the design automation community.