ppxscal/embedding_network huggingface dataset:
Attribute Trees in Image Analysis ¾ Heuristic Matching and Learning Techniques
Authors: Markus Peura
Venue: Proceedings of the 10th International Conference on Image Analysis and Processing (1999)

As a data structure, a tree is an optimal presentation of hierarchical objects. Many irregular and dynamical phenomena studied for example in biology, medical sciences, meteorology, and geomorphology can be modeled as a tree. In addition, objects initially modeled as a graph can sometimes be transformed to a tree, say to a minimum spanning tree.This paper presents new techniques for indexing, matching, and generalizing rooted unordered attribute trees. The proposed matching scheme is based on dividing the tree recursively into sub-trees. The sub-trees are matched according to topological indices which have been calculated in advance using linear updating rules. The feasibility of the suggested methods is illustrated with experiments on real data extracted from remote sensing imagery.
The SPS-41 and SPS-81 programmable digital signal processors
Authors: Joseph R. Fisher
Venue: Conference record of the 6th annual workshop on Microprogramming (1973)

The SPS-41 and SPS-81 are very high speed multiprocessor computers designed for signal processing applications. They can either function as stand-alone processors or operate in conjunction with a conventional computer. The SPS-41 provides the capability to perform signal processing functions with about a 100 fold increase in speed over a conventional computer&mdash;typically 8.3 milliseconds for a 1024 complex Fast Fourier Transform. The SPS-81 is roughly twice as fast as the SPS-41. This speed is achieved through a highly parallel architecture which is optimized for signal processing operations.
Design verification of large scientific computers
Authors: Howard E. Krohn
Venue: Proceedings of the 14th Design Automation Conference (1977)

Large scientific computers containing 2 million gates can be simulated using a combination of block simulation and gate simulation of 450, 00O gates.
Verification of the FTSC microprogram
Authors: Dono van-Mierop, Leo Marcus, Steve Crocker
Venue: Proceedings of the 11th annual workshop on Microprogramming (1978)

At ISI, we are halfway into a two year research program in microcode verification. We are focussing our attention on microcode that implements a target instruction set. The Fault-Tolerant Spaceborne Computer is a typical microcoded machine and we are using an early version of it as the prime example for the present work. example for the present work. The host machine decodes a 78 bit microinstruction into 37 separate fields. About 750 microinstructions are used to implement the target instruction set. The target machine is word oriented with 32 bit words. The CPU has eight general purpose registers and carries out the usual repertoire of integer, logical and floating point operations.
Function minimization on special computers
Authors: J. C. Nash
Venue: Proceedings of the ACM 1980 annual conference (1980)

For the purposes of discussion, a special computer will be taken to be one in which it is not possible to employ standard mathematical software libraries. Thus we are concerned with the ubiquitous personal computers, various array or pipeline machines, and some mini and micro computers primarily destined to tasks other than general purpose computing (e.g. control applications). The function minimization problem, that of finding a set of parameters b* so that S(b*) &le; S(b) for all b @@@@ b* within some region is of interest in many real and contrived problems. The global minimization problem will be addressed only in passing, and attention will be paid mainly to the case where S is continuous and smooth. Brief mention will be made of problems with several constraints on the parameters. However, the mathematical programming problem, where there may be large numbers of constraints, continues to provide a serious challenge to developers of numerical methods for small computers.
On an automated method
Authors: Paul E. Hamburger
Venue: Proceedings of the 1966 21st national conference (1966)

The MITRE Corporation has been involved in the acquisition of digital information processing systems for the Air Force and other United States Government agencies. Each of these systems has had characteristic critical execution time requirements for its digital computer programs. If the execution times of the produced programs were larger than specified by requirements, unacceptable degradation in performance would result. An abbreviated view of system acquisition is as follows: The user states the processing features he desires and estimates his load. A computer is selected, and a program is designed, coded, and checked out. The program is executed. It has time characteristics which may or may not be satisfactory. In any case, the requirements often change with system use and changing environment. To best predict what changes in implementation will produce or maintain a satisfactory execution time, the time should be expressed as a function of user load, program blocks, and computer configuration variables. Given a functional (symbolic) description of execution time, predictions can be made as to the effect of increasing user-load, changing hardware configurations, or adding or deleting features. Also, areas consuming large amounts of execution time or storage can become candidates for program improvement. In a typical application, only some variables are of interest. Others are fixed by externally imposed conditions. By substituting numbers for fixed variables into symbolic time and storage expressions, the time as a function of only the variables of interest can be examined. It must be emphasized that the variables of interest vary from case to case. Therefore, an approach which allows symbolic representation of as many variables as possible should best serve the general user.
A New Overflow Replacement Policy for Efficient Location Management in Mobile Networks
Authors: Ying Luo, Yi Pan, Jie Li, Yang Xiao, Xiaola Lin
Venue: Proceedings of the 23rd International Conference on Distributed Computing Systems (2003)

Location management is one of the most important issues in mobile networking systems. Most current mobile systems employ a two-tier database structure to store mobile users' information. HLR (Home Location Register) is used to retrieve user's information, and VLR (Visitor Location Register) is the temporal database for storing visitors' profile. In the case that the number of users exceeds the capacity of the VLR due to mobility, database overflow occurs. In this paper, we propose a new policy, the least frequent replacement policy, which selects the least frequently accessed users as replacement candidates. Extensive simulation is carried out forpredicting the performance of the existing replacement policies and the proposed least frequent policy. Our simulation results show that the most idle and least frequent policies outperform the inactive and random replacement policies in most cases and that the least frequent policy performs slightly better than the most idle replacement policy.
Computer data communication: Packet switching in a slotted satellite channel
Authors: Simon S. Lam
Venue: Proceedings of the ACM annual conference (1973)

Methods for data communication using a packet switching technology over a slotted satellite channel are proposed and studied. The basic model assumes an input source from many independent lowrate stations which use the channel in a multiple random access mode. When simultaneous transmissions interfere with one another, all of the conflicting packets are destroyed and must be retransmitted after some random delay. The message delay vs. channel throughput tradeoff is studied for various random delay policies. The dynamic behavior and stability of the model is analyzed. The channel is locally stable if the traffic rate is less than 1. Control policies are studied to return the channel from an unstable state to a stable state. The maximum channel throughput for this model (corresponding to a channel traffic rate of 1) is limited to below 1/e. Two other models are studied in which the channel throughput exceeds 1/e. The first consists of the addition of one or more high-rate buffered stations to the previous model. In this case the increase in overall channel throughput is at the expense of degraded performance for the low-rate stations. The second involves using a fraction of the channel capacity for the stations to make reservations. In this case, the increase in channel through put is at the expense of longer message delays.
Computer aided design in North American Schools of Architecture
Authors: Robert Simpson Frew
Venue: Proceedings of the 14th Design Automation Conference (1977)

A catalogue of computer aided design teaching and project work is presented for a number of Schools of Architecture in North America. Each participating school has completed one page that explains the projects that are in operation and under development.
A role for computer simulation in the economic analysis of manufacturing systems
Authors: Syed Wali Haider, Leland T. Blank
Venue: Proceedings of the 15th conference on Winter simulation - Volume 1 (1983)

This paper discusses traditional economic analysis methodologies used in evaluating manufacturing systems and points out some potential problems with these methodologies because of the omission of certain cost elements in the analysis and/or not having an appropriate mechanism for accurately estimating certain additional cost elements and product revenues. Integrating computer simulation into the economic analysis methodologies is proposed as a way of eliminating the shortcomings preceived in them. The paper further discusses how computer simulation models can be used to develop product revenues and certain system cost components that are either not included or not estimated accurately in the current approaches.
Performance evaluation of a feedback data flow processor using simulation
Authors: C. Retna Dhas
Venue: Proceedings of the 1980 international symposium on Computer performance modelling, measurement and evaluation (1980)

This paper presents a method to estimate the performance of a feedback data flow processor using software simulation. A brief over view of a data flow language and a data flow processor along with the conceptual view of a software simulator are described. Numerical measurements of parallelism and resources requirements are obtained by translating high level language programs to data flow language and then executing them on the simulator.
A time-space tradeoff for sorting on a general sequential model of computation
Authors: A. Borodin, S. Cook
Venue: Proceedings of the twelfth annual ACM symposium on Theory of computing (1980)

In a general sequential model of computation, no restrictions are placed on the way in which the computation may proceed, except parallel operations are not allowed. We show that in such an unrestricted environment TIME&bull;SPACE&equil;&Ohgr;(N2/log N) in order to sort N elements, each in the range [1,N2].
An approach to a fault-tolerant system architecture
Authors: L. Boi, P. Michel
Venue: Proceedings of the 5th annual symposium on Computer architecture (1978)

Inside a Toulousian project on &ldquo;Fault tolerant computing system&rdquo;, we are interested by error confinement (hardware and software errors) and by error recovery at the operating system level. This paper discusses the principles of domains and the architecture of a capability machine (&sect; II). We detail management of scheduling and object sharing between processes, by monitors (&sect; III).Then we present error recovery mechanisms (reconfiguration, rollback) in a capability machine (&sect; IV).
On the cryptographic security of single RSA bits
Authors: Michael Ben-Or, Benny Chor, Adi Shamir
Venue: Proceedings of the fifteenth annual ACM symposium on Theory of computing (1983)

The ability to &ldquo;hide&rdquo; one bit in trapdoor functions has recently gained much interest in cryptography research, and is of great importance in many transactions protocols. In this paper we study the cryptographic security of RSA bits. In particular, we show that unless the cryptanalyst can completely break the RSA encryption, any heuristic he uses to determine the least significant bit of the cleartext must have an error probability greater than 1&edivide;4&mdash;&egr; A similar result is shown for Rabin's encryption scheme.
Performance of Lisp systems
Authors: Richard P. Gabriel, Larry M. Masinter
Venue: Proceedings of the 1982 ACM symposium on LISP and functional programming (1982)

This paper describes the issues involved in evaluating the performance of Lisp systems. We explore the various levels at which quantitative statements can be made about the performance of a Lisp system, giving examples from existing implementations wherever possible. Our thesis is that benchmarking is most effective when performed in conjunction with an analysis of the underlying Lisp implementation and computer architecture. We examine some simple benchmarks which have been used to measure Lisp systems, and examine some of the complexities of evaluating the resulting timings. This paper will explain in detail the technical issues and trade-offs that determine the efficiency and usability of a Lisp implementation; though there will appear to be a plethora of facts, we will only discuss those aspects of a Lisp implementation that we feel are the most important for evaluation. Throughout we will talk about the impact of these issues and trade-offs on benchmarks and benchmarking methodologies.
Function distribution in computer system architectures
Authors: Harold W. Lawson,  Jr.
Venue: Proceedings of the 3rd annual symposium on Computer architecture (1976)

The levelwise structuring and complexity of a computer system is presented informally and as a general model based upon the notion of abstract machines (processors), processes and interpreters. The important domains of the computer architect are considered along with historical perspectives of certain stimulae and decisions that have affected the distribution of functions amongst the various levels of computer system implementations.
A Novel Video Shot Detection Technique Using Color Anglogram and Latent Semantic Indexing
Authors: Rong Zhao, William I. Grosky
Venue: Proceedings of the 23rd International Conference on Distributed Computing Systems (2003)

In this paper, we present the results of our work that seeks to negotiate the gap between low-level features and highlevel concepts in the domain of video shot detection. We introduce a novel technique for spatial color indexing, color anglogram, which is invariant to rotation, scaling, and translation. This work also concerns a dimension reduction technique, latent semantic indexing (LSI), which has been used for textual information retrieval for many years. In this paper, we examine the use of these techniques for video shot detection, hoping to uncover the semantic correlation between video frames. Experimental results show that LSI, together with color anglogram, is able to extract the underlying semantic structure of videocontents, thus helping to improve the shot detection performance.
The minerva multi-microprocessor
Authors: Lawrence C. Widdoes,  Jr.
Venue: Proceedings of the 3rd annual symposium on Computer architecture (1976)

A multiprocessor system is described which is an experiment in low cost, extensible, multiprocessor architectures. Global issues such as inclusion of a central bus, design of the bus arbiter, and methods of interrupt handling are considered. The system initially includes two processor types, based on microprocessors, and these are discussed. Methods for reducing processor demand for the central bus are described.
SLAM tutorial
Authors: Claude Dennis Pegden, A. Alan B. Pritsker
Venue: Proceedings of the 13th conference on Winter simulation - Volume 1 (1981)

This paper provides an overview of the important features of the SLAM simulation language. The focus of the paper is the unified system-modeling framework of SLAM which allows systems to be viewed from process, event, or state variable perspectives.
A data base system for river basin management
Authors: Nguyen Duong, Daryl B. Simons, Ruh-Ming Li
Venue: Proceedings of the 10th conference on Winter simulation - Volume 1 (1978)

A data base system for the analysis of a large river basin was developed that permits users to retrieve and process a set of data elements to obtain the desired information pertaining to any gaging station, segment of a river, or a particular river in the basin. The data base management package is written in FORTRAN IV to operate under the NOS operating system. It uses a simple query language to direct the operations of various component programs. The command language specifications are also presented along with sample results of data retrieval and processing that show the usefulness of the data base system for large river basin management.
A conceptual model of raster graphics systems
Authors: James Acquah, James Foley, John Sibert, Patricia Wenner
Venue: Proceedings of the 9th annual conference on Computer graphics and interactive techniques (1982)

In this paper we present a conceptual model of raster graphics systems which integrates, at a suitable level of abstraction, the major features found in both contemporary and anticipated graphics systems. These features are the refresh buffer; the image creation (scan-conversion) system; the single address-space architecture which integrates the address space of the refresh buffer with those of the image creation system and the associated general-purpose computer; the RasterOp or BitBlt instructions found in some single address-space architectures; the video look-up table, and refresh buffer to screen transformations. Also included are the major components from the conceptual model of vector graphics systems which are embodied in the ACM/SIGGGRAPH/GSPC Core System. Using the conceptual model as a base, we proceed to sketch out the capabilities we have defined in a substantial addition to the Core System. The capabilities are currently being implemented as part of the George Washington University Core System.
Implementation of the Alpha-6 programming system
Authors: A. O. Buda, A. A. Granovaky, A. P. Ershov
Venue: Proceedings of the international conference on Reliable software (1975)

The implementation of a large compiler system is described, and conclusions are drawn about organization, time scales and the quality achieved.
User-Defined Template for Identifying Document Type and Extracting Information from Documents
Authors: Tsukasa Kochi, Takashi Saitoh
Venue: Proceedings of the Fifth International Conference on Document Analysis and Recognition (1999)

An automatic document entry system is described that identifies the type of document and extracts textual information, such as titles or authors, from semi-formatted document images. The system registers documents, offers easy retrieval of documents used in a daily workflow, analyzes the layout structure of documents by using document-specific models, and assumes that each type of document is known in advance. In this paper we focus on a method for identifying the type of document.
&ldquo;A survey of multiple-valued algorithmic logics:: From a practical point of view&rdquo;.
Authors: David Rine
Venue: Proceedings of the sixth international symposium on Multiple-valued logic (1976)

This paper on structured flowcharting suggests several fundamental changes, from a practical point of view, which need to be made in a number of representative theoretical papers covering multiple-valued algorithmic logics. The author suggests changes in the current models and gives reasons for using some new structures. A SURVEY OF MULTIPLE-VALUED ALGORITHMIC LOGICS: FROM A PRACTICAL POINT OF VIEW
Multiple fault diagnosis in combinational networks
Authors: C. W. Cha
Venue: Proceedings of the 16th Design Automation Conference (1979)

The concept of prime faults is introduced for the study of multiple fault diagnosis in combinational logic networks. It is shown that every multiple fault in a network can be represented by a structurally equivalent fault with prime faults as its only components. Functional and structural masking and covering relations among faults are defined. These relations can be exploited to greatly simplify multiple fault analysis and their test generation. We present an efficient algorithm that generates a multiple fault detection test set and identifies redundancies. Suggestions for designing networks to yield a minimum number of tests in the multiple fault detection test set are also included.
A case against the GOTO
Authors: William A. Wulf
Venue: Proceedings of the ACM annual conference - Volume 2 (1972)

It has been proposed, by E. W. Dijkstra and others, that the goto statement in programming language is a principal culprit in programs which are difficult to understand, modify, and debug. More correctly, the argument is that it is possible to use the goto to synthesize program structures with these undesirable properties. Not all uses of the goto are to be considered harmful; however, it is further argued that the &ldquo;good&rdquo; uses of the gotofall into one of a small number of specific cases which may be handled by specific language constructs. This paper summarizes the arguments in favor of eliminating the goto statement and some of the theoretical and practical implications of the proposal.
Automatic generation and characterization of CMOS polycells
Authors: C. M. Lee, B. R. Chawla, S. Just
Venue: Proceedings of the 18th Design Automation Conference (1981)

With increasing complexity and size of integrated circuits, computer aids for layout and simulation have begun to play an ever-increasing role. An approach to take advantage of these aids is the polycell design approach. However, thus far, manual procedures have been used in creating the interior of polycells. A layout style in which CMOS technology lends itself to automation and design rule updatability has been found and is described here. A program has been implemented which takes as input a symbolic description of polycells and a set of design rules, and outputs a mask description of polycells. This mask description and a command file are then input to a layout characterization and verification software system to automatically generate inputs for a polycell layout system, a circuit simulator, and a timing simulator.
Matrix inversion by partitioning
Authors: M. Lotkin, R. Remage
Venue: Proceedings of the 1952 ACM national meeting (Toronto) (1952)

There is presently available a large number of techniques purporting to accomplish the inversion of matrices. While the purely mathematical aspects of this problem, on one hand, are thus well recognized, the computational ones, on the other hand, are not. The growth of the rounding error, in particular, may be so rapid as to make some inversion procedures altogether unstable. It is from this point of view that the partitioning method seems to be capable of yielding more accurate results than do other methods. By stopping, at any desired step, to improve the intermediate inverses until satisfactory accuracy is attained, the growth of the rounding error may be kept in check.