ppxscal/embedding_network huggingface dataset:
The Research on an Adaptive Information Grid Architecture for Recommendation System
Authors: Xiao-gao Yu, Xiao-peng Yu
Venue: Proceedings of the 2006 IEEE Asia-Pacific Conference on Services Computing (2006)

This paper presents an adaptive information grid architecture for recommendation systems, which consists of the features of the recommendation rule and a co-citation algorithm. The algorithm addresses some challenges that are essential for further searching and recommendation algorithms. It does not require users to provide a lot of interactive communication. Furthermore, it supports other queries, such as keyword, URL and document investigations. When the structure is compared to other algorithms, the scalability is noticeably better. The high online performance can be obtained as well as the repository computation, which can achieve a high group-forming accuracy using only a fraction of web pages from a cluster.
A Multi-Standard Reconfigurable Viterbi Decoder using Embedded FPGA Blocks
Authors: Lucia Bissi, Pisana Placidi, Giuseppe Baruffa, Andrea Scorzoni
Venue: Proceedings of the 9th EUROMICRO Conference on Digital System Design (2006)

This paper presents a Viterbi Decoder (VD) architecture for a reprogrammable data transmission system, implemented using a Field Programmable Gate Array (FPGA) device. This VD has been conceived as a building block of a Software Defined Radio (SDR) mobile transceiver, reconfigurable on user request and capable to provide agility in choosing between different standards. UMTS and GPRS standards decoding is achieved by choosing different coding rates and constraint lengths, and the possibility to switch, at run time, between them guarantees a high degree of reconfigurability. The architecture has been tested and verified with a Xilinx XC2V2000 FPGA, to provide a generalized co-simulation/co-design testbed. The results show that this decoder can sustain an uncoded data rate of about 2 Mbps, with an area occupation of 45%, due to the efficient resource reuse.
A Monitoring Approach for Safe IPv6 Renumbering
Authors: Frederic Beck, Isabelle Chrisment
Venue: Proceedings of the International Multi-Conference on Computing in the Global Information Technology (2006)

Network renumbering is a very interesting feature of IPv6. It is also one of the most risky procedure which needs special attention in the management plane. In this paper we identify the challenges of renumbering and demonstrate how monitoring can improve this process. We also present an implementation of a monitoring framework and share the experience gained in its deployment.
Fast algorithms for identifying maximal common connected sets of interval graphs
Authors: Fabien Coulon, Mathieu Raffinot
Venue: Discrete Applied Mathematics (2006)

Given a family of interval graphs F = {G1 = (V, E1) ..... Gk = (V, Ek)} on the same vertices V, a set S ⊂ V is a maximal common connected set of F if the subgraphs of Gi, 1 ≤ i ≤ k, induced by S are connected in all Gi and S is maximal for the inclusion order. The maximal general common connected set for interval graphs problem (gen-CCPI) consists in efficiently computing the partition of V in maximal common connected sets of F. This problem has many practical applications, notably in computational biology. Let n = |V| and m = Σi=1k|Ei|. For k ≥ 2, an algorithm in O((kn + m) log n) time is presented in Habib et al. [Maximal common connected sets of interval graphs, in: Combinatorial Pattern Matching (CPM), Lecture Notes in Computer Science, vol. 3109, Springer, Berlin, 2004, pp. 359-372]. In this paper, we improve this bound to O(kn logn + m). Moreover, if the interval graphs are given as k sets of n intervals, which is often the case in bioinformatics, we present a simple O(kn log 2 n) time algorithm.
An Isomorphism between Subexponential and Parameterized Complexity Theory
Authors: Yijia Chen, Martin Grohe
Venue: Proceedings of the 21st Annual IEEE Conference on Computational Complexity (2006)

We establish a close connection between (sub)exponential time complexity and parameterized complexity by proving that the so-called miniaturization mapping is a reduction preserving isomorphism between the two theories.
Combined Scheduling of Sensing and Communication for Real-Time Indoor Tracking in Assisted Living
Authors: Min-Young Nam, Mhd Zaher Al-Sabbagh, Chang-Gun Lee
Venue: Proceedings of the 27th IEEE International Real-Time Systems Symposium (2006)

As the elderly population increases, the elderly care using inexpensive technological means becomes critical. This paper proposes novel scheduling algorithms for real-time indoor tracking of elderly residents, which is essential to assist and secure their independent living. Our scheduling algorithms are designed by harmonizing both sensing and communication signals and leveraging location-awareness and mobility-consciousness, in order to improve the tracking accuracy while reducing the energy consumption. We performed extensive experiments through both simulation and actual implementation. Our experimental result says that our scheduling algorithms can provide real-time tracking of residents within 20 cm error bound in the typical range of human mobility.
Pervasive Computing Context Access Control Based on UCON_ABC Model
Authors: Fang Pu, Daoqin Sun, Qiying Cao, Haibin Cai, Fan Yang
Venue: Proceedings of the 2006 International Conference on Intelligent Information Hiding and Multimedia (2006)

The proliferation of smart gadgets, appliances, mobile devices and sensors has enabled the construction of pervasive computing environment, transforming regular physical spaces into "Active Information Spaces". However, access control remains a major challenge for the deployment of this computing paradigm in real-life. A context access control model based on UCON_ABC model is presented in this paper, which not only focuses on authorization, but also introduces obligations, and conditions. And it includes pre-authentication, pre-condition, pre-obligation, active-right and passive-right sub-models. The operations of sub-models are presented. And the security, flexibility and usefulness of our proposed model are demonstrated by a typical pervasive computing scenario.
Low maintenance verification
Authors: Valeria Bertacco
Venue: Proceedings of the 19th annual symposium on Integrated circuits and systems design (2006)

The verification of modern computing systems has grown to dominate the cost of system design, often with limited success, as designs continue to be released with latent bugs. This trend is accelerated by the advent of highly integrated system-on-a-chip (SoC) designs, which feature multiple complex subcomponents connected by simultaneously active interfaces. To cope with this challenge, logic simulation techniques are predominant in the industry, however, the coverage of the tests generated is usually low, with the result that even months of simulation provide little confidence in the correctness of the design. Additionally, these traditional techniques require a lot of effort from the engineering team to direct the verification activity towards specific design areas of critical quality. Nonetheless, they have such high inertia in existing development processes that the cost to transition to alternative methodologies, such as formal techniques, is high.This talk will introduce a new generation of hybrid verification solutions, which we call "Low Maintenance Verification", where the contribution of formal techniques is transparently deployed within a simulation-based verification framework. Our use of formal techniques in this context greatly enhances the level of automation of the verification process, by generating solutions which can focus on a verification goal with minimal guidance from the engineer. We will overview some of the techniques that we developed in this space, including Guido and StressTest, two solutions that can automatically generate "interesting" verification scenarios. Our preliminary experience in the domain of low maintenance verification indicates that this family of techniques can effectively lead to high-performance, high-coverage verification solutions, by generating concise error traces with minimal demands on verification engineers and no change in the verification process.
On the asymptotics of fault probability in least-recently-used caching with Zipf-type request distribution
Authors: Toyoaki Sugimoto, Naoto Miyoshi
Venue: Random Structures Algorithms (2006)

We consider the least-recently-used cache replacement rule with a Zipf-type page request distribution and investigate an asymptotic property of the fault probability with respect to an increase of cache size. We first derive the asymptotics of the fault probability for the independent-request model and then extend this derivation to a general dependent-request model, where our result shows that under some weak assumptions the fault probability is asymptotically invariant with regard to dependence in the page request process. In a previous study, a similar result was derived by applying a Poisson embedding technique, where a continuous-time proof was given through some assumptions based on a continuous-time modeling. The Poisson embedding, however, is just a technique used for the proof and the problem is essentially on a discrete-time basis; thus, it is preferable to make assumptions, if any, directly in the discrete-time setting. We consider a general dependent-request model and give a direct discrete-time proof under different assumptions. A key to the proof is that the numbers of requests for respective pages represent conditionally negatively associated random variables. &copy; 2005 Wiley Periodicals, Inc. Random Struct. Alg., 2006
Imagine That, Inc: extend overview
Authors: David Krahl
Venue: Proceedings of the 37th conference on Winter simulation (2005)

See the present and the future in two sessions on the Extend simulation application. This session showcases the core Extend 6 application and includes hierarchical model building, user interface creation and interactive modeling. The next session (11:15am-12:00pm) introduces Extend 7 with its revolutionary new simulation technology and new 3D animation.
A Marketable Quality and Profitability Model for Network Service Pricing
Authors: Valbona Barolli, Heihachiro Fukuda, Leonard Barolli, Makoto Takizawa
Venue: Proceedings of the IEEE International Conference on e-Business Engineering (2006)

In this paper, we provide an evaluation model for marketable quality and profitability. We define the marketable quality as a qualitative aspect of profitability. In general, in some cases there is a trade off relation between marketable quality and profitability, but in other cases there is not. Therefore, it is an important problem to be considered how to increase the profitability by enhancing marketable quality. We apply the real values of some leading manufacturing corporations in Japan to our proposed model to analyze its accuracy. From the analysis, we found that theoretical and real standard values of the marketable quality indicator were both 0.6 (that is 60%). This shows that the proposed model has a good approximation. From the fair relation of network service providers and consumers, we present the network pricing guidelines for the maximum profitability while enhancing the marketable quality.
Adaptive Kernel Principal Component Analysis with Unsupervised Learning of Kernels
Authors: Daoqiang Zhang, Zhi-Hua Zhou, Songcan Chen
Venue: Proceedings of the Sixth International Conference on Data Mining (2006)

Choosing an appropriate kernel is one of the key problems in kernel-based methods. Most existing kernel selection methods require that the class labels of the training examples are known. In this paper, we propose an adaptive kernel selection method for kernel principal component analysis, which can effectively learn the kernels when the class labels of the training examples are not available. By iteratively optimizing a novel criterion, the proposed method can achieve nonlinear feature extraction and unsupervised kernel learning simultaneously. Moreover, a noniterative approximate algorithm is developed. The effectiveness of the proposed algorithms are validated on UCI datasets and the COIL-20 object recognition database.
The use of simulation to support major transportation planning decisions
Authors: Beth C. Kulick
Venue: Proceedings of the 36th conference on Winter simulation (2004)

When major transportation infrastructures such as freight corridors or port systems are being planned, there are typically multiple phases of preliminary engineering required. During these phases, there are design decisions made that have impacts on investment required, level of service provided, and the environment. The basic question that is typically asked during these phases is "What level of infrastructure is really needed to support the expected demands upon the system?" Simulation provides a framework to quantify the level of service provided when an infrastructure design is imposed with projected demands. There are numerous challenges associated with constructing a simulation model of the magnitude needed to support planning initiatives. This paper describes a simulation modeling approach that integrates needed planning flexibility with sufficient fidelity to understand infrastructure performance.
PSSLSA: Participatory Simulation System for Learning Sorting Algorithms
Authors: Chengjiu Yin, Hiroaki Ogata, Tomonobu Sasada, Yoneo Yano
Venue: Proceedings of the Sixth IEEE International Conference on Advanced Learning Technologies (2006)

During learning computer science theory, it is essential to learn sorting algorithms, but it is not easy to understand the concept of the different sorting algorithms. This paper describes a system called PSSLSA (PDA-based Participatory Simulation System for Learning Sorting Algorithms). This is an interactive simulation system to learn the sorting algorithms. Learners use it to deeply understand the sorting algorithms. Using this system, the teacher can assign tasks to his student and ask them to sort a list of numbers according to a certain algorithm. Learners receive these tasks, collaborate together and send the result to the server. The system will check it and feedback the student with the positions of the numbers if there is a mistake. The learners will correct the number positions and send it back to the server. Learners can understand the algorithm through the dissections and their errors.
Integer Multipliers with Overflow Detection
Authors: Mustafa Gok Michael J. Schulte, Mark G. Arnold
Venue: IEEE Transactions on Computers (2006)

This paper presents a general approach for designing array and tree integer multipliers with overflow detection. The overflow detection techniques are based on an analysis of the magnitudes of the input operands. The overflow detection circuits operate in parallel with a simplified multiplier to reduce the overall area and delay.
Graphics and the Understanding of Perceptual Mechanisms: Analogies and Similarities
Authors: Lilia Hess, Brian Mayoh
Venue: Proceedings of the conference on Geometric Modeling and Imaging: New Trends (2006)

Graphics give an alternative representation model for images and graphic rewriting gives another viewpoint for image matching, image retrieval and identity of shape constancy - all subjects that have raised passionate discussion of mathematical models for both machine and human vision[1,2,3,4,5,6,7,8]. A graphic is a graph where all vertices get both a label and other attribute values from a \sum-algebra, so our graphic grammars are a particular kind of attributed graph grammar: Hess et al [9,10]. Attributed graph grammars are a powerful way of describing transformations of complex structures. Many kinds of attributed graph grammars have been studied but they all seem to describe graph transformations as pushouts in an adhesive HLR category [11], so they enjoy such desirable theoretic properties as locally Church-Rosser and Ehrig Parallelism and Concurrency [12]. Attributed graph grammars have been applied to describe visual languages [13], distributed systems [14], chemical reactions [15], music analysis [16] and much else. In this paper we describe a new application: analysis of how we perceive shape and motion.
Efficient Built-In Self-Test Schemes for Video Coding Cores: a Case Study on DCT/IDCT Circuits
Authors: Shyue-Kung Lu, Ting-Yu Chen, Wei-Yuan Liu
Venue: Proceedings of the 12th Pacific Rim International Symposium on Dependable Computing (2006)

Owing to the rapid advance in semiconductor fabrication technology, a large number of transistors can be incorporated onto a single chip. However, this will reduce the controllability and observability of the chip significantly. Consequently, testing such highly complex and dense circuits becomes very difficult and expensive. Therefore, we propose an efficient design-for-testability technique based on M-testability conditions for the 2D systolic DCT/IDCT processors in this paper. The cell fault model is adopted. For chip testing consideration, we modify the processing elements of the 2D array and make the module function bijective. The proposed DFT technique is also suitable for BIST implementation. The test pattern generator is simply a binary counter. Moreover, the adders and registers in each processing element can be combined as signature analyzers to perform accumulation and compression operations to evaluate the signatures during different test sessions. The signatures for each test session are stored in each processing element and propagated to the primary outputs when the test session is finished. An experimental chip is designed and implemented with Synopsys synthesis tools. Experimental results show that the hardware overhead of the BIST architecture for 2D DCT/IDCT architectures is less than 10%. The fault coverage of each processing element can achieve 98.18%.
An Improved Distance Heuristic Function for Directed Software Model Checking
Authors: Neha Rungta, Eric G. Mercer
Venue: Proceedings of the Formal Methods in Computer Aided Design (2006)

State exploration in directed software model checking is guided using a heuristic function to move states near errors to the front of the search queue. Distance heuristic functions rank states based on the number of transitions needed to move the current program state into an error location. Lack of calling context information causes the heuristic function to underestimate the true distance to the error; however, inlining functions at call sites in the control flow graph to capture calling context leads to an exponential growth in the computation. This paper presents a new algorithm that implicitly inlines functions at call sites to compute distance data with unbounded calling context that is polynomial in the number of nodes in the control flow graph. The new algorithm propagates distance data through call sites during a depth-first traversal of the program. We show in a series of benchmark examples that the new heuristic function with unbounded distance data is more efficient than the same heuristic function that inlines functions at their call sites up to a certain depth.
A server performance model for static Web workloads
Authors: K. Kant
Venue: Proceedings of the 2000 IEEE International Symposium on Performance Analysis of Systems and Software (2000)

The paper describes a queuing network model for a multiprocessor system running a static Web workload such as SPECweb96. The model includes architectural details of the Web server in terms of multilevel cache hierarchy, processor bus, memory pipeline, PCI bus based I/O subsystem, and bypass I/O-memory path for DMA transfers. The model is based on detailed measurements from a baseline system and a few of its variants. The model operates at the Web transaction level, and does not explicitly model the CPU core or the caching hierarchy. Yet, the model predicts the performance impact of low level features such as number of processors, processor speeds, cache sizes and latencies, memory latencies, higher level caches, sector prefetching, etc. The model shows an excellent match with measured results. Because of many features that are difficult to handle analytically, the default solution technique is simulation. However, the paper also proposes a simple hybrid approach that can significantly speed up the solution without affecting the accuracy appreciably. The model has also been extended to handle clusters of symmetric multiprocessor systems with both centralized and distributed memories.
Study of the impact of winding form and film thickness on thin-film inductors
Authors: Xiao-Li Tang, H. W. Zhang, H. Su, Y. Shi, X. D. Jiang
Venue: Microelectronic Engineering (2005)

Using a DC-magnetron sputtering system, we fabricated several forms of double-sided coupling thin-film inductors on a PCB (Printed Circuit Board). Due to the effects of winding forms and thickness of the film, the inductance, Q factor and resonance frequency of the inductors are different. Of the three types of inductors covering the same area, the meander inductor has the highest resonance frequency (up to 400 MHz), the circular-spiral inductor has the largest inductance (up to 1 @mH/cm^2) and Q factor (up to 25) at low frequency, and the hexagon-spiral inductor has moderate inductance and Q factor at an intermediate frequency. So the proper choice of winding form will depend on the specific application.
Bustle: Using Hitchhiking to Monitor Meaningful Locations
Authors: Karen P. Tang, James Fogarty, Pedram Keyani, Jason I. Hong
Venue: Proceedings of the Seventh IEEE Workshop on Mobile Computing Systems & Applications (2006)

Hitchhiking is a client-focused, software-based approach to anonymous and privacy-sensitive collection of sensed data in location-based applications. In this paper, we demonstrate hitchhiking by implementing a WiFi-based locationcentric service called Bustle. Using only software sensors, Bustle models the busyness of coffee shops while incorporating hitchhiking principles to protect the anonymity and privacy of the application users.
Dissociations in Processing Past Tense Morphology: Neuropathology and Behavioral Studies
Authors: Lorraine K. Tyler, Paul Demornay-davies, Rebekah Anokhina, Catherine Longworth, Billi Randall, William D. Marslen-wilson
Venue: Journal of Cognitive Neuroscience (2002)

Neuropsychological research showing that the regular ("jump-jumped") and irregular ("drive/drove") past tense inflectional morphology can dissociate following brain damage has been important in testing claims about the cognitive and neural status of linguistic rules. These dissociations have been interpreted as evidence for two different computational systems&mdash;a rule-based system underlying the processing of regulars and the irregulars being individually listed in the mental lexicon. In contrast, connectionist accounts claim that these dissociations can be modeled within a single system. Combining behavioral data from patients with detailed information about their neuropathology can, in principle, provide strong constraints on accounts of the past tense. In this study, we tested five nonfluent aphasic patients, all of whom had extensive left hemisphere (LH) damage involving the left inferior frontal gyrus and underlying structures, and four patients with semantic deficits following herpes simplex encephalitis (HSE) who had extensive damage to the inferior temporal cortex. These patients were tested in experiments probing past tense processing. In a large priming study, the nonfluent patients showed no priming for the regular past tense but significant priming for the irregulars (whereas controls show priming for both). In contrast, the HSE patients showed significantly impaired performance for the irregulars in an elicitation task. These patterns of behavioral data and neuropathology suggest that two separable but interdependent systems underlie processing of the regular and irregular past tense.