ppxscal/embedding_network huggingface dataset:
Partitioning programs for parallel execution
Authors: M. Girkar, C. Polychronopoulos
Venue: Proceedings of the 2nd international conference on Supercomputing (1988)

The ability of parallel computers to execute multiple instruction streams (tasks) simultaneously gives rise to the problem of partitioning a program into a set of tasks that can be assigned to different processors. The degree to which parallelism can be exploited, the amount of overhead involved during parallel execution of a program and a number of other factors depend directly on partitioning. A good partitioning scheme must take into account all these factors. In this paper we present algorithms to compute optimal partitions in diverse models of the problem. Both directed and undirected graph representations of a parallel program are considered. For some instances of the problem where practical optimal schemes are not possible we suggest simple and efficient heuristics. Finally, a polynomial time algorithm to compute optimal partitions for chains is given.
Comments on 'Signature Analysis for Multiple Output Circuits' by R. David
Authors: R. David
Venue: IEEE Transactions on Computers (1990)

The probability of a fault-free signature has been calculated in the above-named paper and in an earlier paper by the same author. Implicitly, it was considered as the probability of masking due to signature analysis. It is shown here that this does not correspond exactly to the probability of aliasing. A new definition is given. The difference centers on the event where there are no bit errors in the data to be compressed. When the response of the circuit is correct, the signature is fault-free. However, there is no aliasing.
Primitives for Distributed Computing in a Heterogeneous Local Area Network Environment
Authors: G. Bernard, A. Duda, Y. Haddad, G. Harrus
Venue: IEEE Transactions on Software Engineering (1989)

Epsilon is a testbed for monitoring distributed applications involving heterogeneous computers, including microcomputers, interconnected by a local area network. Such a hardware configuration is usual but raises difficulties for the programmer. First, the interprocess communication mechanisms provided by the operating systems are rather cumbersome to use. Second, they are different from one system to another. Third, the programmer of distributed applications should not worry about system and/or network aspects that are not relevant for the application level. The authors present the solution chosen in Epsilon. A set of high-level communication primitives has been designed and implemented to provide the programmer with an interface independent of the operating system and of the underlying interprocess communications facilities. A program participating in a distributed application can be executed on any host without any change in the source code except for host names.
Via Assignment in Single-Row Routing
Authors: J. Bhasker, S. Sahni
Venue: IEEE Transactions on Computers (1989)

Examines the via assignment problem that arises when the single-row routing approach to the interconnection problem is used. Some new complexity results and two new heuristics are obtained. Experimental results establish the superiority of the new heuristics over earlier ones.
A scheduling and resource allocation algorithm for hierarchical signal flow graphs
Authors: M. Potkonjack, J. Rabaey
Venue: Proceedings of the 26th ACM/IEEE Design Automation Conference (1989)

The paper describes a new algorithm for the scheduling and resource allocation problem in high-level synthesis. The algorithm can not only efficiently treat flattened signal flow graphs, but also handles graphs with embedded control constructs such as conditional branches and loops. Based on simple and clear, but powerful principles, the algorithm simultaneously minimizes the number of execution units, the number of registers and the amount of interconnections. The algorithm has been implemented and we present the first results, which are very promising.
A survey of fast packet switches
Authors: Andrew R. Jacob
Venue: ACM SIGCOMM Computer Communication Review (1989)

With the advent of optical fiber and its large bandwidth, many services, such as packetized data, voice, and video, are now becoming available on physical transmission lines. The high data rates, however, have created a demand for high speed switching. Included among the different strategies which have been proposed are fully- and non-fully-connected switches, intelligent and non-intelligent switching nodes, broadcast capability, input and output queueing, input concentration and output reentry, and path preallocation. Most switches have a modular design. This paper compares the Knockout Switch [1], a switch designed by Jonathan Turner [2, 3], a switch designed by Joseph Hui and Edward Arthurs [4], and the Starlite Switch [5] based on the strategies listed above. Advantages and disadvantages are cited and conclusions have been made about the tradeoffs involved with operating conditions. Finally, future issues affecting fast packet switching are described.
Maintaining state constraints in relational databases: a proof theoretic basis
Authors: William W. McCune, Lawrence J. Henschen
Venue: Journal of the ACM (JACM) (1989)

If a relational database is required to satisfy a set of integrity constraints, then when the database is updated, one must ensure that it continues to satisfy the constraints. It is desirable not to have to evaluate each constraint after each update. A method is described that takes a constraint C and a class of updates, and either proves that an update in the class cannot violate C, or produces a formula C' (a complete test) that is satisfied before the update if and only if C would continue to be satisfied were the update to occur. C' is frequently much easier to evaluate than C. In addition, a formula D (a sufficient test) is sometimes produced such that if D is satisfied before the update, then C would continue to be satisfied were the update to occur. The method is proved correct. The method is substantially more general than other reported techniques for this problem. The method has been implemented, and a number of experiments with the implementation are presented.
Causes of motivational problems among AI managers
Authors: J. D. Couger, S. C. McIntyre
Venue: Proceedings of the ACM SIGCPR conference on Management of information systems personnel (1988)

A survey of members of the American Association of Artificial Intelligence revealed that AI managers perceived their jobs less motivational than do their subordinates. A second survey was undertaken to ascertain the causes. Seven principal causes were postulated and a structured interview was conducted with 22 AI managers, the majority of whom were first-line managers. The results showed that almost three-quarters would rather be doing AI work than managing it. Two-thirds were dissatisfied with the current technology in AI. In addition, in most cases the applications chosen for initial demonstration of the validity of AI were not challenging. In some companies there are jurisdictional problems concerning which organizations should have principal responsibility for developing AI applications. Also revealed in the survey was a threshold of new problems which will make motivation even more difficult. Although the survey sample is small, it provided enough information to be able to suggest approaches for improving motivation.
Program optimization for instruction caches
Authors: S. McFarling
Venue: ACM SIGARCH Computer Architecture News (1989)

This paper presents an optimization algorithm for reducing instruction cache misses. The algorithm uses profile information to reposition programs in memory so that a direct-mapped cache behaves much like an optimal cache with full associativity and full knowledge of the future. For best results, the cache should have a mechanism for excluding certain instructions designated by the compiler. This paper first presents a reduced form of the algorithm. This form is shown to produce an optimal miss rate for programs without conditionals and with a tree call graph, assuming basic blocks can be reordered at will. If conditionals are allowed, but there are no loops within conditionals, the algorithm does as well as an optimal cache for the worst case execution of the program consistent with the profile information. Next, the algorithm is extended with heuristics for general programs. The effectiveness of these heuristics are demonstrated with empirical results for a set of 10 programs for various cache sizes. The improvement depends on cache size. For a 512 word cache, miss rates for a direct-mapped instruction cache are halved. For an 8K word cache, miss rates fall by over 75%. Over a wide range of cache sizes the algorithm is as effective as increasing the cache size by a factor of 3 times. For 512 words, the algorithm generates only 32% more misses than an optimal cache. Optimized programs on a direct-mapped cache have lower miss rates than unoptimized programs on set-associative caches of the same size.
The RGYB color geometry
Authors: Colin Ware, William Cowan
Venue: ACM Transactions on Graphics (TOG) (1990)

Background:The gamut of a color CRT is defined by its three primary colors, each produced by a phosphor/electron gun combination. Light from the primaries combines additively, so the color gamut is a subset of a three dimensional vector space [1]. With the primaries as basis vectors normalized to 1.0, the color gamut is a unit cube, known as the RGB color geometry, since the three primaries are usually red, green, and blue. User interaction via RGB is generally thought to be counterintuitive, and transformations of RGB, such as Smith's HSV geometry [10] which is derived from centuries old artists' models [2], are more popular. More recent color theories, based on psychophysical and physiological models of early visual processing, suggest that more intuitive geometries may be possible. The RGYB geometry is based on two recent discoveries about the human visual system. First, the three color signals from the cone receptors are organized into three opponent channels [1, 7]. A single achromatic channel indicates lightness or brightness. Two chromatic channels, red/green and yellow/blue, signal the chromatic quantities. Second, signals on the achromatic channel are easily distinguishable from signals on the chromatic ones [6]. Consequently, it is usual to represent colors as a set of surfaces of colors that vary in chromaticity, each at a different level of brightness. Examples are as diverse as CIE chromaticity coordinates, the CIELUV uniform color space, the Munsell color system, and computer graphics color spaces such as HSV and HLS [10, 12].
The use of inverse layout trees for hierarchical design rule checking
Authors: N. Hedenstierna, K. O. Jeppson
Venue: Proceedings of the 26th ACM/IEEE Design Automation Conference (1989)

The inverse layout tree concept is used to perform fully hierarchical DRC without any constraints on the use of overlapping or incomplete cells that are completed at higher levels of hierarchy. Hierarchy is preserved and design rule violations are displayed in the cell where they should be corrected. The DRC is corner-based and processes 200-800 corners/second on a VAX 11/750.
Analysis of Faults in an N-Version Software Experiment
Authors: Susan S. Brilliant, John C. Knight, Nancy G. Leveson
Venue: IEEE Transactions on Software Engineering (1990)

The authors have conducted a large-scale experiment in N-version programming. A total of 27 versions of a program were prepared independently from the same specification at two universities. The results of executing the versions revealed that the versions wereindividually extremely reliable but that the number of input cases in which more than one failed was substantially more than would be expected if they were statistically independent. After the versions had been executed, the failures of each version were examined and the associated faults located. It appears that minor differences in the software development environment would not have a major impact in reducing the incidence of faults that cause correlated failures.
A Queueing Network Model for a Distributed Database Testbed System
Authors: Bao-Chyuan Jenq, Walter H. Kohler, Don Towsley
Venue: IEEE Transactions on Software Engineering (1988)

A queuing network model for analyzing the performance of a distributed database testbed system with a transaction workload is developed. The model includes the effects of the concurrency control protocol (two-phase locking with distributed deadlock detection), the transaction recovery protocol (write-ahead logging of before-images), and the commit protocol (centralized two-phase commit) used in the testbed system. The queuing model differs from previous analytical models in three major aspects. First, it is a model for a distributed transaction processing system. Second, it is more general and integrated than previous analytical models. Finally, it reflects a functioning distributed database testbed system and is validated against performance measurements.
Analysis of Self-Stabilizing Clock Synchronization by Means of Stochastic Petri Nets
Authors: Meiliu Lu, Du Zhang, Tadao Murata
Venue: IEEE Transactions on Computers (1990)

A model for analyzing a FCS (fault-tolerant clock synchronization) system of the type supported by a statistical self-diagnosis is described. Once a self-diagnosis scheme is integrated into an FCS design, the problem of controlling and measuring the system's self-stability arises. A stochastic Petri net (SPN) model is constructed to derive the self-stability measures of such FCS systems. An example is given to demonstrate the entire modeling and analyzing procedure. The mapping from SPN model to Markov model shown in an example can be automated by using an SPN software package. The results show that the SPN model is an excellent tool for obtaining self-stability measures and that several important system features, such as synchronization and parallelism, can be modeled using the SPN method in a much clearer manner than they can be modeled using other available tools.
Color-coding categories in menus
Authors: J. E. McDonald, M. E. Molander, R. W. Noel
Venue: Proceedings of the SIGCHI conference on Human factors in computing systems (1988)

Categorical menu layouts are currently designed according to conventions and opinions, rather than by employing formal techniques. In this paper we describe a formal methodology for categorically organizing menus. We go on to show how color-coding can be applied to these layouts either to emphasize organization or to provide additional information. The results of a controlled study comparing layouts based on frequency of co-occurrence and similarity show that the formal menu-layout methodology is effective. However, the use of color-coding to identify categories is not supported. Potential reasons for this failure are discussed.
Methods for knowledge acquisition and refinement in second generation expert systems
Authors: Nada Lavrac, Igor Mozetic
Venue: Issue 108 (April 1989) (1989)

First generation expert systems rely on the use of surface knowledge, such as associational or heuristic. Second generation technology is characterized by two additional features: deep knowledge and machine learning. Three second generation methods for knowledge acquisition are reviewed: learning rules from examples, model-based rule learning, and semi-automatic model acquisition. The man-machine process of acquiring and refining knowledge extends the role of expert systems to expert support systems, since both man and machine learn through repeated knowledge refinement cycles. Explanation of solutions and of the knowledge base itself is crucial for this man-machine learning process. An extended expert system shell schema is presented that includes a knowledge acquisition and a knowledge explanation module.
Laying the foundations for computer science
Authors: L. A. Larsen
Venue: ACM SIGCSE Bulletin (1989)

This paper has three primary goals: Stimulate the discussion of possible skills which might be incorporated into the K-12 curriculum in order to provide students with a foundation for the study of computer science. Stimulate the discussion of strategies for incorporating into the K-12 curriculum the fundamental skills needed by students pursuing topics in the computer science discipline. Present a possible set of fundamental skills.
Bisimulation can't be traced
Authors: B. Bloom, S. Istrail, A. R. Meyer
Venue: Proceedings of the 15th ACM SIGPLAN-SIGACT symposium on Principles of programming languages (1988)

Bisimulation is the primitive notion of equivalence between concurrent processes in Milner's Calculus of Communicating Systems (CCS); there is a nontrivial game-like protocol for distinguishing nonbisimular processes. In contrast, process distinguishability in Hoare's theory of Communicating Sequential Processes (CSP) is determined solely on the basis of traces of visible actions. We examine what additional operations are needed to explain bisimulation similarly&mdash;specifically in the case of finitely branching processes without silent moves. We formulate a general notion of Structured Operational Semantics for processes with Guarded recursion (GSOS), and demonstrate that bisimulation does not agree with trace congruence with respect to any set of GSOS-definable contexts. In justifying the generality and significance of GSOS's, we work out some of the basic proof theoretic facts which justify the SOS discipline.
Unidirectional Byte Error Detecting Codes for Computer Memory Systems
Authors: L. A. Dunning, M. R. Varanasi, G. Dial
Venue: IEEE Transactions on Computers (1990)

Codes are developed for detecting unidirectional errors in t bytes simultaneously (t-UBED) while also providing all unidirectional error detection (AUED). These classes of codes differ from purely all unidirectional error detecting codes in that the errors in one byte may be of the form 1 to 0, while in another byte they may be of the form 0 to 1. The codes utilize 2 B for parity check information. As an example, a code providing 3-UBED+AUED protection for up to 12 information bytes of 8 b each can be constructed.
Binary partitions with applications to hidden surface removal and solid modelling
Authors: M. S. Paterson, F. F. Yao
Venue: Proceedings of the fifth annual symposium on Computational geometry (1989)

We consider schemes for recursively dividing a set of geometric objects by hyperplanes until all objects are separated. Such a binary partition is naturally considered as a binary tree where each internal node corresponds to a division and the leaves correspond to the resulting fragments of objects. The goal is to choose the hyperplanes properly so that the size of the binary partition, i.e., the number of resulting fragments of the objects, is minimized. We construct binary partitions of size &Ogr;(n log n) for n edges in the plane, and of size &Ogr;(n) if the edges are orthogonal. In three dimensions, we obtain binary partitions of size &Ogr;(n2) for n planar facets, and prove a lower bound of &OHgr;(n3/2). Two applications of efficient binary partitions are given. The first is an &Ogr;(n2)-sized data structure for implementing a hidden-surface removal scheme of Fuchs, Kedem and Naylor [5]. The second application is in solid modelling: given a polyhedron described by its n faces, we show how to generate an &Ogr;(n2)-sized CSG (constructive-solid-geometry) formula whose literals correspond to half-spaces supporting the faces of the polyhedron (see Peterson [9] and Dobkin et al. [3]). The best previous results for both of these problems were &Ogr;(n3).
Generating sequential code from parallel code
Authors: J. Ferrante, M. Mace, B. Simons
Venue: Proceedings of the 2nd international conference on Supercomputing (1988)

We consider the problem of generating sequential code for parallel programs written in a language which contains a FORALL operator, predicates and statements. This problem can arise when compiling for a multiprocessor where each processor is sequential, and in the vectorization of sequential programs. We present a necessary and sufficient condition for determining if extra guard variables or duplicate code must be inserted when generating a correct sequential program from a given, well-structured parallel program. We also have an efficient method for checking whether this condition occurs in the parallel program. This method gives rise to an algorithm for generating sequential code from parallel code which inserts guard variables (or duplicate code) only when determined by our necessary and sufficient condition. Given the choice to insert duplicate code, an exponential blow-up in size may result. We suggest some simple heuristics to limit such blow-up. We also show that in a restricted case, the minimal size sequential code can be efficiently generated. However, we show that a problem closely related to finding the minimal size sequential code (or equivalently, the minimum number of guards to be inserted) in NP-Complete. We conjecture that this problem in the general case is indeed NP-Complete.
Correspondenceless Stereo and Motion: Planar Surfaces
Authors: J. Aloimonos, J.-Y. Hervé
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1990)

It is shown that a binocular observer can recover the depth and three-dimensional motion of a rigid planar patch without using any correspondences between the left and right image frames (static) or between the successive dynamic frames (dynamic). Uniqueness and robustness issues are studied with respect to this problem and experimental results are given from the application of the theory to real images.
Extending Ina Jo with Temporal Logic
Authors: Jeannette M. Wing, Mark R. Nixon
Venue: IEEE Transactions on Software Engineering (1989)

The authors give both informal and formal descriptions of both the current Ina Jo specification language and Ina Jo enhanced with temporal logic. They include details of a simple example to demonstrate the use of the proof system and details of an extended example to demonstrate the expressiveness of the enhanced language. The authors discuss their language design goals, decisions, and their implications.
Neural networks: a new technolgy for information processing
Authors: C. Klimasauskas
Venue: ACM SIGMIS Database (1989)

Neural networks are an innovative approach to information processing. Their characteristics lend themselves to directed analysis of the contents of computer data-bases. Potential payoffs from this include increased sales, decreased risk, and improved profitability. This presentation includes a brief look at the technology with an emphasis on providing a basic understanding of its characteristics and how they can be applied.