ppxscal/embedding_network huggingface dataset:
Talking in circles: designing a spatially-grounded audioconferencing environment
Authors: Roy Rodenstein, Judith S. Donath
Venue: Proceedings of the SIGCHI conference on Human factors in computing systems (2000)

This paper presents Talking in Circles, a multimodal audioconferencing environment whose novel design emphasizes spatial grounding with the aim of supporting naturalistic group interaction behaviors. Participants communicate primarily by speech and are represented as colored circles in a two-dimensional space. Behaviors such as subgroup conversations and social navigation are supported through circle mobility as mediated by the environment and the crowd and distance-based attenuation of the audio. The circles serve as platforms for the display of identity, presence and activity: graphics are synchronized to participants' speech to aid in speech-source identification and participants can sketch in their circle, allowing a pictorial and gestural channel to complement the audio. We note user experiences through informal studies as well as design challenges we have faced in the creation of a rich environment for computer-mediated communication.
Supporting diversity with component frameworks as architectural elements
Authors: Jan Gerben Wijnstra
Venue: Proceedings of the 22nd international conference on Software engineering (2000)

In this paper, we describe our experience with component frameworks within a family architecture for a medical imaging product family. The component frameworks are handled as an integral part of the architectural approach and are an important means to support diversity in the functionality provided by the individual family members.This paper focuses on a particular kind of component framework that has been applied throughout the medical imaging product family. This kind of framework is useful when the various family members are based on the same concepts and the diversity is formed by the differences in the specific instances of these concepts that are present in the family members. These component frameworks have a number of similarities, allowing a standardised approach to their development. They support the division of the system into a generic architectural skeleton, which can be extended with plug-ins to realise specific family members, each with their own set of features.
Authoring animated Web pages using &ldquo;contact points&rdquo;
Authors: Pete Faraday, Alistair Sutcliffe
Venue: Proceedings of the SIGCHI conference on Human factors in computing systems: the CHI is the limit (1999)

This paper explores how contact points or co-references between an animation and text should be designed in web pages. Guidelines are derived from an eye tracking study. A dynamic HTML authoring tool is described which supports these requirements. An evaluation study is reported in which four designs of animation in web pages were tested.
Comparing lower bounds on messages and rounds for two classes of key establishment protocols
Authors: Anish Mathuria
Venue: ACM SIGCOMM Computer Communication Review (1998)

An important requirement in designing protocols for key establishment is to provide assurance to protocol participants that a session key is fresh. This paper compares lower bounds on messages and rounds for two classes of protocols based on fundamentally different methods for achieving session key freshness.
Chameleon: A Software Infrastructure for Adaptive Fault Tolerance
Authors: Zbigniew T. Kalbarczyk, Ravishankar K. Iyer, Saurabh Bagchi, Keith Whisnant
Venue: IEEE Transactions on Parallel and Distributed Systems (1999)

This paper presents Chameleon, an adaptive infrastructure, which allows different levels of availability requirements to be simultaneously supported in a networked environment. Chameleon provides dependability through the use of special ARMORs¿Adaptive, Reconfigurable, and Mobile Objects for Reliability¿that control all operations in the Chameleon environment. Three broad classes of ARMORs are defined: 1) Managers oversee other ARMORs and recover from failures in their subordinates. 2) Daemons provide communication gateways to the ARMORs at the host node. They also make available a host's resources to the Chameleon environment. 3) Common ARMORs implement specific techniques for providing application-required dependability. Employing ARMORs, Chameleon makes available different fault-tolerant configurations and maintains run-time adaptation to changes in the availability requirements of an application. Flexible ARMOR architecture allows their composition to be reconfigured at run-time, i.e., the ARMORs may dynamically adapt to changing application requirements. In this paper, we describe ARMOR architecture, including ARMOR class hierarchy, basic building blocks, ARMOR composition, and use of ARMOR factories. We present how ARMORs can be reconfigured and reengineered and demonstrate how the architecture serves our objective of providing an adaptive software infrastructure. To our knowledge, Chameleon is one of the few real implementations which enables multiple fault tolerance strategies to exist in the same environment and supports fault-tolerant execution of substantially off-the-shelf applications via a software infrastructure only. Chameleon provides fault tolerance from the application's point of view as well as from the software infrastructure's point of view. To demonstrate the Chameleon capabilities, we have implemented a prototype infrastructure which provides set of ARMORs to initialize the environment and to support the dual and TMR application execution modes. Through this testbed environment, we measure the execution overhead and recovery times from failures in the user application, the Chameleon ARMORs, the hardware, and the operating system.
Fast-software-checkpointing in optimistic simulation: embedding state saving into the event routine instructions
Authors: Francesco Quaglia
Venue: Proceedings of the thirteenth workshop on Parallel and distributed simulation (1999)

In this paper we present a software approach, namely Fast-Software-Checkpointing (FSC), to reduce the running time of the state saving protocol in optimistic parallel discrete event simulation. The idea behind FSC is to use the instructions performed during the execution of an event as part of the state saving protocol, hence the total number of instructions due to state saving is reduced. Under FSC the time for saving the state of a logical process prior to the execution of an event e requires an amount of time proportional to the amount of state variables not updated by e's execution, as only these variables must be copied. This outlines that FSC shows some dualism with respect to incremental state saving. We show, however, that there exists a basic difference between the two solutions as in FSC some of the state saving instructions are actually event routine instructions, while in incremental state saving they are only added and mixed to the latter ones. We also present a simple software architecture to support FSC and simulation results to demonstrate the effectiveness of such solution. The obtained data show that FSC, combined with a sparse state saving strategy, may represent the best checkpointing solution in case of both medium/small state granularity simulations and large state granularity simulations even with small (but non-minimal) portions of the state updated by event execution. FSC may result therefore suited for a wide class of simulation problems.
Noise Analysis of Switched-Current Circuits
Authors: Ivan H. H. Jørgensen, Gudmundur Bogason
Venue: Analog Integrated Circuits and Signal Processing (1999)

The understanding of noise in analog sampled data systems is vital for the design of high resolution circuitry in the discrete time domain. In this paper a general description of sampled and held noise is presened. The noise calculations are verified by measurements on an analog delay line implemented using switched-current (SI) technique. The SI delay line is based on a new topology current copier (CCOP). For the verification of the theory a new measurement technique is used. This technique enables one to measure the power spectral density of sampled and held noise which is below the continuous time noise floor.
Programming Languages in Economics
Authors: David A. Kendrick, Hans M. Amman
Venue: Computational Economics (1999)

Young economists sometimes ask which computer programming languages they should learn. This paper answers that question by suggesting that they begin with a high level language like GAUSS, GAMS, Mathematica, Maple or MATLAB depending on their field of specialization in economics. Then they should work down to one of the low level languages such as Fortran, Basic, C, C++ or Java depending on the planned areas of application. Finally, they should proceed to the languages which are used to develop graphical interfaces and internet applications, viz. Visual Basic, C, C++ or Java.
Monitoring Changes in Home Health Care: A Comparison of Two National Surveys
Authors: Ross M. Mullner, Mark A. Jewell, Murray A. Mease
Venue: Journal of Medical Systems (1999)

Home health care is the fastest growing component of medical care in the United States. To understand better the nature and scope of changes taking place in home health, two current national surveys are described and compared. The two federally sponsored surveys are the National Home and Hospice Care Survey (NHHCS) conducted by the National Center for Health Statistics and the Medical Expenditure Panel Survey (MEPS) of the Agency for Health Care Policy and Research. Computer data files from both surveys are publicly available.
A type system for Java bytecode subroutines
Authors: Raymie Stata, Martin Abadi
Venue: ACM Transactions on Programming Languages and Systems (TOPLAS) (1999)

Java is typically compiled into an intermediate language, JVML, that is interpreted by the Java Virtual Machine. Because mobile JVML code is not always trusted, a bytecode verifier enforces static constraints that prevent various dynamic errors. Given the importance of the bytecode verifier for security, its current descriptions are inadequate. This article proposes using typing rules to describe the bytecode verifier because they are more precise than prose, clearer than code, and easier to reason about than either. JVML has a subroutine construct which is used for the compilation of Java's try-finally statement. Subroutines are a major source of complexity for the bytecode verifier because they are not obviously last-in/first-out and because they require a kind of polymorphism. Focusing on subroutines, we isolate an interesting, small subset of JVML. We give typing rules for this subset and prove their correctness. Our type system constitutes a sound basis for bytecode verification and a rational reconstruction of a delicate part of Sun's bytecode verifier.
Model-based and empirical evaluation of multimodal interactive error correction
Authors: Bernhard Suhm, Brad Myers, Alex Waibel
Venue: Proceedings of the SIGCHI conference on Human factors in computing systems: the CHI is the limit (1999)

Our research addresses the problem of error correction in speech user interfaces. Previous work hypothesized that switching modality could speed up interactive correction of recognition errors (so-called multimodal error correction). We present a user study that compares, on a dictation task, multimodal error correction with conventional interactive correction, such as speaking again, choosing Tom a list, and keyboard input. Results show that multimodal correction is faster than conventional correction without keyboard input, but slower than correction by typing for users with good typing skills. Furthermore, while users initially prefer speech, they learn to avoid ineffective correction modalities with experience. To extrapolate results from this user study we developed a performance model of multimodal interaction that predicts input speed including time needed for error correction. We apply the model to estimate the impact of recognition technology improvements on correction speeds and the influence of recognition accuracy and correction method on the productivity of dictation systems. Our model is a first step towards formalizing multimodal (recognition-based) interaction.
An empirical study of TCP&ndash;IP performance over FR&ndash;ATM service interworking
Authors: Isil Sebüktekin
Venue: International Journal of Network Management (1998)

This article outlines some basic performance characteristics of the Transmission Control Protocol&ndash;Internet Protocol &lpar;TCP&ndash;IP&rpar; over Frame Relay&ndash;Asynchronous Transfer Mode &lpar;FR&ndash;ATM&rpar; Service Interworking. The cconclusions are based on empirical TCP&sol;IP performance test results collected on a FR&rdquo;ATM Service Interworking testbed, architected with commercially available IP, FR, and ATM equipment. &copy; 1998 John Wiley Sons, Ltd.
Using a wearable computer for continuous learning and support
Authors: Lawrence J. Najjar, Chris Thompson, Jennifer J. Ockerman
Venue: Mobile Networks and Applications (1999)

A wearable computer with an electronic performance support system can provide continuous learning and support to mobile workers. This system allows mobile users to ask for advice, receive instruction, access productivity tools, communicate with others, and assess their knowledge on a continuous basis. Workers can get this support when they need it, where they need it. Compared to traditional training and support, this new technique may provide substantial performance improvements. We are developing an architecture for this type of support system and are currently investigating the use of this system to help mobile factory workers perform their tasks.
Fast Convergent Generalized Back-Propagation Algorithm with Constant Learning Rate
Authors: S. C. Ng, S. H. Leung, A. Luk
Venue: Neural Processing Letters (1999)

The conventional back-propagation algorithm is basically a gradient-descent method, it has the problems of local minima and slow convergence. A new generalized back-propagation algorithm which can effectively speed up the convergence rate and reduce the chance of being trapped in local minima is introduced. The new back-propagation algorithm is to change the derivative of the activation function so as to magnify the backward propagated error signal, thus the convergence rate can be accelerated and the local minimum can be escaped. In this letter, we also investigate the convergence of the generalized back-propagation algorithm with constant learning rate. The weight sequences in generalized back-propagation algorithm can be approximated by a certain ordinary differential equation (ODE). When the learning rate tends to zero, the interpolated weight sequences of generalized back-propagation converge weakly to the solution of associated ODE.
Robust optimization based backtrace method for analog circuits
Authors: Alfred V. Gomes, Abhijit Chatterjee
Venue: Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design (1999)

In this paper, we propose a new robust approach to signal backtrace for efficiently testing embedded analog modules in a large system. The proposed signal backtrace method is formulated as a solution to a multi-point boundary value problem (BVP), with constraints on the output state and the input. This error constraint minimizes large spurious deviations in the input signal and the corvergence problems that arise if multiple solutions exist or if the desired signal does not exist in the feasible signal space. As an additional attractive advantage, this formulation preserves the core iteration structure of a SPICE-like simulator without modifications, greatly easing implementation.
Bregman Proximal Relaxation of Large-Scale 0&ndash;1 Problems
Authors: Krzysztof C. Kiwiel, P. O. Lindberg, Andreas Nõu
Venue: Computational Optimization and Applications (2000)

We apply a recent extension of the Bregman proximal method for convex programming to LP relaxations of 0&ndash;1 problems. We allow inexact subproblem solutions obtained via dual ascent, increasing their accuracy successively to retain global convergence. Our framework is applied to relaxations of large-scale set covering problems that arise in airline crew scheduling. Approximate relaxed solutions are used to construct primal feasible solutions via a randomized heuristic. Encouraging preliminary experience is reported.
Measuring the allocation of control in a 6 degree-of-freedom docking experiment
Authors: Maurice R. Masliah, Paul Milgram
Venue: Proceedings of the SIGCHI conference on Human factors in computing systems (2000)

Coordination definitions and metrics are reviewed from the motor control, biomedical, and human factors literature. This paper presents an alternative measurement called the M-metric, the product of the simultaneity and efficiency of a trajectory, as a means of quantifying allocation of control within a docking task. A 6 degree-of-freedom (DOF) longitudinal virtual docking task experiment was conducted to address how control is allocated across six DOFs, how allocation of control changes with extended practice, and if differences in the allocation of control are input device dependent. The results show that operators, rather than controlling all 6 DOFs equally, allocate their control to the rotational and translational DOFs separately, and switch control between the two groups. With practice, allocation of control within the translational and rotational subsets increases at a faster rate than across all 6 DOFs together.
Instruction-level power estimation for embedded VLIW cores
Authors: M. Sami, D. Sciuto, C. Silvano, V. Zaccaria
Venue: Proceedings of the eighth international workshop on Hardware/software codesign (2000)

In this paper, a power estimation methodology operating at the instruction-level is proposed. The methodology is tightly related to the characteristics of the system architecture, mainly in terms of one or more target processors, the memory sub-system, the system-level buses and the coprocessors. In this system-level framework, our main goal is to define a power model for CPU cores at the instruction-level. First, the proposed power model deals with a general five-stage pipeline processor architecture, then, the model is extended to VLIW processors. The derivation of a VLIW instruction-level power model results to be intractable from the point of view of spatial complexity (which grows exponentially w.r.t. the number of possible operations in the ISA). In order to tackle this complexity, a new kind of simplification, based on the original concept of separability of processor functional units, is introduced. The proposed system-level methodology is the first step toward a more general framework to support the design of power-oriented applications through hardware/software co-design.1
The complexity of ordering subgoals
Authors: Jeffrey D. Ullman, Moshe Y. Vardi
Venue: Proceedings of the seventh ACM SIGACT-SIGMOD-SIGART symposium on Principles of database systems (1988)

Selection of an appropriate order for the evaluation of subgoals in a logical rule frequently is essential for efficiency. We formulate the problem as one of feasible subgoal orders and show that the question is inherently exponential in time. The proof is by reduction from linear-space alternating Turing machine recognition, which appears to be far easier, in this case, than the more obvious reduction from exponential-time (ordinary) Turing machines
Estimation of BIST Resources During High-Level Synthesis
Authors: Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer
Venue: Journal of Electronic Testing: Theory and Applications (1998)

Lower bound estimations of functional resources at various stages of high-level synthesis have been developed to guide synthesis algorithms toward optimal solutions. In this paper we present lower bounds on the number of test resources (i.e., registers that generate pseudo-random test patterns and/or compress test responses) required to test a synthesized data path using built-in self-test (BIST). The bounds on different types of test resources are proved to be individually achievable and experiments show that in most cases the bounds can be achieved simultaneously and with minimum number of functional registers. Efficient ways of computing the lower bounds are developed. The estimations are performed on scheduled data flow graphs with a given module assignment and provide a practical way of selecting or modifying module assignments and schedules such that the resulting synthesized data path requires a small number of BIST resources to test itself.
Ada: a commercial flop and proud of it!-or-how to deal with Java envy
Authors: Dave Wood
Venue: ACM SIGAda Ada Letters (1999)

This paper provides a brief summary of a presentation provided at the 1998 SIGAda conference in Washington DC. Part of the "Commercializing Ada" workshop, the presentation discusses the alleged commercial failure of Ada, and how we can improve Ada's commercial lot in life.
A Best Possible Deterministic On-Line Algorithm for Minimizing Maximum Delivery Time on a Single Machine
Authors: J. A. Hoogeveen, A. P. A. Vestjens
Venue: SIAM Journal on Discrete Mathematics (2000)

We consider a single-machine on-line scheduling problem where jobs arrive over time. A set of independent jobs has to be scheduled on the machine, where preemption is not allowed and the number of jobs is unknown in advance. Each job becomes available at its release date, which is not known in advance, and its characteristics, i.e., processing requirement and delivery time, become known at its arrival. The objective is to minimize the time by which all jobs have been delivered. We propose and analyze an on-line algorithm based on the following idea: As soon as the machine becomes available for processing, choose an available job with highest priority, and schedule it if its processing requirement is not too large. Otherwise, postpone the start of this job. We prove that our algorithm has performance bound $(\sqrt{5}+1)/2 \approx 1.61803$, and we show that there cannot exist a deterministic on-line algorithm with a better performance ratio for this problem.
Similarity-Based Models of Word Cooccurrence Probabilities
Authors: Ido Dagan, Lillian Lee, Fernando C. N. Pereira
Venue: Machine Learning (1999)

In many applications of natural language processing (NLP) it is necessary to determine the likelihood of a given word combination. For example, a speech recognizer may need to determine which of the two word combinations &ldquo;eat a peach&rdquo; and &rdquo;eat a beach&rdquo; is more likely. Statistical NLP methods determine the likelihood of a word combination from its frequency in a training corpus. However, the nature of language is such that many word combinations are infrequent and do not occur in any given corpus. In this work we propose a method for estimating the probability of such previously unseen word combinations using available information on &ldquo;most similar&rdquo; words.We describe probabilistic word association models based on distributional word similarity, and apply them to two tasks, language modeling and pseudo-word disambiguation. In the language modeling task, a similarity-based model is used to improve probability estimates for unseen bigrams in a back-off language model. The similarity-based method yields a 20% perplexity improvement in the prediction of unseen bigrams and statistically significant reductions in speech-recognition error.We also compare four similarity-based estimation methods against back-off and maximum-likelihood estimation methods on a pseudo-word sense disambiguation task in which we controlled for both unigram and bigram frequency to avoid giving too much weight to easy-to-disambiguate high-frequency configurations. The similarity-based methods perform up to 40% better on this particular task.