ppxscal/embedding_network huggingface dataset:
Commutativity-Based Concurrency Control for Abstract Data Types
Authors: W. E. Weihl
Venue: IEEE Transactions on Computers (1988)

Two novel concurrency algorithms for abstract data types are presented that ensure serializability of transactions. It is proved that both algorithms ensure a local atomicity property called dynamic atomicity. The algorithms are quite general, permitting operations to be both partial and nondeterministic. The results returned by operations can be used in determining conflicts, thus allowing higher levels of concurrency than otherwise possible. The descriptions and proofs encompass recovery as well as concurrency control. The two algorithms use different recovery methods: one uses intentions lists, and the other uses undo logs. It is shown that conflict relations that work with one recovery method do not necessarily work with the other. A general correctness condition that must be satisfied by the combination of a recovery method and a conflict relation is identified.
Bull: A World-Wide Company Born in Europe
Authors: P. E. Mounier-Kuhn
Venue: IEEE Annals of the History of Computing (1989)

The patents of Fredrik-Rosing Bull, registered from 1919, were the origins of statistic punched card machines, initially manufactured in Norway, then in Switzerland, and finally in France after the creation of the company there in 1931. From 1935 onwards, the firmly established Compagnie des Machines Bull began to expand internationally until about 1960 when Bull had reached the point of being the second largest electronic business machine manufacturer in the world. Bull's conversion to electronics during the 1950s brought the company new successes (Gamma 3 in 1952, drum-augmented Gamma in 1956) but destabilized the company, since its financial position and management methods were rather unsuited to the new "technical system." Poor commercial distribution of the Gamma 60 (1960) was, in spite of its technical performance, only one of the reasons for the crisis that culminated in General Electric's acquiring a controlling interest in 1964, sold then to Honeywell in 1970. By the end of the 1980s, Bull, once again a company with a French shareholding majority, is now the leading European computer manufacturer and is ranked seventh worldwide.
Performance evaluation of programs for certain Bessel functions
Authors: W. J. Cody, L. Stoltz
Venue: ACM Transactions on Mathematical Software (TOMS) (1989)

This paper presents methods for performance evaluation of the K Bessel functions. Accuracy estimates are based on comparisons involving the multiplication theorem. Some ideas for checking robustness are also given. The techniques used here are easily extended to the Y Bessel functions and, with a little more effort, to the I and J functions. Details on a specific implementation for testing the K Bessel functions are included.
The type system of DBPL
Authors: Florian Matthes, Joachim W. Schmidt
Venue: Proceedings of the second international workshop on Database programming languages (1989)

This paper presents the type system of the database programming language DBPL [SEM88] within the framework proposed in [ADG*89].
Evaluating hypermedia systems (panel)
Authors: Gary Perlman
Venue: Proceedings of the SIGCHI conference on Human factors in computing systems: Empowering people (1990)

Hypermedia systems provide online access to complex networks of information with the goal of making it easier to find and use information. To validate the utility of their systems, several researchers and system developers have attempted to collect evaluation data on the usability and effectiveness of their systems and the features in their systems. Because of the potential complexity of hypermedia systems and the information structures they may represent, a variety of evaluation measures and methods have been used. These trade off the need for timely feedback in the development of new technology, the difficulty of controlling one or two variables in systems with dozens or hundreds of components, and the goal of gaining an understanding of hypermedia systems.
Type consistency of queries in an object-oriented database system
Authors: Dave D. Straube, M. Tamer Özsu
Venue: Proceedings of the European conference on object-oriented programming on Object-oriented programming systems, languages, and applications (1990)

Queries in object-oriented databases can return non-homogeneous sets of objects when no type restrictions are placed on the inputs to the query. The tradition has been to force homogeneity on the result by restricting the types of the inputs. This restricts the range of permissible, and possibly useful, queries. We propose a type consistency theory for queries in object-oriented databases which supports the existence of multiple types in the query result. The technique is illustrated by developing type inference rules for an object algebra. The main result is that the loss of type information associated with a query operation is reduced in most cases. We also show how type information is increased when queries are qualified by conjunctive predicates.
Covering orthogonal polygons with star polygons: the perfect graph approach
Authors: R. Motwani, A. Raghunathan, H. Saran
Venue: Proceedings of the fourth annual symposium on Computational geometry (1988)

We consider the problem of covering simple orthogonal polygons with star polygons. A star polygon contains a point p, such that for every point q in the star polygon, there is an orthogonally convex polygon containing p and q.In general, orthogonal polygons can have concavities (dents) with four possible orientations. In this case, we show that the polygon covering problem can be reduced to the problem of covering a weakly triangulated graph with a minimum number of cliques. We thus obtain a &Ogr; (n10) algorithm. Since weakly triangulated graphs are perfect, we also obtain an interesting duality relationship. In the case where the polygon has at most three dent orientations, we show that the polygon covering problem can be reduced to the problem of covering a triangulated (chordal) graph with a minimum number of cliques. This gives us an &Ogr; (n3) algorithm.
Software Storming: Combining Rapid Prototyping and Knowledge Engineering
Authors: Karl S. Keller, Pamela W. Jordan, Richard W. Tucker, David Vogel
Venue: Computer (1989)

A method for rapidly producing highly functional prototypes is described. This method, called software storming, involves experts in the initial design and implementation of a system during an intense development effort that combines knowledge engineering with the latest advances in software-development technology and workstation hardware The experiment described is a test of tools and techniques developed in the field of artificial intelligence as well as the first step in the development of software storming. Using this approach, the authors developed a software prototype which possesses significantly more functionality than a standard prototype, in less than four months.
A threaded/flow approach to reconfigurable distributed systems and service primitives architectures
Authors: L. F. Ludwig
Venue: Proceedings of the ACM workshop on Frontiers in computer communications technology (1987)

This paper discusses a methodology for managing the assembly, control, and disassembly of large numbers of independent small-scale configurations within large-scale reconfigurable distributed systems. The approach is targeted at service primitives architectures for enhanced telecommunications networks, but can apply to more general settings such as multi-tasking supercomputers and network operations systems.* Study of the methods presented here was a key motivation in founding the Bell Communications Research Integrated Media Architecture Laboratory (IMAL) [1]. The Threaded/Flow approach uses data-flow constructs to assemble higher level functions from other distributed functions and resources with arbitrary degrees of decentralization. Equivalence between algorithms and hard and virtual resources is accomplished via threaded-interpretive constructs. Function autonomy, concurrency, conditional branching, pipelining, and setup/execution interaction are implicitly supported. Some elementary performance comparisons are argued. This work is motivated by telecommunications applications involving coordinated multiple-media in open architectures supporting large numbers of users and outside service vendors. In such networks it is desired that services may be flexibly constructed by the network, service vendors, or by users themselves from any meaningful combination of elementary primitives and previously defined services. Reliability, billing, call progress, real-time user control, and network management functions must be explicitly supported. These needs are handled with apparent high performance by the approach.
The theory of function arrays
Authors: D. Landaeta
Venue: ACM SIGAPL APL Quote Quad (1987)

This paper presents a theoretical foundation for objects known as function arrays, which have been widely written about in past conferences. In contrast to the usual constructive approach, where the emphasis is on the method for creating function arrays, this paper follows a deductive approach, where a given function is defined to be a function array if it has certain properties. The principles outlined here are independent of any method for constructing function arrays, but when particular examples are required, they are taken from APL2.
A survey of discrete event simulation and state-of-the-art discrete event languages
Authors: Lissa F. Pollacia
Venue: ACM SIGSIM Simulation Digest (1989)

This paper provides an introduction to the main concepts of discrete event simulation and surveys the field of current discrete event simulation languages. Discrete event simulation is a modeling technique for the study of systems whose state may change only at discrete points in time. This type of modeling is applicable to many real-world problems, and a wide variety of languages have been developed for the purpose of modeling these situations. In this paper, a survey of current discrete event simulation languages is presented. The focus of the survey is on identifying new trends in simulation languages, such as extensions to general purpose programming languages, artificial intelligence concepts, special-purpose features, and graphics-based capabilities.
A global object name space for the Intel hypercube
Authors: W. L. Bain
Venue: Proceedings of the third conference on Hypercube concurrent computers and applications: Architecture, software, computer systems, and general issues - Volume 1 (1988)

The Intel iPSC and iPSC&reg;/2 concurrent computer systems provide the processing power and memory to solve very large parallel programming problems. However, their distributed memory and large grain process model complicate the implementation of object oriented programs. As part of the Interwork II Concurrent Programming Toolkit, software facilities have been constructed for the management of a large number of objects (up to 2**32) in a global object name space. This simplifies the Pisces' programming model by allowing uniform access to objects from any node within the hypercube. Objects are dynamically created and destroyed, and two methods of object access are provided. First, a process can gain exclusive access to an object using the Open_obj procedure; the object migrates to the process's local node as a side effect. A second and more efficient access method is to execute one of an object's associated procedures using the Apply procedure. The current implementation transports the procedure name and arguments to the node on which the object resides for execution; a copy of the code exists on every node. Interwork II uses the global object name space to support a distributed, lightweight process model. This allows processes to be uniformly accessed throughout the cube. Additional objects for inter-process communication are also provided. The global object name space is implemented in a fully distributed manner in order to eliminate performance bottlenecks. Techniques for caching object references to further speed up object access are described.
The 1987&mdash;1988 Taulbee survey
Authors: David Gries, Dorothy Marsh
Venue: Communications of the ACM (1989)

The Computing Research Board's 1987-1988 Taulbee Survey includes the latest statistics on production and employment of Ph.D.'s and faculty in computer science and engineering. Included also are departments offering Ph.D.'s in computer engineering.
A computer graphics course
Authors: D. A. Sewry
Venue: ACM SIGCSE Bulletin (1989)

A computer graphics course is presented that was introduced at the honours level at Rhodes University in 1988. In the past, a course in graphics has not been included in either the undergraduate or post-graduate curriculum. However, with the increased emphasis on the "visual" aspects of computing (full-screen editors combining text and images, windowing, graphical languages, CAD), it was thought appropriate to enhance the honours curriculum. This paper discusses the course structure, possible texts, supporting hardware and experience gained.
Putting the expert in charge: graphical knowledge acquisition for fault diagnosis and repair
Authors: L. L. Rodi, J. A. Pierce, R. E. Dalton
Venue: Issue 108 (April 1989) (1989)

Thesis: With respect to the fault diagnosis and repair problem, bull; experts who are not programmers can work alone to specify test and repair plans and make use of a natural idiom; bull; a graphical interface can be built which limits keyboard input and avoids natural language headaches; bull; consistency checking to prevent cycles and redundancies in test/repair sequences can be carried out during knowledge acquisition prior to running the resulting diagnostic routines; bull; a current version of the (output) diagnostic routine may be run easily during knowledge acquisition to verify the knowledge base while it is being built; bull; diagnostic testing can be deterministic but need not be fully-ordered, and probably should not be; bull; rules and uncertainty measures are not necessary.
GCDHEU: Heuristic polynomial GCD algorithm based on integer GCD computation
Authors: Bruce W. Char, Keith O. Geddes, Gaston H. Gonnet
Venue: Journal of Symbolic Computation (1989)

A heuristic algorithm, GCDHEU, is described for polynomial GCD computation over the integers. The algorithm is based on evaluation at a single large integer value (for each variable), integer GCD computation, and a single-point interpolation scheme. Timing comparisons show that this algorithm is very efficient for most univariate problems and it is also the algorithm of choice for many problems in up to four variables.
Characterizing computer performance with a single number
Authors: J. E. Smith
Venue: Communications of the ACM (1988)

The controversy surrounding single number performance reduction is examined and solutions are suggested through a comparison of measures.
Fast, Deterministic Routing, on Hypercubes, Using Small Buffers
Authors: Bradley C. Kuszmaul
Venue: IEEE Transactions on Computers (1990)

A deterministic routing scheme for a communications network based on the k-dimensional hypercube is proposed. The author presents two formulations of the scheme. The first formulation delivers messages in O(k/sup 2/) bit times using O(K) bits of buffer space at each node in the hypercube. The second formulation assumes that there are several batches of messages to be delivered, and makes certain assumptions about the cost of sending messages along the various dimensions of the cube. In this case, the latency for delivery time is still O(k/sup 2/) bit times, but the throughput is increased to one set of messages every O(k) bit times. For the first formulation, the author restricts himself to routings which are subsets of permutations (i.e. every node sends at most one message and receives at most one message). The second formulation indicates a way to perform routings which are subsets of H-permutations (i.e. every node sends at most H messages and receives at most H messages).
Optimal VLSI Dictionary Machines Without Compress Instructions
Authors: Hon F. Li, David K. Probst
Venue: IEEE Transactions on Computers (1990)

Several designs are presented for VLSI dictionary machines that combine both a linear (modify) network and a logarithmic (query) network with a novel idea for separation of concerns. The initial design objectives included: (1) single-cycle operability of host-issued modify and query commands (no compress instructions), (2) complete processor utilization (no waste processors), and (3) optimal 2 log n response times, where n is the current population of the machine. The authors sought simple ideas that, for the first time, would allow all three objectives to be achieved simultaneously. They were forced to abandon objective (3), instead achieving a slightly weaker objective, namely, near-optimal (2 log n+R) response times, where R is the time for a round trip through the particular prenetwork used to connect the host to the roots of the query trees in the logarithmic network. Both sorted and unsorted versions of dictionary machines are presented. Those with orthogonal command networks achieve all objectives; those without orthogonal networks achieve only the first and third.
John von Neumann Reconsidered
Authors: J. R. Brink
Venue: IEEE Annals of the History of Computing (1989)

This essay offers a general assessment of von Neumann's life and his contributions to computer science. Responding to biased attacks on von Neumann's political stance, this essay attempts to rectify misrepresentations of von Neumann's position on national defense and scientific research.
Energy consumption in VLSI circuits
Authors: Alok Aggarwal, Ashok Chandra, Prabhakar Raghavan
Venue: Proceedings of the twentieth annual ACM symposium on Theory of computing (1988)

We study energy consumption in CMOS-style VLSI circuits, where a wire of length / consumes energy &THgr;(l)when switching. Three model are considered: the uniswitch model where a wire is assumed to switch at most once if the input changes, the multiswitch model which allows the possibility of multiple switches caused by uncontrolled delays, and the clock model which also takes clock distribution energy into account. Previous lower bound results for the uniswitch model applied only to circuits where intermediate data were not encoded (for example, in unary) by using additional wires and area to reduce the energy. We show that such encodings can be useful for adding two n-bit numbers using synchronous Boolean circuits (energy reduction from &THgr;(n log n) to &Ogr;(n log n/(log log n)), but not for transitive functions such as the cyclic shift of n bits (energy &THgr;(n2)). For the multiswitch model, we develop layouts that achieve energy close to the uniswitch case for these problems, and show a separation result between the uniswitch and multiswitch models. Finally, some energy-period tradeoffs are shown for the clock model.
Research toward the development of a lexical knowledge base for natural language processing
Authors: R. A. Amsler
Venue: ACM SIGIR Forum (1989)

This paper documents research toward building a complete lexicon containing all the words found in general newspaper text. It is intended to provide the reader with an understanding of the inherent limitations of existing vocabulary collection methods and the need for greater attention to multi-word phrases as the building blocks of text. Additionally, while traditional reference books define many proper nouns, they appear to be very limited in their coverage of the new proper nouns appearing daily in newspapers. Proper nouns appear to require a grammar and lexicon of components much the way general parsing of text requires syntactic rules and a lexicon of common nouns.
Macrotasking the singluar value decomposition of block circulant matrices on the Cray-2
Authors: J. R. Baker
Venue: Proceedings of the 1989 ACM/IEEE conference on Supercomputing (1989)

A parallel algorithm to compute the singular value decomposition (SVD) of block circulant matrices on the Cray-2 is described. For a block circulant form described by M blocks with m x n elements in each block, the computation time using an SVD algorithm for general matrices has a lower bound &OHgr;(M3min(m, n)mn). Using a combination of fast Fourier transform (FFT) and SVD steps, the computation time for block circulant singular value decomposition (BCSVD) has a lower bound &OHgr;(Mmin(m, n)mn); a relative savings of ~ M2. Memory usage bounds are reduced from &THgr;(M2mn) to &THgr;(Mmn); a relative savings of ~ M. For M = m = n = 64, this decreases the computation time from approximately 12 hours to 30 seconds and memory usage is reduced from 768 megabytes to 12 megabytes. The BCSVD algorithm partitions well into n macrotasks with a granularity of &THgr;(mM log M) for the FFT portion of the algorithm. The SVD portion of the algorithm partitions into M macrotasks with a granularity of &OHgr;(min(m, n)mn). Again, for the case where M = m = n = 64, the FFT granularity is 29ms and the SVD granularity is 428ms. A speedup of 3.06 was achieved by using a prescheduled partitioning of tasks. The process creation overhead was 2.63ms. Using a more elaborate self-scheduling method with four synchronizing server processes, a speedup of 3.25 was observed with four processors available. The server synchronization overhead was 0.32ms. Relative memory overhead in both cases was about 4% for data space and 40% for code space.
Transistor size optimization in the tailor layout system
Authors: D. Marple
Venue: Proceedings of the 26th ACM/IEEE Design Automation Conference (1989)

This paper describes a combination transistor sizing/layout compaction tool used to synthesize high performance CMOS circuits. This optimization tool is part of a large integrated layout system, called Tailor. Given any CMOS circuit layout, Tailor's transistor size optimizer will simultaneously adjust transistor sizes and compact the layout so that the minimum required area (cell pitch) for a specified upper bound on circuit delay is achieved. All delay paths are considered by modeling circuit delay with a logic independent delay graph. Tailor's optimizer globally optimizes circuit area (in one dimension) and delay by use of compaction and nonlinear programming algorithms. The optimizer does not yet optimize in two dimensions simultaneously or optimize hierarchical circuits. Results for a few optimized CMOS circuits are presented.
A bit-plane architecture for optical computing with two-dimensional symbolic substitution
Authors: A. Louri, K. Hwang
Venue: Proceedings of the 15th Annual International Symposium on Computer architecture (1988)

A novel architecture based on optical technology is presented for constructing parallel computers. The architecture exploits optics for its ultra-high speed, massive parallelism, and dense connectivity. The processing is based on a new technique called 2-D symbolic substitution which can be implemented with very fast optical components. Two-dimensional symbolic substitution algorithms are developed for arithmetic/logic operations as well as for complex scientific computations such as matrix algebra and FFT. The predicted performance of the system is compared with the performance of existing electronic array processors and is shown to be potentially superior. The bit-plane architecture is shown feasible and economical based on state-of-the-art optical and electro-optical technologies.