ppxscal/embedding_network huggingface dataset:
Robots, productivity and quality
Authors: Charles A. Rosen
Venue: Proceedings of the ACM annual conference - Volume 1 (1972)

There is a growing national need to increase the real productivity of our society, wherein &ldquo;productivity&rdquo; is redefined to include such major factors as the quality of life of workers and the quality of products, consistent with the desires and expectations of the general public. This paper proposed the development of automation technology designed to increase quality, in all its aspects, at an acceptable cost to society. The proposed program is divided into two phases. The first phase is designed to catalyze the potential resources of industrial concerns by developing two demonstrable systems that include general-purpose programmed manipulation and automated inspection. The second phase, with longer term objectives, would aim at devising techniques to broaden the utilization of programmed manipulators and sensors, to provide supervisory control of these systems by human speech, and to develop a capability for automatic manipulation of two or more sensor-controlled &ldquo;hands&rdquo; working cooperatively.
A teacher/learner
Authors: William S. Curran
Venue: Proceedings of the thirteenth SIGCSE technical symposium on Computer science education (1982)

The present paper is a report on a program which was originally developed as a teaching device for courses in Artificial Intelligence, but which developed into a program which is an expert on the topic of Computer Science. As such it is used in the dual capacity of instruction in A/I and in introductory courses in Computer Science.
On deterministic context-free languages, multihead automata, and the power of an auxiliary pushdown store
Authors: I. H. Sudborough
Venue: Proceedings of the eighth annual ACM symposium on Theory of computing (1976)

A deterministic context-free language L0 is described which is log(n)-complete for the family of languages recognized by deterministic log(n)- tape bounded auxiliary pushdown automata in polynomial time. It follows that L0 is a &ldquo;hardest&rdquo; deterministic context-free language (DCFL), since all DCFL's are recognized in polynomial time by deterministic pushdown automata. L0 is, moreover, a simple precedence language and a simple LL(1) language. Thus the tape complexities of these proper subfamilies are essentially the same as the tape complexity of all DCFL's. We show that an auxiliary pushdown store does, in fact, add some power to some restricted families of log(n)-tape bounded Turing machines. The basic result is that every two-way 2k-head nondeterministic finite automation can be replaced by an equivalent two-way k-head nondeterministic pushdown automation. This indicates, also, that every 2k-head nondeterministic finite automation language can be recognized in 0(n3k) steps. Other results relate multihead automata classes with other multihead automata classes, with families recognized by log(n)-tape bounded Turing machines with restricted tape alphabets, and with time-bounded complexity classes.
Composing letters with a simulated listening typewriter
Authors: John D. Gould, John Conti, Todd Hovanyecz
Venue: Proceedings of the 1982 conference on Human factors in computing systems (1982)

Speech recognition is not yet advanced enough to provide people with a reliable listening typewriter with which they could compose documents. The aim of this experiment was to determine if an imperfect listening typewriter would be useful for highly experienced dictators. Participants dictated either in isolated words or in continuous speech, and used a simulated listening typewriter which recognized a limited vocabulary as well as one which recognized an unlimited one. Results suggest that reducing the rate at which people dictate, either through limitations in vocabulary size or through speaking in isolated words, led to reductions in people's performance. For these first-time users, no version of the listening typewriter was better than traditional dictating methods.
Statistics, stationarity and random number generation
Authors: Robert Bohrer, Peter B. Imrey
Venue: Proceedings of the 9th conference on Winter simulation - Volume 1 (1977)

This paper remarks upon some issues involved in evaluating the &ldquo;randomness&rdquo; of numerical sequences. The question of how much to test is addressed, particularly with respect to pseudorandom generators. Historical failures of seemingly random sequences are noted. The dependence of evaluation programme upon proposed use of the sequence is stressed. The meaning and importance of stationarity are considered, and results from statistical distribution theory useful in checking for it, and in further evaluation of a sequence, are described. An example illustrates differences in power of three tests directed against a particular class of stationary alternatives to Normal white noise.
CAD system for VLSI
Authors: Warren Wiemann
Venue: Proceedings of the 16th Design Automation Conference (1979)

One million device systems on a chip will be partitioned into manageable subsystem building blocks. These basic building blocks will be equivalent in complexity to the chips of today. Using programmable elements such as ROMs and PLAs, these building blocks can be configured to implement a wide variety of different systems. CAD systems will evolve from a loosely coupled collection of programs to a system oriented around a common data base. This data base will allow more automation and will provide the information to close the design loop. Layout techniques will improve through the use of sophisticated on-line design systems. These systems should also access the data base to provide feedback to the designer in the form of circuit and logic checks. CAD systems of today are moving in the right direction and will meet the challenge of the 80's.
Walsh functions for spectral analysis
Authors: Paul Sanchez
Venue: Proceedings of the 15th conference on Winter Simulation - Volume 2 (1983)

Walsh analysis has several nice properties aside from allowing the experimenter to work with discrete parameter spaces. There is a Fast Walsh Transform (FWT) which is analogous to the Fast Fourier Transform (FFT) used in more traditional spectral computations. The FWT is like the FFT in that it requires n log2n operations to evaluate, where n is the number of observations available. However, in the case of the FWT those operations are additions or subtractions, which are substantially faster for digital computers than the complex multiplications required by the FFT. Furthermore, addition and subtraction are computationally stable operations for finite bit arithmetic, while multiplication and division are not. We will show in the oral presentation that if the error term of a stochastic system is additive discrete white noise then the Walsh spectral estimator has a x2 distribution with 2 degrees of freedom. This enables the experimenter to perform statistical tests to accept or reject the hypothesis that a spike in the spectrum is due to random fluctuation.
Creating efficient systems for object-oriented languages
Authors: Norihisa Suzuki, Minoru Terada
Venue: Proceedings of the 11th ACM SIGACT-SIGPLAN symposium on Principles of programming languages (1984)

Increasingly computer science research has been done using workstations with high-resolution bitmap display systems. Smalltalk-80&uarr; is a very attractive programming language for such computation environments, since it has very sophisticated graphical systems and programming environments. Unfortunately there are still very few computer systems on which Smalltalk-80 can run with satisfactory speed, and furthermore they are quite expensive. In order to make Smalltalk-80 accessible to a large group of people at low cost,. we have developed compiler techniques useful to generate efficient code for standard register machines such as MC68000. We have also extended Smalltalk-80 to include type expressions, which allow compilers to generate efficient code
A video disc oriented educational system
Authors: Demetrios A. Michalopoulos
Venue: ACM SIGCUE Outlook (1976)

One of the challenging fields of computer science is the computer graphics field which, because of its relatively high cost, has not been used extensively for educational purposes. Recent hardware developments in the graphics technology and price breakthroughs in digital equipment are beginning to influence the educational uses of computer graphics. If &ldquo;a picture is worth a thousand words&rdquo; and if the cost is not at this ratio, one can provide the student, not necessarily of computer sciences, with the possibility of a continuous interaction in which the student can see the results of his decision and thus allows him to experiment and practice with ideas not completely understood yet. This paper presents a design for an interactive educational system incorporating the recent development of the video-disc.
Classes of functions for computing on binary trees (Extended Abstract)
Authors: F. Hawrusik, K. N. Venkataraman, A. Yasuhara
Venue: Proceedings of the thirteenth annual ACM symposium on Theory of computing (1981)

This paper constitutes part of a general investigation into abstract computability on finitely generated free algebras (term algebras). The general idea is to determine an abstract computational process appropriate for computing on term algebras, the effectiveness of which should be apparent from the inductive structure of that domain, without reference to computability on the natural numbers (say, via coding).
The Charrette Ada compiler
Authors: Jonathan Rosenberg, David Alex Lamb, Andy Hisgen, Mark Sherman
Venue: Proceedings of the ACM-SIGPLAN symposium on The ADA programming language (1980)

The Charrette Ada compiler is a working compiler for a substantial subset of the preliminary Ada language. The Ada source program is translated into an equivalent program in an intermediate implementation language. The result of the compilation process is machine language generated for this intermediate program. This paper provides a brief overview of the compiler with special attention given to the primary translation phase. Emphasis is placed on the transformation of Ada type and subtype information and the representation of objects. The translation of several interesting statement and expression forms is also outlined.
A temporal ordering specification of some session services
Authors: Vincenza Carchiolo, Alberto Faro, Giuseppe Scollo
Venue: ACM SIGCOMM Computer Communication Review (1984)

The achievement of widely accepted standards for Open Systems Interconnection (OSI) is closely tied to the ability of producing unambiguous and implementation independent specifications of related protocols and services. LOTOS, the Language fOr Temporal Ordering Specification, is a Formal Description Technique (FDT) whose definition, though not completed, has already reached such a state as to allow trial specifications of rather sophisticated services and protocols. This paper explores the specification in LOTOS of some of the session services whose discussion is underway within various standardization bodies. Conciseness of specification is tried by adopting a few notational variants which are guessed to be useful at various OSI layers. The session services selected for this trial specification comprise the Basic Combined Subset (BCS) enriched with the Expedited Data service.
The educational issues confronting Ada (Panel Discussion)
Authors: Hal Hart, Vance Mall, Phil Miller, Peter Wegner
Venue: Proceedings of the thirteenth SIGCSE technical symposium on Computer science education (1982)

Sponsored by the Department of Defense, Ada is a programming language that embodies and enforces many modern software methodologies. Thus, the introduction of the language gives the opportunity for improvements in software reliability, maintainability, and clarity. Ada also offers some unique educational challenges and opportunities, so this panel will focus on some of the requirements for industrial, graduate, and undergraduate Ada education. In particular, the panel will explore different teaching methodologies, and will share their experiences in teaching the language. Each panelist is actively involved in the Ada program, and has contributed to the development of an educational strategy for the Ada Joint Program Office.
Simulation methodology: Lessons of the Past, Challenges for the Future
Authors: Bernard P. Zeigler
Venue: Proceedings of the 15th conference on Winter simulation - Volume 1 (1983)

This panel discussion is patterned after a similar session held at the recent Annual Meeting of the Society for General Systems Research, held in Detroit (May, 1983). The objective of that panel session was to raise the level of awareness of systems researchers regarding the role of modelling and simulation as a key tool in systems methodologies. Audience reaction to the session was intense and generated much debate. Consequently, the idea arose of presenting a matching version to the simulation community. It will be interesting to compare reactions emerging from the different perspectives of systems research and simulation modelling practice. For interested readers, the panel contributions are being expanded and deepened by the authors to take the form of articles for publication in the post proceedings of the Detroit SGSR meeting and the journal Behavioral Science. The current panel discussion aims to examine the methodology of current practice, and from this base, go on to point out the challenges that lie in the near and long term future. The session will consist of an integrated sequence of presentations by simulation methodologists. Beginning with problems and approaches in contemporary large-scale simulation modelling, it will move onto more ambitious computer-supported methodologies under development.
Complete register allocation problems
Authors: Ravi Sethi
Venue: Proceedings of the fifth annual ACM symposium on Theory of computing (1973)

The search for efficient algorithms for register allocation dates back to the time of the first Fortran compiler for the IBM 704. Since then, many variants of the problem have been considered; depending on two factors: (1) the particular model for registers, and (2) the definition of the term &ldquo;computation of a program&rdquo; e.g. whether values may be computed more than once. We will show that several variants of the register allocation problem for straight line programs are polynomial complete. In particular we consider, (1) the case when each value is computed exactly once, and (2) the case when values may be recomputed as necessary. The completeness of the third problem considered is surprising. A straight line program starts with a set of initial values, and computes intermediate and final values. Suppose, for each value, the register that value must be computed into is preassigned. Then, (3) the problem of determining if there is a computation of the straight line program, that computes values into the assigned registers, is polynomial complete.
A fast APL algorithm for logic minimization
Authors: Alfred A. Schwartz
Venue: Proceedings of the international conference on APL (1984)

This paper presents an algorithm for logic reduction which exploits APL's array and Boolean processing capabilities. The traditional algorithm, the Quine-McCluskey method, requires extensive looping and hence is very slow when implemented in an interpretive language. The APL algorithm accomplishes the same function as the Quine-McCluskey method, but in a totally different way and much faster.
An Ada code generator for VAX 11/780 with Unix
Authors: Mark Sherman, Andy Hisgen, David Alex Lamb, Jonathan Rosenberg
Venue: Proceedings of the ACM-SIGPLAN symposium on The ADA programming language (1980)

This paper describes the final phase of an Ada compiler which produces code for the VAX 11/780 running the Unix operating system. Problems encountered in the implementation of subprogram calls, parameter passing, function return values, and exception handling are discussed and their solutions outlined. An underlying requirement for the code generator has been speed of implementation consistent with being a test bed for an Ada implementation. To accomplish this, a common model for the target environment has been assumed. The assumptions include: the VAXis a stack machine, a single address space is used, only the general case is implemented (no optimization of special cases), the hardware does as much work as possible, run time routines for lengthy code sequences are acceptable, and the conventions given in the VAX architecture, hardware, and software manuals are used. The code generator has been running on a PDP-10 with Tops-10, producing a VAX assembly language source program as output. It has been available to local users since the beginning of 1980.
An efficient variable-cost maze router
Authors: Robert K. Korn
Venue: Proceedings of the 19th Design Automation Conference (1982)

A variable cost maze router is described. The router is substantially faster than most other maze routers and also provides a flexibility which is valuable in a variety of ways. It is particularly well suited for use on multiple layer routing surfaces in which adjacent layers have primary wire directions which are perpendicular to each other. The router has been incorporated as a final phase into both a circuit board routing system and an LSI gate array router. Experience with these systems is described. Potential applications of the variable cost ability are also discussed.
Improving the throughput of a pipeline by insertion of delays
Authors: Janak H. Patel, Edward S. Davidson
Venue: Proceedings of the 3rd annual symposium on Computer architecture (1976)

A pipeline is defined to be a collection of resources, called segments which can be kept busy simultaneously. A task once initiated, flows from segment to segment for its execution. A collision occurs if two or more tasks attempt to use the same segment at the same time. The collision characteristics of a pipeline with respect to a schedule of task initiations are investigated. A methodology is presented for modifying the collision characteristics with the insertion of delays so as to increase the utilization of segments and hence the throughput under appropriate scheduling.
The relationship between computational circuit complexity and radix
Authors: James R. Armstrong
Venue: Proceedings of the sixth international symposium on Multiple-valued logic (1976)

The relationship between computational circuit complexity and radix is analyzed. Circuit complexity is measured by the computation time or the number of (d, r) modules in the circuit. The effect of radix on complexity is determined by showing what happens to lower bounds on computation time and number of modules when the radix is varied. If the radix is changed from d1 to d2, the lower bound on computation time is changed by the additive factor logr (logd2d1); the lower bound on number of modules is multiplied by (logd2d1) or log(d2d1)2.
Computer aided logic design
Authors: Frank W. Bliss
Venue: Proceedings of the 9th Design Automation Workshop (1972)

This paper describes an interactive computer-aided design system which converts a state table description of a small scale synchronous digital system into a logic diagram. The input to the design programs is a State Table and a Unit Control Table that is generated by another design automation program. The State Table sequences the operations of the system. The Unit Control Table describes the operations that are to be performed on the defined units of the digital system and the conditions under which the operations are to be performed. The output of the design system is a detailed logical design of the control logic of the digital system. The output is in the form of an interconnection diagram that can be read by a digital hardware simulation program. The Computer-Aided Logic Design (CALD) System is interactive to allow the designer to change various parameters and generate many different logic designs for any particular State Table. The user may specify the state assignment, the type of memory element, and the maximum allowed gate fan-in. CALD assists the designer in performing State Table reduction and generates the state assignment at the users option. The tabular description of the digital machine is translated into a Boolean description resulting in a set of cannonical form Boolean equations in sum of product form. Memory element application equations are generated. Boolean equation minimization is performed followed by a factoring routine to enforce the fan-in constraint. The equations are then translated into a logic diagram. The CALD system is implemented in FORTRAN and running on a mini-computer with 8K of core.
Interpolating splines with local tension, continuity, and bias control
Authors: Doris H. U. Kochanek, Richard H. Bartels
Venue: ACM SIGGRAPH Computer Graphics (1984)

This paper presents a new method for using cubic interpolating splines in a key frame animation system. Three control parameters allow the animator to change the tension, continuity, and bias of the splines. Each of these three parameters can be used for either local or global control. Our technique produces a very general class of interpolating cubic splines which includes the cardinal splines as a proper subset.
Hierarchical channel router
Authors: Michael Burstein, Richard Pelavin
Venue: Proceedings of the 20th Design Automation Conference (1983)

The channel routing problem is a special case of the wire routing problem when interconnections have to be performed within a rectangular strip having no obstructions, between terminals located on opposite sides of the rectangle. We present here a new channel routing algorithm, based on reduction of the problem to the case of a (2&times;n) grid and on consistent utilization of a &ldquo;divide and conquer&rdquo; approach. For the current implementation of the algorithm, the running time is proportional to N&times;n&times;log (m), where N is the number of nets, n is the length of the channel (number of columns) and m is the width of the channel (number of tracks). Traditional technological restrictions are assumed, i.e. net terminals are located on vertical grid lines, two wiring layers are available for interconnections - one layer is used exclusively for vertical segments, another for horizontal and vias are introduced for each layer change. This algorithm consistently outperforms several known routers in quality of wiring. We tested the algorithm on several benchmark problems. One of them - Deutsch's &ldquo;difficult ex&le&rdquo; - was routed with only 19 horizontal wiring tracks (the absolute minimum for this case), whereas all other known routers required 20 or more tracks.
Women in science: A pilot project in accelerated computer training for returning women students
Authors: N. Dale
Venue: Proceedings of the eighth SIGCSE technical symposium on Computer science education (1977)

Women make up 51% of our population, yet they represent only 10% of those currently employed as scientists. Recognizing the underutilized scientific resource that women represent the congress of the United States directed the National Science Foundation to make available not less than &dollar;1,500,000 to develop and test methods of increasing the flow of women into scientific careers. (Public Law 94-80, 1976) To carry out this mandate, NSF sent out a call for proposals in early 1976. The proposals were to be of two kinds: (1) Science Career Workshops where women students would be introduced to and hopefully motivated into choosing careers in the sciences and (2) Career Facilitation Projects where women who have scientific training but are not using it could be brought up to date and made ready to enter the job market or enter graduate school. This paper describes the Career Facilitation Project being undertaken by the Computer Sciences Department of the University of Texas at Austin, supported by the National Science Foundation under Grant #SMI6-20420.