ppxscal/embedding_network huggingface dataset:
Scalable QoS provision through buffer management
Authors: R. Guérin, S. Kamat, V. Peris, R. Rajan
Venue: ACM SIGCOMM Computer Communication Review (1998)

In recent years, a number of link scheduling algorithms have been proposed that greatly improve upon traditional FIFO scheduling in being able to assure rate and delay bounds for individual sessions. However, they cannot be easily deployed in a backbone environment with thousands of sessions, as their complexity increases with the number of sessions. In this paper, we propose and analyze an approach that uses a simple buffer management scheme to provide rate guarantees to individual flows (or to a set of flows) multiplexed into a common FIFO queue. We establish the buffer allocation requirements to achieve these rate guarantees and study the trade-off between the achievable link utilization and the buffer size required with the proposed scheme. The aspect of fair access to excess bandwidth is also addressed, and its mapping onto a buffer allocation rule is investigated. Numerical examples are provided that illustrate the performance of the proposed schemes. Finally, a scalable architecture for QoS provisioning is presented that integrates the proposed buffer management scheme with WFQ scheduling that uses a small number of queues.
On the Expressive Power of OKFDDs
Authors: Bernd Becker, Rolf Drechsler, Michael Theobald
Venue: Formal Methods in System Design (1997)

Ordered Decision Diagrams (ODDs) as a means for the representation of Boolean functions are used in many applications in CAD. Depending on the decomposition type, various classes of ODDs have been defined, among them being the Ordered Binary Decision Diagrams (OBDDs), the Ordered Functional Decision Diagrams (OFDDs) and the Ordered Kronecker Functional Decision Diagrams (OKFDDs).Based on a formalization of the concept decomposition type we first investigate all possible decomposition types and prove that already OKFDDs, which result from the application of only three decomposition types, result in the most general class of ODDs. We then show from a (more) theoretical point of view that the generality of OKFDDs is really needed. We prove several exponential gaps between specific classes of ODDs, e.g. between OKFDDs on the one side and OBDDs, OFDDs on the other side. Combining these results it follows that a restriction of the OKFDD concept to subclasses, such as OBDDs and OFDDs as well, results in families of functions which lose their efficient representation.
A fast algorithm to minimize multi-output mixed-polarity generalized Reed-Muller forms
Authors: Martin Helliwell, Marek Perkowski
Venue: Proceedings of the 25th ACM/IEEE Design Automation Conference (1988)

A very fast computer program that accepts a Boolean function as an array of multi-output disjoint cubes and returns a mixed-polarity Generalized Reed-Muller Form is presented. Such circuits often have gates and interconnections than classical sum-of-product realizations and are easily testable. The program was tested on many examples from literature as well as on many large arithmetic functions with up to 8 inputs, 8 output and 255 minterms. On all the examples from the literature the solutions were either the same or better than those generated by other methods. The algorithm is based on a new cube operation, called xlinking, that generalizes known operations of merger, exclusion and other logic operations specified by previous authors.
Compiler techniques for data synchronization in nested parallel loops
Authors: Peiyi Tang, Pen-Chung Yew, Chuan-Qi Zhu
Venue: Proceedings of the 4th international conference on Supercomputing (1990)

The major source of parallelism in ordinary programs is do loops. When loop iterations of parallelized loops are executed on multiprocessors, the cross-iteration data dependencies need to be enforced by synchronization between processors. Existing data synchronization schemes are either too simple to handle general nested loop structures with non-trivia array subscript functions or inefficient due to the large run-time overhead. In this paper, we propose a new synchronization scheme based on two data-oriented synchronization instructions: synch_read(x,s) and synch_write(x,s). We present the algorithm to compute the ordering number, s, for each data access. Using our scheme, a parallelizing compiler can parallelize a general nested loop structure with complicated cross-iteration data dependencies. If the computations of ordering numbers cannot be done at compile time, the run-time overhead is smaller than the other existing run-time schemes.
On the combination of hardware and software concurrency extraction methods
Authors: Augustus K. Uht, Constantine D. Polychronopoulos, John F. Kolen
Venue: Proceedings of the 20th annual workshop on Microprogramming (1987)

It has been shown that parallelism is a very promising alternative for enhancing computer performance. Parallelism, however, introduces much complexity to the programming effort. This has lead to the development of automatic concurrency extraction techniques. Prior work has demonstrated that static program restructuring via compiler based techniques provides a large degree of parallelism to the target machine. Purely hardware based extraction techniques (without software preprocessing) have also demonstrated significant (but lesser) degrees of parallelism. This paper considers the performance effects of the combination of both hardware and software techniques. The concurrency extracted from a given set of benchmarks by each technique separately, and together, is determined via simulations and/or analysis. The &ldquo;common parallelism&rdquo; extracted by the two methods is thus also considered, using new metrics. The analytic techniques for predicting the performance of specific programs are also described.
State Spaces of Convolutional Codes
Authors: Zhe-Xian Wan
Venue: Designs, Codes and Cryptography (1997)

There are various definitions of convolutional codes and each definition leads to a definition of code state space. In the usual definition of a convolutional code generated by a rational encoding matrix input sequences can be any Laurent series. It is proved that restricting input sequences to be rational functions or restricting output sequences to be finite do not change the code state space, and that restricting both input and output sequences to be finite may change the code state space.
Post-compaction register assignment in a retargetable compiler
Authors: Philip Sweany, Steven Beaty
Venue: Proceedings of the 23rd annual workshop and symposium on Microprogramming and microarchitecture (1990)

We discuss graph-coloring register assignment in a retargetable compiler for Long-Instruction-Word architectures. Of specific concern is when, during the compilation process, should register assignment be performed. We conclude that, for best results, register assignment should follow compaction. We discuss methods of circumventing the implementation problems inherent in such late register assignment.
Performance evaluation of Ethernet and HYPERbus local area networks using computer modeling
Authors: David S. Jennings, Aaron H. Konstam
Venue: Proceedings of the 17th conference on Winter simulation (1985)

The local area networks Ethernet and HYPERbus were simulated using the GPSS program language. Measurements of performance were network stability, messages transmitted per unit time, and the number of transmission attempts required per message. The simulations produced these results. Both networks were stable at the normal, 90 and 100 percent loads. At the 90 and 100 percent loads, Ethernet transmitted between 90.31 and 99.16 percent of the expected number of messages per unit time. HYPERbus under the same conditions transmitted 97.52 and 103.87 percent of the expected number of messages per unit time. Ethernet required up to 13 transmission attempts for some messages, with an average of 2.061 attempts per message. HYPERbus transmitted all of its messages on the first attempt.
Automatic insertion of BIST hardware using VHDL
Authors: Kwanghyun Kim, Joseph G. Tront, Dong S. Ha
Venue: Proceedings of the 25th ACM/IEEE Design Automation Conference (1988)

We present a system which automatically inserts BIST hardware to a circuit described in VHDL. An appropriate VHDL modeling style for automatic insertion of BIST hardware is investigated. Use of BILBO is primarily pursued in the system. Algorithmic and rule-based approaches are used in the insertion of BILBO. Test scheduling and control signal distribution are also performed by the system.
Specification of Realtime Systems Using ASTRAL
Authors: Amy W. Apon, Larry W. Dowdy
Venue: IEEE Transactions on Software Engineering (1997)

ASTRAL is a formal specification language for realtime systems. It is intended to support formal software development and, therefore, has been formally defined. The structuring mechanisms in ASTRAL allow one to build modularized specifications of complex systems with layering. A realtime system is modeled by a collection of state machine specifications and a single global specification. This paper discusses the rationale of ASTRAL's design. ASTRAL's specification style is illustrated by discussing a telephony example. Composability of one or more ASTRAL system specifications is also discussed by the introduction of a composition section, which provides the needed information to combine two or more ASTRAL system specifications.
Check Character Systems Using Chevalley Groups
Authors: Claudia Broecker, Ralph-Hardo Schulz, Gernot Stroth
Venue: Designs, Codes and Cryptography (1997)

We show that the Sylow 2-subgroups of nearly all Chevalley groups in even characteristic allow the definition of a check-character-system which detects all single and the most important double errors.
P-trees: storage efficient multiway trees
Authors: David M. Arnow, Aaron M. Tenenbaum, Connie Wu
Venue: Proceedings of the 8th annual international ACM SIGIR conference on Research and development in information retrieval (1985)

A new variation of high order multiway tree structures, the P-tree is presented. P-trees have average access costs that are significantly better than those of B-trees and are no worse (and often better) in storage utilization. Unlike compact B-trees, they can be maintained dynamically, and unlike dense multiway trees and B-trees, their associated insertion algorithm, which is also presented, is cheap and involves (at most) a very localized rearrangement of keys.
Hierarchical VLSI Fault Tracing by Successive CircuitExtraction from CAD Layout Data in the CAD-Linked EB TestSystem
Authors: Katsuyoshi Miura, Koji Nakamae, Hiromu Fujioka
Venue: Journal of Electronic Testing: Theory and Applications (1997)

A hierarchical VLSI fault tracing method is proposed which is applicable to the case where only CAD layout data is available in the CAD-linked electron beam test system. The CAD layout data is assumed to be hierarchically structured. The method uses the expansion of a previously proposed integrated algorithm which combines a transistor-level fault tracing algorithm and a successive circuit extraction from a non-hierarchically or a flat structured CAD layout data. The method allows us to trace a fault hierarchically from the top level cell to the lowest primitive cell and from the primitive cell to the transistor-level circuit in a consistent manner independent of circuit functions even when the cell data and the transistor-level circuit data exist in a level as a mixture. An application of the method to a hierarchically structured CMOS model layout with about 600 transistors shows its validity.
MOGAC: a multiobjective genetic algorithm for the co-synthesis of hardware-software embedded systems
Authors: Robert P. Dick, Niraj K. Jha
Venue: Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design (1997)

In this paper, we present a hardware-software co-synthesis system, called MOGAC, that partitions and schedules embedded system specifications consisting of multiple periodic task graphs. MOGAC synthesizes real-time heterogeneous distributed architectures using an adaptive multiobjective genetic algorithm that can escape local minima. Price and power consumption are optimized while hard real-time constraints are met. MOGAC places no limit on the number of hardware or software processing elements in the architectures it synthesizes. Our general model for bus and point-to-point communication links allows a number of link types to be used in an architecture. Application-specific integrated circuits consisting of multiple processing elements are modeled. Heuristics are used to tackle multi-rate systems, as well as systems containing task graphs whose hyperperiods are large relative to their periods. The application of a multiobjective optimization strategy allows a single co-synthesis run to produce multiple designs which trade off different architectural features. Experimental results indicate that MOGAC has advantages over previous work in terms of solution quality and running time.
On the testing of microprogrammed processor
Authors: S. Hwang, R. Rajsuman, Y. K. Malaiya
Venue: Proceedings of the 23rd annual workshop and symposium on Microprogramming and microarchitecture (1990)

In this paper a testing procedure is given for a microprogrammed processor. The conventional procedure to generate test vectors is used instead of C-testability for bit-slice microprocessor. The minimal complete test sequences are calculated for the micro-sequencer and the ALU, and stored in the micro-memory. Micro-memory is implemented by an electrically erasable PLA which has the capability to test itself using a universal test set. A one-bit wide processor section has been assumed in this paper. However, the method can be extended to a processor of any word length. The tests for the microsequencer and the ALU are applied from the micromemory. The response is compared against precalculated signature stored in the system memory. A parity bit is generated to indicate a fault.
Towards a polynomial-time randomized algorithm for closed product-form networks
Authors: Wu-Lin Chen, Colm Art O'Cinneide
Venue: ACM Transactions on Modeling and Computer Simulation (TOMACS) (1998)

We present a Markov chain Monte Carlo method for class throughputs in closed multiclass product-form networks. The method is as follows. For a given network, we construct a &ldquo;regularized&rdquo; network with a highly simplified structure that has the same steady-state distribution. We then simulate the regularized network. The method has performed reasonably well across a broad range of problems. We give a heuristic explanation of this and prove that the regularized network &ldquo;mixes in polynomial time&rdquo; in some special cases.
Doubly Logarithmic Communication Algorithms for Optical-Communication Parallel Computers
Authors: Leslie Ann Goldberg, Mark Jerrum, Tom Leighton, Satish Rao
Venue: SIAM Journal on Computing (1997)

In this paper, we consider the problem of interprocessor communication on parallel computers that have optical communication networks. We consider the completely connected optical-communication parallel computer (OCPC), which has a completely connected optical network, and also the mesh-of-optical-buses parallel computer (MOB-PC), which has a mesh of optical buses as its communication network. The particular communication problem that we study is that of realizing an h-relation. In this problem, each processor has at most h messages to send and at most h messages to receive. It is clear that any 1-relation can be realized in one communication step on an OCPC. However, the best previously known p-processor OCPC algorithm for realizing an arbitrary h-relation for h > 1 requires $\Theta(h + \log p)$ expected communication steps. (This algorithm is due to Valiant and is based on earlier work of Anderson and Miller.) Valiant's algorithm is optimal only for $h=\Omega(\log p)$, and it is an open question of Geréb-Graus and Tsantilas whether there is a faster algorithm for h=o(log p). In this paper, we answer this question in the affirmative and we extend the range of optimality by considering the case in which $h\leq \log p$. In particular, we present a $\Theta(h + \log\log p)$-communication-step randomized algorithm that realizes an arbitrary h-relation on a p-processor OCPC. We show that if $h\leq \log p$, then the failure probability can be made as small as $p^{-\alpha}$ for any positive constant $\alpha$. We use the OCPC algorithm as a subroutine in a $\Theta(h + \log\log p)$-communication-step randomized algorithm that realizes an arbitrary h-relation on a $p\times p$-processor MOB-PC. Once again, we show that if $h\leq \log p$, then the failure probability can be made as small as $p^{-\alpha}$ for any positive constant $\alpha$.
Focal-Plane and Multiple Chip VLSI Approaches to CNNs
Authors: M. Anguita, F. J. Pelayo, E. Ros, D. Palomar, A. Prieto
Venue: Analog Integrated Circuits and Signal Processing (1998)

In this paper, three alternative VLSI analog implementations of CNNs are described, which have been devised to perform image processing and vision tasks: a programmable low-power CNN with embedded photo-sensors, a compact fixed-template CNN based on unipolar current-mode signals, and basic CMOS circuits to implement an extended CNN model using spikes. The first two VLSI approaches are intended for focal-plane image processing applications. The third one allows, since its dynamics is defined by process-independent local ratios and its input/outputs can be efficiently multiplexed in time, the construction of very large multiple chip CNNs for more complex vision tasks.
Double Circulant Codes over Z\!Z_{\bf 4}and Even Unimodular Lattices
Authors: A. R. Calderbank, N. J. A. Sloane
Venue: Journal of Algebraic Combinatorics: An International Journal (1997)

With the help of some new results about weight enumerators of self-dual codes over Z\!Z_4 we investigate a class of double circulant codes over Z\!Z_4, one of which leads to an extremal even unimodular 40-dimensional lattice. It is conjectured that there should be &ldquo;Nine more constructions of the Leech lattice&rdquo;
The T-Ruby Design System
Authors: Robin Sharp, Ole Rasmussen
Venue: Formal Methods in System Design (1997)

This paper describes the T-Ruby system for designing VLSI circuits, starting from formal specifications in which they are described in terms of relational abstractions of their behaviour. The design process involves correctness-preserving transformations based on proved equivalences between relations, together with the addition of constraints. A class of implementable relations is defined. The tool enables such relations to be simulated or translated into a circuit description in VHDL. The design process is illustrated by the derivation of a circuit for 2-dimensional convolution.
Time machine&mdash;the dynamic worksheet
Authors: William B. Nordgren
Venue: Proceedings of the 28th conference on Winter simulation (1996)

Time Machine is a menu-driven simulation package mainly used for process re-engineering. It is developed for the analysis and quantitative evaluation of processes especially those with a dynamic character. A lot of applications in different industries show that there is an increasing need for simulation tools for processes such as paper flows, staffling, and customer service. This paper will demonstrate the process of building, analyzing and presenting models of real world systems with Time Machine.
Groupware Environments as Action Constitutive Resources: A Social Action Framework for Analyzing Groupware Technologies
Authors: Ojelanki K. Ngwenyama, Kalle J. Lyytinen
Venue: Computer Supported Cooperative Work (1997)

Computer Supported Cooperative Work (CSCW) is a relatively new and dynamic field dealing with the development and use of groupware technologies in organizations. Several frameworks and models have been proposed for studying CSCW, each conveying a different perspective and theoretical basis. Although these frameworks have contributed much to our understanding of the field, they can be criticized for a lack of holistic understanding of the complex social activity that is constitutive of groupwork. This often leads to the failure of otherwise well designed CSCW applications. In this paper we take up this challenge and propose a social action framework for analyzing groupware technologies. The framework is based on Habermas&lsquo;s theory of social action and four action categories, and the idea that groupware applications serve as sets of rules and resources which mediate group interactions. We demonstrate the value of the framework by analyzing a wide range of existing groupware technologies for their appropriateness to specific groupwork situations in terms of their espoused or implicit assumptions of groupwork, and the action constitutive resources they provide. Our analysis points out that a host of current groupware applications can be fairly easily classified and examined by the way they are configured to support different types of social action. It also suggests that, when implementing groupware applications, developers should critically evaluate: (a) the need for supporting a rich variety of action types, (b) the possible role of computer support in the specific groupwork situations, and (c) the underlying assumptions of groupwork embedded in the groupware platform. Finally, we will discuss how the framework can inform future research and development in the field.
Network Communities: Something Old, Something New, Something Borrowed &hellip;
Authors: Elizabeth D. Mynatt, Vicki L. O‘Day, Annette Adler, Mizuko Ito
Venue: Computer Supported Cooperative Work (1998)

Collaboration has long been of considerable interest to both designers and researchers in the CHI and CSCW communities. This paper contributes to this discussion by proposing the concept of network communities as a new genre of collaboration for this discussion. Network communities are robust and persistent communities based on a sense of locality that spans both the virtual and physical worlds of their users. They are a technosocial construct that requires understanding of both the technology and the sociality embodying them. We consider several familiar systems as well as historical antecedents to describe the affordances these systems offer their community of users. Based on our own experience as designers, users and researchers of a variety of network communities, we extend this initial design space along three dimensions: the boundary negotiations between real and virtual worlds, support for social rhythms and the emergence and development of community. Finally we offer implications for designers, researchers and community members based on our findings.
Barrier techniques for incremental tracing
Authors: Pekka P. Pirinen
Venue: Proceedings of the 1st international symposium on Memory management (1998)

This paper presents a classification of barrier techniques for interleaving tracing with mutator operation during an incremental garbage collection. The two useful tricolour invariants are derived from more elementary considerations of graph traversal. Barrier techniques for maintaining these invariants are classified according to the action taken at the barrier (such as scanning an object or changing its colour), and it is shown that the algorithms described in the literature cover all the possibilities except one. Unfortunately, the new technique is impractical. Ways of combining barrier techniques are also discussed.