VHDL for Programmable Logic
Authors: Kevin Skahill
Venue:  (1996)

From the Book:PREFACE: Preface Audience and Approach VHDL for Programmable Logic is appropriate for courses in VHDL, advanced logic design, and ASIC design, as well as for professional engineers and graduate students interested in updating their design methodologies to include both VHDL and programmable logic devices. The objective of this book is to equip the reader with: the skills to write VHDL code that can be synthesized to efficient logic circuits, an understanding of the VHDL and programmable logic design process--from design description through synthesis, placement, and routing, to the creation of test benches for design verification, a knowledge of design trade-offs that can be made, and a toolbox of techniques that can be modified and used to solve unique design problems. To achieve these objectives, the book covers VHDL by: emphasizing real-world examples rather than abstract theories, including coverage of design topics such as state machine design, area versus performance trade-offs, parameterized components, hierarchy and libraries, pipelining, and resource sharing, using numerous examples reduced through synthesis to logic gates, demonstrating options for synthesizing, fitting, placing, and routing logic circuits within CPLDs and FPGAs, introducing Breakout Exercises that reinforce design topics and quickly bring the reader up to speed with using the included Warp software, and including over 80 design files on the enclosed CD-ROM, some for use with the problem sets and hands-on experience with synthesizing, fitting, placing, and routing. The philosophy ofthistext is to thoroughly involve readers in numerous synthesis and design issues so that they nearly forget they are simultaneously learning a new design language and methodology. This text teaches by showing how VHDL models are synthesized for implementation in programmable logic devices--which are in turn are explained through a series of design issues, examples, and techniques. This is in contrast to focusing on syntax and language structure--an abstract and theoretical approach that tends to emphasize building simulation models that cannot necessarily be synthesized, because the designs are either physically meaningless or contain constructs that are not particularly well suited for synthesis. Many exercises encourage hands-on use of synthesis software in order to reduce theory to practice. This also helps readers to understand how abstract VHDL descriptions are reduced to digital logic. It is also expected that with practice, readers will write code that can be synthesized to efficient digital logic circuits. Understanding and executing the design objectives is also emphasized. The reader is challenged to make compromises between requirements such as time-to-market, cost, design features, performance, and manufacturing capabilities. Content and Organization Chapter 1 examines reasons for a design methodology that includes VHDL and programmable logic devices. It presents the process of designing for VHDL and programmable logic devices and for EDA tool flow. A Breakout Exercise introduces the reader to the Warp2 tool flow. Chapter 2 is a programmable logic primer that brings the reader from an understanding of simple logic gates and discrete devices to an appreciation for the capabilities of PALs, simple PLDs, CPLDs, and FPGAs. The chapter presents several device architectures and their features, and outlines the decisions that go into selecting an appropriate device for an application. Chapter 3 introduces the basic building blocks of VHDL design. The behavioral, dataflow, and structural architecture description styles are introduced and explained vis-a-vis synthesis efficiency. The chapter explores the simulation cycle and the differences between processing code for simulation and synthesis, and ends with a discussion of data objects and types. Chapter 4 describes how to use VHDL language constructs to build combinational and synchronous logic. Sequential statements such as if-then-else and case-when, as well as concurrent statements such as when-else and with-select-when, are compared and reduced to logic gates to illustrate the synthesis process. The chapter also uses design examples to illustrate the concept of overloaded operators; this provides a good context for introducing the IEEE 1076.3 numeric_std and numeric_bit packages. Other topics include: creating flip-flops, control logic, three-state outputs, bidirectional outputs, and implicit memory. The chapter ends in with the design of a FIFO. Chapter 5 explains how to easily translate state flow diagrams to equivalent VHDL state machine descriptions. Several state machine implementations are examined to determine effects of implementation on resource usage, setup times, clock-to-output times, and maximum operating frequency. Discussions of state encoding schemes, including one-hot, focus on area versus speed trade-offs and on fault-tolerance. Chapter 6 introduces large designs and VHDL's capabilities to deal with hierarchy, as well as design libraries and their components. Generics are used to create parameterized components. Packages containing type declarations and components are compiled into a library for use with two large designs developed in this chapter. The first is the design of an AM2901 microprocessor slice. The second is the design of the core logic for a 100 BASE-T4 network repeater, a "real world" 8,000-gate design that illustrates the complexity of designs that programmable logic devices and VHDL synthesis tools are intended to handle. Product-term clocks, synchronization of asynchronous signals, and communicating state machines are design issues explored through this case study. Chapter 7 illustrates how to create and use subprograms (functions and procedures) effectively in designs intended for synthesis. Subprograms are used for type conversion and as a substitute for component instantiation; examples of overloaded functions, procedures, and operators are given for both various types and various numbers of operands. The concept of module generation is introduced and compared to standard operator overloading. The subprogram body for the std_match function of the 1076.3 numeric_std package is explained. Chapter 8 uses the Flash370 architecture for a case study in synthesis and fitting to CPLD architectures; the pASIC380 is used for a case study in synthesis, placement, and routing to FPGA architectures. The strengths and weaknesses of both types of devices are explored, with special emphasis on how designs are realized in architectures, and how device resources can and cannot be used. Issues include routing into logic blocks, product-term distribution, clocking schemes, and loading. Chapter 9 illustrates several techniques for optimizing datapaths, including pipelining, resource sharing, and choosing either area- or speed-optimized versions of components, such as adders, comparators, and counters. Emphasis in this chapter is on altering the design topology to meet area and speed objectives for a design. Chapter 10 illustrates the concept of a test bench, using three methods for implementation. The first implementation uses a record to hold a table of test vectors. The second reads test vectors from a file and writes output vectors to another file. The third is a procedural approach that uses sequential statements to compute test vectors. Overloaded read and write procedures are given in the text (and in the enclosed CD-ROM) for use in reading and writing std_logic and std_logic_vectors to files. Appendix A contains instructions for installing Warp from the CD-ROM and gaining access to on-line documentation; Appendix B contains a list of VHDL reserved words; and Appendix C contains a VHDL quick reference guide. The organization of the book follows an emphasis on synthesis and design issues. The chapter on creating test benches is last to maintain this focus. Readers who wish to learn how to write test benches earlier may wish to read Chapter 10 after Chapter 4, this will be equip them to write both design models and their test benches for the remainder of the exercises in the text. Instructional Materials Software. The text includes Cypress Semiconductor's Warp2 CPLD and FPGA synthesis, fitting, and placing and routing software. It also includes an interactive waveform simulator that performs functional simulation of CPLDs based on a JEDEC programming file. Use of Warp is integrated into the text, but the text is not tied to the use of this software. Readers who have access to another VHDL processing tool can benefit equally from this text. Of course, some of the Breakout Exercises and end-of-chapter Problems will need modification to suit these readers' particular software environments. Solutions Manual. A solutions manual for the problems at the end of each chapter is available from Addison-Wesley. Suggestions The reviewers helped root out inaccuracies during various stages of this manuscript. The accountability for any remaining errors lies with me. If you find any errors or have suggestions for improvement for this text, please forward them via e-mail to Addison-Wesley Engineering. New examples and exercises (with solutions) are also welcome. Acknowledgments It is a pleasure to recognize the many individuals who helped me in all phases of this project. Without their help, I would not have finished this project, or even started it. So, to begin with, I wish to thank Barry Fitzgerald for providing the impetus to get this book off the ground. Once started, I relied heavily on David Johnson and Terri Fusco to manage schedules and enlist the support of others. A special debt of gratitude is owed to David Johnson for creating nearly every drawing in the text and providing guidance and assistance while I finished the book. For the version of the manuscript that went to reviewers, I relied on Garret Choy to capture many of the initial drawings, Krishna Rangasayee to supply additional exercises, Caleb Chen to type the quick reference guide and generate the table of contents, and Nancy Schweiger to edit. Steve Klinger performed the difficult job of indexing while also reviewing the text. For the final manuscript delivered to Addison-Wesley, Bert Koehler put the finishing touches on format and figures, and Rich Kapusta provided the glossary and technical edit. To those colleagues who generously offered their advice and counsel on issues of VHDL, programmable logic, and design, I am especially grateful: Haneef Mohammed, Alan Coppola, Chris Jones, Jeff Freedman, John Shannon, John Nemec, Larry Hemmert, Tim Lacey, and Krishna Rangasayee. Chris Jones also reviewed an early version of the manuscript, providing many suggestions for improvement, and Krishna Rangasayee provided resource material for Chapter 9. I wish to express my appreciation to the Warp software development group for their quick response to my questions and suggestions. I am grateful to Greg Somer for providing the Verilog code for the 100BASE-T4 network repeater design and explaining its operation to me. A special thanks to the contributing authors: Jay Legenhausen for developing and writing material for Chapter 5; and Corey Wilner, Ron Wade, and Blair Wilson for providing input and working on the outlines for Chapters 2, 3, and 4, respectively. Jay and Corey also provided the Solutions Manual. Ross Smith of Configured Energy Systems, Diane Rover of Michigan State University, Bob Reese of Mississippi State University, Ralph Carestia of Oregon Institute of Technology, Tom Chiacchira, and Daniel Harmon reviewed the manuscript and provided valuable constructive criticism and advice to help improve the text. I hope they are pleased with the result. The team at Addison-Wesley was instrumental through the development of this book. Tim Cox lent his support from the book's conception. He and Laura Cheu acquired reviewers and provided feedback to improve the text and integrate the use of the software into the text. Lisa Weber lead me through the production process, Elizabeth Gehrman performed a careful copy edit, and many others behind the scenes helped produce this book. I would also like to recognize the support I received from the management at Cypress Semiconductor while I worked on this project. A special thanks to John Hamburger, David Johnson, Al Graf, David Barringer, and J. Daniel McCranie. Thanks most of all to my wife Karen for her encouragement, patience, and support throughout this long process. Kevin Skahill Sunnyvale, California March, 1996