ppxscal/embedding_network huggingface dataset:
Virtual Full Replication by Adaptive Segmentation
Authors: Gunnar Mathiason, Sten F. Andler, Sang H. Son
Venue: Proceedings of the 13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (2007)

We propose Virtual Full Replication by Adaptive segmentation (ViFuR-A), and evaluate its ability to maintain scalability in a replicated real-time database. With full replication and eventual consistency, transaction timeliness becomes independent of network delays for all transactions. However, full replication does not scale well, since all updates must be replicated to all nodes, also when data is needed only at a subset of the nodes. With Virtual Full Replication that adapts to actual data needs, resource usage can be bounded and the database can be made scalable. We propose a scheme for adaptive segmentation that detects new data needs and adapts replication. The scheme includes an architecture, a scalable protocol and a replicated directory service that together maintains scalability. We show that adaptive segmentation bounds the required storage at a significantly lower level compared to static segmentation, for a typical workload where the data needs change repeatedly. Adaptation time can be kept constant for the workload when there are sufficient resources. Also, the storage is constant with an increasing amount of nodes and linear with an increasing rate of change to data needs.
Effect of IR-Drop on Path Delay Testing Using Statistical Analysis
Authors: Chunsheng Liu, Yang Wu, Yu Huang
Venue: Proceedings of the 16th Asian Test Symposium (2007)

IR-drop has become a major source of delay defects in deep sub-micron VLSI designs. In this work, we analyze the effect of IR-drop in path-delay test and how to obtain more accurate delay information of critical paths. For possible regions with IR-drop, we perform timing analysis on these nodes such that a certain amount of voltage drop can be associated with extra delays on victim nodes. Power analysis is conducted to determine the occurrence probability of a certain voltage drop. These probability values are used to weigh the extra delays caused by IR-drop of all victim nodes, which are then accumulated along each path. Experimental results show that such a process can effectively take the small delays caused by IR-drop into consideration and can have a significant impact on the identification and analysis of critical paths.
An Efficient Elliptic Curves Scalar Multiplication for Wireless Network
Authors: Bangju Wang, Huanguo Zhang, Yuhua Wang
Venue: Proceedings of the 2007 IFIP International Conference on Network and Parallel Computing Workshops (2007)

Mobile and wireless devices like cell phones and network enhanced PDAs have become increasingly popular in recent years. The security of data transmitted via these devices has become the bottleneck for wireless network. Elliptic curves cryptography (ECC) is especially attractive for devices and is suited for wireless network, which has restrictions of the limited bandwidth, processing power, storage space and power consumption. The efficiency of ECC implementation is highly dependent on the performance of arithmetic operations of scalar multiplication(SM) dP, which mainly applied in encryption, signature and protocol. A new signed binary representation (SBR) for integers is proposed, which needs less memory and cost of computation compared to other methods mentioned in this paper. According to analyzing and comparing to other methods, algorithm for computing dP using new SBR is more efficient in window methods and is the simplest for applying in software and hardware. The new SBR needs less computational power and memory and can improve the security of wireless network efficiently.
Short-Term Load Forecasting Using Support Vector Machine with SCE-UA Algorithm
Authors: Gang Li, Chun-tian Cheng, Jian-yi Lin, Yun Zeng
Venue: Proceedings of the Third International Conference on Natural Computation - Volume 01 (2007)

Short-term load forecasting (STLF) has always been a very important issue in power system planning and operation. Recently, along with power system privatization and deregulation, accurate forecast of electricity load has received increasing attention. However, forecasting electricity load is difficult because of the randomness and uncertainties of load demand. Support vector machine (SVM) is a novel type of learning machine, which has been successfully employed to solve nonlinear regression and time series problems and showed its potential in STLF. However, the accuracy of STLF is greatlty related to the selected parameters of SVM. In this paper, the SCE-UA algorithm, which is an effective and efficient method to optimize model parameters and widely applied to optimize the parameters of the hydrologic models, is employed to optimize the parameters of a SVM model. Subsequently, examples of electricity load data from GuiZhou Power Grid, China were used to compare the forecast performance of the proposed SCE-UA SVM model and back propagation neural network(BPNN) which has obtained wide attention in STLF . The results reveal that the proposed model outperforms the BPNN model. Consequently, the proposed SCE-UA SVM model provides a promising alternative for forecasting electricity load.
Collision Avoidance Multiple Access inWireless Sensor Networks
Authors: Jianwei Wang, Yuping Zhao, Dong Wang, Timo Korhonen
Venue: Proceedings of the 2007 IFIP International Conference on Network and Parallel Computing Workshops (2007)

Collision avoidance multiple access plays an important role in wireless sensor networks, especially for those composed of nodes having a simple access protocol functionality. Numerous protocols have been proposed for wireless sensor networks during the past decades. However, the majority of these proposals require too much actions to be taken by sensor nodes, which makes the sensor nodes too complex. In this paper, we focus on the sensor networks composed of simple function nodes and presented novel collision avoidance multiple access algorithms. Both suggested algorithms are based on two functional stages: the channel allocation stage and the actual data transmission by using TDMA and/or CDMA. Simulation results indicate that our algorithms significantly improve communication efficiency via collision avoidance scheme, comparing to existing proposals. In reference to this improvement, we will also address user-fairness of our algorithms.
An Effective Strategy for Porting C++ Applications on Cell
Authors: Ana Lucia Varbanescu, Henk Sips, Kenneth A. Ross, Qiang Liu, Lurng-Kuo Liu, Apostol (Paul) Natsev, John R. Smith
Venue: Proceedings of the 2007 International Conference on Parallel Processing (2007)

In this paper we present a solution for efficient porting of sequential C++ applications on the Cell B.E. processor. We present our step-by-step approach, focusing on its generality, we provide a set of code templates and optimization guidelines to support the porting, and we include a set of equations to estimate the performance gain of the new application. As a case-study, we show the use of our solution on a multimedia content analysis application, named MARVEL. The results of our experiments with MARVEL prove the significant performance increase in favor of the application running on Cell when compared with the reference implementation.
A Case Study of Human Factors Guidelines in Computer Graphics
Authors: Robert Swezey, Elaine Davis
Venue: IEEE Computer Graphics and Applications (1983)

Does conventional human factors wisdom meet the needs of a state-of-the-art computer graphics display system? This case study suggests that human factors lags behind computer technology.
Developing Workflow Engine for Mobile Devices
Authors: Lasse Pajunen, Suresh Chande
Venue: Proceedings of the 11th IEEE International Enterprise Distributed Object Computing Conference (2007)

Mobile devices are today capable to run and maintain long running interaction and communication between people and external systems over cell and local proximity networks. In this paper, we will describe a mobile workflow system which provides a platform for deploying and managing process oriented applications and services in mobile devices. We will discuss the architecture and the implementation aspects of our prototype. We will discuss the value of this system to the users in managing and partly automating their regular activities in both personal and professional life. In addition, we will argue the use of standards and the advantages of integrating two open standards on web forms and web services in order to execute the mobile workflows.
Combinational Equivalence Checking Using Incremental SAT Solving, Output Ordering, and Resets
Authors: S. Disch, C. Schollm
Venue: Proceedings of the 2007 Asia and South Pacific Design Automation Conference (2007)

Combinational equivalence checking is an essential task in circuit design. In this paper we focus on SAT based equivalence checking making use of incremental SAT techniques which are well known from their application in bounded model checking. Based on an analysis of shared circuit structures we present heuristics which try to maximize the benefit from incremental SAT solving in this application by looking for good orders in which the equivalence of different circuit outputs is checked. Moreover, we present a reset strategy for situations where the benefit from the incremental SAT approach seems to decrease. Experimental results demonstrate that our novel method outperforms traditional methods significantly.
Migration from traditional to web-based instruction for information assurance courses
Authors: William I. Bullers,  Jr., Stephen D. Burd, Alessandro F. Seazzu
Venue: Proceedings of the sixth conference on IASTED International Conference Web-Based Education - Volume 2 (2007)

Instructors face significant challenges when migrating a course using a traditional pedagogic approach to a web-based format. The preparation of learning modules, conduct of discussions, provision for hands-on labs to elucidate learning module concepts, and problems with student assessment must all be considered. This paper discusses how these components were brought together for information assurance courses at our university. It provides information regarding the history of these types of courses, the nature of their traditional delivery, their migration to an online format, and the outcome of this migration.
Anytime Learning of Decision Trees
Authors: Saher Esmeir, Shaul Markovitch
Venue: The Journal of Machine Learning Research (2007)

The majority of existing algorithms for learning decision trees are greedy---a tree is induced top-down, making locally optimal decisions at each node. In most cases, however, the constructed tree is not globally optimal. Even the few non-greedy learners cannot learn good trees when the concept is difficult. Furthermore, they require a fixed amount of time and are not able to generate a better tree if additional time is available. We introduce a framework for anytime induction of decision trees that overcomes these problems by trading computation speed for better tree quality. Our proposed family of algorithms employs a novel strategy for evaluating candidate splits. A biased sampling of the space of consistent trees rooted at an attribute is used to estimate the size of the minimal tree under that attribute, and an attribute with the smallest expected tree is selected. We present two types of anytime induction algorithms: a contract algorithm that determines the sample size on the basis of a pre-given allocation of time, and an interruptible algorithm that starts with a greedy tree and continuously improves subtrees by additional sampling. Experimental results indicate that, for several hard concepts, our proposed approach exhibits good anytime behavior and yields significantly better decision trees when more time is available.
Improving Circuit Robustness with Cost-Effective Soft-Error-Tolerant Sequential Elements
Authors: Mingjing Chen, Alex Orailoglu
Venue: Proceedings of the 16th Asian Test Symposium (2007)

Soft errors induced by alpha particles and cosmic radiation have become a highly challenging problem in the design of UDSM or nanoscale circuits, making the incorporation of circuit hardening techniques essential. In this paper, a design technique for soft-error-tolerant sequential elements is presented to improve circuit robustness. The proposed technique exploits time and space redundancy using an elaborate flip-flop structure, and provides complete soft error immunity for both the transient faults generated in the combinatorial logic and the particle strikes inside the flipflops. The proposed technique is developed to be compatible with current digital design technology, thus having minimal impact on design flow and hardware cost. Simulation results confirm the effectiveness of the proposed technique.
A highly efficient implementation of back propagation algorithm using matrix instruction set architecture
Authors: Mostafa I. Soliman, Samir A. Mohamed
Venue: Neural, Parallel Scientific Computations (2007)

Back Propagation (BP) training algorithm has received intensive research efforts to exploit its parallelism in order to reduce the training time for complex problems. A modified version of BP based on matrix-matrix multiplication was proposed for parallel processing. This paper discusses the implementation of Matrix Back Propagation (MBP) using scalar, vector, and matrix instruction set architecture (ISA). Besides, it shows that the performance of the MBP is improved by switching form scalar to vector ISA and form vector to matrix ISA. On a practical application, speech recognition, the speedup of training a neural network using unrolling scalar over scalar ISA is 1.83. On eight parallel lanes, the speedup of using vector, unrolling vector, and matrix ISA are respectively 10.33, 11.88, and 15.36, where the maximum theoretical speedup is 16. Our results show that the use of matrix ISA gives a performance close to the optimal because of reusing the loaded data, decreasing the loop overhead, and overlapping the memory operations by arithmetic operations.
Analysis of Memory Hierarchies for Sequential Data Access
Authors: T. A. Welch
Venue: Computer (1979)

Analytic modeling techniques permit system designers to compare memory-system alternatives quickly and easily. An example is the use of buffers or caches on disks.
Benchmarking quality measurement
Authors: John Moses
Venue: Software Quality Control (2007)

This paper gives a simple benchmarking procedure for companies wishing to develop measures for software quality attributes of software artefacts. The procedure does not require that a proposed measure is a consistent measure of a quality attribute. It requires only that the measure shows agreement most of the time. The procedure provides summary statistics for measures of quality attributes of a software artefact. These statistics can be used to benchmark subjective direct measurement of a quality attribute by a company's software developers. Each proposed measure is expressed as a set of error rates for measurement on an ordinal scale and these error rates enable simple benchmarking statistics to be derived. The statistics can also be derived for any proposed objective indirect measure or prediction system for the quality attribute. For an objective measure or prediction system to be of value to the company it must be `better' or `more objective' than the organisation's current measurement or prediction capability; and thus confidence that the benchmark's objectivity has been surpassed must be demonstrated. By using Bayesian statistical inference, the paper shows how to decide whether a new measure should be considered `more objective' or whether a prediction system's predictive capability can be considered `better' than the current benchmark. Furthermore, the Bayesian inferential approach is easy to use and provides clear advantages for quantifying and inferring differences in objectivity.
Non-volatile memory and disks:: avenues for policy architectures
Authors: Kevin R. B. Butler, Stephen E. McLaughlin, Patrick D. McDaniel
Venue: Proceedings of the 2007 ACM workshop on Computer security architecture (2007)

As computing models change, so too do the demands on storage. Distributed and virtualized systems introduce new vulnerabilities, assumptions, and performance requirements on disks. However,traditional storage systems have very limited capacity to implement needed "advanced storage" features such as integrity and dataisolation. This is largely due to the simple interfaces and limited computing resources provided by commodity hard-drives. A new generation of storage devices affords better opportunities to meet these new models, but little is known about how to exploit them. In this paper, we show that the recently introduced fast-accessnon-volatile RAM-enhanced hybrid (HHD) disk architectures can be used to implement a range of valuable storage-security services. We specifically discuss the use of these new architectures to provide data integrity, capability-based access control, and labeled information flow at the disk access layer. In this, we introduce systems that place a security perimeter at the disk interface--and deal with the parent operating system only as a largely untrusted entity.
Emulating Access Grid features at web endpoints
Authors: Pablo Sendin-Rana, Nicolas Otero-Alonso, Vicente Goyanes de Miguel, Francisco J. Gonzalez-Castano
Venue: Proceedings of the Sixth International Conference on Grid and Cooperative Computing (2007)

In this paper we present a system that captures and processes streams from Access Grid virtual rooms (venues) and distributes them to web endpoints. Its distinctive advantage is the emulation of Access Grid features using standard web clients. The system includes a toolset to handle audio and video contents, demultiplex the different sources, transcode them to adequate formats and store the resulting multimedia streams in repositories in real-time. A specialized server delivers those streams to standard web browsers that synchronize them, emulating typical Access Grid features like multiple windows or dynamic video selection. Web browsers can compose multiple independent streams, providing the appearance of Access Grid presentations. This paper presents the design principles, the system architecture and our current implementation in detail.
Error-Control Techniques for Logic Processors
Authors: D. K. Pradhan
Venue: IEEE Transactions on Computers (1972)

A new error-control technique for logic processors is given. The proposed technique uses Reed-Muller codes (RMC's). The design scheme given has better efficiency than the schemes proposed earlier. The improved efficiency is obtained by relaxing a basic assumption originally made by Elias. Furthermore, it is shown that the efficiency of the proposed scheme asymptotically approaches the maximum efficiency achievable by a practical though restricted class of error-control schemes. Reliability of the proposed scheme is studied.
On-Line Analysis of Exercise Electrocardiograms
Authors: M. L. Simoons
Venue: Computer (1975)

Computer assisted interpretation of exercise electrocardiograms (XECGs) is generally expected to improve the value of exercise testing for detection of ischemic heart disease (IHD) in patients with normal resting ECGs. There are several reasons for this:
TOD: A Software System for the Aramis Data Bank
Authors: D. J. McShane
Venue: Computer (1979)

This system is organized for statistical analysis of patient information. Such analysis yields accurate predictions of outcome and, by pointing to appropriate treatments, helps contain medical costs.
RISC3202: A Software Configuration Dual-Issue/Dual-Core Microprocessor
Authors: Yingbiao YAO, Bin Wang, Jianwu Zhang, Qingdong YAO
Venue: Proceedings of the 2007 IFIP International Conference on Network and Parallel Computing Workshops (2007)

RISC-based processors have been extended into almost all kinds of embedded applications. These applications have different features thus require different processor architectures. Thus, we have developed a dual-core/dual-issue mixed microarchitecture processor named as RISC3202 which is based on two simple RISC cores. On the one hand, RISC3202 is an in-order dual-issue superscalar processor for single-thread applications. On the other hand, RISC3202 is a shared-memory dual-core processor for multiple-thread applications. The work mode of RISC3202 is configurable during running programs. Therefore, RISC3202 fits well for different features of target applications and its hardware usage rate is always high.
Theoretical analysis of singleton arc consistency and its extensions
Authors: Christian Bessiere, Romuald Debruyne
Venue: Artificial Intelligence (2008)

Singleton arc consistency (SAC) is a consistency property that is simple to specify and is stronger than arc consistency. Algorithms have already been proposed to enforce SAC, but they have a high time complexity. In this paper, we give a lower bound to the worst-case time complexity of enforcing SAC on binary constraints. We discuss two interesting features of SAC. The first feature leads us to propose an algorithm for SAC that has optimal time complexity when restricted to binary constraints. The second feature leads us to extend SAC to a stronger level of local consistency that we call Bidirectional SAC (BiSAC). We also show the relationship between SAC and the propagation of disjunctive constraints.
MAC-layer QoS management for streaming rate-adaptive VBR video over IEEE 802.11e HCCA WLANs
Authors: Jianfei Cai, Deyun Gao, Jianhua Wu
Venue: Advances in Multimedia (2007)

With the increasing popularity of using WLANs for Internet access, the HCCA mechanism in IEEE 802.11e WLANs has received much more attention due to its efficiency in handling time-bounded multimedia traffic. To achieve high network utilization and good end-to-end QoS in the scenario of VBR video over HCCA is a very challenging task because of the dynamics coming from both the network conditions and the video content. In this paper, we propose a cross-layer framework for efficiently delivering multiclass rate-adaptive VBR video over HCCA. The proposed framework consists of three major modules: the MAC-layer admission control, the MAC-layer resource allocation, and the application-layer video adaptation. Experimental results demonstrate the effectiveness of each individual module and the advantage of dynamic interactions among different modules.
SIGMCC: A system for sharing meta patient records in a Peer-to-Peer environment
Authors: Mario Cannataro, Domenico Talia, Giuseppe Tradigo, Paolo Trunfio, Pierangelo Veltri
Venue: Future Generation Computer Systems (2008)

This paper considers the interoperability and information sharing between health care providers. It proposes a distributed Peer-to-Peer (P2P) based framework that enables health operators of different hospitals to share and aggregate clinical information about patients and therapy effects. Patient records are mapped into a simple XML-based meta-Electronic Patient Record (meta-EPR). The meta-EPR is not a standard EPR proposal, but it is a lightweight data structure defined to contain relevant and aggregate information extracted from the different EPRs adopted by each hospital. Hospital operators formulate queries against meta-EPR schema; queries are then distributed to the connected hospitals hosting meta-EPR instances, through a P2P infrastructure. The presented framework has been fully implemented in a system called SIGMCC, which offers an Application Programming Interface (API) for query formulation, data loading and updating. As a case study, an application of the proposed meta-EPR to the cancer medical domain has been developed. Finally, SIGMCC implements a view mechanism to allow personal (patient) information protection against unauthorized users.