ppxscal/embedding_network huggingface dataset:
Curriculum recommendations for graduate professional programs in information systems: recommended addendum on information systems administration
Authors: F. Warren McFarlan, Richard L. Nolan
Venue: Communications of the ACM (1973)

An addendum to the Report of the ACM Curriculum Committee on Computer Education for Management is proposed. The proposed addendum is to include in the curriculum a course on Information Systems Administration. It is important for two reasons: (1) the systems designer must understand the administrative framework in which he must operate to work effectively, and (2) an important objective of the curriculum recommendations is to prepare the future manager of the computer activity. It is felt that the importance of these two reasons justifies the addition of the recommended course. The course is outlined in the format of the original report.
On the downhill method
Authors: H. Bach
Venue: Communications of the ACM (1969)

The downhill method is a numerical method for solving complex equations &fnof;(z) = 0 on which the only restriction is that the function w = &fnof;(z) must be analytical. An introduction to this method is given and a critical review of relating literature is presented. Although in theory the method always converges, it is shown that a fundamental dilemma exists which may cause a breakdown in practical applications. To avoid this difficulty and to improve the rate of convergence toward a root, some modifications of the original method are proposed and a program (FORTRAN) based on the modified method is given in Algorithm 365. Some numerical examples are included.
Product line software engineering of embedded systems
Authors: Eila Niemelä, Tuomas Ihme
Venue: ACM SIGSOFT Software Engineering Notes (2001)

In order to be able to determine whether the product line approach is suitable, a company needs to analyse its business drivers, commonality of existing products, domain knowledge owned by the engineering staff, and quality of the representations of existing software artefacts. In this paper we present evaluation criteria for the development of a product line and give an overview of the current state of practices in the embedded software area. Evaluation criteria are divided into three classes. Business drivers of a product line are defined by analysing product assortment and business manners. Domains and personnel are considered in the analysis of the preconditions and targets of a product line. In the development of core assets, elements that affect assets engineering are considered as well as the mechanisms needed in their maintenance. A product line architecture that brings about a balance between sub- domains and their most important properties is an investment that must be looked after. However, the subdomains need flexibility to use, change and manage their own technologies, and evolve separately, but in a controlled way.
An experiment in a user-oriented computer system
Authors: Melvin Klerer, Jack May
Venue: Communications of the ACM (1964)

A version of a software-hardware system for the purpose of facilitating the programming and analysis of well-formulated problems is described. A modified Flexowriter is used to generate computer-acceptable input when equations or computable requests are typed in much the same manner as they would appear in conventional mathematical texts. The typing and language rules are quite flexible and unrestrictive. While the compiler part is efficient, the system as a whole has much broader aspects as a tool for the study of problem solving and self-teaching systems.
Hollerith punched card code
Authors: E. Lohse
Venue: Communications of the ACM (1968)

This proposed USA Standard presents the standard Hollerith Card Code representation of the 128 characters of USASCII in twelve-row punched cards. Other standards specify the dimensions and quality of punched paper ca rds, and the dimensions and locations of the holes punched in the cards. This coded representation of the USASCII character set for the twelve-row punched card was developed from research, review of historical work and careful consideration of the use of punched cares in information processing and communication. Resolution of several conflicting requirements is reflected herein.
An efficient design-for-verification technique for HDLs
Authors: Chien-Nan Jimmy Liu, I-Ling Chen, Jing-Yang Jou
Venue: Proceedings of the 2001 Asia and South Pacific Design Automation Conference (2001)

Due to the high complexity of modern circuit designs, verification has become the major bottleneck of the entire design process. There is an emerging need for a practical solution to reduce the verification time. In manufacturing test, a well-known technique, "design-for-testability", is often used to reduce the testing time. By inserting some extra circuits on the hard-to-test points, the testability can be improved and the testing time can be reduced. In this paper, we apply the similar idea to functional verification and propose an efficient "design-for-verification" (DFV) technique to help users reduce the verification time. The conditions for hard-to-control (HTC) codes in a HDL design are clearly defined, and an efficient algorithm to detect them automatically is proposed. Besides the HTC detection, we also propose an algorithm that can eliminate those HTC points with minimum number of DFV points. By the help of those DFV points, the number of required test patterns to reach the same coverage can be greatly reduced especially for deep-sequential designs.
Polynomial-time approximation schemes for geometric graphs
Authors: Thomas Erlebach, Klaus Jansen, Eike Seidel
Venue: Proceedings of the twelfth annual ACM-SIAM symposium on Discrete algorithms (2001)

A disk graph is the intersection graph of a set of disks with arbitrary diameters in the plane. For the case that the disk representation is given, we present polynomial-time approximation schemes (PTASs) for the maximum weight independent set problem (selecting disjoint disks of maximum total weight) and for the minimum weight vertex cover problem in disk graphs. These are the first known PTASs for NP-hard optimization problems on disk graphs. They are based on a novel recursive subdivision of the plane that allows applying a shifting strategy on different levels simultaneously, so that a dynamic programming approach becomes feasible. The PTASs for disk graphs represent a common generalization of previous results for planar graphs and unit disk graphs. They can be extended to intersection graphs of other &ldquo;disk-like&rdquo; geometric objects (such as squares or regular polygons), also in higher dimensions.
A serial technique to determine minimum paths
Authors: Don L. Weimer
Venue: Communications of the ACM (1963)

The need to determine minimum paths through a maze very often arises in such fields as traffic, transportation, communication and network studies. Computer analysis of these maze problems has been hampered in many cases due to the excessive size of the network under consideration. A technique has been developed to handle networks of very large magnitude by serially processing the network repetitively until only minimum paths remain. The ACM Portal is published by the Association for Computing Machinery. Copyright © 2010 ACM, Inc. Terms of Usage Privacy Policy Code of Ethics Contact Us Useful downloads: Adobe Acrobat QuickTime Windows Media Player Real Player
Something from nothing: augmenting a paper-based work practice via multimodal interaction
Authors: David R. McGee, Philip R. Cohen, Lizhong Wu
Venue: Proceedings of DARE 2000 on Designing augmented reality environments (2000)

In this paper, we describe Rasa: an environment designed to augment, rather than replace, the work habits of its users. These work habits include drawing on Post-it&trade; notes using a symbolic language. Rasa observes and understands this language, assigning meaning simultaneously to objects in both the physical and virtual worlds. With Rasa, users rollout a paper map, register it, and move the augmented objects from one place to another on it. Once an object is augmented, users can modify the meaning represented by it, ask questions about that representation, view it in virtual reality, or give directions to it, all with speech and gestures. We examine the way Rasa uses language to augment objects, and compare it with prior methods, arguing that language is a more visible, flexible, and comprehensible method for creating augmentations than other approaches.
Workload decomposition for particle simulation applications on hierarchical distributed-shared memory parallel systems with integration of HPF and OpenMP
Authors: Sergio Briguglio, Beniamino Di Martino, Gregorio Vlad
Venue: Proceedings of the 15th international conference on Supercomputing (2001)

A crucial issue in programming hierarchical distributed-shared memory systems is the workload decomposition. In this paper we address this issue in the framework of porting typical particle in cell (PIC) applications on hierarchical distributed-shared memory parallel systems. The workload decomposition we have devised consists in a two-stage procedure: a higher-level decomposition among the computational nodes, and a lower-level one among the processors of each computational node. We have implemented the described work decomposition without large programming effort by using and integrating the high-level languages High Performance Fortran and OpenMP.
Network and service management for wide-area electronic commerce networks
Authors: Symeon Papavassiliou
Venue: International Journal of Network Management (2001)

This paper focuses on the effective management of wide&hyphen;area electronic commerce networks supporting services and applications that require high availability and reliability as well as fast reconstitution time, in the event of failures. Copyright &copy; 2001 John Wiley Sons, Ltd.
Conversion of decision tables to efficient sequential testing procedures
Authors: I. K. Sethi, B. Chatterjee
Venue: Communications of the ACM (1980)

Sequential testing procedures for checking the rule-applicability of the decision tables encountered in practice are usually found to be minimum-path-length trees. On the basis of this observation, an algorithm is developed for converting decision tables to efficient decision trees. A criterion is defined for estimating the minimum expected cost of the tree in terms of rule probabilities and condition-testing costs and is utilized in arriving at the efficient decision tree. The algorithm is applicable to general limited-entry decision tables and can also be employed for manual coding.
Transmission-efficient routing in wireless networks using link-state information
Authors: J. J. Garcia-Luna-Aceves, Marcelo Spohn
Venue: Mobile Networks and Applications (2001)

The efficiency with which the routing protocol of a multihop packet-radio network uses transmission bandwidth is critical to the ability of the network nodes to conserve energy. We present and verify the source-tree adaptive routing (STAR) protocol, which we show through simulation experiments to be far more efficient than both table-driven and on-demand routing protocols proposed for wireless networks in the recent past. A router in STAR communicates to its neighbors the parameters of its source routing tree, which consists of each link that the router needs to reach every destination. To conserve transmission bandwidth and energy, a router transmits changes to its source routing tree only when the router detects new destinations, the possibility of looping, ot the possibility of node failures or network partitions. Simulation results show that STAR is an order of magnitude more efficient than any topology-broadcast protocol proposed to date and depending on the scenario is up to six times more efficient than the Dynamic Source Routing (DSR) protocol, which has been shown to be one of the best performing on-demand routing protocols.
Grading student programs - a software testing approach
Authors: Edward L. Jones
Venue: Proceedings of the fourteenth annual consortium on Small Colleges Southeastern conference (2000)

This paper describes an experience of automating the grading of student programs. A testing framework provides guidance for developing the assignment specification and the grading program. Automation saves time and improves grading consistency and feedback to students. After an adjustment period, student programs improved. Although the instructor invests more time writing a testable assignment specification and developing the grading program, these costs are expected to be amortized over multiple courses and assignments.
A Modular Multi-Chip Neuromorphic Architecture for Real-Time Visual Motion Processing
Authors: Charles M. Higgins, Christof Koch
Venue: Analog Integrated Circuits and Signal Processing (2000)

The extent of pixel-parallel focal plane image processing is limited by pixel area and imager fill factor. In this paper, we describe a novel multi-chip neuromorphic VLSI visual motion processing system which combines analog circuitry with an asynchronous digital interchip communications protocol to allow more complex pixel-parallel motion processing than is possible in the focal plane. This multi-chip system retains the primary advantages of focal plane neuromorphic image processors: low-power consumption, continuous-time operation, and small size. The two basic VLSI building blocks are a photosensitive sender chip which incorporates a 2D imager array and transmits the position of moving spatial edges, and a receiver chip which computes a 2D optical flow vector field from the edge information. The elementary two-chip motion processing system consisting of a single sender and receiver is first characterized. Subsequently, two three-chip motion processing systems are described. The first three-chip system uses two sender chips to compute the presence of motion only at a particular stereoscopic depth from the imagers. The second three-chip system uses two receivers to simultaneously compute a linear and polar topographic mapping of the image plane, resulting in information about image translation, rotation, and expansion. These three-chip systems demonstrate the modularity and flexibility of the multi-chip neuromorphic approach.
Interface Mutation: An Approach for Integration Testing
Authors: Máarcio E. Delamaro, José C. Maldonado, Aditya P. Mathur
Venue: IEEE Transactions on Software Engineering (2001)

The need for test adequacy criteria is widely recognized. Several criteria have been proposed for the assessment of adequacy of tests at the unit level. However, there remains a lack of criteria for the assessment of the adequacy of tests generated during integration testing. We present a mutation-based interprocedural criterion, named Interface Mutation (IM), suitable for use during integration testing. A case study to evaluate the proposed criterion is reported. In this study, the UNIX sort utility was seeded with errors and Interface Mutation evaluated by measuring the cost of its application and its error revealing effectiveness. Alternative IM criteria using different sets of Interface Mutation operators were also evaluated. While comparing the error revealing effectiveness of these Interface Mutation-based test sets with same size randomly generated test sets we observed that in most cases Interface Mutation-based test sets are superior. The results suggest that Interface Mutation offers a viable test adequacy criteria for use at the integration level.
Text Database Discovery on the Web: Neural Net Based Approach
Authors: Yong S. Choi, Suk I. Yoo
Venue: Journal of Intelligent Information Systems (2001)

As large numbers of text databases have become available on the Web, many efforts have been made to solve the text database discovery problem: finding which text databases (out of many candidates) are most likely to provide relevant documents to a given query. In this paper, we propose a neural net based approach to this problem. First, we present a neural net agent that learns about underlying text databases from the user's relevance feedback. For a given query, the neural net agent, which is sufficiently trained on the basis of the backpropagation learning mechanism, discovers the text databases associated with the relevant documents and retrieves those documents effectively. In order to scale our approach with the large number of text databases, we also propose the hierarchical organization of neural net agents which reduces the total training cost at the acceptable level. Finally, we evaluate the performance of our approach by comparing it to those of the conventional well-known statistical approaches.
On binary searching with non-uniform costs
Authors: Eduardo S. Laber, Ruy L. Milidiú, Artur A. Pessoa
Venue: Proceedings of the twelfth annual ACM-SIAM symposium on Discrete algorithms (2001)

Let us consider an ordered vector A[1 : n]. If the cost of testing each position is similar, then the standard binary search is the best strategy to search the vector. This is true in both average and worst case. However, if the costs are non-uniform, then the best strategy is not necessarily the standard binary search. The best algorithm to construct a strategy that minimizes the expected search cost runs in &Ogr;(n3) time and requires &Ogr;(n2) space. The same complexities hold for the best algorithm to construct a strategy that minimizes the worst case search cost. Here, we show how to efficiently construct search strategies that are at most at a constant factor from the optimal one. These constructions take linear time and use only linear space. For the problem of minimizing the expected search cost, we present an algorithm that requires &Ogr;(n) space and gives a (2 + &isin; + &Ogr;(1))-approximated solution in &Ogr;(n) time, for any fixed value of &isin; > 0. On the other hand, for the problem of minimizing the worst case search cost, we describe an algorithm that requires &Ogr;(n) space and gives a (2 + &isin; + &Ogr;(1))- approximated solution in &Ogr;(n) time, for any fixed value of &isin; > 0. These two problems arise when processing a query in a distributed text database indexed by a suffix array.
Recursive programming in Fortran II
Authors: James A. Ayers
Venue: Communications of the ACM (1963)

An oft-mentioned advantage of ALGOL over FORTRAN is the recursion capability of the former. FORTRAN adherents often belittle this advantage by claiming that all recursive relations can be reduced to recurrence or iterative relations, or that no recursive relations exist which are worth coding as recursive relations. The question of the truth of this must be left unanswered here. It is hoped that the technique described below will draw the poison from the FORTRANers' wounds by allowing them to recurse to their complete satisfaction. There is an hereditary resemblance between this technique and the MAD (Michigan Algorithm Decoder) recursion technique.
On face detection in the compressed domain
Authors: Huitao Luo, Alexandros Eleftheriadis
Venue: Proceedings of the eighth ACM international conference on Multimedia (2000)

We propose a fast face detection algorithm that works directly on the compressed DCT domain. Unlike the previous DCT domain processing designs that are mainly based on skin-color detection, our algorithm analyzes both color and texture information contained in the DCT parameters, therefore could generate more reliable detection results. Our texture analysis is mainly based on statistical model training and detection. A number of fundamental problems, e.g., block quantization, preprocessing in the DCT domain, and feature vector selection and classification in the DCT domain, are discussed.
A Single-Chip CMOS Transceiver Front-End for DCS-1800 Wireless Communications
Authors: M. Steyaert, M. Borremans, J. Janssens, B. De Muer, N. Itoh, J. Craninckx, J. Crols, E. Morifuji, H. S. Momose, W. Sansen
Venue: Analog Integrated Circuits and Signal Processing (2000)

This work describes the design and realization of a low voltage single-chip wireless transceiver front-end in a standard 0.25 &mu;m CMOS technology. The presented prototype integrates the LNA, down-converters, VCO, quadrature generator, up-converter and pre-amplifier on a single die. A high level of integration is achieved by using a low-IF topology for reception, a direct quadrature up-conversion topology for transmission and an oscillator with on-chip integrated inductor. The final objective of this design is to develop a complete transceiver system for wireless communications at 1.8 GHz that can be built with a minimum of surrounding components: only an antenna, a duplexer, a power amplifier and a baseband signal processing chip. The presented circuit consumes 240 mW from a 2.5 V supply and occupies a die area of 8.6\,\hbox{mm}^{2}.
Probability Models for Clutter in Natural Images
Authors: Ulf Grenander, Anuj Srivastava
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (2001)

We propose a framework for modeling clutter in natural images. Assuming that: 1) images are made up of 2D (projected) views of 3D (real) objects and 2) certain simplifying conditions hold, we derive an analytical density for natural images. This expression is shown to match well with the observed densities (histograms). In addition to deriving multidimensional densities, several extensions are also proposed.
Minimal event-node network of project precedence relations
Authors: D. G. Corneil, C. C. Gotlieb, Y. M. Lee
Venue: Communications of the ACM (1973)

A procedure for constructing a minimal event-node network to represent a set of precedence relations without parallel activities is presented. A minimal event-node network is an event-node network in which both the number of nodes and the number of arcs are the minima to preserve the given precedence relations. Counterexamples are given to show that the algorithm presented by A.C. Fisher, J.S. Liebman, and G.L. Nemhauser (1968) produces event-node networks which are not minimal. Since our procedure includes the set-covering problem, the time required may grow exponentially with the number of given activities.
Triple boot machines for cash-strapped small college labs
Authors: Paul de Palma
Venue: Proceedings of the fourteenth annual consortium on Small Colleges Southeastern conference (2000)

This paper describes a small college computer lab consisting of machines bootable in Windows NT, Linux, and Minix. I argue that such an arrangement allows small departments to use the same machine for projects in operating systems and data communications that would normally require dedicated labs. I offer technical advice on configuring such a lab and suggest some possible extensions to be implemented in the future.
Threading Fundamental Matrices
Authors: Shai Avidan, Amnon Shashua
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (2001)

We present a new function that operates on Fundamental matrices across a sequence of views. The operation, we call ¿threading¿, connects two consecutive Fundamental matrices using the trifocal tensor as the connecting thread. The threading operation guarantees that consecutive camera matrices are consistent with a unique 3D model, without ever recovering a 3D model. Applications include recovery of camera ego-motion from a sequence of views, image stabilization (plane stabilization) across a sequence, and multiview image-based rendering.