ppxscal/embedding_network huggingface dataset:
Optimization of instruction fetch mechanisms for high issue rates
Authors: Thomas M. Conte, Kishore N. Menezes, Patrick M. Mills, Burzin A. Patel
Venue: ACM SIGARCH Computer Architecture News (1995)

Recent superscalar processors issue four instructions per cycle. These processors are also powered by highly-parallel superscalar cores. The potential performance can only be exploited when fed by high instruction bandwidth. This task is the responsibility of the instruction fetch unit. Accurate branch prediction and low I-cache miss ratios are essential for the efficient operation of the fetch unit. Several studies on cache design and branch prediction address this problem. However, these techniques are not sufficient. Even in the presence of efficient cache designs and branch prediction, the fetch unit must continuously extract multiple, non-sequential instructions from the instruction cache, realign these in the proper order, and supply them to the decoder. This paper explores solutions to this problem and presents several schemes with varying degrees of performance and cost. The most-general scheme, the collapsing buffer, achieves near-perfect performance and consistently aligns instructions in excess of 90% of the time, over a wide range of issue rates. The performance boost provided by compiler optimization techniques is also investigated. Results show that compiler optimization can significantly enhance performance across all schemes. The collapsing buffer supplemented by compiler techniques remains the best-performing mechanism. The paper closes with recommendations and suggestions for future.
Scheduling Soft Real-Time Jobs Over Dual Non-Real-Time Servers
Authors: Benjamin Kao, Hector Garcia-Molina
Venue: IEEE Transactions on Parallel and Distributed Systems (1996)

In this paper, we consider soft real-time systems with redundant off-the-shelf processing components (e.g., CPU, disk, network), and show how applications can exploit the redundancy to improve the system's ability of meeting response time goals (soft deadlines). We consider two scheduling policies, one that evenly distributes load (Balance), and one that partitions load according to job slackness (Chop). We evaluate the effectiveness of these policies through analysis and simulation. Our results show that by intelligently distributing jobs by their slackness amount the servers, Chop can significantly improve real-time performance.
The living textbook and the K&ndash;12 classroom of the future
Authors: Kim Mills, Geoffrey Fox, Paul Coddington, Barbara Mihalas, Marek Podgorny, Barbara Shelly, Steven Bossert
Venue: Proceedings of the 1995 ACM/IEEE conference on Supercomputing (CDROM) (1995)

The Living Textbook creates a unique learning environment enabling teachers and students to use educational resources on multimedia information servers, supercomputers, parallel databases, and network testbeds. We have three innovative educational software applications running in our laboratory, and under test in the classroom. Our education-focused goal is to learn how new, learner-driven, explorative models of learning can be supported by these high bandwidth, interactive applications and ultimately how they will impact the classroom of the future.
Lower Bounds on Representing Boolean Functions as Polynomials in $z_{m}$
Authors: Shi-Chun Tsai
Venue: SIAM Journal on Discrete Mathematics (1996)

Define the $MOD_{m}$-degree of a boolean function $F$ to be the smallest degree of any polynomial $P$, over the ring of integers modulo $m$, such that for all 0-1 assignments $\vec{x}$, $F(\vec{x}) =0$ iff $P(\vec{x}) =0$. By exploring the periodic property of the binomial coefficients modulo $m$, two new lower bounds on the $MOD_{m}$-degree of the $MOD_{l}$ and $\neg MOD_{m}$ functions are proved, where $m$ is any composite integer and $l$ has a prime factor not dividing $m$. Both bounds improve from sublinear to $\Omega(n)$. With the periodic property, a simple proof of a lower bound on the $MOD_{m}$-degree with symmetric multilinear polynomial of the OR function is given. It is also proved that the majority function has a lower bound $n \over 2$ and the {MidBit} function has a lower bound $\sqrt{n}$.
High-level optimization via automated statistical modeling
Authors: Eric A. Brewer
Venue: ACM SIGPLAN Notices (1995)

We develop the use of statistical modeling for portable high-level optimizations such as data layout and algorithm selection. We build the models automatically from profiling information, which ensures robust and accurate models that reflect all aspects of the target platform.We use the models to select among several data layouts for an iterative PDE solver and to select among several sorting algorithms. The selection is correct more than 99% of the time on each of four platforms. In the few cases it selects suboptimally, the selected implementation performs nearly as well; that is, it always makes at least a very good choice. Correct selection is platform and workload dependent and can improve performance by nearly a factor of three.We also use the models to optimize parameters of these applications automatically. In all cases, the models predicted the optimal parameter setting, resulting in improvements ranging up to a factor of three.Finally, we use the models to construct portable high-level libraries, which contain multiple implementations and support for automatic selection and parameter optimization of the fastest implementation for the target platform and workload.
A Basis-Kernel Representation of Orthogonal Matrices
Authors: Xiaobai Sun, Christian Bischof
Venue: SIAM Journal on Matrix Analysis and Applications (1995)

In this paper we introduce a new representation of orthogonal matrices. We show that any orthogonal matrix can be represented in the form $Q = I - Y S Y^T$, which we call the basis-kernel representation of $Q$. In particular, we point out that the kernel $S$ can be chosen to be triangular and that a familiar representation of an orthogonal matrix as a product of Householder matrices can be readily deduced from a basis-kernel representation with triangular kernel. We also show that there exists, in some sense, a minimal orthogonal transformation between two subspaces of same dimension, an important application of which is on block elimination problems. We explore how the basis $Y$ determines the subspaces that $Q$ acts on in a nontrivial fashion, and how $S$ determines the way $Q$ acts on this subspace. Especially, there is a canonical representation that explicitly shows that $Q$ partitions {\bf R}$^n$ into three invariant subspaces in which it acts as the identity, a reflector, and a rotator, respectively. We also present a generalized Cayley representation for arbitrary orthogonal matrices, which illuminates the degrees of freedom we have in choosing orthogonal matrices acting on a predetermined subspace.
Algorithm 757: MISCFUN, a software package to compute uncommon special functions
Authors: Allan J. MacLeod
Venue: ACM Transactions on Mathematical Software (TOMS) (1996)

MISCFUN (MISCellaneous FUNctions) is a Fortran package for the evaluation of several special functions, which are not used often enough to have been included in the standard libraries or packages. The package uses Chebyshev expansions as the underlying method of approximation, with the Chebyshev coefficients given to 20D. A wide variety of functions are included, and the package is designed so that other functions can be added in a standard manner.
Register estimation in unscheduled dataflow graphs
Authors: R. Moreno, R. Hermida, M. Fernández
Venue: ACM Transactions on Design Automation of Electronic Systems (TODAES) (1996)

A method for register number estimation in unscheduled or partially scheduled dataflow graphs is presented. The strategy consists of studying the probability that an edge between two nodes crosses the boundary between two control steps, and its is based on a model that associates probabilities with the different scheduling alternatives of each node. These probabilities are computed by means of an analytic method that takes into account the distribution of operations in the dataflow graph and the hardware modules available in the library. The results highlight that the estimation method is very accurate becaused the error between the estimated value and the real value is always within a narrow margin.
On the power of cascade ciphers
Authors: S. Even, O. Goldreich
Venue: ACM Transactions on Computer Systems (TOCS) (1985)

The unicity distance of a cascade of random ciphers, with respect to known plaintext attack, is shown to be the sum of the key lengths. A time-space trade-off for the exhaustive cracking of a cascade of ciphers is shown. The structure of the set of permutations realized by a cascade is studied; it is shown that only l.2k exhaustive experiments are necessary to determine the behavior of a cascade of l stages, each having k key bits. It is concluded that the cascade of random ciphers is not a random cipher. Yet, it is shown that, with high probability, the number of permutations realizable by a cascade of l random ciphers, each having k key bits, is 2lk. Next, it is shown that two stages are not worse than one, by a simple reduction of the cracking problem of any of the stages to the cracking problem of the cascade. Finally, it is shown that proving a nonpolynomial lower bound on the cracking problem of long cascades is a hard task, since such a bound implies that P &nap; NP.
Parallel processing of spaceborne imaging radar data
Authors: Craig Miller, David G. Payne, Thanh N. Phung, Herb Siegel, Roy Williams
Venue: Proceedings of the 1995 ACM/IEEE conference on Supercomputing (CDROM) (1995)

We discuss the results of a collaborative project on parallel processing of Synthetic Aperture Radar (SAR) data, carried out between the NASA/Jet Propulsion Laboratory (JPL), the California Institute of Technology (Caltech) and Intel Scalable Systems Division (SSD). Through this collaborative effort, we have successfully parallelized the most compute-intensive SAR correlator phase of the Spaceborne Shuttle Imaging Radar-C/X-Band SAR (SIR-C/X-SAR) code, for the Intel Paragon. We describe the data decomposition, the scalable high-performance I/O model, and the node-level optimizations which enable us to obtain efficient processing throughput. In particular, we point out an interesting double level of parallelization arising in the data decomposition which increases substantially our ability to support ''high volume'' SAR. Results are presented from this code running in parallel on the Intel Paragon. A representative set of SAR data, of size 800 Megabytes, which was collected by the SIR-C/X-SAR instrument aboard NASA's Space Shuttle in 15 seconds, is processed in 55 seconds on the Concurrent Supercomputing Consortium's Paragon XP/S 35+. This compares well with a time of 12 minutes for the current SIR-C/X-SAR processing system at JPL. For the first time, a commercial system can process SIR-C/X-SAR data at a rate which is approaching the rate at which the SIR-C/X-SAR instrument can collect the data. This work has successfully demonstrated the viability of the Intel Paragon supercomputer for processing ''high volume" Synthetic Aperture Radar data in near real-time.
Architectural partitioning of control memory for application specific programmable processors
Authors: Wei Zhao, Christos A. Papachristou
Venue: Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design (1995)

Abstract: Because of programmability of Application Specific Programmable Processors (ASPPs), microcode-based control is effectively used to drive ASPP datapaths for different applications. In ASPPs, each application needs a separate microprogram resulting in large microcode memory. This paper proposes a distributed microcode memory model in which only distinct microcodes are stored in each separate memory module to save memory area. A hierarchical clustering approach is also proposed for the design of this distributed microcode memory. Experimental results indicate this approach is especially well suited for ASPP microcode memory design because of the existence of repetitive microcodes across multiple behaviors.
User interface software tools
Authors: Brad A. Myers
Venue: ACM Transactions on Computer-Human Interaction (TOCHI) (1995)

Almost as long as there have been user interfaces, there have been special software systems and tools to help design and implement the user interface software. Many of these tools have demonstrated significant productivity gains for programmers, and have become important commercial products. Others have proven less successful at supporting the kinds of user interfaces people want to build. This article discusses the different kinds of user interface software tools, and investigates why some approaches have worked and others have not. Many examples of commercial and research systems are included. Finally, current research directions and open issues in the field are discussed.
Effective cache prefetching on bus-based multiprocessors
Authors: Dean M. Tullsen, Susan J. Eggers
Venue: ACM Transactions on Computer Systems (TOCS) (1995)

Compiler-directed cache prefetching has the potential to hide much of the high memory latency seen by current and future high-performance processors. However, prefetching is not without costs, particularly on a shared-memory multiprocessor. Prefetching can negatively affect bus utilization, overall cache miss rates, memory latencies and data sharing. We simulate the effects of a compiler-directed prefetching algorithm, running on a range of bus-based multiprocessors. We show that, despite a high memory latency, this architecture does not necessarily support prefetching well, in some cases actually causing performance degradations. We pinpoint several problems with prefetching on a shared-memory architecture (additional conflict misses, no reduction in the data-sharing traffic and associated latencies, a multiprocessor's greater sensitivity to memory utilization and the sensitivity of the cache hit rate to prefetch distance) and measure their effect on performance. We then solve those problems through architectural techniques and heuristics for prefetching that could be easily incorporated into a compiler: (1) victim caching, which eliminates most of the cache conflict misses caused by prefetching in a direct-mapped cache, (2) special prefetch algorithms for shared data, which significantly improve the ability of our basic prefetching algorithm to prefetch individual misses, and (3) compiler-based shared-data restructuring, which eliminates many of the invalidation misses the basic prefetching algorithm does not predict. The combined effect of these improvements is to make prefetching effective over a much wider range of memory architectures.
Transparent running and contextual help to learn and to teach an imperative language
Authors: Jean-François Brette
Venue: ACM SIGCSE Bulletin (1995)

This paper presents the design choices and the realization of an imperative programming learning tool. This tool follows a Guided Discovery Learning line and is concentrated on the dynamic processes. On the one hand, transparent runnings enable a better understanding of the roles of the variables: proper reactive interfaces will help the student to compare his own conceptions with the actual behavior of the program. On the other hand, a contextual 'intelligent' help on types constraint errors highlights the domain structuration through different suggestions of the system.
Tail recursion elimination in deductive databases
Authors: Kenneth A. Ross
Venue: ACM Transactions on Database Systems (TODS) (1996)

We consider an optimization technique for deductive and relational databases. The optimization technique is an extension of the magic templates rewriting, and it can improve the performance of query evaluation by not materializing the extension of intermediate views. Standard relational techniques, such as unfolding embedded view definitions, do not apply to recursively defined views, and so alternative techniques are necessary. We demonstrate the correctness of our rewriting. We define a class of &ldquo;nonrepeating&rdquo; view definitions, and show that for certain queries our rewriting performs at least as well as magic templates on nonrepeating views, and often much better. A syntactically recognizable property, called &ldquo;weak right-linearity&rdquo;, is proposed. Weak right-linearity is a sufficient condition for nonrepetition and is more general than right-linearity. Our technique gives the same benefits as right-linear evaluation of right-linear views, while applying to a significantly more general class of views.
A Heuristic Scheduling of Independent Tasks with BottleneckResource Constraints
Authors: Qingzhou Wang, Ernst L. Leiss
Venue: SIAM Journal on Computing (1995)

In this paper, the problem of scheduling independent tasks with bottleneck resource constraints is investigated. There is a set of independent tasks ${\cal T} = \{T_1, \ldots, T_n\}$ and a set of resources ${\cal R} = \{R_1, \ldots, R_m\}$. The available amount of resource $R_j$, for $j = 1, \ldots, m$, is (normalized to) 1. Each task $T_i$'s execution requires at least $\lambda_{(i,j)} \leq 1$ units of resource $R_j \in {\cal R}$, and with these minimal resources, the execution time of $T_i$ is $\tau_i$. If there is a resource $R_{\beta(i)}$ so that $T_i$ can use $\xi$ units $(\xi \geq \lambda_{(i, \beta(j))})$ and reduce the execution time to $\frac{\lambda_{(i, \beta(i))}}{\xi} \tau_{i}$, we say that $T_i$ can achieve linear speed-up with respect to $R_{\beta(i)}$. It is assumed that for each $T_i$, there is one, and only one, resource $R_{\beta(i)}$ that is $T_i$'s bottleneck resource: $T_i$ can use $\xi$ units of $R_{(i, \beta(i))}$ and achieve linear speed-up, where $\xi$ is between $\lambda_{(i, \beta(i))}$ and $\Lambda_{(i, \beta(i))} \leq 1$. The problem is to find a feasible schedule for all the tasks in ${\cal T}$ that has a shortest overall makespan. This problem is a combination of two previously studied problems---scheduling tasks with resource constraints [SIAM J. Comput., 4 (1975), pp.~187--200.] scheduling parallel tasks [SIAM J. Comput., 21 (1992), pp.~281--294]. A variant of this problem was studied in [J. Combin. Theory, 21 (1976), pp.~257--298]. Because the problem is NP-hard, we propose the ECT (earliest completion time) algorithm as a heuristic solution and show that the performance ratio of the ECT makespan $M_{{\scriptsize ECT}}$ to the optimal makespan $M_{{\scriptsize OPT}}$ is bounded by $2l+m+1$, where $l$ is the number of the bottleneck resources in ${\cal R}$. When $l=0$, this is exactly the performance bound shown by Garey and Graham in [SIAM J. Comput., 4 (1975), pp.~187--200].
A distributed mutual exclusion algorithm
Authors: Ichiro Suzuki, Tadao Kasami
Venue: ACM Transactions on Computer Systems (TOCS) (1985)

A distributed algorithm is presented that realizes mutual exclusion among N nodes in a computer network. The algorithm requires at most N message exchanges for one mutual exclusion invocation. Accordingly, the delay to invoke mutual exclusion is smaller than in an algorithm of Ricart and Agrawala, which requires 2*(N - 1) message exchanges per invocation. A drawback of the algorithm is that the sequence numbers contained in the messages are unbounded. It is shown that this problem can be overcome by slightly increasing the number of message exchanges.
Business process oriented information management: conceptual models at work
Authors: P. Peters, P. Szczurko, M. Jarke, M. Jeusfeld
Venue: Proceedings of conference on Organizational computing systems (1995)

The reorganization of function-oriented, hierachically structured firms into interacting business process networks of functional islands integrated by flow of material and information is a major challenge for a company that wants to meet the steadily changing business demands of today. As information has become an important production resource during the last decades, the reorganization of information management has to accompany organizational restructuring. In this paper we propose a partially decentralized and business process oriented information management approach for quality management processes. We will describe how conceptual modeling of those processes supports the information system design within this approach. Staring from a presentation of the developed architecture, we will describe our experiences with several information access and engineering mechanisms that make use of the defined conceptual models.
Serverless network file systems
Authors: Thomas E. Anderson, Michael D. Dahlin, Jeanna M. Neefe, David A. Patterson, Drew S. Roselli, Randolph Y. Wang
Venue: ACM Transactions on Computer Systems (TOCS) (1996)

We propose a new paradigm for network file system design: serverless network file systems. While traditional network file systems rely on a central server machine, a serverless system utilizes workstations cooperating as peers to provide all file system services. Any machine in the system can store, cache, or control any block of data. Our approach uses this location independence, in combination with fast local area networks, to provide better performance and scalability than traditional file systems. Furthermore, because any machine in the system can assume the responsibilities of a failed component, our serverless design also provides high availability via redundatn data storage. To demonstrate our approach, we have implemented a prototype serverless network file system called xFS. Preliminary performance measurements suggest that our architecture achieves its goal of scalability. For instance, in a 32-node xFS system with 32 active clients, each client receives nearly as much read or write throughput as it would see if it were the only active client.
Multithreading in C++
Authors: John English
Venue: ACM SIGPLAN Notices (1995)

This paper describes the design and implementation of a C++ class library which provides timesliced multithreading capabilities for C++ programs. The implementation described here runs under MS-DOS on an IBM PC, but the library could easily be reimplemented for other systems. The library and its source code are freely available by anonymous FTP from a number of sites.
A fast asynchronous GVT algorithm for shared memory multiprocessor architectures
Authors: Z. Xiao F. Gomes, B. Unger, J. Cleary
Venue: ACM SIGSIM Simulation Digest (1995)

The computation of Global Virtual Time is of fundamental importance in Time Warp based Parallel Discrete Event Simulation Systems. Shared memory multiprocessor architectures can support interprocess communication with much smaller overheads than distributed memory systems. This paper presents a new, completely asynchronous, Gvt algorithm which provides very fast and accurate Gvt estimation with significantly lower overhead than previous approaches. The algorithm presented is able to support more efficient memory management, termination, and other global control mechanisms.The Gvt algorithm described enables any Time Warp entity to compute Gvt at any time without slowing down other entities, in particular, those executing on the critical path. Experimental results are presented for a shared memory Time Warp system that employs a two tiered distributed memory management scheme.The proof of the correctness and the accuracy of the algorithm are also presented. Finally, some suggestions on possible further optimization of the implementation are given.
Algorithm 762: LLDRLF, log-likelihood and some derivatives for log-F models
Authors: Barry W. Brown, Lawrence B. Levy, James Lovato, Kathy Russell, Floyd M. Spears
Venue: ACM Transactions on Mathematical Software (TOMS) (1996)

The flexible statistical models incorporating the log-F distribution are little used because of numeric difficulties. We describe a method for calculating the log-likelihood and two derivatives with respect to the data argument. Fortran subroutines incorporating these calculations are provided.