ppxscal/embedding_network huggingface dataset:
Toward Scalability and Interoperability of Heterogeneous Information Sources
Authors: Son Dao
Venue: Proceedings of the Eleventh International Conference on Data Engineering (1995)

Future large and complex information systems create new challenges and opportunities for research and advanced development in data management. A brief description of Hughes research and prototype efforts to meet these challenges is summarized.
Teaching an OLTP Database Kernel Advanced Data Warehousing Techniques
Authors: Clark D. French
Venue: Proceedings of the Thirteenth International Conference on Data Engineering (1997)

Most, if not all, of the major commercial database products available today were written more than 10 years ago. Their internal designs have always been heavily optimized for OLTP applications. Over the last couple of years as DSS and data warehousing have become more important, database companies have attempted to increase their performance with DSS-type applications. Most of their attempts have been in the form of added features like parallel table scans and simple bitmap indexing techniques. These were chosen because they could be quickly implemented (1-2 years), giving some level of increased query performance. The paper contends that the real performance gains for the DSS application have not yet been realized. The performance gains for DSS will not come from parallel table scans, but from major changes to the low level database storage management used by OLTP systems. One Sybase product, Sybase-IQ has pioneered some of these new techniques. The paper discusses a few of these techniques and how they could be integrated into an existing OLTP database kernel.
An Editing System for Working Processes
Authors: Yin-Shinn Chen, Feng-Jian Wang
Venue: Proceedings of the 25th International Computer Software and Applications Conference on Invigorating Software Development (2001)

Business processes are often complex and varying. Workflow technologies help people minimize errors and delays in the progress of a process within an enterprise. Within a workflow management system (WFMS), a process or even a project can be specified and interpreted to work directly. In this paper, we present an editing system and its two major components, PDE and FormDesigner, for the specification of a process. PDE is a graphical editor for constructing / modifying process definition. FormDesigner assumes the responsibility of integrating software components for building / modifying active application forms. With PDE and FormDesigner, a workflow application system can be constructed / modified rapidly and easily so that WFMS is allowed to run smoothly.
On the Impossibility of Min-Process Non-Blocking Checkpointing and An Efficient Checkpointing Algorithm for Mobile Computing Systems
Authors: Guohong Cao, Mukesh Singhal
Venue: Proceedings of the 1998 International Conference on Parallel Processing (1998)

Mobile computing raises many new issues, such as lack of stable storage, low bandwidth of wireless channel, high mobility, and limited battery life. These new issues make traditional checkpointing algorithms unsuitable. Prakash and Singhal \cite{PraSin96} proposed the first coordinated checkpointing algorithm for mobile computing systems. However, we showed that their algorithm may result in an inconsistency \cite{CaoSin97}. In this paper, we prove a more general result about coordinated checkpointing: there does not exist a non-blocking algorithm that forces only a minimum number of processes to take their checkpoints. Based on the proof, we propose an efficient algorithm for mobile computing systems, which forces only a minimum number of processes to take checkpoints and dramatically reduces the blocking time during the checkpointing process. Correctness proofs and performance analysis of the algorithm are provided.
Efficient Processor Allocation Scheme for Multi Dimensional Interconnection Networks
Authors: Hyunseung Choo, Hee Yong Youn, Gyung-Leen Park, Behrooz Shirazi
Venue: Proceedings of the international Conference on Parallel Processing (1997)

Abstract - The task scheduling policy ans the processor allocation scheme affect the system performance significantly. In this paper, we propose an efficient processor allocation scheme for 3D mesh interconnection network with a simple FIFO scheduling policy. Complexity analysis shows that the allocation and deallocation of the scheme are O(LWH2 ) and O(LH), respectively, which are better than earlier schemes. Comprehensive computer simulation shows that the averuge allocation time of the proposed scheme is improved up to about 25% comparing to the best earlier 30 approach.
Parallel Synchronization of Continuous Time Discrete Event Simulators
Authors: Peter Frey, Harold W. Carter, Philip A. Wilsey
Venue: Proceedings of the international Conference on Parallel Processing (1997)

Mixed-Mode simulation has been generating considerable interest in the simulation community and has continued to grow as an active research area. Traditional mixed-mode simulation involves the merging of digital and analog simulators in various ways. However, efficient methods for the synchronization between the two time domains remains elusive. This is due to the fact that the analog simulator uses dynamic time step control whereas the digital simulator uses the event driven paradigm. This paper proposes two new synchronization methods and presents their capabilities using a component-based continuous-time simulator integrated with an optimistic parallel discrete event simulator. The results of the performance evaluation leads us to believe that while both synchronization methods are functionally viable, one has superior performance.
The resource conflict methodology for early-stage design space exploration of superscalar RISC processors
Authors: John-David Wellman, Edward S. Davidson
Venue: Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors (1995)

In this paper we propose a new execution trace driven simulation technique, called the Resource Conflict Methodology (RCM) for modeling and simulating computer systems early in the design cycle. By using a simplified hardware element model which allows the user to easily add or delete hardware elements in the model, RCM allows the user to readily change the machine design being investigated and to evaluate the resulting machine on a given workload. We describe the RCM model with reference to a family of superscalar processors and develop an RCM-based analysis program (called REAP) for this family of processors. Using REAP, we demonstrate the validity of our method by comparing its RCM performance estimates to those of a traditional early design stage timer model.
Coarse Grained Parallel Maximum Matching In Convex Bipartite Graphs
Authors: P. Bose, Albert Chan, Frank K. H. A. Dehne, M. Latzel
Venue: Proceedings of the 13th International Symposium on Parallel Processing and the 10th Symposium on Parallel and Distributed Processing (1999)

We present a coarse grained parallel algorithm for computing a maximum matching in a convex bipartite graph G = (A; B; E).For p processors with N=p memory per processor, N = jAj +jBj, N=p = p, the algorithm requires O(log p) communication rounds and O(Tsequ( n p ; m p ) + n p log p) local computation, where n = jAj, m = jBj and Tsequ(n; m) is the sequential time complexity for the problem. For the BSP model, this implies O(log p) supersteps with O(gN + g n p log p) communication cost and O(Tsequ( n p ; m p ) + n p log p) local computation.
Medial Axes Neuronal Codification in Topographical Maps
Authors: Luciano da Fontoura Costa
Venue: Proceedings of the 15th Brazilian Symposium on Computer Graphics and Image Processing (2002)

A simple neuronal model for medial axes codification in biological vision systems is presented which is based on the concept of the propagation of wavefronts along topographically organized cortical structures.
An Inverse-Ackermann Style Lower Bound for the Online Minimum Spanning Tree
Authors: Seth Pettie
Venue: Proceedings of the 43rd Symposium on Foundations of Computer Science (2002)

We consider the problem of preprocessing an edge-weighted tree T in order to quickly answer queries of the following type: does a given edge e belong in the minimum spanning tree of T \cup \{ e\}? Whereas the offline minimum spanning tree verification problem admits a lovely linear time solution, we demonstrate an inherent inverse-Ackermann type tradeoff in the online MST verification problem. In particular, any scheme that answers queries in t comparisons must invest \Omega (n\log \lambda _t (n)) time preprocessing the tree, where \lambda _tis the inverse of the tth row of Ackermann's function. This implies a query lower bound of \Omega (\alpha (n)) for the case of linear preprocessing time. We also show that our lower bound is tight to within a factor of 2 in the t parameter.
Temporal Characterization of Demands for Data Movement on Parallel Programs
Authors: Bernardo Rodriguez, Harry F. Jordan, Gita Alaghband
Venue: Proceedings of the 10th International Parallel Processing Symposium (1996)

We propose a metric to characterize program demands for data movement at small time scales. This metric is computed statically over SPMD programs for a particular number of processors. We build a model to define time scales at which the execution progress of distinct processors can be consider equal and use operation count to define temporal distance between operations. We apply the metric to a set of programs that are part of the Splash benchmarks and discuss the results.
Local Skew Angle Estimation from Background Space in Text Regions
Authors: Apostolos Antonacopoulos
Venue: Proceedings of the 4th International Conference on Document Analysis and Recognition (1997)

Almost all document analysis approaches need to perform a global analysis of the page orientation as a separate process at an early stage. It would be preferable to estimate the orientation locally after page segmentation and classification, when more knowledge about the different regions is available. In this paper, a novel local skew estimation method is presented that takes advantage of the information available after flexible and efficient page segmentation and classification methods have been applied to the document image. The proposed method accurately estimates the orientation of individual text regions by efficiently analysing the arrangement of background space contained in them. No assumption is made of the existence of a uniform or dominant orientation in the document. The whole process is very efficient, as only the regions of text are considered and the points used for the angle estimation are already available as by-products of previous document analysis stages.
Monitoring and controlling remote parallel computations using Schooner
Authors: Zhanliang Chen, Richard D. Schlichting
Venue: Proceedings of the 9th International Symposium on Parallel Processing (1995)

Scientific visualization systems such as AVS have the potential to help users of parallel systems monitor and control their computations. Unfortunately, the machines most suitable for visualization systems are not the parallel systems on which the computation executes, often leading to the use of two distinct machines and the viewing of results only after the computation has completed. Here, an approach to solving this problem is presented in which AVS and a remote parallel computation are incorporated into a single metacomputation using the Schooner software interconnection system. This scheme gives the user enhanced control, including the ability to dynamically select the parallel platform to be used, monitor the progress of the computation, and modify parameters.
Fuzzy Data Mining: Effect of Fuzzy Discretization
Authors: Hisao Ishibuchi, Takashi Yamamoto, Tomoharu Nakashima
Venue: Proceedings of the 2001 IEEE International Conference on Data Mining (2001)

When we generate association rules, continuous attributes have to be discretized into intervals while our knowledge representation is not always based on such discretiztion.Forexample, we usually use some linguistic terms (e.g., young, middle age, and old) for dividing our ages into somefuzzy categories.In this paper, we describe the extraction of linguistic association rules and examine the performanceof extracted rules.First we modify the definitions of the two basic measures (i.e., confidence and support) ofassociation rules for extracting linguistic association rules. The main difference between standard and linguistics association rules is the discretiztion of continuous attributes. We divide the domain interval of each attribute into some Fuzzy discretiztion with standard on-fuzzy discretiztion Through computer simulations on a pattern classificationproblem with many continuous attributes.The classification performance of extracted rules on unseen test patterns is examined under various conditions.Simulation results show that linguistic association rules with rule weights have highgeneralization ability even when the domain of each continuous attribute is homogeneously partitioned.
Crossbar Analysis for Optimal Deadlock Recovery Router Architecture
Authors: Yungho Choi, Timothy Mark Pinkston
Venue: Proceedings of the 11th International Symposium on Parallel Processing (1997)

We explore the design of optimal deadlock recovery-based fully adaptive routers by evaluating promising internal router crossbar designs. Unified and decoupled crossbar designs aimed at exploiting the full capabilities of adaptive routing are evaluated by analyzing their effect on overall network performance. We show that an enhanced hierarchical crossbar design that supports routing locality in virtual network class achieves highest performance with relatively low cost.
Optimal System of Loops on an Orientable Surface
Authors: Éric Colin de Verdière, Francis Lazarus
Venue: Proceedings of the 43rd Symposium on Foundations of Computer Science (2002)

Every compact orientable boundaryless surface M can be cut along simple loops with a common point v0, pairwise disjoint except at v0, so that the resulting surface is a topological disk; such a set of loops is called a fundamental system of loops for M . The resulting disk is a polygon in which the edges are pairwise identified on the surface; it is called a polygonal schema. Assuming that M is triangulated, and that each edge has a given length, we are interested in a shortest (or optimal) system homotopic to a given one, drawn on the vertex-edge graph of M. We prove that each loop of such an optimal system is a shortest loop among all simple loops in its homotopy class. We give a polynomial (under some reasonable assumptions) algorithm to build such a system. As a byproduct, we get a polynomial algorithm to compute a shortest simple loop homotopic to a given simple loop.
Reducing Waiting Costs in User-Level Communication
Authors: Stefanos N. Damianakis, Yuqun Chen, Edward W. Felten
Venue: Proceedings of the 11th International Symposium on Parallel Processing (1997)

Describes a mechanism for reducing the cost of waiting for messages in architectures that allow user-level communication libraries. We reduce waiting costs in two ways: by reducing the cost of servicing interrupts, and by carefully controlling when the system uses interrupts and when it uses polling. We have implemented our mechanism on the SHRIMP multicomputer and integrated it with our user-level sockets library. Experiments show that a hybrid spin-then-block strategy offers good performance in a wide variety of situations, and that speeding up the interrupt path significantly improves performance.
Pollution control caching
Authors: Stephen J. Walsh, John A. Board
Venue: Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors (1995)

The bandwidth mismatch of today's high speed processors and standard DRAMS is between a factor of 10 to 50. From 1995 to the year 2000 this mismatch is expected to grow to three orders of magnitude, necessitating greater emphasis for on-chip caches. Today on-chip caches typically consume from 20% to 50% of the total chip area and their cost is mostly a function of the chip area they consume. Clearly, any technique which can maintain memory performance and reduce chip area requirements is extremely important. In this paper we present two novel cache architectures called pollution control caching (PCC) and pollution control caching plus victim buffering (PCC+VB). We have used trace driven simulation to obtain miss ratio statistics and we developed analytical models of the expected clock cycles per instruction (E[CPI]) for each architecture and cache size studied. Analytical models were parameterized with the results of our trace driven simulation. These models incorporate provisions to study the effect that on-chip cache size has on access time, and the effect that this and different main memory latencies have on the E[CPI]. Chip area models were also developed for each architecture and used as a basis for comparison. Finally, we used ANOVA techniques to better quantify the differences in the miss rate performance of the cache sizes and cache architectures studied. Our research has shown that, given the constraints of our design space, PCC+VB equipped caches can match the miss rate performance and E[CPI] of direct napped caches that require greater than five times the silicon area.
Time-Triggered Message-Triggered Object Modeling of a Distributed Real-Time Control Application for Its Real-Time Simulation
Authors: Moon Hae Kim, Jung-Guk Kim, K. H. Kim, Myeong-Soo Lee, Shin-Yeol Park
Venue: 24th International Computer Software and Applications Conference (2000)

The time-triggered message-triggered object (TMO) has been devised as the basic component model for high-level distributed real-time programming as well as real-time application system/subsystem design and modeling. One of the strengths of the TMO is its facilitation of multi-phased top-down modeling of real-time distributed computing application systems. TMO-structured models are capable of representing both a real-time control system and its controlled facilities (composed of sensors, actuators, and monitored infrastructure) in a uniform fashion. Also, TMO-structured real-time simulation models can be generated in attractively simple forms and they can be executed to enable examination of not only the logical accuracy of a real-time control system being developed but also the correctness of its timing behavior. A case study of such simulation modeling has been conducted in the context of constructing a real-time simulator of a real-time control system called the safety injection system (SIS), which is a subsystem of a nuclear power plant. In the course of this case study, some tools that support efficient real-time simulation have been developed. The refined modeling steps, the support tools developed, and the cost-effectiveness confirmed in the course of this case study are the main subjects discussed in this paper.
Partial Video Sequence Caching Scheme for VOD Systems with Heterogeneous Clients
Authors: Y. M. Chiu, K. H. Yeung
Venue: Proceedings of the Thirteenth International Conference on Data Engineering (1997)

Video on Demand is one of the key application in the information era. An hinge factor to its wide booming is the huge bandwidth required to transmit digitized video to a large group of clients with widely varying requirements. This paper addresses issues due to heterogeneous clients by proposing a program caching scheme called Partial Video Sequence (PVS) Caching Scheme. PVS Caching Scheme decomposes video sequences into a number of parts by using a scalable video compression algorithm. Video parts are selected to be cached in local video servers based on the amount of bandwidth it would be demanded from the distribution network and central video server if it is only kept in central video server. In this paper, we also show that PVS Caching Scheme is suitable for handling vastly varying client requirements.
Fast Parallel Computation of the Polynomial Shift
Authors: Eugene V. Zima
Venue: Proceedings of the 11th International Symposium on Parallel Processing (1997)

Given an n-degree polynomial f(x) over an arbitrary ring, the shift of f(x) by c is the operation which computes coefficients of the polynomial f(x+c). This operation is used in many applications such as, for example, polynomial roots isolation, changing polynomial basis etc. The complexity of the shift (the number of ring operations performing the shift) computed sequentially by straightforward formula is O(n^3). Known methods (such as based on Horner scheme or "synthetic division") reduce the complexity to O(n^2). Parallelization of these methods gives O(n) complexity of the procedure.In this paper we concentrate on the case when the shift by given constant c has to be performed several times (repeatedly) . We propose a parallel algorithm suited for SIMD architecture to perform the shift in O(1) time if we have O(n^2) Processor Elements available.Algorithm is based on converting a given polynomial to the special matrix representation. The complexity of the conversion is O(n). Algorithm proposed is easy to generalize to multivariate polynomials shift. We show that after some preliminary work the shift of d-variate polynomial can be performed in O(d) parallel steps. The possibility of applying this algorithm to polynomials with coefficients from non-commutative rings is discussed as well as the bit-wise complexity of the algorithm.
Metrics-Guided Quality Management for Component-Based Software Systems
Authors: Sahra Sedigh-Ali, Arif Ghafoor, Raymond A. Paul
Venue: Proceedings of the 25th International Computer Software and Applications Conference on Invigorating Software Development (2001)

The growing reliance on Commercial-Off-The-Shelf (COTS) components for developing large-scale projects introduces a new paradigm in software engineering, which requires the design of new software development and business processes. Large scale component reuse leads to savings in development resources, enabling these resources to be applied to areas such as quality improvement. These savings come at the price of integration difficulties, performance constraints, and incompatibility of components from multiple vendors. Relying on COTS components also increases the system's vulnerability to risks arising from third-party development, which can negatively affect the quality of the system, as well as causing expenses not incurred in traditional software development. We aim to alleviate such concerns by using software metrics to accurately quantify factors contributing to the overall quality of a Component-Based System (CBS), guiding quality and risk management by identifying and eliminating sources of risk.
Kiloprocessor Extensions to SCI
Authors: Stefanos Kaxiras
Venue: Proceedings of the 10th International Parallel Processing Symposium (1996)

To expand the Scalable Coherent Interface's (SCI) capabilities so it can be used to efficiently handle sharing in systems of hundreds or even thousands of processors, the SCI working group is developing the Kiloprocessor Extensions to SCI. In this paper we describe the proposed GLOW and STEM kiloprocessor extensions to SCI. These two sets of extensions provide SCI with scalable reads and scalable writes to widely-shared data. This kind of datum represents one of the main obstacles to scalability for many cache coherence protocols. The GLOW extensions are intended for systems with complex networks of interconnected SCI rings, (e.g., large networks of workstations). GLOW extensions are based on building k-ary sharing trees that map well to the underlying topology. In contrast, STEM is intended for systems where GLOW is not applicable (e.g., topologies based on centralized switches). STEM defines algorithms to build and maintain binary sharing trees. We show that latencies of GLOW reads and writes grow only logarithmically with the number of nodes sharing, in contrast to SCI where latencies grow linearly, therefore validating GLOW as a good solution to efficient wide sharing of data. Previous work showed the same for STEM.