ppxscal/embedding_network huggingface dataset:
Ogg Vorbis&mdash;Open, Free Audio&mdash;Set Your Media Free
Authors: Jack Moffitt
Venue: Linux Journal (2001)

Ogg Vorbis is the Open Source Community's hot alternative to MP3.
Enhancing the computer networking curriculum
Authors: Jon Rickman, Merry McDonald, Gary McDonald Phillip Heeler
Venue: Proceedings of the 6th annual conference on Innovation and technology in computer science education (2001)

An increasing number of students in computer science are requesting advanced study and active learning experiences in computer networking. Employers need graduates who not only understand the fundamentals of networking but those who can quickly be involved in network administration. Meeting these demands in the curriculum suggests that new and well-planned laboratory and internship experiences should be incorporated into the computer science curriculum. However, there are some major challenges in providing these experiences; it is much more complex than just adding another compiler or server to a laboratory. This paper describes several efforts the authors are making to meet these challenges.The environment in which these efforts have been studied is a small state-supported university, Northwest Missouri State University, in rural Missouri. Northwest has over 6,200 students pursuing baccalaureate, masters and specialist degrees. The networking environment at Northwest is more robust than one might expect. In 1987, the University became the first public institution in the United States to develop an "Electronic Campus" featuring University-provided, networked computing stations located in every residence hall room and faculty office. Then in 1999, each faculty member was issued a personal notebook computer and the residence halls were upgraded to Windows-based, networked desktop computers. [9]
How Bad May Learning Curves Be?
Authors: Hanzhong Gu, Haruhisa Takahashi
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (2000)

In this paper, we motivate the need for estimating bounds on learning curves of average-case learning algorithms when they perform the worst on training samples. We then apply the method of reducing learning problems to hypothesis testing ones to investigate the learning curves of a so-called ill-disposed learning algorithm in terms of a system complexity, the Boolean interpolation dimension. Since the ill-disposed algorithm behaves worse than ordinal ones, and the Boolean interpolation dimension is generally bounded by the number of system weights, the results can apply to interpreting or to bounding the worst-case learning curve in real learning situations. This study leads to a new understanding of the worst-case generalization in real learning situations, which differs significantly from that in the uniform learnable setting via Vapnik-Chervonenkis (VC) dimension analysis. We illustrate the results with some numerical simulations.
On quadratic adaptive routing algorithms
Authors: Carson E. Agnew
Venue: Communications of the ACM (1976)

Two analytic models of a store-and-forward communications network are constructed, one to find the optimal message routing and the other to illustrate the equilibrium (stationary state) maintained by an adaptive routing algorithm. These models show that adaptive routing does not satisfy the necessary conditions for an optimal routing. Adaptive routing tends to overuse the direct path and underuse alternate routes because it does not consider the impact of its current routing decision on the future state of the network. The form of the optimality conditions suggests that a modification of the adaptive algorithm will result in optimality. The modification requires the substitution of a quadratic bias term instead of a linear one in the routing table maintained at each network node. Simulation results are presented which confirm the theoretical analysis for a simple network.
Heap profiling for space-efficient Java
Authors: Ran Shaham, Elliot K. Kolodner, Mooly Sagiv
Venue: ACM SIGPLAN Notices (2001)

We present a heap-profiling tool for exploring the potential for space savings in Java programs. The output of the tool is used to direct rewriting of application source code in a way that allows more timely garbage collection (GC) of objects, thus saving space. The rewriting can also avoid allocating some objects that are never used. The tool measures the difference between the actual collection time and the potential earliest collection time of objects for a Java application. This time difference indicates potential savings. Then the tool sorts the allocation sites in the application source code according to the accumulated potential space saving for the objects allocated at the sites. A programmer can investigate the source code surrounding the sites with the highest savings to find opportunities for code rewriting that could save space. Our experience shows that in many cases simple code rewriting leads to actual space savings and in some cases also to improvements in program runtime. Experimental results using the tool and manually rewriting code show average space savings of 18% for the SPECjvm98 benchmark suite. Results for other benchmarks are also promising. We have also classified the program transformations that we have used and argue that in many cases improvements can be achieved by an optimizing compiler.
Processor-programmable memory BIST for bus-connected embedded memories
Authors: Ching-Hong Tsai, Cheng-Wen Wu
Venue: Proceedings of the 2001 Asia and South Pacific Design Automation Conference (2001)

We present a processor-programmable built-in self-test (BIST) scheme suitable for embedded memory testing in the system-on-a-chip (SOC) environment. The proposed BIST circuit can be programmed via an on-chip microprocessor. Upon receiving the commands from the microprocessor, the BIST circuit generates pre-defined test patterns and compares the memory outputs with the expected outputs. Most popular memory test algorithms can be realized by properly programming the BIST circuit using the processor instructions. Compared with processor-based memory BIST schemes that use an assembly-language program to generate test patterns and compare the memory outputs, the test time of the proposed memory BIST scheme is greatly reduced.
Systems analysis: the challenge of integrating two competing technologies
Authors: Paula Gabbert
Venue: Proceedings of the fourteenth annual consortium on Small Colleges Southeastern conference (2000)

As object oriented technologies continue to permeate industrial software development methodologies, it is imperative that the techniques used in these methodologies are re-evaluated. Classic top down structured analysis and design techniques are competing against object oriented techniques within these methodologies. This paper compares and contrasts both of these paradigms drawing conclusions about their strengths and weaknesses and suggesting that the two paradigms within systems analysis may actually provide similar information.
Improved approximation algorithms for rectangle tiling and packing
Authors: Piotr Berman, Bhaskar DasGupta, S. Muthukrishnan, Suneeta Ramaswami
Venue: Proceedings of the twelfth annual ACM-SIAM symposium on Discrete algorithms (2001)

We provide improved approximation algorithms for several rectangle tiling and packing problems (RTILE, DRTILE and d-RPACK) studied in the literature. Our algorithms are highly efficient since their running times are near-linear in the space input size rather than in the domain size. In addition, we improve the best known approximation ratios, in some cases quite significantly.
How can cooperative work tools support dynamic group process? bridging the specificity frontier
Authors: Abraham Bernstein
Venue: Proceedings of the 2000 ACM conference on Computer supported cooperative work (2000)

In the past, most collaboration support systems have focused on either automating fixed work processes or simply supporting communication in ad-hoc processes. This results in systems that are usually inflexible and difficult to change or that provide no specific support to help users decide what to do next.This paper describes a new kind of tool that bridges the gap between these two approaches by flexibly supporting processes at many points along the spectrum: from highly specified to highly unspecified. The development of this approach was strongly based on social science theory about collaborative work.
The computational metaphor and quantum physics
Authors: Michael J. Manthey, Bernard M.E. Moret
Venue: Communications of the ACM (1983)

Concurrent computational systems, viewed as sets of cooperating processes, are shown to have close analogies in the world of quantum physics. In particular, analogies exist between processes and particles, between a process' state and a particle's mass, between a process'state changes and a particle's velocity, and between interprocess communications and particle interactions. This view allows the application in the computational world of special relativity theory, the uncertainty principle, the law of conservation of momentum, and many of particle physics' fundamental results. This paper describes the basic analogy and some fundamental results. It is the authors' belief that new insights into a computational processes will be gained as the analogy is developed and vice versa. It is conceivable that established results of the computational sciences may contribute to a new understanding of some of the problems of physics. Other process-oriented sciences, such as biology, economics, and psychology, could also benefit from such development.
A Temperature Time Counter Scheme for the Boltzmann Equation
Authors: Sergej Rjasanow, Wolfgang Wagner
Venue: SIAM Journal on Numerical Analysis (2000)

This paper gives a rigorous derivation of a new stochastic particle method for the Boltzmann equation and illustrates its numerical efficiency. Using estimates based on the local temperature of the simulation cells, any truncation error related to large velocities is avoided. Moreover, time steps between collisions are larger than in the standard direct simulation method. This fact and an efficient modelling procedure for the index distribution of the collision partners lead to a considerable reduction of computational effort in certain applications.
ContextBox (extended abstract) (poster session): a visual builder for context beans
Authors: David H. Lorenz, Predrag Petkovic
Venue: Addendum to the 2000 proceedings of the conference on Object-oriented programming, systems, languages, and applications (Addendum) (2000)

We present an assembly-design environment that supports the JavaBeans extensible runtime containment and services protocol. The environment provides: a vehicle for demonstrating the Java component model; a third-party client for testing BeanContext and BeanContextChild components; and a prototype illustrating how a visual builder might unify visual and context nesting during component assembly.
Augmented reality: which augmentation for which reality?
Authors: Emmanuel Dubois, Laurence Nigay
Venue: Proceedings of DARE 2000 on Designing augmented reality environments (2000)

In this paper, we first present a brief review of approaches used for studying and designing Augmented Reality (AR) systems. The variety of approaches and definitions in AR requires classification. We define two intrinsic characteristics of AR systems, task focus and nature of augmentation. Based on these two characteristics, we identify four classes of AR systems. In addition our OP-a-S notation provides a complementary characterization method based on interaction. Using OP-a-S, an AR system is modeled as a set of components that communicate with each other. One crucial type of OP-a-S component is the Adapter that establishes a bridge between the real world and the virtual world. By defining a classification scheme, we aim at providing a better understanding of the paradigm of AR and at laying the foundations of future design principles according to the class of systems.
Detecting Independent Motion: The Statistics of Temporal Continuity
Authors: Robert Pless, Tomás&caron; Brodský, Yiannis Aloimonos
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (2000)

We consider a problem central in aerial visual surveillance applications¿detection and tracking of small, independently moving objects in long and noisy video sequences. We directly use spatiotemporal image intensity gradient measurements to compute an exact model of background motion. This allows the creation of accurate mosaics over many frames, and the definition of a constraint violation function which acts as an indicator of independent motion. A novel temporal integration method maintains confidence measures over long subsequences without computing the optic flow, requiring object models, or using a Kalman filter. The mosaic acts as a stable feature frame, allowing precise localization of the independently moving objects. We present a statistical analysis of the effects of image noise on the constraint violation measure and find a good match between the predicted probability distribution function and the measured sample frequencies in a test sequence.
Integrated power supply planning and floorplanning
Authors: I-Min Liu, Hung-Ming Chen, Tan-Li Chou, Adnan Aziz, D. F. Wong
Venue: Proceedings of the 2001 Asia and South Pacific Design Automation Conference (2001)

One of the most challenging issues in today's high-performance VLSI design is to ensure high-quality power supply to each individual circuit blocks. Reduced power supply voltage can result in slower cell switching, or even circuit failure. Nevertheless, most floorplanning methodologies have ignored power supply considerations. Thus, the resulting floorplan may suffer from local hot spots and insufficient power supply for certain circuit blocks. In this paper, we present an optimal power supply planning algorithm based on network flow to shorten the current paths from power bumps to local power supply wirings. We have incorporated our algorithm into a floorplanning algorithm for integrated floorplanning and power supply planning. Experimental results are encouraging.
Combining decision rules in a decision table
Authors: Keith Shwayder
Venue: Communications of the ACM (1975)

The techniques for minimizing logic circuits are applied to the simplification of decision tables by the combining of decision rules. This method is logically equivalent to the Quine-McCluskey method for finding prime implicants. If some of the decision rules implied in the ELSE Rule occur with low frequency, then the ELSE Rule can be used to further simplify the decision table. Several objectives merit consideration in optimizing a decision table: reducing machine execution time; reducing preprocessing time; reducing required machine memory; reducing the number of decision rules. (This often improves the clarity of the decision table to a human reader.) It will be shown that objectives (3) and (4) can be furthered with the above methods. Objective (1) is also attained if overspecified decision rules are not combined. Objective (2) must be compared against the potential benefits of objectives (1), (3), and (4) in deciding whether to use the above methods.
A semi-custom design flow in high-performance microprocessor design
Authors: Gregory A. Northrop, Pong-Fei Lu
Venue: Proceedings of the 38th annual Design Automation Conference (2001)

In this paper we present techniques shown to significantly enhance the custom circuit design process typical of high-performance microprocessors. This methodology combines flexible custom circuit design with automated tuning and physical design tools to provide new opportunities to optimized design throughout the development cycle.
Dynamic Access Ordering for Streamed Computations
Authors: Sally A. McKee, William A. Wulf, James H. Aylor, Maximo H. Salinas, Robert H. Klenke, Sung I. Hong, Dee A. B. Weikle
Venue: IEEE Transactions on Computers (2000)

Memory bandwidth is rapidly becoming the limiting performance factor for many applications, particularly for streaming computations such as scientific vector processing or multimedia (de)compression. Although these computations lack the temporal locality of reference that makes traditional caching schemes effective, they have predictable access patterns. Since most modern DRAM components support modes that make it possible to perform some access sequences faster than others, the predictability of the stream accesses makes it possible to reorder them to get better memory performance. We describe a Stream Memory Controller (SMC) system that combines compile-time detection of streams with execution-time selection of the access order and issue. The SMC effectively prefetches read-streams, buffers write-streams, and reorders the accesses to exploit the existing memory bandwidth as much as possible. Unlike most other hardware prefetching or stream buffer designs, this system does not increase bandwidth requirements. The SMC is practical to implement, using existing compiler technology and requiring only a modest amount of special-purpose hardware. We present simulation results for fast-page mode and Rambus DRAM memory systems and we describe a prototype system with which we have observed performance improvements for inner loops by factors of 13 over traditional access methods.
Representing super-sparse matrices with perturbed values
Authors: Harvey J. Greenberg, Richard P. O'Neill
Venue: Communications of the ACM (1981)

This paper describes a form of purposeful data perturbation in a linear programming model which pertains to uncertainties in the magnitudes of the matrix coefficients. A problem in value pool construction is described first, then a resolution based on a new concept, &ldquo;covering lattices.&rdquo; Computer representations of real values, limited by finite precision, is an example of a covering lattice. After presenting the strategy and tactical variations, the effects of resident distortion are analyzed. Several theorems are presented that measure bias under a variety of assumptions. An appendix is included that contains mathematical proofs.
Verifying security protocols as planning in logic programming
Authors: Luigia Carlucci Aiello, Fabio Massacci
Venue: ACM Transactions on Computational Logic (TOCL) (2001)

We illustrate ALSP (Action Language for Security Protocol), a declarative executable specification language for planning attacks to security protocols. ALSP is based on logic programming with negation as failure, and with stable model semantics. In ALSP we can give a declarative specification of a protocol with the natural semantics of send and receive actions which can be performed in parallel. By viewing a protocol trace as a plan to achieve a goal, attacks are (possibly parallel) plans achieving goals that correspond to security violations. Building on results from logic programming and planning, we map the existence of an attack into the existence of a model for the protocol that satisfies the specification of an attack. We show that our liberal model of parallel actions can adequately represent the traditional Dolev-Yao trace-based model used in the formal analysis of security protocols. Specifications in ALSP are executable, as we can automatically search for attacks via an efficient model generator (smodels), implementing the stable model semantics of normal logic programs.
Wire packing: a strong formulation of crosswalk-aware chip-level track/layer assignment with an efficient integer programming solution
Authors: R. Kay, R. A. Rutenbar
Venue: Proceedings of the 2000 international conference on Computer-aided design (2001)

By focusing on chip-wide slices of the global routing grid, making a few mild geometric assumptions about layer use, and suitably abstracting pin details, we derive an extremely efficient integer linear programming (ILP) formulation for track/layer assignment. The key technical insight is to model all constraints - both geometric and crosstalk - as cliques in an appropriate conflict graph; these cliques can be extracted quickly from the interval structures of wires in a slice. We develop a "strong" linear relaxation of this problem that almost always yields the integral optimum; this solution gives us directly the maximum number of wires that can pack legally without crosstalk risk. Experiments on synthetic netlists that match statistics of wire layouts from industrial 0.25um designs demonstrate that we can pack 100 - 1000 wires optimally, or with at worst a very few overflows, in seconds.
Current Directions in Automatic Test-Pattern Generation
Authors: Kwang-Ting Cheng, Angela Krstic
Venue: Computer (1999)

Test development can be tedious and time-consuming, sometimes stretching over several months for complex designs. In the past two decades, various test development automation tools have attempted to address this problem and reduce the bottleneck in the product's time to market. These tools, which automate dozens of tasks essential for developing adequate tests, generally fall into four categories: design for testability (DFT), test pattern generation, pattern-grading, and test program development and debugging. The focus in this article is on automatic test-pattern- generation tools. Researchers have looked primarily at issues such as scalability, ability to handle various fault models, and how to extend the algorithms beyond Boolean domains to handle different abstraction levels. Their aims were to speed up test generation, reduce test sequence length, and minimize power consumption. As design trends move toward nanometer technology, however, new ATPG problems are emerging. Current modeling and vector generation techniques must give way to new techniques that consider timing information during test generation, scale to larger designs, and can capture extreme design conditions. The authors describe current ATPG techniques and efforts to adapt ATPG technology to handle deep-submicron faults and to identify design errors and timing problems during design verification.
Intrusion confinement by isolation in information systems
Authors: Peng Liu, Sushil Jajodia, Catherine D. McCollum
Venue: Journal of Computer Security (2000)

System protection mechanisms such as access controls can be fooled by authorized but malicious users, masqueraders, and misfeasors. Intrusion detection techniques are therefore used to supplement them. However, damage could have occurred before an intrusion is detected. In many computing systems the requirement for a high degree of soundness of intrusion reporting can yield poor performance in detecting intrusions and cause long detection latency. As a result, serious damage can be caused either because many intrusions are never detected or the average detection latency is too long. The process of bounding the damage caused by intrusions during intrusion detection is referred to as intrusion confinement. We justify the necessity for intrusion confinement during detection by using a probabilistic analysis model, and propose a general solution to achieve intrusion confinement. The key idea of the solution is to isolate likely suspicious actions before a definite determination of intrusion is reported. We also present two concrete isolation protocols in the database and file system contexts, respectively, to evaluate the feasibility of the general solution, which can be applied to many types of information systems.
Algorithm 488: A Gaussian pseudo-random number generator
Authors: Richard P. Brent
Venue: Communications of the ACM (1974)

The algorithm calculates the exact cumulative distribution of the two-sided Kolmogorov-Smirnov statistic for samples with few observations. The general problem for which the formula is needed is to assess the probability that a particular sample comes from a proposed distribution. The problem arises specifically in data sampling and in discrete system simulation. Typically, some finite number of observations are available, and some underlying distribution is being considered as characterizing the source of the observations.