ppxscal/embedding_network huggingface dataset:
Optimisation and performance issues: things the user can do to exploit VAX Ada
Authors: Bevin Brett
Venue: Proceedings of the conference on TRI-ADA '90 (1990)

This talk is mainly about the Ada programming styles that users can adopt to exploit the optimisation capabilities of the Digital Equipment Corporation's VAX1 Ada compiler. We also discuss what users can do optimize the compilation performance of the VAX Ada compiler, and engage in some crystal ball gazing. The VAX Ada compiler generates large amounts of data that are consumed by DIGITAL's Performance and Coverage Analyser (PCA). This tool enables the quick and accurate identification of hotspots, along with direct correlation back to the original source code that should be examined for possible improvements. The compiler, by default, does all the traditional optimisations such as common subexpression exploitation, removal of loop invariants, and selecting tight code sequences with excellent register allocation. These optimisations can be inhibited, however, by several coding practices such as the use of `ADDRESS or implicit subunits that result from generic instantiations used to implement abstract data types. Guidelines for recognising such practices and replacing them with equally good but more efficient Ada practices will be given, along with several examples, during the presentation. The compiler also implements a wide range of advanced optimizations, which the user can also exploit or inhibit by the choice of programming style. This presentation will focus on the following areas - Inlining, Check Elimination, High Performance System Libraries, Generic Code Sharing, Memory Alignment of Variables and Components, Tasking and I/O, and Operations involving Composite Types. Much less understood than the techniques for improving execution times, but of equal import on many projects, and the ways of improving compilation, recompilation, and link times. The presentation will also cover how to set up a programming environment that can dramatically improve the wall-clock times needed to compile both small numbers of units, and also systems involving many thousands of units. This part of the presentation will be based on work DIGITAL has done with several large customers on real systems. Finally the presentation will involve some crystal ball gazing to describe possible future directions in improving both execution and development times, both for the DIGITAL Ada effort, and for the Ada community in general.
Analysis of a Minimum Perturbation Algorithm for Nonsymmetric Linear Systems
Authors: Ebrahim M. Kasenally, Valeria Simoncini
Venue: SIAM Journal on Numerical Analysis (1997)

This paper presents a theoretical analysis of a minimum perturbation Krylov subspace method for the solution of nonsymmetric linear systems $Ax=b$. At each step, the algorithm minimizes the joint backward perturbation norm $\|[\Delta_A, \Delta_b]\|_F$ of the matrix $[A,\, b]$ and computes an approximate solution $x_m$ satisfying $(A-\Delta_A)x_m=(b+\Delta_b)$. This process is a generalization of the Saad and Schultz generalized minimum residual (GMRES) algorithm [SIAM J. Sci. Statist. Comput., 7 (1986), pp. 856--869] and the generalized minimum backward error (GMBACK) process of Kasenally [ SIAM J. Sci. Comput., 16 (1995), pp. 698--719]. The minimum perturbation algorithm is used to analyze the performance of these Krylov subspace methods by gauging the proximity of their solutions to joint backward perturbation optimality. The relationships among these methods are thoroughly investigated and numerical results are provided to illustrate their key differences.
A Subdivision Scheme for Continuous-Scale B-Splinesand Affine-Invariant Progressive Smoothing
Authors: Guillermo Sapiro, Albert Cohen, Alfred M. Bruckstein
Venue: Journal of Mathematical Imaging and Vision (1997)

Multiscale representations and progressive smoothing constitute an important topic in different fields as computer vision, CAGD, and image processing. In this work, a multiscale representation of planar shapes is first described. The approach is based on computing classical B-splines of increasing orders, and therefore is automatically affine invariant. The resulting representation satisfies basic scale-space properties at least in a qualitative form, and is simple to implement.The representation obtained in this way is discrete in scale, since classical B-splines are functions in {\bf C}^{k-2}, where k is an integer bigger or equal than two. We present a subdivision scheme for the computation of B-splines of finite support at continuous scales. With this scheme, B-splines representations in {\bf C}^r are obtained for any real r in [0, \infty) , and the multiscale representation is extended to continuous scale.The proposed progressive smoothing receives a discrete set of points as initial shape, while the smoothed curves are represented by continuous (analytical) functions, allowing a straightforward computation of geometric characteristics of the shape.
A new model for scheduling packet radio networks
Authors: Arunabha Sen, Mark L. Huson
Venue: Wireless Networks (1997)

Packet radio networks are modeled as arbitrary graphs by most researchers. In this paper we show that an arbitrary graph is an inaccurate model of the radio networks. This is true because there exists a large class of graphs which will not model the radio networks. Radio networks can be modeled accurately by a restricted class of graphs called the planar point graphs. Since the radio networks can accurately be modeled only by a restricted class of graphs, the NP-completeness results for scheduling using an arbitrary graph as the model, do not correctly reflect the complexity of the problem. In this paper we study the broadcast scheduling problem using the restricted class as the model. We show that the problem remains NP-complete even in this restricted domain. We give an O(n log n) algorithm when all the transceivers are located on a line.
Healthcare information architecture: elements of a new paradigm
Authors: Daniel J. Essin, Thomas L. Lincoln
Venue: Proceedings of the 1994 workshop on New security paradigms (1994)

An Electronic Medical Record (EMR) must provide a secure, permanent archive for an individual's medical records and also function as a multi-purpose database that supports the complex, varied activities of patient care. Meeting these objectives requires unusual flexibility in how data are retrieved and processed. Semantic and referential integrity must preserved both over time and as chunks of information are exchanged with other systems. Relationships between data entries must determined dynamically based on actual events, rather than statically through application design. Distributed data requires that new forms of system security be incorporated into an EMR at a structural level, with an emphasis on the labeling of elements to be secured behind a security barrier, with audit trails to document necessary overrides and monitor for suspicious use. A modular information architecture is proposed that integrates requirements for structure, content, processing and security.
Convergence and Stability of Multistep Methods Solving Nonlinear Initial Value Problems
Authors: F. Iavernaro, F. Mazzia
Venue: SIAM Journal on Scientific Computing (1997)

Convergence and stability of initial and boundary value multistep methods are analyzed for a class of nonlinear problems, satisfying a one-sided Lipschitz condition. The linear multistep methods are recast to handle the numerical solution globally on the time interval. This allows us to use the theory of Toeplitz matrices to show that, under suitable assumptions, global properties of the exact solution are preserved by its numerical approximation. In particular, a new concept of stability, which avoids the unpleasant passage to one-leg methods, is introduced.
An efficient transistor folding algorithm for row-based CMOS layout design
Authors: Jaewon Kim, S. M. Kang
Venue: Proceedings of the 34th annual Design Automation Conference (1997)

In timing-driven layout synthesis, transistor sizes tend to besignificantly different from each other and thus the use of conventionallayout approaches can cause inefficient area utilization.We propose an efficient algorithm to find the optimaltransistor folding sizes in row-based designs.Our algorithmfinds optimal folding sizes given a CMOS circuit with m pairsof pMOS and nMOS transistors in O(m{2} log m) time complexitywith the effective reduction of the solution space.MCNCbenchmark circuits are used to demonstrate the area-efficiencyof the physical layouts with optimal folding sizes.
Database performance in the real world: TPC-D and SAP R/3
Authors: Joachen Doppelhammer, Thomas Höppler, Alfons Kemper, Donald Kossmann
Venue: Proceedings of the 1997 ACM SIGMOD international conference on Management of data (1997)

Traditionally, database systems have been evaluated in isolation on the basis of standardized benchmarks (e.g., Wisconsin, TPC-C, TPC-D). We argue that very often such a performance analysis does not reflect the actual use of the DBMSs in the &ldquo;real world.&rdquo; End users typically don't access a stand-alone database system; rather they use a comprehensive application system, in which the database system constitutes an integrated component. In order to derive performance evaluations of practical relevance to the end users, the application system including the database system has to be benchmarked. In this paper, we present TPC-D benchmark results carried out using the SAP R/3 system, an integrated business administration system. Like many other application systems SAP R/3 is based on a commercial relational database system. We compare the SAP R/3 benchmark results with TPC-D results of an isolated database system, the database product that served as SAP R/3's back-end.
System Identification by Dynamic Factor Models
Authors: C. Heij, W. Scherrer
Venue: SIAM Journal on Control and Optimization (1997)

This paper concerns the modeling of stochastic processes by means of dynamic factor models. In such models the observed process is decomposed into a structured part called the latent process and a remainder that is called noise. The observed variables are treated in a symmetric way so that no distinction between inputs and outputs is required. This motivates the additional condition that the prior assumptions on the noise are symmetric in nature. One of the central questions in this paper is how uncertainty about the noise structure translates into nonuniqueness of the possible underlying latent processes. We investigate several possible noise specifications and analyze properties of the resulting class of observationally equivalent factor models. This concerns in particular the characterization of optimal models and properties of continuity and consistency.
Experiences in building C++ front end
Authors: Fuqing Yang, Hong Mei, Wanghong Yuan, Qiong Wu, Yao Guo
Venue: ACM SIGPLAN Notices (1998)

It is difficult, if not impossible, for the code analyzers to employ front end from compilers, because these front ends extract different program information using different strategy. This paper describes our experiences in building C++ front end as a part of code analysis toolset. The front end customizes the lexical analyzer incorporating a special preprocessing technique to accurately associate program entities with physical source code location. To support analysis of different C++ languages, the front end employs YACC to generate the parser, and uses token lookahead technique to disambiguate C++ grammar for YACC.
Real time analysis and priority scheduler generation for hardware-software systems with a synthesized run-time system
Authors: Vincent J. Mooney,  III, Giovanni De Micheli
Venue: Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design (1997)

We present a tool, called Clara, that performs real-time analysis and priority assignment for software tasks in a mixed hardware-software system with a custom run-time scheduler. We start from a system described in tasks/threads consisting of hardware specified in Verilog and software specified in C. We obtain the worst case execution time for each individual task. Then, based on the control flow of the application, Clara uses a dynamic programmming algorithm to automatically find optimal priorities for the software tasks assuming no interrupts. Assuming the set of software tasks runs on a microprocessor in a target architecture using a template we provide for the priority scheduler and interrupt code, Clara then finds the worst case execution time for the application with interrupts allowed. Thus, this tool brings real-time analysis to a system level for a particular run-time system. Clara helps a designer minimize the worst case execution time of a mixed hardware-software application.
One-bit counts between unique and sticky
Authors: David J. Roth, David S. Wise
Venue: ACM SIGPLAN Notices (1999)

Stoye's one-bit reference tagging scheme can be extended to local counts of two or more via two strategies. The first, suited to pure register transactions, is a cache of referents to two shared references. The analog of Deutsch's and Bobrow's multiple-reference table, this cache is sufficient to manage small counts across successive assignment statements. Thus, accurate reference counts above one can be tracked for short intervals, like those bridging one function's environment to its successor's.The second, motivated by runtime stacks that duplicate references, avoids counting any references from the stack. It requires a local pointer-inversion protocol in the mutator, but one still local to the referent and the stack frame. Thus, an accurate reference count of one can be maintained regardless of references from the recursion stack.
The design and performance of a conflict-avoiding cache
Authors: Nigel Topham, Antonio González
Venue: Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture (1997)

High performance architectures depend heavily on efficient multi-level memory hierarchies to minimize the cost of accessing data. This dependence will increase with the expected increases in relative distance to main memory. There have been a number of published proposals for cache conflict-avoidance schemes. We investigate the design and performance of conflict-avoiding cache architectures based on polynomial modulus functions, which earlier research has shown to be highly effective at reducing conflict miss ratios. We examine a number of practical implementation issues and present experimental evidence to support the claim that pseudo-randomly indexed caches are both effective in performance terms and practical from an implementation viewpoint.
A traveling salesman in Java
Authors: Pascal Ledru
Venue: ACM SIGPLAN Notices (1998)

Java is a language which provides built-in multithreading and synchronized methods. Orca is a language for programming parallel applications on distributed computing systems. Processes in Orca communicate through shared-data objects. Shared-data objects provide both mutual exclusion synchronization as Java synchronized methods do, and condition synchronization which allows processes to wait until a certain condition becomes true. This paper presents how shared-data objects can be implemented in Java both on a shared memory system and on a distributed memory system. The traveling salesman problem is used to demonstrate how the transformation is achieved.
Modeling of chain conveyors and their equipment interfaces
Authors: Ali K. Gunal, Edward J. Williams, Shigeru Sadakane
Venue: Proceedings of the 28th conference on Winter simulation (1996)

Chain conveyors are a specific type of conveyor often used in a variety of manufacturing and production applications, such as body and paint shops. These conveyors must typically interface with other types of conveyors such as cross-transfer conveyors, and also with other material-handling equipment such as lift tables and hold tables. Micromodeling of chain conveyors and their equipment interfaces requires close attention to numerous details. These details include not only static and operational properties of the chain conveyors themselves, but also the particulars of dimensional and operational interfaces of the conveyors and the equipment served by the conveyors, such as lift tables and the conveyor acceleration and deceleration ramps. In this paper, we first delineate the situations in which micromodeling of material-handling equipment is appropriate. We then present an overview of conveyor types and terminology. Next, we describe the challenges of modeling chain conveyors accurately, and our recominendations for meeting these challenges within the framework of typical modeling tools and simulation-study contexts. As an example, we present details of these recommendations relative to the AutoMod modeling tool. In conclusion, we summarize these recomendations and indicate promising directions for further development of modeling techniques and enhancement of model-building tools.
Group consistency model which separates the intra-group consistency maintenance from the inter-group consistency maintenance in large scale DSM systems
Authors: Qun Li, Hua Ji, Li Xie
Venue: ACM SIGOPS Operating Systems Review (1997)

According to the characteristics of large scale network computing systems, we proposed a group consistency model based on the concept of group to construct a DSM system. The novel model can use different inter-group and intra-group consistencies and lend itself to flexible, easily-managable, and application-suitable DSM in large scale systems. A group consistency model, which applies entry consistency among groups and lazy release consistency in a group, together with its implementation policy is discussed in this paper. It employs write-update and multiple-writer protocols in a group, and thus facilitates the simultaneous read and write in a group. The suitable protocols eliminate the false sharing and reduce the data acquiring time in a group. Furthermore, the inter-group consistency also suits the features of data sharing among groups and transmits the data modifications originated from a group in bulk to reduce the network traffic. In the end, an example using group consistency model is given and the trivial group consistency is discussed.
A Heuristic Approach to the Multitask-Multiprocessor AssignmentProblem using the Empty-Slots Method and Rate Monotonic Scheduling
Authors: J. Santos, E. Ferro, J. Orozco, R. Cayssials
Venue: Real-Time Systems (1997)

A heuristic approach to the problem of assigning a set of preemptible resource-sharing and blockable real-time tasks to be executed in a set of heterogeneous processors communicated through an interprocessor network, is presented. The problem is NP-hard. The empty-slots method is used to test the RM schedulability in each processor. There are placement, time, memory, communication and precedence constraints. A general expression for the modification of hard-precedence deadlines of related tasks executing in the same or in different processors is given. The effects of the Average Processor Utilization Factor and the Network Bandwidth on the number of solutions found are shown and discussed through systematic sets of examples. Also, Success Ratios are obtained and plotted vs. Average Processor Utilization Factors for different Network Bandwidths. Results obtained are compared to those obtained by other methods.
Distance-Regular Graphs with Strongly RegularSubconstituents
Authors: Anna Kasikova
Venue: Journal of Algebraic Combinatorics: An International Journal (1997)

In [3] Cameron et al. classified strongly regular graphs with strongly regular subconstituents. Here we prove a theorem which implies that distance-regular graphs with strongly regular subconstituents are precisely the Taylor graphs and graphs witha_1=0 and a_i\in \ 0,1\ fori=2,\ldots,d .
High Accuracy Concurrent Event Processing in Hard Real-Time Systems
Authors: Wolfgang A. Halang, Markus Wannemacher
Venue: Real-Time Systems (1997)

A computer organisation suitable to improve the performance of embedded systems encountered in hard real-time environments is described, which enhances dependability and efficiency by exploiting possibilities for parallel processing inherent to real-time systems. It is shown that internal data transmissions due to context-switching can be eliminated and that CPUs can be relieved from a considerable amount of routine work by providing a separate module for major functions of real-time operating systems, viz., for interrupt and signal recognition, for time management, and for the administration of task execution plans and states. Considering the layer model of contemporary real-time operating systems, these functions constitute kernel and first layer. The hardware implementation of typical hard real-time support features provides a clear physical separation of the intrinsically independent functions event reaction and (user) task processing. While minimising response times in general, the architecture enables to guarantee predefined, short upper bounds for them. It also incorporates a new approach for and hardware realisation of timers characterised by utmost precision and high handling comfort. Such timers are particularly well-suited to serve in distributed real-time systems, since, by employing the exact UTC received from the satellites of GPS (the global navigation and positioning system), synchronisation is not needed anymore.
Concepts for knowledge-based system design environments
Authors: Jerzy W. Rozenblit, Bernard P. Zeigler
Venue: Proceedings of the 17th conference on Winter simulation (1985)

The paper sets up a conceptual framework for constructing knowledge-based, computer-aided environments for system design. The framework is based on the formal structures underlying the expert system design methodology being developed by Zeigler [18], namely that of the system entity structure and experimental frame. The system entity formalism is employed to structure the family of design configurations. The rules for design model synthesis are generated by pruning the design entity structure with respect to generic experimental frames [13] that represent the design objectives. This leads to a methodology for design of system design environments which recognizes three primary relationships of the application domain that must be modelled: the decomposition hierarchy (of the system being designed), the taxonomic structure (determining the design alternatives), and the coupling constraints (restricting the combinations in which components can be synthesized into the target system).
Engineering Software Design Processes to Guide Process Execution
Authors: Xiping Song, Leon J. Osterweil
Venue: IEEE Transactions on Software Engineering (1998)

Abstractt¿Using systematic development processes is an important characteristic of any mature engineering discipline. In current software practice, Software Design Methodologies (SDMs) are intended to be used to help design software more systematically. This paper shows, however, that one well-known example of such an SDM, Booch Object-Oriented Design (BOOD), as described in the literature is too imprecise and incomplete to be considered as a fully systematic process for specific projects. To provide more effective and appropriate guidance and control in software design processes, we applied the process programming concept to the design process. Given two different sets of plausible design process requirements, we elaborated two more detailed and precise design processes that are responsive to these requirements. We have also implemented, experimented with, and evaluated a prototype (called Debus-Booch) that supports the execution of these detailed processes.