ppxscal/embedding_network huggingface dataset:
Estimating system availability and reliability
Authors: A. Goyla
Venue: Proceedings of the 21st conference on Winter simulation (1989)

This paper deals with methods for constructing and solving large Markov chain models of computer system availability and reliability. A set of powerful high level modeling constructs is discussed that can be used to represent the failure and repair behavior of the components that comprise a system, including important component interactions. If time independent failure and repair rates are assumed then a time homogeneous continuous time Markov chain can be constructed automatically from the modeling constructs used to describe the system. Since, the size of Markov chains grows exponentially with the number of components modeled, simulation appears to be a practical way for solving models of large systems. However, the standard simulation takes very long simulation runs to estimate availability and reliability measures because the system failure event is a rare event. Therefore, variance reduction techniques which can aid in computing rare-event probabilities quickly are of interest. Specifically, the Importance Sampling technique has been found to be most useful. The modeling language and the simulation methods discussed in this paper have been implemented in a program package called the System Availability Estimator (SAVE).
More iteration space tiling
Authors: M. Wolfe
Venue: Proceedings of the 1989 ACM/IEEE conference on Supercomputing (1989)

Subdividing the iteration space of a loop into blocks or tiles with a fixed maximum size has several advantages. Tiles become a natural candidate as the unit of work for parallel task scheduling. Synchronization between processors can be done between tiles, reducing synchronization frequency (at some loss of potential parallelism). The shape and size of a tile can be optimized to take advantage of memory locality for memory hierarchy utilization. Vectorization and register locality naturally fits into the optimization within a tile, while parallelization and cache locality fits into optimization between tiles.
Worst-case delay estimation of transistor groups
Authors: S. Gaiotti, M. R. Dagenais, N. C. Rumin
Venue: Proceedings of the 26th ACM/IEEE Design Automation Conference (1989)

This paper presents two algorithms for performing worst-case delay estimation using transistor-level timing simulation techniques. The first algorithm, Dynamic Path Selection (DPS), determines in linear time the slowest paths in series-parallel transistor groups; the exponential complexity remains for transistor groups with bridges. The second algorithm, Delay Subnetwork Enumeration (DSE), complements the DPS method by taking into account logic dependencies within transistor groups. The two methods are combined in the static timing analyzer TAMIA, to provide accurate worst-case delay estimation of digital CMOS circuits.
IOBENCH: a system independent IO benchmark
Authors: B. Wolman, T. M. Olson
Venue: ACM SIGARCH Computer Architecture News (1989)

IOBENCH is an operating system and processor independent synthetic input/output (IO) benchmark designed to put a configurable IO and processor (CP) load on the system under test. It is meant to stress the system under test in a manner consistent with the way in which Oracle, Ingres, Prime INFORMATION or other data management products do IO. The IO and CP load is generated by background processes doing as many "transactions" as they can on a specified set of files during a specified time interval. By appropriately choosing and varying the benchmark parameters, IOBENCH can be configured to approximate the IO access patterns of real applications. IOBENCH can be used to compare different hardware platforms, different implementations of the operating system, different disk buffering mechanisms, and so forth. IOBENCH has proven to be a very good indicator of system IO performance. Use of IOBENCH has enabled us to pinpoint operating system bugs and bottlenecks.IOBENCH currently runs on PRIMOS and a number of UNIX systems; this paper discusses the UNIX versions. IOBENCH can be ported to a new platform in a few days. Prime proposes that IOBENCH and a standard spectrum of runs be adopted as an industry standard for measuring IO performance. Sources and documentation for IOBENCH will be made available free of charge.
A calculus of higher order communicating systems
Authors: B. Thomsen
Venue: Proceedings of the 16th ACM SIGPLAN-SIGACT symposium on Principles of programming languages (1989)

In this paper we present A Calculus of Higher Order Communicating Systems. This calculus considers sending and receiving processes to be as fundamental as nondeterminism and parallel composition. The calculus is an extension of CCS [Mil80] in the sense that all the constructions of CCS are included or may be derived from more fundamental constructs and most of the mathematical framework of CCS carries over almost unchanged. Clearly CCS with processes as first class objects is a powerful metalanguage and we show that it is possible to simulate the untyped &lgr;-calculus in CHOCS. The relationship between CHOCS and the untyped &lgr;-calculus is further strengthened by a result showing that the recursion operator is unnecessary in the sense that recursion can be simulated by means of process passing and communication. As pointed out by R. Milner in [Mil80], CCS has its limitations when one wants to describe unboundedly expanding systems as e.g. an unbounded number of procedure invocations in an imperative concurrent programming language. We show how neatly CHOCS may describe both call by value and call by reference parameter mechanisms for the toy language of chapter 6 in [Mil80].
Pseudo-natural algorithms for finitely generated presentations of monoids and groups
Authors: Klaus Madlener, Friedrich Otto
Venue: Journal of Symbolic Computation (1988)

Let G be a finitely generated group such that the word problem for G is E"n-decidable for some n>=1. Then there exists a finitely generated context-sensitive presentation of G such that the word problem for this presentation can be solved by a pseudo-natural algorithm in the class E"n. This result cannot be strengthened to always yield a context-free presentation. However, it can be extended to hold for finitely generated monoids as well.
The performance potential of multiple functional unit processors
Authors: A. R. Pleszkun, G. S. Sohi
Venue: ACM SIGARCH Computer Architecture News (1988)

In this paper, we look at the interaction of pipelining and multiple functional units in single processor machines. When implementing a high performance machine, a number of hardware techniques maybe used to improve the performance of the final system. Our goal is to gain an understanding of how each of these techniques contribute to performance improvement. As a basis for our studies we use a CRAY-like processor model and the issue rate (instructions per clock cycle) as the performance measure. We then systematically augment this base, non-pipelined, machine with more and more hardware features and evaluate the performance impact of each feature. We find, for example, that in non-vector machines, pipelining multiple function units does not provide significant performance improvements. Dataflow limits are then derived for our benchmark programs to determine the performance potential of each benchmark. In addition, other limits are computed which apply more realistic constraints on a computation. Based on these more realistic limits, we determine it is worthwhile to investigate the performance improvements that can be achieved from issuing multiple instructions each clock cycle. Several hardware approaches are evaluated for issuing multiple instructions each clock cycle.
The convex C240 architecture
Authors: M. Chastain, G. Gostin, J. Mankovich, S. Wallach
Venue: Proceedings of the 1988 ACM/IEEE conference on Supercomputing (1988)

The C240, a tightly coupled, shared memory, parallel/multi-processor, supports up to 4, 40-nanosecond ECL/CMOS Cray-like processors. Managed by a fully semaphored UNIX operating the C240, it can support up to 4 gigabytes of directly addressable physical memory. CONVEX proprietary compiler technology provides automatic vectorization and parallelization for FORTRAN, C, and ADA. Allocation of parallel threads to physical processors is managed by an innovation approach ASAP (Automatic Self-Allocating Processors). ASAP dynamically allocates and deallocates parallel threads to the processors. In creating a second generation supercomputer, several factors were considered prior to commencing design. Among these factors are: Performance - Scalar/Vector/Parallel. Parallel processing efficiency. Semiconductor technology. Compiler optimization strategies. With these factors in mind, the C240 system evolved. The salient features of the C240 are: Tightly coupled, MIMD processor system. Where each processor, up to 4, is a general purpose scientific processor, with a 4 gigabyte virtual address space. Operands are addressed at the byte level. Each processor is a 40 nanosecond, ECL/CMOS implementation of the CONVEX C1, Cray-like, instruction set architecture (see WALLACH 85). Additional instructions were added, in a super-set manner using pre-existing spare opcodes. These instructions provide vector conversions, vector shifts, vector square root, and fully pipelined operations under mask. Additional scalar instructions were added mainly in the area of intrinsics: Sin, Cos, etc. A set of parallel processing instructions was also added and will be discussed in more detail later. A very high bandwidth, 800 Mbytes/sec, multiported memory system capable of supporting up to 4 gigabytes of directly addressable physical memory. Revisions of CONVEX's proprietary compiler technology that support automatic parallelism for Fortran, C and ADA. A fully semaphored UNIX kernel. The UNIX kernel was modified extensively to support multiple simultaneous system calls to different resources and the management of CONVEX's parallel processing paradigm. Lastly, a new and innovative concept for the allocation and scheduling of parallel processes and threads is supported. This unique concept, ASAP, (Automatic Self-Allocating Processors), is a distributed mechanism that permits physical processors to dynamically associate and disassociate themselves from an executing process.
A yellow-pages service for a local-area network
Authors: L. L. Peterson
Venue: ACM SIGCOMM Computer Communication Review (1987)

We introduce a yellow-pages service that maps service names into server addresses. The service is novel in that it associates a set of attributes with each server. Clients specify the attributes the server should possess when requesting a service and the yellow-pages service determines what servers satisfy the request. In addition to describing the implementation of the yellow-pages service within a local-area network, we show how the service can be integrated with the available internet communication protocols to enable clients from throughout the internet to access local servers.
A microprogramming support tool for pipelined architectures
Authors: S. Molnar, M. C. Surles
Venue: Proceedings of the 21st annual workshop on Microprogramming and microarchitecture (1988)

We describe a software tool to aid the development of microcode for horizontal, pipelined architectures. The tool is a preprocessor for microcode source that allows the programmer full flexibility to optimize code, but removes many of the tedious and error-prone aspects of microprogramming. It automatically allocates floating-point registers, expands complex instructions, and analyzes code for pipeline-related errors. We have written a working version of the tool for the Weitek XL-8032 floating-point chip set, a horizontal architecture with pipelined sequencer and floating-point datapaths. Although the tool was designed for the XL architecture, the algorithms used are applicable to other parallel/pipelined architectures. This paper argues for the existence of such tools, summarizes the algorithms needed to analyze control and data flow in the presence of pipelining, and characterizes the tool's performance based on nine microcoded routines written for a real-time 3-D graphics system.
Protein structure prediction by a data-level parallel algorithm
Authors: X. Zhang, D. Waltz, J. P. Mesirov
Venue: Proceedings of the 1989 ACM/IEEE conference on Supercomputing (1989)

We have developed a software system, PHI-PSI, on the Connection Machine that uses a parallel algorithm to retrieve and use information from a database of 112 known protein structures (selected from the Brookhaven Protein Databank) to predict the structures of other proteins. The &phgr; and &psgr; angles of each amino acid (the angles each amino acid forms with its immediate neighbors) in a protein are used to represent its 3-D structure. PHI-PSI's algorithm is based on the idea of Memory-based reasoning (MBR) [10] and extends it to include a recursive procedure to refine its initial prediction and a &ldquo;window&rdquo; of varying sizes to look at different contexts of an input. PHI-PSI has been tested with all the available data. Initial results show that it performs better than distribution-based guesses for most of the &phgr; and &psgr; angle values.
New challenges of systems development: a vision of the 90's
Authors: Kalle Lyytinen
Venue: ACM SIGMIS Database (1989)

During the 90's substantial changes will occur in systems development. Its design objects such as technological base, content and nature of information processes, and the organizational environment of information systems will undergo a rapid change. Its context including user populations, development tools, methods, and governing organizational form will become more complex and varied. Finally, its process features such as the espoused phase model and preferred organizational strategy will undergo a drastic change. All these changes point out that systems development will be radically different in the 90's and this will challenge the accepted wisdom of systems development. New methods and approaches must be developed, theoretical foundations established, organizational forms adopted, and system development skills will become more varied, dispersed and scarce.
Strong normalizability for the combined system of the typed lmbda calculus and an arbitrary convergent term rewrite system
Authors: M. Okada
Venue: Proceedings of the ACM-SIGSAM 1989 international symposium on Symbolic and algebraic computation (1989)

We give a proof of strong normalizability of the typed &lgr;-calculus extended by an arbitrary convergent term rewriting system, which provides the affirmative answer to the open problem proposed in Breazu-Tannen [1]. Klop [6] showed that a combined system of the untyped &lgr;-calculus and convergent term rewriting system is not Church-Rosser in general, though both are Church-Rosser. It is well-known that the typed &lgr;-calculus is convergent (Church-Rosser and terminating). Breazu-Tannen [1] showed that a combined system of the typed &lgr;-calculus and an arbitrary Church-Rosser term rewriting system is again Church-Rosser. Our strong normalization result in this paper shows that the combined system of the typed &lgr;-calculus and an arbitrary convergent term rewriting system is again convergent. Our strong normalizability proof is easily extended to the case of the second order (polymorphically) typed lambda calculus and the case in which &mgr;-reduction rule is added.
The placement optimization program: a practical solution to the disk file assignment problem
Authors: J. Wolf
Venue: ACM SIGMETRICS Performance Evaluation Review (1989)

In this paper we describe a practical mathematical formulation and solution of the so-called &ldquo;File Assignment Problem&rdquo; (FAP) for computer disks. Our FAP solution has been implemented in a PL/I program known as the Placement Optimization Program (POP). The algorithm consists of three major components &mdash; two heuristic optimization models and a queueing network model. POP has been used in validation studies to assign files to disks in two IBM MVS complexes. The resulting savings in I/O response times were 22% and 25%, respectively. Throughout the paper we shall emphasize the real-world nature of our approach to the disk FAP, which we believe sets it apart from previous attempts.
Simplifying conditional term rewriting systems: Unification, termination and confluence
Authors: Stephane Kaplan
Venue: Journal of Symbolic Computation (1987)

In the field of conditional term rewriting systems, the reduction of a given term involves recursive reduction of the premises of the rule currently applied, which leads to intractability, In this paper, we introduce simplifying systems, that allow to control this recursivity. Our approach enables the extension of several results for non-conditional rewriting to the conditional fmmework. In particular, we obtain results about the correctness of evaluation procedures, unification in conditional theories, termination and confluence, together with Knuth-Bendix theorem proving methods. Finally, the extension of such results to fully general conditional systems is discussed.
Computer animation with CINEMA
Authors: J. P. Poorte, D. A. Davis
Venue: Proceedings of the 21st conference on Winter simulation (1989)

Cinema is a general purpose animation system designed to animate models developed using the SIMAN simulation language. The Cinema package consists of two separate modules. With the first module, called CINEMA, users specify graphical images used in the animation. The second module, called CSIMAN, is used to execute a SIMAN simulation model and concurrently render the associated animation.Animation typically centers around the presentation of final modeling results. However, the simplicity of developing Cinema animations allows users to exploit animation in more phases of a simulation project. By using Cinema, contributions of animation can be found throughout the entire simulation project from initial model debugging through the presentation of the final simulation results.Recent enhancements to Cinema IV include accumulating conveyors, AGV modeling features, dynamic plots and histograms, symbol fetch from backgrounds, and an improved user interface.Cinema is available on a wide variety of platforms and operating systems. These include microcomputers under DOS and OS/2, as well as Sun, Apollo, and VAX workstations under the UNIX and VMS operating systems.
Partial Shape Recognition Using Dynamic Programming
Authors: J. W. Gorman, O. R. Mitchell, F. P. Kuhl
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1988)

A partial-shape-recognition technique utilizing local features described by Fourier descriptors is introduced. A dynamic programming formulation for shape matching is developed, and a method for comparison of match quality is discussed. This technique is shown to recognize unknown contours that may be occluded or that may overlap other objects. Precise scale information is not required, and the unknown objects may appear at any orientation with respect to the camera. The segment-matching dynamic programming method is contrasted with other sequence-comparison techniques that utilize dynamic programming. Experimental results are discussed that indicate that partial contours can be recognized with reasonable accuracy.
Numerical experience with sequential quadratic programming algorithms for equality constrained nonlinear programming
Authors: David F. Shanno, Kang Hoh Phua
Venue: ACM Transactions on Mathematical Software (TOMS) (1989)

Computational experience is given for a sequential quadratic programming algorithm when LaGrange multiplier estimates, Hessian approximations, and merit functions are varied to test for computational efficiency. Indications of areas for further research are given.
A two-view approach to constructing user interfaces
Authors: Gideon Avrahami, Kenneth P. Brooks, Marc H. Brown
Venue: Proceedings of the 16th annual conference on Computer graphics and interactive techniques (1989)

This paper describes a system for constructing graphical user interfaces following a two-view paradigm: one view contains a textual representation of the interface in a special-purpose, "little" language, and the other view contains a direct manipulation, interactive editor for the user interface. The user interface can be edited in either view, and the changes are reflected in the other view. The language allows dialog boxes to be expressed in a simple and natural way, and has a well-defined mapping into the interactive editor. A base set of interactors is currently available, but the system can be easily extended with more interactors. We believe this approach to building user interfaces combines the advantages of the direct manipulation, WYSIWYG approach with the advantages of the textual, descriptive approach, and does not suffer from the limitations of either approach.
The standards factor
Authors: P. Billingsley
Venue: ACM SIGCHI Bulletin (1989)

As the newly-appointed SIGCHI Standards Liaison, I hope to continue in the fine tradition established by Jon Meads over the past several years. As I see it, my primary task is to inform SIGCHI members about any standards activities that may affect them as designers and users of interactive software. I also hope to stimulate discussion and debate about the direction of various standards efforts, and to provide a forum for others to express their opinions. I will consider the column a great success if it encourages more people with a genuine interest in end user concerns to participate in the standards-making process.
QCD with dynamical fermions on the connection machine
Authors: C. F. Bailie, R. G. Brickner, R. Gupta, L. Johnsson
Venue: Proceedings of the 1989 ACM/IEEE conference on Supercomputing (1989)

We have implemented Quantum Chromo-Dynamics (QCD) on the massively parallel Connection Machine in *Lisp. The code uses dynamical Wilson fermions and the Hybrid Monte Carlo Algorithm (HMCA) to update the lattice. We describe our program and give performance measurements for it. With no tuning or optimization, the code runs at approximately 500 to 1000 MFLOPS on a 64-K Connection Machine, model CM-2, depending on the VP ratio.
Combinatorial analysis of ramified patterns and computer imagery of trees
Authors: X. Viennot, G. Eyrolles, N. Janey, D. Arqués
Venue: Proceedings of the 16th annual conference on Computer graphics and interactive techniques (1989)

Herein is presented a new procedural method for generating images of trees. Many other algorithms have already been proposed in the last few years focusing on particle systems, fractals, graftals and L-systems or realistic botanical models. Usually the final visual aspect of the tree depends on the development process leading to this form. Our approach differs from all the previous ones. We begin by defining a certain "measure" of the form of a tree or a branching pattern. This is done by introducing the new concept of ramification matrix of a tree. Then we give an algorithm for generating a random tree having as ramification matrix a given arbitrary stochastic triangular matrix. The geometry of the tree is defined from the combinatorial parameters implied in the analysis of the forms of trees. We obtain a method with powerful control of the final form, simple enough to produce quick designs of trees without loosing in the variety and rendering of the images. We also introduce a new rapid drawing of the leaves. The underlying combinatorics constitute a refinment of some work introduced in hydrogeology in the morphological study of river networks. The concept of ramification matrix has been used very recently in physics in the study of fractal ramified patterns.