ppxscal/embedding_network huggingface dataset:
Pipelining and Bypassing in a VLIW Processor
Authors: A. Abnous, N. Bagherzadeh
Venue: IEEE Transactions on Parallel and Distributed Systems (1994)

This short note describes issues involved in the bypassing mechanism for a very longinstruction word (VLIW) processor and its relation to the pipeline structure of theprocessor. The authors first describe the pipeline structure of their processor and analyzeits performance and compare it to typical RISC-style pipeline structures given the contextof a processor with multiple functional units. Next they study the performance effects ofvarious bypassing schemes in terms of their effectiveness in resolving pipeline data hazards and their effect on the processor cycle time.
The Effect of Buffering on the Performance of R-Trees
Authors: Scott T. Leutenegger, Mario A. López
Venue: IEEE Transactions on Knowledge and Data Engineering (2000)

Past R-tree studies have focused on the number of nodes visited as a metric of query performance. Since database systems usually include a buffering mechanism, we propose that the number of disk accesses is a more realistic measure of performance. We develop a buffer model to analyze the number of disk accesses required for spatial queries using R-trees. The model can be used to evaluate the quality of R-tree update operations, such as various node splitting and tree restructuring policies, as measured by query performance on the resulting tree. We use our model to study the performance of three well-known R-tree loading algorithms. We show that ignoring buffer behavior and using number of nodes accessed as a performance metric can lead to incorrect conclusions, not only quantitatively, but also qualitatively. In addition, we consider the problem of how many levels of the R-tree should be pinned in the buffer.
Let's Stop the Bipolar Drift
Venue: IEEE Software (1990)

No abstract available
DFT Expert: Designing Testable VLSI Circuits
Authors: Sudipta Bhawmik, P. Palchaudhuri
Venue: IEEE Design Test (1989)

A set of expert-system modules for designing easily testable VLSI circuits called DFT Expert is described. DFT Expert operates at the register-transfer level of circuit description, classifying circuit components into data transporters (DTs) and data processors (DPs). It identifies DPs and DTs, selects a test method, configures global design for test (DFT), and generates test schedules. DFT Expert's ability to test a practical circuit is demonstrated.
Virtual Simulation of Distributed IP-Based Designs
Authors: Marcello Dalpasso, Alessandro Bogliolo, Luca Benini
Venue: IEEE Design Test (2002)

JavaCAD, an Internet-based tool with a secure client-server architecture, lets designers perform functional simulation, fault simulation, and cost estimation of circuits containing IP components. It also ensures IP protection for both IP vendors and users, and provides seamless transition between IP evaluation and purchase.
Visualization Techniques for Mining Large Databases: A Comparison
Authors: Daniel A. Keim, Hans-Peter Kriegel
Venue: IEEE Transactions on Knowledge and Data Engineering (1996)

Visual data mining techniques have proven to be of high value in exploratory data analysis, and they also have a high potential for mining large databases. In this article, we describe and evaluate a new visualization-based approach to mining large databases. The basic idea of our visual data mining techniques is to represent as many data items as possible on the screen at the same time by mapping each data value to a pixel of the screen and arranging the pixels adequately. The major goal of this article is to evaluate our visual data mining techniques and to compare them to other well-known visualization techniques for multidimensional data: the parallel coordinate and stick figure visualization techniques. For the evaluation of visual data mining techniques, in the first place the perception of properties of the data counts, and only in the second place the CPU time and the number of secondary storage accesses are important. In addition to testing the visualization techniques using real data, we developed a testing environment for database visualizations similar to the benchmark approach used for comparing the performance of database systems. The testing environment allows the generation of test data sets with predefined data characteristics which are important for comparing the perceptual abilities of visual data mining techniques.
Automatic Partitioning of Parallel Loops and Data Arrays for Distributed Shared-Memory Multiprocessors
Authors: Anant Agarwal, David A. Kranz, Venkat Natarajan
Venue: IEEE Transactions on Parallel and Distributed Systems (1995)

This paper presents a theoretical framework for automatically partitioning parallel loops to minimize cache coherency traffic on shared-memory multiprocessors. While several previous papers have looked at hyperplane partitioning of iteration spaces to reduce communication traffic, the problem of deriving the optimal tiling parameters for minimal communication in loops with general affine index expressions has remained open. Our paper solves this open problem by presenting a method for deriving an optimal hyperparallelepiped tiling of iteration spaces for minimal communication in multiprocessors with caches. We show that the same theoretical framework can also be used to determine optimal tiling parameters for both data and loop partitioning in distributed memory multicomputers. Our framework uses matrices to represent iteration and data space mappings and the notion of uniformly intersecting references to capture temporal locality in array references. We introduce the notion of data footprints to estimate the communication traffic between processors and use linear algebraic methods and lattice theory to compute precisely the size of data footprints. We have implemented this framework in a compiler for Alewife, a distributed shared-memory multiprocessor.
Conflict Resolution and Fault-Free Path Selection in Multicast-Connected Cube-Based Networks
Authors: A. A. Abonamah, F. N. Sibai, N. K. Sharma
Venue: IEEE Transactions on Computers (1994)

Presents an algorithm that solves the conflict resolution problem in fault-tolerant multicast-connected MINs. Without loss of generality, the authors apply the algorithm to reconfigure a four-path cube-based network. An intensive simulation study is conducted to reveal the performance improvement gained by the conflict resolution and fault-free path selection algorithm on the network under study. The simulation results indicate that the probability of failure to provide multicast connections using two paths is comparable to that of using three and four paths under various fault scenarios. The results also indicate that an effective reconfiguration algorithm based on two alternate paths has a great impact on the network performance in the presence of faults and conflicts.
Luminescence properties of II-VI quantum hall systems at high magnetic fields
Authors: Y. Imanaka, T. Takamasu, G. Kido, G. Karczewski, T. Wojtowicz, J. Kossut
Venue: Microelectronic Engineering (2002)

The evolution of photoluminescence spectra with varying Mn concentration was investigated in CdMnTe-CdMgTe single quantum well at steady high magnetic fields up to 35 T. The symmetrical variation of the luminescence intensity was observed around ν = 1 in CdTe-CdMgTe quantum well, and a satellite PL peak appeared at the higher energy side of main peak around ν = 1 in CdMnTe-CdMgTe quantum well only at low temperatures. The observed anomalies at the filling factor ν = 1 show the singularity related to the many body effect in quantum Hall systems.
Effective Scale: A Natural Unit for Measuring Scale-Space Lifetime
Authors: T. Lindberg
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1993)

A manner in which a notion of effective scale can be introduced in a formal way is developed. For continuous signals, a scaling argument directly gives a natural unit for measuring scale-space lifetime in terms of the logarithm of the ordinary scale parameter. That approach is, however, not appropriate for discrete signals since an infinite lifetime would be assigned to structures existing in the original signal. It is shown how such an effective scale parameter can be defined to give consistent results for both discrete and continuous signals. The treatment is based on the assumption that the probability that a local extremum disappears during a short-scale interval should not vary with scale. As a tool for the analysis, estimates are given of how the density of local extrema can be expected to vary with scale in the scale-space representation of different random noise signals both in the continuous and discrete cases.
Object Design: Roles, Responsibilities, and Collaborations
Authors: Rebecca Wirfs-Brock, Alan McKean
Venue:  (2002)

:If you create software using object-oriented languages and tools, then Responsibility-Driven Design has likely influenced your work. For over ten years Responsibility-Driven Design methodology has been the standard bearer of the behavioral approach to designing object-oriented software. Object Design: Roles, Responsibilities, and Collaborations focuses on the practice of designing objects as integral members of a community where each object has specific roles and responsibilities. The authors present the latest practices and techniques of Responsibility-Driven Design and show how you can apply them as you develop modern object-based applications.Working within this conceptual framework, Rebecca Wirfs-Brock and Alan McKean present how user requirements, system architecture, and design patterns all contribute to the design of an effective object model. They introduce a rich vocabulary that designers can use to discuss aspects of their designs, discuss design trade-offs, and offer practical guidelines for enhancing the reliability and flexibility of applications. In addition, case studies and real-world examples demonstrate how the principles and techniques of Responsibility-Driven Design apply to real-world software designs.You'll find coverage of such topics as: Strategies for selecting and rejecting candidate objects in an emerging design model Object role stereotypes and how to identify objects' behaviors How to characterize objects using role stereotypes Allocating responsibilities to appropriate objects Developing a collaboration model Strategies for designing application controlcenters Documenting and describing a design, focusing on use cases, design conversations, and annotations Strategies for enhancing reliability, including handling exceptions and recovering from errors How to characterize software variations and design to support them for greater flexibility How to categorize and treat various kinds of design problemsAs all experienced designers know, software design is part art and inspiration and part consistent effort and solid technique. Object Design: Roles, Responsibilities, and Collaborations will help all software designersfrom students to seasoned professionalsdevelop both the concrete reasoning skills and the design expertise necessary to produce responsible software designs.
Flexible synchronization of shared groupware objects
Authors: Stephan Lukosch, Claus Unger
Venue: ACM SIGGROUP Bulletin (1999)

In this paper we describe an object manager, that has been developed for simplifying groupware development. The object manager offers a variety of services for controlling an application's shared data, including flexible object distribution, flexible coupling of user interface and shared data, latecomer support and configurable concurrency control. After a brief description of the object manager in total, we focus on a configurable concurrency control scheme. An example and directions for future work conclude the paper.
Cosmological lower bound on the circuit complexity of a small problem in logic
Authors: Larry Stockmeyer, Albert R. Meyer
Venue: Journal of the ACM (JACM) (2002)

An exponential lower bound on the circuit complexity of deciding the weak monadic second-order theory of one successor (WS1S) is proved. Circuits are built from binary operations, or 2-input gates, which compute arbitrary Boolean functions. In particular, to decide the truth of logical formulas of length at most 610 in this second-order language requires a circuit containing at least 10125 gates. So even if each gate were the size of a proton, the circuit would not fit in the known universe. This result and its proof, due to both authors, originally appeared in 1974 in the Ph.D. thesis of the first author. In this article, the proof is given, the result is put in historical perspective, and the result is extended to probabilistic circuits.&ast;
Generating Reliable Embedded Processors
Authors: Matthias Pflanz, Heinrich Theodor Vierhaus
Venue: IEEE Micro (1998)

A new approach to enhance the reliability of embedded processor-based systems is presented. It was developed for applications with high-reliability demands under heavy cost-constraints. The concept is a minimized duplication of processor macro-components in programmable logic devices in accordance with the application of the embedded system. This concept is described in detail with the design flow of the processor control structure as an example. We show that the hardware overhead and the costs of classical fault-tolerant techniques like triple-modular redundant (TMR) component implementation can be reduced significantly. Furthermore, we show the possibilities and limitations of programmable logic devices used in this approach.
Integrity Constraints in the Information Source Tracking Method
Authors: Fereidoon Sadri
Venue: IEEE Transactions on Knowledge and Data Engineering (1995)

In this paper we study the issue of integrity constraints in the Information Source Tracking (IST) method. The IST method is an approach to the management of uncertain data in database systems. The main idea behind IST is that database information is supplied, or confirmed, by information sources. The accuracy of data is modeled by the reliability of the contributing information sources.In practice, information sources that are generally quite reliable may supply conflicting data at times. A database system based on IST must accept such data, and be capable of functioning correctly despite the inconsistency. We concentrate on cases where conflicting data is in violation of ¿key constraints, a special form of functional dependencies resulting from the imposition of a key for each relation in the database. We present an approach, based on the adjustment of conflicting information source reliabilities, to handle data in violation of key constraints.
The Adaptive-Hash Join Algorithm for a Hypercube Multicomputer
Authors: E. Omiecinski, E. T. Lin
Venue: IEEE Transactions on Parallel and Distributed Systems (1992)

The cube adaptive-hash join algorithm, which combines the merits of nested-loop and hybrid-hash, is presented. The performance of these algorithms is compared through analytical cost modeling. The nonuniform data value distribution of the inner relation is shown to have a greater impact than that of the outer relation. The cube adaptive-hash algorithm outperforms the cube hybrid-hash algorithm when bucket overflow occurs. In the worst case, this algorithm converges to the cube nested-loop-hash algorithm. When there is no hash table overflow, the cube adaptive-hash algorithm converges to the cube hybrid-hash algorithm. Since the cube adaptive-hash algorithm adapts itself depending on the characteristics of the relations, it is relatively immune to the data distribution.
Feature Extraction Based on Decision Boundaries
Authors: C. Lee, D. A. Landgrebe
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1993)

A novel approach to feature extraction for classification based directly on the decision boundaries is proposed. It is shown how discriminantly redundant features and discriminantly informative features are related to decision boundaries. A procedure to extract discriminantly informative features based on a decision boundary is proposed. The proposed feature extraction algorithm has several desirable properties: (1) it predicts the minimum number of features necessary to achieve the same classification accuracy as in the original space for a given pattern recognition problem; and (2) it finds the necessary feature vectors. The proposed algorithm does not deteriorate under the circumstances of equal class means or equal class covariances as some previous algorithms do. Experiments show that the performance of the proposed algorithm compares favorably with those of previous algorithms.
A Hierarchical 3-D Poisson Modified Fourier Solver by Domain Decomposition
Authors: Moshe Israeli, Elena Braverman, Amir Averbuch
Venue: Journal of Scientific Computing (2002)

We present a Domain Decomposition non-iterative solver for the Poisson equation in a 3-D rectangular box. The solution domain is divided into mostly parallelepiped subdomains. In each subdomain a particular solution of the non-homogeneous equation is first computed by a fast spectral method. This method is based on the application of the discrete Fourier transform accompanied by a subtraction technique. For high accuracy the subdomain boundary conditions must be compatible with the specified inhomogeneous right hand side at the edges of all the interfaces. In the following steps the partial solutions are hierarchically matched. At each step pairs of adjacent subdomains are merged into larger units. In this paper we present the matching algorithm for two boxes which is a basis of the domain decomposition scheme. The hierarchical approach is convenient for parallelization and minimizes the global communication. The algorithm requires O(N3&emsp14;log&emsp14;N) operations, where N is the number of grid points in each direction.
Innovation and Obstacles: The Future of Computing
Authors: David D. Clark, Edward A. Feigenbaum, Juris Hartmanis, Robert W. Lucky, Robert M. Metcalfe, Raj Reddy, Mary Shaw
Venue: Computer (1998)

In this multidisciplinary glimpse forward, some of this decade's key players offer opinions on a range of topics- from what has driven progress, to where innovation will come from and to obstacles we have yet to overcome. In this excerpt from "Visions for the Future of the Fields," a panel discussion held at the 10th anniversary of the US Computer Science and Telecommunications Board, experts identify critical issues for various aspects of computing. In the accompanying sidebars, some of the same experts elaborate on points in the panel discussion in mini-essays: David Clark, CSTB chairman, looks at the changes needed, as computing science research comes of age. The current context of computer science, Clark states, is shaped by past successes and chronic trouble spots. Mary Shaw, Carnegie Mellon University, examines challenges for software system designers. Shaw states that disintermediation-the direct connection of users and their software-has created new problems for software system designers. Robert Lucky, Bellcore, looks at IP dial tone, a new infrastructure for the Internet. Lucky states that data traffic will soon eclipse voice traffic, portending not just a revolution in technology but in the very basis of telecommunications economics. Donald Greenberg, Cornell University, rounds out the essays with an outlook on computer graphics. Greenberg states that by 2025 we will have the technology to produce realistic real-time images at resolutions up to or beyond the limits of our visual perception.Finally, in an interview with William Wulf, president of the US National Academy of Engineering, Computer explores the roots of innovation and the broader societal aspects that will ultimately drive innovation in the near term.
Size of the Largest Antichain in a Partition Poset
Authors: V. M. Blinovsky, L. H. Harper
Venue: Problems of Information Transmission (2002)

Partitions &lcub;(k1, &hellip;, k&ell;)&rcub; of a given set are considered as a partially ordered set (poset) with a natural partial ordering with respect to inclusion. Asymptotics for the size of the largest antichain in this poset is found for &ell; fixed.
Natural Language Grammatical Inference with Recurrent Neural Networks
Authors: Steve Lawrence, C. Lee Giles, Sandiway Fong
Venue: IEEE Transactions on Knowledge and Data Engineering (2000)

This paper examines the inductive inference of a complex grammar with neural networks¿specifically, the task considered is that of training a network to classify natural language sentences as grammatical or ungrammatical, thereby exhibiting the same kind of discriminatory power provided by the Principles and Parameters linguistic framework, or Government-and-Binding theory. Neural networks are trained, without the division into learned vs. innate components assumed by Chomsky, in an attempt to produce the same judgments as native speakers on sharply grammatical/ungrammatical data. How a recurrent neural network could possess linguistic capability and the properties of various common recurrent neural network architectures are discussed. The problem exhibits training behavior which is often not present with smaller grammars and training was initially difficult. However, after implementing several techniques aimed at improving the convergence of the gradient descent backpropagation-through-time training algorithm, significant learning was possible. It was found that certain architectures are better able to learn an appropriate grammar. The operation of the networks and their training is analyzed. Finally, the extraction of rules in the form of deterministic finite state automata is investigated.
Analysis of substrate thermal gradient effects on optimal buffer insertion
Authors: Amir H. Ajami, Kaustav Banerjee, Massoud Pedram
Venue: Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design (2001)

This paper studies the effects of the substrate thermal gradients on the buffer insertion techniques. Using a non-uniform temperature-dependent distributed RC interconnect delay model, the buffer insertion problem is analyzed and design guidelines are provided to ensure the near-optimality of the signal performance in the presence of the thermal gradients. In addition, the effect of temperature-dependent driver resistance on the buffer insertion is studied. Experimental results show that neglecting thermal gradients in the substrate and the interconnect lines can result in non-optimal solutions when using standard buffer insertion techniques and that these effects intensify with technology scaling.