ppxscal/embedding_network huggingface dataset:
Switch-stacks: a scheme for microtasking nested parallel loops
Authors: Jyh-Herng Chow, Williams Ludwell Harrison,  III
Venue: Proceedings of the 1990 ACM/IEEE conference on Supercomputing (1990)

This paper discusses run-time microtasking support for executing nested parallel loops on a shared memory multiprocessor system, and presents a new scheme called switch-stacks for implementing such support. We first discuss current approaches to flat microtasking, and investigate how to extend these for full microtasking. We point out the problem of dummy waiting in the processor that initiates a parallel loop. To solve this problem, two schemes, dequeue-tasks and dequeue-descendant-tasks are considered and their disadvantages are discussed. The switch-stacks scheme we proposed perfectly solves the problem. These schemes have been implemented in the PARCEL run-time system. The results show that the new scheme achieves the best performance in execution time and stability nearly always.
Application of measurement theory to software metrics: comments on the Bollmann-Zuse approach
Authors: Erhard Konrad
Venue: ACM SIGPLAN Notices (1992)

In this paper, Bollmann and Zuse's reply to a criticism of their approach to software metrics will be examined. As a result it will be shown that they have failed to achieve their goal of refuting this criticism.
Performance Analysis of Multistage Interconnection Network Configurations and Operations
Authors: Chuan-lin Wu, Manjai Lee
Venue: IEEE Transactions on Computers (1992)

A performance evaluation using both analytical and simulation models, of circuit-switching multistage interconnection networks in aspects of configurations and operations is presented. Two configurations of the networks, single and dual, are evaluated. Network operations considered include conflict resolution strategies and communication strategies. Two different conflict resolution strategies, drop and hold, are analyzed. New analyses using Markov chains, are given, and are verified by simulation results. In the single-network configuration, it is shown that the drop strategy is better than the hold strategy for randomly distributed traffic. In the dual network configuration, five different communication strategies are investigated, and the optimum performance level is shown to be dependent on the length of the data transfer time.
On-line navigation in a room
Authors: E. Bar-Eli, Piotr Berman, A. Fiat, Peiyuan Yan
Venue: Proceedings of the third annual ACM-SIAM symposium on Discrete algorithms (1992)

We consider the problem of navigating through an unknown environment in which the obstacles are disjoint oriented rectangles enclosed in an n x n square room. The task of navigating algorithm is to reach the center of the room starting from one of the corners. While there always exists a path of length n, the best previously known navigating algorithm finds paths of length n201nn . We give an efficient deterministic algorithm which finds a path of length O(n ln n); this algorithm uses tactile information only. Moreover, we prove that any deterministic algorithm can be forced to traverse a distance of &OHgr;(n ln n), even if it uses visual information.
Noised or filtered programming? (about enumerated types)
Authors: Michel Gauthier
Venue: ACM SIGPLAN Notices (1992)

This paper is yet another contribution to a debate where many people contributed recently [Delft 89, Meek 90, Sakkinen 91, and others...], the ones pleading for considering enumerated types as harmful, and the others as important. But the debate will probably be more useful if levels --- layers --- of programming are taken into account. The good answer has no reason to be the same in real life and at machine level. From my point of view, programming includes an untyping process from the former to the latter. I claim here that enumerated types do give right answers to very real questions in programming, but that they would be yet more useful if they were restricted enough to become closer to real life, as it can be done with Ada private types.
Fast causal multicast
Authors: Pat Stephenson, Kenneth Birman
Venue: ACM SIGOPS Operating Systems Review (1991)

We begin by outlining a new protocol that efficiently implements a reliable, causally ordered multicast primitive and is easily extended into a totally ordered one. Since measurements show that the dominant cost of this protocol is message transport, the design of a lower level multicast transport protocol is discussed. The overall scheme scales with bounded overhead. Our first conclusion is that systems such as Isis can achieve performance competitive with the best existing multicast facilities - a finding contradicting the widespread concern that fault-tolerance may be unacceptably costly. Our second conclusion is that the paradigm of multicast transport is extremely useful for constructing fault-tolerant applications. Our final conclusion is that the framework for fault-tolerant programming provided by Isis is very useful in the design and construction of these extensions to the basic system.
Prefetch unit for vector operations on scalar computers
Authors: Ivan Sklenář
Venue: ACM SIGARCH Computer Architecture News (1992)

Current caches are not adequate for vector operations. A new kind of support for vector operations, called prefetch unit, is designed to improve the performance of the scalar (SISD) processors. The prefetch unit can be used for any SISD architecture and also for many kinds of MIMD architectures. It may run in parallel and asynchronously with other parts of processor. It keeps trace of the history of memory references, and therefore initializes rarely any superfluous prefetches.
A modification support system&mdash;automatic correction of side&mdash;effects caused by type modifications
Authors: T. Tenma, Y. Sato, Y. Morimoto, M. Tanaka, T. Ichikawa
Venue: Proceedings of the 1990 ACM annual conference on Cooperation (1990)

Programmers modify software for many reasons. When a part of a software is modified, side-effects of the modification are propagated to other parts of the software. By correcting these side-effects automatically, the productivity and the reliability of software development increases. This paper proposes an approach based on constraints and component-based software representation for detecting and correcting side-effects. A system based on the approach for type modifications is presented. The system is developed independent of a particular language.
Scientific workload characterization by loop-based analyses
Authors: Michael W. Berry
Venue: ACM SIGMETRICS Performance Evaluation Review (1992)

A number of scientific and engineering benchmarks have emerged during the 1980's. Each of these benchmarks has a different origin, methodology and interpretation. This report presents a case study of two current scientific benchmarks and includes a comparison of them based on their instruction mixes as measured by the CRAY X-MP hardware performance monitor (hpm). This particular case study was conducted by graduate students in a Performance Evaluation course taught during Spring Quarter 1991 in the Department of Computer and Information Sciences at the University of Alabama at Birmingham.Students analyzed the dominant loops of the application-based Perfect Benchmarks and noted (where applicable) significant performance comparisons with the loop-based Livermore Fortran Kernels. Whether or not any collection of kernel or loop-based benchmarks can effectively predict the performance of more sophisticated scientific application programs is not clear. This case study does reveal, however, the types of loops which are most prevalent in codes from various scientific applications and what their impact is on the overall performance of these applications.
Perfect Benchmarks decomposition and performance on VAX multiprocessors
Authors: Zarka Cvetanovic, Edward G. Freedman, Charles Nofsinger
Venue: Proceedings of the 1990 ACM/IEEE conference on Supercomputing (1990)

This paper presents the methods for decomposition and the performance of the Perfect Benchmark suite on two VAX multiprocessors. Our results indicate that by several efficient decomposition techniques we were able to obtain significant performance gains on both VAX multiprocessors relative to a uniprocessor case. We propose a methodology that can be applied for decomposing other existing scientific and engineering applications and provide guidelines for auto-decomposing compiler improvements. Finally, we discuss and quantify the effect of different cache designs on the multiprocessor performance.
Camera Calibration with Distortion Models and Accuracy Evaluation
Authors: Juyang Weng, Paul Cohen, Marc Herniou
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1992)

A camera model that accounts for major sources of camera distortion, namely, radial, decentering, and thin prism distortions is presented. The proposed calibration procedure consists of two steps: (1) the calibration parameters are estimated using a closed-form solution based on a distribution-free camera model; and (2) the parameters estimated in the first step are improved iteratively through a nonlinear optimization, taking into account camera distortions. According to minimum variance estimation, the objective function to be minimized is the mean-square discrepancy between the observed image points and their inferred image projections computed with the estimated calibration parameters. The authors introduce a type of measure that can be used to directly evaluate the performance of calibration and compare calibrations among different systems. The validity and performance of the calibration procedure are tested with both synthetic data and real images taken by tele- and wide-angle lenses.
Performance Analysis of Transaction Driven Computer Systems Via Queueing Analysis of Polling Models
Authors: Wim P. Groenendijk, Hanoch Levy
Venue: IEEE Transactions on Computers (1992)

A class of computer systems whose primary task is the massive processing of batch transitions and which are called transaction-driven computer systems (TDCSs) is modeled and analyzed. A generic queuing model for transaction-driven computer systems is presented, and the mean sojourn time experienced by the different transactions is calculated. The approach is to model a TDCS by a cyclic polling system with bulk arrivals, deterministic service times, limited-one service, and zero switch-over periods. Since the performance analysis of this polling model has not been provided before, the emphasis is on deriving mean delay approximations for it. The analysis is carried out for models with general switch-over periods, and a special case of it (zero switch-over periods) is suitable for analyzing a TDCS.
First experiences with the SB-ONE knowledge representation workbench in natural-language applications
Authors: Alfred Kobsa
Venue: ACM SIGART Bulletin (1991)

SB-ONE is a workbench for the representation of conceptual knowledge, with the emphasis on applications in natural-language systems. Besides the SB-ONE language, the workbench comprises three different interfaces, a partition mechanism, a consistency maintenance system for the syntactic well-formedness of SB-ONE knowledge bases, a classifier, a realizer, a pattern matcher, a spreading-activation mechanism, an interpreter and classifier for SB-ONE to SB-ONE translation rules, an integration mechanism for an external frame-based representation, and a connection between SB-ONE and an extended Prolog. These components have been employed by a fairly large number of people in various natural-language applications. This paper describes the SB-ONE workbench, illustrates the motivations and philosophies behind its components, and reports some feedback received from users.
Providing paradigm orientation without implementational handcuffs
Authors: Howard E. Shrobe
Venue: ACM SIGART Bulletin (1991)

Why is it hard to implement a Knowledge Representation or Reasoning tool that people actually use?
Using Ada for rapid prototyping of database applications
Authors: Eugen Vasilescu
Venue: Proceedings of the eighth annual Washington Ada symposium summer SIGAda meeting on Ada: software: foundation for competitveness (1991)

We present an Ada-based methodology for developing database applications. When using this methodology an application programmer needs to concern himself mainly with high-level schema types and associated object declarations, while the access to the database is non-procedural, automatic, and through a small number of semantically well-defined subprogram calls. A prototype implementation of this methodology confirmed our expectations regarding the ease of use, portability and high programmer productivity.
A Novel Division Algorithm for the Residue Number System
Authors: Mi Lu, Jen-Shiun Chiang
Venue: IEEE Transactions on Computers (1992)

A novel general algorithm for signed number division in the residue number system (RNS) is presented. The parity checking technique used for sign and overflow detection in this algorithm is more efficient and practical than conventional methods. Sign magnitude arithmetic division is implemented using binary search. There is no restriction to the dividend and the divisor (except zero divisor), and no quotient estimation is necessary before the division is executed. Only simple operations are needed to accomplish this RBS division. All these characteristics have made the algorithm simple, efficient, and practical for implementation on a real RNS divider.
Performance of Synchronous and Asynchronous Schemes for VLSI Systems
Authors: Morteza Afghahi, Christer Svensson
Venue: IEEE Transactions on Computers (1992)

Continuous advances in VLSI technology have made it possible to implement a system on a chip. One consequence of this is that the system will use a homogeneous technology for interconnections, gates, and synchronizers. Another consequence is that the system size and operation speed increase, which leads to increased problems with timing and synchronization. System and delay models necessary for the study of time performances of synchronous and asynchronous systems are developed. Clock skew is recognized as a key factor for the performance of synchronous systems. A mode of clocking that reduces the clock skew substantially is proposed and examined. Time penalty introduced by synchronizers is recognized as a key factor for the performance of asynchronous systems. This parameter is expressed in terms of system parameters. Different techniques and recommendations concerning performance improvement of synchronous and asynchronous systems are discussed.
The robustness of NUMA memory management
Authors: Richard P. LaRowe,  Jr., Carla Schlatter Ellis, Laurence S. Kaplan
Venue: ACM SIGOPS Operating Systems Review (1991)

The study of operating systems level memory management policies for nonuniform memory access time (NUMA) shared memory multiprocessors is an area of active research. Previous results have suggested that the best policy choice often depends on the application under consideration, while others have reported that the best policy depends on the particular architecture. Since both observations have merit, we explore the concept of policy tuning on an application/architecture basis.We introduce a highly tunable dynamic page placement policy for NUMA multiprocessors, and address issues related to the tuning of that policy to different architectures and applications. Experimental data acquired from our DUnX operating system running on two different NUMA multiprocessors are used to evaluate the usefulness, importance, and ease of policy tuning.Our results indicate that while varying some of the parameters can have dramatic effects on performance, it is easy to select a set of default parameter settings that result in good performance for each of our test applications on both architectures. This apparent robustness of our parameterized policy raises the possibility of machine-independent memory management for NUMA-class machines.
A simple realization of a parallel device recognizing regular trace languages
Authors: Ryszard Janicki, Thomasz Muldner
Venue: Proceedings of the 1990 ACM annual conference on Cooperation (1990)

This paper studies parallel devices recognizing trace languages. We introduce a concept of an asynchronous automaton with &egr;-moves and show that for a given regularly defined trace language there exists a simple version of an asynchronous automaton with &egr;-moves recognizing this language.
Setup Algorithms for Cube-Connected Parallel Computers Using Recursive Karnaugh Maps
Authors: A. Yavuz Oruç, M. Mittal
Venue: IEEE Transactions on Computers (1991)

Optimal setup procedures for cube-connected networks are described. The setup patterns include paths, transpositions, cycles, and one-pass permutations. It is shown that for an N-input cube-connected network, the procedure for paths requires O(log/sub 2/ N) steps and O(N) space, the procedure for transportations and cycles requires O(N) steps and O(N) space, and the procedure for permutations takes O(N log/sub 2/ N) steps and O(N) space. It is also shown that the time complexities of the setup procedures for transpositions, cycles, and permutations can be improved as O(log/sub 2/ N) by using O(N) processors.
A plea for readable pleas for a readable Prolog programming style
Authors: Randy M. Kaplan
Venue: ACM SIGPLAN Notices (1991)

Writing a plea for a readable Prolog programming style is not like writing most pleas. In writing a plea for a readable Prolog programming style in particular, one could possibly bring forth many results. This means that special care must be taken when writing a plea for a readable Prolog programming style. Not only must the plea be readable, it must also be written in such a way as to make clear the process of writing well-styled Prolog programs.Plea writing makes use of a set of rules to specify how a certain task might be accomplished. In general, if these rules are written without attention to their meaning, there is no telling how the style of a particular Prolog program will be affected. It is from this aspect of plea writing both the power and danger of plea writing arise.We will attempt to discuss ways in which pleas for a readable Prolog programming style may be written so that they may be clearly understood and applied to make Prolog programs more readable. We will also give an example of the application of plea writing rules by writing a plea and then applying this plea to excerpts of Prolog code.
The spring model for knowledge-based systems analysis: a case study
Authors: Edgar A. Whitley, Angeliki Poulymenakou, Tony Cornford
Venue: ACM SIGMIS Database (1992)

This article presents the initial results of a case study undertaken to develop a knowledge-based system to support the management of information technology in small- and medium-sized businesses. It explores the prerequisites for undertaking investigations in such a context and presents a method for knowledge-based systems anlaysis that is flexible in allowing the consideration of the complex contextual factors in the domain, while providing guidance and control for the incremental development of understanding. The results of this analysis can support rigorous development and implementation activities
High Performance Software Testing on SIMD Machines
Authors: Edward W. Krauser, Aditya P. Mathur, Vernon J. Rego
Venue: IEEE Transactions on Software Engineering (1991)

A method for high-performance, software testing, called mutant unification, is described. The method is designed to support program mutation on parallel machines based on the single instruction multiple data stream (SIMD) paradigm. Several parameters that affect the performance of unification have been identified and their effect on the time to completion of a mutation test cycle and speedup has been studied. Program mutation analysis provides an effective means for determining the reliability of large software systems and a systematic method for measuring the adequacy of test data. However, it is likely that testing large software systems using mutation is computation bound and prohibitive on traditional sequential machines. Current, implementations of mutation tools are unacceptably slow and are only suitable for testing relatively small programs. The proposed unification method provides a practical alternative to the current approaches. The method also opens up a new application domain for SIMD machines.
The generation of binary trees as a numerical problem
Authors: Renzo Sprugnoli
Venue: Journal of the ACM (JACM) (1992)

The problem of generating random, uniformly distributed, binary trees is considered. A closed formula that counts the number of trees having a left subtee with k-1 nodes k=1,2,...,n is found. By inverting the formula, random trees with n nodes are generated according to the appropriate probability distribution, determining the number of nodes in the left and right subtrees that can be generated recursively. The procedure is shown to run in time On , occupying an extra space in the order of On .
Configuring a Wafer-Scale Two-Dimensional Array of Single-Bit Processors
Authors: Ahmed Boubekeur, Jean-Luc Patry, Gabrièle Saucier, Jacques Trilhe
Venue: Computer (1992)

An overview of the ELSA (European large SIMD array) project, which uses a two-level strategy to achieve defect tolerance for wafer-scale architectures implemented in silicon, is presented. The target architecture is a 2-D array of processing elements for low-level image processing. An array is divided into subarrays called chips. At the chip level, defect tolerance is proved by an extra column of PEs (processing element) and bypassing techniques. At the wafer level, a double-rail connection network is used to construct a target array of defect-free chips that is as large and as fast as possible. Its main advantage is being independent of chip defects, as it is controlled from the I/O pads. An algorithm for constructing an optimized two-dimensional array on a wafer containing a given number of defect-free PEs and connections, a method to program the switches for the target architecture found by the algorithm, and software for programming the switches using laser cuts are discussed.
Parallelization of loops with exits on pipelined architectures
Authors: P. Tirumalai, M. Lee, M. Schlansker
Venue: Proceedings of the 1990 ACM/IEEE conference on Supercomputing (1990)

Modulo scheduling theory can be applied successfully to overlap Fortran DO loops on pipelined computers issuing multiple operations per cycle both with and without special loop architectural support [1, 2, 3]. This paper shows that a broader class of loops - repeat-until, while, and loops with more than one exit - where the trip count is not known beforehand, can also be overlapped efficiently on multiple issue pipelined machines. Special features that are required in the architecture, as well as compiler representations for accelerating these loop constructs, are discussed. Performance results are presented for a few select examples. A prototype scheduler is currently under construction at HP Laboratories.
Performance analysis case study (abstract): application of experimental design statistical data analysis techniques
Authors: Robb Newman
Venue: ACM SIGMETRICS Performance Evaluation Review (1991)

A common requirement of computer vendor's competitive performance analysis departments is to measure and report on the performance characteristics of another vendor's system. In many cases the amount of prior knowledge concerning the competitor's systcm is limited to sales brochures and non-technical publications. Availability of the system for benchmarking is minimal; there is little choice concerning memory and I/O configurations; and time to complete the project is short. A project of this nature is not, however, unique to computer vendors. Many users of computer systems that want to better understand a system's performance characteristics before deciding on a purchase, are also faced with similar restrictions.