ppxscal/embedding_network huggingface dataset:
Using counter-examples in the data structures course
Authors: Alan Fekete
Venue: Proceedings of the fifth Australasian conference on Computing education - Volume 20 (2003)

In many computer science courses, students face a sequence of activities that is quite monotonous in style: most assignments and labs ask the student to write a program that does something, to follow a procedure, or else to prove something. We advocate varying the pattern by including different types of activity which bring students to reflect on their ideas and especially to confront directly common misconceptions. We use the traditional "data structures" subject as the domain in which to present this approach to teaching. We give detailed accounts of several activities that include debugging wrong code and explaining the misconception in an argument.
Family of fast mixed arithmetic logic transforms for multiple-valued input binary functions
Authors: S. Rahardja, B. J. Falkowski
Venue: Proceedings of the 26th International Symposium on Multiple-Valued Logic (1996)

A family of mixed arithmetic logic whose transform matrices possess fast algorithms is introduced. The mixed arithmetic transforms are applied to multiple-valued input binary functions. The paper describes basic properties and lists those mixed arithmetic transforms which have fast forward and easily defined inverse transforms. Finally, the advantages of mixed arithmetic logic spectra for some multiple-valued input binary functions are shown.
An Algorithm for Determining Whether the Connectivity of a Graph is at Least k
Authors: Shimon Even
Venue:  (1973)

The algorithm presented in this paper is for testing whether the connectivity of a large graph of $n$ vertices is at least $k$. First the case of undirected graphs is discussed, and then it is shown that a variation of this algorithm works for directed graphs. The number of steps the algorithm requires, in case $k > \sqrt{n}$, is bounded by $O(kn^{3})$.
Mastering Jakarta Struts, 1 edition
Authors: James Goodwill
Venue:  (2002)

:Developing Web applications with Java became considerably easier with the advent of JavaServer Pages (JSP) and servlets. Unfortunately, when used for large-scale applications, JSPs have been less successful -- they can become bloated with code, resulting in applications that are slow and inefficient. Jakarta Struts helps provide the solution to this problem. Struts handles a number of specific tasks involved in controlling how servlets, EJBs, and other components work together. It also makes use of JSP custom tags to help developers create interactive, form-based applications. James Goodwill has loaded each chapter with real-world code examples that show how to build applications using Jakarta Struts. Written for experienced Java programmers who need to learn how to use Struts to build enterprise-level applications, this book begins by examining the concepts and architecture of the Struts Framework of technologies.
An Animatable Operational Semantics of the Verilog Hardware Description Language
Authors: Jonathan P. Bowen, He Jifeng, Xu Qiwen
Venue: Proceedings of the 3rd IEEE International Conference on Formal Engineering Methods (2000)

An operational semantics of a significant subset of the Verilog Hardware Description Language (HDL) is presented. The semantics is encoded using the logic programming language Prolog in a literate programming style. This allows the associated documentation to be maintained in step with the semantics, and the printed version to be presented in a standard mathematical operational semantics style. It also enables the semantics to be directly animated using a Prolog interpreter. Using this approach allows the exploration of sometimes-subtle behaviours of parallel programs and the possibility of rapid changes or additions to the semantics of the language covered that could be missed otherwise. In addition, it provides an extra check on the validity of the operational semantics.
The Basic Business Library: Core Resources, 4 edition
Authors: Rashelle S. Karp, Bernard S. Schlessinger
Venue:  (2002)

:The fourth edition contains an updated core list of the best current business resources, as well as a collection of new essays on important topics in business librarianship. Entries in the core list provide full bibliographic information, online ordering information, brief descriptions of authority and scope, and brief evaluations of the works' strengths and weaknesses.
A Probabilistic Image Model for Smoothing and Compression
Authors: C. H. Li, P. C. Yuen, P. K. S. Tam
Venue: Proceedings of the The International Conference on Information Technology: Coding and Computing (ITCC'00) (2000)

In this paper, the problem of edge preserving smoothing in image processing is tackled by combining a noise corruption model and a region and edge image model. The derivation of the probability model for the first order difference in the gray levels of the region pixels and edge pixels lead to a non-linear filter with coefficients as functions of the estimated noise variance and edge intensity. Such a model-based approach allows the design of improved filters for noise filtering and image compression. Experimental results demonstrate the improved performance of the filter for both synthetic and natural images.
A CASE Tool Supports the Software Life Cycle of Participator Dependent Multimedia Presentations
Authors: Timothy K. Shih, Yih-Jia Tsai, Jason C. Hung, Ding-Rong Jiang
Venue: Proceedings of the IEEE International Conference on Multimedia Computing and Systems (1998)

This paper presents a CASE tool for the specification, design, implementation, testing, and maintenance of multimedia presentations. The proposed system is based on a Petri net machine to control event-based resource synchronization. Data flow diagrams and control flow diagrams are used as the specification of a multimedia presentation. The system then allows the specification to be Stepwise refined toward the final multimedia presentation.
Implementing the Real-Time Publisher/Subscriber Model on the Controller Area Network (CAN)
Authors: J. Kaiser, M. Mock
Venue: Proceedings of the 2nd IEEE International Symposium on Object-Oriented Real-Time Distributed Computing (1999)

Designing distributed real-time systems as being composed of communicating objects offers many advantages with respect to modularity and extensibility of these systems. However, distributed real-time applications exhibit communication patterns that significantly differ from the traditional object invocation style.The publisher/subscriber model for inter-object communication matches well with these patterns. Any implementation of that model must address the problems of binding subscribers to publishers, of routing and filtering of messages, as well as reliability, efficiency and latency of message delivery. In the context of real-time applications, all these issues must be subject to a rigid inspection with respect to meeting real-time requirements.We argue that for embedded control systems built around smart microcontroller-powered devices these requirements can only be met when exploiting the properties of the underlying network. The CAN-Bus (CAN: Controller Area Network) which is an emerging standard in the field of real-time embedded systems is particularly suited to implement a publisher/subscriber model of communication. In this paper, we present an implementation of the real-time publisher/subscriber model that exploits the underlying facilities of the CAN-Bus.In particular, we introduce a novel addressing scheme for publisher/subscriber communication that makes efficient use of the CAN-Bus addressing method. We provide a detailed design and implementation details along with some preliminary performance estimations.
Rate-monotonic scheduling on uniform multiprocessors
Authors: Sanjoy K. Baruah, Joël Goossens
Venue: Proceedings of the 23rd International Conference on Distributed Computing Systems (2003)

Each processor in a uniform multiprocessor ma-chine is characterized by a speed or computing capac-ity, with the interpretation that a job executing on aprocessor with speed s for t time units completes (s \times t)units of execution. The scheduling of systems of periodic tasks on uniform multiprocessor platforms usingthe rate-monotonic scheduling algorithm is considered here. A simple, sufficient test is presented fordetermining whether a given periodic task system willbe successfully scheduled by algorithm upon a particularuniform multiprocessor platform - this test generalizes earlier results concerning rate-monotonic scheduling upon identical multiprocessor platforms.
Cartographic generalisation using cooperative agents
Authors: Cécile Duchêne, Christophe Cambier
Venue: Proceedings of the second international joint conference on Autonomous agents and multiagent systems (2003)

We use a multi-agent approach to automatically perform cartographic generalisation, a task of the cartography domain that aims to simplify a digital map in order to produce another digital map with less details. Our agents are geographical objects such as houses, roads, rivers, etc. The agents interact so that each of them finds a new place and geometric representation that fits to the final map requirements. The principles of our approach are described here and some preliminary results are shown.
A Layout Automation Problem Combining Standard Cells and Marco Blocks
Authors: Jitendra Apte
Venue:  (1990)

Heuristic algorithms for automatically generating layouts of VLSI circuits containing either a set of large marco blocks or a set of electrical gates, have been studied extensively for over a decade. As a result, efficient techniques for the layout of such special netlists have been developed. Some such techniques are marco blocks, standard cells, gate arrays, programmable logic arrays and sea-of-gates. More challenging layout problems are now being sought and investigated. This work concentrates on one such VLSI layout problem. A layout problem that occurs naturally in existing design automation systems is that of automatically generating compact layouts of netlists containing a mixture of a few macro blocks and large number of standard cells. This problem, referred to as the mixed netlist layout problem, has been studied in the work described in this dissertation. The primary aim of the study was to develop new algorithms for solving the mixed netlist layout problem. Additionally, the desire to solve large instances of the problem motivated a search for algorithms that are efficient in their use of time and memory. This report describes an approach that has been evolved for solving the mixed netlist layout problem. The approach borrows some models and algorithms from existing layout design automation literature. It also introduces some new models suitable for capturing the nuances of the mixed layout problem. Based on this collection of tools, some new algorithms have been proposed. The algorithms have been shown to have a low running time complexity. The new algorithms and models have been implemented in a prototype software system called {\em montage}. The performance of the algorithms has been analyzed by scrutinizing the layouts produced by running {\em montage} on several industrial circuits. The results of the test runs have demonstrated that the approach generates compact layouts. The tests also demonstrate that the algorithms do not require exorbitant amounts of memory. In conclusion, a promising and viable new approach has been presented for solving the mixed netlist layout problem.
Indexing to Efficiently Support Fussy Queries on Range Specifications
Authors: T. Glagowski, W. DeForeest
Venue: Proceedings of the 2nd IEEE International Conference on Engineering of Complex Computer Systems (1996)

Range specifications, such as the temperature operating range of an electrical circuit component, are widely used in the process of component selection. This paper proposes n method to index such specifications in a fuzzy query database system which supports a search engine for component selection and which performs efficient and accurate queries. We discuss the rationale for range specifications, fuzzy queries, and reasons why commonly used spatial database indexing methods do not meet the requirements for queries on range specifications. We the describe a method to represent range specifications in the database and show that we can use this representation to efficiently and accurately perform queries. Queries involving indexed attributes can then be performed without exhaustively searching the entire database.
Banked multiported register files for high-frequency superscalar microprocessors
Authors: Jessica H. Tseng, Krste Asanović
Venue: ACM SIGARCH Computer Architecture News (2003)

Multiported register files are a critical component of high-performance superscalar microprocessors. Conventional multiported structures can consume significant power and die area. We examine the designs of banked multiported register files that employ multiple interleaved banks of fewer ported register cells to reduce power and area. Banked register files designs have been shown to provide sufficient bandwidth for a superscalar machine, but previous designs had complex control structures that would likely limit cycle time and add to design complexity. We develop a banked register file with much simpler and faster control logic while only slightly increasing the number of ports per bank. We present area, delay, and energy numbers extracted from layouts of the banked register file. For a four-issue superscalar processor, we show that we can reduce area by a factor of three, access time by 20%, and energy by 40%, while decreasing IPC by less than 5%.
Red Hat Linux 7.3 Secrets, 1 edition
Authors: Naba Barkakati, Nabajyoti Barkakati
Venue:  (2002)

:Packed with shortcuts, tune-ups, fixes, and workarounds, this one-of-a-kind guide is all you need to get more done with Red Hat Linux 7.3. From troubleshooting configuration problems and tweaking GNOME to setting up an Apache server and writing Perl scripts, Linux guru Naba Barkakati delivers hundreds of Red Hat Linux secrets that will take your productivity to a new level.
MCSE Training Guide (70-216), 2 edition
Authors: Dave Bixler, Larry Chambers, Joseph Phillips
Venue:  (2002)

:Exam 70-216, Implementing & Administering a Microsoft Windows 2000 Network Infrastructure, measures your ability to install, manage, monitor, configure, and troubleshoot DNS, DHCP, Remote Access, network protocols, IP routing, and WINS in a Windows 2000 network. Designed for current MCPs or MCSEs and network professionals with at least a year of experience, this self-study Training Guide is organized according to the actual exam objectives, equipping you with the knowledge you need to pass the exam. Each book in the best-selling Training Guide series undergoes a stringent review process, including at least two industry experts who serve as technical reviewers -- ensuring the books are accurate, comprehensive, and the ultimate resource for your exam-preparation needs.
An approach to distributed software systems
Authors: Jean Bacon
Venue: ACM SIGOPS Operating Systems Review (1981)

A conceptual framework is given for software designed as an integrated whole for a distributed system or local area network. The ISO reference model for open systems interconnection is incorporated into the design approach. A summary of mechanisms provided in systems and languages for inter-process communication is given and each mechanism is evaluated in the context of support for distributed software. A classification of typical inter-process interactions is given as a further basis for comparison.
On Arithmetic Branching Programs
Authors: Amos Beimel, Anna Gal
Venue:  (1997)

We consider the model of arithmetic branching programs, which is a generalization of modular branching programs. We show that, up to a polynomial factor in size, arithmetic branching programs are equivalent to complements of dependency programs, a model introduced by Pudlak and Sgall in 1996. Using this equivalence we prove that dependency programs are closed under conjunction, answering an open problem of Pudlak and Sgall. Furthermore, we show that span programs, an algebraic model of computation introduced by Karchmer and Wigderson in 1993, are at least as strong as arithmetic programs; every arithmetic program can be simulated by a span program of size not more than twice the size of the arithmetic program. Using the above results we give a new proof that the class NL/poly is contained in the class parity-L/poly, first proved by Wigderson in 1994. Our simulation of NL/poly is more efficient, and it holds for logspace counting classes over every field.
Design and Use of Memory-Specific Test Structures to Ensure SRAM Yield and Manufacturability
Authors: F. Duan, R. Castagnetti, R. Venkatraman, O. Kobozeva, S. Ramesh
Venue: Proceedings of the 4th International Symposium on Quality Electronic Design (2003)

High-density and high-performance single-port anddual-port SRAM increasingly occupy a majority of thechip area in System-on-Chip product designs. Therefore,good yieldability and manufacturability of theSRAM are essential. At the same time there is tremendouscompetitive pressure to get the best SRAM densityand performance. We have previously published andpresented the industry's smallest and fastest embedded6T SRAM bitcells in 0.18um and 130nm generationstandard CMOS process [1]. We have described howthese SRAM bitcells are robust by design even whileaggressively driving density and performance. In thispaper we discuss the design and use of SRAM-specifictest structures that have enabled us to quickly evaluateprocess-design interactions [2] and to fine-tune processand/or design for improving yields and manufacturability.We have designed test structures using our aggressiveproduction bitcell as basis to probe for any possibleweaknesses of the process or design in SRAM. Resultsfrom these SRAM-specific test structures show goodcorrelation to yield results and in-line SEM observations,and enable us to improve SRAM yields quickly.We have also designed SRAM-transistor test structuresto characterize the SRAM cell devices in their realworking environment. Results help to evaluate the circuitperformance and provide us with guidelines forfurther design improvements. These data when used inthe early stage of the development cycle are also usefulfor model validation.
Packet Scheduling in a Combined Input and Output Queued Switch Using Virtual Time Reference System
Authors: Yiwei Thomas Hou, Takeo Hamada, Zhi-Li Zhang
Venue: Proceedings of the Seventh International Conference on Parallel and Distributed Systems: Workshops (2000)

There is an increasing demand for Internet core nodes to have (1) quality-of-service (QoS) guarantees and (2) higher switching capacity. The combined input and output queued (CIOQ) switching has been shown to be a promising solution to meet such demand. However, many of the proposed scheduling algorithms for a CIOQ switch cannot be practically implemented due to problems from scalability and complexity. This paper shows how the virtual time reference system (VTRS) proposed in [15] can be applied to packet scheduling in a CIOQ switch. The VTRS is a unifying scheduling framework to provide scalable support for guaranteed services. In the context of packet scheduling for a CIOQ switch, we show that the use of VTRS can eliminates both the scalability and complexity problems associated with many of the scheduling algorithms proposed in the literature. More important, we show that in term of providing end-to-end guaranteed service, packet scheduling using VTRS for a CIOQ switch has the same performance as an output queued (OQ) switch employing weighted fair queuing (WFQ) scheduler.
Arc-Consistency in Dynamic CSPs Is No More Prohibitive
Authors: Romuald Debruyne
Venue: Proceedings of the 8th International Conference on Tools with Artificial Intelligence (1996)

Constraint satisfaction problems (CSPs) are widely used in Artificial Intelligence. The problem of the existence of a solution in a CSP being NP-complete, filtering techniques and particularly arc-consistency are essential. They remove some local inconsistencies and so make the search easier. Since many problems in AI require a dynamic environment, the model was extended to dynamic CSPs (DCSPs) and some incremental arc-consistency algorithms were proposed. However, all of them have important drawbacks. DnAC-4 has an expensive worst-case space complexity and a bad average time complexity. AC|DC has a non-optimal worst-case time complexity which prevents from taking advantage of its good space complexity. The algorithm we present in this paper has both lower space requirements and better time performances than DnAC-4 while keeping an optimal worst case time complexity.
Flipping the analytical coin: closing the information flow loop in high speed (real time) analysis
Authors: Kamran E Shahroudi
Venue:  (1997)

Analysis modules tend to be set up as one way flow of information, i.e a clear distinction between cause and effect or input and output. However, as the speed of analysis approaches real time (or faster than movie rate), it becomes increasingly difficult for an external user to distinguish between cause and effect because they are simultaneously available for visualization and can be viewed in any desired order. This paper discusses some potential benefits of setting up a Flipping Analytical Coin Tool (FACT) which closes the information flow loop, thereby taking advantage of the apparent equivalence between forward and reverse analysis. A simple and stable non-linear algorithm is derived which uses the principle of dimensional similarity in each independent dimension of the problem to efficiently calculate the reverse path of high speed multidimensional functions or analysis modules. An example application in the field of conceptual thermodynamic design of a turbofan engine demonstrates the usefulness of this approach to interactive design optimization of complex engineering systems. The method given here is applicable to both well and ill-posed problems.
A Framework for Dependability Specification
Authors: Richard C. Scalzo, Michelle Hugue
Venue: Proceedings of the 2nd IEEE International Conference on Engineering of Complex Computer Systems (1996)

There are many problems which arise during the development cycle of a complex real-time system. Among these are incomplete and inconsistent system-level requirements for dependable system operation, incomplete specification for system-level fault tolerance, and incomplete plans for test and evaluation. A framework for the specification of dependability properties of a system is an important part of the solution to these problems. Such a framework can be used to guide system engineers through the specification process so that the result is as complete as possible at every stage of the development cycle. It will also provide a means for checking the consistency of specifications and will provide more useful inputs for system evaluation than usual. Finally, such a framework will provide the means for providing additional information for traceability of requirements, design decisions, and test plans. The purpose of this paper is to provide such a framework.
Continuous Characterizations of the Maximum Clique Problem
Authors: Luana E. Gibbons, Donald W. Hearn, Panos M. Pardalos, Motakuri V. Ramana
Venue:  (1996)

Given a graph $G$ whose adjacency matrix is $A$, the Motzkin-Strauss formulation of the Maximum-Clique Problem is the quadratic program $\max\{x^TAx|x^Te=1,x\geq 0\}$. It is well known that the global optimum value of this QP is $(1-1/\omega(G))$, where $\omega(G)$ is the clique number of $G$. Here, we characterize the following: 1) first order optimality 2) second order optimality 3) local optimality 4) strict local. These characterizations reveal interesting underlying discrete structures, and are polynomial time verifiable. A parametrization of the Motzkin-Strauss QP is then introduced and its properties are investigated. Finally, an extension of the Motzkin-Strauss formulation is provided for the weighted clique number of a graph and this is used to derive a maximin characterization of perfect graphs.