ppxscal/embedding_network huggingface dataset:
Solving and Estimating Dynamic Models under Rational Expectations
Authors: Fabrice Collard, Patrick Fève, Corinne Perraudin
Venue: Computational Economics (2000)

This paper combines recent developments in methods for solving and estimating rational expectations dynamic models. These developments are applied to a model of labor-market search, where firms operate under uncertainty. We assess the ability of the structural model to mimic nonlinear features found in the data. The solution to the model is obtained using a method of weighted residuals. The model is then estimated using an auxiliary model technique. Our results indicate that the simple theoretical representation of the labor market we propose is able to match the overall behavior of US hours worked along various dimensions. Beyond they show the usefulness of this combined approach to study dynamic models under rational expectations.
On a solution to the cigarette smoker's problem (without conditional statements)
Authors: D. L. Parnas
Venue: Communications of the ACM (1975)

This report discusses a problem first introduced by Patil, who has claimed that the cigarette smoker's problem cannot be solved using the P and V operations introduced by Dijkstra unless conditional statements are used. An examination of Patil's proof shows that he has established this claim only under strong restrictions on the use of P and V. These restrictions eliminate programming techniques used by Dijkstra and others since the first introduction of the semaphore concept. This paper contains a solution to the problem. It also discusses the need for the generalized operators suggested by Patil.
Are you interested in computers and electronics?
Authors: David Abramson, Gordon Lowe, Peter Atkinson
Venue: Proceedings of the Australasian conference on Computing education (2000)

Secondary school students, when investigating tertiary study, have little opportunity to discover what a particular course has to offer and often have a poor understanding of employment options in that field. Further, many secondary schools have limited resources, and are thus unable to provide career advice in any detail. Whilst University Open Days' are a good opportunity for information seeking, we often experience parents driving the direction of the student's choice. In 1997 a program was initiated aimed at informing students about the &ldquo;Bachelor of Digital System&rdquo; at Monash University as a course option. Because the degree involves both digital hardware and computing, a project that offered both disciplines in a non-trivial task was desirable. The development of a computer controlled house in which electronic appliances could be monitored and operated via a computer was proposed. This system is known as the &ldquo;Smart House&rdquo;. In this paper we will discuss the concept of the Smart House with an overview of the equipment. Discussion of activities in the workshops, and feedback from participants, is also covered. One of the major outcomes mentioned by participants was that the construction of hardware and software was both fun and new, and lead to a real sense of achievement.
Autosate
Authors: O. T. Gatto
Venue: Communications of the ACM (1964)

An automated data system analysis technique is described. The technique is designed to alleviate some of the principal problems that beset current analysis&mdash;large data workloads, long span of time between project inception and system operational date, the lack of explicit directions for conducting data system analysis and using the results, and the lack of a technique to control data system changes throughout its lifetime. The analysis is geared to determining workload, relationships and storage characteristics of documents in the information network automatically.
Software Pipelining Irregular Loops On the TMS320C6000 VLIW DSP Architecture
Authors: Elana Granston, Eric Stotzer, Joe Zbiciak
Venue: ACM SIGPLAN Notices (2001)

The TMS320C6000 architecture is a leading family of Digital Signal Processors (DSPs). To achieve peak performance, this VLIW architecture relies heavily on software pipelining. Traditionally, software pipelining has been restricted to regular (FOR) loops. More recently, software pipelining has been extended to irregular (WHILE) loops, but only on architectures that provide special-purpose hardware such as rotating (predicate and general-purpose) register files, specific instructions for filling/draining software pipelined loops, and possibly hardware support for speculative code motion. In contrast, the TMS320C6000 family has a limited, static register file and no specialized hardware beyond the ability to predicate instructions using a few static registers. In this paper, we describe our experience extending a production compiler for the TMS320C6000 family to software pipeline irregular loops. We discuss our technique for preprocessing irregular loops so that they can be handled by the existing software pipeliner. Our approach is much simpler than previous approaches and works very well in the presence of the DSP applications and the target architecture which characterize our environment. With this optimization, we achieve impressive speedups on several key DSP and non-DSP algorithms.
Critical are computation for missing material defects in VLSI circuits
Authors: E. Papadopoulou
Venue: Proceedings of the 2000 international conference on Computer-aided design (2001)

We address the problem of computing critical area for missing material defects in a circuit layout. The extraction of critical area is the main computational problem in VLSI yield prediction. Missing material defects cause open circuits and are classified into breaks and via-blocks. Our approach is based on the L 1 medial axis of polygons and the weighted L 1 Voronoi diagram of segments. The critical area problem for both breaks and via-blocks is reduced to a weighted L 1 Voronoi diagram of segments. This reduction results in a plane sweep algorithm to compute critical area in one pass. The time complexity is O(n log n) in the case of breaks and O(n log n + K) in the case of via-blocks, where n is the size of the input and K is bounded by the number of interacting vias (in practice K is small). The critical area computation assumes square defects and reflects all possible defect sizes following the D(r) = r20/ r3 defect size distribution. The method is presented for rectilinear layouts. The ACM Portal is published by the Association for Computing Machinery. Copyright © 2010 ACM, Inc. Terms of Usage Privacy Policy Code of Ethics Contact Us Useful downloads: Adobe Acrobat QuickTime Windows Media Player Real Player
The cube-connected cycles: a versatile network for parallel computation
Authors: Franco P. Preparata, Jean Vuillemin
Venue: Communications of the ACM (1981)

An interconnection pattern of processing elements, the cube-connected cycles (CCC), is introduced which can be used as a general purpose parallel processor. Because its design complies with present technological constraints, the CCC can also be used in the layout of many specialized large scale integrated circuits (VLSI). By combining the principles of parallelism and pipelining, the CCC can emulate the cube-connected machine and the shuffle-exchange network with no significant degradation of performance but with a more compact structure. We describe in detail how to program the CCC for efficiently solving a large class of problems that include Fast Fourier transform, sorting, permutations, and derived algorithms.
Cascade Generalization
Authors: João Gama, Pavel Brazdil
Venue: Machine Learning (2000)

Using multiple classifiers for increasing learning accuracy is an active research area. In this paper we present two related methods for merging classifiers. The first method, Cascade Generalization, couples classifiers loosely. It belongs to the family of stacking algorithms. The basic idea of Cascade Generalization is to use sequentially the set of classifiers, at each step performing an extension of the original data by the insertion of new attributes. The new attributes are derived from the probability class distribution given by a base classifier. This constructive step extends the representational language for the high level classifiers, relaxing their bias. The second method exploits tight coupling of classifiers, by applying Cascade Generalization locally. At each iteration of a divide and conquer algorithm, a reconstruction of the instance space occurs by the addition of new attributes. Each new attribute represents the probability that an example belongs to a class given by a base classifier. We have implemented three Local Generalization Algorithms. The first merges a linear discriminant with a decision tree, the second merges a naive Bayes with a decision tree, and the third merges a linear discriminant and a naive Bayes with a decision tree. All the algorithms show an increase of performance, when compared with the corresponding single models. Cascade also outperforms other methods for combining classifiers, like Stacked Generalization, and competes well against Boosting at statistically significant confidence levels.
The security problem of nested classes
Authors: Li Yu, Xie Gaoyan, Xu Yongsen, Yang Yi
Venue: ACM SIGPLAN Notices (2000)

This paper mainly discusses the security problem of OO languages caused by the introduction of the nested class mechanism. Firstly, by analyzing various cases concerning about nested classes instances and their owner objects in detail, we illustrate the invalid owner problem arising from the difference between the lifetime of nested class instances and their owner objects. Then a solution to solve this problem is presented. Finally, a conclusion is drawn that the nested class mechanism should be suitable for the languages in which user defined classes are only used to declare dynamically created objects and which have garbage collection support, such as Java, not for the languages in which classes are allowed to declare static objects or local objects and which have no garbage collection support, such as C++.
A Fingerprint Verification System Based on Triangular Matching and Dynamic Time Warping
Authors: Zsolt Miklós Kovács-Vajna
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (2000)

An effective fingerprint verification system is presented. It assumes that an existing reference fingerprint image must validate the identity of a person by means of a test fingerprint image acquired online and in real-time using minutiae matching. The matching system consists of two main blocks: The first allows for the extraction of essential information from the reference image offline, the second performs the matching itself online. The information is obtained from the reference image by filtering and careful minutiae extraction procedures. The fingerprint identification is based on triangular matching to cope with the strong deformation of fingerprint images due to static friction or finger rolling. The matching is finally validated by Dynamic Time Warping. Results reported on the NIST Special Database 4 reference set, featuring 85 percent correct verification (15 percent false negative) and 0.05 percent false positive, demonstrate the effectiveness of the verification technique.
On the interface between computers and data communications systems
Authors: A. G. Fraser
Venue: Communications of the ACM (1972)

Future systems that combine computers, digital terminals, and communications equipment present design optimization problems that require reconsideration of the traditional functional responsibilities of the respective subsystems. Several &ldquo;standard&rdquo; interfaces, by means of which computers and digital terminals connect to the communications systems will be required. When specifying these interfaces, consideration must be given to problems of coordination, synchronization, error control, signaling, stream multiplexing, and switch control, in addition to minimizing the technological interdependence of specific subsystem designs. A focus on some of the problems is obtained in a discussion of a detailed specification for a paticular computer-communications system interface.
Optimized address assignment for DSPs with SIMD memory accesses
Authors: Markus Lorenz, David Koffmann, Steven Bashford, Rainer Leupers, Peter Marwedel
Venue: Proceedings of the 2001 Asia and South Pacific Design Automation Conference (2001)

This paper deals with address assignment in code generation for digital signal processors (DSPs) with SIMD (single instruction multiple data) memory accesses. In these processors data are organized in groups (or partitions), whose elements share one common memory address. In order to optimize program performance for processors with such memory architectures it is important to have a suitable memory layout of the variables. We propose a two-step address assignment technique for scalar variables using a genetic algorithm based partitioning method and a graph based heuristic which makes use of available DSP address generation hardware. We show that our address assignment techniques lead to a significant code quality improvement compared to heuristics.
On blooming first year programming, and its blooming assessment
Authors: Raymond Lister
Venue: Proceedings of the Australasian conference on Computing education (2000)

The traditional approach to introductory programming has students writing complete programs, as early as possible. Also, the traditional emphasis is on the technology, not the explicit cognitive development of the student. This approach jumps to the fifth and sixth levels of Bloom's Taxonomy of Educational Objectives, when these last two levels depend upon competence in the first four levels. I describe my alternative approach that addresses the six stages in sequence, emphasising effective assessment processes for the first four levels.
A simple method for generating gamma variables
Authors: George Marsaglia, Wai Wan Tsang
Venue: ACM Transactions on Mathematical Software (TOMS) (2000)

We offer a procedure for generating a gamma variate as the cube of a suitably scaled normal variate. It is fast and simple, assuming one has a fast way to generate normal variables. In brief: generate a normal variate x and a uniform variate U until In (U)x2 + d - dv + dln(italic>v), then return dv. Here, the gamma parameter is &agr; &ge; 1, and v = (1 + x/ *** with d = &agr; - 1/3. The efficiency is high, exceeding 0.951, 0.981, 0.992, 0.996 at &agr; = 1,2,4,8. The procedure can be made to run faster by means of a simple squeeze that avoids the two logarithms most of the time; return dv if U < 1-0.0331x4. We give a short C program for any &agr; &ge; 1, and show how to boost an &agr; <1 into an &agr; > 1. The gamma procedure is particularly fst for C implementation if the normal variate is generated in-line, via the #define feature. We include such an inline version, based on our ziggurat method. With it, and an inline uniform generator, gamma variates can be produced in 400MHz CPUs at better than 1.3 million per second, with the parameter &agr; changing from call to call.
The effect of rapid IT change on the demand for training
Authors: John Skip Bernamati, Albert L. Lederer
Venue: Proceedings of the 2001 ACM SIGCPR conference on Computer personnel research (2001)

Information technology is rapidly changing. This increases the complexity of IT management. Research has yet to explain the IT management problems due to such change. The current study developed a survey instrument about such problems based on experiences described in structured interviews with 16 IT professionals. The instrument was mailed to a nationwide sample of 1,000 IT professionals. Two hundred forty-six provided useable data. The research identified five of problems of rapid IT change, namely Vendor Competitiveness, Poor Quality, Incompatibility, Management Confusion, and Training Demands. It confirmed a model suggesting that increased Vendor Competitiveness leads to Poor Quality, Incompatibility, and Management Confusion, and that these increase Training Demands. The research also offers suggestions for future investigation of the problems and a potential instrument with which to conduct it.
A computer center simulation project
Authors: George K. Hutchinson
Venue: Communications of the ACM (1965)

Today's computation centers are based on rapidly changing technologies of hardware and software systems. It is difficult, therefore, to base decisions on experience; in most instances, the benefits of comparable experience for a given problem situation are not available. In this paper, a mathematical model of the Lockheed Central Computer Center is formulated that describes the operation of a computation center in terms of information nets, decision processes, and control functions. Experiments performed with this model, the results of the experiments, and the application of the results are discussed.
Full table quadratic searching for scatter storage
Authors: A. Colin Day
Venue: Communications of the ACM (1970)

The quadratic residue search method for hash tables avoids much of the clustering experienced with a linear search method. The simple quadratic search only accesses half the table. It has been shown that when the length of the table is a prime of the form 4n + 3, where n is an integer, the whole table may be accessed by two quadratic searches plus a separate access for the original entry point. A search method is presented which is computationally simple, has all the advantages of the quadratic search, and yet accesses all the table in one sweep.
Distributed resource discovery and structured data searching with Chesire II
Authors: Ray R. Larson
Venue: Proceedings of the 24th annual international ACM SIGIR conference on Research and development in information retrieval (2001)

This demonstration will show describe the construction and application of Cross-Domain Information Servers using features of the standard Z39.50 information retrieval protocol[Z39.50]. The system is currently being used to build and search distributed indexes for databases with disparate structured data (SGML and XML). We use the Z39.50 Explain Database to determine the databases and indexes of a given server, then use the Z39.50 SCAN facility to extract the contents of the indexes. This information is used to build collection documents that can be retrieved using probabilistic retrieval algorithms.
Design rewiring based on diagnosis techniques
Authors: Andreas Veneris, Magdy S. Abadir, Ivor Ting
Venue: Proceedings of the 2001 Asia and South Pacific Design Automation Conference (2001)

Logic optimization is the step of the VLSI design cycle where the designer performs modifications on a design to satisfy different constraints such as area, power or delay. Recently, ATPG-based design rewiring techniques for logic optimization have gained increasing popularity. In this paper we propose a novel ATPG-based design rewiring methodology that borrows from previous design error diagnosis and correction techniques. We also present examples and experiments that indicate the added potential of our approach which is expected to provide a "powerful" route to design optimization.
An Unclever Time-Sharing System
Authors: Caxton C. Foster
Venue: ACM Computing Surveys (CSUR) (1971)

This paper describes the internal structure of a time-sharing system in some detail. This system is dedicated to providing remote access, and has a simple file structure. It is intended for use in a university type environment where there are many short jobs that will profit from one- or two-second turnaround. Despite its simplicity, this system can serve as a useful introduction to the problems encountered by the designers of any time-sharing system. Included are a discussion of the command language, the hardware organization toward which the design is oriented, the general internal organization, the command sequences, the CPU scheduler, handling of interrupts, the assignment of core space, execution and control of the user's program, backup storage management, and the handling of errors.
Intrinsic response for analog module testing using an analog testability bus
Authors: Chauchin Su, Yue-Tsang Chen, Shyh-Jye Jou
Venue: ACM Transactions on Design Automation of Electronic Systems (TODAES) (2001)

A parasitic effect removal methodology is proposed to handle the large parasitic effects in analog testability buses. The removal is done by an on-chip test generation technique and an intrinsic response extraction algorithm. On-chip test generation creates test signals on-chip to avoid the parasitic effects of the test application bus. The intrinsic response extraction cross-checks and cancels the parasitic effects of both test application and response observation paths. The tests using both SPICE simulation and MNABST-1 P1149.4 test chip reveal that the proposed algorthm can not only remove the parasitic effects of the test buses but also tolerate test signal variations. Furthermore, it is robust enough to handle loud environmental noise and the nonlinearity of the switching devices.
A modular middleware flow scheduling framework (poster session)
Authors: Alexandre R. J. François, Gérard G. Medioni
Venue: Proceedings of the eighth ACM international conference on Multimedia (2000)

Immersive, interactive applications require on-line processing and mixing of multimedia data. In order to realize the Immersipresence vision, we propose a generic, extensible, modular multimedia system software architecture. We describe here the Flow Scheduling Framework (FSF), that constitutes the core of its middleware layer. The FSF is an extensible set of classes that provide basic synchronization functionality and composition mechanisms to develop data-stream processing components. In this dataflow approach, applications are implemented by specifying data streams and their path through processing nodes, where they can undergo various manipulations. We describe the details of the FSF data and processing model that supports stream synchronization in a concurrent processing framework. We illustrate the FSF concepts with a real-time video stream processing application.
Advanced Exception Handling Mechanisms
Authors: Peter A. Buhr, W. Y. Russell Mok
Venue: IEEE Transactions on Software Engineering (2000)

It is no longer possible to consider exception handling as a secondary issue in language design, or even worse, a mechanism added after the fact via a library approach. Exception handling is a primary feature in language design and must be integrated with other major features, including advanced control flow, objects, coroutines, concurrency, real-time, and polymorphism. Integration is crucial as there are both obvious and subtle interactions between exception handling and other language features. Unfortunately, many exception handling mechanisms work only with a subset of the features and in the sequential domain. A framework for a comprehensive, easy to use, and extensible exception handling mechanism is presented for a concurrent, object-oriented environment. The environment includes language constructs with separate execution stacks, e.g., coroutines and tasks, so the exception environment is significantly more complex than the normal single-stack situation. The pros and cons of various exception features are examined, along with feature interaction with other language mechanisms. Both exception termination and resumption models are examined in this environment, and previous criticisms of the resumption model, a feature commonly missing in modern languages, are addressed.