ppxscal/embedding_network huggingface dataset:
Empowering the student: prospects for an unintelligent tutoring system
Authors: Mitchell J. Nathan
Venue: Proceedings of the SIGCHI conference on Human factors in computing systems: Empowering people (1990)

Computer based instructional systems either direct students so modelling their actions is tractable, or provide them with total autonomy, but give little support to learning and problem solving processes. Instructional principles for empowering the student are emerging whereby more of the responsibility of diagnosis and goal-setting is placed on the student. Critical to this view is providing an environment which makes the ramifications of students' actions clear so students can meaningfully assess their own performance. In the domain of word algebra, the meaning of formal expressions can be reflected in computer animation which depicts the corresponding situation. An unintelligent tutor &mdash; knowing nothing of the problem being solved and possessing no student model &mdash; helps students to understand problems and debug formal expressions.
An algebraic treatment of quantum vibrations using REDUCE
Authors: Martin L. Sage
Venue: Journal of Symbolic Computation (1988)

Many eigenvalue problems that arise in mathematical physics and chemistry can be solved using the algebra of non-commuting operators. REDUCE can readily be used to perform the many time consuming algebraic manipulations necessary to find the solutions to these problems. Applications of REDUCE are given to the quantum mechanical one and two dimensional nearly harmonic oscillator using an algebraic approach.
Flexible aggregation of channel bandwidth in primary rate ISDN
Authors: J. W. Burren
Venue: ACM SIGCOMM Computer Communication Review (1989)

This paper describes an algorithm that allows a number of 64 Kbps ISDN circuits running between the same pair of subscribers to be aggregated into a single wideband circuit. The algorithm permits flexible aggregation in the sense that the bandwidth of the wideband circuit may be changed by the addition or removal of 64 Kbps circuits without disturbing the flow of data on the wideband channel. The paper also describes an implementation of this algorithm in an apparatus that interfaces a LAN to a primary rate ISDN interface. This interface is built using an array of transputers, and can achieve high utilization of the bandwidth available on the primary rate channel.
The birth of the second generation: the Hitachi S-820/80
Authors: C. Eoyang, R. H. Mendez, O. M. Lubeck
Venue: Proceedings of the 1988 ACM/IEEE conference on Supercomputing (1988)

A performance evaluation and comparison of the new Hitachi S-820/80 supercomputer on a set of standard Fortran benchmark codes which range from simple kernels to fluid dynamics applications.
Analysis of the Fork-Join Queue
Authors: C. Kim, A. K. Agrawala
Venue: IEEE Transactions on Computers (1989)

A fork-join queue is considered as a typical model of parallel processing systems with arrival and departure synchronizations. An approach for obtaining the transient and the steady-state solutions of the fork-join queue in terms of the virtual waiting times, which can be used to obtain the response time and the delay between the fork and the join instants, is presented. With the restriction of the service time being the Erlangian distribution, the formulations result in a form of a series, the worth of which is in actually computing numerical results. The joint-state-occupancy probabilities can be easily deduced from the results. The approximate solutions in the steady state are presented for the cases where the interarrival time distributions are exponential and hyperexponential, and the service-time distributions are exponential and two-state Erlangian. The parallelism achievable with synchronization constraints is examined from the approximations.
Introducing parallel processing at the undergraduate level
Authors: Ralph M. Butler, Roger E. Eggen, Susan R. Wallace
Venue: ACM SIGCSE Bulletin (1988)

With multiprocessor computers becoming more readily available on college campuses and with the recent development of software tools to aid in the implementation of parallel algorithms, it is time for parallel processing to enter the undergraduate curriculum. In this paper we show how widely available tools combined with concepts learned in an operating systems course could be used to develop an upper level undergraduate course in parallel processing. A typical artificial intelligence search problem (N-queens) is implemented in C and exhibits almost linear speedups.
Capturing designer expertise the CGEN system
Authors: W. P. Birmingham, D. P. Siewiorek
Venue: Proceedings of the 26th ACM/IEEE Design Automation Conference (1989)

Knowledge-based systems are becoming pervasive in the computer-aided design area. For these systems to achieve satisfactory levels of performance large amounts of knowledge are necessary; however, the acquisition of knowledge is a difficult task. Automated knowledge-acquisition tools (AKAT) provide capabilities for quickly building and maintaining knowledge-bases. This paper describes CGEN, a tool which allows hardware designers, unfamiliar with artificial intelligence, to deposit their expertise into a knowledge-base. A set of experiments which tested CGEN's capabilities are presented. The experiments demonstrate hardware designers can produce high quality knowledge-bases using CGEN.
An implementation supporting distributed execution of partitioned ada programs
Authors: R. Jha, G. Eisenhauer, J. M. Kamrad, D. Cornhill
Venue: ACM SIGAda Ada Letters (1989)

This paper describes the implementation of a novel paradigm for building distributed application software in Ada. The entire application is written as a single program, which is partitioned for distributed execution after its design. The partitioning is expressed in a separate notation called the Ada Program Partitioning Language (APPL). A modified compilation system accepts an Ada program and an APPL specification for it as input, to produce a separate executable image for each node. There is considerable freedom in what Ada entities may be placed on different nodes. The two-phase design approach helps reduce design complexity, and allows experimentation with different strategies for allocating software to hardware without requiring software redesign. Our implementation is currently under the final stages of testing using a modified version of the Ada compiler validation test-suite.Section 1 presents an overview of our paradigm and the rationale behind it. Section 2 introduces APPL. Section 3 describes our current implementation. Section 4 discusses the question of what Ada entities should be distributable, and compares several alternatives. Finally, section 5 concludes the paper with pointers to future work.
On the execution of parallel programs on multiprocessor systems&mdash;a queuing theory approach
Authors: François Baccelli, Zhen Liu
Venue: Journal of the ACM (JACM) (1990)

The new class of queuing models, called Synchronized Queuing Networks, is proposed for evaluating the performance of multiprogrammed and multitasked multiprocessor systems, where workloads consists of parallel programs of similar structure and where the scheduling discipline is first-come-first-serve. Pathwise evolution equations are established for these networks that capture the effects of competition for processors and the precedence constraints governing tasks executions. A general expression is deduced for the stability condition of such queuing networks under general statistical assumptions (basically the stationarity and the ergodicity of input sequences), which yields the maximum program throughput of the multiprocessor system, or equivalently, the maximum rate at which programs can be executed or submitted. The proof is based on the ergodic theory of queues. Basic integral equations are also derived for the stationary distribution of important performance criteria such as the workload of the queues and program response times. An iterative numerical schema that converges to this solution is proposed and various upper and lower bounds on moments are derived using stochastic ordering techniques.
CMOS stuck-open fault detection using single test patterns
Authors: R. Rajsuman, A. P. Jayasumana, Y. K. Malaiya
Venue: Proceedings of the 26th ACM/IEEE Design Automation Conference (1989)

CMOS combinational circuits exhibit sequential behavior in the presence of open faults, thus making it necessary to use two pattern tests. Two or multi-pattern sequences may fail to detect CMOS stuck-open faults in the presence of glitches. The available methods for augmenting CMOS gates to test CMOS stuck-open faults, are found to be inadequate in the presence of glitches. A new CMOS testable design is presented. The scheme uses two additional MOSFETs, which convert a CMOS gate to either pseudo nMos or pseudo pMOS gate during testing. The proposed design ensures the detection of stuck-open faults using a single vector during testing
Rapid controlled movement through a virtual 3D workspace
Authors: Jock D. Mackinlay, Stuart K. Card, George G. Robertson
Venue: Proceedings of the 17th annual conference on Computer graphics and interactive techniques (1990)

Computer graphics hardware supporting real-time interactive 3D animation has the potential to support effective user interfaces by enabling virtual 3D workspaces. However, this potential requires development of viewpoint movement techniques that support rapid and controlled movement through workspaces. Rapid movement through large distances avoids wasted work time; controlled movement near target objects allows the user to examine and interact with objects in the workspace. Current techniques for viewpoint movement typically use high velocities to cover distances rapidly, but high velocities are hard to control near objects. This paper describes a new technique for targeted viewpoint movement that solves this problem. The key idea is to have the user indicate a point of interest (target) on a 3D object and use the distance to this target to move the viewpoint logarithmically, by moving the same relative percentage of distance to the target on every animation cycle. the result is rapid motion over distances that slows as the viewpoint approaches the target object. The technique can be used with 2D and multidimensional input devices. We also extend the technique to move objects in the workspace.
The architecture and programming of the Ametek series 2010 multicomputer
Authors: C. L. Seitz, W. C. Athas, C. M. Flaig, A. J. Martin, J. Seizovic, C. S. Steele, W-K. Su
Venue: Proceedings of the third conference on Hypercube concurrent computers and applications: Architecture, software, computer systems, and general issues - Volume 1 (1988)

During the period following the completion of the Cosmic Cube experiment [1], and while commercial descendants of this first-generation multicomputer (message-passing concurrent computer) were spreading through a community that includes many of the attendees of this conference, members of our research group were developing a set of ideas about the physical design and programming for the second generation of medium-grain multicomputers. Our principal goal was to improve by as much as two orders of magnitude the relationship between message-passing and computing performance, and also to make the topology of the message-passing network practically invisible. Decreasing the communication latency relative to instruction execution times extends the application span of multicomputers from easily partitioned and distributed problems (eg, matrix computations, PDE solvers, finite element analysis, finite difference methods, distant or local field many-body problems, FFTs, ray tracing, distributed simulation of systems composed of loosely coupled physical processes) to computing problems characterized by &ldquo;high flux&rdquo; [2] or relatively fine-grain concurrent formulations [3, 4] (eg, searching, sorting, concurrent data structures, graph problems, signal processing, image processing, and distributed simulation of systems composed of many tightly coupled physical processes). Such applications place heavy demands on the message-passing network for high bandwidth, low latency, and non-local communication. Decreased message latency also improves the efficiency of the class of applications that have been developed on first-generation systems, and the insensitivity of message latency to process placement simplifies the concurrent formulation of application programs. Our other goals included a streamlined and easily layered set of message primitives, a node operating system based on a reactive programming model, open interfaces for accelerators and peripheral devices, and node performance improvements that could be achieved economically by using the same technology employed in contemporary workstation computers. By the autumn of 1986, these ideas had become sufficiently developed, molded together, and tested through simulation to be regarded as a complete architectural design. We were fortunate that the Ametek Computer Research Division was ready and willing to work with us to develop this system as a commercial product. The Ametek Series 2010 multicomputer is the result of this joint effort.
Feature Extraction from Boundary Models of Three-Dimensional Objects
Authors: L. de Floriani
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1989)

An algorithm for extracting certain classes of form features from a relational boundary model of an object, called the generalized edge-face graph (GEFG), is described. The GEFG provides a face-based topological description of the object boundary and encodes the minimum number of relations needed in the recognition process. The feature identification and classification are based on the analysis of the connectivity properties of the edge-face graph associated with the GEFG and on some geometric considerations. The result is a hierarchical graph decomposition of the object boundary into components representing form features.
APL: The language of science and management
Authors: A. Eisner, S. M. Yionoulis, J. A. Platt, R. Jernigan
Venue: Proceedings of the international conference on APL (1987)

APL (A Programming Language) has been in use at the Space Department of The Johns Hopkins University Applied Physics Laboratory (JHU/APL) for scientific problem solving. APL was a very attractive alternative to the slow, expensive and often unavailable pool of scientific programmers, and became the language of choice for a variety of scientific projects. APL was not considered to be suitable for solving business and management related problems or for building end-user applications. A critical need for modern management tools, the availability of experienced APL Programmer/Analysts, and the introduction at JHU/APL of APL Application Development Programming Productivity (ADPP) tools, resulted in management decision to explore the potential of APL for developing end-user applications. The two business (management) oriented applications which have been developed have resulted in management's acceptance of APL as an end-user application development language in addition to its traditional role in science and engineering. The rationale for choosing APL to develop end-user business applications and a short description of some of the ADPP tools and applications developed are the subject of this paper.
Limiting a resolution set in a large Prolog database using special hardware
Authors: K. F. Wong, M. H. Williams
Venue: Proceedings of the 1988 ACM SIGSMALL/PC symposium on ACTES (1988)

There is a growing interest in the application of Prolog and related languages like Parlog to database implementation. Existing Prolog systems, however, are unable to cope with large sets of data of the size necessary for databases. A large Prolog database would consist of millions of clauses. The size of physical memory required to store the database has deemed main memory impractical in many computer systems. Therefore clauses are usually placed on secondary disc memory. Clause retrieval, however, becomes extremely slow. Furthermore, the enormous amount of time required for unification upon a large set of clauses has drastically degraded system performance. Either of these factors leads to non-timely database response which is irritating and in many cases, intolerable. To mediate these problems, a special hardware unit is proposed - the CLAuse Retrieval Engine (CLARE). The functions of the CLARE are to search discs storing database clauses on-the-fly and select potentially unifiable clauses. Two stages of filtering will be applied to the database clauses; thus a small resolution set will be guaranteed.
Optimal selection theory for superconcurrency
Authors: R. F. Freund
Venue: Proceedings of the 1989 ACM/IEEE conference on Supercomputing (1989)

This paper describes a mathematical programming approach to finding an optimal, heterogeneous suite of processors to solve supercomputing problems. This technique, called superconcurrency, works best when the computational requirements are diverse and significant portions of the code are not tightly-coupled. It is also dependent on new methods of benchmarking and code profiling, as well as eventual use of AI techniques for intelligent management of the selected superconcurrent suite.
System architecture of parallel processing system -Harry-
Authors: H. Yamana, T. Marushima, T. Hagiwara, Y. Muraoka
Venue: Proceedings of the 2nd international conference on Supercomputing (1988)

This paper proposes a parallel processing system -Harray- for scientific computations. Data flow computers are expected to obtain the high performance because they can extract parallelism fully from a program. However, they have many problems, such as the difficulty of controlling the sequence of execution. The -Harray- system is an array processor which adapts two levels of control mechanism; data flow execution in each processor and control flow between processors, in order to take full advantage of both mechanisms. A task which is assigned to a processor is called a &ldquo;macro-block&rdquo;. Three types of macro-blocking and three types of activation schemes for the macro-block which initiates its execution are introduced in order to attain the high performance. Moreover, a hardware synchronization mechanism is used to reduce synchronization overhead and to gain the liner speedup of the -Harray- system. In this paper, the system architecture of the -Harray- system and its performance evaluation by software simulation are presented.
On the Complexity of Mod-2l Sum PLA's
Authors: T. Sasao, P. Besslich
Venue: IEEE Transactions on Computers (1990)

Consideration is given to the realization of logic functions by using PLAs with an exclusive-OR (EXOR) array, where a function is represented by mod-2 (EXOR) sum-of-products (ESOPs) and both true and complemented variables are used. The authors propose a new PLA structure using an EXOR array. They derive upper bounds on the number of products of this type of PLA that are useful for estimating the size of a PLA as well as for assessing the minimality of the solutions obtained by heuristic ESOP minimization algorithms. Computer simulation using randomly generated functions shows that PLAs with the EXOR array require, on the average, fewer products than conventional PLAs. For symmetric functions, the authors conjecture that the PLAs with an EXOR array require, at most, as many products as the conventional PLAs. The proposed PLAs can be made easily testable by adding a small amount of hardware.
Employing path dissolution to shorten tableaux proofs
Authors: N. V. Murray, E. Rosenthal
Venue: Proceedings of the ACM-SIGSAM 1989 international symposium on Symbolic and algebraic computation (1989)

Path dissolution is an inferencing mechanism that generalizes the method of analytic tableaux. The main result presented is that every non-trivial step in any tableau proof can be speeded up with the application of dissolution techniques.
An intelligent interface for the design of optimal control systems
Authors: R. Acerbi, P. O. Simoni, E. Cardoso
Venue: Proceedings of the 2nd international conference on Industrial and engineering applications of artificial intelligence and expert systems - Volume 1 (1989)

An interface for giving suggestions about how to modify weighting matrixes which appear in the formulation of optimal control problems with quadratic performance index is described. The suggestions come both from heuristics for choosing the matrix elements, some of them being obtained through simulations for several systems, and also from criteria for improving the system in relation to the specification of some parameters.
An environment for operational software engineering in Ada
Authors: M. Baldassari, G. Bruno
Venue: Proceedings of the conference on Tri-Ada '89: Ada technology in context: application, development, and deployment (1989)

This paper presents PROTOB, an object-oriented methodology and CASE system based on an extended dataflow model defined using PROT nets. It consists of several tools supporting specification, modelling and prototyping activities within the framework of the operational software life cycle paradigm. As its major application area it addresses distributed systems, such as real-time embedded systems, communication protocols and manufacturing control systems. The system automatically generates the distributed and Object-Oriented implementation code in Ada exploiting advanced features of the language such as tasks and packages.
Automated facilities scheduling
Authors: David S. Condrey, Cynthia J. Calcutt
Venue: Proceedings of the 16th annual ACM SIGUCCS Conference on User Services (1988)

In Consulting Technical Services (CTS) at Clemson University, one of our goals is to provide staffed public access computing facilities. With this goal in mind, we currently staff 15 facilities with student consultants. In order to staff 15 facilities 7 days per week, we employ approximately 120 student consultants. We schedule each facility once a semester. We have found scheduling by hand to be too cumbersome and time consuming. Therefore, in August of 1986 we initiated a project to configure an on-line scheduling system. The result was a SAS-based data acquisition subsystem providing information for a Pascal scheduler running on a NAS AS/XL-60, which is an IBM 3090 compatible mainframe. The system is open-ended which enables it to run on any machine supporting both SAS and Pascal languages. This paper will explain the configuration and use of this system.
A simple technique to motivate structured programming
Authors: Terry Flaherty
Venue: ACM SIGCSE Bulletin (1988)

Programs with only sequence, selection, and iteration control structures (structured programs) are more understandable and changeable than programs with unrestricted control structures (flowchart programs). However, flowcharts are intuitive, simple, and easy to follow step by step. The transition from teaching general flowcharts to structured ones is usually made by postulating the standard structured flowchart patterns without much justification. The present method establishes the correspondence between flowcharts and structured programs via sets of computations. The student examines a set of computations of a flowchart program and describes the general structure with a regular expression. A structured program that corresponds to this regular expression is constructed. In this way, the student is led to (1) see the difference between program and computation, (2) see how &ldquo;structure&rdquo; arises, (3) see that a structured program is one whose textual structure is identical to the structural description of its computations, (4) appreciate the cognitive simplicity of structure descriptions versus flowcharts.