ppxscal/embedding_network huggingface dataset:
Automatic translation of FORTRAN programs to vector form
Authors: Randy Allen, Ken Kennedy
Venue: ACM Transactions on Programming Languages and Systems (TOPLAS) (1987)

The recent success of vector computers such as the Cray-1 and array processors such as those manufactured by Floating Point Systems has increased interest in making vector operations available to the FORTRAN programmer. The FORTRAN standards committee is currently considering a successor to FORTRAN 77, usually called FORTRAN 8x, that will permit the programmer to explicitly specify vector and array operations. Although FORTRAN 8x will make it convenient to specify explicit vector operations in new programs, it does little for existing code. In order to benefit from the power of vector hardware, existing programs will need to be rewritten in some language (presumably FORTRAN 8x) that permits the explicit specification of vector operations. One way to avoid a massive manual recoding effort is to provide a translator that discovers the parallelism implicit in a FORTRAN program and automatically rewrites that program in FORTRAN 8x. Such a translation from FORTRAN to FORTRAN 8x is not straightforward because FORTRAN DO loops are not always semantically equivalent to the corresponding FORTRAN 8x parallel operation. The semantic difference between these two constructs is precisely captured by the concept of dependence. A translation from FORTRAN to FORTRAN 8x preserves the semantics of the original program if it preserves the dependences in that program. The theoretical background is developed here for employing data dependence to convert FORTRAN programs to parallel form. Dependence is defined and characterized in terms of the conditions that give rise to it; accurate tests to determine dependence are presented; and transformations that use dependence to uncover additional parallelism are discussed.
On the application of sheared retrieval to orthogonal range queries
Authors: D E Willard
Venue: Proceedings of the second annual symposium on Computational geometry (1986)

We propose a new search technique, called the Shear-Based Format, which shows that Yao's lower bound on the time-space tradeoff for orthogonal range queries is either optimal or nearly optimal [Ya82, Ya85]. Shearing is also a very pragmatic technique.
Language support for the specification and development of composite systems
Authors: Martin S. Feather
Venue: ACM Transactions on Programming Languages and Systems (TOPLAS) (1987)

When a complex system is to be realized as a combination of interacting components, development of those components should commence from a specification of the behavior required of the composite system. A separate specification should be used to describe the decomposition of that system into components. The first phase of implementation from a specification in this style is the derivation of the individual component behaviors implied by these specifications. The virtues of this approach to specification are expounded, and specification language features that are supportive of it are presented. It is shown how these are incorporated in the specification language Gist, which our group has developed. These issues are illustrated in a development of a controller for elevators serving passengers in a multistory building.
A polynomial time generator for minimal perfect hash functions
Authors: Thomas J. Sager
Venue: Communications of the ACM (1985)

A perfect hash function PHF is an injection F from a set W of M objects into the set consisting of the first N nonnegative integers where N &ges; M. If N = M, then F is a minimal perfect hash function, MPHF. PHFs are useful for the compact storage and fast retrieval of frequently used objects such as reserved words in a programming language or commonly employed words in a natural language.The mincycle algorithm for finding PHFs executes with an expected time complexity that is polynomial in M and has been used successfully on sets of cardinality up to 512. Given three pseudorandom functions h0, h1, and h2, the mincycle algorithm searches for a function g such that F(w) = (h0(w) + g &deg; h1(w) + g &deg; h2(w)) mod N is a PHF.
Notable computer networks
Authors: John S. Quarterman Josiah C. Hoskins
Venue: Communications of the ACM (1986)

Computer networks are becoming more numerous and more diverse. Collectively, they constitute a worldwide metanetwork.
The Burroughs integrated adaptive routing system (BIASTM)
Authors: S Gruchevsky, D Piscitello
Venue: ACM SIGCOMM Computer Communication Review (1987)

The routing function used for Burroughs Network Architecture (BNA) to determine the best routes for traffic through the network is known as the BURROUGHS INTEGRATED ADAPTIVE ROUTING SYSTEM, or BIAS trade;.Based on the algorithm devised for the MERIT Computer Network [3], BIAS trade; is a decentralized, deterministic system which adapts to changes in network topology automatically. The current BIAS trade; routing architecture incorporates improvements in the original algorithm [1] which significantly reduce the recovery time from failures of network elements and is virtually loop-free, even during recovery from those failures.BIAS trade; automatically responds to the following changes to the network topology:- a node (an end system or intermediate system) is added to the network;- a node is removed from the network;- the cost of transiting a node is changed;- a logical link (LAN, leased or switched circuit, X.25 virtual circuit) is added to the network;- a link is removed from the network; and/or- the cost of transiting a link is changed;and re-determines the best route for all traffic throughout the network.
Access control for network directory systems
Authors: M Goodwin, K J McDonell
Venue: ACM SIGCOMM Computer Communication Review (1986)

Directory Systems to support communications networks are currently the subject of serious international standardization efforts. The most recent CCITT and ISO proposals for Directory Systems are summarized, and within this context the requirements for flexible and robust access control mechanisms are examined. The existence of varied access control policies at the international, national and local levels and the need to maintain the integrity of Directory System information are identified as major factors determining access control procedures. Techniques are suggested for access control mechanisms capable of capturing and enforcing the relevant access control semantics at each network site.
Empty types in polymorphic lambda calculus
Authors: A. R. Meyer, J. C. Mitchell, E. Moggi, R. Statman
Venue: Proceedings of the 14th ACM SIGACT-SIGPLAN symposium on Principles of programming languages (1987)

The model theory of simply typed and polymorphic (second-order) lambda calculus changes when types are allowed to be empty. For example, the &ldquo;polymorphic Boolean&rdquo; type really has exactly two elements in a polymorphic model only if the &ldquo;absurd&rdquo; type &forall;t.t is empty. The standard &bgr;-&egr; axioms and equational inference rules which are complete when all types are nonempty are not complete for models with empty types. Without a little care about variable elimination, the standard rules are not even sound for empty types. We extend the standard system to obtain a complete proof system for models with empty types. The completeness proof is complicated by the fact that equational &ldquo;term models&rdquo; are not so easily obtained: in contrast to the nonempty case, not every theory with empty types is the theory of a single model.
A Simulation Study of the Vertical-Migration Microprocessor Architecture
Authors: Veljko Milutinovic
Venue: IEEE Transactions on Software Engineering (1987)

Vertical-migration microprocessor architecture was introduced in [1], and results of its analytical study were presented in the same paper. This paper presents results of its simulation study which is based on selected production benchmarks. Vertical-migration architecture enables the constructs typical of HLL's to be mapped into the constructs typical of microcode. This mapping is provided only for selected types of HLL statements and for HLL statements with a relatively small number of operands and parameters, i.e., for-the most frequent HLL constructs. Using an extended subset of Fortran 77, one that matches the typical demands of the targeted application, i.e., dedicated microprocessing, it has been shown how the proposed architecture supports the mapping of HLL constructs into microinstructions. That was done through the description of a flexible register-transfer level simulator which was implemented to support this study. It was used to run benchmarks, typical of various applications, on various configurations of the architecture. Simulation study has shown that this approach is particularly suitable for the time-critical dedicated signal processing and robotics/control applications, as well as for the GaAs implementation.
Modeling of Software Partition for Distributed Real-Time Applications
Authors: James P. Huang
Venue: IEEE Transactions on Software Engineering (1985)

The issue of software partition deals with the process of mapping the given set of logical modules, which reflect the user's point of view, into a set of software tasks, which reflect the software implementor's point of view. It is shown in this paper that the software partitioning problem can be modeled as one that maximizes the efficiency in resource utilization while observing the constraints on CPU throughput, memory space available, maximally allowed task execution time, and the order of module execution. The CPU and memory constraints are implementation dependent. The maximum task execution time constraint is due to considerations on the response time performance. The constraint on module execution order is a logical one, and it is shown to have significant performance impact. It is proven that by employing the module precedence relation, which reflects the sequence of module execution, the order of module execution can be properly maintained during the software partitioning process. And thus the defined tasks can be guaranteed to be completely executable, once properly activated With completely executable tasks, the operating overhead cost and the response time delay can be minimized. The following four module precedence relations are explored: precede, succeed, parallel, and precede as well as succeed. The validity of the selected partitioning criterion of maximizing the resource utilization efficiency is also assessed through simulation experiments. The results of simulation show that performance of the selected criterion is insensitive to the application environment, as well as to the application requirements.
An interactive demonstration system for implementations of abstract data types
Authors: Martin Hitz
Venue: ACM SIGCSE Bulletin (1987)

A dialogue-oriented tutorial system to visualize various kinds of implementations of abstract data types (ADTs) like LIST, STACK, QUEUE, or SET is presented.The system runs on a PRIME 750 mini-computer and supports an advanced course on data structures and algorithms by graphically showing the way the ADT's primitive operations (like MakeNull, Insert, Delete etc.) can be realized by Pascal-procedures using different basic data types. The user walks through the Pascal-code when accessing the data structure. Help-screens explain the basic concepts of the algorithms under investigation.This paper describes the capabilities of the system and shows an example of its usage.
Countable nondeterminism and random assignment
Authors: K. R. Apt, G. D. Plotkin
Venue: Journal of the ACM (JACM) (1986)

Four semantics for a small programming language involving unbounded (but countable) nondeterminism are provided. These comprise an operational semantics, two state transformation semantics based on the Egli-Milner and Smyth orders, respectively, and a weakest precondition semantics. Their equivalence is proved. A Hoare-like proof system for total correctness is also introduced and its soundness and completeness in an appropriate sense are shown. Finally, the recursion theoretic complexity of the notions introduced is studied. Admission of countable nondeterminism results in a lack of continuity of various semantic functions, and this is shown to be necessary for any semantics satisfying appropriate conditions. In proofs of total correctness, one resorts to the use of (countable) ordinals, and it is shown that all recursive ordinals are needed.
Toward a history of (personal) workstations
Authors: Gordon Bell
Venue: Proceedings of the ACM Conference on The history of personal workstations (1986)

I originally accepted this keynote honor for five reasons: to respond to Alan Perlis' request (he told me I could present anything from a new taxonomy to personal reminiscences); second, to identify the important artifacts that should be preserved in The Computer Museum; third, to posit a framework of the history of workstations that can be written in the next century (we're all too close to create it); fourth, to summarize my own involvement on interactive computing including timesharing and large personal computers (both styles of use led to personal workstations); finally, to record my work on Digital's VAX Homogeneous Computing Environment that was totally announced last year. I led the architecture for this environment over the decade from 1973 to 1982 and was strongly influenced by the personal workstation computing movement including Ethernet. This work hasn't been described outside of product brochures.
Optimal shortest path queries in a simple polygon
Authors: L. J. Guibas, J. Hershberger
Venue: Proceedings of the third annual symposium on Computational geometry (1987)

Let P be a simple polygon with n sides. This paper shows how to preprocess the polygon so that, given two query points p and q inside P, the length of the shortest path inside the polygon from p to q can be found in time &Ogr;(log n). The path itself must be polygonal and can be extracted in additional time proportional to the number of turns it makes. The preprocessing consists of triangulation plus a linear amount of additional work.
RISCs vs. CISCs for Prolog: a case study
Authors: Gaetano Borriello, Andrew R. Cherenson, Peter B. Danzig, Michael N. Nelson
Venue: ACM SIGARCH Computer Architecture News (1987)

This paper compares the performance of executing compiled Prolog code on two different architectures under development at U. C. Berkeley. The first is the PLM, a special-purpose CISC architecture intended as a coprocessor for a host machine. The second is SPUR, a general-purpose RISC architecture that supports tagged data. Fourteen standard benchmark programs were run on both the PLM and SPUR simulators. The compiled code for SPUR was obtained by simple macro-expansion of PLM code generated by the PLM Prolog compiler. The two implementations are compared with regard to static and dynamic program size, execution speed, and memory system performance. On average, the macrocoded SPUR implementation has a static code size 14 times larger than the PLM, executes 16 times more instructions, yet requires only 2.3 times the number of machine cycles (or has the performance of 0.43 PLMs). When memory system performance is taken into account, SPUR is equivalent to 0.29 PLMs. Optimizations of the macro-expanded code and minor architectural changes to SPUR would increase this ratio to 0.53, or 0.60 for the largest benchmarks. Thus a tagged RISC architecture can execute Prolog at least half as fast as a special-purpose CISC architecture for Prolog.
Summary of the second annual UCLA survey of business school computer usage
Authors: Jason L. Frand, Ephraim R. McLean
Venue: Communications of the ACM (1986)

The compilation and analysis of data collected from 125 business schools reveal important trends and identify problems that arise when computers are integrated into education.
New methods and fast algorithms for database normalization
Authors: Jim Diederich, Jack Milton
Venue: ACM Transactions on Database Systems (TODS) (1988)

A new method for computing minimal covers is presented using a new type of closure that allows significant reductions in the number of closures computed for normalizing relations. Benchmarks are reported comparing the new and the standard techniques.
Distributed logging for transaction processing
Authors: Dean S. Daniels, Alfred Z. Spector, Dean S. Thompson
Venue: ACM SIGMOD Record (1987)

Increased interest in using workstations and small processors for distributed transaction processing raises the question of how to implement the logs needed for transaction recovery. Although logs can be implemented with data written to duplexed disks on each processing node, this paper argues there are advantages if log data is written to multiple log server nodes. A simple analysis of expected logging loads leads to the conclusion that a high performance, microprocessor based processing node can support a log server if it uses efficient communication protocols and low latency, non volatile storage to buffer log data. The buffer is needed to reduce the processing time per log record and to increase throughput to the logging disk. An interface to the log servers using simple, robust, and efficient protocols is presented. Also described are the disk data structures that the log servers use. This paper concludes with a brief discussion of remaining design issues, the status of a prototype implementation, and plans for its completion.
Computer backup pools, disaster recovery, and default risk
Authors: Yehuda Kahane, Seev Neumann, Charles S. Tapiero
Venue: Communications of the ACM (1988)

There is a growing popularity of computer backup pools, where a few members share the ownership, or right for service, of a computer center. Such a center stands by to provide for the lost computing capacity of a member suffering a computer breakdown and disaster recovery. The efficiency of such a solution may be examined from various points of view, such as costs, response time, reliability etc. We focus on the reliability of such an arrangement. Two types of default risks are discussed: the probability that the center itself will break down when needed, so that it would be unable to provide service (this is similar to the traditional measure of a "probability of ruin") and a "perceived probability of ruin" (the probability that a member will be affected by the failure of the center). We borrow the concepts of probability of ruin from the risk management and insurance literature, in order to reach explicit relationships between these probabilities and the pricing of a mutual computer pool. It is shown that the membership fee for each participant must be a function of both the payments of all members and their loss (call for service) distributions, reflecting thereby the simultaneity of and mutual interdependence of members.
A simple expert system
Authors: B. I. Blum
Venue: ACM SIGBIO Newsletter (1988)

Expert systems are one field of artificial intelligence (AI) that has received considerable recent attention. These systems generally are written in Lisp or Prolog -- languages that are interpretive, have flexible data accessing mechanisms, and use powerful string manipulation tools. This raises two questions: what are expert systems, and can they be implemented using MUMPS? Some answers are presented in this paper.
An Optimum Parallel Architecture for High-Speed Real-Time Digital Signal Processing
Authors: Gordon R. Lang, Moez Dharssi, Fred M. Longstaff, Philip S. Longstaff, Peter A. S. Metford, Malcolm T. Rimmer
Venue: Computer (1988)

The authors describe a parallel processing architecture for real-time digital signal processing that has demonstrated virtually 100% data processing efficiency in a number of areas. The Teamed-Architecture Signal Processor (T-ASP) is a field-proven, commercially available optimal system solution to the extremely high computational and I/O rates encountered in modern digital-signal-processing environments. The design of T-ASP involves the consideration and implementation of many architectural concepts used to enhance the performance of a computer, including programmability, parallel processing, vector processing and pipelining, memory interleaving, double cache memories, multiple high-speed I/O interfaces, and segmentation of the processors for elimination of both CPU and data-handling overhead. The authors discuss hardware architecture design and implementation; hardware management; and software architecture design and implementation.
Software for an implementation of Weeks' method for the inverse Laplace transform
Authors: B. S. Garbow, G. Giunta, J. N. Lyness, A. Murli
Venue: ACM Transactions on Mathematical Software (TOMS) (1988)

A software package based on a modification of the Weeks' method is presented for calculating function values f(t) of the inverse Laplace transform. This method requires transform values F(z) at arbitrary points in the complex plane, and is suitable when f(t) has continuous derivatives of all orders; it is especially attractive when f(t) is required at a number of different abscissas t.
A system to make visible the structure and execution of student programs
Authors: Willett Kempton
Venue: Proceedings of the seventeenth SIGCSE technical symposium on Computer science education (1986)

Visual models help to convey programming insights and computer science principles. This paper describes the design criteria for a software system which automatically constructs visual models as a program runs. Line-by-line execution and data structures are dynamically updated on a display screen. The system can be used either by an instructor in class demonstrations, or by the student in running his or her own programs. Motivations for the design criteria are discussed, along with tradeoffs in implementation. A system has been developed for the Pascal programming language, running on a variety of popular microcomputers.
A linear time algorithm for residue computation and a fast algorithm for division with a sparse divisor
Authors: Michael Kaminski
Venue: Journal of the ACM (JACM) (1987)

An algorithm is presented to compute the residue of a polynomial over a finite field of degree n modulo a polynomial of degree O(log n) in O(n) algebraic operations. This algorithm can be implemented on a Turing machine. The implementation is based on Turing machine procedure that divides a polynomial of degree n by a sparse polynomial with k nonzero coefficients in O(kn) steps. This algorithm can be adapted to compute the residue of a number of length n modulo a number of length O(log n) in O(n) bit operations.
Optimal bounds for decision problems on the CRCW PRAM
Authors: P. Beame, J. Hastad
Venue: Proceedings of the nineteenth annual ACM symposium on Theory of computing (1987)

We prove optimal &OHgr;(log n/log log n) lower bounds on the time for CRCW PRAM's with polynomially bounded numbers of processors or memory cells to compute parity and a number of related problems. We also exhibit a strict time hierarchy of explicit Boolean functions of n bits on such machines which holds up to &Ogr;(log n/log log n) time. Furthermore, we show that almost all Boolean functions of n bits require log n - log log n + &OHgr;(1) time when the number of processors is at most polynomial in n. Our bounds do not place restrictions on the uniformity of the algorithms nor on the instruction sets of the machines.