ppxscal/embedding_network huggingface dataset:
Stereo Error Detection, Correction, and Evaluation
Authors: Rakesh Mohan, Gerard Medioni, Ramakant Nevatia
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1989)

An algorithm is presented for error detection and correction of disparity, as a process separate from stereo matching, with the contention that matching is not necessarily the best way to utilize all the physical constraints characteristic to stereopsis. As a result of the bias in stereo research towards matching, vision tasks like surface interpolation and object modeling have to accept erroneous data from the stereo matchers without the benefits of any intervening stage of error correction. An algorithm which identifies all errors in disparity data that can be detected on the basis of figural continuity and corrects them is presented. The algorithm can be used as a postprocessor to any edged-based stereo matching algorithm, and can additionally be used to automatically provide quantitative evaluations on the performance of matching algorithms of this class.
TS: an optimizing compiler for smalltalk
Authors: Ralph E. Johnson, Justin O. Graver, Laurance W. Zurawski
Venue: ACM SIGPLAN Notices (1988)

TS (Typed Smalltalk) is a portable optimizing compiler that produces native machine code for a typed variant of Smalltalk, making Smalltalk programs much faster. This paper describes the structure of TS, the kinds of optimizations that it performs, the constraints that it places upon Smalltalk, the constraints placed upon it by an interactive programming environment, and its performance.
Fully automatic VLSI diagnosis in a CAD-linked E-beam probing system
Authors: M. Melgara, M. Battu', P. Garino, J. Dowe, M. Marzouki
Venue: Microelectronic Engineering (1988)

The use of E-beam equipment in VLSI validation has been stated repeatedly in the past. However, only recently, the necessity for a full integration between the CAD (Computer Aided Design) world and the E-Beam world has been felt. The next step is to completely automate the E-beam debugging procedure. This paper, after a draft description of an integrated E-beam debugging system, developed under Esprit Project 271, will present the strategies and the algorithms to achieve a fully automatic trouble-shooting procedure.
Threading Lisp
Authors: D. J. Nordstrom
Venue: ACM SIGPLAN Notices (1990)

An interpreter for Lisp based on the Forth model is described: Lisp and Forth are compared, threaded interpreters are discussed, and aspects of a Lisp implementation are presented.
A benchmark of NonStop SQL on the debit credit transaction
Authors: Tandem Performance Group
Venue: Proceedings of the 1988 ACM SIGMOD international conference on Management of data (1988)

NonStop SQL is an implementation of ANSI SQL on Tandem Computer Systems Debit Credit is a widely used industry-standard transaction. This paper summarizes a benchmark of NonStop SQL which demonstrated linear growth of throughout from 14 to 208 Debit Credit transactions per second as the hardware grew from 2 to 32 processors. The benchmark also compared the performance of NonStop SQL to the performance of a record-at a time file system interface
Concurrent data structures and actor programming under the Matroshka model
Authors: L. A. Crowl
Venue: Proceedings of the 1988 ACM SIGPLAN workshop on Object-based concurrent programming (1988)

In the late panel session, Maurice Herlihy questioned whether the Actor model [1] could implement wait-free shared queue. Processes are guaranteed to complete queue operations in a finite amount of steps even if other processes may fail at arbitrary points. Consequently, the queue may not have an implementation based on mutual exclusion, but may be implemented with non-trivial atomic operations. Gul Agha did not provide a method for implementing such an abstraction, but argued that the techniques used to implement the wait-free queue would also apply to implementing the Actor model.The Matroshka model (described in the position statement "A Uniform Object Model for Parallel Programming" within these proceedings and [2]) can implement both wait-free queues and the Actor model of computation.
A robust parallel solver for block tridiagonal systems
Authors: R. Bramley, A. Sameh
Venue: Proceedings of the 2nd international conference on Supercomputing (1988)

An iterative method for the solution of nonsymmetric linear systems of equations is described and tested. The method, block symmetric successive over-relaxation with conjugate gradient acceleration (BSSOR), is remarkably robust and when applied to block tridiagonal systems allows parallelism in the computations. BSSOR compares favorably to unpreconditioned conjugate gradient-like algorithms in efficiency, and although generally slower than preconditioned methods it is far more reliable. The concept behind BSSOR can, in general, be applied to sparse linear systems (even if they are singular), sparse nonlinear systems of equations and least squares problems.
Linearising nonlinear recursions in polynomial time
Authors: Y. P. Saraiya
Venue: Proceedings of the eighth ACM SIGACT-SIGMOD-SIGART symposium on Principles of database systems (1989)

The replacement of nonlinear recursions with equivalent linear recursions is a potentially useful query optimization strategy, since it permits the use of efficient algorithms for the evaluation of linear logic programs. We show that a member of a certain class of bilinear recursions is linearizable in a strong sense if and only if a specific partial proof tree derived from this recursion is contained in a bounded number of partial proof trees generated by the recursion. Further, while each such test of containment between proof trees involves an exponential number of conjunctive-query containment tests, we present syntactic conditions on the recursion that are necessary and sufficient for the containment and verifiable in polynomial time.
Multinomial conjunctoid statistical learning machines
Authors: Y. Takefuji, R. Jannarone, Y. B. Cho, T. Chen
Venue: ACM SIGARCH Computer Architecture News (1988)

Multinomial Conjunctoids are supervised statistical modules that learn the relationships among binary events. The multinomial conjunctoid algorithm precludes the following problems that occur in existing feedforward multi-layered neural networks: (a) existing networks often cannot determine underlying neural architectures, for example how many hidden layers should be used, how many neurons in each hidden layer are required, and what interconnections between neurons should be made; (b) existing networks cannot avoid convergence to suboptimal solutions during the learning process; (c) existing networks require many iterations to converge, if at all, to stable states; and (d) existing networks may not be sufficiently general to reflect all learning situations. By contrast, multinomial conjunctoids are based on a well-developed statistical decision theory framework, which guarantees that learning algorithms will converge to optimal learning states as the number of learning trials increases, and that convergence during each trial will be very fast. In this paper a prototype multinomial conjunctoid circuit based on CMOS VLSI technology is described.
Variance reduction of quantile estimates via nonlinear control
Authors: P. A. W. Lewis, R. L. Ressler
Venue: Proceedings of the 21st conference on Winter simulation (1989)

Linear controls are a well known technique for achieving variance reduction in computer simulation. Unfortunately the effectiveness of a linear control depends upon the correlation between the statistic of interest and the control which is often low. Since statistics are often nonlinear functions of the control this implies that nonlinear controls offer a means for improvement over linear controls. Nonlinear controls have had success in increasing the variance reduction over a linear control. This current work focuses on the use of nonlinear controls for reducing the variance of quantile estimates. The paper begins with a short discussion of linear controls. It describes nonlinear controls and the possibility for improved performance. The final sections discuss quantiles as controls and the potential of nonlinear controls for variance reduction in quantile estimation.
Optimal scheduling policies for mixed scalar-vector multiprocessor supercomputers
Authors: Y. Liu, O. Johnson
Venue: Proceedings of the 1988 ACM/IEEE conference on Supercomputing (1988)

A queueing network model is developed for multiprocessing supercomputer systems implemented on two heterogeneous processors which are thought of as a scalar unit and a vector unit which work concurrently on a single process. The model is analysed theoretically for a representative case of model job mixes. It is found that the utilization of one of the two central service stations in the model can only be maximized at the expense of minimizing the utilization of the other central service station. The method of analysis adopted is the technique of variable aggregation based on nearly complete decomposability.
On-the-fly detection of access anomalies
Authors: D. Schonberg
Venue: ACM SIGPLAN Notices (1989)

Access anomalies are a common class of bugs in shared-memory parallel programs. An access anomaly occurs when two concurrent execution threads both write (or one thread reads and the other writes) the same shared memory location without coordination. Approaches to the detection of access anomalies include static analysis, post-mortem trace analysis, and on-the-fly monitoring. A general on-the-fly algorithm for access anomaly detection is presented, which can be applied to programs with both nested fork-join and synchronization operations. The advantage of on-the-fly detection over post-mortem analysis is that the amount of storage used can be greatly reduced by data compression techniques and by discarding information as soon as it becomes obsolete. In the algorithm presented, the amount of storage required at any time depends only on the number V of shared variables being monitored and the number N of threads, not on the number of synchronizations. Data compression is achieved by the use of two techniques called merging and subtraction. Upper bounds on storage are shown to be V &times; N2 for merging and V &times; N for subtraction.
Faster algorithms for the shortest path problem
Authors: Ravindra K. Ahuja, Kurt Mehlhorn, James Orlin, Robert E. Tarjan
Venue: Journal of the ACM (JACM) (1990)

Efficient implementations of Dijkstra's shortest path algorithm are investigated. A new data structure, called the radix heap, is proposed for use in this algorithm. On a network with n vertices, m edges, and nonnegative integer arc costs bounded by C, a one-level form of radix heap gives a time bound for Dijkstra's algorithm of O(m + n log C). A two-level form of radix heap gives a bound of O(m + n log C/log log C). A combination of a radix heap and a previously known data structure called a Fibonacci heap gives a bound of O(m + na @@@@log C). The best previously known bounds are O(m + n log n) using Fibonacci heaps alone and O(m log log C) using the priority queue structure of Van Emde Boas et al. [ 17].
A Study of Two Approaches for Reconfiguring Fault-Tolerant Systolic Arrays
Authors: Clement W. Lam, Hon F. Li, R. Jayakumar
Venue: IEEE Transactions on Computers (1989)

Presents a critical study of two approaches, the classical RC-cut approach and H.T. Kung and M.S. Lam's (Proc. 1984 MIT Conf. Advanced Res. VLSI p.74-83, 1984) RCS-cut approach, for reconfiguring faulty systolic arrays. The amount of cell (processing element) redundancy needed to ensure successful reconfiguration into an n*n array is considered. It is shown that no polynomial bounded redundancy is sufficient for the classical approach, whereas O(n/sup 2/log n) redundancy is sufficient for the Kung and Lams approach. The number of faulty cells that can be tolerated in a given array regardless of their locations is characterized and derived. It is shown that, for both approaches, in almost all cases a square array has better fault tolerance than a rectangular array having the same number of cells. A minimal fault pattern in a 2n*2n array with 3n+1 faults that is not reconfigurable into an n*n array using either of the two approaches is established.
SPAM: a microcode based tool for tracing operating sytsem events
Authors: S. Melvin, Y. Patt
Venue: ACM SIGMICRO Newsletter (1988)

We have developed a tool called SPAM (for System Performance Analysis using Microcode), based on microcode modifications to a VAX 8600, that traces operating system events as a side-effect to normal execution. This trace of interrupts, exceptions, system calls and context switches can then be processed to analyze operating system behavior for the purpose of debugging, tuning or development. SPAM allows measurement to be made on a fully operating UNIX system with little perturbation (typically less than 10%) and without the need for modifying the kernel.
The Design of a Testable Parallel Multiplier
Authors: Sung Je Hong
Venue: IEEE Transactions on Computers (1990)

A scheme for an easily testable multiplier and the corresponding test generation procedures are presented. To provide 100% controllability of the summand-counter, the summand-generator is modified. The modified summand-generator can be implemented with little hardware overhead. Since the summands are 100% controllable, the summand-counter can be constructed with the minimum number of adder cells. The multiplier is not C-testable, but can be tested with a small numbers of test vectors, i.e. 3n+60 vectors. It requires only one extra input, whereas C-testable multipliers usually require at least four or five extra inputs and more adder cells along with extra circuitry. Using the modified summand-generator, other types of multipliers can be easily constructed to be testable with only one extra input. Test sets for these multipliers can be obtained using the same test generation approach.
Instruction Issue Logic for High-Performance, Interruptible, Multiple Functional Unit, Pipelined Computers
Authors: Gurindar S. Sohi
Venue: IEEE Transactions on Computers (1990)

The problems of data dependency resolution and precise interrupt implementation in pipelined processors are combined. A design for a hardware mechanism that resolves dependencies dynamically and, at the same time, guarantees precise interrupts is presented. Simulation studies show that by resolving dependencies the proposed mechanism is able to obtain a significant speedup over a simple instruction issue mechanism as well as implement precise interrupts.
Experiments on incorporating syntactic processing of user queries into a document retrieval strategy
Authors: A. F. Smeaton, C. J. van Rijsbergen
Venue: Proceedings of the 11th annual international ACM SIGIR conference on Research and development in information retrieval (1988)

Traditional information has relied on the extensive use of statistical parameters in the implementation of retrieval strategies. This paper sets out to investigate whether linguistic processes can be used as part of a document retrieval strategy. This is done by predefining a level of syntactic analysis of user queries only, to be used as part of the retrieval process. A large series of experiments on an experimental test collection are reported which use a parser for noun phrases as part of the retrieval strategy. The results obtained from the experiments do yield improvements in the level of retrieval effectiveness and given the crude linguistic process used and the way it was used on queries and not on document texts, suggests that the approach of using linguistic processing in retrieval, is valid.
Squeezing more CPU performance out of a Cray-2 by Vector block scheduling
Authors: C. Eisenbeis, W. Jalby, A. Lichnewsky
Venue: Proceedings of the 1988 ACM/IEEE conference on Supercomputing (1988)

Compile time scheduling of vector activities on the CRAY 21 is studied using a simplified model of the vector instruction stream. Due to several of the hardware characteristics of the machine, an approach using much know-how obtained on Array-Processor micro-code scheduling by the authors is shown practical. It calls for a pass of loop scheduling followed by a pass of resource allocation. Actual benchmarks of the resulting code are shown, exhibiting speed-ups as large as 50% over the current CFT77 compiler. Our results also give a new perspective in the comparison of vector chaining and non-chaining processor architectures.
The Effect of Execution Policies on the Semantics and Analysis of Stochastic Petri Nets
Authors: M. A. Marsan, G. Balbo, A. Bobbio, G. Chiola, G. Conte, A. Cumani
Venue: IEEE Transactions on Software Engineering (1989)

Petri nets in which random delays are associated with atomic transitions are defined in a comprehensive framework that contains most of the models already proposed in the literature. To include generally distributed firing times into the model one must specify the way in which the next transition to fire is chosen, and how the model keeps track of its past history; this set of specifications is called an execution policy. A discussion is presented of the impact that different execution policies have on semantics of the mode, as well as the characteristics of the stochastic process associated with each of these policies. When the execution policy is completely specified by the transition with the minimum delay (race policy) and the firing distributions are of the phase type, an algorithm is provided that automatically converts the stochastic process into a continuous time homogeneous Markov chain. An execution policy based on the choice of the next transition to fire independently of the associated delay (preselection policy) is introduced, and its semantics is discussed together with possible implementation strategies.
Average interconnection length and interconnection distribution based on rent's rule
Authors: C. V. Gura, J. A. Abraham
Venue: Proceedings of the 26th ACM/IEEE Design Automation Conference (1989)

In this paper we show that it is necessary to utilize different partitioning coefficients in interconnection length analyses which are based on Rent's rule, depending on whether one- or two-dimensional placement strategies are used. &bgr;, the partitioning coefficient in the power-law relationship &agr;&Bgr;&bgr;, provides a measure of the number of interconnections which cross a boundary enclosing &Bgr; blocks. The partitioning coefficients are &bgr;=p/2 and &bgr;=p for two- and one-dimensional arrays, respectively, where p is the experimental coefficient of the Rent relationship T=&agr;&Bgr;p. Based on these separate partitioning coefficients, an average interconnection length prediction is presented for rectangular arrays that outperforms existing predictions. Examples are given to support this theory.
Comparing representations with relational and EER models
Authors: D. Batra, J. A. Hoffler, R. P. Bostrom
Venue: Communications of the ACM (1990)

The diffusion of technology to end users who can now develop their own information systems raises issues concerning the cost, quality, efficiency, and accuracy of such systems.
Can computers cope with human races?
Authors: L. Earnest
Venue: Communications of the ACM (1989)

In trying to apply a computer to a task that humans do, we often discover that it doesn't work. One common problem is that humans are able to deal with fuzzy concepts, but computers are not&mdash;they need precise representations and it is hard to represent a fuzzy concept in a precise way. However, if we look closer at such tasks, we often discover that the weakness actually lies not in the computer but in ourselves&mdash;that we didn't understand what we were doing in the first place. When faced with a problem of this sort, some people refuse to recognize the conceptual failure. Instead of seeking a better representation for the task, they thrash away at making the fuzzy scheme work, insisting that there is nothing wrong with the conceptual base. I will illustrate one such problem with a true story. The central theme is the fuzzy concept of racial and ethnic classification, as used by the U.S. government and a horde of other bureaucracies. These organizations have been carrying out elaborate statistical computations and making major policy decisions based on this concept for many years with problematical results. I begin with my first encounter with this scheme, some 25 years ago.
A VHDL compiler based on attribute grammar methodology
Authors: R. Farrow, A. G. Stanculescu
Venue: ACM SIGPLAN Notices (1989)

This paper presents aspects of a compiler for a new hardware description language (VHDL) written using attribute grammar techniques. VHDL is introduced, along with the new compiler challenges brought by a language that extends an Ada subset for the purpose of describing hardware. Attribute grammar programming solutions are presented for some of the language challenges. The organization of the compiler and of the target virtual machine represented by the simulation kernel are discussed, and performance and code-size figures are presented. The paper concludes that attribute grammars can be used for large commercial compilers with excellent results in terms of rapid development time and enhanced maintainability, and without paying any substantial penalty in terms of either the complexity of the language that can be handled or the resulting compilation speed.
A Case for Direct-Mapped Caches
Authors: Mark D. Hill
Venue: Computer (1988)

Direct-mapped caches are defined, and it is shown that trends toward larger cache sizes and faster hit times favor their use. The arguments are restricted initially to single-level caches in uniprocessors. They are then extended to two-level cache hierarchies. How and when these arguments for caches in uniprocessors apply to caches in multiprocessors are also discussed.
Constructing the vertex-transitive graphs of order 24
Authors: Gordon F. Royle, Cheryl E. Praeger
Venue: Journal of Symbolic Computation (1989)

This paper describes the construction of all the vertex-transitive graphs on 24 vertices, thus extending the currently available catalogues. This construction differes significantly from previous constructions of the vertex-transitive graphs of order up to 23 in that we are forced to use far more sophisticated group-theoretic techniques. We include an analysis of all the symmetric graphs on 24 vertices.
The Join Algorithms on a Shared-Memory Multiprocessor Database Machine
Authors: G. Z. Qadah, K. B. Irani
Venue: IEEE Transactions on Software Engineering (1988)

The authors develop and present a large set of parallel algorithms for implementing the join operation on a shared-memory multiprocessor database machine. The development of these algorithms follows a structured approach. The major steps involved in the processing of the join operation by the machine are first identified. Then, alternative join algorithms are constructed by concatenating the different ways of performing these steps. A study of the performance of the proposed algorithms is presented. This study shows, among other things, that for a given hardware configuration there is not just one overall best performing join algorithm, but rather different algorithms score the best performance, depending on the characteristics of the data participating in the join operation.