ppxscal/embedding_network huggingface dataset:
A Fast and Robust Network Bisection Algorithm
Authors: Youssef G. Saab
Venue: IEEE Transactions on Computers (1995)

Partitioning is a fundamental problem in diverse fields of study such as pattern recognition, parallel processing, and the design of VLSI circuits. Recently, node clustering or compaction has been shown to enhance the performance of iterative partitioning algorithms by several authors. However, clustering has been mainly used as a preprocessing step before partitioning in existing methods. This paper describes a technique to extract clusters using information collected during a pass of an iterative exchange algorithm. Alternative approaches for the implementation of this new clustering technique are discussed, and one such approach is chosen to be incorporated in a modified Fiduccia-Mattheyses algorithm based on a tradeoff between run time and performance. The resulting algorithm, BISECT, performs well in comparison with variants of the Kernighan-Lin algorithm including the Fiduccia-Mattheyses algorithm, local approaches, and simulated annealing on a wide variety of real and randomly generated benchmarks. BISECT is also used to find small vertex separators, and its results are compared with previous methods on several benchmarks. The empirical results show that BISECT is stable and is not very sensitive to the initial partition. Under suitably mild assumptions, BISECT can be shown to run in linear time. The empirical results confirm the speed of BISECT which can partition very large graphs (12,598 nodes and 91,961 edges) in less than six minutes of CPU time on a Sun Sparc 1+ workstation.
The Use of Three- and Four-Dimensional Surface Harmonics for Rigid and Nonrigid Shape Recovery and Representation
Authors: Art Matheny, Dmitry B. Goldgof
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1995)

The use of spherical harmonics for rigid and nonrigid shape representation is well known. This paper extends the method to surface harmonics defined on domains other than the sphere and to four-dimensional spherical harmonics. These harmonics enable us to represent shapes which cannot be represented as a global function in spherical coordinates, but can be in other coordinate systems. Prolate and oblate spheroidal harmonics and cylindrical harmonics are examples of surface harmonics which we find useful. Nonrigid shapes are represented as functions of space and time either by including the time-dependence as a separate factor or by using four-dimensional spherical harmonics. This paper compares the errors of fitting various surface harmonics to an assortment of synthetic and real data samples, both rigid and nonrigid. In all cases we use a linear least-squares approach to find the best fit to given range data. It is found that for some shapes there is a variation among geometries in the number of harmonics functions needed to achieve a desired accuracy. In particular, it was found that four-dimensional spherical harmonics provide an improved model of the motion of the left ventricle of the heart.
Point Counterpoint: What's the Proper Role for CASE Tools?
Authors: Alan Chmura, Henry David Crockett
Venue: IEEE Software (1995)

Point:Alan Chmura, CASE Associates¿ Proper use of CASE tools can and does significantly improve developer productivity and yield high-quality systems. Appropriate management, methods, techniques, and tools contribute to successes every day. When the input mix is right, quality software results, regardless of language, discipline, organization size or type, or the use of internal or external developers. Counterpoint:Henry David Crockett, Portland State University¿As they are currently applied, CASE tools seldom improve productivity or quality. This failure is based on faulty expectations: Many IS managers assume that CASE is a software solution to all development problems. Management understanding and support are key to the proper implementation of CASE. Management must select and apply methods the CASE tool supports and train developers in those methods.
250-MHz Advanced Test Systems
Authors: Algirdas J. Gruodis, Dale E. Hoffman
Venue: IEEE Design Test (1988)

New generations of electronic chips bring with them the promise of more capacity, storage, and speed. They also bring new challenges to design, test and manufacturing. A look at a series of advanced test systems, how they were designed and why, sheds new light on this practical side of advanced technology. These test systems are the ATS series from IBM.
Substitution Deciphering Based on HMMs with Applications to Compressed Document Processing
Authors: Dar-Shyang Lee
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (2002)

It has been shown that simple substitution ciphers can be solved using statistical methods such as probabilistic relaxation. However, the utility of such solutions has been limited by their inability to cope with noise encountered in practical applications. In this paper, we propose a new solution to substitution deciphering based on hidden Markov models. We show that our algorithm is more accurate than relaxation and much more robust in the presence of noise, making it useful for applications in compressed document processing. Recovering character interpretations from the sequence of cluster identifiers in a symbolically compressed document can be treated as a cipher problem. Although a significant amount of noise is present in the cluster sequence, enough information can be recovered with a robust deciphering algorithm to accomplish certain document analysis tasks. The feasibility of this approach is demonstrated in a multilingual document duplicate detection system.
Foreword
Authors: E. D. Lazowska, K. C. Sevcik
Venue: IEEE Transactions on Computers (1989)

No abstract availavle.
Optimal Multicast Communication in Wormhole-Routed Torus Networks
Authors: David F. Robinson, Philip K. McKinley, Betty H. C. Cheng
Venue: IEEE Transactions on Parallel and Distributed Systems (1995)

This paper presents efficient algorithms that implement one-to-many, or multicast, communication in wormhole-routed torus networks. By exploiting the properties of the switching technology and the use of virtual channels, a minimum-time multicast algorithm is presented for n-dimensional torus networks that use deterministic, dimension-ordered routing of unicast messages. The algorithm can deliver a multicast message to m - 1 destinations in $\lceil {\bf log_2} \, {\mbi m} \rceil$ message-passing steps, while avoiding contention among the constituent unicast messages. Performance results of a simulation study on torus networks with up to 4096 nodes are also given.
Current Approaches to Handling Imperfect Information in Data and Knowledge Bases
Authors: Simon Parsons
Venue: IEEE Transactions on Knowledge and Data Engineering (1996)

This paper surveys methods for representing and reasoning with imperfect information. It opens with an attempt to classify the different types of imperfection that may pervade data, and a discussion of the sources of such imperfections. The classification is then used as a framework for considering work that explicitly concerns the representation of imperfect information, and related work on how imperfect information may be used as a basis for reasoning. The work that is surveyed is drawn from both the field of databases and the field of artificial intelligence. Both of these areas have long been concerned with the problems caused by imperfect information, and this paper stresses the relationships between the approaches developed in each.
Feature Selection via Discretization
Authors: Huan Liu, Rudy Setiono
Venue: IEEE Transactions on Knowledge and Data Engineering (1997)

Discretization can turn numeric attributes into discrete ones. Feature selection can eliminate some irrelevant and/or redundant attributes. Chi2 is a simple and general algorithm that uses the ¿2 statistic to discretize numeric attributes repeatedly until some inconsistencies are found in the data. It achieves feature selection via discretization. It can handle mixed attributes, work with multiclass data, and remove irrelevant and redundant attributes.
Buffer allocation in flow-shop-type production systems with general arrival and service patterns
Authors: Ming-Guang Huang, Pao-Long Chang, Ying-Chyi Chou
Venue: Computers and Operations Research (2002)

This study investigates the buffer allocation strategy of a flow-shop-type production system that possesses a given total amount of buffers and finite buffer capacity for each workstation as well as general interarrival and service times in order to optimize such system performances as minimizing work-in-process, cycle time and blocking probability, maximizing throughput, or their combinations. In theory, the buffer allocation problem is in itself a difficult NP-hard combinatorial optimization problem, it is made even more difficult by the fact that the objective function is not obtainable in closed form for interrelating the integer decision variables (i.e., buffer sizes) and the performance measures of the system. Therefore, the purpose of this paper is to present an effective design methodology for buffer allocation in the production system. Our design methodology uses a dynamic programming process along with the embedded approximate analytic procedure for computing system performance measures under a certain allocation strategy. Numerical experiments show that our design methodology can quickly and quite precisely seek out the optimal or sub-optimal allocation strategy for most production system patterns.
This Old House
Authors: Dan O'Day
Venue: IEEE Software (1998)

The construction metaphor provides a useful way to describe how software is built. The author adopts that metaphor to the development process, comparing the improvement of existing development processes to fixing up an old house. Pay attention to the basics first, he argues, and work on one thing at a time-this often proves more practical than starting from the ground up.
High-Speed Data Paths in Host-Based Routers
Authors: Simon Walton, Anne Hutton, Joe Touch
Venue: Computer (1998)

In networking today, host workstations are increasingly being used as routers. Host-based routers offer a number of ad-vantages, but they suffer from inefficient support for high-bandwidth interfaces. The authors' work has focused on the technology's major drawback-its inefficiency in supporting high-bandwidth interfaces. Their approach is to optimize packet processing by applying techniques that transfer packets directly among host interfaces, thus removing an extra data copy. This technique increases data throughput by 45 percent while reducing the host's CPU load. They found that peer-DMA forwarding can increase host-based router throughput by up to 45 percent, supporting bandwidths of 480 Mbps. Peer-DMA host-based forwarding requires network interface cards with substantial shared-memory resources, because packet queues are stored on the interfaces themselves, rather than in host RAM. The queuing algorithm remains in the host CPU, supporting advanced queue management. Current systems have limited packet processing. A combination of stream-lined forwarding algorithms and aggregate interrupt processing should further increase host-based capability. Moving some of the IP processing out to the NIC coprocessor may enable this. It is also apparent that as processor speeds increase, the advantages of peer-DMA will aid throughput for small packet sizes.
Branch Target Buffer Design and Optimization
Authors: C. H. Perleberg, A. J. Smith
Venue: IEEE Transactions on Computers (1993)

A branch target buffer (BTB) can reduce the performance penalty of branches in pipelined processors by predicting the path of the branch and caching information used by the branch. Two major issues in the design of BTBs that achieves maximum performance with a limited number of bits allocated to the BTB implementation are discussed. The first is BTB management. A method for discarding branches from the BTB is examined. This method discards the branch with the smallest expected value for improving performance; it outperforms the least recently used (LRU) strategy by a small margin, at the cost of additional complexity. The second issue is the question of what information to store in the BTB. A BTB entry can consist of one or more of the following: branch tag, prediction information, the branch target address, and instructions at the branch target. Various BTB designs, with one or more of these fields, are evaluated and compared.
Challenges in Cross-Development
Authors: Richard W. Earnshaw, Lee D. Smith, Kevin Welton
Venue: IEEE Micro (1997)

When the capabilities or usage of a hardware technology change qualitatively, the focal challenges of developing software for it change too. Such changes are reflected directly in what is required of development tools. We believe the focal challenges of developing software for the emerging generation of single-chip, deeply embedded, multi-processor systems will be debugging and simulation. In this article we discuss how Advanced RISC Machines is responding to the challenge of generating the collateral simulation models needed to turn a large integrated circuit layout component into a component for every stage of the design cycle. We describe our perceptions of how these challenges are being shaped by time-to-market pressure and the emergence of independent intellectual property providers and we hint at further blurring of the historical separation between hardware and software development.
Using Processor-Cache Affinity Information in Shared-Memory Multiprocessor Scheduling
Authors: M. S. Squiillante, E. D. Lazowska
Venue: IEEE Transactions on Parallel and Distributed Systems (1993)

In a shared-memory multiprocessor system, it may be more efficient to schedule a taskon one processor than on another if relevant data already reside in a particularprocessor's cache. The effects of this type of processor affinity are examined. It isobserved that tasks continuously alternate between executing at a processor andreleasing this processor due to I/O, synchronization, quantum expiration, or preemption.Queuing network models of different abstract scheduling policies are formulated, spanning the range from ignoring affinity to fixing tasks on processors. These models are solved via mean value analysis, where possible, and by simulation otherwise. An analytic cache model is developed and used in these scheduling models to include the effects of an initial burst of cache misses experienced by tasks when they return to a processor forexecution. A mean-value technique is also developed and used in the scheduling modelsto include the effects of increased bus traffic due to these bursts of cache misses. Onlya small amount of affinity information needs to be maintained for each task. Theimportance of having a policy that adapts its behavior to changes in system load isdemonstrated.
Interrupt Handling for Out-of-Order Execution Processors
Authors: H. C. Torng, M. Day
Venue: IEEE Transactions on Computers (1993)

Processors with multiple functional units, including the superscalars, achieve significant performance enhancement through low-level execution concurrency. In such processors, multiple instructions are often issued and definitely executed concurrently and out-of-order. Consequently, interrupt and exception handling becomes a vexing problem. The authors identify latency, cost, and performance degradation as factors that must be considered in evaluating the effectiveness of interrupt and exception handling schemes. They then briefly enumerate proposals and implementations for interrupt and exception handling on out-of-order execution processors. An efficient hardware mechanism, the instruction window (IW), and an approach which allows for precise, responsive, and flexible interrupt and exception handling are presented. The implementation of the IW is discussed. The design of an eight-cell IW has been carried out; it can work with a very short machine cycle time. A comparison of all interrupt and exception handling schemes for out-of-order execution processors is also presented.
A notion of non-interference for timed automata
Authors: Roberto Barbuti, Nicoletta De Francesco, Antonella Santone, Luca Tesei
Venue: Fundamenta Informaticae (2002)

The non-interference property of concurrent systems is a security property concerning the flow of information among different levels of security of the system. In this paper we introduce a notion of timed non-interference for real-time systems specified by timed automata. The notion is presented using an automata based approach and then it is characterized also by operations and equivalence between timed languages. The definition is applied to an example of a time-critical system modeling a simplified control of an airplane.
Seven More Myths of Formal Methods
Authors: Jonathan P. Bowen, Michael G. Hinchey
Venue: IEEE Software (1995)

In 1990, Anthony Hall published a seminal article that listed and dispelled seven myths about the nature and application of formal methods. Today -- five years and many successful applications later -- formal methods remain one of the most contentious areas of software-engineering practice. Despite 25 years of use, few people understand exactly what formal methods are or how they are applied. Many nonformalists seem to believe that formal methods are merely an academic exercise -- a form of mental masturbation that has no relation to real-world problems. The media's portrayal of formal methods does little to help the situation. In many "popular press" science journals, formal methods are subjected to either deep criticism or, worse, extreme hyperbole. Fortunately, today these myths are held more by the public and the computer-science community at large than by system developers. It is our concern, however, that new myths are being propagated, and more alarmingly, are receiving a certain tacit acceptance from the system-development community.Following Hall's lead, we address and dispel seven new myths about formal methods: Formal methods delay the development process; formal methods lack tools; formal methods replace traditional engineering design methods; formal methods only apply to software; formal methods are unnecessary; formal methods are not supported; and formal-methods people always use formal methods.
Strategies for resolving inter-class data conflicts in mixed real-time database systems
Authors: Kim-Yiu Lam, Tei-Wei Kuo, Tony S. H. Lee
Venue: Journal of Systems and Software (2002)

Although many efficient concurrency control protocols have been proposed for real-time database systems, they are mainly restricted for systems with a single type of real-time transactions or a mixed set of soft real-time and non-real-time transactions only. Their performance objective usually aims at the minimization of the number of missed deadlines of soft real-time transactions or to guarantee the deadline satisfaction of hard real-time transactions. So far, it is still lack of any good study on the design of concurrency control strategies for mixed real-time database systems (MRTDBS), which consist of both hard and soft real-time transactions, and together with non-real-time transactions. Due to the very different performance requirements of hard and soft real-time transactions, existing real-time concurrency control protocols may not be suitable to MRTDBS. In this paper, we propose strategies for resolving data conflicts between different types of transactions in an MRTDBS so that the performance requirements of each individual transaction type can be satisfied and, at the same time, the overall system performance can be improved. The performance of the proposed strategies is evaluated and compared with a real-time optimistic approach, which has been shown to give a better performance than the lock-based protocols for soft and firm real-time transactions.
Comments on "Hash-Based and Index-Based Join Algorithms for Cube and Ring Connected Multicomputers"
Authors: J. -Y. Tien, W. -P. Yang
Venue: IEEE Transactions on Knowledge and Data Engineering (1991)

The cost distributions of both the parallel hybrid-hash join and the parallel join-index join algorithms proposed in the above-named work are presented in more detail. The result shows that almost the entire relation may need to be retrieved from disk, though the join selectivity is low. A table of semi-join selectives and cube sizes is given to show the condition that the join-index method performs better than the hybrid-hash method, i.e., the really low selectivity for the join-index method. An error in one of the cost formulas is corrected, and a more efficient method on the final join in the join-index method is proposed.
A Complexity Analysis of a Smoothing Method Using CHKS-functions for Monotone Linear Complementarity Problems
Authors: Keisuke Hotta, Masatora Inaba, Akiko Yoshise
Venue: Computational Optimization and Applications (2000)

We consider the standard linear complementarity problem (LCP): Find (x, y) &isin; R2n such that y &equals; Mx + q, (x, y) &ge; 0 and xiyi &equals; 0 (i &equals; 1, 2, &hellip; , n), where M is an n &times; n matrix and q is an n-dimensional vector. Recently several smoothing methods have been developed for solving monotone and/or P0 LCPs. The aim of this paper is to derive a complexity bound of smoothing methods using Chen-Harker-Kanzow-Smale functions in the case where the monotone LCP has a feasible interior point. After a smoothing method is provided, some properties of the CHKS-function are described. As a consequence, we show that the algorithm terminates in O (\frac{\bar{\gamma}^{6}n}{\epsilon^6} \hbox{ log }\frac{\bar{\gamma}^2n}{\epsilon^2}) Newton iterations where \bar{\gamma} is a number which depends on the problem and the initial point. We also discuss some relationships between the interior point methods and the smoothing methods.
Generalized Hopfield Neural Network for Concurrent Testing
Authors: J. Ortega, A. Prieto, A. Lloris, F. J. Pelayo
Venue: IEEE Transactions on Computers (1993)

The use of generalized Hopfield neural networks in designing the checking circuitry of a concurrent testable circuit is discussed. The aliasing probability, a measure for evaluating the performance of the checking circuitry, is provided. It is shown how, by using spectral techniques based on the Reed-Muller transform, the aliasing probability can be expressed as a function of the Reed-Muller coefficients. Therefore, obtaining the checking circuitry means selecting a set of Reed-Muller spectral coefficients, with fewer elements than a given bound, that minimizes the aliasing probability. To apply the neural networks to design the checking circuitry for concurrent testing, the aliasing probability has been used as an energy function, and the Hopfield neural network has been modified to have an associated energy function with any type of polynomial dependence on the processor states.
Analysis of Stochastic Automata Algorithm for Relaxation Labeling
Authors: P. S. Sastry, M. A. L. Thathachar
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1994)

A parallel stochastic algorithm for relaxation labeling is analyzed. For the case of symmetric compatibility functions, it is proved that time algorithm will always converge to a consistent labeling.
Software and Privacy: Revising Orwell
Venue: IEEE Software (1993)

It is argued that employers frequently use computers as a surveillance device and a means to monitor almost every aspect of employee performance. Employers justify such conduct by asserting that this helps ensure job safety and workplace security, reduce costs and limit liability; and increase productivity, efficiency, and product quality. Taken too far, however, surveillance can make employees overstressed and anxious, ultimately hindering the employers' objectives. The use of impairment tests and computerized impairment tests are discussed. The privacy issues raised by computerized impairment tests are discussed.