ppxscal/embedding_network huggingface dataset:
A scalable architecture for multi-threaded JAVA applications
Authors: M. Mrva, K. Buchenrieder, R. Kress
Venue: Proceedings of the conference on Design, automation and test in Europe (1998)

The paper presents a scalable architecture for multi-threaded Java applications. Threads enable modeling of concurrent behavior in a more or less natural way. Thus threads give a migration path to multi-processor machines. The proposed architecture consists of multiple application-specific processing elements, each able to execute a single thread at one time. The architecture is evaluated by implementing a portable and scalable Java machine onto an FPGA board for demonstration.
Parallel phylogenetic inference
Authors: Quinn Snell, Michael Whiting, Mark Clement, David McLaughlin
Venue: Proceedings of the 2000 ACM/IEEE conference on Supercomputing (CDROM) (2000)

Recent advances in DNA sequencing technology have created large data sets upon which phylogenetic inference can be performed. However, current research is limited by the prohibitive time necessary to perform tree search on even a reasonably-sized data set. Some parallel algorithms have been developed but the biological research community does not use them because they do not trust the results from newly developed parallel software. This paper presents a new phylogenetic algorithm that allows existing, trusted phylogenetic software packages to be executed in parallel using the DOGMA parallel processing system. The results presented here indicate that data sets that currently take as much as 11 months to search using current algorithms, can be searched in as little as two hours using as few as eight processors. This reduction in the time necessary to complete a phylogenetic search allows new research questions to be explored in many of the biological sciences.
Recognition of Visual Activities and Interactions by Stochastic Parsing
Authors: Yuri A. Ivanov, Aaron F. Bobick
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (2000)

This paper describes a probabilistic syntactic approach to the detection and recognition of temporally extended activities and interactions between multiple agents. The fundamental idea is to divide the recognition problem into two levels. The lower level detections are performed using standard independent probabilistic event detectors to propose candidate detections of low-level features. The outputs of these detectors provide the input stream for a stochastic context-free grammar parsing mechanism. The grammar and parser provide longer range temporal constraints, disambiguate uncertain low-level detections, and allow the inclusion of a priori knowledge about the structure of temporal events in a given domain. To achieve such a system we: 1) provide techniques for generating a discrete symbol stream from continuous low-level detectors; 2) extend stochastic context-free parsing to handle uncertainty in the input symbol stream; 3) augment a run-time parsing algorithm to enforce intersymbol constraints such as requiring temporal consistency between primitives; and 4) extend the consistency filtering to maintain consistent multiobject interactions. We develop a real-time system and demonstrate the approach in several experiments on gesture recognition and in video surveillance. In the surveillance application, we show how the system correctly interprets activities of multiple, interacting objects.
Very-High Radix CORDIC Rotation Based on Selection by Rounding
Authors: Elisardo Antelo, Tomás Lang, Javier D. Bruguera
Venue: Journal of VLSI Signal Processing Systems (2000)

A very-high radix algorithm and implementation for CORDIC rotation in circular and hyperbolic coordinates is presented. The selection function consists of rounding the residual. It is shown that this assures convergence from the second iteration on. For the first iteration, the selection is done by table, using a lower radix than for the remaining iterations. The compensation of the variable scale factor is done by computing the logarithm of the scale factor and performing the compensation by an exponential. Estimations of the delay for 32-bit and 64-bit precision show a substantial speed up when compared to low radix implementations. The proposed algorithm is also compared with previously proposed very-high radix ones, and significant advantages are identified.
Storage utilization in a memory hierarchy when storage assignment is performed by a hashing algorithm
Authors: John G. Williams
Venue: Communications of the ACM (1971)

The utilization of storage is studied in a two-level memory hierarchy. The first storage level, which is the fast store, is divided into a number of storage areas. When an entry is to be filed in the hierarchy, a hashing algorithm will attempt to place the entry into one of these areas. If this particular area is full, then the entry will be placed into the slower second-level store, even though other areas in the first-level store may have space available. Given that N entries have been filed in the entire hierarchy, an expression is derived for the expected number of entries filed in the first-level store. This expression gives a measure of how effectively the first-level store is being used. By means of examples, storage utilization is then studied as a function of the hashing algorithm, the number of storage areas into which the first-level store is divided and the total size of the first-level store.
Are wires plannable?
Authors: Ralph H. J. M. Otten, Giuseppe S. Garcea
Venue: Proceedings of the 2001 international workshop on System-level interconnect prediction (2001)

A simple approach to global wire delays leads to the conclusion that within a few years interconnect is going to demand an overwhelming portion of the chip estate. In addition, memory-to-compute ratio for area is growing very fast. These observations are added to the already considerable set of arguments for breaking radically with traditional silicon design paradigms.
Comparing interfaces based on what users watch and do
Authors: Eric C. Crowe, N. Hari Narayanan
Venue: Proceedings of the 2000 symposium on Eye tracking research & applications (2000)

With the development of novel interfaces controlled through multiple modalities, new approaches are needed to analyze the process of interaction with such interfaces and evaluate them at a fine grain of detail. In order to evaluate the usability and usefulness of such interfaces, one needs tools to collect and analyze richly detailed data pertaining to both the process and outcomes of user interaction. Eye tracking is a technology that can provide detailed data on the allocation and shifts of users' visual attention across interface entities. Eye movement data, when combined with data from other input modalities (such as spoken commands, haptic actions with the keyboard and the mouse, etc.), results in just such a rich data on set. However, integrating, analyzing and visualizing multimodal data on user interactions remains a difficult task. In this paper we report on a first step toward developing a suite of tools to facilitate this task. We designed and implemented an Eye Tracking Analysis System that generates combined gaze and action visualizations from eye movement data and interaction logs. This new visualization allows an experimenter to see the visual attention shifts of users interleaved with their actions on each screen of a multi-screen interface. A pilot experiment on comparing two interfaces &mdash; a traditional interface and a speech-controlled one &mdash; to an educational multimedia application was carried out to test the utility of our tool.
The structure of yet another ALGOL compiler
Authors: H. Kanner, P. Kosinski, C. L. Robinson
Venue: Communications of the ACM (1965)

A high-speed &ldquo;top down&rdquo; method of syntax analysis which completely eliminates &ldquo;back-up&rdquo; of the source string has been implemented in a convenient macro-language. A technique of simulation at compile time of the use of a conventional run-time stack enables the generation of code for expressions which minimizes stores, fetches and stack-pointer motion at run time, while properly treating recursion and side effects of procedures. Block structure and recursion are handled without need for interpretive methods at run time. The &ldquo;context problem&rdquo; in the transmission to recursive procedures of parameters &ldquo;called by name&rdquo; is solved in a manner which permits the handling of the common cases of simple expressions and array identifiers with particular efficiency.
Comments on a paper by T.C. Chen and I.T. Ho
Authors: Alan Jay Smith
Venue: Communications of the ACM (1975)

Tien Chi Chen and Irving T. Ho in their paper &ldquo;Storage-Efficient Representation of Decimal Data&rdquo; [1] present a scheme for the compression of numbers stored in binary coded decimal (BCD) form. Their compression scheme involves coding two or three digits at a time in seven bit or ten bit fields and requires only permutations, deletions, and insertions for coding and decoding. We would like to briefly present some alternatives to their compression method and to discuss the relative advantages of these other methods.
Design of a LISP-based microprocessor
Authors: Guy Lewis Steele,  Jr., Gerald Jay Sussman
Venue: Communications of the ACM (1980)

We present a design for a class of computers whose &ldquo;instruction sets&rdquo; are based on LISP. LISP, like traditional stored-program machine languages and unlike most high-level languages, conceptually stores programs and data in the same way and explicitly allows programs to be manipulated as data, and so is a suitable basis for a stored-program computer architecture. LISP differs from traditional machine languages in that the program/data storage is conceptually an unordered set of linked record structures of various sizes, rather than an ordered, indexable vector of integers or bit fields of fixed size. An instruction set can be designed for programs expressed as trees of record structures. A processor can interpret these program trees in a recursive fashion and provide automatic storage management for the record structures. We discuss a small-scale prototype VLSI microprocessor which has been designed and fabricated, containing a sufficiently complete instruction interpreter to execute small programs and a rudimentary storage allocator.
The effects of filtered video on awareness and privacy
Authors: Michael Boyle, Christopher Edwards, Saul Greenberg
Venue: Proceedings of the 2000 ACM conference on Computer supported cooperative work (2000)

Video-based media spaces are designed to support casual interaction between intimate collaborators. Yet transmitting video is fraught with privacy concerns. Some researchers suggest that the video stream be filtered to mask out potentially sensitive information. While a variety of filtering techniques exist, they have not been evaluated for how well they safeguard privacy. In this paper, we analyze how a blur and a pixelize video filter might impact both awareness and privacy in a media space. Each filter is considered at nine different levels of fidelity, ranging from heavily applied filter levels that mask almost all information, to lightly applied filters that reveal almost everything. We examined how well observers of several filtered video scenes extract particular awareness cues: the number of actors; their posture (moving, standing, seated); their gender; the visible objects (basic to detailed); and how available people look (their busyness, seriousness and approachability). We also examined the privacy-preserving potential of each filter level in the context of common workplace activities. Our results suggest that the blur filter, and to a lesser extent the pixelize filter, have a level suitable for providing awareness information while safeguarding privacy.
An algorithm for the blocks and cutnodes of a graph
Authors: Keith Paton
Venue: Communications of the ACM (1971)

An efficient method is presented for finding blocks and cutnodes of an arbitrary undirected graph. The graph may be represented either (i) as an ordered list of edges or (ii) as a packed adjacency matrix. If w denotes the word length of the machine employed, the storage (in machine words) required for a graph with n nodes and m edges increases essentially as 2(m + n) in case (i), or n2/w in case (ii). A spanning tree with labeled edges is grown, two edges finally bearing different labels if and only if they belong to different blocks. For both representations the time required to analyze a graph on n nodes increases as n&ggr; where &ggr; depends on the type of graph, 1 &le; &ggr; &le; 2, and both bounds are attained. Values of &ggr; are derived for each of several suitable families of test graphs, generated by an extension of the web grammar approach. The algorithm is compared in detail with that proposed by Read for which 1 &le; &ggr; &le; 3.
Using multiplayer games to teach interprocess communication mechanisms
Authors: Donna S. Reese
Venue: ACM SIGCSE Bulletin (2000)

An advanced operating system (OS) course teaches students how the OS mechanisms that they have learned in OS I are implemented. Solaris and Windows NT are used to illustrate these implementations. This course covers the major aspects of OS functionality and addresses both OS design issues and user level programming issues. The area of inter-process communication is not conceptually difficult for students to grasp, but the actual implementation and use of these concepts requires some practice. For the past three years, the author has experimented with the use of multi-player games as a mechanism for teaching students these programming constructs. This paper reports on these experiences.
On the construction of a representative synthetic workload
Authors: K. Sreenivasan, A. J. Kleinman
Venue: Communications of the ACM (1974)

A general method of constructing a drive workload representative of a real workload is described. The real workload is characterized by its demands on the various system resources. These characteristics of the real workload are obtained from the system accounting data. The characteristics of the drive workload are determined by matching the joint probability density of the real workload with that of the drive workload. The drive workload is realized by using a synthetic program in which the characteristics can be varied by varying the appropriate parameters. Calibration experiments are conducted to determine expressions relating the synthetic program parameters with the workload characteristics. The general method is applied to the case of two variables, cpu seconds and number of I/O activities; and a synthetic workload with 88 jobs is constructed to represent a month's workload consisting of about 6000 jobs.
Mechanization of the curve fitting process: DATAN
Authors: Roger H. Simonsen, D. Louise Anketell
Venue: Communications of the ACM (1966)

A process for fitting a curve to approximate data and the problem it creates for the engineer-programmer is defined. An approach has also been defined and a system has been written for the SRU 1107 to mechanize a major portion of this process. The techniques developed to accomplish the mechanization are largely empirical, and are dependent for their information only on the actual data points.
Improving the aircraft design process using Web-based modeling and simulation
Authors: John A. Reed, Gregory J. Follen, Abdollah A. Afjeh
Venue: ACM Transactions on Modeling and Computer Simulation (TOMACS) (2000)

Designing and developing new aircraft systems is time-consuming and expensive. Computational simulation is a promising means for reducing design cycle times, but requires a flexible software environment capable of integrating advanced multidisciplinary and multifidelity analysis methods, dynamically managing data across heterogeneous computing platforms, and distributing computationally complex tasks. Web-based simulation, with its emphasis on collaborative composition of simulation models, distributed heterogeneous execution, and dynamic multimedia documentation, has the potential to meet these requirements. This paper outlines the current aircraft design process, highlighting its problems and complexities, and presents our vision of an aircraft design process using Web-based modeling and simulation.
Cooperative-Competitive Algorithms for Evolutionary Networks Classifying Noisy Digital Images
Authors: A. D. Brown, H. C. Card
Venue: Neural Processing Letters (1999)

We describe an efficient method of combining the global search of genetic algorithms (GAs) with the local search of gradient descent algorithms. Each technique optimizes a mutually exclusive subset of the network&lsquo;s weight parameters. The GA chromosome fixes the feature detectors and their location, and a gradient descent algorithm starting from random initial values optimizes the remaining weights. Three algorithms having different methods of encoding hidden unit weights in the chromosome are applied to multilayer perceptrons (MLPs) which classify noisy digital images. The fitness function measures the MLP classification accuracy together with the confidence of the networks.
Attacking the semantic gap between application programming languages and configurable hardware
Authors: Greg Snider, Barry Shackleford, Richard J. Carter
Venue: Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays (2001)

It is difficult to exploit the massive, fine-grained parallelism of configurable hardware with a conventional application programðming language such as C, Pascal or Java. The difficulty arises from the mismatch between the synchronous, concurrent processing capability of the hardware and the expressiveness of the lanðguage-the so-called "semantic gap." We attack this problem by using a programming model matched to the hardware's capabilities that can be implemented in any (unmodified) object-oriented lanðguage, and building a corresponding compiler. The result is appliðcation code that can be developed, compiled, debugged and executed on a personal computer using conventional tools (such as Visual C++ or Visual Cafe), and then recompiled without modifiðcation to the configurable hardware target. A straightforward C++ implementation of the Serpent encryption algorithm compiled with our compiler onto a Virtex XCV1000 FPGA yielded an implemenðtation that was smaller (3200 vs. 4502 CLBs) and faster (77 MHz vs. 38 MHz) than an independent VHDL implementation with the same degree of pipelining. A tuned version of the source yielded an implementation that ran at 95 MHz.
An algorithm for the construction of bounded-context parsers
Authors: Jacques Loeck
Venue: Communications of the ACM (1970)

An algorithm is described which accepts an arbitrary context-free grammar and constructs a bounded-context parser for it whenever such a parser exists. In the first part of the paper the definition of a context-free grammar and the working of a bounded-context parser are recalled. The notion of reduction class for a context-free grammar is then introduced and its connection with the structure of a bounded-context parser is indicated. Next, pushdown automata which generate the different reduction classes of a context-free grammar are defined. Finally, the algorithm is described; it essentially carries out an exhaustive study of all possible runs of the pushdown automata generating the reduction classes. In the second part, the utility of the algorithm is discussed in the light of the experience gained from its use in compiler design. The algorithm is claimed to be particularly useful in the simultaneous design of a language and a compiler for it.
Distance-Regular Graphs Related to the Quantum Enveloping Algebra of sl(2)
Authors: Brian Curtin, Kazumasa Nomura
Venue: Journal of Algebraic Combinatorics: An International Journal (2000)

We investigate a connection between distance-regular graphs and i>Uq(i>sl(2)), the quantum universal enveloping algebra of the Lie algebra i>sl(2). Let &Gamma; be a distance-regular graph with diameter i>d &ge; 3 and valency i>k &ge; 3, and assume &Gamma; is not isomorphic to the i>d-cube. Fix a vertex i>x of &Gamma;, and let {\cal T} = {\cal T} (i>x) denote the Terwilliger algebra of &Gamma; with respect to i>x. Fix any complex number i>q &notin; &lcub;0, 1, &minus;1&rcub;. Then {\cal T} is generated by certain matrices satisfying the defining relations of i>Uq(i>sl(2)) if and only if &Gamma; is bipartite and 2-homogeneous.
A paradigm shift to OOP has occurred&hellip;implementation to follow
Authors: William Mitchell
Venue: Proceedings of the fourteenth annual consortium on Small Colleges Southeastern conference (2000)

This paper reflects on the discussions concerning the first year programming sequence that have transpired at the last few national symposiums in Computer Science Education and at other computer education conferences in the past two years. Both paper and birds-of-a-feather sessions suggest that computer science educators are deep into the transition from the procedural to object approach as the preferred basis for the design and implementation of software. This transition has become evident in the introductory textbooks, but it is more evident in the struggles of a faculty that has grown up with structured programming and now has to overcome that deeply entrenched mind-set. The author reflects on the characteristics of this struggle by comparing it to academic worldview struggles that have been termed &ldquo;paradigm shifts.&rdquo; Such struggles have been studied in other scientific disciplines and the pattern observed there is emphasized in the author's interpretation of recent events in computer science education.
Optimal reorganization of distributed space disk files
Authors: K. Maruyama, S. E. Smith
Venue: Communications of the ACM (1976)

In most database organizations, the cost of accessing the database will increase due to structural changes caused by updates and insertions. By reorganizing the database, the access costs can be reduced. A basic problem is to establish the proper tradeoff between performance, storage costs, and reorganization costs. This paper considers the optimum points at which to reorganize a database. A disk file organization which allows for distributed free space is described. A cost function describing the excess costs due to physical disorganization is defined, and this function is minimized to obtain the optimum reorganization points. Numerical examples based on the characteristics of existing disk storage devices are given.
Using synthetic images to register real images with surface models
Authors: Berthold K. P. Horn, Brett L. Bachman
Venue: Communications of the ACM (1978)

A number of image analysis tasks can benefit from registration of the image with a model of the surface being imaged. Automatic navigation using visible light or radar images requires exact alignment of such images with digital terrain models. In addition, automatic classification of terrain, using satellite imagery, requires such alignment to deal correctly with the effects of varying sun angle and surface slope. Even inspection techniques for certain industrial parts may be improved by this means. We achieve the required alignment by matching the real image with a synthetic image obtained from a surface model and known positions of the light sources. The synthetic image intensity is calculated using the reflectance map, a convenient way of describing surface reflection as a function of surface gradient. We illustrate the technique using LANDSAT images and digital terrain models.
Novel technique for testing FPGAs
Authors: C. Metra, G. Mojoli, S. Pastore, D. Salvi, G. Sechi
Venue: Proceedings of the conference on Design, automation and test in Europe (1998)

This paper presents a novel technique for testing Field Programmable Gate Arrays (FPGAs), suitable to be used in case of frequent FPGA reuse and rapid dynamic modifiability of the implemented function.