ppxscal/embedding_network huggingface dataset:
Barycentric formulae for some optimal rational approximants involving Blaschke products
Authors: J.-P. Berrut
Venue: Computing (1990)

We want to approximate the value Lf of some bounded linear functional L (e.g., an integral or a function evaluation) for f&isin;H2 by a linear combination j=0najf j where fj:=fzj for some points zj in the unit disk and the numbers aj are to be chosen independent of fj. Using ideas of Sard, Larkin has shown that, for the error Lf-j=0najf j to be minimal, aj must be chosen such that j=0najf j=Lf&perp; for the rational function f&perp;z= j=0nk =0n1-z&d1; kzj/k =0n1-z&d1; kzlj zfj, in which ljz are the Lagrange polynomials. Evaluating f&perp; as given above requires O(n2) operations for every z. We give here formulae, patterned after the barycentric formulae for polynomial, trigonometric and rational interpolation, which permit the evaluation of f&perp; in O(n) operations for every z, once some weights (that are independent of z) have been computed. Moreover, we show that certain rational approximants introduced by F. Stenger (Math. Comp., 1986) can be interpreted as special cases of Larkin's interpolants, and are therefore optimal in the sense of Sard for the corresponding points. &mdash;Author's Abstract
Portable programming within a message-passing model: the FFT as an example
Authors: D. W. Walker
Venue: Proceedings of the third conference on Hypercube concurrent computers and applications - Volume 2 (1989)

This paper describes a portable programming environment for MIMD concurrent processors based on an object-oriented, message-passing paradigm. The basis of this environment is the Virtual Machine Loosely Synchronous Communication System (VMLSCS) which is designed to be used for loosely synchronous problems. VMLSCS is structured to make efficient use of hierarchical memory, and permits communication and calculation to be overlapped on certain concurrent processors. As an example, the use of VMLSCS in performing both one-dimensional and multi-dimensional fast Fourier transforms (FFTs) on concurrent multiprocessors is described. It is shown that all necessary interprocessor communication can be performed by a single routine, vm_index. Thus the construction of a portable concurrent FFT rests on the implementation of vm_index on the target machines. In the multi-dimensional algorithm a strip decomposition is applied to each of the directions in turn so that each of the FFTs performed in a particular direction are done in one processor. This allows fast sequential one-dimensional FFTs to be exploited. The implementation of vm_index on both homogeneous and inhomogeneous hypercubes, and shared memory multiprocessors is discussed.
A knowledge acquisition model with applications for requirements specification and definition
Authors: T. Kinoshita
Venue: Issue 108 (April 1989) (1989)

From a practical point of view, the knowledge acquisition task for developing knowledge-based systems may be viewed as a cooperative task between domain experts, knowledge engineers, and support systems (environments). Based on this perspective, a system called the Multi-Layered Knowledge Acquisition Model (MLKAM), has been proposed [1].
Micro-optimization of floating-point operations
Authors: W. J. Dally
Venue: ACM SIGARCH Computer Architecture News (1989)

This paper describes micro-optimization, a technique for reducing the operation count and time required to perform floating-point calculations. Micro-optimization involves breaking floating-point operations into their constituent micro-operations and optimizing the resulting code. Exposing micro-operations to the compiler creates many opportunities for optimization. Redundant normalization operations can be eliminated or combined. Also, scheduling micro-operations separately allows dependent operations to be partially overlapped. A prototype expression compiler has been written to evaluate a number of micro-optimizations. On a set of benchmark expressions operation count is reduced by 33% and execution time is reduced by 40%.
A view of academic computing in China
Authors: John E. Skelton
Venue: ACM SIGUCCS Newsletter (1989)

Early last summer I had the privilege of spending six weeks in the People's Republic of China. The visit was sponsored by the Chinese Provincial Universities Project which is funded by the World Bank. One of the purposes of the project is to improve the use of technology in the provincial universities. Thus I spent four weeks as the guest of Anhui University in Hefei, the capital of Anhui Provence. These observations are mine alone and do not represent the views of any other organization or individual. The information was gained by either direct observation or a little bit of research into existing information.
Oscillation amplitude considerations in frequency domain experiments
Authors: S. H. Jacobson
Venue: Proceedings of the 21st conference on Winter simulation (1989)

We present a discussion of the issues to consider when setting oscillation amplitudes in frequency domain experiments, with particular reference to gradient direction estimators.
Optimization of the traveling sequence of a &ldquo;pick and place" robot by simulating its operation as a traveling salesman problem
Authors: Dimitrios A. Andreou
Venue: Proceedings of the 21st annual symposium on Simulation (1988)

This paper presents an approach to a problem of practical concern to the optimum guidance of a robot of at least two degrees of freedom but which may also have a direct application in any scientific field where optimum and near optimum solutions for the traveling salesman problem is needed. It is shown that the optimization of the traveling pattern of a surface mounting robot constitutes a TSP. Thereafter, the developed technique is applied to generate the traveling sequence of the robot. Results of examples are presented to illustrate the developed method and its effect in increasing the robot's throughput. The examples are real word applications of printed circuit board population. The production line consists of picking up IC's and other components and placing them at preprogrammed places on a board.
Fractals for secondary key retrieval
Authors: C. Faloutsos, S. Roseman
Venue: Proceedings of the eighth ACM SIGACT-SIGMOD-SIGART symposium on Principles of database systems (1989)

In this paper we propose the use of fractals and especially the Hilbert curve, in order to design good distance-preserving mappings. Such mappings improve the performance of secondary-key- and spatial- access methods, where multi-dimensional points have to be stored on an 1-dimensional medium (e.g., disk). Good clustering reduces the number of disk accesses on retrieval, improving the response time. Our experiments on range queries and nearest neighbor queries showed that the proposed Hilbert curve achieves better clustering than older methods (&ldquo;bit-shuffling&rdquo;, or Peano curve), for every situation we tried.
Reduction of group constructions to point stabilizers
Authors: G. Cooperman, L. Finkelstein, E. Luks
Venue: Proceedings of the ACM-SIGSAM 1989 international symposium on Symbolic and algebraic computation (1989)

The construction of point stabilizer subgroups is a problem which has been studied intensively. [1, 4, 5, 10, 11, 12, 14] This work describes a general reduction of certain group constructions to the point stabilizer problem. Examples are given for the centralizer, the normal closure, and a restricted group intersection problem. For the normal closure problem, this work provides an alternative to current algorithms, which are limited by the need for repeated closures under conjugation. For the centralizer and restricted group intersection problems, one can use an existing point stabilizer sequence along with a recent base change algorithm [2] to avoid generating a new point stabilizer sequence. This reduces the time complexity by at least an order of magnitude. Algorithms and theoretical time estimates for the special case of a small base are also summarized. An implementation is in progress.
Multidimensional icons
Authors: Tyson R. Henry, Scott E. Hudson
Venue: ACM Transactions on Graphics (TOG) (1990)

Background: Direct manipulation interfaces, such as the Macintosh desktop, often represent objects with icons [l, 41. For example, text files are represented by icons. Selection of the icon invokes an editor to view the file it represents, thus the icon not only represents the text file but also represents a text editor used to view the text file. Each type of object is viewed by using a specific program. Diagram objects, for example, require a graphical editor to view. In a typical iconic interface, icons represent a single view of an object. While the single-view single-icon model has proven very intuitive and easy to use, some objects have more than one logical view [2]. Program code can be viewed as text by using a text editor, or it can be viewed as program code by a compiler. The machine code that corresponds to the program code can be thought of as another view, thus the execution of a program can be thought of as another view of program code. This paper describes a mechanism for grouping a set of icons that depict several views of a single object into one multidimensional icon. Multidimensional icons group sets of icons, each describing a unique view of an object, into a single entity. The individual icons are projected onto the sides of a simulated cube. There are two distinct advantages to using a cube instead of displaying all the icons in a menu. The first advantage is that since cubes are very familiar objects, it is a natural mental model to think of the faces of a cube as views of the entire cube&mdash;views of the actual object. The second advantage is that by allowing rotation of the cube, several icons representing views of an object are accessible using only a fraction of the screen space required to display all the icons.
Fortran 8X draft
Authors: Loren P. Meissner
Venue: ACM SIGPLAN Fortran Forum (1989)

Standard Programming Language Fortran. This standard specifies the form and establishes the interpretation of programs expressed in the Fortran language. It consists of the specification of the language Fortran. No subsets are specified in this standard. The previous standard, commonly known as "FORTRAN 77", is entirely contained within this standard, known as "Fortran 8x". Therefore, any standard-conforming FORTRAN 77 program is standard conforming under this standard. New features can be compatibly incorporated into such programs, with any exceptions clearly indicated in the text of this standard.
Simple Algorithms and Architectures for B-spline Interpolation
Authors: P. V. Sankar, L. A. Ferrari
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1988)

It is proved that the Toeplitz binary value matrix inversion associated with mth-order B-spline interpolation can be implemented using only 2(m+1) additions. Pipelined architectures are developed for real-time B-spline interpolation based on simple running average filters. It is shown that an ideal interpolating function, which is approximated by a truncated sinc function with M half cycles, can be implemented using B-splines with M+2 multiplies. With insignificant loss of performance, the coefficients at the knots of the truncated sinc function can be approximated using coefficients which are powers of two. The resulting implementation requires only M+4m+6 additions. It is believed that the truncated sinc function approximated by zero-order B-spline functions actually achieves the best visual performance.
The Test Engineer's Assistant: A Support Environment for Hardware Design for Testability
Authors: Jill J. Hallenbeck, James R. Cybrynski, Nick Kanopoulos, Tassos Markas, Nagesh Vasanthavada
Venue: Computer (1989)

A description is given of TEA (Test Engineer's Assistant), a CAD (computer-aided design) environment developed to provide the knowledge base and tools needed by a system designer for incorporating testability features into a design. TEA helps the designer meet the requirements of fault coverage and ambiguity group size. Fault coverage is defined as the percentage of faults that can be detected out of the population of all faults of a unit under test with a particular test set. An ambiguity group is defined as the smallest hardware entity in a given level of the system design hierarchy (that is, board, subsystem, and system) to which a fault can be isolated. The fault model considered throughout is the single stuck-at fault model. An example application of TEA is included.
Utilizing multilevel models and reasoning for diagnosis of a complex electro-mechanical system
Authors: John A. Smith, Gautam Biswas
Venue: Proceedings of the 2nd international conference on Industrial and engineering applications of artificial intelligence and expert systems - Volume 1 (1989)

A multi-level system which utilizes both an evidential and a qualitative model for diagnosing fault symptoms in complex electro-mechanical systems is presented. The operation of both models, enhancement by a historical database, and the global control strategy are all discussed. In addition, the constraining of qualitative reasoning with information from the evidential session and the enhancement of the evidential model with information from the qualitative model is demonstrated.
A Hybrid Monitor for Behavior and Performance Analysis of Distributed Systems
Authors: Dieter Haban, Dieter Wybranietz
Venue: IEEE Transactions on Software Engineering (1990)

The authors describe a hybrid monitor for measuring the performance and observing the behavior of distributed systems during execution. They emphasize data collection, analysis and presentation of execution data. A special hardware support, which consists of a test and measurement processor (TMP), was designed and has been implemented in the nodes of experimental multicomputer system consisting of eleven nodes. The operations of the TMP are completely transparent with a minimal, less than 0.1%, overhead to the measured system. In the experimental system, all the TMPs were connected with a central monitoring station, using an independent communication network, in order to provide a global view of the monitored system. The central monitoring station displayed the resulting information in easy-to-read charts and graphs. Experience with the TMP shows that it promotes an improved understanding of run-time behavior and performance measurements, which aids in deriving qualitative and quantitative assessments of distributed systems.
Automated circuit diagnosis using first order logic tools
Authors: Barbara Smith, Ralph Wilkerson, Gerald E. Peterson
Venue: Proceedings of the 1st international conference on Industrial and engineering applications of artificial intelligence and expert systems - Volume 1 (1988)

While numerous diagnostic expert systems have been successfully developed in recent years, they are almost uniformly based on heuristic reasoning techniques (i.e., shallow knowledge) in the form of rules. This paper reports on an automated circuit diagnostic tool based on Reiter's theory of diagnosis. In particular, this is a theory of diagnosis based on deep knowledge (i.e., knowledge based on certain design information) and using first order logic as the representation language. The inference mechanism which is incorporated as part of the diagnostic tool is a refutation based theorem prover using rewriting systems for Boolean algebra developed by Hsiang. Consequently, the diagnostic reasoning tool is broadly based on Reiter's model, but incorporates complete sets of reductions for Boolean algebra to reason over equational descriptions of the circuits to be analyzed. The refutational theorem prover uses an associative commutative identity unification algorithm described by Hsiang, but requires additional focusing techniques in order to be appropriate for diagnosing circuits. A prototype version of the mainline diagnostic program has been developed, and has been successfully demonstrated on several small but nontrivial combinational circuit examples.
Efficient Algorithms for Reconfiguration in VLSI/WSI Arrays
Authors: V. P. Roychowdhury, Jehoshua Bruck, Thomas Kailath
Venue: IEEE Transactions on Computers (1990)

The issue of developing efficient algorithms for reconfiguring processor arrays in the presence of faulty processors and fixed hardware resources is discussed. The models discussed consist of a set of identical processors embedded in a flexible interconnection structure that is configured in the form of a rectangular grid. An array grid model based on single-track switches is considered. An efficient polynomial time algorithm is proposed for determining feasible reconfigurations for an array with a given distribution of faulty processors. In the process, it is shown that the set of conditions in the reconfigurability theorem is not necessary. A polynomial time algorithm is developed for finding feasible reconfigurations in an augmented single-track model and in array grid models with multiple-track switches.
Supervised Textured Image Segmentation Using Feature Smoothing and Probabilistic Relaxation Techniques
Authors: J. Y. Hsiao, A. A. Sawchuk
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1989)

A description is given of a supervised textured image segmentation algorithm that provides improved segmentation results. An improved method for extracting textured energy features in the feature extraction stage is described. It is based on an adaptive noise smoothing concept that takes the nonstationary nature of the problem into account. Texture energy features are first estimated using a window of small size to reduce the possibility of mixing statistics along region borders. The estimated texture energy feature values are smoothed by a quadrant filtering method to reduce the variability of the estimates while retaining the region border accuracy. The estimated feature values of each pixel are used by a Bayes classifier to make an initial probabilistic labeling. The spatial constraints are enforced through the use of a probabilistic relaxation algorithm. Two probabilistic relaxation algorithms are investigated. Limiting the probability labels by probability threshold is proposed. The tradeoff between efficiency and degradation of performed is studied.
A factorization algorithm for linear ordinary differential equations
Authors: F. Schwarz
Venue: Proceedings of the ACM-SIGSAM 1989 international symposium on Symbolic and algebraic computation (1989)

The reducibility and factorization of linear homogeneous differential equations are of great theoretical and practical importance in mathematics. Although it has been known for a long time that factorization is in principle a decision procedure, its use in an automatic differential equation solver requires a more detailed analysis of the various steps involved. Especially important are certain auxiliary equations, the so-called associated equations. An upper bound for the degree of its coefficients is derived. Another important ingredient is the computation of optimal estimates for the size of polynomial and rational solutions of certain differential equations with rational coefficients. Applying these results, the design of the factorization algorithm LODEF and its implementation in the Scratchpad II Computer Algebra System is described.
Distributing resources in hypercube computers
Authors: M. Livingston, Q. F. Stout
Venue: Proceedings of the third conference on Hypercube concurrent computers and applications: Architecture, software, computer systems, and general issues - Volume 1 (1988)

Given a type of resource such as disk units, extra memory modules, connections to the host processor, or software modules, we consider the problem of distributing the resource units to processors in a hypercube computer so that certain performance requirements are met at minimal cost. Typical requirements include the condition that every processor is within a given distance of a resource unit, that every processor is within a given distance of each of several resources, and that every m-dimensional subcube contains a resource unit. The latter is particularly important in a multiuser system in which different users are given their own subcubes. In this setting, we also consider the problem of meeting the performance requirements at minimal cost when the subcube allocation system cannot allocate all possible subcubes and the requirements apply only to allocable subcubes. We also analyze the problem of partitioning processors with resources into different classes, requiring that every processor is within a given distance of, or in a subcube of given dimension with, a member of each class. Efficient constructive techniques for distributing or partitioning a resource are given for several performance requirements, along with upper and lower bounds on the total number of resource units required.
The data model of the configuration management assistant (CMA)
Authors: E. Ploedereder, A. Fergany
Venue: ACM SIGSOFT Software Engineering Notes (1989)

In an environment in which systems are configured by reusing existing subsystems, the determination of complete and consistent configurations is a non-trivial and error-prone task, although considerable information about the subsystems may already be available from previous configurations. The Configuration Management Assistant is a tool that supports tracking and exploiting such information in the difficult process of re-configuration on a large scale. Its data model was designed to be as independent as possible of configuration management policies and procedures and yet provide substantive assistance in this process. The most important elements of this data model are described in this paper.1
A comprehensive mathematics curriculum for the computer science undergraduate program
Authors: A. Behforooz, O. P. Sharma
Venue: ACM SIGCSE Bulletin (1989)

Mathematics requirements for computer science majors have been discussed in many papers and panels during the last twenty years. This paper, while reexamining this issue, presents a comprehensive view of the total mathematics requirement for a computer science undergraduate program rather than discuss some course contents in a piecemeal fashion. The time distribution among different topics, the depth of the topics to be covered and the minimal qualifications of the intructor to teach the courses are also included.
On tuning the microarchitecture of an HPS implementation of the VAX
Authors: James E. Wilson, Steve Melvin, Michael Shebanow, Wen-Mei Hwu, Yale N. Patt
Venue: ACM SIGMICRO Newsletter (1988)

The HPS Microarchitecture has been developed as an execution model for implementing various architectures at very high performance. A considerable amount of effort has gone into the use of HPS as a microarchitecture for the VAX. In this paper, we describe our first full simulation of the micro VAX subset, and report the results of varying (i.e. tuning) certain important parameters.