ppxscal/embedding_network huggingface dataset:
A linear space algorithm for computing maximal common subsequences
Authors: D. S. Hirschberg
Venue: Communications of the ACM (1975)

The problem of finding a longest common subsequence of two strings has been solved in quadratic time and space. An algorithm is presented which will solve this problem in quadratic time and in linear space.
A Language for Array and Vector Processors
Authors: R. H. Perrott
Venue: ACM Transactions on Programming Languages and Systems (TOPLAS) (1979)

The scientific community has consistently demanded from computing machines an increase in the number of instructions executed per second. The latest increase has been achieved by duplication of arithmetic units for an array processor and the pipelining of functional units for vector processors. The high level programming languages for such machines have not benefited from the advances which have been made in programming language design and implementation techniques. A high level language is described in this paper which is appropriate for both array and vector processors and is defined without reference to the hardware of either type of machine. The syntax enables the parallel nature of a problem to be expressed in a form which can be readily exploited by these machines. This is achieved by using the data declarations to indicate the maximum extent of parallel processing and then to manipulate this, or a lesser extent, in the course of program execution. It was found to be possible to modify many of the structured programming and data structuring concepts for this type of parallel environment and to maintain the benefits of compile time and run time checking. Several special constructs and operators are also defined. The language offers to the large scale scientific computing community many of the advances which have been made in software engineering techniques while it exploits the architectural advances which have been made.
Effective use of boolean satisfiability procedures in the formal verification of superscalar and VLIW
Authors: Miroslav N. Velev, Randal E. Bryant
Venue: Proceedings of the 38th annual Design Automation Conference (2001)

We compare SAT-checkers and decision diagrams on the evalua-tion of Boolean formulas produced in the formal verification of both correct and buggy versions of superscalar and VLIW micro-processors. We identify one SAT-checker that significantly out-performs the rest. We evaluate ways to enhance its performance by variations in the generation of the Boolean correctness formu-las. We reassess optimizations previously used to speed up the formal verification and probe future challenges.
An auction agent for bidding on combinations of items
Authors: Yasuo Matsumoto, Satoru Fujita
Venue: Proceedings of the fifth international conference on Autonomous agents (2001)

This paper describes a way to obtain sub-optimal profits in bidding for combinations of goods that are on auction at different sites, and results for an autonomous agent that bids for goods according to the proposed strategy. The types of requirements for combinations are classified as complementary, substitutive and independent. For each type, this paper specifies the region in which bidding on goods will make a positive profit. A bidding strategy is then proposed for sequential auctions under the condition that the bids by the other participants in the auction can be represented by a probabilistic function. Two simulations were constructed to evaluate the proposed strategy. They indicated that the agent that applies the proposed strategy was superior to others that bid for combinations of goods according to simple and intuitive strategies. The simulations also indicated that the proposed strategy was the equilibrium strategy of those we tested, when two agents were simultaneously bidding for the same combination of goods.
Superlinear Convergence of an Interior-Point Method Despite Dependent Constraints
Authors: Daniel Ralph, Stephen J. Wright
Venue: Mathematics of Operations Research (2000)

We show that an interior-point method for monotone variational inequalities exhibits superlinear convergence provided that all the standard assumptions hold except for the well-known assumption that the Jacobian of the active constraints has full rank at the solution. We show that superlinear convergence occurs even when the constant-rank condition on the Jacobian assumed in an earlier work does not hold.
An approximate analysis of the shortest queue policy on soft real-time scheduling
Authors: Weiping Zhu
Venue: ACM SIGMETRICS Performance Evaluation Review (2000)

The join the shortest queue (JSQ) policy is studied in the context of soft real-time scheduling. An approximate analysis of the JSQ is developed and presented in this paper. The result obtained from the approximate analysis is compared against the simulation one, that shows the approximate analysis is highly accurate. Thus, the approximate analysis can be applied to the development of soft real-time systems.
The versatile list: a pathway to abstraction
Authors: John Hamer, Adriana Ferraro
Venue: Proceedings of the Australasian conference on Computing education (2000)

The humble &ldquo;list&rdquo; is usually presented early in a first course on data structures and algorithms, one topic among many, generally considered less interesting than trees and graphs. We believe the list deserves better, and show how the list can be used to bring together a wide variety of Computer Science topics, including: algebraic reasoning, proof by induction, abstract data types, recursion, and generic programming. The emphasis is on developing abstraction and design skills, applying both theory and engineering considerations, ultimately arriving at an unexpectedly powerful framework.
A statistical static timing analysis considering correlations between delays
Authors: Shuji Tsukiyama, Masakazu Tanaka, Masahiro Fukui
Venue: Proceedings of the 2001 Asia and South Pacific Design Automation Conference (2001)

In this paper, we present a new algorithm for the statistical static timing analysis of a CMOS combinatorial circuit, which can treat correlations of arrival times of input signals to a logic gate and correlations of switching delays in a logic gate. We model each switching delay by a normal distribution, and use a normal distribution of two stochastic variables with a coefficient of correlation for computing the distribution of output delay of a logic gate. Since the algorithm takes the correlation into account, the time complexity is O(n*m) in the worst-case, where n and m are the numbers of vertices and edges of the acyclic graph representing a given combinatorial circuit.
Probabilistic Analysis of Scheduling Precedence Constrained Parallel Tasks on Multicomputers with Contiguous Processor Allocation
Authors: Keqin Li, Yi Pan
Venue: IEEE Transactions on Computers (2000)

Given a set of precedence constrained parallel tasks with their processor requirements and execution times, the problem of scheduling precedence constrained parallel tasks on multicomputers with contiguous processor allocation is to find a nonpreemptive schedule of the tasks on a multicomputer such that the schedule length is minimized. This scheduling problem is substantially more difficult than other scheduling problems due to precedence constraints among tasks, the inherent difficulty of task scheduling, and processor allocation in multicomputers. We present an approximation algorithm called LLB that schedules tasks level-by-level using the largest-task-first strategy supported by the binary system partitioning scheme to handle the three difficult issues in our scheduling problem. Though algorithm LLB does not have a bounded worst-case performance ratio, we show through probabilistic analysis that LLB has a quite reasonable average-case performance ratio for typical classes of parallel computations. In particular, algorithm LLB has an average-case performance ratio less than two for large scale parallel computations that have wide task graphs (i.e., that exhibit large parallelism).
Simultaneous shield insertion and net ordering for capacitive and inductive coupling minimization
Authors: L. He, K. M. Lepak
Venue: Proceedings of the 2000 international conference on Computer-aided design (2001)

In this paper, we first show that existing net ordering formulations to minimize noise are no longer valid with presence of inductive noise, and shield insertion is needed to minimize inductive noise. We then formulate two simultaneous shield insertion and net ordering (SINO) problems: the optimal SINO/NF problem to find a min-area SINO solution that is free of capacitive and inductive noise, and the optimal SINO/NB problem to find a min-area SINO solution that is free of capacitive noise and is under the given inductive noise bound. We reveal that both optimal SINO problems are NP-hard, and propose effective approximate algorithms for the two problems. Experiments show that our SINO/NB algorithm uses from 15% to 57% fewer shield wires when compared to separated net ordering and shield insertion procedure. Furthermore, under practical noise bounds, the SINO/NB solutions use from 44% to 67% fewer shield wires when compared to SINO/NF solutions, and use 10% to 40% fewer shield wires when compared to the theoretical lower bound for optimal SINO/NF solutions. Additionally, all our algorithms are extremely efficient to finish all examples in a few seconds. To the best of our knowledge, it is the first work that presents an in-depth study on the simultaneous shield insertion and net ordering problem to minimize both capacitive and inductive noise.
Numerical Study of Flows of Two Immiscible Liquids at Low Reynolds Number
Authors: Jie Li, Yuriko Renardy
Venue: SIAM Review (2000)

We review our recent results on fingering, bamboo waves, and drop breakup in low Reynolds number flows composed of two viscous liquids under shear.
Compiler-directed shared-memory communication for iterative parallel applications
Authors: Guhan Viswanathan, James R. Larus
Venue: Proceedings of the 1996 ACM/IEEE conference on Supercomputing (CDROM) (1996)

Many scientific applications are iterative and specify repetitive communication patterns. This paper shows how a parallel-language compiler and custom cache-coherence protocols in a distributed shared memory system together can implement shared-memory communication efficiently for applications with unpredictable but repetitive communication patterns. The compiler uses data-flow analysis to identify program points where repetitive communication occurs. At runtime, the custom protocol builds communication schedules in one iteration and uses it to pre-send data in following iterations. This paper contains measurements on three iterative applications (including adaptive programs with unstructured data accesses) to show that custom protocols increase the number of shared-data requests satisfied locally, thus reducing the amount of time spent waiting for remote data.
Algorithms to Select IDDQ Measurement Vectors for Bridging Faults in Sequential Circuits
Authors: Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita
Venue: Journal of Electronic Testing: Theory and Applications (2000)

In order to reduce IDDQ testing time, it is important to reduce the number of IDDQ measurement vectors, because IDDQ measurement is a time-consuming process. For obtaining minimum number of IDDQ measurement vectors for sequential circuits, fault simulation needs to be performed without fault-dropping, thus requiring very high simulation time. In this paper we propose algorithms to select small number of IDDQ measurement vectors. The proposed algorithms can concurrently simulate multiple faults and use heuristics for selection of IDDQ measurement vectors to reduce simulation time. Experimental results are presented to demonstrate the effectiveness of the proposed method.
Multigrain shared memory
Authors: Donald Yeung, John Kubiatowicz, Anant Agarwal
Venue: ACM Transactions on Computer Systems (TOCS) (2000)

Parallel workstations, each comprising tens of processors based on shared memory, promise cost-effective scalable multiprocessing. This article explores the coupling of such small- to medium-scale shared-memory multiprocessors through software over a local area network to synthesize larger shared-memory systems. We call these systems Distributed Shared-memory MultiProcessors (DSMPs). This article introduces the design of a shared-memory system that uses multiple granularities of sharing, called MGS, and presents a prototype implementation of MGS on the MIT Alewife multiprocessor. Multigrain shared memory enables the collaboration of hardware and software shared memory, thus synthesizing a single transparent shared-memory address space across a cluster of multiprocessors. The system leverages the efficient support for fine-grain cache-line sharing within multiprocessor nodes as often as possible, and resorts to coarse-grain page-level sharing across nodes only when absolutely necessary. Using our prototype implementation of MGS, an in-depth study of several shared-memory application is conducted to understand the behavior of DSMPs. Our study is the first to comprehensively explore the DSMP design space, and teh compare the performance of DSMPs against all-software and all-hardware DSMs on a signle experimental platform. Keeping the total number of processors fixed, we show that applications execute up to 85% faster on a DSMP as compared to an all-software DSM. We also show that all-hardware DSMs hold a significant performance advantage over DSMPs on challenging applications, between 159% and 1014%. However, program transformations to improve data locality for these applications allow DSMPs to almost match the performance of an all-hardware multiprocessor of the same size.
Slicing concurrent java programs
Authors: Zhenqiang Chen, Baowen Xu
Venue: ACM SIGPLAN Notices (2001)

Program slicing is an important approach to testing, understanding and maintaining programs. The paper presents a slicing algorithm for concurrent Java programs. Because the execution process of concurrent programs is unpredictable, there are many problems to be solved when slicing. To slice concurrent Java programs, we present concurrent control flow graphs and concurrent program dependence graphs to representconcurrent Java programs. Based on these models, we design an efficient static slicing algorithm for concurrent Java programs. The algorithm may get more precise slices than previous approaches we know.
Component framework infrastructure for virtual environments
Authors: Manuel Oliveira, Jon Crowcroft, Mel Slater
Venue: Proceedings of the third international conference on Collaborative virtual environments (2000)

Virtual Environments (VE) present a complex problem with interesting non-trivial challenges for system development, in particular when the VE is distributed and shared amongst multiple participants. Most problems are common to any VE system, however the development effort is replicated because current systems are neither evolutionary nor allow integration of code across different systems. This paper presents the Java Adaptive Dynamic Environment (JADE), which consists of a light-weight cross-platform kernel with inherent capabilities for dynamic extensibility in run-time. This kernel is the embodiment of a component framework for the underlying infrastructure of VE systems, addressing the problems of evolution and integration.
Instruction translation for an experimental S/390 processor
Authors: Rolf Hilgendorf, Wolfram Sauer
Venue: ACM SIGARCH Computer Architecture News (2001)

The IBM trade; S/390 trade; architecture is a complex architecture, which has grown over a long period of time. Typical implementations use microcode to cope with the more complex instructions and facilities of S/390. Current IBM S/390 processors even contain two levels of microcode.We report on an experimental S/390 processor based on a RISC processor kernel employing superscalar, out of order execution of instructions. S/390 instructions have to be translated into internal sequences of RISC instructions. Actually two closely coupled internal sequences - one for register based execution and one for storage based execution are generated. The translation is a straight-forward mapping in most cases with some flexibility for special instructions.The paper introduces the hardware mechanisms used for mapping S/390 instructions to internal sequences. The facilities, which provide a greater degree of flexibility are discussed. The interactions of the low-level mapping scheme with the microcode levels is examined. Finally we discuss our experiences with this type of implementation of a CISC architecture on a RISC processor kernel.
Wait-Free Deflection Routing of Long Messages
Authors: Ludek Kucera
Venue: IEEE Transactions on Parallel and Distributed Systems (2001)

In order to obtain the lowest possible latency, routing algorithms should try to avoid a message waiting for resources (network links) blocked by other messages or multiplexing of more messages over one physical channel. This requirement becomes especially important in the case of long messages. The only type of protocols able to guarantee waiting free routing under heavy load are algorithms based on deflection (also called nonminimal adaptive or hot potato) routing. This paper deals with problems connected with the use of deflection algorithms. In contrast to the case of nonadaptive or partially (e.g., minimal) adaptive routing, it is very infrequent that an unrestricted deflection routing becomes deadlocked and, similarly, livelock is not a serious problem. On the other hand, there is another phenomenon, called a deflection jam, that limits throughput of deflection algorithms used to route long messages. It has been observed for many deflection heuristics, interconnection network topologies, and both virtual cut-through and wormhole routing. A deflection jam is a sudden and persistent saturation of a network which sometimes occur, after a very long period of undisturbed communication. This paper describes events that trigger this saturation which suggest ways to design improved and stable deflection routing algorithms.
Using the Ravenscar profile for space applications: the OBOSS case
Authors: Tullio Vardanega, Gert Caspersen
Venue: ACM SIGAda Ada Letters (2001)

The Ravenscar Profile emerged in 1997 as a most promising approach to bringing mature, predictable and efficient concurrency into real-time systems with integrity requirements. One of the crucial questions that have arisen since is whether the expressive power of the profile would be truly sufficient for the effective construction of such systems. This paper provides positive evidence to this effect by discussing the merit of the Ravenscar compliant architecture of a reuse library that supports the construction of on-board embedded real-time systems of the new generation. This paper argues that the notions of the profile especially contributed to increase the maturity of the reuse product. As true object orientation is the next frontier of the product, this paper also reflects on the importance of integrating the profile with suitable flavours of object orientation.
Self-Calibration of a 1D Projective Camera and Its Application to the Self-Calibration of a 2D Projective Camera
Authors: Olivier Faugeras, Long Quan, Peter Strum
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (2000)

We introduce the concept of self-calibration of a 1D projective camera from point correspondences, and describe a method for uniquely determining the two internal parameters of a 1D camera, based on the trifocal tensor of three 1D images. The method requires the estimation of the trifocal tensor which can be achieved linearly with no approximation unlike the trifocal tensor of 2D images and solving for the roots of a cubic polynomial in one variable. Interestingly enough, we prove that a 2D camera undergoing planar motion reduces to a 1D camera. From this observation, we deduce a new method for self-calibrating a 2D camera using planar motions. Both the self-calibration method for a 1D camera and its applications for 2D camera calibration are demonstrated on real image sequences.
Medical Resource Planning for Combat Operations: Utilizing Percentile Estimates as an Alternative to the Mean
Authors: James M. Zouris, Christopher G. Blood
Venue: Journal of Medical Systems (2000)

Forecasting medical resource requirements during combat operations is dependent upon reliable estimates of the anticipated patient load. Traditionally, mean patient load estimations are used to determine the medical resources and supplies. However, these approximations can underestimate the resources needed to treat casualties during certain peak periods of an operation. This paper discusses the use of percentile estimates in forecasting patient loads as an alternative to using measures of central tendency. To assist in providing alternative estimates of ground casualty rates, the SLICECAS model has been developed to compute the varying percentile estimates. Design and construction of the model is based on data and trends observed during previous combat operations.
A novel network node architecture for high performance and function flexibility
Authors: Takahiro Murooka, Atsushi Takahara, Toshiaki Miyazaki
Venue: Proceedings of the 2001 Asia and South Pacific Design Automation Conference (2001)

We developed a flexible network node that is tuned for high-speed and multilayer packet manipulation. The key idea is a dynamic function assignment mechanism; each packet processing task is assigned to several processing modules in an on-the-fly manner and incoming packets are processed in them. With this mechanism, we can freely arrange the modules and add extra ones if more processing power is needed. In addition, the processing modules are realized using field programmable gate arrays (FPGAs) and micro processing units (MPUs). Thus, the functionality of each module can be dynamically changed at anytime. In this paper, the system concept and its implementation are described with an example application.
Scanning text with a 1401
Authors: James J. Baker
Venue: Communications of the ACM (1964)

Scanning text on a computer, as in forming word lists or editing, usually involves isolating and identifying certain characters or classes of characters. For example, if we scan text to form a list of words, the definition of &ldquo;word&rdquo; might be &ldquo;everything between two blanks that isn't punctuation.&rdquo; To program this, we must be able to identify a single character (blank) and a class of characters (punctuation). In a computer such as the 7090, where characters are numbers, we can put a character into an index register and index a table of transfers (one table-entry per character), thus getting to a section of code appropriate for handling that particular character. This is not natural for the 1401 because characters are not numbers and turning them into numbers is a bit clumsy. However, 1401 addresses are a combination of numbers and other characters, and we can use characters directly to reference certain addresses provided we can turn all characters (there are 64) into the 40 that are allowable in specifying an address. The ACM Portal is published by the Association for Computing Machinery. Copyright © 2010 ACM, Inc. Terms of Usage Privacy Policy Code of Ethics Contact Us Useful downloads: Adobe Acrobat QuickTime Windows Media Player Real Player