ppxscal/embedding_network huggingface dataset:
Clustering based simulated annealing for standard cell placement
Authors: Sivanarayana Mallela, Lov K. Grover
Venue: Proceedings of the 25th ACM/IEEE Design Automation Conference (1988)

Simulated annealing has been shown to be effective in producing good quality results for the standard cell placement problem. Its main drawback is the excessive computation time required, which increases significantly with the problem size. In this paper we present a novel technique for reducing the effective problem size for simulated annealing without compromising the solution quality. We form clusters of cells based on their interconnections, and place them first using conventional simulated annealing. We then break up the clusters, and place the individual cells using another simulated annealing process that does a refinement on the placement. The original problem is thus divided into two subproblems, each requiring much less time. The results with this 2-stage simulated annealing have been superior to those with our conventional simulated annealing implementation, with more significant improvements observed for larger chips. For chips with more than 2500 cells, we have observed a factor of 2 to 3 speed-up in CPU time, together with a 6 to 17% improvement in the estimated wire-length.
Electronic mail as a coalition-building information technology
Authors: Celia T. Romm, Nava Pliskin
Venue: ACM Transactions on Information Systems (TOIS) (1998)

One of the most intriguing lines of research within the literature on diffusion of information technologies (IT) is the study of the power and politics of this process. The major objective of this article is to build on the work of Kling and Markus on power and IT, by extending their perspective to email. To demonstrate how email can be used for political purposes within an organizational context, a case study is presented. The case study describes a series of events which took place in a university. In the case, email was used by a group of employees to stage a rebellion against the university president. The discussion demonstrates that email features make it amenable to a range of political uses. The article is concluded with a discussion of the implications from this case to email research and practice.
A New Weight Initialization Method for the MLP with the BP inMulticlass Classification Problems
Authors: Myung-Chan Kim, Chong-Ho Choi
Venue: Neural Processing Letters (1997)

Initial learning process of the BP, which can influence the performance of learning in multiclass classification problems, is analyzed. Also, the weights decreasing phenomena in the initial stage of learning are investigated. On the basis of this analysis, a new initialization method is proposed. The proposed method minimizes the initial objective function. It eliminates the phenomenon that weights decrease in the beginning of learning. Several simulation results show that the proposed initialization method performs much better than the conventional random initialization method in the batch mode and slightly better in the pattern mode. Since it requires only a little additional computation, it is a strong alternative to the conventional random initialization. It is expected that the proposed initialization method can be used with any accelerated learning algorithm to enhance the learning speed.
An Optimal Algorithm for Scheduling Soft Aperiodic Tasks in Dynamic-Priority Preemptive Systems
Authors: Ismael Ripoll, Alfons Crespo, Ana García-Fornes
Venue: IEEE Transactions on Software Engineering (1997)

This paper addresses the problem of jointly scheduling tasks with both hard and soft real-time constraints. We present a new analysis applicable to systems scheduled using a priority preemptive dispatcher, with priorities assigned dynamically according to the EDF policy. Further, we present a new efficient on-line algorithm (the acceptor algorithm) for servicing aperiodic work load. The acceptor transforms a soft aperiodic task into a hard one by assigning a deadline. Once transformed, aperiodic tasks are handled in exactly the same way as periodic tasks with hard deadlines. The proposed algorithm is shown to be optimal in terms of providing the shortest aperiodic response time among fixed- and dynamic-priority schedulers. It always guarantees the proper execution of periodic hard tasks. The approach is composed of two parts: an off-line analysis and a run-time scheduler. The off-line algorithm runs in pseudopolynomial time O(mn), where n is the number of hard periodic tasks and m is the hyperperiod/min deadline.
How to obtain more compactable channel routing solutions
Authors: Jingsheng Cong, D. F. Wong
Venue: Proceedings of the 25th ACM/IEEE Design Automation Conference (1988)

In this paper, we present several powerful techniques which allow us to generate efficiently channel routing solutions which are beneficial to further compaction. Our techniques can be applied to straight track compaction as well as to contour routing compaction, and produce very encouraging results. In particular, for Deutsch's Difficult Example, we obtained a straight track routing solution whose area is 7% less than the best known result after straight track compaction. Also, our router generated a routing solution using less area than reported results of all well known routers after contour routing compaction.
Electron Beam Probing&mdash;A Solution for MCM Test and FailureAnalysis
Authors: R. Schmid, R. Schmitt, M. Brunner, O. Gessner, M. Sturm
Venue: Journal of Electronic Testing: Theory and Applications (1997)

Electron beam probing is applied for test and analysis of miniaturised MCM structures. Wiring structures are tested for shorts and opens while fully assembled MCMs are analysed in order to identify process or design problems [1, 2]. An electron beam short/open tester for laminated substrates has been developed and installed. It allows the test of substrates up to a size of 300 &times; 300 mm&sup2; with a spot size of below 30 &mu;m without mechanical movement. The system is automated for routine application in the fabrication line. Electron beam probe stations are common tools for design verification and debugging of integrated circuits. This type of system was adapted to MCM requirements. The travel range was extended to 80 &times; 100 mm&sup2; to allow for waveform measurements and diagnostics.
Accurate and efficient macromodel of submicron digital standard cells
Authors: Cristiano Forzan, Bruno Franzini, Carlo Guardiani
Venue: Proceedings of the 34th annual Design Automation Conference (1997)

In this paper a new analytic gate delay modelingtechnique is presented that allows to accuratelyreproduce the timing behavior of deep submicron digitalstandard cells for a large range of operating conditions.The proposed technique sensibly improves the accuracyof the existing analytic delay models and it usuallyrequires less simulations for the cell characterization.Moreover it is compatible with the most advanced interconnectdelay models that have been recently proposed inthe literature.
SPARK: a benchmark package for sparse computations
Authors: Youcef Saad, Harry A. G. Wijshoff
Venue: ACM SIGARCH Computer Architecture News (1990)

As the diversity of novel architectures expands rapidly there is a growing interest in studying the behavior of these architectures for computations arising in different applications. There has been significant efforts in evaluating the performance of supercomputers on typical dense computations, and several packages for this purpose have been developed, such as the Linpack benchmark, the Lawrence Livermore Loops, and the Los Alamos Kernels. On the other hand there has been little effort put into evaluating the performance of these architectures on the more complicated and perhaps more important sparse computations. In this paper a package is proposed to fill this gap. Its goal is not only to evaluate the performance of supercomputers on sparse computations, but also to analyze the machine-algorithm interaction.
MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
Authors: Chunho Lee, Miodrag Potkonjak, William H. Mangione-Smith
Venue: Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture (1997)

Significant advances have been made in compilation technology for capitalizing on instruction-level parallelism (ILP). The vast majority of ILP compilation research has been conducted in the context of general-purpose computing, and more specifically the SPEC benchmark suite. At the same time, a number of microprocessor architectures have emerged which have VLIW and SIMD structures that are well matched to the needs of the ILP compilers. Most of these processors are targeted at embedded applications such as multimedia and communications, rather than general-purpose systems. Conventional wisdom, and a history of hand optimization of inner-loops, suggests that ILP compilation techniques are well suited to these applications. Unfortunately, there currently exists a gap between the compiler community and embedded applications developers. This paper presents MediaBench, a benchmark suite that has been designed to fill this gap. This suite has been constructed through a three-step process: intuition and market driven initial selection, experimental measurement to establish uniqueness, and integration with system synthesis algorithms to establish usefulness.
Montgomery Multiplication in GF(2^k
Authors: Cetin K. Koc, Tolga Acar
Venue: Designs, Codes and Cryptography (1998)

We show that the multiplication operation c=a &middot; b &middot; r^-1 in the field GF(2^k can be implemented significantly faster in software than the standard multiplication, where r is a special fixed element of the field. This operation is the finite field analogue of the Montgomery multiplication for modular multiplication of integers. We give the bit-level and word-level algorithms for computing the product, perform a thorough performance analysis, and compare the algorithm to the standard multiplication algorithm in GF(2^k. The Montgomery multiplication can be used to obtain fast software implementations of the discrete exponentiation operation, and is particularly suitable for cryptographic applications where k is large.
RIO: a real-time multimedia object server
Authors: Richard Muntz, Jose Renato Santos, Steve Berson
Venue: ACM SIGMETRICS Performance Evaluation Review (1997)

A multimedia object server must be ready to handle a variety of media object types (video, audio, image, 3D interactive, etc.) as well as non real-time workload. Even when a homogeneous set of object types are maintained in the store (e.g., all videos) the storage system workload is generally quite variable due to the need to provide for example, VCR functionality, multiple playout rates, different resolution levels for the same objects, etc. Attempting to carefully layout data and optimally schedule delivery to meet just-in-time delivery constraints is very difficult in the face of this heterogeneous workload. Our approach to the unpredictability of the I/O workload is to randomize the allocation of disk blocks. This turns all workloads into the same uniformly random access pattern and thus gives one problem to deal with. The main disadvantage of this approach is that statistical variation can result in short term imbalances in disk utilization which in turn, cause large variances in latencies. Our approach to this problem is to introduce limited redundancy and asynchronous scheduling for short term load balancing.This approach is being implemented in the RIO (Random I/O) multimedia object server. The RIO multimedia object server provides applications a guaranteed rate of storage access with bounded delay even at very high ( gt; 90%) disk utilization.
A Prolog-based connectivity verification tool
Authors: Alexander C. Papaspyrdis
Venue: Proceedings of the 25th ACM/IEEE Design Automation Conference (1988)

A technology mapping system, used for computer design in NEC, is presented. The features of this system are technology conversion and logical/physical optimization, based on a rule base, partitioning support, conversion verification and special layout consideration. This system is practically used for many applications for technology mapping, including redesigning an existing total unit into a new unit, based on up-to-date LSI technology. The resulting effect is quick inputting of integrated circuit technology progress into practical computer design area.
Reuse of algorithms: still a challenge to object-oriented programming
Authors: Karsten Weihe
Venue: ACM SIGPLAN Notices (1997)

This paper is about reusable, efficient implementations of complex algorithms and their integration into software packages. It seems that this problem is not yetwell understood, and that it is not at all clear how object-oriented and other approaches may contribute to a solution. We analyze the problem and try to reduce it to a few key design goals. Moreover, we discuss various existing approaches in light of these goals, and we briefly report experiences with experimental case studies, in which these goals were rigorously addressed.
Scalable parallel data mining for association rules
Authors: Eui-Hong Han, George Karypis, Vipin Kumar
Venue: Proceedings of the 1997 ACM SIGMOD international conference on Management of data (1997)

One of the important problems in data mining is discovering association rules from databases of transactions where each transaction consists of a set of items. The most time consuming operation in this discovery process is the computation of the frequency of the occurrences of interesting subset of items (called candidates) in the database of transactions. To prune the exponentially large space of candidates, most existing algorithms, consider only those candidates that have a user defined minimum support. Even with the pruning, the task of finding all association rules requires a lot of computation power and time. Parallel computers offer a potential solution to the computation requirement of this task, provided efficient and scalable parallel algorithms can be designed. In this paper, we present two new parallel algorithms for mining association rules. The Intelligent Data Distribution algorithm efficiently uses aggregate memory of the parallel computer by employing intelligent candidate partitioning scheme and uses efficient communication mechanism to move data among the processors. The Hybrid Distribution algorithm further improves upon the Intelligent Data Distribution algorithm by dynamically partitioning the candidate set to maintain good load balance. The experimental results on a Cray T3D parallel computer show that the Hybrid Distribution algorithm scales linearly and exploits the aggregate memory better and can generate more association rules with a single scan of database per pass.
The SR-tree: an index structure for high-dimensional nearest neighbor queries
Authors: Norio Katayama, Shin'ichi Satoh
Venue: Proceedings of the 1997 ACM SIGMOD international conference on Management of data (1997)

Recently, similarity queries on feature vectors have been widely used to perform content-based retrieval of images. To apply this technique to large databases, it is required to develop multidimensional index structures supporting nearest neighbor queries efficiently. The SS-tree had been proposed for this purpose and is known to outperform other index structures such as the R*-tree and the K-D-B-tree. One of its most important features is that it employs bounding spheres rather than bounding rectangles for the shape of regions. However, we demonstrate in this paper that bounding spheres occupy much larger volume than bounding rectangles with high-dimensional data and that this reduces search efficiency. To overcome this drawback, we propose a new index structure called the SR-tree (Sphere/Rectangle-tree) which integrates bounding spheres and bounding rectangles. A region of the SR-tree is specified by the intersection of a bounding sphere and a bounding rectangle. Incorporating bounding rectangles permits neighborhoods to be partitioned into smaller regions than the SS-tree and improves the disjointness among regions. This enhances the performance on nearest neighbor queries especially for high-dimensional and non-uniform data which can be practical in actual image/video similarity indexing. We include the performance test results the verify this advantage of the SR-tree and show that the SR-tree outperforms both the SS-tree and the R*-tree.
Address compression through base register caching
Authors: Arvin Park, Matthew Farrens
Venue: Proceedings of the 23rd annual workshop and symposium on Microprogramming and microarchitecture (1990)

This paper presents a technique to reduce processor-to-memory address bandwidth by exploiting temporal and spatial locality in address reference streams. Higher order portions of address words are cached in base registers at both the processor and memory. This makes it possible to transmit small register indexes between processor and memory instead of the high order address bits themselves. Trace driven simulations indicate that Base Register Caching reduces processor-to-memory address bandwidth up to 60% without appreciable loss in performance.
Computing the Additive Complexity of Algebraic Circuits with Root Extracting
Authors: Dima Grigoriev, Marek Karpinski
Venue: SIAM Journal on Computing (1998)

We design an algorithm for computing the generalized (algebraic circuits with root extracting; cf.\ Pippenger [J. Comput. System Sci., 22 (1981), pp. 454--470], Ja'Ja' [Proc. 22nd IEEE FOCS, 1981, pp. 95--100], Grigoriev, Singer, and Yao [ SIAM J. Comput., 24 (1995), pp. 242--246]) additive complexity of any rational function. It is the first computability result of this sort on the additive complexity of algebraic circuits.
A Survey of Distributed Database Checkpointing
Authors: Jun-Lin Lin, Margaret H. Dunham
Venue: Distributed and Parallel Databases (1997)

Checkpointing a database is a vital technique to reduce the recovery time in the presence of a failure. For distributed databases, checkpointing also provides an efficient way to perform global reconstruction. In this paper, we survey and classify previous approaches for checkpointing a distributed database. Since the need for global reconstruction is infrequent in most distributed databases, a less restrictive and less resource-consuming approach to checkpoint distributed databases in an integrated distributed database system is recommended over a transaction consistent checkpoint approach. For a federated or multidatabase system, any type of global consistent checkpoint is difficult to achieve without violating local autonomy.
Toward a More Realistic Performance Evaluation of Interconnection Networks
Authors: Walter B. Ligon,  III, Umakishore Ramachandran
Venue: IEEE Transactions on Parallel and Distributed Systems (1997)

Interconnection network design plays a central role in the design of parallel systems. Most of the previous research has evaluated the performance of interconnection networks in isolation. In this study, we investigate the relationship between application program characteristics and interconnection network performance using an execution driven simulation testbed: the Reconfigurable Architecture Workbench (RAW). We simulate five topological configurations of a k-ary n-cube interconnect and four different network link models for a 4,096 node SIMD machine, and quantify the impact of the network on two application programs. We provide experimental evidence that such "in-context" simulation provides a better view of the impact of network design variables on system performance. We show that recent results, indicating that low-dimensional designs provide better ICN performance, ignore application requirements that may favor high-dimensional designs. Furthermore, applications that would appear to favor low-dimensional designs may not, in fact, be significantly impacted by the network's dimensionality. We experimentally test the results of published performance models comparing the use of a synthetic load to that of a load generated by a typical application program. The experiments indicate that the standard metric of average message latency can vary considerably under different application loads and that average message latency may not reflect overall application performance.In particular, at the level of the offered (application generated) load to the network, the topological properties of the network are important in determining the average message latency. However, for overall application performance, we found that the network topology may not be critical so long as there is sufficient network bandwidth. In such cases, the results suggest that optimizing the implementation cost of the network should be the key design criterion. We also present a simple abstraction for the network that captures all the important design parameters of the interconnect that can be easily incorporated into any execution-driven simulation framework.
Design of Testable Multipliers for Fixed-Width Data Paths
Authors: Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
Venue: IEEE Transactions on Computers (1997)

The usage of multipliers in fixed-width data-dominated architectures (also termed data paths) poses serious testability problems. Due to truncation of their outputs, the fault observability of the multipliers degrades, and the resulting output patterns are inadequate to completely test functional blocks that are driven by them. Consequently, the overall random pattern testability of data paths deteriorates substantially. In this paper, we propose new generic design schemes, based on residue number system arithmetic, to improve the overall testability of data paths. The approach uses, in the test mode, the truncated least significant bits of the product to increase the variety of patterns at the output of a multiplier. This, in turn, improves the fault detectability of multipliers, and consequently, have a remarkable impact on the overall testability of data paths. The proposed techniques can be incorporated with a minimal performance degradation and area overhead, and are independent of the multiplier architecture. Experimental analysis performed on four high-level synthesis benchmarks exhibits a significant improvement in the overall testability of the corresponding data-path implementations.
Document Image Binarization Based on Texture Features
Authors: Ying Liu, Sargur N. Srihari
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1997)

Binarization has been difficult for document images with poor contrast, strong noise, complex patterns, and/or variable modalities in gray-scale histograms. We developed a texture feature based thresholding algorithm to address this problem. Our algorithm consists of three steps: 1) Candidate thresholds are produced through iterative use of Otsu's algorithm; 2) Texture features associated with each candidate threshold are extracted from the run-length histogram of the accordingly binarized image; 3) The optimal threshold is selected so that desirable document texture features are preserved. Experiments with 9,000 machine printed address blocks from an unconstrained U.S. mail stream demonstrated that over 99.6 percent of the images were successfully binarized by the new thresholding method, appreciably better than those obtained by typical existing thresholding techniques. Also, a system run with 500 troublesome mail address blocks showed that an 8.1 percent higher character recognition rate was achieved with our algorithm as compared with Otsu's algorithm.