ppxscal/embedding_network huggingface dataset:
SMARTS: accelerating microarchitecture simulation via rigorous statistical sampling
Authors: Roland E. Wunderlich, Thomas F. Wenisch, Babak Falsafi, James C. Hoe
Venue: ACM SIGARCH Computer Architecture News (2003)

Current software-based microarchitecture simulators are many orders of magnitude slower than the hardware they simulate. Hence, most microarchitecture design studies draw their conclusions from drastically truncated benchmark simulations that are often inaccurate and misleading. This paper presents the Sampling Microarchitecture Simulation (SMARTS) framework as an approach to enable fast and accurate performance measurements of full-length benchmarks. SMARTS accelerates simulation by selectively measuring in detail only an appropriate benchmark subset. SMARTS prescribes a statistically sound procedure for configuring a systematic sampling simulation run to achieve a desired quantifiable confidence in estimates.Analysis of 41 of the 45 possible SPEC2K benchmark/input combinations show CPI and energy per instruction (EPI) can be estimated to within &plusmn;3% with 99.7% confidence by measuring fewer than 50 million instructions per benchmark. In practice, inaccuracy in microarchitectural state initialization introduces an additional uncertainty which we empirically bound to &sim;2% for the tested benchmarks. Our implementation of SMARTS achieves an actual average error of only 0.64% on CPI and 0.59% on EPI for the tested benchmarks, running with average speedups of 35 and 60 over detailed simulation of 8-way and 16-way out-of-order processors, respectively.
A simple approach to 3D object metamorphosis
Authors: I. Korfiatis, Y. Paker
Venue: Proceedings of the IEEE Conference on Information Visualisation (1997)

This paper presents a technique for smoothly blending some special categories of three-dimensional polygonal objects. Polygon blending is usually considered a two-part process: generating vertex correspondences and interpolating between corresponding vertices to create the intermediate polygons. This paper emphasises on the problem of automatic vertex correspondence determination. The proposed algorithm is based on a simple heuristic method for the metamorphosis of closed planar contours.
A new Kloosterman sum identity over F2m for odd m
Authors: Dong-Joon Shin, Wonjin Sung
Venue: Discrete Mathematics (2003)

A new Kloosterman sum identity over F2m is derived and a class of rational function pairs that satisfy the identity is presented. It is also shown that the Kloosterman sum identity used in the derivation of 3-designs from the Goethals codes over Z4 is a special case of the presented result.
GMRES/CR and Arnoldi/Lanczos as Matrix Approximation Problems
Authors: Anne Greenbaum, Lloyd N. Trefethen
Venue:  (1992)

The GMRES and Arnoldi algorithms, which reduce to the CR and Lanczos algorithms in the symmetric case, both minimize ||p(A)b|| over polynomials p of degree n. The difference is that p is normalized at z=0 for GMRES and at z=infinity for Arnoldi. Analogous "ideal GMRES" and "ideal Arnoldi" problems are obtained if one removes b from the discussion and minimizes ||p(A)|| instead. Investigation of these true and ideal approximation problems gives insight into how fast GMRES converges and how the Arnoldi iteration locates eigenvalues.
The art of seeing: observational techniques for learning about users and their work
Authors: Susan M. Dray, David A. Siegel
Venue: Proceedings of the 1st European UPA conference on European usability professionals association conference - Volume 3 (2002)

Participants gain handle-on experience with observational methods of users and their work, in context. Puts an emphasis on createing an environment where people can explore have fun, promoting effective learning.
PIM Architectures to Support Petaflops Level Computation in the HTMT Machine
Authors: Peter M. Kogge, Jay B. Brockman, Vincent W. Freeh
Venue: Proceedings of the 1999 International Workshop on Innovative Architecture (1999)

The HTMT project is an ambitious attempt to combine a variety of emerging technologies into a petaflops-level computing system available many years before an equivalent machine can be built from current technologies. One of the key problems in such architecture is overcoming latencies between the main memory and the high performance CPUs, which can grow to literally tens of thousands of cycles. In HTMT, the approach taken to overcoming this is a multi-level memory system, with most of the levels to be fabricated using Processing-In-Memory (PIM) technologies in architectures, which actively manage the flow of data without centralized CPU control. This paper overviews the current architecture for such chips within the context of the HTMT system, and how this architecture supports the expected execution model.
Software Reliability: Assumptions, Realities and Data
Authors: Michel Defamie, Patrick Jacobs, Jacques Thollembeck
Venue: Proceedings of the IEEE International Conference on Software Maintenance (1999)

Software Reliability Models are an important issue to identify the actual state of the system during the quality assurance process and to predict the customer release reliability. Major assumptions of the State of The Art models are compared with some realities of a very large system from the industry. Data (failure statistics) observed during the quality assurance process and after 7 years of customer release are supplied to validate existing or coming research models.
Discrete Mathematical Structures, 5 edition
Authors: Bernard Kolman, Robert C. Busby, Sharon Cutler Ross
Venue:  (2003)

:More than any other book in this field, this book ties together discrete topics with a theme. Written at an appropriate level of understanding for those new to the world of abstract mathematics, it limits depth of coverage and areas covered to topics of genuine use in computer science. Chapter topics include fundamentals, logic, counting, relations and digraphs, trees, topics in graph theory, languages and finite-state machines, and groups and coding. For individuals interested in computer science and other related fields  looking for an introduction to discrete mathematics, or a bridge to more advanced material on the subject.
Object-oriented support for specification of distributed protocols
Authors: D. C. Sturman
Venue: Proceedings of the 5th International Workshop on Object Orientation in Operating Systems (IWOOOS '96) (1996)

Existing support for distributed software development falls into one of two classes: tool-kits which provide a static set of tools, and system techniques which are quite flexible yet difficult to use. The author presents a technique that combines the ease-of-use of tool-kits while preserving flexibility. Reflection is used to enable meta-level objects to customize distributed interactions. The architecture supports development of distributed protocols using standard object-oriented techniques without requiring knowledge of an excessive system API. Thus, developing distributed protocols follows the same process as writing any application with distributed objects. Implementation is through compiled objects preserving performance.
On many-valued partitions and many-valued equivalence relations
Authors: Mustafa Demirci
Venue: International Journal of Uncertainty, Fuzziness and Knowledge-Based Systems (2003)

For a fixed integral commutative cl-monoid M = (L, ≤, *), introducing the notions of M-partitions and M-equivalence relations as the extensions of T-partitions and T- equivalence relations to the integral commutative cl-monoid M = (L, ≤, *), respectively, it is shown that the previous approaches on T-partitions and T-equivalence relations can be unified, and most of the results in these works can be easily stated based on the integral commutative cl-monoid M = (L, ≤, *). Modifying the notion of T-redundancy of finite family of fuzzy sets of a nonempty ordinary set X, it is extended to arbitrary family of L-fuzzy sets on the basis of the integral commutative cl-monoid M, and is shown that the proposed definition has more desirable properties than the previous one. Furthermore, handling the works of Höhle, Klawonn, Gebhardt and Kruse on fuzzy partitions and fuzzy equivalence relations, some of their results are improved, and several new results in this direction are pointed out.
A Portable Mechanism for Vectorizing Compiled Event-Driven Simulation
Authors: Swapnajit Mittra
Venue: Proceedings of the 1997 IEEE International Verilog HDL Conference (IVC '97) (1997)

This paper presents a portable mechanism for vectorization of a Hardware Description Language (HDL) in a multi-processing environment. Each of the functional modules in the environment is atomized and put in a centralized event queue using the traditional dynamic event scheduling mechanism. However, during the execution phase, the set of events in a particular time instant form, what we call a `rope' of independent events. Each of the events in this rope is simulated through the creation of an independent thread in the environment. In a multi processing operating system (OS) this means, depending on the availability of processor time-slice, independent threads created from the same process will run parallely on different processors without any special input from the program, thus ensuring a platform-independent portable mechanism . As there is no direct interaction between the program and the kernel of the OS, it is possible to port the code even on a uni processor machine with the worst-case performance being same as that of a sequential simulator.
Using Concurrent and Semi-Concurrent On-Line Testing During HLS: An Adaptable Approach
Authors: M. A. Naal, M. Rakotoar, E. Simeu, C. Aktouf
Venue: Proceedings of the Proceedings of The Eighth IEEE International On-Line Testing Workshop (IOLTW'02) (2002)

This paper proposes a suitable on-line testing technique during the synthesis of complex electronic structures. On-line testability is addressed by exploiting time redundancy in the scheduled data flow graph. On-line testability constraints are taken into account at the scheduling and allocation tasks. The technique implements non-concurrent; semi-concurrentor fully concurrent on-line tests according to the ability of the synthesized structure.
Connected morphological operators for binary images
Authors: Henk J.A.M. Heijmans
Venue:  (1997)

This paper presents a comprehensive discussion on connected morphological operators for binary images. Introducing a connectivity on the underlying space, every image induces a partition of the space in foreground and background components. A connected operator is an operator that coarsens this partition for every input image. A connected operator is called a grain operator if it has the following `local property'': the value of the output image at a given point $x$ is exclusively determined by the zone of the partition of the input image that contains $x$. Every grain operator is uniquely specified by two grain criteria, one for the foreground and one for the background components. A well-known criterion is the area criterion demanding that the area of a zone is not below a given threshold. The second part of the paper is devoted to connected filters and grain filters. It is shown that alternating sequential filters resulting from grain openings and closings are strong filters and obey a strong absorption property, two properties that do not hold in the classical non-connected case.
Client-Server Applications with Visual FoxPro and SQL Server
Authors: Chuck Urwiler, Mike Levy, Leslie Koorhan
Venue:  (2002)

:Visual FoxPro is the perfect front end for client-server applications. Its robust user interface, native local data engine and integral hooks into binding with remote data sources, and rich object model, combined with the powerful SQL Server database engine are an unbeatable combination. But with power and flexibility comes potential complexity. Client-Server Applications with Visual FoxPro and SQL Server teaches users how to put these two powerful tools together and take advantage of the best features of both.
Using QR to solve quantitative modeling problems: an application to intracellular thiamine kinetics
Authors: R. Bellazzi, R. Guglielmann, L. Ironi
Venue:  (2000)

Recent works carried out within the Qualitative Reasoning (QR) research framework are centred on the exploitation of QR techniques to address the problem of quantitative System Identification (SI) with the goal to enhance the overall process, namely the selection of a proper model identifier and the parameter estimation procedure. Traditional SI, both parametric and non-parametric, may be really problematic for those application domains, such as the medical/physiological one, of which either the available knowledge is incomplete or the structural model is not identifiable or the observed data are poor in number and in quality. This paper deals with the application of an hybrid method, which builds a fuzzy system identifier upon a qualitative structural model, to solve identification problems of the intracellular kinetics of Thiamine (vitamin B1). The model obtained is not as much informative as a purely structural one but robust enough to be used as a simulator, and then to provide physiologists with a deeper understanding of the Thiamine metabolism in the cells.
Combined Analysis of User Interface and Domain Requirements
Authors: Georg Kösters, Hans-Werner Six, Josef Voss
Venue: Proceedings of the 2nd International Conference on Requirements Engineering (ICRE '96) (1996)

A requirements analysis method called Fluid is proposed which in contrast to conventional methods explicitly captures the requirements of direct manipulation user interfaces. The main concepts addressing the user interface requirements comprise a task model and a UIA-model. The latter reveals the essential structure of the user interface and defines the basic dialog behavior, the presentation of domain model components on the screen, and links to the domain model. User interface requirements are described on a level of abstraction similar to that of conventional requirements, e.g. details of screen layout and dialog behavior are deferred to later development stages. The result of the entire requirements analysis a combination of domain model and UIA-model serves as a basis for the further development process. The method also provides for (semi-) automatic generation of user interface prototypes at intermediate stages of the analysis.
The effects of active queue management on web performance
Authors: Long Le, Jay Aikat, Kevin Jeffay, F. Donelson Smith
Venue: Proceedings of the 2003 conference on Applications, technologies, architectures, and protocols for computer communications (2003)

We present an empirical study of the effects of active queue management (AQM) on the distribution of response times experienced by a population of web users. Three prominent AQM schemes are considered: the Proportional Integrator (PI) controller, the Random Exponential Marking (REM) controller, and Adaptive Random Early Detection (ARED). The effects of these AQM schemes were studied alone and in combination with Explicit Congestion Notification (ECN). Our major results are: <ol>For offered loads up to 80% of bottleneck link capacity, no AQM scheme provides better response times than simple drop-tail FIFO queue management. For loads of 90% of link capacity or greater when ECN is not used, PI results in a modest improvement over drop-tail and the other AQM schemes. With ECN, both PI and REM provide significant response time improvement at offered loads above 90% of link capacity. Moreover, at a load of 90% PI and REM with ECN provide response times competitive to that achieved on an unloaded network. ARED with recommended parameter settings consistently resulted in the poorest response times which was unimproved by the addition of ECN.</ol.We conclude that without ECN there is little end-user performance gain to be realized by employing the AQM designs studied here. However, with ECN, response times can be significantly improved. In addition it appears likely that provider links may be operated at near saturation levels without significant degradation in user-perceived performance.
Hierarchical Replacement Decisions in Hierarchical Stores
Authors: Ozalp Babaoglu, Domenico Ferrari
Venue:  (1982)

One of the primary motivations for implementing virtual memory is its ability to automatically manage a hierarchy of storage systems with different characteristics. The composite system behaves as if it were a single-level system having the more desirable characteristics of each of its constituent levels. In this paper, we extend the virtual memory concept to within each of the levels of the hierarchy. Each level is thought of as containing two additional levels within it. This hierarchy is not a physical one, but rather an artificial one arising from the employment of two different replacement algorithms. Given two replacement algorithms, one of which has good performance but high implementation cost and the other poor performance but low implementation cost, we propose and analyze schemes that result in an overall algorithm having the performance characteristics of the former and the cost characteristics of the latter. We discuss the suitability of such schemes in the management of storage hierarchies that lack page reference bits.
An integrated environment for HDL verification
Authors: G. York, R. Mueller-Thuns, J. Patel, D. Beatty
Venue: Proceedings of the 4th IEEE International Verilog HDL Conference (1995)

The functional verification of a digital design is an expensive step in the design process. As designs become more complex, simulation is challenged throughout the design and verification process, both at the low level (implementation verification), to show that a low level implementation implements a higher-level specification, and at the high level (design verification), to show that a design complies with some abstract specification. In both areas, formal methods can extend the reach of simulation: for implementation verification, equivalence checking is used to show that two circuits are functionally the same in some well defined sense. For design verification, model checking and other property checking techniques serve as a smart simulator. This paper describes Forte, a formal verification prototype that integrates formal verification and simulation. Forte fits into a standard top-down design flow using standard HDL's such as Verilog-HDL and VHDL, and works well with synthesis. Forte includes traditional and symbolic simulation, combinational and sequential equivalence, and CTL model checking. We discuss its design and implementation, and illustrate the utility of combining formal verification and simulation using an example. Moreover, Forte's object-oriented design makes it an ideal platform for rapidly evaluating new ideas in verification.
PASM: a reconfigurable parallel system for image processing
Authors: Howard Jay Siegel, Thomas Schwederski, Nathaniel J. Davis,  IV, James T. Kuehn
Venue: ACM SIGARCH Computer Architecture News (1984)

PASM is a multifunction partitionable SIMD/MIMD system being designed at Purdue for parallel image understanding. It is to be a large-scale, dynamically reconfigurable multimicroprocessor system, which will incorporate over 1,000 complex processing elements. Parallel algorithm studies and simulations have been used to analyze application tasks in order to guide design decisions. A prototype of PASM is under construction (funded by an equipment grant from IBM), including 30 Motorola MC68010 processors, a multistage interconnection network, five disk drives, and connections to the Purdue Engineering Computer Network (for access to peripherals, terminals, software development tools, etc.). PASM is to serve as a vehicle for studying the use of parallelism for performing the numeric and symbolic processing needed for tasks such as computer vision. The PASM design concepts and prototype are overviewed and brief examples of parallel algorithms are given.
Rim Sensitivity Analysis from an Interior Solution
Authors: Harvey J. Greenberg
Venue:  (1996)

This establishes theorems about the simultaneuos variation of right-hand sides and cost coefficients in a linaer program from an interior solution. Some results are extensions of those that have been proven for varying the right-hand side of the primal or the dual, but not both; other results are new. In addition, changes in the optimal partition and what that means in economic terms are related to the basis-driven approach, notable to the Theory of Compatibility. In addition to new theorems about this relation, the transition graph is extended to provide visualization of the underlying economics.
Genetic algorithm trained counter-propagation neural net in structural optimization
Authors: A. Iranmanesh, M. Fahimi
Venue: Proceedings of the sixth international conference on Application of artificial intelligence to civil & structural engineering (2001)

The main objective of this research is to improve the efficiency of the Counter-Propagation Neural net response in structural analysis and optimization. To achieve this, a modification has been made on the learning coefficients, which resulted in a higher performance. The net is trained by two different procedures, random and genetic generation of training pairs. To examine the efficiency of the net, different examples has been investigated. The results of genetic trained Counter-Propagation net and the random trained one are compared with the exact solution. The effects of various parameters, such as number of training pairs, number of Kohonen units, and the number of winning nodes are researched. The work has been compared with others and the results are much better and overall performance of the net is improved. The purpose of using Genetic Algorithms is mainly to investigate its efficiency in the net response.
Scalability, Throughput Stability and Efficient Buffering in Reliable Multicast Protocols
Authors: Oznur Ozkasap
Venue:  (2000)

This study investigates the issues of scalability, throughput stability and efficient buffering in reliable multicast protocols. The focus is on a new class of scalable reliable multicast protoco, PBcast that is based on an epidemic loss recovery mechanism. The protocol offers scalability, throughput stability and a bimodal delivery guarantee as the key features. A theoretical analysis study for the protocol is already available.
C Compiler Targeting the Java Virtual Machine
Authors: Jack Pien
Venue:  (1998)

One of the major drawbacks in the field of computer software development has been the inability for applications to compile once and execute across many different platforms. With the emergence of the Internet and the networking of many different platforms, the Java programming language and the Java Platform was created by Sun Microsystems to address this "Write Once, Run Anywhere" problem. What sets a compiled Java program apart from programs compiled from other high level languages is the ability of a Java Virtual Machine to execute the compiled Java program on any platform, as long as the Java Virtual Machine is running on top of that platform. Java''s cross platform capabilities can be extended to other high level languages such as C. The main objective of our project is to implement a compiler targeting the Java Platform for a subset of the C language. This will allow code written in that subset of C to be compiled into Java Virtual Machine instructions, also known as JVM bytecode, which can then be executed on a Java Virtual Machine running on any platform. The reader is assumed to be intimately familiar with compiler construction, the use of the flex scanner generator, the use of the GNU bison parser generator, and the structure and implementation of the Java Virtual Machine. The ACM Portal is published by the Association for Computing Machinery. Copyright © 2010 ACM, Inc. Terms of Usage Privacy Policy Code of Ethics Contact Us Useful downloads: Adobe Acrobat QuickTime Windows Media Player Real Player