ppxscal/embedding_network huggingface dataset:
Passenger-based predictive modeling of airline no-show rates
Authors: Richard D. Lawrence, Se June Hong, Jacques Cherrier
Venue: Proceedings of the ninth ACM SIGKDD international conference on Knowledge discovery and data mining (2003)

Airlines routinely overbook flights based on the expectation that some fraction of booked passengers will not show for each flight. Accurate forecasts of the expected number of no-shows for each flight can increase airline revenue by reducing the number of spoiled seats (empty seats that might otherwise have been sold) and the number of involuntary denied boardings at the departure gate. Conventional no-show forecasting methods typically average the no-show rates of historically similar flights, without the use of passenger-specific information.We develop two classes of models to predict cabin-level no-show rates using specific information on the individual passengers booked on each flight. The first of these models computes the no-show probability for each passenger, using both the cabin-level historical forecast and the extracted passenger features as explanatory variables. This passenger-level model is implemented using three different predictive methods: a C4.5 decision-tree, a segmented Naive Bayes algorithm, and a new aggregation method for an ensemble of probabilistic models. The second cabin-level model is formulated using the desired cabin-level no-show rate as the response variable. Inputs to this model include the predicted cabin-level no-show rates derived from the various passenger-level models, as well as simple statistics of the features of the cabin passenger population. The cabin-level model is implemented using either linear regression, or as a direct probability model with explicit incorporation of the cabin-level no-show rates derived from the passenger-level model outputs.The new passenger-based models are compared to a conventional historical model, using train and evaluation data sets taken from over 1 million passenger name records. Standard metrics such as lift curves and mean-square cabin-level errors establish the improved accuracy of the passenger-based models over the historical model. All models are also evaluated using a simple revenue model, and it is shown that the cabin-level passenger-based model can produce between 0.4% and 3.2% revenue gain over the conventional model, depending on the revenue-model parameters.
Accurate simulation of a 6-pulse inverter with real-time event compensation in ARTEMISTM
Authors: Christian Dufour, Jean Bélanger, Simon Abourida
Venue: Mathematics and Computers in Simulation (2003)

This paper presents new simulation software that allows the efficient and accurate fixed-time-step simulation of complex event-based electrical systems. The software, named Advanced Real-Time Electro-Mechanical Transient Simulator (ARTEMISTM), accurately simulates time-segment linear systems with discontinuities occurring anywhere between time-steps. The new software is used for the simulation of energy and power system dynamics, and is implemented in the ARTEMISTM add-on for Simulink's Power System Blockset (PSB). With ARTEMISTM real-time compensation of switching events (RTE), the between-step events are transparently taken into account and compensated for in the simulation results. This eliminates sub-synchronous jitter while causing only minor increase in both the average time-step and real-time time-step (typically <10%), making ARTEMISTM with RTE suitable software for real-time simulation of precision-critical hardware-in-the-loop (HIL) electromechanical and drives systems. The RTE algorithm is very good at handling difficult fixed-step simulation cases, like multiple single time-step discontinuities encountered in the simulation of electric drives and power converters.
IBIS: an Interactive Bytecode Inspection System, using symbolic execution and constraint logic programming
Authors: J. Doyle, C. Meudec
Venue: Proceedings of the 2nd international conference on Principles and practice of programming in Java (2003)

A fundamental area of software engineering that remains a challenge is the delivery of software with the minimum of remaining defects. The principal technique currently used in the software industry for the verification and validation of software is dynamic software testing where the software under consideration is actually executed using test data. The actual generation of test data for the purpose of automated software testing is still however mainly a manual task. This problem is further compounded for Java programmers because testing criteria can be imposed at the Java Bytecode level rather than at the source level. To alleviate these difficulties an Interactive Bytecode Inspection System (IBIS) has been developed that allows examination of the Java Bytecode and the automatic generation and execution of test data.
Intelligent Web Topics Search Using Early Detection and Data Analysis
Authors: Ching-Cheng Lee, Yixin Yang
Venue: Proceedings of the 27th Annual International Conference on Computer Software and Applications (2003)

Topic-specific search engines that offered users relevanttopics as search results have recently been developed.However, these topic-specific search engines requireintensive human efforts to build and maintain. In addition,they visit many irrelevant pages. In our project, wepropose a new approach for Web topics search. First, wedo early detection for "candidate topics" while extractingwords from the HTML text. Secondly, we perform dataanalysis on the appearance information such asappearance times and places for candidate topics. Bythese two techniques, we can reduce candidate topics'crawling times and computing cost. Analysis of the resultsand the comparisons with related research will be madeto demonstrate the effectiveness of our approach.
Why software writing is difficult and will remain so
Authors: Michael Jackson
Venue: Information Processing Letters (2003)

Software writing is difficult for many reasons. One important reason is the interplay between the formal world of the computer and its programming language with the informal world where the problem to be solved is located. In this paper some of the direct and indirect consequences of this interplay are briefly discussed, both for software specification and design generally and for the composition of independently identified and specified subproblems.
Irredundance and Maximum Degree in Graphs
Authors: E. J. Cockayne, C. M. Mynhardt
Venue: Combinatorics, Probability and Computing (1997)

It is proved that the smallest cardinality among the maximal irredundant sets in an n&ndash;vertex graph with maximum degree &Delta;(&ge;2) is at least 2n&#x002F;3&Delta;. This substantially improves a bound by Bollob&aacute;s and Cockayne [1]. The class of graphs which attain this bound is characterised.
Object classification and recognition using Toeplitz matrices
Authors: Khalid Saeed
Venue: Artificial intelligence and security in computing systems (2003)

A new object-classifying algorithm is presented in this paper. The algorithm is based on the theory of Toeplitz matrices and their characteristic minimal eigenvalues. The derived Toeplitz forms are applied to verify the projected views of the given images for recognition. Experiments are carried out for some selected standard letters of twelve different font styles. The results are good and encouraging for algorithm extension to apply on other applications like handwritten script, spoken-letter image and varieties of geometrical patterns including views of three dimensional objects for the sake of classification and recognition.
Proof of Two Conjectures of Brenti and Simion on Kazhdan-Lusztig Polynomials
Authors: Fabrizio Caselli
Venue: Journal of Algebraic Combinatorics: An International Journal (2003)

We find an explicit formula for the Kazhdan-Lusztig polynomials Pui,a,vi of the symmetric group \mathfrak(n) where, for a, i, n &isin; \Bbb N such that 1 &le; a &le; i &le; n, we denote by ui,a &equals; sasa+1 &middot;&middot;&middot; si&minus;1 and by vi the element of \mathfrak(n) obtained by inserting n in position i in any permutation of \mathfrak(n &minus; 1) allowed to rise only in the first and in the last place. Our result implies, in particular, the validity of two conjectures of Brenti and Simion [4, Conjectures 4.2 and 4.3], and includes as a special case a result of Shapiro, Shapiro and Vainshtein [13, Theorem 1]. All the proofs are purely combinatorial and make no use of the geometry of the corresponding Schubert varieties.
On abstract interpretation of mobile ambients
Authors: Francesca Levi, Sergio Maffeis
Venue: Information and Computation (2004)

We introduce an abstract interpretation framework for mobile ambients, based on a new semantics called normal semantics. Then, we derive within this setting two analyses computing a safe approximation of the run-time topological structure of processes. Such a static information can be successfully used to establish interesting security properties.
An FFT Approximation Technique Suitable for On-Chip Generation and Analysis of Sinusoidal Signals
Authors: John M. Emmert, Jason A. Cheatham, Badhri Jagannathan, Sandeep Umarani
Venue: Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (2003)

Signal generation and analysis are an important part of BIST for analog and mixed-signalsystems. An accurate analysis of the spectral content of signals produced by analog components can be accomplished with a digital implementation of a fast Fourier transform (FFT) algorithm. In the past, size and speed have limited the application of such a techniqueto o.-chip test equipment or DSP chips (primarily due to the number of multiplication operations). In this paper, we present an FFT approximation technique suitable for on-chipspectral BIST signal generation and analysis. For signal generation, we show that the noiseproduced by the approximation technique is under 24.74 dB for a 256 point FFT with a 32 point approximate kernel. For signal analysis, we show that the instantaneous dynamic range (IDR) for the approximation technique is under 21.80 dB for a 256 point FFT with a 32 point approximate kernel. Our techniques have been implemented and demonstrated on a Xilinx Virtex-II FPGA using an o.-chip ADC and DAC, and we are currently implementing the technique on an ASIC using a 0.13µm SiGe process for 2-16GHz applications 1.
Beating in-order stalls with "flea-flicker" two-pass pipelining
Authors: Ronald D. Barnes, Erik M. Nystrom, John W. Sias, Sanjay J. Patel, Nacho Navarro, Wen-mei W. Hwu
Venue: Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture (2003)

Accommodating the uncertain latency of load instructionsis one of the most vexing problems in in-order microarchitecturedesign and compiler development. Compilers cangenerate schedules with a high degree of instruction-levelparallelism but cannot effectively accommodate unanticipatedlatencies; incorporating traditional out-of-order executioninto the microarchitecture hides some of this latencybut redundantly performs work done by the compiler andadds additional pipeline stages. Although effective techniques,such as prefetching and threading, have been proposedto deal with anticipable, long-latency misses, theshorter, more diffuse stalls due to difficult-to-anticipate,first- or second-level misses are less easily hidden on in-orderarchitectures. This paper addresses this problemby proposing a microarchitectural technique, referred toas two-pass pipelining, wherein the program executes ontwo in-order back-end pipelines coupled by a queue. The"advance" pipeline executes instructions greedily, withoutstalling on unanticipated latency dependences (executingindependent instructions while otherwise blocking instructionsare deferred). The "backup" pipeline allows concurrentresolution of instructions that were deferred in theother pipeline, resulting in the absorption of shorter missesand the overlap of longer ones. This paper argues that thisdesign is both achievable and a good use of transistor resourcesand shows results indicating that it can deliver significantspeedups for in-order processor designs.
The development of a case study methodology in the information technology (IT) field: a step by step approach
Authors: Sam Lubbe
Venue: Ubiquity (2003)

An important step any researcher should take is establishing a framework in which to conduct the research.
A framework for designing and implementing the Ada standard container library
Authors: Jordi Marco, Xavier Franch
Venue: Proceedings of the 2003 annual ACM SIGAda international conference on Ada: the engineering of correct and reliable software for real-time & distributed systems using ada and related technologies (2003)

An open issue of the Ada language is the definition of a standard container library. Containers in this library (e.g., sets, maps and lists) shall offer some core functionalities that characterise their behaviour (i.e., different strategies for managing the elements stored therein) as well as other general functionalities. Among these general functionalities, we are interested in alternative ways for accessing the containers, namely direct access by position and traversals using iterators. In this paper, we present the Shortcut-Based Framework (SBF), a framework aimed at providing suitable, uniform, accurate and secure access by position and iterators, while keeping other nice properties such as comprehensibility and changeability. The SBF should be considered as a baseline upon which the Ada standard container library can be built. We assess the feasibility of our proposal defining a quality model for container libraries and evaluating the SBF using some metrics defined with the Goal-Question-Metric approach.
PeAgent - A Mobile Agent System to Support Secure Internet and Web Applications
Authors: Qingkai Ma, Wei Hao, Wei Li, Manghui Tu, I-Ling Yen
Venue: Proceedings of the 27th Annual International Conference on Computer Software and Applications (2003)

Many agent-based systems have been developed over thepast decade; however, the security issues are usually notaddressed adequately. In order to make the mobile agentparadigm more useful and acceptable for Web and Internetapplications, the security considerations should go beyond theprotection of basic agent execution environments. In thispaper, we present the design of a robust Java-based mobileagent system, PeAgent. The PeAgent system not onlyincorporates a fine-grain agent privilege control mechanism,but also includes a multi-level protection mechanism that canbe used throughout the life-cycle of agents. A two-leveldomain hierarchy is constructed to organize the large numberof Internet nodes in the agent system into manageable units:the Global/Domain Management Unit (GMU/DMU). Eachunit consists of a Certification Authority (CA) and a LocationManager (LM). The certificates issued from GMU and DMUdefine the access privileges on the PeAgent servers for eachagent. A context hierarchy is built up on the PeAgent serversfor fine-level resource access control and agent management.Overall, the PeAgent system provides a secure computingenvironment for widely distributed applications over anetwork of heterogeneous platforms. It also facilitates thedevelopment of secure Web-based applications.
A versatile tool for student projects: an ASM programming language for the Lego mindstorm
Authors: Jason Gilder, Michael Peterson, Jason Wright, Travis Doom
Venue: Journal on Educational Resources in Computing (JERIC) (2003)

Finding new and exciting senior design projects for undergraduate computer engineers can be challenging for both students and faculty advisors. The challenge is even more pronounced when attempting to construct interdisciplinary design projects to better meet ABET 2000 criteria and to better prepare graduating students for careers as engineers. We present an interdisciplinary, honors senior design project incorporating robotics control, algorithmic state machine design, reverse-engineering, assembly programming, and language, and basic compiler design. We believe this two-quarter project was extremely successful, and can be used as a model for similar design projects at other undergraduate institutions.
The process specification language (PSL) theory and applications
Authors: Michael Grüninger, Christopher Menzel
Venue: AI Magazine (2003)

The PROCESS SPECIFICATION LANGUAGE (PSL) has been designed to facilitate correct and complete exchange of process information among manufacturing systems, such as scheduling, process modeling, process planning, production planning, simulation, project management, work flow, and business-process reengineering. We give an overview of the theories within the PSL ontology, discuss some of the design principles for the ontology, and finish with examples of process specifications that are based on the ontology.
Reuse of analogous specifications during requirements analysis
Authors: N. A. M. Maiden, A. G. Sutcliffe
Venue: Proceedings of the 6th international workshop on Software specification and design (1991)

Analogy is proposed as an alternative paradigm for specification reuse during requirements analysis. However, extensive analyst involvement is necessary to maximise analogical reuse across domains. An intelligent reuse advisor which supports analysts during the retrieval, understanding and customisation of complex specifications is proposed. Its design is based on cognitive models of analogical reasoning during software reuse derived from empirical studies of analytic behaviour.
Authentication and Key Distribution Methods in Mobile Computing Environments
Authors: Bin Zhang, Jiang-xing Wu
Venue: Proceedings of the 2003 International Conference on Computer Networks and Mobile Computing (2003)

This paper discusses the authentication problem of the mobile user based on public key cryptosystem and shared key cryptosystem. We analyze several authentication and key distribution protocols in mobile environment. Weaknesses of each protocol are pointed out. A global initial authentication and key distribution method based on public key certificate chain is presented. It is argued that using hybrid system is feasible in order to authenticate the mobile user.
In-situ study of stress evolution during solid state reaction of Pd with Si(001) using synchrotron radiation
Authors: M. Megdiche, P. Gergaud, C. Curtil, O. Thomas, B. Chenevier, A. Mazuelas
Venue: Microelectronic Engineering (2003)

Using X-ray diffraction experiments and curvature measurements, in-situ real-time measurements of stress are performed during solid state reaction of a palladium thin film with Si(001). From X-ray diffraction measurements and using the sin2ψ method, we found out that the stress in the metal and in the silicide is compressive. This stress decreases all along the solid-state reaction for the silicide. We then compared our results with the qualitative model proposed by Zhang and d'Heurle. This model suggests the development of a high compressive stress (-2.4 GPa) in the silicide.
INFTY: an integrated OCR system for mathematical documents
Authors: Masakazu Suzuki, Fumikazu Tamari, Ryoji Fukuda, Seiichi Uchida, Toshihiro Kanahori
Venue: Proceedings of the 2003 ACM symposium on Document engineering (2003)

An integrated OCR system for mathematical documents, called INFTY, is presented. INFTY consists of four procedures, i.e., layout analysis, character recognition, structure analysis of mathematical expressions, and manual error correction. In those procedures, several novel techniques are utilized for better recognition performance. Experimental results on about 500 pages of mathematical documents showed high character recognition rates on both mathematical expressions and ordinary texts, and sufficient performance on the structure analysis of the mathematical expressions.
Assessing the assessment of programming ability
Authors: Charlie Daly, John Waldron
Venue: Proceedings of the 35th SIGCSE technical symposium on Computer science education (2004)

A recent study [7] has shown that many computing students are not able to develop straightforward programs after the introductory programming sequence. Normal student assessment should have highlighted this problem, it did not, therefore normal assessment of programming ability does not work.We examine why current assessment methods (written exams and programming assignments) are faulty. We investigate another method of assessment (the lab exam) and show that this form of assessment is more accurate.We explain why accurate assessment is essential in order to encourage students to develop programming ability.
Examining possible antecedents of IT impact on the supply chain and its effect on firm performance
Authors: Terry Anthony Byrd, Nancy W. Davidson
Venue: Information and Management (2003)

Our study examined the impact of information technology (IT) on the supply chain through a survey of 225 large for-profit US firms. Specifically, it involved the determination of IT antecedents to IT impact on the supply chain and the effect that these relationships had on overall firm performance. The respondents were primarily chief information officers and other top IT executives. The factors in the study were validated using confirmatory factor analysis. A model featuring the IT antecedents, IT impact on the supply chain, and firm performance was evaluated using a structural equation analysis. The data used fit well with the hypothesized relationships in the model, as all links were significant. The findings here suggested that the antecedents, IT department technical quality, IT plan utilization, and top management of IT positively affected IT impact on the supply chain. The results also revealed a positive relationship between IT impact and firm performance.
Packing Circuits into KN
Authors: Paul Balister
Venue: Combinatorics, Probability and Computing (2001)

We shall pack circuits of arbitrary lengths into the complete graph KN. More precisely, if N is odd and &sum;ti=1 mi = (N2), mi &ge; 3, then the edges of KN can be written as an edge-disjoint union of circuits of lengths m1,&hellip;,mt. Since the degrees of the vertices in any such packing must be even, this result cannot hold for even N. For N even, we prove that if &sum;ti=1 mi &le; (N2) &minus; N&minus;2 then we can write some subgraph of KN as an edge-disjoint union of circuits of lengths m1,&hellip;,mt. In particular, KN minus a 1-factor can be written as a union of such circuits when &sum;ti=1 mi = (N2) &minus; N&minus;2. We shall also show that these results are best possible.
Approximate coloring of uniform hypergraphs
Authors: Michael Krivelevich, Benny Sudakov
Venue: Journal of Algorithms (2003)

We consider an algorithmic problem of coloring r-uniform hypergraphs. The problem of finding the exact value of the chromatic number of a hypergraph is known to be NP-hard, so we discuss approximate solutions to it. Using a simple construction and known results on hardness of graph coloring, we show that for any r ≥ 3 it is impossible to approximate in polynomial time the chromatic number of r-uniform hypergraphs on n vertices within a factor n1-ε for any ε > 0, unless NP ⊆ ZPP. On the positive side, improving a result of Hofmeister and Lefmann, we present an approximation algorithm for coloring r-uniform hypergraphs on n vertices, whose performance ratio is O(n(log logn)2/(logn)2).