ppxscal/embedding_network huggingface dataset:
SIMP (Single Instruction stream/Multiple instruction Pipelining): a novel high-speed single-processor architecture
Authors: K. Murakami, N. Irie, S. Tomita
Venue: ACM SIGARCH Computer Architecture News (1989)

SIMP is a novel multiple instruction-pipeline parallel architecture. It is targeted for enhancing the performance of SISD processors drastically by exploiting both temporal and spatial parallelisms, and for keeping program compatibility as well. Degree of performance enhancement achieved by SIMP depends on; i) how to supply multiple instructions continuously, and ii) how to resolve data and control dependencies effectively. We have devised the outstanding techniques for instruction fetch and dependency resolution. The instruction fetch mechanism employs unique schemes of; i) prefetching multiple instructions with the help of branch prediction, ii) squashing instructions selectively, and iii) providing multiple conditional modes as a result. The dependency resolution mechanism permits out-of-order execution of sequential instruction stream. Our out-of-order execution model is based on Tomasulo's algorithm which has been used in single instruction-pipeline processors. However, it is greatly extended and accommodated to multiple instruction pipelining with; i) detecting and identifying multiple dependencies simultaneously, ii) alleviating the effects of control dependencies with both eager execution and advance execution, and iii) ensuring a precise machine state against branches and interrupts. By taking advantage of these techniques, SIMP is one of the most promising architectures toward the coming generation of high-speed single processors.
How do writers view usability information? A case study of a developing documentation writer
Authors: Patricia A. Sullivan, James E. Porter
Venue: ACM SIGDOC Asterisk Journal of Computer Documentation (1990)

As Dieli (1989) notes, writers sometimes have trouble focusing their concerns into questions that usability groups can test. As teachers of future documentation writers, we have observed that writers also have trouble turning the results of those usability tests into strategies for document revision. Our first investigation into these issues&mdash;see Sullivan Porter (1990)&mdash;described a class of fifteen professional writing students employing usability information to write computer documentation. That study indicated that the writer's use of information is guided by that writer's rhetorical orientation, particularly his/her view of the audience/user. Though all the writers in the study conducted the same type of usability test (modeled after Atlas' &ldquo;user edit&rdquo;&mdash;see Atlas, 1981), they interpreted their test results in different ways. This investigation continues the Sullivan Porter (1990) study using a longitudinal case study of one professional writer, called &ldquo;Max.&rdquo; This follow-up study aims to probe how the writer's rhetorical orientation guides that writer's interpretation of usability test results. We take a slightly uncommon view of usability. We have opted to focus on the writer's view of users' actions&mdash;both what is noticed and how it is interpreted. Typically, usability studies have examined the interaction between texts/systems and readers/users (see McDonald Schvaneveldt, 1988; Ramey, 1988; Rubens Rubens, 1988), subordinating the important variable of how the writer interprets and uses results. Although both Sullivan (March, 1985) and Schriver (1987) suggest that writers can be trained to successfully use user information in revising documents they do not author, usability studies still have not examined how writers view the findings from usability studies run on their own work. Our study examines how, and to what degree, one writer's rhetorical orientation filters results from usability tests. what is his rhetorical orientation? what value does he place on, and how does he classify and apply, usability test information?
Word processing techniques and user learning preferences
Authors: Amiram Raban
Venue: ACM SIGCHI Bulletin (1988)

This study compared guided exploration training and instruction- based training as methods of learning to use a word processing system. User learning preferences and attitudes toward computers were also assessed. Seventy five computer-naive people learned basic word processing functions in two training sessions. Post- training performance and knowledge tests were then administered. Guided exploration proved to be more effective than the instruction-based method. There is evidence for the potential benefit of matching training techniques to user learning preferences.
ESUDL: an expert system for monitoring unclassified data link (UDL) communication systems protocols
Authors: M. T. Lin, I. Chen, J. Lao
Venue: Proceedings of the 2nd international conference on Industrial and engineering applications of artificial intelligence and expert systems - Volume 1 (1989)

The ESUDL is a specially designed Expert System for monitoring a non-U.S. Army Unclassified Data Link (UDL) communication system. ESUDL consists of four components: data base, rule base, computer program, and a backward chaining inference engine. This system is implemented to overcome the limitations of the current manual approach. The implementation of the ESUDL system will result in a more reliable and much faster processing and monitoring of the UDL communication system.
Parallel Sorting in a Ring Network of Processors
Authors: Y.-C. Hong, T. H. Payne
Venue: IEEE Transactions on Computers (1989)

A parallel implementation of selection sorting algorithms is presented that uses a ring-connected array of processors, in which each processor has the same amount of memory. The scheme allows all processors to have the same amount of memory with a small fragmentation loss. Uniformity in the size of the memories provides advantages from the viewpoint of manufacture, maintenance, inventory, item placement, and many other aspects of system design. These memories can, together, function as an interleaved memory for a general-purpose computer. Hence, it is possible to build a medium-scale system in which parallel-sort is implemented as a primitive, like block-move, without a large increment in hardware complexity and cost. An analysis is presented that shows how to improve performance by overlapping comparisons with memory accesses and how to achieve performance improvement by applying carry-look-ahead techniques to comparison.
The architecture of an active database management system
Authors: Dennis McCarthy
Venue: ACM SIGMOD Record (1989)

The HiPAC project is investigating active, time-constrained database management. An active DBMS is one which automatically executes specified actions when specified conditions arise. HiPAC has proposed Event-Condition-Action (ECA) rules as a formalism for active database capabilities. We have also developed an execution model that specifies how these rules are processed in the context of database transactions. The additional functionality provided by ECA rules makes new demands on the design of an active DBMS. In this paper we propose an architecture for an active DBMS that supports ECA rules. This architecture provides new forms of interaction, in support of ECA rules, between application programs and the DBMS. This leads to a new paradigm for constructing database applications.
An experiment into the use of auditory cues to reduce visual workload
Authors: M. L. Brown, S. L. Newsome, E. P. Glinert
Venue: ACM SIGCHI Bulletin (1989)

The potential utility of dividing the information flowing from computer to human among several sensory modalities is investigated by means of a rigorous experiment which compares the effectiveness of auditory and visual cues in the performance of a visual search task. The results indicate that a complex auditory cue can be used to replace cues traditionally presented in the visual modality. Implications for the design of multimodal workstations are discussed.
Using distributed simulation for distributed application development
Authors: Max Muhlhauser
Venue: Proceedings of the 21st annual symposium on Simulation (1988)

The software engineering environment DESIGN integrates several approaches for the development of distributed applications. The distributed programming language DC provides for language support. A workstation based human interface integrates programming tools such as a language sensitive editor, a distributed debugger, data evaluation tools, etc. This paper concentrates on a further approach of DESIGN: performance evaluation and prototyping on the basis of distributed simulation. The use of distributed simulation allowed to make effective use of the parallelism provided by a distributed system, not only after the accomplishment of a distributed program, but from the very beginning of the development. A central goal of the DESIGN approach was computer assisted modeling, i.e. automatic generation of the simulation model out of the program text of a network application under development; this feature substantially simplifies performance evaluation and optimization in early development phases. The distributed simulation approach, the computer assisted modeling technique, and the modeling system for distributed applications are the main topics of the paper.
Distributed round-robin and first-come first-serve protocols and their applications to multiprocessor bus arbitration
Authors: M. K. Vernon, U. Manber
Venue: ACM SIGARCH Computer Architecture News (1988)

Two new distributed protocols for fair and efficient bus arbitration are presented. The protocols implement round-robin (RR) and first-come first-serve (FCFS) scheduling, respectively. Both protocols use relatively few control lines on the bus, and their logic is simple. The round-robin protocol, which uses statically assigned arbitration numbers to resolve conflict during an arbitration, is more robust and simpler to implement than previous distributed RR protocols that are based on rotating agent priorities. The proposed FCFS protocol uses partly static arbitration numbers, and is the first practical proposal for a FCFS arbiter known to the authors. The proposed protocols thus have a better combination of efficiency, cost, and fairness characteristics than existing multiprocessor bus arbitration algorithms. Three implementations of our RR protocol, and two implementations of our FCFS protocol, are discussed. Simulation results are presented that address: 1) the practical potential for unfairness in the simpler implementation of the FCFS protocol, 2) the practical implications of the higher waiting time variance in the RR protocol, and 3) the allocation of bus bandwidth among agents with unequal request rates in each protocol. The simulation results indicate that there is very little practical difference in the performance of the two protocols.
A fault-tolerant communication system for the B-Hive generalized hypercube multiprocessor
Authors: B. D. Harry, R. A. Balla, D. P. Agrawal, T. K. Miller, E. F. Gehringer
Venue: Proceedings of the third conference on Hypercube concurrent computers and applications: Architecture, software, computer systems, and general issues - Volume 1 (1988)

We describe the implementation of a communication system on the B-HIVE generalized hypercube. B-HIVE has 24 nodes connected in a 2 x 3 x 4 structure. Each node consists of two processors: an application processor (AP) and a communication processor (CP). The communication system runs solely on the CP and presents a simple DMA-like interface to user programs. A fault-tolerant communication system was developed for these reasons: (1) We desired a way to transmit messages reliably over a potentially unreliable communication network, and (2) B-HIVE implements both packet-switched and circuit-switched communications in the same network. At any time many channels may be allocated to a circuit-switched transaction and therefore be unusable for packet-switched routing. Since these channels can be rapidly allocated and then deallocated, we wanted an automatic mechanism for discovering these &ldquo;failed&rdquo; routes rather than broadcasting to the entire network each time a link is removed. These requirements mandated a simple protocol for detecting failed links, and updating the necessary routing tables. An algorithm is described that routes messages efficiently in a network where large portions are not functioning, A related issue is broadcasting a message to all nodes in the network. Several different methods of broadcasting are considered, and the routing algorithm is adapted to perform a broadcast. Currently we have implemented a static routing network where routes are only changed in the case of a detected failure. Future research will be directed towards more dynamic routing with load balancing.
Applying Synthesis Principles to Create Responsive Software Systems
Authors: C. U. Smith
Venue: IEEE Transactions on Software Engineering (1988)

The general principles for formulating software requirements and designs that meet response-time goals are reviewed. The principles are related to the system performance parameters that they improve, and thus their application may not be obvious to those whose speciality is system architecture and design. The author addresses the designer's perspective and illustrates how these principles apply to typical design problems. The examples illustrate requirements and design of: communication, user interfaces, information storage, retrieval and update, information hiding, and data availability. Strategies for effective use of the principles are described.
Babbage and Aiken
Authors: I. Bernard Cohen
Venue: IEEE Annals of the History of Computing (1988)

Because Howard H. Aiken expressed such an admiration for the ideas of Charles Babbage, the machine he conceived - brought into being through the engineering talents of IBM (the Mark I or ASCC) - is often cited as an example of Babbage's dream come true. This article explores the depth and extent of Aiken's knowledge of Babbage's ideas, the stage of his own thinking when he first encountered Babbage's writings, and the way in which he found out about Babbage.
A Necessary Condition for Learning from Positive Examples
Authors: Haim Shvaytser
Venue: Machine Learning (1990)

We present a simple combinatorial criterion for determining concept classes that cannot be learned in the sense of Valiant from a polynomial number of positive-only examples. The criterion is applied to several types of Boolean formulae in conjunctive and disjunctive normal form, to the majority function, to graphs with large connected components, and to a neural network with a single threshold unit. All are shown to be nonlearnable from positive-only examples.
Survey of closed queueing networks with blocking
Authors: Raif O. Onvural
Venue: ACM Computing Surveys (CSUR) (1990)

Closed queueing networks are frequently used to model complex service systems such as production systems, communication systems, computer systems, and flexible manufacturing systems. When limitations are imposed on the queue sizes (i.e., finite queues), a phenomenon called blocking occurs. Queueing networks with blocking are, in general, difficult to treat. Exact closed form solutions have been reported only in a few special cases. Hence, most of the techniques that are used to analyze such queueing networks are in the form of approximations, numerical analysis, and simulation. In this paper, we give a systematic presentation of the literature related to closed queueing networks with finite queues. The results are significant for both researchers and practitioners.
Transparent interconnection of incompatible local area networks using bridges
Authors: R. Perlman, G. Varghese
Venue: Proceedings of the ACM workshop on Frontiers in computer communications technology (1987)

No single LAN technology is sufficient to interconnect all the computers in a given plant, campus, or site. Thus it is desirable to combine different types of LANs, using a device called a Bridge, to produce an Extended LAN. Some LANs in the Extended LAN may have incompatible Data Link formats. Thus a bridge may need to encapsulate a frame originating on LAN A inside the Data Link header of another (incompatible) LAN B in order to allow the type A frame to travel over LAN B. In general, frames sent between any pair of LANs in the Extended LAN must be encapsulated across every incompatible LAN in the path between the LANs. Bridges learn their routing information from information contained in frames they forward. Besides the problems of distinguishing various kinds of encapsulated and unencapsulated frames, the encapsulating protocol used by bridges must also solve the learning problem. This leads to a new set of considerations and solutions. We begin with a rough solution, and refine it using informal arguments and examples to lead to the final description. The stages in the description roughly mimic the design process.
Summary of Fortran 88
Authors: Loren P. Meissner
Venue: ACM SIGPLAN Fortran Forum (1989)

The first part of this Fortran 88 Summary, through Section 4 in the following outline, appears in this issue. The next issue of Fortran Forum will continue with new features in the area of Data Types (including Structures and Arrays).
An introduction to function rank
Authors: R. Bernecky
Venue: Proceedings of the international conference on APL (1987)

This paper gives a simple introduction to the concepts of Function Rank and the Rank Operator as they are defined in SHARP APL, and presents examples of their use. It shows the benefits, both in language design and in practice, of these concepts. Comparisons are made with other APL implementations, which do not use these concepts.
The case for Modula-2 in CS1 and CS2
Authors: Elliot B. Koffman
Venue: ACM SIGCSE Bulletin (1988)

During 1984 and 1985 I was part of an ACM Task Force to update the recommended curricula for CSI and CS2, the first two courses in programming methods for computer science majors. Our findings were reported in the communications of the ACM (Koffman, 1984 and 1985). The objectives of CS1 and CS2 as stated in these reports follow.
Artificial intelligence techniques applied to maintenance management
Authors: A. K. Ray, M. S. S. N. Murty
Venue: Proceedings of the 2nd international conference on Industrial and engineering applications of artificial intelligence and expert systems - Volume 1 (1989)

In a Steel Industry Maintenance Mangement (MM) functions are customarily performed using both conventional data processing systems and Manual Processes. Automated processes are implemented for those MM functions distinguished by their respective nature; manual processes are used for those MM functions that require human judgement and intervention. The manual processes are generally performed by personnel with different levels of &ldquo;Expertise&rdquo;. MM functions requiring human judgement and intervention is an appropriate applications for artificial intelligence (AI) techniques such as expert systems and Natural Language Proceessing.The first part of the paper describes about a computer program developed in 'C' and which is in use for acquiring knowledge about maintenance planning and trouble-shooting of equipments. The second part of the paper briefly describes the areas in which we are planning to apply AI techniques in Maintenance Management.
Computational Efficiency of Parallel Combinatorial OR-Tree Searches
Authors: Guo-Jie Li, Benjamin W. Wah
Venue: IEEE Transactions on Software Engineering (1990)

The performance of parallel combinatorial OR-tree searches is analytically evaluated. This performance depends on the complexity of the problem to be solved, the error allowance function, the dominance relation, and the search strategies. The exact performance may be difficult to predict due to the nondeterminism and anomalies of parallelism. The authors derive the performance bounds of parallel OR-tree searches with respect to the best-first, depth-first, and breadth-first strategies, and verify these bounds by simulation. They show that a near-linear speedup can be achieved with respect to a large number of processors for parallel OR-tree searches. Using the bounds developed, the authors derive sufficient conditions for assuring that parallelism will not degrade performance and necessary conditions for allowing parallelism to have a speedup greater than the ratio of the numbers of processors. These bounds and conditions provide the theoretical foundation for determining the number of processors required to assure a near-linear speedup.
Implementing the beam and warming method on the hypercube
Authors: J. Bruno, P. R. Cappello
Venue: Proceedings of the third conference on Hypercube concurrent computers and applications - Volume 2 (1989)

Numerical simulation of a wide range of physical phenomena typically involves enormous amounts of computation and, for scores of practical problems, these simulations cannot be carried out even on today's fastest supercomputers. The economic and scientific importance of many of these problems is driving the explosive research in computer architecture, especially the work aimed at achieving ultra high-speed computation by exploiting concurrent processing. Correspondingly, there is great interest in the design and analysis of numerical algorithms which are suitable for implementation on concurrent processor systems. In this paper we consider the implementation of the Beam and Warming implicit factored method on a hypercube concurrent processor system. We present a set of equations and give the numerical method in sufficient detail to illustrate and analyze the problems which arise in implementing this numerical method. We show that there are mappings of the computational domain onto the nodes of a hypercube concurrent processor system which maintain the efficiency of the numerical method. We also show that better methods do not exist.
On Mapping Algorithms to Linear and Fault-Tolerant Systolic Arrays
Authors: V. K. Prasanna Kumar, Y.-C. Tsai
Venue: IEEE Transactions on Computers (1989)

A simple mapping technique is developed to design systolic arrays with limited I/O capability. The technique is used to improve systolic algorithms for some matrix computations on linearly connected arrays of PEs (processor elements) with constant I/O bandwidth. The important features of these designs are modularity with constant hardware in each PE, few control lines, simple data-input/output format, and improved delay time. This technique is extended to design an optimal n square root n-time systolic algorithm for n*n matrix multiplication with O( square root n) I/O bandwidth requirement on a fault-tolerant VLSI model. In this model, the propagation delay is assumed to be proportional to wire length. Fault reconfiguration is achieved by using buffers to bypass faulty PEs, which does not affect the clock rate of the system. The unidirectional flow of control and data assures correctness of the algorithm in the presence of faulty PEs. The design can be implemented on reconfigurable fault-tolerant VLSI arrays using the Diogenes methodology. The present designs are compared to those in the literature and are shown to be superior with respect to I/O format, control, and delay from input to output.
Human factors in teaching
Authors: D. Sharpe, M. J. Willshire
Venue: ACM SIGCHI Bulletin (1989)

In this paper we discuss the parallels between human factors in computer systems and human factors in the classroom. We look at some of the human factors guidelines for computer system design and discuss their analogs in course design and execution. Since many of us are called upon to share our expertise in a classroom setting, perhaps we can learn from our experience with software and thus try to maximize our teaching effectiveness.