ppxscal/embedding_network huggingface dataset:
Planar-adaptive routing: low-cost adaptive networks for multiprocessors
Authors: Andrew A. Chien, Jae H. Kim
Venue: Journal of the ACM (JACM) (1995)

Network throughput can be increased by allowing multipath, adaptive routing. Adaptive routing allows more freedom in the paths taken by messages, spreading load over physical channels more evenly. The flexibility of adaptive routing introduces new possibilities of deadlock. Previous deadlock avoidance schemes in k-ary n-cubes require an exponential number of virtual channels. We describe a family of deadlock-free routing algorithms, called planar-adaptive routing algorithms, that require only a constant number of virtual channels, independent of networks size and dimension. Planar-adaptive routing algorithms reduce the complexity of deadlock prevention by reducing the number of choices at each routing step. In the fault-free case, planar-adaptive networks are guaranteed to be deadlock-free. In the presence of network faults, the planar-adaptive router can be extended with misrouting to produce a working network which remains provably deadlock free and is provably livelock free. In addition, planar-adaptive networks can simultaneously support both in-order and adaptive, out-of-order packet delivery.Planar-adaptive routing is of practical significance. It provides the simplest known support for deadlock-free adaptive routing in k-ary n-cubes of more than two dimensions (with k>2). Restricting adaptivity reduces the hardware complexity, improving router speed or allowing additional performance-enhancing network features. The structure of planar-adaptive routers is amenable to efficient implementation.Simulation studies show that planar-adaptive routers can increase the robustness of network throughput for nonuniform communication patterns. Planar-adaptive routers outperform deterministic routers with equal hardware resources. Further, adding virtual lanes to planar-adaptive routers increases this advantage. Comparisons with fully adaptive routers show that planar-adaptive routers, limited adaptive routers, can give superior performance. These results indicate the best way to allocate router resources to combine adaptivity and virtual lanes.Planar-adaptive routers are a special case of limited adaptivity routers. We define a class of adaptive routers with f degrees of routing freedom. This class, termed f-flat adaptive routers, allows a direct cost-performance tradeoff between implementation cost (speed and silicon area) and routing freedom (channel utilization). For a network of a particular dimension, the cost of adaptivity grows linearly with the routing freedom. However, the rate of growth is a much larger constant for high-dimensional networks. All of the properties proven for planar-adaptive routers, such as deadlock and livelock freedom, also apply to f-flat adaptive routers.
XTracker, a graphical tool for parallel simulations
Authors: Steven Bellenot, Li Duty
Venue: ACM SIGSIM Simulation Digest (1995)

A Motif based graphical tool XTracker is described. XTracker can show Gannt-like charts of the activities on each node or it can show the event messages as traffic between simulation objects. XTracker can take its data from sequential simulation runs and simulate a parallel execution under a number of simulation methods. XTracker can act as a performance modeling tool.
Memory bandwidth limitations of future microprocessors
Authors: Doug Burger, James R. Goodman, Alain Kägi
Venue: Proceedings of the 23rd annual international symposium on Computer architecture (1996)

This paper makes the case that pin bandwidth will be a critical consideration for future microprocessors. We show that many of the techniques used to tolerate growing memory latencies do so at the expense of increased bandwidth requirements. Using a decomposition of execution time, we show that for modern processors that employ aggressive memory latency tolerance techniques, wasted cycles due to insufficient bandwidth generally exceed those due to raw memory latencies. Given the importance of maximizing memory bandwidth, we calculate effective pin bandwidth, then estimate optimal effective pin bandwidth. We measure these quantities by determining the amount by which both caches and minimal-traffic caches filter accesses to the lower levels of the memory hierarchy. We see that there is a gap that can exceed two orders of magnitude between the total memory traffic generated by caches and the minimal-traffic caches---implying that the potential exists to increase effective pin bandwidth substantially. We decompose this traffic gap into four factors, and show they contribute quite differently to traffic reduction for different benchmarks. We conclude that, in the short term, pin bandwidth limitations will make more complex on-chip caches cost-effective. For example, flexible caches may allow individual applications to choose from a range of caching policies. In the long term, we predict that off-chip accesses will be so expensive that all system memory will reside on one or more processor chips.
Benchmark Evaluation of the IBM SP2 for Parallel Signal Processing
Authors: Kai Kwang, Masahiro Arakawa
Venue: IEEE Transactions on Parallel and Distributed Systems (1996)

This paper evaluates the IBM SP2 architecture, the AIX parallel programming environment, and the IBM message-passing library (MPL) through STAP (Space-Time Adaptive Processing) benchmark experiments. Only coarse-grain parallelism was exploited on the SP2 due to its high communication overhead. A new parallelization scheme is developed for programming message passing multicomputers. Parallel STAP benchmark structures are illustrated with domain decomposition, efficient mapping of partitioned programs, and optimization of collective communication operations. We measure the SP2 performance in terms of execution time, Gflop/s rate, speedup over a single SP2 node, and overall system utilization. With 256 nodes, the Maui SP2 demonstrated the best performance of 23 Gflop/s in executing the High-Order Post-Doppler program, corresponding to a 34% system utilization. We have conducted a scalability analysis to reveal the performance growth rate as a function of machine size and STAP problem size. Important lessons learned from these parallel processing benchmark experiments are discussed in the context of real-time, adaptive, radar signal processing on massively parallel processors (MPP).
Exploiting choice: instruction fetch and issue on an implementable simultaneous multithreading processor
Authors: Dean M. Tullsen, Susan J. Eggers, Joel S. Emer, Henry M. Levy, Jack L. Lo, Rebecca L. Stamm
Venue: Proceedings of the 23rd annual international symposium on Computer architecture (1996)

Simultaneous multithreading is a technique that permits multiple independent threads to issue multiple instructions each cycle. In previous work we demonstrated the performance potential of simultaneous multithreading, based on a somewhat idealized model. In this paper we show that the throughput gains from simultaneous multithreading can be achieved without extensive changes to a conventional wide-issue superscalar, either in hardware structures or sizes. We present an architecture for simultaneous multithreading that achieves three goals: (1) it minimizes the architectural impact on the conventional superscalar design, (2) it has minimal performance impact on a single thread executing alone, and (3) it achieves significant throughput gains when running multiple threads. Our simultaneous multithreading architecture achieves a throughput of 5.4 instructions per cycle, a 2.5-fold improvement over an unmodified superscalar with similar hardware resources. This speedup is enhanced by an advantage of multithreading previously unexploited in other architectures: the ability to favor for fetch and issue those threads most efficiently using the processor each cycle, thereby providing the "best" instructions to the processor.
Sample Compression, Learnability, and the Vapnik-Chervonenkis Dimension
Authors: Sally Floyd, Manfred Warmuth
Venue: Machine Learning (1995)

Within the framework of pac-learning, we explore the learnability of concepts from samples using the paradigm of sample compression schemes. A sample compression scheme of size k for a concept class C &sube; 2X consists of a compression function and a reconstruction function. The compression function receives a finite sample set consistent with some concept in C and chooses a subset of k examples as the compression set. The reconstruction function forms a hypothesis on X from a compression set of k examples. For any sample set of a concept in C the compression set produced by the compression function must lead to a hypothesis consistent with the whole original sample set when it is fed to the reconstruction function. We demonstrate that the existence of a sample compression scheme of fixed-size for a class C is sufficient to ensure that the class C is pac-learnable.Previous work has shown that a class is pac-learnable if and only if the Vapnik-Chervonenkis (VC) dimension of the class is finite. In the second half of this paper we explore the relationship between sample compression schemes and the VC dimension. We define maximum and maximal classes of VC dimension d. For every maximum class of VC dimension d, there is a sample compression scheme of size d, and for sufficiently-large maximum classes there is no sample compression scheme of size less than d. We discuss briefly classes of VC dimension d that are maximal but not maximum. It is an open question whether every class of VC dimension d has a sample compression scheme of size O(d).
CAA Decoder for Cellular Automata Based Byte Error Correcting Code
Authors: Koppolu Sasidhar, Santuanu Chattopadhyay, Parimal Pal Chaudhuri
Venue: IEEE Transactions on Computers (1996)

Design of Cellular Automata (CA) based byte error correcting code analogous to extended Reed-Solomon code has been proposed in [1], [2]. This code has same restrictions on error correction as that of extended R-S code. In this paper a new design scheme has been reported for parallel implementation of CA based SbEC/DbED and DbEC/DbED code that is analogous to the conventional R-S code. Both the encoder and decoder of this code can be efficiently implemented with an array of CA (CAA) with high throughput. The design is ideally suited for high speed memory systems built with byte organized RAM chips. Extension of the scheme to detect/correct larger number of byte errors has also been reported. Throughput of the decoder to handle t byte errors (t¿ 4) can be found to be substantially better than that of conventional R-S decoder. The proposed decoder provides a simple, modular and cost effective design that ideally suits for VLSI implementation.
Zeros of Spectral Factors, the Geometry of Splitting Subspaces, and the Algebraic Riccati Inequality
Authors: Anders Lindquist, Gyorgy Michaletzky, Giorgio Picci
Venue: SIAM Journal on Control and Optimization (1995)

In this paper it is shown how the zero dynamics of (not necessarily square) spectral factors relate to the splitting subspace geometry of stationary stochastic models and to the corresponding algebraic Riccati inequality. The notion of output-induced subspace of a minimal Markovian splitting subspace, which is the stochastic analogue of the supremal output-nulling subspace in geometric control theory, is introduced. Through this concept, the analysis can be made coordinate-free and straightforward geometric methods can be applied. It is shown how the zero structure of the family of spectral factors relates to the geometric structure of the family of minimal Markovian splitting subspaces in the sense that the relationship between the zeros of different spectral factors is reflected in the partial ordering of minimal splitting subspaces. Finally, the well-known characterization of the solutions of the algebraic Riccati equation is generalized in terms of Lagrangian subspaces invariant under the corresponding Hamiltonian to the larger solution set of the algebraic Riccati inequality.
The EM-X parallel computer: architecture and basic performance
Authors: Yuetsu Kodama, Hirohumi Sakane, Mitsuhisa Sato, Hayato Yamana, Shuichi Sakai, Yoshinori Yamaguchi
Venue: ACM SIGARCH Computer Architecture News (1995)

Latency tolerance is essential in achieving high performance on parallel computers for remote function calls and fine-grained remote memory accesses. EM-X supports interprocessor communication on an execution pipeline with small and simple packets. It can create a packet in one cycle, and receive a packet from the network in the on-chip buffer without interruption. EM-X invokes threads on packet arrival, minimizing the overhead of thread switching. It can tolerate communication latency by using efficient multi-threading and optimizing packet flow of fine grain communication. EM-X also supports the synchronization of two operands, direct remote memory read/write operations and flexible packet scheduling with priority. This paper describes distinctive features of the EM-X architecture and reports the performance of small synthetic programs and larger more realistic programs.
BIRCH: an efficient data clustering method for very large databases
Authors: Tian Zhang, Raghu Ramakrishnan, Miron Livny
Venue: ACM SIGMOD Record (1996)

Finding useful patterns in large datasets has attracted considerable interest recently, and one of the most widely studied problems in this area is the identification of clusters, or densely populated regions, in a multi-dimensional dataset. Prior work does not adequately address the problem of large datasets and minimization of I/O costs.This paper presents a data clustering method named BIRCH (Balanced Iterative Reducing and Clustering using Hierarchies), and demonstrates that it is especially suitable for very large databases. BIRCH incrementally and dynamically clusters incoming multi-dimensional metric data points to try to produce the best quality clustering with the available resources (i.e., available memory and time constraints). BIRCH can typically find a good clustering with a single scan of the data, and improve the quality further with a few additional scans. BIRCH is also the first clustering algorithm proposed in the database area to handle "noise" (data points that are not part of the underlying pattern) effectively.We evaluate BIRCH's time/space efficiency, data input order sensitivity, and clustering quality through several experiments. We also present a performance comparisons of BIRCH versus CLARANS, a clustering method proposed recently for large datasets, and show that BIRCH is consistently superior.
Barriers and resistance to the evaluation of a computerized pharmacological information system: a case study
Authors: Henry P. Lundsgaarde
Venue: ACM SIGBIO Newsletter (1995)

Studies of technology innovation, implementation and adoption [Erasmus 1961, Barnett 1953, Goodenough 1966, Rogers 1983] have documented how even the simplest technological change can cause people to change their work habits, attitudes, and social relationships in the workplace [Forsy the et al. 1991]. These studies, and many others like them, help us to understand and explain why medical information systems, such as the one discussed here, take time to implement and why inattention to contextual and social organizational factors on the part of developers and health care administrators can result in under utilization and even system sabotage [Anderson et al. 1987, Graves et al. 1992]. I will discuss one particular aspect of research with a large Midwest Medical Center to illustrate and address some of the organizational problems and issues that must be faced before major benefits can be realized from the introduction of new technologies.The application of computer technology to health care provides broad opportunities to improve the quality and cost effectiveness of health care. But there is an unfortunate trend to develop and market computer software applications prematurely without adequate clinical evaluation. While it is difficult to choose among programs designed to serve the particular needs of a sub-specialty, the task of finding computer applications that can meet the needs of a diverse group of practitioners seems even more difficult. The main obstacle to achieving the benefits of new hardware or software applications is not so much a function of consumers having too many choices, but rather in educating medical practitioners to accept and use innovative clinical applications. Evaluation research activities ideally bridge the interests of developers and end-users. Developers want to see their products accepted and put to good use but they frequently exaggerate the benefits to be achieved from the purchase of a particular product. Endusers, on the other hand, often may invest in a product without having the benefit of the kind of comparative and objective empirical data from evaluation studies that can inform and guide intelligent decision making.
Software protection and simulation on oblivious RAMs
Authors: Oded Goldreich, Rafail Ostrovsky
Venue: Journal of the ACM (JACM) (1996)

Software protection is one of the most important issues concerning computer practice. There exist many heuristics and ad-hoc methods for protection, but the problem as a whole has not received the theoretical treatment it deserves. In this paper, we provide theoretical treatment of software protection. We reduce the problem of software protection to the problem of efficient simulation on oblivious RAM.A machine is oblivious if thhe sequence in which it accesses memory locations is equivalent for any two inputs with the same running time. For example, an oblivious Turing Machine is one for which the movement of the heads on the tapes is identical for each computation. (Thus, the movement is independent of the actual input.) What is the slowdown in the running time of a machine, if it is required to be oblivious? In 1979, Pippenger and Fischer showed how a two-tape oblivious Turing Machine can simulate, on-line, a one-tape Turing Machine, with a logarithmic slowdown in the running time. We show an analogous result for the random-access machine (RAM) model of computation. In particular, we show how to do an on-line simulation of an arbitrary RAM by a probabilistic oblivious RAM with a polylogaithmic slowdown in the running time. On the other hand, we show that a logarithmic slowdown is a lower bound.
Prolog in 10 figures
Authors: Alain Colmerauer
Venue: Communications of the ACM (1985)

In the fall of 1981, a Japanese report officially initiated the quest for fifth-generation computers that would encompass the functions of knowledge processing and artificial intelligence. The conceptual underpinnings behind Prolog&mdash;Japan's language of choice for these activities&mdash;are presented here in a way that suggests why Prolog or a similar language might be considered a model for designing the computers of the future.
Parallel and distributed simulation of free choice Petri Nets
Authors: François Baccelli, Nathalie Furmento, Bruno Gaujal
Venue: Proceedings of the ninth workshop on Parallel and distributed simulation (1995)

In this paper, we present two new methods to simulate Petri Nets: a data parallel simulation and a distributed simulation. Both simulations use an equational representation of the net in the so called (min, +) algebra. The data parallel simulation is based on the use of matrix representation of these equations, and the distributed simulation on the decomposition of a Petri Net into marked graph components.
A Randomized Maximum-Flow Algorithm
Authors: Joseph Cheriyan, Torben Hagerup
Venue: SIAM Journal on Computing (1995)

A randomized algorithm for computing a maximum flow is presented. For an $n$-vertex $m$-edge network, the running time is $O(nm + n^2(\log n)^2)$ with probability at least $1 - 2^{-\sqrt{nm}}$. The algorithm is always correct, and in the worst case runs in $O(nm \log n)$ time. The only use of randomization is to randomly permute the adjacency lists of the network vertices at the start of the execution. The analysis introduces the notion of premature target relabeling (PTR) events and shows that each PTR event contributes $O(\log n)$ amortized time to the overall running time. The number of PTR events is always $O(nm)$; however, it is shown that when the adjacency lists are randomly permuted, then this quantity is $O(n^{3/2}m^{1/2} + n^2 \log n)$ with high probability.
Application and experimental evaluation of state space reduction methods for deadlock analysis in Ada
Authors: S. Duri, U. Buy, R. Devarapalli, S. M. Shatz
Venue: ACM Transactions on Software Engineering and Methodology (TOSEM) (1994)

An emerging challenge for software engineering is the development of the methods and tools to aid design and analysis of concurrent and distributed software. Over the past few years, a number of analysis methods that focus on Ada tasking have been developed. Many of these methods are based on some form of reachability analysis, which has the advantage of being conceptually simple, but the disadvantage of being computationally expensive. We explore the effectiveness of various Petri net-based techniques for the automated deadlock analysis of Ada programs. Our experiments consider a variety of state space reduction methods both individually and in various combinations. The experiments are applied to a number of classical concurrent programs as well as a set of &ldquo;real-world&rdquo; programs. The results indicate that Petri net reduction and reduced state space generation are mutually beneficial techniques, and that combined approaches based on Petri net models are quite effective, compared to alternative analysis approaches.
A proposed structured collaboration architecture&mdash;derived from Scrutiny project
Authors: John W. Gintell, Roland F. McKenney
Venue: ACM SIGOIS Bulletin (1995)

This position paper describes a proposed architecture for a family of collaborative applications where the collaboration is governed by a definable process. The architecture is derived from lessons learned and generalizations made from a recently completed three year project to build and use Scrutiny, a distributed CSCW system for performing software inspection and review.
Optimizing parallel programs with explicit synchronization
Authors: Arvind Krishnamurthy, Katherine Yelick
Venue: ACM SIGPLAN Notices (1995)

We present compiler analyses and optimizations for explicitly parallel programs that communicate through a shared address space. Any type of code motion on explicitly parallel programs requires a new kind of analysis to ensure that operations reordered on one processor cannot be observed by another. The analysis, based on work by Shasha and Snir, checks for cycles among interfering accesses. We improve the accuracy of their analysis by using additional information from post-wait synchronization, barriers, and locks.We demonstrate the use of this analysis by optimizing remote access on distributed memory machines. The optimizations include message pipelining, to allow multiple outstanding remote memory operations, conversion of two-way to one-way communication, and elimination of communication through data re-use. The performance improvements are as high as 20-35% for programs running on a CM-5 multiprocessor using the Split-C language as a global address layer.
Sensitivity Analysis in Nonlinear Programs and Variational Inequalities via Continuous Selections
Authors: Jiming Liu
Venue: SIAM Journal on Control and Optimization (1995)

Sufficient conditions for solution Lipschitz continuity, piecewise differentiability, and directional differentiability are presented for parametric nonlinear programs and variational inequalities using the idea of continuous selections. The gaps between the sufficient conditions obtained here and the weakest possible conditions for the corresponding conclusions are discussed and measured by known regularity conditions.