ppxscal/embedding_network huggingface dataset:
Enhanced PVM Communications over a High-Speed LAN
Authors: Sheue-Ling Chang, David Hung-Chang Du, Jenwei Hsieh, Rose P. Tsang, Mengjou Lin
Venue: IEEE Parallel Distributed Technology: Systems Technology (1995)

Performance results of PVM over a local ATM network show the availability of much greater communication bandwidth over traditional LANs such as Ethernet. Application-level performance, however, still lags far behind the capabilities of the physical medium. Realizing the full potential of high-speed networks, therefore, will require further improvements in both hardware and software components of network I/O subsystems.Emulating a parallel machine via a collection of heterogeneous, independent hosts and a general-purpose local-area network has obvious advantages, including cost-effectiveness and very large aggregate processing power and memory. However, the ability of most general-purpose LANs to support communication-intensive parallel applications is debatable. Today, with the emergence of several high-speed, switch-based networks, such as High-Performance Parallel Interface (Hippi), Fibre Channel, and Asynchronous Transfer Mode (ATM), networks that effectively support communication-intensive parallel applications may soon become a reality.Network-based computing offers several advantages. First, independent, commercially available systems and a general LAN can readily incorporate advances in processor and network technology. Second, due to the large memory and processing power available in the aggregate collection of individual host systems, very large applications can execute on a collection of relatively low-priced host systems. Third, the underlying network can support high-speed input/output to applications, for instance, by using disk arrays.One factor that previously fueled much skepticism about the feasibility of network-based parallel computing was the limitations imposed by using traditional LANs, such as Ethernet, as the system interconnect. For many typical network applications that require only occasional file transfers, or infrequent small amounts of data to be transmitted between workstations, an Ethernet-based cluster of workstations will suffice. However, for network-based applications, such as communication-intensive, course-grain parallel applications, traditional networks such as Ethernet simply cannot provide adequate performance. Thus, for this study, we chose a high-speed transport mode as the supporting communication medium.
Computed tomography angiography: a case study of peripheral vessel investigation
Authors: Armin Kanitsar, Dominik Fleischmann, Rainer Wegenkittl, Dominique Sandner, Petr Felkel, Eduard Gröller
Venue: Proceedings of the conference on Visualization '01 (2001)

This paper deals with vessel exploration based on computed tomography angiography. Large image sequences of the lower extremities are investigated in a clinical environment. Two different approaches for peripheral vessel diagnosis dealing with stenosis and calcification detection are introduced. The paper presents an automated vessel-tracking tool for curved planar reformation. An interactive segmentation tool for bone removal is proposed.
Management and Integrated Tools
Authors: Sorel Reisman
Venue: IEEE Software (1990)

After a brief overview, tools representing a broad spectrum of management features are described in separate presentations. DSCC and Configuration Management Assistant offer a user-definable development framework in which other tools and systems can be included. Amplify Control, EAST IPSE, and Epos are integrated project-management software-engineering systems that provide specific functions in such development frameworks. Aisle, is also such a system but with the even more specific purpose of aiding Ada developers. The Integrated Test Tool System is a utility system that can be integrated with the output of an integrated programming environment to test and validate the results of development efforts, either in Ada, C, Cobol, Fortran, or Pascal. CASE-PM is an example of a learning tool being used by software-engineering students.
A New Graph Approach to Minimizing Processor Fragmentation in Hypercube Multiprocessors
Authors: Q. Yang, H. Wang
Venue: IEEE Transactions on Parallel and Distributed Systems (1993)

The authors propose a new approach for subcube and noncubic processor allocations forhypercube multiprocessors. The main idea is to represent available processors in thesystem by means of a prime cube graph (PC-graph). The PC-graph maintains theinter-relationships between free subcubes and hence reduces both internal and externalprocessor fragmentations. Their simulation results show that the PC-graph approachoutperforms the existing allocation strategies by 25% to 50% under certain loadconditions.
Caching on the World Wide Web
Authors: Charu Aggarwal, Joel L. Wolf, Philip S. Yu
Venue: IEEE Transactions on Knowledge and Data Engineering (1999)

With the recent explosion in usage of the World Wide Web, the problem of caching Web objects has gained considerable importance. Caching on the Web differs from traditional caching in several ways. The nonhomogeneity of the object sizes is probably the most important such difference. In this paper, we give an overview of caching policies designed specifically for Web objects and provide a new algorithm of our own. This new algorithm can be regarded as a generalization of the standard LRU algorithm. We examine the performance of this and other Web caching algorithms via event- and trace-driven simulation.
Numerical Strategies for Solving the Nonlinear Rational Expectations Commodity Market Model
Authors: Mario J. Miranda
Venue: Computational Economics (1998)

In this paper, I compare the accuracy, efficiency and stability of different numerical strategies for computing approximate solutions to the nonlinear rational expectations commodity market model. I find that polynomial and spline function collocation methods are superior to the space discretization, linearization and least squares curve-fitting methods that have been preferred by economists in the past.
An Overlaying Technique for Solving Linear Equations in Real-Time Computing
Authors: S. Y. Berkovich
Venue: IEEE Transactions on Computers (1993)

A computer organization for solving a continuous stream of sets of linear equations A*b with relatively close consecutive parameters is described. The conditions of closeness enabling this technique are monitored during the computations. The cycles of the computational process are divided into two stages: finding a solution of a current set of linear equations by multiplying components of a polynomial approximation of the inverse matrix by a right-hand-side vector; and calculating this inverse matrix in order to arrange for an approximation of the next inverse matrix. The former procedure can be performed in O(n/sup 2/) operations, reducing the time for obtaining the solution of linear equations. The more lengthy calculation of the inverse itself, which requires O(n/sup 3/) operations, can overlay the preparation of the upcoming set of equations in the next cycle. The approach can be effectively utilized for organization of real-time computations.
The Next-Generation Internet: Unsafe at Any Speed?
Authors: Kenneth P. Birman
Venue: Computer (2000)

Users who need to run mission-critical applications on the Internet will require functionality unlikely to be available in the Next-Generation Internet (NGI). Traditionally, critical networked applications have exploited physical or logical separation to justify a style of reasoning that considers each application independently. Migrating systems to a shared network infrastructure, however, frequently means isolation loss, compromising the safety argument. Thus a means of achieving and validating safety for NGI applications is necessary. This requires devising a way to isolate applications from one another in shared settings.The author proposes a new networking isolation capability, termed a virtual overlay network, or VON. Although a VON offers a response to the reliability and security needs of critical applications, it would be prohibitively costly to implement using contemporary technologies. This article explains VONs and how extending an existing router feature and coupling it with well-understood group communication techniques could support VONs at low cost, with good scalability.
Fast Indexing and Visualization of Metric Data Sets using Slim-Trees
Authors: C. Traina,  Jr., A. Traina, C. Faloutsos, B. Seeger
Venue: IEEE Transactions on Knowledge and Data Engineering (2002)

Many recent database applications must deal with similarity queries. For such applications, it is important to measure the similarity between two objects using the distance between them. Focusing on this problem, this paper proposes the Slim-tree, a new dynamic tree for organizing metric data sets in pages of fixed size. The Slim-tree uses the triangle inequality to prune distance calculations needed to answer similarity queries over objects in metric spaces. The proposed insertion algorithm uses new policies to select the nodes where incoming objects are stored. When a node overflows, the Slim-tree uses a Minimal Spanning Tree to help with the split. The new insertion algorithm leads to a tree with high storage utilization and improved query performance. The Slim-tree is the first metric access method to tackle the problem of overlap between nodes in metric spaces and to propose a technique to minimize it. The proposed ¿fat-factor¿ is a way to quantify whether a given tree can be improved and also to compare two trees. We show how to use the fat-factor to achieve accurate estimates of the search performance and also how to improve the performance of a metric tree through the proposed ¿Slim-down¿ algorithm. This paper also presents a new tool in the arsenal of resources of Slim-tree aimed at visualizing it. Visualization is a powerful tool for interactive data mining and for the visual tracking of the behavior of a tree under updates. Finally, we present a formula to estimate the number of disk accesses in range queries. Results from experiments with real and synthetic data sets show that the new algorithms of the Slim-tree lead to performance improvements. These results show that the Slim-tree outperforms the M-tree up to 200 percent for range queries. For insertion and split, the Minimal-Spanning-Tree-based algorithm achieves up to 40 times faster insertions. We observed improvements up to 40 percent in range queries after applying the Slim-down algorithm.
Query Optimization in Multidatabase Systems Considering Schema Conflicts
Authors: Chiang Lee, Chia-Jung Chen
Venue: IEEE Transactions on Knowledge and Data Engineering (1997)

In a multidatabase system, the participating databases are autonomous. The schemas of these databases may be different in various ways, while the same information is represented. A global query issued against the global database needs to be translated to a proper form before it can be executed in a local database. Since data requested by a query (or a part of a query) is sometimes available in multiple sites, the site (database) that processes the query with the least cost is the desired query processing site. In this paper, we study the effect of differences in schemas on the cost of query processing in a multidatabase environment. We first classify schema conflicts to different types. For each type of conflict, we show how much more or less complex a translated query can become in comparison with the originally user-issued global query. Based on this observation, we propose an analytical method that considers the conflicts between local databases and finds the database(s) that renders the least execution cost in processing a global query. This research introduces a new level of query optimization (termed the schema-level optimization) in multidatabase environments. Our results provide a new dimension of enhancement for the capability of query optimizer in multidatabase systems.
Deductive Fault Simulation for Sequential Module Circuits
Authors: K. Walczak
Venue: IEEE Transactions on Computers (1988)

A cost-effective method is presented for the deductive simulation of fault effects propagating through sequential functional modules that are described by the state-diagram representation of a Moore or Mealy automaton. The cornerstone of the method is a novel definition of the internal fault list of a sequential module. The method can be particularly useful for sequential modules when the state assignment and the gate-level realization are unknown.
Optimal finite-precision approximation of FIR Filters
Authors: Wei-Yong Yan, Kok Lay Teo
Venue: Signal Processing (2002)

This paper treats the problem of optimal approximation of a given FIR filter by a discrete coefficient FIR filter for fast implementation in hardware. It is shown that the problem can be arbitrarily closely approximated by problems of optimization over a certain smooth compact manifold. Two simple algorithms, which are defined in terms of an ordinary differential equation and a recursive equation, respectively, are derived and guaranteed to be convergent.
An Optimal Scheduling Algorithm Based on Task Duplication
Authors: C. I. Park, T. Y. Choe
Venue: IEEE Transactions on Computers (2002)

Under the condition where communication time is relatively shorter than the computation time for a given task, the task duplication-based scheduling (TDS) algorithm proposed by Darbha and Agrawal generates an optimal schedule. In this paper, we propose an extended TDS algorithm whose optimality condition is less restricted and the length of the generated schedule is shorter than the TDS algorithm.
Starburst Mid-Flight: As the Dust Clears
Authors: L. M. Haas, W. Chang, G. M. Lohman, J. McPherson, P. F. Wilms, G. Lapis, B. Lindsay, H. Pirahesh, M. J. Carey, E. Shekita
Venue: IEEE Transactions on Knowledge and Data Engineering (1990)

The purpose of the Starburst project is to improve the design of relational database management systems and enhance their performance, while building an extensible system to better support nontraditional applications and to serve as a testbed for future improvements in database technology. The design and implementation of the Starburst system to date are considered. Some key design decisions and how they affect the goal of improved structure and performance are examined. How well the goal of extensibility has been met is examined: what aspects of the system are extensible, how extensions can be done, and how easy it is to add extensions. Some actual extensions to the system, including the experiences of the first real customizers, are discussed.
Reducing System Cost with Software Modems
Authors: Dave Walsh
Venue: IEEE Micro (1997)

Modern 32-bit RISC processors can be used to implement many functions, including signal processing, in software, thus replacing hardware components and thus reducing system cost and complexity. The embedded software market is poised for dramatic growth as engineers and organizations look to third party suppliers of software components to reduce time to market and allow focus on the core competencies that determine key market differentiation for OEMs. The voice and data communications markets, including Internet access, is fuelling this growth. A large and increasing number of products are shipping that offer modem functionality. Until recently, the only way to implement this in an end product was to buy-in a packaged solution containing a microprocessor and DSP element bundled with the necessary software in ROM to function as a modem. Because of the capabilities of modern RISC processors, this same software can be executed cost effectively by the main system CPU. The modem industry is governed by standards that guarantee interoperability, so exactly the same functionality can be had from software running on the system CPU. This results in many advantages over the traditional approach: Reduced Bill of Materials cost for the product, Reduced board space (lower cost), Reduced manufacturing cost, Lower power consumption, Software flexibility enables future upgrades. This article introduces software modem technology and the requirements it places upon CPUs, describes how the Advanced RISC Machines (ARM) RISC architecture is ideally suited to exploit the advantages of software modems, describes the benchmarking results of different software modem technology implemented on different ARM processor architectures and finally discusses some practical issues for the OEM designer wishing to take advantage of software modems.
Representation and Self-Similarity of Shapes
Authors: Davi Geiger, Tyng-Luh Liu, Robert V. Kohn
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (2003)

Representing shapes in a compact and informative form is a significant problem for vision systems that must recognize or classify objects. We describe a compact representation model for two-dimensional (2D) shapes by investigating their self-similarities and constructing their shape axis trees (SA-trees). Our approach can be formulated as a variational one (or, equivalently, as MAP estimation of a Markov random field). We start with a 2D shape, its boundary contour, and two different parameterizations for the contour (one parameterization is oriented counterclockwise and the other clockwise). To measure its self-similarity, the two parameterizations are matched to derive the best set of one-to-one point-to-point correspondences along the contour. The cost functional used in the matching may vary and is determined by the adopted self-similarity criteria, e.g., cocircularity, distance variation, parallelism, and region homogeneity. The loci of middle points of the pairing contour points yield the shape axis and they can be grouped into a unique free tree structure, the SA-tree. By implicitly encoding the (local and global) shape information into an SA-tree, a variety of vision tasks, e.g., shape recognition, comparison, and retrieval, can be performed in a more robust and efficient way via various tree-based algorithms. A dynamic programming algorithm gives the optimal solution in O(N^4), where N is the size of the contour.
A Methodology to Retrieve Text Documents from Multiple Databases
Authors: Clement Yu, King-Lup Liu, Weiyi Meng, Zonghuan Wu, Naphtali Rishe
Venue: IEEE Transactions on Knowledge and Data Engineering (2002)

This paper presents a methodology for finding the n most similar documents across multiple text databases for any given query and for any positive integer n. This methodology consists of two steps. First, the contents of databases are indicated approximately by database representatives. Databases are ranked using their representatives with respect to the given query. We provide a necessary and sufficient condition to rank the databases optimally. In order to satisfy this condition, we provide three estimation methods. One estimation method is intended for short queries; the other two are for all queries. Second, we provide an algorithm, OptDocRetrv, to retrieve documents from the databases according to their rank and in a particular way. We show that if the databases containing the n most similar documents for a given query are ranked ahead of other databases, our methodology will guarantee the retrieval of the n most similar documents for the query. When the number of databases is large, we propose to organize database representatives into a hierarchy and employ a best-search algorithm to search the hierarchy. It is shown that the effectiveness of the best-search algorithm is the same as that of evaluating the user query against all database representatives.
A Method for Speed Optimized Partial Product Reduction and Generation of Fast Parallel Multipliers Using an Algorithmic Approach
Authors: Vojin G. Oklobdzija, David Villeger, Simon S. Liu
Venue: IEEE Transactions on Computers (1996)

This paper presents a method and an algorithm for generation of a parallel multiplier, which is optimized for speed. This method is applicable to any multiplier size and adaptable to any technology for which speed parameters are known. Most importantly, it is easy to incorporate this method in silicon compilation or logic synthesis tools. The parallel multiplier produced by the proposed method outperforms other schemes used for comparison in our experiment. It uses the minimal number of cells in the partial product reduction tree. These findings are tested on design examples simulated in 1¿ CMOS ASIC technology.
Speakers' direction finding using estimated time delays in the frequency domain
Authors: Baruch Berdugo, Judith Rosenhouse, Haim Azhari
Venue: Signal Processing (2002)

Speaker localization is an important issue in the study of human communication, and is related to a variety of practical applications. When two or more speakers speak simultaneously, finding the direction of arrival of the speech signals is a complicated task. The spectral separation between different speech signals was first quantified. Some 40%, in the mean sense, of the spectral information for the 0-5 kHz band were found to differ significantly (by at least 10 dB) between any two speakers, even when they speak the same utterance at the same time and with the same intensity. Signals in the frequency domain were analyzed to transform the problem into a set of single-source single-frequency problems. This made it possible to apply a time delay direction finding (TDDF) algorithm (Berdugo et al., J. Acoust. Soc. Am. 105 (6) (1999) 3355). Next, a new "fusion" algorithm was developed which extended the solution to separate the speech signals of two speakers at low SNR values. The results obtained in simulations as well as in actual experimental studies, demonstrated high angular resolution between two speakers (approximately 20° for a 10 cm array extent) even at low SNR ratios. This algorithm may be suitable for various applications, such as video conferencing and hearing aids.
On-Chip IDDQ Testing in the AE11 Fail-Stop Controller
Authors: Eberhard Böhl, Thomas Lindenkreuz, Matthias Meerwein
Venue: IEEE Design Test (1998)

The development of the Fail-Stop Controller AE11 aimed at the replacement of the classic safety structure, using two identical controllers, by a single controller with various online fault detection measures. Target applications are high-volume products like automotive and railway safety electronics. For these applications the reduction of chip area related costs without reducing the degree of safety is an important task. A short reaction time to occurring faults is needed, too. These requirements lead to the use of a combination of Concurrent Checking, Built-In Self-Test and Built-In Current-Monitoring (IDDQ-Test) which give the controller the so called "fail-stop" property. On-chip measurement of the quiescent current (IDDQ) of the logic circuitry provides a way of detecting a class of hardware faults that cause an abnormal leakage current and is achieved by inserting current monitoring cells in the power supply lines of the (appropriately partitioned) functional logic of the module. On the other hand Concurrent Checking is an indispensable part of the test concept at least for such components which contain vital information within the application (e.g. ALU registers and RAM). To incorporate all these on-chip fault detection measures the standard cell based design flow had to be considerably extended. This paper outlines the design of an appropriate current monitor cell as well as the methodologies and in-house tools supplementing a modern standard design flow to constitute a consistent and robust design environment for this controller.