ppxscal/embedding_network huggingface dataset:
Pivoted Cauchy-Like Preconditioners for Regularized Solution of Ill-Posed Problems
Authors: Misha E. Kilmer, Dianne P. O'Leary
Venue: SIAM Journal on Scientific Computing (1999)

Many ill-posed problems are solved using a discretization that results in a least squares problem or a linear system involving a Toeplitz matrix. The exact solution to such problems is often hopelessly contaminated by noise, since the discretized problem is quite ill conditioned, and noise components in the approximate null-space dominate the solution vector. Therefore we seek an approximate solution that does not have large components in these directions. We use a preconditioned conjugate gradient algorithm to compute such a regularized solution. A unitary change of coordinates transforms the Toeplitz matrix to a Cauchy-like matrix, and we choose our preconditioner to be a low rank Cauchy-like matrix determined in the course of Gu's fast modified complete pivoting algorithm. We show that if the kernel of the ill-posed problem is smooth, then this preconditioner has desirable properties: the largest singular values of the preconditioned matrix are clustered around one, the smallest singular values, corresponding to the lower subspace, remain small, and the upper and lower spaces are relatively unmixed. The preconditioned algorithm costs only O(n lg n) operations per iteration for a problem with n variables. The effectiveness of the preconditioner for filtering noise is demonstrated on three examples.
The Timed Asynchronous Distributed System Model
Authors: Flaviu Cristian, Christof Fetzer
Venue: IEEE Transactions on Parallel and Distributed Systems (1999)

We propose a formal definition for thetimed asynchronous distributed system model. We present extensive measurements of actual message and process scheduling delays and hardware clock drifts. These measurements confirm that this model adequately describes current distributed systems such as a network of workstations. We also give an explanation of why practically needed services, such as consensus or leader election, which are not implementable in the time-free model, are implementable in the timed asynchronous system model.
Partitioning Customers Into Service Groups
Authors: Christos Alexopoulos, Akram A. El-Tannir, Richard F. Serfozo, Ward Whitt
Venue: Management Science (1999)

We explore the issues of when and how to partition arriving customers into service groups that will be served separately, in a first-come first-served manner, by multiserver service systems having a provision for waiting, and how to assign an appropriate number of servers to each group. We assume that customers can be classified upon arrival, so that different service groups can have different service-time distributions. We provide methodology for quantifying the tradeoff between economies of scale associated with larger systems and the benefit of having customers with shorter service times separated from other customers with longer service times, as is done in service systems with express lines. To properly quantify this tradeoff, it is important to characterize service-time distributions beyond their means. In particular, it is important to also determine the variance of the service-time distribution of each service group. Assuming Poisson arrival processes, we then can model the congestion experienced by each server group as an M/G/s queue with unlimited waiting room. We use previously developed approximations for M/G/s performance measures to quickly evaluate alternative partitions.
A Performance Analysis of Appel's Algorithm for Performing Pairwise Calculations in a Many Particle System
Authors: M. S. Hingst, A. T. Phillips
Venue: Computational Optimization and Applications (1999)

Appel's algorithm for efficiently performing pairwise potential energy calculations is analyzed with regard to both computing time required and error incurred. Four factors are identified which determine the practical value of Appel's method: the total number of particles in the system, the tolerance for error in the calculations, the complexity of the pairwise energy calculation, and the spacial distribution of the particles.
Embedding security policies into a distributed computing environment
Authors: Udo Halfmann, Winfried E. Kühnhauser
Venue: ACM SIGOPS Operating Systems Review (1999)

This paper discusses the implementation of security policies in multipolicy systems. Multipolicy systems are systems supporting a multitude of security policies, each policy governing the applications within its own and precisely defined security domain.The paper argues that within multipolicy systems, traditional approaches for implementing security policies such as security kernels are both too weak and too strong. In order to support this thesis, we will discuss architectural issues of the implementation of policy separation, policy persistency, total mediation and putting off-the-shelf applications under the control of security policies. Whenever our statements are illustrated by examples, these examples are taken from a case study we implemented for the OSF Distributed Computing Environment.
ATM Architectures Using Optical Technology: An Overview of Switching, Buffering and Multiplexing
Authors: M. Guizani
Venue: International Journal of Network Management (1997)

This overview presents recent studies on photonic switches and discusses the existing different types, such as space-division switches, free-space switches, time-division switches, wavelength division switches, and frequency division switches. The architectures and applications of these switches are also discussed. &copy; 1997 John Wiley Sons, Ltd.
Computer speech: streaming technology
Authors: Judith M. Myerson
Venue: International Journal of Network Management (2000)

Have you ever listened to a talking Web page&dagger; that became speechless in five minutes&quest; Have you found it embarrassing while in a conference room of corporate executives&quest; Have you ever wished the computer talker would slow down a little bit, so a decision maker can understand it&quest; In answering these questions, we need to consider not only how the answers address the impacts of streaming technology on computer speech but also how they may affect global decision makers. Copyright &copy; 2000 John Wiley Sons, Ltd.
Second-Order Conditions for Optimization Problems with Constraints
Authors: Jean-Paul Penot
Venue: SIAM Journal on Control and Optimization (1999)

Using a projective approach, new necessary conditions and new sufficient conditions for optimization problems with explicit or implicit constraints are examined. They are compared to previous ones. A particular emphasis is given to mathematical programming problems with non-polyhedral constraints. This case occurs in particular when the constraints are defined in functional spaces.
A Semicoarsening Multigrid Method for Elliptic Partial Differential Equations with Highly Discontinuous and Anisotropic Coefficients
Authors: Steve Schaffer
Venue: SIAM Journal on Scientific Computing (1998)

The purpose of this paper is to present a semicoarsening multigrid algorithm for solving the finite difference discretization of symmetric and nonsymmetric, two- and three-dimensional elliptic partial differential equations with highly discontinuous and anisotropic coefficients. The discrete equations are assumed to be defined on a logically rectangular grid, obtained possibly through grid generation for a problem defined on an irregular domain. The basic algorithm is described along with some modifications which are designed to improve its efficiency and robustness for certain types of problem cases. FORTRAN codes that implement the two- and three-dimensional semicoarsening multigrid algorithms are described briefly, and numerical results are presented.
Distance learning model with local workshop sessions applied to in-service teacher training
Authors: Bruria Haberman, David Ginat
Venue: ACM SIGCSE Bulletin (1999)

This paper presents the development, implementation and evaluation of a novel distance learning model integrated with local workshop sessions. The model was developed for a large-scale in-service teacher training, and applied to introduce a new computer science curriculum and its didactic approach. The model evaluation showed a significant success, both in terms of participants' attitudes, and the assimilation of the subject matter and its didactic approach.
Multiple-banked register file architectures
Authors: José-Lorenzo Cruz, Antonio González, Mateo Valero, Nigel P. Topham
Venue: ACM SIGARCH Computer Architecture News (2000)

The register file access time is one of the critical delays in current superscalar processors. Its impact on processor performance is likely to increase in future processor generations, as they are expected to increase the issue width (which implies more register ports) and the size of the instruction window (which implies more registers), and to use some kind of multithreading. Under this scenario, the register file access time could be a dominant delay and a pipelined implementation would be desirable to allow for high clock rates. However, a multi-stage register file has severe implications for processor performance (e.g. higher branch misprediction penalty) and complexity (more levels of bypass logic). To tackle these two problems, in this paper we propose a register file architecture composed of multiple banks. In particular we focus on a multi-level organization of the register file, which provides low latency and simple bypass logic. We propose several caching policies and prefetching strategies and demonstrate the potential of this multiple-banked organization. For instance, we show that a two-level organization degrades IPC by 10% and 2% with respect to a non-pipelined single-banked register file, for SpecInt95 and SpecFP95 respectively, but it increases performance by 87% and 92% when the register file access time is factored in.
Decoupling local variable accesses in a wide-issue superscalar processor
Authors: Sangyeun Cho, Pen-Chung Yew, Gyungho Lee
Venue: Proceedings of the 26th annual international symposium on Computer architecture (1999)

Providing adequate data bandwidth is extremely important for a wide-issue superscalar processor to achieve its full performance potential. Adding a large number of ports to a data cache, however, becomes increasingly inefficient and can add to the hardware complexity significantly. This paper takes an alternative or complementary approach for providing more data bandwidth, called the data-decoupled architecture. The approach, with support from the compiler and/or hardware, partitions the memory stream into two independent streams early in the processor pipeline, and feeds each stream to a separate memory access queue and cache. Under this model, the paper studies the potential of decoupling memory accesses to program's local variables that are allocated on the run-time stack. Using a set of integer and floating-point programs from the SPEC95 benchmark suite, it is shown that local variable accesses constitute a large portion of all the memory references, while their reference space is very small, averaging around 7 words per (static) procedure. To service local variable accesses quickly, two optimizations, fast data forwarding and access combining, are proposed and studied. Some of the important design parameters, such as the cache size, the number of cache ports, and the degree of access combining, are studied based on simulations. The potential performance of the proposed scheme is measured using various configurations, and it is concluded that the scheme can become a viable alternative to building a single multi-ported data cache.
Allowing for ILP in an embedded Java processor
Authors: Ramesh Radhakrishnan, Deependra Talla, Lizy Kurian John
Venue: ACM SIGARCH Computer Architecture News (2000)

Java processors are ideal for embedded and network computing applications such as Internet TV's, set-top boxes, smart phones, and other consumer electronics applications. In this paper, we investigate cost-effective microarchitectural techniques to exploit parallelism in Java bytecode streams. Firstly, we propose the use of a fill unit that stores decoded bytecodes into a decoded bytecode cache. This mechanism improves the fetch and decode bandwidth of Java processors by 2 to 3 times. These additional hardware units can also be used to perform optimizations such as instruction folding. This is particularly significant because experiments with the Verilog model of Sun Microsystems pico Java-II core demonstrates that instruction folding lies in the critical path. Moving folding logic from the critical path of the processor to the fill unit allows to improve the clock frequency by 25%. Out-of-order ILP exploitation is not investigated due to the prohibitive cost, but in-order dual-issue with a 64-entry decoded bytecode cache is seen to result in 10% to 14% improvement in execution cycles. Another contribution of the paper is a stack disambiguation technique that allows elimination of false dependencies between different types of stack accesses. Stack disambiguation further exposes parallelism and a dual in-order issue microengine with a 64-entry bytecode cache yields an additional 10% reduction in cycles, leading to an aggregate reduction of 17% to 24% in execution cycles.
An overview of regression testing
Authors: Nancy J. Wahl
Venue: ACM SIGSOFT Software Engineering Notes (1999)

Regression testing is an important part of the software development life cycle. Many articles have been published lately detailing the different approaches. This article is an overview of regression testing in the following areas: types of regression testing; unit, integration and system level testing, regression testing of global variables, regression testing of object-oriented software, comparisons of selective regression techniques, and cost comparisons of the types of regression testing.
Operating-system directed power reduction
Authors: Yung-Hsiang Lu, Luca Benini, Giovanni De Micheli
Venue: Proceedings of the 2000 international symposium on Low power electronics and design (2000)

this paper presents a new approach for power reduction by taking a global, software-centric view. It analyzes the sources of power consumption: tasks that require services from hardware components. When a component is not used by any task, it can enter a sleeping state to save power. Operating systems have detailed information about tasks; therefore, OS is the best place for identifying hardware idleness and shutting down unused components. We implement this technique in Linux and show that it can save more than 50% power compared to traditional hardware-centric shutdown techniques.
Internet Usage and Potential Impact for Acute Care Hospitals: Survey in the United States
Authors: Myron Hatcher
Venue: Journal of Medical Systems (1998)

These survey results are from a national survey of acute care hospitals. A random sample of 813 hospitals was selected with 115 responding and 33 incorrect addresses resulting in a 15% response rate. The purpose of the study was to measure the extent of information systems integration in the financial, medical, and administrative systems of the hospitals. Internet usage including homepages and advertising was measured. Other selected telecommunication applications are analyzed. As demonstration projects from the literature are compared to the survey results, the potential for hospitals is tremendous. Resulting cost savings could be equally impressive. This information will provide a benchmark for hospitals to determine their position relative to Internet technology and to set goals.
Probabilistic Analyses and Algorithms for Three-Level Distribution Systems
Authors: Lap Mui Ann Chan, David Simchi-Levi
Venue: Management Science (1998)

We consider the problem of integrating inventory control and vehicle routing into a cost-effective strategy for a distribution system consisting of a single outside vendor, a fixed number of warehouses and many geographically dispersed retailers. Each retailer faces a constant, retailer specific, demand rate and inventory holding cost is charged at the retailers and the warehouses. We show that, in an effective strategy which minimizes the asymptotic long run average cost, each warehouse receives fully loaded trucks from the vendor but never holds inventory. That is, each warehouse serves only as a coordinator of the frequency, time and sizes of deliveries to the retailers. This insight is used to construct an inventory control policy and vehicle routing strategy for multi-echelon distribution systems. Computational results are also reported.
Products and Help Bits in Decision Trees
Authors: Noam Nisan, Steven Rudich, Michael Saks
Venue: SIAM Journal on Computing (1999)

We investigate two problems concerning the complexity of evaluating a function f on k distinct inputs by k parallel decision-tree algorithms.In the product problem, for some fixed depth bound d, we seek to maximize the fraction of input k-tuples for which all k decision trees are correct. Assume that for a single input to f, the best depth-d decision tree is correct on a fraction p of inputs. We prove that the maximum fraction of k-tuples on which k depth-d algorithms are all correct is at most pk, which is the trivial lower bound. We show that if we replace the restriction to depth d by "expected depth d," then this result need not hold.In the help-bits problem, before the decision-tree computations begin, up to k-1 arbitrary binary questions (help-bit queries) can be asked about the k-tuple of inputs. In the second stage, for each possible (k-1)-tuple of answers to the help-bit queries, there is a k-tuple of decision trees where the ith tree is supposed to correctly compute the value of the function on the ith input, for any input that is consistent with the help bits. The complexity here is the maximum depth of any of the trees in the algorithm. We show that for all k sufficiently large, this complexity is equal to degs(f), which is the minimum degree of a multivariate polynomial whose sign is equal to f.
Software process validation: quantitatively measuring the correspondence of a process to a model
Authors: Jonathan E. Cook, Alexander L. Wolf
Venue: ACM Transactions on Software Engineering and Methodology (TOSEM) (1999)

To a great extent, the usefulness of a formal model of a software process lies in its ability to accurately predict the behavior of the executing process. Similarly, the usefulness of an executing process lies largely in its ability to fulfill the requirements embodied in a formal model of the process. When process models and process executions diverge, something significant is happening. We have developed techniques for uncovering and measuring the discrepancies between models and executions, which we call process validation. Process validation takes a process execution and a process model, and measures the level of correspondence between the two. Our metrics are tailorable and give process engineers control over determining the severity of different types of discrepancies. The techniques provide detailed information once a high-level measurement indicates the presence of a problem. We have applied our processes validation methods in an industrial case study, of which a portion is described in this article.
Valuation of Investments in Real Assets with Implications for the Stock Prices
Authors: Thomas S. Knudsen, Bernhard Meister, Mihail Zervos
Venue: SIAM Journal on Control and Optimization (1998)

A general model for the valuation of natural resource investments is formulated and analyzed within a stochastic control theoretic framework. Using dynamic programming, the value of such an investment with a general payoff function is determined under the assumption that the commodity price process is given by a stochastic differential equation. The analysis results in closed form analytic solutions which can easily be computed and exhibits qualitatively different optimal behaviors, depending on parameter values. Implications for stocks and options are also considered.
Biologically-Inspired On-Chip Learning in Pulsed Neural Networks
Authors: Torsten Lehmann, Robin Woodburn
Venue: Analog Integrated Circuits and Signal Processing (1999)

Self-learning chips to implement many popular ANN (artificial neural network) algorithms are very difficult to design. We explain why this is so and say what lessons previous work teaches us in the design of self-learning systems. We offer a contribution to the &ldquo;biologically-inspired&rdquo; approach, explaining what we mean by this term and providing an example of a robust, self-learning design that can solve simple classical-conditioning tasks. We give details of the design of individual circuits to perform component functions, which can then be combined into a network to solve the task. We argue that useful conclusions as to the future of on-chip learning can be drawn from this work.
Colorful examples for elaborating exploration of regularities in high-school CS1
Authors: David Ginat
Venue: Proceedings of the 5th annual SIGCSE/SIGCUE ITiCSEconference on Innovation and technology in computer science education (2000)

Exploration of regularities is a key element in problem analysis - the primary stage of algorithm design. The recognition of regularities during problem analysis elicits underlying principles of the design. While university teachers are well aware of the significance of regularities, high-school computer science teachers often fail to appreciate it, and focus on technical details of program design and implementation. We believe that the elaboration of regularities in high-school computer science education enhances teachers' and students' scientific conception of computer science.In this paper we present an approach for elaborating the role of regularities. The elaboration is done by directing the students, at the primary stage of problem analysis, to look for problem characteristics from various angles, in different ways, and for diverse tasks. Our approach is based on colorful and attractive examples, which include challenging problems and games, often with physical objects. Such examples enrich the students' intuition, and leave a long-term imprint.
On event ordering in parallel discrete event simulation
Authors: Robert Rönngren, Michael Liljenstam
Venue: Proceedings of the thirteenth workshop on Parallel and distributed simulation (1999)

Ordering of simultaneous events in DES is an important issue as it has an impact on modelling expressiveness, model correctness as well as causal dependencies. In sequential DES this is a problem which has attracted much attention over the years and most systems provide the user with tools to deal with such issues. This has also attracted some attention within the PDES community and we present an overview of these efforts. We have, however, not yet found a scheme which provides us with the desired functionality. Thus, we present and evaluate some simple schemes to achieve a well defined ordering of events and means to identify both causally dependent and independent events with identical timestamps in the context of optimistic simulations. These schemes should be applicable also to conservative PDES.