ppxscal/embedding_network huggingface dataset:
Distributed Fault Diagnosis in Multistage Network-Based Multiprocessors
Authors: Woei Lin, Tsang-Ling Sheu, Chita R. Das
Venue: IEEE Transactions on Computers (1995)

This paper is concerned with a distributed, system-level fault diagnosis scheme for multistage network-based multiprocessors. The target system, which we choose as a representative, employs a multistage interconnection network (MIN) with 4 × 4 switching elements. We propose a fast diagnostic method which uses a quadtree [1] and its coupler structure. These two quadtree structures partition the system into a number of Link-Independent Groups (LIGs). This partitioning provides an important diagnostic property; the communication paths in each LIG are either identical or disjoint. Several previous works in fault diagnosis investigated the multistage interconnection network only. This paper presents an entire multiprocessor diagnosis, including the detection and location of single faults caused by processor nodes, switching elements, and communication links. In addition, the diagnosis of a group of multiple faults partitioned by the tree structures is also discussed.
A Performance Comparison of Locking Methods with Limited Wait Depth
Authors: Alexander Thomasian
Venue: IEEE Transactions on Knowledge and Data Engineering (1997)

A number of recent studies have proposed lock conflict resolution methods to improve the performance of standard locking, i.e., strict two-phase locking with the general waiting method. This paper is primarily concerned with the performance of wait depth limited methods with respect to each other and some other methods. The methods considered include the general waiting, wound-wait, and no-waiting methods, symmetric and asymmetric versions of cautious waiting and running priority methods, the wait depth limited (WDL) method, and a modified version of it. In spite of the availability of analytic solutions for most of wait depth limited methods, for reasons given in the paper, the performance comparison is based on simulation results. The contributions of this study are as follows: 1) modeling assumptions, i.e., a careful definition of transaction restart options; 2) new results concerning the relative performance of wait depth limited methods, which show that a) the running priority method outperforms cautious waiting and may even outperform the WDL method in a system with limited hardware resource, b) WDL outperforms other methods in high lock contention, high capacity systems, and c) modified WDL has a performance comparable to WDL, but incurs less overhead in selecting the abort victim; and 3) contrary to common belief, Tay's Effective Database Size Paradigm for dealing with shared and exclusive locks and/or skewed database accesses in standard locking is applicable to some wait depth limited methods and provides acceptably accurate approximations in others¿as long as locking modes for restarted transactions are not resampled.
Simplistic dynamic image based rendering
Authors: Niklas Bakos, Claes Järvman, Mark Ollila
Venue: Proceedings of the 1st international conference on Computer graphics and interactive techniques in Australasia and South East Asia (2003)

We present a very inexpensive way of creating dynamic image-based renderings of digitally recorded, photo realistic, real-life objects. Together with computer vision algorithms, the recorded person is visualized using the Relief Texture Mapping algorithm [Oliveira et al. 2000]. This mapping technique requires depth information for all texels representing the recorded object from all recorded views. By using two digital video cameras, the dynamic object is recorded in stereo in different views to cover its whole volume. As the depth information from the separate views is generated by stereo correlation, it is used together with the recorded video as relief textures on a pre-defined bounding box and morphed into a three dimensional representation by justifying the known depth disparities.
On Computing Multiplicative Inverses in GF(2/sup m/)
Authors: H. Brunner, A. Curiger, M. Hofstetter
Venue: IEEE Transactions on Computers (1993)

The design of a modular standard basis inversion for Galois fields GF(2/sup m/) based on Euclid's algorithm for computing the greatest common divisor of two polynomials is presented. The asymptotic complexity is linear with m both in computation time and area requirement, thus resulting in an AT-complexity of O(m/sup 2/). This is a significant improvement over the best previous proposal which achieves AT-complexity of only O(m/sup 3/).
Object-Oriented Intelligent Computer-Integrated Design, Process Planning, and Inspection
Authors: M. Marefat, Sandeep Malhotra, R. L. Kashyap
Venue: Computer (1993)

The methodology for developing intelligent integrated computer-aided design and manufacturing systems based on object-oriented principles is discussed. The ways in which the application of these principles affects the nature of these systems are reviewed. The implementation of an automated, intelligent, and flexible computer-integrated-manufacturing (CIM) system prototype using an object-oriented programming environment (Smalltalk-80, Version 4.0) is detailed. A CIM system includes CAD, a process planner, and an inspection planner. Each of these components is discussed individually.
Standards
Venue: IEEE Design Test (2002)

(available without subscription)No abstract available.
Software Component Certification
Authors: John Morris, Gareth Lee, Kris Parker, Gary A. Bundell, Chiou Peng Lam
Venue: Computer (2001)

Most current process-based methods for certifying software require software publishers to"take oaths concerning which development standards and processes they will use." Jeffrey Voas, among others, has suggested that independent agencies¿software certification laboratories (SCLs)¿should take on a product certification role. The authors accept that this approach may work well for certain software distribution models, but they also observe that it cannot be applied to all software development.Third-party SCLs would add unnecessarily to the costs that small developers incur by speculating on the success of a given component. However, supplying complete test sets with components incurs little additional cost because component authors must generate the tests in the first place. Any extra effort adds value to a component because a tested component certainly offers a more marketable commodity.The authors believe that while SCLs have a place in large or safety-critical software projects, there will always be small commercial-software developments for which failure represents a moderate cost. In such cases, the cost of generating and inspecting tests can be justified.
Modelling roughness, grain and confinement effects on transport in embedded metallic films
Authors: Gary D. Knight, Tom Smy
Venue: Microelectronic Engineering (2002)

Roughness and grain effects in nanowires or oxide-embedded damascene ULSI structures are modelled using a pseudo-Monte Carlo carrier particle optics (CPO) method [MRS Advanced Metallization Conference for ULSI applications (AMC 2001) (2002) 371], matching experimental data on aluminum and platinum films and electrodeposited copper wire. Diffuse scatter from rough and specular scatter from uneven geometric surfaces is considered. Diffusive results accord with Sambles and Elsom [J. Phys. F 11 (1981) 647; J. Phys. F 10 (1980) 1487], matching temperature-dependent resistivities in very thin films more closely than Fuchs and Sondheimer [Proc. Cambridge Phil. Soc. 34 (1938) 100; Adv. Phys. 1 (1952) 1]. Grain profile effects improve the model of resistance increase in embedded structures, suggesting directions for improving conduction through enlarged grain cross-section.
Uniquely colorable mixed hypergraphs
Authors: Zsolt Tuza, Vitaly Voloshin, Huishan Zhou
Venue: Discrete Mathematics (2002)

A mixed hypergraph consists of two families of edges: the C-edges and D-edges. In a coloring, every C-edge has at least two vertices of the same color, while every D-edge has at least two vertices colored differently. The largest and smallest possible numbers of colors in a coloring are termed the upper and lower chromatic number, χ and χ, respectively. A mixed hypergraph is called uniquely colorable if it has precisely one coloring apart from the permutation of colors. We begin a systematic study of uniquely colorable mixed hypergraphs.In particular, we show that every colorable mixed hypergraph can be embedded into some uniquely colorable mixed hypergraph; we investigate the role of uniquely colorable subhypergraphs being separators, study recursive operations (orderings and subset contractions) and unique colorings, and prove that it is NP-hard to decide whether a mixed hypergraph is uniquely colorable.We also discuss the weaker property where the mixed hypergraph has a unique coloring with χ colors and a unique coloring with χ colors, where χ > χ. The class of these "weakly uniquely colorable" mixed hypergraphs contains all uniquely colorable graphs in the usual sense.
Optimal VLSI Networks for Multidimensional Transforms
Authors: H. M. Alnuweiri
Venue: IEEE Transactions on Parallel and Distributed Systems (1994)

This paper presents a new class of AT/sup 2/-optimal networks for computing themultidimensional discrete Fourier transform. Although optimal networks have beenproposed previously, the networks proposed in this paper are based on a newmethodology for mapping large K-shuffle networks, K/spl ges/2, onto smaller areanetworks that maintain the optimality of the DFT network. Such networks are used toperform the index-rotation operations needed by the multidimensional computation. Theresulting networks have simple regular layouts, and can be easily partitioned among several chips in order to reduce the number of input-output pins per chip.
Cochannel Interference in Cellular Fixed Broadband Access Systems with Directional Antennas
Authors: Salina Q. Gong, David Falconer
Venue: Wireless Personal Communications: An International Journal (1999)

The Cellular Fixed Broadband Access System for LMCS (Local Multipoint Communication Services) is aiming to provide broadband services to fixed subscribers through wireless access. A representative LMCS scenario involves a cellular system design with the entire allocated bandwidth being used in each cell and with a highly directional antenna employed at the subscriber. The LMCS system designs rely on assumed information regarding radio propagation phenomena in the anticipated coverage areas. The research reported here, therefore, has the objective of verifying such information by theoretical modeling and simulation. Simulation and analysis have been used to study the effects of a number of factors on the system performance and interference characteristics of such a LMCS system. The investigated factors include beamwidth and gain ratio of directional antennas, sectorization of hub antennas, propagation exponent, lognormal shadowing, site diversity and transmitter power control. Both models of LOS (line of sight) and NLOS (non-line of sight) have been investigated in this work. The simulation results demonstrate that highly directional antennas at the subscribers can dramatically improve the system performance for both uplink and downlink. The system design with frequency reuse of one is examined, and it is confirmed that an outage of 0.9% for a NLOS system could be achieved by using narrow beam antennas of 3 degrees with site diversity and power control techniques employed. Under the condition of LOS available for the desired links, the outage can be expected to be as low as 0.3%.
A Blackboard Approach for Diagnosis in Pilot's Associate
Authors: Bruce Pomeroy, Russel Irving
Venue: IEEE Expert: Intelligent Systems and Their Applications (1990)

A description is given of Pilot's Associate (PA), a control-advisory system expected to fly in late-1990s tactical fighter aircraft. PA will improve pilot effectiveness by improving pilot awareness of not only external situations but also the internal status of aircraft systems and options for accommodating faulty equipment. A blackboard architecture was used in developing the internal-awareness function, called system status. To get a clearer view of system status functionality, several examples are given to show how it aids pilots and supports other PA functions. System status architecture is described. Performance testing and evaluation results for PA are presented. Positive characteristics and drawbacks of the current architecture are summarized.
Test Resource Partitioning for SOCs
Authors: Anshuman Chandra, Krishnendu Chakrabarty
Venue: IEEE Design Test (2001)

A new test-resource-partitioning approach, based on test data compression and on-chip decompression, reduces data volume, decreases testing time, and accommodates slower (less expensive) testers without decreasing test quality.
3D Mapping of an Interactive Synthetic Environment
Authors: Roy Ladner, Mahdi Abdelguerfi, Kevin Shaw
Venue: Computer (2000)

Traditional geospatial information systems (GIS) use geographically referenced data to produce highly accurate digital maps. These two-dimensional maps include well-recognized symbols that represent features such as mountains, forests, buildings, and transportation networks. Although this flat view provides an excellent means of orienting the user to the general nature and location of the geographic features for a given area, it does not provide the full experiential value that comes from immersion within a 3D environment.The authors, working in conjunction with the University of New Orleans' Computer Science Department, developed a 3D-GIS to assist the US Marine Corps with mission preparation and rehearsal. It also provides on-site awareness during actual field operations in urban areas.Going beyond presenting stereoscopic views of an area or merely applying photo textures to highly simplified geometric shapes, they created an environment that replicates its real-world counterpart by including detailed 3D objects. The article details the design considerations they faced as well as the implementation and structural overview for the entire system.
A Multiaccess Frame Buffer Architecture
Authors: D. T. Harper,  III
Venue: IEEE Transactions on Computers (1994)

Many current graphical display systems are based around a memory array commonly known as a frame buffer. In these systems, the frame buffer contains the array of pixels currently being displayed. Updates to the display are accomplished by modifying the values in the frame buffer. The author demonstrates how the performance of frame buffer based systems can be improved by decreasing the number of accesses to the frame buffer memory array. The proposed architecture, referred to as a multiaccess frame buffer, allows parallel access to constant area rectangles of the array of pixels stored in the frame buffer rather than the row oriented accesses required by most current frame buffer architectures. By allowing more general types of access, a given update can be performed with fewer frame buffer accesses.
ASSET-2: Real-Time Motion Segmentation and Shape Tracking
Authors: S. m. Smith, J. m. Brady
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1995)

This paper describes a system for detecting and tracking moving objects in a moving world. The feature-based optic flow field is segmented into clusters with affine internal motion which are tracked over time. The system runs in real-time, and is accurate and reliable.
Partial Indexing for Nonuniform Data Distributions in Relational DBMS's
Authors: C. Sartori, M. R. Scalas
Venue: IEEE Transactions on Knowledge and Data Engineering (1994)

It is well known that the effectiveness of relational database systems is greatly dependent on the efficiency of the data access strategies. For this reason, much work has been devoted to the development of new access techniques, supported by adequate access structures such as the B/sup +/trees. The effectiveness of the B/sup +/tree also depends on the data distribution characteristics; in particular, poor performance results when the data show strong key value distribution unbalancing. The aim of this paper is to present the partial index: a new access structure that is useful in such cases of unbalancing, as an alternative to the B/sup +/tree unclustered indexes. The access structures are built in the physical design phase, and at execution (or compilation) time, the optimizer chooses the most efficient access path. Thus, integration of the partial indexing technique in the design and in the optimization process are also described.
Automating Statistics Management for Query Optimizers
Authors: Surajit Chaudhuri, Vivek Narasayya
Venue: IEEE Transactions on Knowledge and Data Engineering (2001)

Statistics play a key role in influencing the quality of plans chosen by a database query optimizer. In this paper, we identify the statistics that are essential for an optimizer. We introduce novel techniques that help significantly reduce the set of statistics that need to be created without sacrificing the quality of query plans generated. We discuss how these techniques can be leveraged to automate statistics management in databases. We have implemented and experimentally evaluated our approach on Microsoft SQL Server 7.0.
Efficient exploration of the SoC communication architecture design space
Authors: Kanishka Lahiri, Anand Raghunathan, Sujit Dey
Venue: Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design (2000)

In this paper, we present a methodology and efficient algorithms for the design of high-performance system-on-chip communication architectures. Our methodology automatically and optimally maps the various communications between system components onto a target communication architecture template that can consist of an arbitrary interconnection of shared or dedicated channels. In addition, our techniques simultaneously configure the communication protocols of each channel in the architecture in order to optimize system performance.We motivate the need for systematic exploration of the communication architecture design space, and highlight the issues involved through illustrative examples. We present a methodology and algorithms that address these issues, including the size and complexity of the design space. We present experimental results on example systems, including a cell forwarding unit of an ATM switch, that demonstrate the benefits of using the proposed techniques. Experimental results indicate that our techniques are successful in achieving significant improvements in system performance over conventional communication architectures (observed speedups over typical architectures such as single shared buses averaged 53%). Moreover, we demonstrate that our design space exploration methodology and optimization algorithms are efficient (low CPU times), underlining their usefulness as part of any system design flow.
Interprocedural compatibility analysis for static object preallocation
Authors: Ovidiu Gheorghioiu, Alexandru Salcianu, Martin Rinard
Venue: ACM SIGPLAN Notices (2003)

We present an interprocedural and compositional algorithm for finding pairs of compatible allocation sites, which have the property that no object allocated at one site is live at the same time as any object allocated at the other site. If an allocation site is compatible with itself, it is said to be unitary: at most one object allocated at that site is live at any given point in the, execution of the program. We use the results of the analysis to statically preallocate memory space for the objects allocated at unitary sites, thus simplifying the computation of an upper bound on the amount of memory required to execute the program. We also use the analysis to enable objects allocated at several compatible allocation sites to share the same preallocated memory. Our experimental results show that, for our set of Java benchmark programs, 60% of the allocation sites are unitary and can be statically preallocated. Moreover, allowing compatible unitary allocation sites to share the same preallocated memory leads to a 95% reduction in the amount of memory preallocated for these sites.
Reducing the variance of point to point transfers in the IBM 9076 parallel computer
Authors: Ronald Mraz
Venue: Proceedings of the 1994 ACM/IEEE conference on Supercomputing (1994)

Commodity workstations have adapted to standard UNIX like environments to allow scientists to efficiently develop and port applications across systems. UNIX based environments, such as IBM's AIX, furnishes such an operating environment while providing efficient uni-processor utilization for user code execution. When these machines are interconnected with a low latency (user space) communication mechanism, large variances in point to point communication times for identical parallel programs are typically found. It is our contention that a large part of this variance is introduced by operating system support functionality that can delay point to point user space communications. We are able to experimentally measure this effect by monitoring the change in time of circulating a token through parallel processors connected in a virtual ring configuration. This paper proposes some solutions and then experimentally validates their ability to reduce point to point message passing variance for the IBM 9076 (SP1) machines.
Multiprocessor Document Allocation: A Genetic Algorithm Approach
Authors: Ophir Frieder, Hava T. Siegelmann
Venue: IEEE Transactions on Knowledge and Data Engineering (1997)

We formally define the Multiprocessor Document Allocation Problem (MDAP) and prove it to be computationally intractable (NP Complete). Once it is shown that MDAP is NP Complete, we describe a document allocation algorithm based on genetic algorithms. This algorithm assumes that the documents are clustered using any one of the many clustering techniques. We later show that our allocation algorithm probabilistically converges to a good solution. For a behavioral evaluation, we present sample experimental results.
A Cataloging Framework for Software Development Methods
Authors: Gerald M. Karam, Ronald S. Casselman
Venue: Computer (1993)

A framework providing a basis for comparing and evaluating software development methods (SDMs), which are systems of technical procedures and notational conventions for the organized construction of software-based systems, is presented. Using the framework, practitioners and methodologists can describe and rate an SDM's support for 21 properties. The application of the framework to two examples, OMT and R.J.A. Buhr's (1990) architectural design, is discussed. Several suggested uses of the framework include: comparing a group of SDMs with one another; defining a standard in terms of the framework and then using this as a basis for discussion; examining an SDM to discover its coverage and capabilities; and combining the properties of different SDMs to create a new SDM.
Performing Effective Fault Isolation in Integrated Diagnostics
Authors: John W. Sheppard, William R. Simpson
Venue: IEEE Design Test (1993)

Fault trees developed using an entropy-directed search process without modifications or constraints are discussed. To construct a fault tree using entropy-directed search, the computation load is reduced by determining which tests are not needed for diagnosis. The case study of an antitank missile ncher is presented in the context of a complete maintenance architecture.
IDDQ Testing for Deep-Submicron ICs: Challenges and Solutions
Authors: Zhanping Chen, Liqiong Wei, Ali Keshavarzi, Kaushik Roy
Venue: IEEE Design Test (2002)

The use of low-threshold devices in scaled low-voltage CMOS circuits leads to increased intrinsic leakage current. As a result, IDDQ testing requires different techniques to remain effective.