ppxscal/embedding_network huggingface dataset:
Yield Analysis of Compiler-Based Arrays of Embedded SRAMs
Authors: X. Wang, M. Ottavi, F. Lombardi
Venue: Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (2003)

This Paper presents a detailed analysis of the yield of embedded static random access memories (eSRAM) which are generated using a compiler. Defect and fault analysis inclusive of industrial data are presented for these chips by taking into account the design constructs (referred to as kernels) and the physical properties of the layout. The new tool CAYA (Compiler-based Array Yield Analysis) is based on a characterization of the design process which accounts for fault types and the relation between functional and structural faults; a novel empirical model is proposed to facilitate the yield calculation. Industrial data is provided for the analysis of various configurations with different structures and redundancy. The effectiveness and accuracy as provided by CAYA are assessed with respect to industrial designs.
Architecture and implementation of analog iterative decoders
Authors: Patrick Glenn Gulak
Venue:  (2003)

Compound codes developed over the past decade are increasingly being used for error control in data communications standards. As demand for throughput increases, the currently existing decoding architectures will no longer be practical for wireless applications due to their growing power consumption. New techniques based on analog and mixed-signal circuits are derived in this thesis. Circuits for analog Viterbi detection are improved and used for soft-output forward-backward decoding of convolutional codes. The circuits are self-normalizing, and can be used with an arbitrary number of trellis stages or states. Architectures for programmable analog interleavers are introduced, some reducing size and capacitance by over 70% relative to full crossbar interleavers with 100 inputs. The soft-output and interleaver techniques are used in an analog turbo decoder test IC, with 4-state convolutional encoders with 16 information bits. The IC, designed in a 0.35&mu;m 3LM CMOS technology, was tested at 13.3Mbps, 1.2&mu;s latency, and consumes 185mW on a single 3.3V power supply, resulting in energy consumption of 13.9nJ per decoded bit, 80% better than published digital implementations. Swinging buffers could triple the speed and reduce the latency with minimal increase in power consumption. The core area is 1131.2 x 1257.9 &mu;m 2.Future error control codes and their corresponding hardware will be designed in a global manner, optimizing code performance and circuit specifications at the same time. A turbo-like code and its associated decoder, operating at very high speeds and low power consumption, is presented in this thesis. The code, inspired by analog architectures, also has very interesting digital decoder realizations that drastically reduce decoding latencies.
SIA: secure information aggregation in sensor networks
Authors: Bartosz Przydatek, Dawn Song, Adrian Perrig
Venue: Proceedings of the 1st international conference on Embedded networked sensor systems (2003)

Sensor networks promise viable solutions to many monitoring problems. However, the practical deployment of sensor networks faces many challenges imposed by real-world demands. Sensor nodes often have limited computation and communication resources and battery power. Moreover, in many applications sensors are deployed in open environments, and hence are vulnerable to physical attacks, potentially compromising the sensor's cryptographic keys.One of the basic and indispensable functionalities of sensor networks is the ability to answer queries over the data acquired by the sensors. The resource constraints and security issues make designing mechanisms for information aggregation in large sensor networks particularly challenging.In this paper, we propose a novel framework for secure information aggregation in large sensor networks. In our framework certain nodes in the sensor network, called aggregators, help aggregating information requested by a query, which substantially reduces the communication overhead. By constructing efficient random sampling mechanisms and interactive proofs, we enable the user to verify that the answer given by the aggregator is a good approximation of the true value even when the aggregator and a fraction of the sensor nodes are corrupted. In particular, we present efficient protocols for secure computation of the median and the average of the measurements, for the estimation of the network size, and for finding the minimum and maximum sensor reading. Our protocols require only sublinear communication between the aggregator and the user. To the best of our knowledge, this paper is the first on secure information aggregation in sensor networks that can handle a malicious aggregator and sensor nodes.
M-commerce: a location-based value proposition
Authors: Nenad Jukic, Abhishek Sharma, Boris Jukic, Manoj Parameswaran
Venue: Managing e-commerce and mobile computing technologies (2003)

Mobile Commerce (m-commerce) has been defined as a process of conducting commercial transactions via "mobile" telecommunications networks using a communication, information, and payment devices such as a mobile phone or a palmtop unit. Here, we analyze the potential ramifications in the field of marketing and changes in the market due to the advent of m-commerce. In particular, we analyze the opportunities that various characteristics of the m-commerce model can bring to the field of marketing. We investigate the likelihood of the emergence of mall-like zones that are based both on the geographical proximity of services and goods providers and the use of mobile communication devices. Such zones have a potential for becoming the basic units for any analysis of m-commerce scenarios. As m-commerce attains maturity, the zones could become the fundamental parameter in marketing evaluation.
Evaluating the educational impact of visualization
Authors: Thomas Naps, Stephen Cooper, Boris Koldehofe, Charles Leska, Guido Rößling, Wanda Dann, Ari Korhonen, Lauri Malmi, Jarmo Rantakokko, Rockford J. Ross, Jay Anderson, Rudolf Fleischer, Marja Kuittinen, Myles McNally
Venue: Working group reports from ITiCSE on Innovation and technology in computer science education (2003)

The educational impact of visualization depends not only on how well students learn when they use it, but also on how widely it is used by instructors. Instructors believe that visualization helps students learn. The integration of visualization techniques in classroom instruction, however, has fallen far short of its potential. This paper considers this disconnect, identifying its cause in a failure to understand the needs of a key member in the hierarchy of stakeholders, namely the instructor. We describe these needs and offer guidelines for both the effective deployment of visualizations and the evaluation of instructor satisfaction. We then consider different forms of evaluation and the impact of student learning styles on learner outcomes.
A graphical single-authoring framework for building multi-platform user interfaces
Authors: Yun Ding, Heiner Litz, Dennis Pfisterer
Venue: Proceedings of the 9th international conference on Intelligent user interfaces (2004)

This paper presents our novel graphical single-authoring framework, which automatically creates customized user interfaces (UI) for a variety of devices by reusing an existing UI originally designed for large devices. It distinguishes itself from other authoring frameworks by its intuitive graphical support, UI reuse and its extensibility.
A translating computer interface for a network of heterogeneous interactive information retrieval systems
Authors: Richard S. Marcus
Venue: ACM SIGIR Forum (1974)

The need for a network of heterogeneous interactive bibliographic information retrieval systems is projected from the facts of wide acceptance and growing demand for these systems and the limitations of their use caused by limited online data base size. Because of the established characters of the different I-R systems and unlikelihood that a standardized I-R system leading directly to the ultimate uniform network will soon be generally adopted, we propose an intermediate solution in which computer interfaces would provide the networking capability by translating and converting among the diverse languages and data bases of existing systems.We have begun work on such a network in which the computer interface is based on the concept of a common language for commands, indexing vocabularies, and data base structures. In particular, the common language for commands and data base structures is based on identifying the basic or primitive I-R functions and bibliographic data base elements. The conversion among indexing vocabularies is based on the concept of a Master Index and Thesaurus containing the conglomerate thesaurus information from the separate data bases. In addition, the phrase decomposition and stemming of the individual words in the search request and subject index phrases are used as further techniques for automated conversion among diverse vocabularies. An initial experimental interface is described which interconnects the M.I.T. Intrex system, the MEDLINE retrieval system, and the TYMNET computer network using the ARPANET Terminal Interface Processors for intercomputer communication.
Detection of multiple input bridging and stuck-on faults in CMOS logic circuits using current monitoring
Authors: Niraj K. Jha, Qiao Tong
Venue: Proceedings of the conference on European design automation (1990)

Current monitoring is a well-established technique for detecting stuck-on and bridging faults in CMOS logic circuits. When such faults are activated by an appropriate vector, the circuit draws current which is much larger than normal and the fault is detected.In this paper we first show that any test set, which detects all single stuck-at faults in any irredundant combinational CMOS logic circuit, also detects all multiple stuck-on faults in it using current monitoring. If the constituent gates of the circuit are all primitive CMOS gates (NAND, NOR, NOT) then we show that the test set detects all multiple stuck-on and input bridging faults (even if the two types of faults occur simultaneously) with current monitoring. Even when the CMOS circuit is redundant we have found that in most cases a test set that detects all detectable single stuck-at faults also has a very high coverage for the multiple stuck-on and input bridging faults and their combinations.
Nash q-learning for general-sum stochastic games
Authors: Junling Hu, Michael P. Wellman
Venue: The Journal of Machine Learning Research (2003)

We extend Q-learning to a noncooperative multiagent context, using the framework of general-sum stochastic games. A learning agent maintains Q-functions over joint actions, and performs updates based on assuming Nash equilibrium behavior over the current Q-values. This learning protocol provably converges given certain restrictions on the stage games (defined by Q-values) that arise during learning. Experiments with a pair of two-player grid games suggest that such restrictions on the game structure are not necessarily required. Stage games encountered during learning in both grid environments violate the conditions. However, learning consistently converges in the first grid game, which has a unique equilibrium Q-function, but sometimes fails to converge in the second, which has three different equilibrium Q-functions. In a comparison of offline learning performance in both games, we find agents are more likely to reach a joint optimal path with Nash Q-learning than with a single-agent Q-learning method. When at least one agent adopts Nash Q-learning, the performance of both agents is better than using single-agent Q-learning. We have also implemented an online version of Nash Q-learning that balances exploration with exploitation, yielding improved performance.
A distributed task environment for teaching artificial intelligence with agents
Authors: John M. D. Hill, Kenneth L. Alford
Venue: Proceedings of the 35th SIGCSE technical symposium on Computer science education (2004)

It is not uncommon to teach Artificial Intelligence (AI) by asking students to implement agents that embody intelligent behavior. This helps students gain a fuller understanding of the many concepts taught in the course. There are two issues with this approach that deserve attention. First, students come into an AI course knowing how to program in different languages and having different levels of programming ability. Second, it's useful for the students to have a single task environment for all of the agents they program. A solution to both issues lies in a distributed system where the agents are clients communicating with a server that handles a configurable task environment. This allows the students to program their agents in any language and on any platform they desire, so long as they can communicate with the task environment server. If the task environment can be configured to provide additional levels of complexity and difficulty, this allows students to program at a level they are comfortable with. They can then challenge themselves by incorporating more advanced capabilities into their agents. This paper presents just such a distributed and configurable task environment that was developed for an undergraduate AI course.
Optimizing Recursive Information Gathering Plans in EMERAC
Authors: Subbarao Kambhampati, Eric Lambrecht, Ullas Nambiar, Zaiqing Nie, Gnanaprakasam Senthil
Venue: Journal of Intelligent Information Systems (2004)

In this paper we describe two optimization techniques that are specially tailored for information gathering. The first is a greedy minimization algorithm that minimizes an information gathering plan by removing redundant and overlapping information sources without loss of completeness. We then discuss a set of heuristics that guide the greedy minimization algorithm so as to remove costlier information sources first. In contrast to previous work, our approach can handle recursive query plans that arise commonly in the presence of constrained sources. Second, we present a method for ordering the access to sources to reduce the execution cost. This problem differs significantly from the traditional database query optimization problem as sources on the Internet have a variety of access limitations and the execution cost in information gathering is affected both by network traffic and by the connection setup costs. Furthermore, because of the autonomous and decentralized nature of the Web, very little cost statistics about the sources may be available. In this paper, we propose a heuristic algorithm for ordering source calls that takes these constraints into account. Specifically, our algorithm takes both access costs and traffic costs into account, and is able to operate with very coarse statistics about sources (i.e., without depending on full source statistics). Finally, we will discuss implementation and empirical evaluation of these methods in Emerac, our prototype information gathering system.
On the choice of consistent canonical form during moment normalization
Authors: Yani Zhang, Changyun Wen, Ying Zhang, Yeng Chai Soh
Venue: Pattern Recognition Letters (2003)

The key issue in normalization with respect to geometric transformation is how to obtain a consistent canonical form which remains unchanged for different geometric transformation related images. Due to ambiguities inherent in the specified normalization methods, more than one canonical form may occur during the normalization procedure. This causes difficulties in obtaining the expected invariant features or the transformation parameters through normalization. This paper aims to provide general schemes to analyze the ambiguity characteristics and to derive the ambiguity matrices through which ambiguities can be eliminated. Three kinds of ambiguities caused by the multi-roots of high-order polynomials, the symmetrical normalization constraints, and the reflection are addressed and solutions are provided to obtain a consistent canonical form for each kind of ambiguities.
DCAP: detecting misbehaving flows via collaborative aggregate policing
Authors: Chen-Nee Chuah, Lakshminarayanan Subramanian, Randy H. Katz
Venue: ACM SIGCOMM Computer Communication Review (2003)

This paper proposes a detection mechanism called DCAP for a network provider to monitor incoming traffic and identify misbehaving flows without having to keep per-flow accounting at any of its routers. Misbehaving flows refer to flows that exceed their stipulated bandwidth limit. Through collaborative aggregate policing at both ingress and egress nodes, DCAP is able to quickly narrow the search to a candidate group that contains the misbehaving flows, and eventually identify the individual culprits. In comparison to per-flow policing, the amount of state maintained at an edge router is reduced from O(n) to O(&radic;n), where n is the number of admitted flows. Simulation results show that DCAP can successfully detect a majority (64--83%) of the misbehaving flows with almost zero false alarms. Packet losses suffered by innocent flows due to undetected misbehaving activity are insignificant (0.02--0.9%). We also successfully build a prototype that demonstrates how DCAP can be deployed with minimal processing overhead in a soft-QoS architecture.
Wireless System for Electrical Networks Testing Based on MODBUS Protocol
Authors: F. H. Ramírez Leyva, J. P. Acevedo Cuellar, R. G. Maldonado Basilio, E. Espinosa Justo
Venue: Proceedings of the 14th International Conference on Electronics, Communications and Computers (2004)

In this work, a wireless system able to test up tofour Remote Terminal Unit (RTU) is shown. Each RTUestablish communication with a Master Unit (MU)through a radio modem,making use of the MODBUSprotocol. In this work, two kinds of RTUs were used.One of them consists of real electrical power meters,while the other one consist of a personal computer thatworks as an electrical power meter emulator. TheMaster Unit can be as far as 4 km distance from eachRTU. The MU permanently runs a graphical softwaredeveloped with LabVIEW ®. This software ask forinformation from each RTU, save this information in afile and generates a report. The information refers tothe main three-phase electrical network variables,which are voltage, current, frequency, power factor,harmonic distortion and active, reactive and apparentpower.
Improving problem definition through interactive evolutionary computation
Authors: I. C. Parmee
Venue: Artificial Intelligence for Engineering Design, Analysis and Manufacturing (2002)

Poor definition and uncertainty are primary characteristics of conceptual design processes. During the initial stages of these generally human-centric activities, little knowledge pertaining to the problem at hand may be available. The degree of problem definition will depend on information available in terms of appropriate variables, constraints, and both quantitative and qualitative objectives. Typically, the problem space develops with information gained in a dynamical process in which design optimization plays a secondary role, following the establishment of a sufficiently well-defined problem domain. This paper concentrates on background human&ndash;computer interaction relating to the machine-based generation of high-quality design information that, when presented in an appropriate manner to the designer, supports a better understanding of a problem domain. Knowledge gained from such information combined with the experiential knowledge of the designer can result in a reformulation of the problem, providing increased definition and greater confidence in the machine-based representation. Conceptual design domains related to gas turbine blade cooling systems and a preliminary air frame configuration are introduced. These are utilized to illustrate the integration of interactive evolutionary strategies that support the extraction of optimal design information, its presentation to the designer, and subsequent human-based modification of the design domain based on knowledge gained from the information received. An experimental iterative designer or evolutionary search process resulting in a better understanding of the problem and improved machine-based representation of the design domain is thus established.
Programming challenges in network processor deployment
Authors: Chidamber Kulkarni, Matthias Gries, Christian Sauer, Kurt Keutzer
Venue: Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems (2003)

Programming multi-processor ASIPs, such as network processors, remains an art due to the wide variety of architectures and due to little support for exploring different implementation alternatives. We present a study that implements an IP forwarding router application on two different network processors to better understand the main challenges in programming such multi-processor ASIPs. The goal of this study is to identify the elements central to a successful deployment of such systems based on a detailed profiling of the two architectures. Our results show that inefficient partitioning can impact the throughput by more than 30%; a better arbitration of resources increases the throughput by at least 10%, and localization of computation related to the memories can increase the available bandwidth on internal buses by a factor of two. The main observation of our study is that there is a critical lack of tools and methods that support an integrated approach to partitioning, scheduling and arbitration, and data transfer management for such system implementations.
Stimuli Generation with Late Binding of Values
Authors: Avi Ziv
Venue: Proceedings of the conference on Design, automation and test in Europe - Volume 1 (2004)

Generating test-cases that reach corner cases in the design is one of the main challenges in the functional verification of complex designs. In this paper, we describe a new technique that increases the ability of test generators by delaying assignment of values in the generated stimuli, until these values are used in the design. This late-binding allows the generator to have a more accurate view of the state of the design, and thus it can better choose the correct values. Experimental results show that late-binding can significantly improve coverage, with a reasonable penalty in simulation time.
Functional abstraction of logic gates for switch-level simulation
Authors: D. T. Blaauw, D. G. Saab, P. Banerjee, J. A. Abraham
Venue: Proceedings of the conference on European design automation (1991)

Switch-level simulation has become a common means for accurate modeling of MOS circuit behavior. In this paper, we propose a new method for detecting logic gate implementations and accurately modeling their switch-level behavior. The functional abstraction replaces logic gate implementation in the switch-level description with an accurate high-level model which incorporates all relevant switch-level phenomena. The switch-level accuracy of the simulation is, therefore, preserved. However, since the gate implementations are modeled at a higher, more abstract level, the simulation speed is greatly increased. The functional abstraction is automatic and completely transparent to the user. Detection of a gate is determined by expressing the logic function of a transistor network in the sum-of-product notation and is not limited to a specific design style. The proposed algorithms have been implemented and tested on several large circuits, including a complete microprocessor. For this processor, 85% of all transistors were substituted with high-level models. A significant decrease in simulation time and storage requirement occurred for these circuits when gate abstraction was performed.