ppxscal/embedding_network huggingface dataset:
Computing global virtual time in shared-memory multiprocessors
Authors: Richard M. Fujimoto, Maria Hybinette
Venue: ACM Transactions on Modeling and Computer Simulation (TOMACS) (1997)

Global virtual time (GVT) is used in the Time Warp synchronization mechanism to perform irrevocable operations such as I/O and to reclaim storage. Most existing algorithms for computing GVT assume a message-passing programming model. Here, GVT computation is examined in the context of a shared-memory model. We observe that computation of GVT is much simpler in shared-memory multiprocessors because these machines normally guarantee that no two processors will observe a set of memory operations as occurring in different orders. Exploiting this fact, we propose an efficient, asynchronous, shared-memory GVT algorithm and prove its correctness. This algorithm does not require message acknowledgments, special GVT messages, or FIFO delivery of messages, and requires only a minimal number of shared variables and data structures. The algorithm only requires one round of interprocessor communication to compute GVT, in contrast to many message-based algorithms that require two. An efficient implementatin is described that eliminates the need for a processor to explicitly compute a local minimum for time warp systems using a lowest-timestamp-first scheduling policy in each processor.In addition, we propose a new mechanism called on-the-fly fossil collection that enables efficient storage reclamation for simulations containing large numbers, e.g., hundreds of thousand or even millions of simulator objects. On-the-fly fossil collection can be used in time warp systems executing on either shared-memory or message-based machines. Performance measurements of the GVT algorithm and the on-the-fly fossil collection mechanism on a Kendall Square Research KSR-2 machine demonstrate that these techniques enable frequent GVT and fossil collections, e.g., every millisecond, without incurring a significant performance penalty
Designing a Scalable Processor Array for Recurrent Computations
Authors: Kumar N. Ganapathy, Benjamin W. Wah, Chien-Wei Li
Venue: IEEE Transactions on Parallel and Distributed Systems (1997)

In this paper, we study the design of a coprocessor (CoP) to execute efficiently recursive algorithms with uniform dependencies. Our design is based on two objectives: 1) fixed bandwidth to main memory (MM) and 2) scalability to higher performance without increasing MM bandwidth. Our CoP has an access unit (AU) organized as multiple queues, a processor array (PA) with regularly connected processing elements (PEs), and input/output networks for data routing. Our design is unique because it addresses input/output bottleneck and scalability, two of the most important issues in integrating processor arrays in current systems. To allow processor arrays to be widely usable, they must be scalable to high performance with little or no impact on the supporting memory system. The use of multiple queues in AU also eliminates the use of explicit data addresses, thereby simplifying the design of the control program. We present a mapping algorithm that partitions a data dependence graph (DG) of an application into regular blocks, sequences the blocks through AU, and schedules the execution of the blocks, one at a time, on PA. We show that our mapping procedure minimizes the amount of communication between blocks in the partitioned DG, and sequences the blocks through AU to reduce the communication between AU and MM. Using the matrix-product and transitive-closure applications, we study design trade-offs involving 1) division of a fixed chip area between PA and AU, and 2) improvements in speedup with respect to increases in chip area. Our results show, for a fixed chip area, 1) that there is little degradation in throughput in using a linear PA as compared to a PA organized as a square mesh, and 2) that the design is not sensitive to the division of chip area between PA and AU. We further show that, for a fixed throughput, there is an inverse square root relationship between speedup and total chip area. Our study demonstrates the feasibility of a low-cost, memory bandwidth-limited, and scalable coprocessor system for evaluating recurrent algorithms with uniform dependencies.
WinRDBI: a Windows-based relational database educational tool
Authors: Suzanne W. Dietrich, Eric Eckert, Kevin Piscator
Venue: ACM SIGCSE Bulletin (1997)

RDBI is an educational tool that provides students with the capability to test their understanding of the formal relational query languages (relational algebra, domain relational calculus and tuple relational calculus) and the industry standard query language SQL. Although RDBI is an integral part of the database management courses at a number of universities, it is unavailable to those universities that do not have a license for the software product in which RDBI is implemented. WinRDBI, a version of RDBI for Windows, removes this limitation by increasing the availability of the educational tool to a standard Windows platform. Another advantage of WinRDBI is its graphical user interface, providing the student with a more intuitive interface than the command line interface of RDBI. This paper describes the architecture and user interface of WinRDBI. The features of WinRDBI are also illustrated using nontrivial examples from a popular database text. Although formal relational query languages do not provide inherent support for aggregation, these examples illustrate how to write queries in the formal languages to support (a limited form of) counting and minimum/maximum queries.
The EDA startup experience (panel): financing the venture
Authors: A. K. Kalekos, Mike Murray, Marty Walker, Penny Herscher, Lucio Lanza, Peter Odrina, John Cooper, Gerald Langeler
Venue: Proceedings of the 34th annual Design Automation Conference (1997)

The EDA Industry and Venture Capital seem to have grown together over the last three decades. While the vast majority of EDA start ups have been venture capital funded, there are other alternatives to creating and growing a new business. By better understanding the relationship between start ups and venture capitalists, the enterpreneur is better equipped to make decisions which effect the ability to start a company in the first place, its ownership structure, its definition of success, its ability to achieve success and its overall rate of growth. From the venture capitalist's perspective there are two key questions to be addressed: 1. Given the present structure of the EDA industry, is there room for EDA start ups to achieve significant growth so they can be attractive investment opportunities, and 2. Doesthe founding team have what it takes to create and run a successful company. In this session, VC's and successful founders/CEO's discuss their points of view based on past experience and their vision of the future.
Adaptive Memory Tabu Search for Binary Quadratic Programs
Authors: Fred Glover, Gary A. Kochenberger, Bahram Alidaee
Venue: Management Science (1998)

Recent studies have demonstrated the effectiveness of applying adaptive memory tabu search procedures to combinatorial optimization problems. In this paper we describe the development and use of such an approach to solve binary quadratic programs. Computational experience is reported, showing that the approach optimally solves the most difficult problems reported in the literature. For challenging problems of limited size, which are capable of being approached by exact procedures, we find optimal solutions considerably faster than the best reported exact method. Moreover, we demonstrate that our approach is significantly more efficient and yields better solutions than the best heuristic method reported to date. Finally, we give outcomes for larger problems that are considerably more challenging than any currently reported in the literature.
Performance and reliability analysis of relevance filtering for scalable distributed interactive simulation
Authors: Mostafa A. Bassiouni, Ming-Hsing Chiu, Margaret Loper, Michael Garnsey, Jim Williams
Venue: ACM Transactions on Modeling and Computer Simulation (TOMACS) (1997)

Achieving the real-time linkage among multiple, geographically-distant, local area networks that support distributed interactive simulation (DIS) requires tremendous bandwidth and communication resources. Today, meeting the bandwidth and communication requirements of DIS is one of the major challenges facing the design and implementation of large scale DIS training exercises. In this article, we discuss the DIS scalability problem, briefly overview the major bandwidth reduction techniques currently being investigated and implemented in contemporary DIS systems, and present a detailed analysis on the performance and reliability of relevance filtering&mdash;a promising technique to improve the scalability of distributed simulation. The idea of relevance filtering is to analyze the semantic contents of the state update messages of a simulated entity (vehicle) and transmit only the ones found to be relevant to other entities. We present our entity-based model for relevance filtering and discuss the implementation of filtering-at-transmission and filtering-at-reception. We introduce the concept of filtering reliability and present different methods to eliminate or reduce filtering errors. Methods that can ensure complete filtering reliability while providing significant bandwidth reduction are developed. Performance evaluation results of relevance filtering and of the filtering reliability methods are presented. The insight gained from our work and the challenges still facing the design of large scale DIS training exercises are discussed.
Regression metamodels and design of experiments
Authors: Willem J. H. van Groenendaal, Jack P. C. Kleijnen
Venue: Proceedings of the 28th conference on Winter simulation (1996)

Simulation models are often used to support decision making for problems with uncertain inputs and parameters. Three types of models are used: deterministic, risk, and uncertainty models. Risk models are popular with researchers, but can be used only when the joint probability distribution of the inputs and parameters is known. In many real-life situations, however, this is not the case. Uncertainty models are too restrictive for real-life situations. Therefore deterministic models are then used. The sensitivity of the results is often analyzed by changing one factor at a time or by simulating a few scenarios. This paper, however, shows that in case of uncertainty it might be better to apply design of experiments (DOE) in combination with regression metamodels.
Garbage collecting the world: one car at a time
Authors: Richard L. Hudson, Ron Morrison, J. Eliot B. Moss, David S. Munro
Venue: Proceedings of the 12th ACM SIGPLAN conference on Object-oriented programming, systems, languages, and applications (1997)

A new garbage collection algorithm for distributed object systems, called DMOS (Distributed. Mature Object Space), is presented. It is derived from two previous algorithms, MOS (Mature Object Space), sometimes called the train algorithm, and PMOS (Persistent Mature Object Space). The contribution of DMOS is that it provides the following unique combination of properties for a distributed collector: safety, completeness, non-disruptiveness, incrementality, and scalability. Furthermore, the DMOS collector is non-blocking and does not use global tracing.
Joint rate control for VBR MPEG video on PVC ATM links
Authors: Daniel Reininger, Wilson Kwok
Venue: Multimedia Systems (1997)

A joint rate control algorithm for variable bit rate(VBR) MPEG-compressed digital video on point-to-point permanent virtual circuit (PVC) ATM links is proposed.The algorithm controls the encoding mode of a numberof video encoders that operate either on VBR or constantbit rate (CBR) mode. The algorithm selects the encodingmode based on the buffer occupancy of a multiplexer co-located with the encoders that interfaces them to the PVClink. VBR encoding is the predominant encoding mode usedduring congestion-free periods. CBR mode is used only during congested periods. When CBR is selected, new bit ratesare jointly assigned to the encoders based on their relativeencoding complexities. The bit rate assigned to the encodersare enforced by a CBR rate control local to each encoder.The performance of the joint rate control algorithm is evaluated through simulation of a packet multiplexer, where anumber of connections are multiplexed onto a fixed-capacity channel. The performance is compared to that of multiplexing conventional CBR and open-loop VBR from the videoquality and bandwidth efficiency points of view. Simulation results show that the proposed algorithm improves performance over multiplexed conventional CBR or open-loop VBR MPEG video, without significantly increasing implementation complexity. The application of the algorithm, tovideo-on-demand over ATM is discussed.
Exploiting horizontal and vertical concurrency via the HPSm microprocessor
Authors: Wen-Mei W. Hwu, Yale N. Patt
Venue: Proceedings of the 20th annual workshop on Microprogramming (1987)

HPSm is a single-chip microarchitecture designed and implemented at the University of California to achieve high performance. The approach is to exploit both vertical and horizontal concurrency in the microarchitecture. Experiments have been conducted to demonstrate the effectiveness of HPSm as compared to a popular single-chip microarchitecture, the Berkeley RISC/SPUR. Evaluations have been done with both control intensive and floating point intensive benchmarks. For both types of benchmarks, we show that the HPSm microarchitecture achieves significant speedup over the RISC/SPUR microarchitecture implemented with the same fabrication technology.
Symbolic analysis of large analog circuits with determinant decision diagrams
Authors: C.-J. Richard Shi, Xiangdong Tan
Venue: Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design (1997)

Symbolic analog-circuit analysis has many applications, and is especially useful for analog synthesis and testability analysis. In this paper, we present a new approach to exact and canonical symbolic analysis by exploiting the sparsity and sharing of product terms. It consists of representing the symbolic determinant of a circuit matrix by a graph---called determinant decision diagram (DDD)---and performing symbolic analysis by graph manipulations. We showed that DDD construction and DDD-based symbolic analysis can be performed in time complexity proportional to the number of DDD vertices. We described a vertex ordering heuristic, and showed that the number of DDD vertices can be quite small --- usually orders-of-magnitude less than the number of product terms. The algorithm has been implemented. An order-of-magnitude improvement in both CPU time and memory usages over existing symbolic analyzers ISAAC and Maple-V has been observed for large analog circuits.
Supporting manufacturing with simulation: model design, development, and deployment
Authors: Frank Chance, Jennifer Robinson, John W. Fowler
Venue: Proceedings of the 28th conference on Winter simulation (1996)

In this paper, we identify and discuss the features we believe are key to the successful use of simulation as a manufacturing support tool. The discussion begins with three sample projects drawn from the authors' industrial and consulting experiences. Using these projects as motivation, we discuss the ideal project lifecycle model design, development, and deployment. For model design, we emphasize the importance of a clear and consistent specification, articulated in a written document. This specification should identify project customers, goals, and deliverables. We next review a range of model development options, stressing the existence of many non-simulation alternatives. We also discuss methods for model verification and validation. Finally, we consider the difficulties of model deployment, including simulation output analysis, data maintenance, and model integration. We close with several suggestions on how best to present simulation results to a management audience.
Asynchronous parallel algorithms for test set partitioned fault simulation
Authors: Dilip Krishnaswamy, Prithviraj Banerjee, Elizabeth M. Rudnick, Janak H. Patel
Venue: Proceedings of the eleventh workshop on Parallel and distributed simulation (1997)

We propose two new asynchronous parallel algorithms for test set partitioned fault simulation. The algorithms are based on a new two-stage approach to parallelizing fault simulation for sequential VLSI circuits in which the test set is partitioned among the available processors. These algorithms provide the same result as the previous synchronous two stage approach. However, due to the dynamic characteristics of these algorithms and due to the fact that there is very minimal redundant work, they run faster than the previous synchronous approach. A theoretical analysis comparing the various algorithms is also given to provide an insight into these algorithms. The implementations were done in MPI and are therefore portable to many parallel platforms. Results are shown for a shared memory multiprocessor.
Stability of Augmented System Factorizations in Interior-Point Methods
Authors: Stephen Wright
Venue: SIAM Journal on Matrix Analysis and Applications (1997)

Some implementations of interior-point algorithms obtain their search directions by solving symmetric indefinite systems of linear equations. The conditioning of the coefficient matrices in these so-called augmented systems deteriorates on later iterations, as some of the diagonal elements grow without bound. Despite this apparent difficulty, the steps produced by standard factorization procedures are often accurate enough to allow the interior-point method to converge to high accuracy. When the underlying linear program is nondegenerate, we show that convergence to arbitrarily high accuracy occurs, at a rate that closely approximates the theory. We also explain and demonstrate what happens when the linear program is degenerate, where convergence to acceptable accuracy (but not arbitrarily high accuracy) is usually obtained.
A path selection algorithm for timing analysis
Authors: H. C. Yen, S. Ghanta, H. C. Du
Venue: Proceedings of the 25th ACM/IEEE Design Automation Conference (1988)

Due to the rapid progress in semiconductor technology, the number of gates that can be placed in a chip increases dramatically. Existing algorithms for timing analysis have difficulties when dealing with large designs. A new algorithm for timing analysis is proposed in this paper. This algorithm enumerates all the paths with delay greater than a given threshold. The execution time of the proposed algorithm is proportional to the number of paths generated. Therefore, it is suitable for large designs. Classification: timing verification.
A modular, polyvariant and type-based closure analysis
Authors: Anindya Banerjee
Venue: Proceedings of the second ACM SIGPLAN international conference on Functional programming (1997)

We observe that the principal typing property of a type system is the enabling technology for modularity and separate compilation [10]. We use this technology to formulate a modular and polyvariant closure analysis, based on the rank 2 intersection types annotated with control-flow information.Modularity manifests itself in a syntax-directed, annotated-type inference algorithm that can analyse program fragments containing free variables: a principal typing property is used to formalise it. Polyvariance manifests itself in the separation of different behaviours of the same function at its different uses: this is formalised via the rank 2 intersection types. As the rank 2 intersection type discipline types at least all (core) ML programs, our analysis can be used in the separate compilation of such programs.
Spline-Based Image Registration
Authors: Richard Szeliski, James Coughlan
Venue: International Journal of Computer Vision (1997)

The problem of image registration subsumes a number of problems and techniques in multiframe image analysis, including the computation of optic flow (general pixel-based motion), stereo correspondence, structure from motion, and feature tracking. We present a new registration algorithm based on spline representations of the displacement field which can be specialized to solve all of the above mentioned problems. In particular, we show how to compute local flow, global (parametric) flow, rigid flow resulting from camera egomotion, and multiframe versions of the above problems. Using a spline-based description of the flow removes the need for overlapping correlation windows, and produces an explicit measure of the correlation between adjacent flow estimates. We demonstrate our algorithm on multiframe image registration and the recovery of 3D projective scene geometry. We also provide results on a number of standard motion sequences.
Dynamic simulation for time series modeling
Authors: Harriet Black Nembhard
Venue: Proceedings of the 28th conference on Winter simulation (1996)

There has been considerable interest in investigating time series in the fields of economics, business, and engineering. This paper illustrates that dynamic simulation can be used as an instructional tool to introduce time series concepts. We design two simulation models using SIMULINK to represent dynamic models for autoregressive moving average (ARMA) time series data given by a state-space representation. SIMULINK is a program for simulating dynamic systems. It offers a graphical user interface that allows easy development of block diagrams and hierarchical models. This paper presents an overview of how SIMULINK can be used for time series modeling.
Building a special purposes simulation tool for earth moving operations
Authors: Dany Hajjar, Simaan M. AbouRizk
Venue: Proceedings of the 28th conference on Winter simulation (1996)

This paper discusses the process of building a special purpose simulation environment. By making the environment specific for a given industry many advantages are gained including wider acceptance and use in practical settings. Special purpose simulation tools help bring simulation to the desks of construction engineers who have little or no experience with simulation theory. By isolating the user from the low level constructs and presenting a modeling interface that more closely represents the actual system the overall environment becomes more effective. Also, through specialization, the simulation reports can be created in the standard format that engineers in the intended domain are accustomed to. Various reports can be made to include varying levels of information summarized in a manner that can be used directly for estimating and bidding purposes. This paper shares some of the design and implementation issues used when building special purpose simulation tools.
A predictive system shutdown method for energy saving of event-driven computation
Authors: Chi-Hong Hwang, Allen C.-H. Wu
Venue: Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design (1997)

We present a system-level power management technique for power saving of event-driven applications. We present a new predictive system shutdown method to exploit sleep mode operations for power saving. We use an exponential-average approach to predict the upcoming idle period. We introduce two mechanisms, prediction-miss correction and pre-wakeup, to improve the hit ratio and to reduce the delay overhead. Experiments on four different event-driven applications show that our proposed method achieves high hit ratios in a wide range of delay overheads, which results in a high degree of power saving with low delay penalties.