ppxscal/embedding_network huggingface dataset:
A CMOS gate array with dynamic-termination GTL I/O circuits
Authors: Junya Kudoh, Toshiro Takahashi, Yukio Umada, Masaharu Kimura, Shigeru Yamamoto, Youichi Ito
Venue: Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors (1995)

A 530 kG gate array with novel GTL I/O circuits has been developed using 0.5 /spl mu/m CMOS triple-metal-layer process technology. The I/O circuit of a push-pull output driver and a dynamic termination receiver can transmit 250 Mb/s data through a long stub line which is connected to a terminated bus line. IDDQ testability is designed for the differential receiver without any delay time overheads.
Evaluating NN and HMM Classifiers for Handwritten Word Recognition
Authors: José Josemar de Oliveira,  Jr., João Marques de Carvalho, Cinthia O. de A. Freitas, Robert Sabourin
Venue: Proceedings of the 15th Brazilian Symposium on Computer Graphics and Image Processing (2002)

This paper evaluates NN and HMM classifiers applied to the handwritten word recognition problem. The goal is analyse the individual and combined performance of these classifiers. They are evaluated considering two different combination strategies and the experiments are performed with the same database and similar feature sets. The strategy proposed takes advantage of the different but complementary mechanisms of NN and HMM to obtain a more efficient hybrid classifier. The recognition rates obtained vary from 75.9% using the HMM classifier alone to 90.4% considering the NN and HMM combination.
Omega - an integrated environment for C++ program maintenance
Authors: Xiaoping Chen, Wei-Tek Tsai, Hai Huang, Mustafa H. Poonawala, Sanjai Rayadurgam, Yamin Wang
Venue: Proceedings of the 1996 International Conference on Software Maintenance (1996)

Proposes several new object-oriented (OO) software-specific techniques that are useful in the maintenance of OO software, especially C++ programs. The proposed techniques include: (1) new OO-specific dependence relations (such as class, message and declaration dependence); (2) algorithms to construct a hierarchical C++ dependence graph (C++DG) to capture these dependences from the source code; (3) several new slicing techniques (such as class, message, constrained and recursive slicing), besides the existing slicing techniques (such as program, variable and condition slicing) for OO programs. Next, the paper discusses the application of the dependence and slicing concepts to other maintenance activities such as ripple effect analysis (REA) and regression testing. Finally, the paper presents the design of an integrated environment, Omega, that implements many of these techniques for C++ program maintenance. Omega has been demonstrated in various industrial sites in the USA and Japan since May 1995.
Affine-by-Statement Transformations of Imperfectly Nested Loops
Authors: Jingling Xue
Venue: Proceedings of the 10th International Parallel Processing Symposium (1996)

A majority of loop restructuring techniques developed so far assume that loops are perfectly nested. The unimodular approach unifies three individual transformations -- loop interchange, skewing and reversal -- but is still limited to perfect loop nests. This paper outlines a framework that enables the use of unimodular transformations to restructure imperfect loop nests. The concepts previously used for perfect loop nests, such as iteration vector, iteration space and lexicographic order, are generalized to characterize imperfect loop nests. Multiple unimodular transformations are allowed, one on each statement in the loop nests. A code generation algorithm is developed that produces the transformed code by scanning a disjunction of conjunctive affine constraints.
Dynamically Scheduling the Trace Produced During Program Execution into VLIW Instructions
Authors: Alberto Ferreira de Souza, Peter Rounce
Venue: Proceedings of the 13th International Symposium on Parallel Processing and the 10th Symposium on Parallel and Distributed Processing (1999)

VLIW machines possibly provide the most direct way to exploit instruction level parallelism; however, they cannot be used to emulate current general-purpose instruction set architectures. Programs scheduled for a particular implementation of a VLIW model cannot be guaranteed to be binary compatible with other implementations of the same machine model with different number of functional-units. This paper describes an architecture, named dynamically trace scheduled VLIW (DTSVLIW), which can be used to implement machines that execute code of current RISC or CISC instruction set architectures in a VLIW fashion, with backward code compatibility. Some preliminary performance measurements of the DTSVLIW, obtained with an execution-driven simulator running the SPECint95 benchmark suite, are also presented.
Parallel Optimistic Logic Simulation with Event Lookahead
Authors: Hong K. Kim, Jack S. N. Jean
Venue: Proceedings of the 1998 International Conference on Parallel Processing (1998)

Parallel discrete event simulation (PDES) on general-purpose machines can reduce the logic simulation time for large circuits considerably. However, it generates more events than necessary for certain high activity circuits and produces inconsistent execution times over different circuits. This is because glitches contribute to a sizable portion of events during a simulation. The proposed Event-lookahead Time Warp (ETW) algorithm can look ahead, combine and execute multiple events at each gate optimistically, and recover from an error by using a rollback mechanism as used in the original Time Warp algorithm. As a result, it reduces unnecessary events and produces more consistent execution times and reasonable speedups.
The 0-1 law fails for frame satisfiability of propositional modal logic
Authors: Jean-Marie Le Bars
Venue: Proceedings of the 17th Annual IEEE Symposium on Logic in Computer Science (2002)

The digraph property KERNEL is a very simple and well-known property studied in various areas. We previously defined a variant of this property as a counterexample of 0-1law for the monadic existential second order logic with at most two first-order variables, over structures with 16 binary relations. Goranko and Kapron have defined two variants in frames which expresses frame satisfiability of propositional modal logic, also expressible in a small fragmentof the logic above over structures with only one relation. We propose another variant of KERNEL which provides a counterexample of the 0-1 law for frame satisfiability of propositional modal logic. This refutes a result by Halpern and Kapron which establishes that the 0-1 law holds for this logic. It also strongly refines our previous counterexample.
Expectations Towards the Adoption of Workflow Systems: The Results of a Case Study
Authors: Mário Lousã, Anabela Sarmento, Altamiro Machado
Venue: Proceedings of the 6th International Workshop on Groupware (2000)

In the last years, workflow systems have stimulated great interest for two main reasons: an economical and a technological one. The economical reason is based on the recognition by several business and information systems executives that, due to globalisation, the present competitive business environment needs the automation of all the processes of a business activity, and not only the automation of some individual tasks. The technological reason results from the appearance of new computational environments, capable of integrating several applications. Due to these reasons, the expectations towards the adoption of workflow systems are great. The comparison between expectations of academics, vendors and organizations is pertinent. The article presents some results of a case study. We verify that the general results meet data from theoretical background. The exception concerns the expectations rewards strategic objectives.
Representing Retroactive and Proactive Versions in Bi-Temporal Databases
Authors: Jongho Won, Ramez Elmasri
Venue: Proceedings of the Twelfth International Conference on Data Engineering (1996)

Bi-Temporal databases allow users to record retroactive (past) and proactive (future planned) versions of an entity, and to retrieve the appropriate versiosns for bi-temporal queries that involve both valid-time and transaction-time. Currently used timestamp representations are mainly for either valid-time or transaction-time databases. In this paper, we first categorize the types of problems that can occur in existing models. These are (1) ambiguity, (2) priority specification, and (3) lost information. We then propose a 2TDB model that allows both retroactive and proactive versions, overcomes the identified problems, and permits the correction of recorded facts.
Applying a Visual Attention Mechanism to the Problem of Traffic Sign Recognition
Authors: Fabrício Augusto Rodrigues, Herman Martins Gomes
Venue: Proceedings of the 15th Brazilian Symposium on Computer Graphics and Image Processing (2002)

This paper presents the details and preliminary results of a saliency-based attention mechanism that is part of an architecture designed to detect and recognise traffic signs from a set of images.
Understanding SQL through Iconic Interfaces
Authors: Lerina Aversano, Gerardo Canfora, Andrea De Lucia, Silvio Stefanucci
Venue: Proceedings of the 26th International Computer Software and Applications Conference on Prolonging Software Life: Development and Redevelopment (2002)

Visual Query Languages represent an evolution, in terms of understandability and adaptability, with respect to traditional textual languages. We present an iconic query system that enables the interaction of a novice user with a relational database. Our goal is to help a novice user tolearn and comprehend the relational data model and a textual query language such as SQL, through the use of the iconic metaphore. In this sense our approach is different from most of the visual query systems proposed in the literature that present the user with a higher levelquery language, hiding the underlying data model. We also present results from an experiment conducted with first year students to evaluate the effectiveness of our approach.
Indexing Mobile Objects on the Plane
Authors: Dimitris Papadopoulos, George Kollios, Dimitrios Gunopulos, Vassilis J. Tsotras
Venue: Proceedings of the 13th International Workshop on Database and Expert Systems Applications (2002)

We present a method to index objects moving on the plane in order to efficiently answer range queries about their position in the future. This problem is motivated by real-life applications, like predicting future congestion areas in a highway system, or allocating more bandwidth for areas where high concetration of mobile phones is imminent. We consider the problem in theexternal memory model of computation and present a dynamic technique. An experimental evaluation is included that shows the applicability of our method.
Self-Timed Resynchronization: A Post-Optimization for Static Multiprocessor Schedules
Authors: Shuvra S. Bhattacharyya, Sundararajan Sriram, Edward A. Lee
Venue: Proceedings of the 10th International Parallel Processing Symposium (1996)

In a shared-memory multiprocessor system, it is possible that certain synchronization operations are redundant - that is, their corresponding sequencing requirements are enforced completely by other synchronizations in the system - and can be eliminated without compromising correctness. This paper addresses the problem of adding new synchronization operations in a multiprocessor implementation in such a way that the number of original synchronizations that consequently become redundant significantly exceeds the number of new synchronizations. We refer to this approach to reducing synchronization overhead as resynchronization. In this paper we formally define the resynchronization problem, we show that optimal resynchronization is NP-hard, and we propose a family of heuristics for this problem. Finally we present a practical example where resynchronization is useful.
Early Zero Detection
Authors: David R. Lutz, D. N. Jayasimh
Venue: Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors (1996)

We present an integrated adder/subtracter/zero-detector in which the zero detection completes well before the sum or difference is known. Previous zero detectors either required the sum to be available before they could complete, or were not well integrated with the ALU. We avoid these problems by exploiting the properties of half-adder form. Sums in half-adder form can be computed very quickly (with the delay of a half adder), yet they have enough structure so that many of the properties of the final sum can be easily detected. Our zero detector is faster than any previously described, requires only a small amount of additional circuitry in the ALU, and adds little or nothing to the overall delay of the ALU. We also examine some of the architectural implications of early zero detection: faster branching, more instruction-level parallelism, more powerful instructions, and reduced hardware needs for supporting speculative execution.
Interpretation of Lines in Distributing Frame Drawings
Authors: Huizhu Luo, Rangachar Kasturi, Juan F. Arias, Atul K. Chhabra
Venue: Proceedings of the 4th International Conference on Document Analysis and Recognition (1997)

This paper describes a method for interpretation of lines in distributing frame drawings of a telephone company. The lines are composed of hierarchical components: intersections, segments and line links. First, intersections are located. Segments of lines are then detected. Adjacent segments are finally linked into a line. A postprocessing step refines the lines. The line extraction and classification are insensitive to touching characters and broken lines. A number of experimental results using real drawings demonstrate good performance of the algorithms.
Modeling Groupware Supporting Synchronous Collaboration with Heterogeneous Single- and Multi-User Devices
Authors: Peter Tandler
Venue: Proceedings of the Seventh International Workshop on Groupware (2001)

AMBIENTE- Workspaces of the FutureAbstract: In future working environments, multiple users work with a wide range of different devices. In many cases, users interact and collaborate using multiple heterogeneous devices at the same time. This produces new requirements for the architecture of an appropriate software infrastructure. This paper proposes to separate clearly models for document, user interface, tools, physical environment, and interaction to gain flexibility in adapting and extending these different aspects independently. In addition, a core model providing a shared-object space and multi-user event handling eases the development of applications supporting synchronous collaboration and multi-user devices. To test the applicability of this approach, this architecture was used as the basis for the implementation of BEACH, the software infrastructure of I-LAND (the future working-environment at GMD-IPSI). It provides the functionality for synchronous cooperation and interaction with roomware components, i.e., room elements with integrated information technology.
Discovery of Association Rules in Tabular Data
Authors: Graeme Richards, Victor J. Rayward-Smith
Venue: Proceedings of the 2001 IEEE International Conference on Data Mining (2001)

In this paper we address the problem of finding all association rules in tabular data. An Algorithm, ARA, for finding rules, that satisfy clearly specified constraints, in tabular data is presented. ARA is based on the Dense Miner algorithm but includes an additional constraintand an improved method of calculating support. ARA is tested and compared with our implementation of Dense Miner ;it is conclude that ARA is usually more efficient than Dense Miner and is often considerably more so.We also consider the potential for modifying the constraints used in ARA in order to find more generalrules.
Performance Evaluation of the ServerNet R SAN under Self-Similar Traffic
Authors: Dimiter R. Avresky, Vladimir Shurbanov, Robert W. Horst, Pankaj Mehra
Venue: Proceedings of the 13th International Symposium on Parallel Processing and the 10th Symposium on Parallel and Distributed Processing (1999)

Self-similar traffic distributions have been observed in a wide range of networking applications and models such as LANs, WANs, telnet, FTP, WWW, ISDN, SS7 and VBR traffic over ATM. Therefore, it has been suggested that many other theoretical protocols and systems need to be reevaluated under this different type of traffic before practical implementations potentially show their faults.The ServerNet SAN is a new core technology for server architectures that focuses on moving data. It is a wormhole-routed, packet-switched, point-to-point network with special attention paid to reducing latency and assuring reliability.In this paper we investigate the implications of self-similar traffic distributions in the ServerNet SAN, and compare the results with those obtained on the basis of the Poisson assumption.
Design for testability of integrated operational amplifiers using oscillation-test strategy
Authors: Karim Arabi, Bozena Kaminska, Stephen K. Sunter
Venue: Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors (1996)

This paper treats the problem of testing integrated operational amplifiers. The efficiency of a new low-cost vector-less test solution, known as oscillation-test, is investigated. During the test mode, the op-amps are converted to a circuit that oscillates. The oscillation frequency is evaluated to monitor faults. The tolerance band of the oscillation frequency is determined using a Monte Carlo analysis taking into account the nominal tolerance of all important technology and design parameters. Faults in the op-amps under test which cause the oscillation frequency to exit the tolerance band can therefore be detected. Some design for testability (DFT) rules to rearrange op-amps to form oscillators are presented and the related practical problems and limitations are discussed. The oscillation frequency can be easily and precisely evaluated using pure digital circuitry. The simulation and practical implementation results confirm that the presented method assures a high fault coverage with a low area overhead.
Set-Oriented Mining for Association Rules in Relational Databases
Authors: Maurice A. W. Houtsma, Arun N. Swami
Venue: Proceedings of the Eleventh International Conference on Data Engineering (1995)

Describe set-oriented algorithms for mining association rules. Such algorithms imply performing multiple joins and may appear to be inherently less efficient than special-purpose algorithms. We develop new algorithms that can be expressed as SQL queries, and discuss the optimization of these algorithms. After analytical evaluation, an algorithm named SETM emerges as the algorithm of choice. SETM uses only simple database primitives, viz. sorting and merge-scan join. SETM is simple, fast and stable over the range of parameter values. The major contribution of this paper is that it shows that at least some aspects of data mining can be carried out by using general query languages such as SQL, rather than by developing specialized black-box algorithms. The set-oriented nature of SETM facilitates the development of extensions.
A Compile-Time Partitioning Strategy for Non-Rectangular Loop Nests
Authors: Rizos Sakellariou
Venue: Proceedings of the 11th International Symposium on Parallel Processing (1997)

This paper presents a compile-time scheme for partitioning non-rectangular loop nests which consist of inner loops whose bounds depend on the index of the outermost, parallel loop. The minimization of load imbalance, on the basis of symbolic cost estimates, is considered the main objective; however, options which may increase other sources of overhead are avoided. Experimental results on a virtual shared memory computer are also presented.
A TeraFLOP Supercomputer in 1996: The ASCI TFLOP System
Authors: Timothy G. Mattson, David Scott, Stephen R. Wheat
Venue: Proceedings of the 10th International Parallel Processing Symposium (1996)

To maintain the integrity of the US nuclear stockpile without detonating nuclear weapons, the DOE needs the results of computer-simulations that overwhelm the world's most powerful supercomputers. Responding to this need, the DOE initiated the Accelerated Strategic Computing Initiative (ASCI). This program accelerates the development of new scalable supercomputers resulting in a TeraFLOP computer before the end of 1996. In September of 1995, DOE announced that it would work with Intel Corporation to build the ASCI TFLOP supercomputer. This system would use Commodity Commercial Off The Shelf (CCOTS) components to keep the price under control and will contain over 9000 Intel Pentium Pro processors. In this paper, we describe the hardware and software design of this supercomputer.
A Study of High-Performance Communication Mechanism for Multicomputer Systems
Authors: Hideki Murayama, Satoshi Yoshizawa, Takeshi Aimoto, Hidenori Inouchi, Shooichi Murase, Takehisa Hayashi, Hiroshi Iwamoto
Venue: Proceedings of the 10th International Parallel Processing Symposium (1996)

Based on our analysis of the behavior of standard UNIX communication software, we propose a new communication mechanism which reduces software overhead. This mechanism is optimized to be used in business applications, such as those of online transaction processing and database management. These applications are currently designed to operate in multiple concurrent processes, thus requiring multiprocessing environments with virtual addressing.The proposed communication mechanism, named DLA (DLA: Dynamic Link Allocation), supports direct data transfer communication between processors without any intermediate data copy operations. The DLA mechanism adopts a synchronous non-blocking interface, which can be used directly by user processes. Since the DLA mechanism provides address translation for each communication port, sender may directly specify the virtual address of the receiver's buffer area. With DLA mechanism, sender and receiver CPU usages are reduced to one-third of those for TCP/IP communication, while attaining 30% higher throughput.
An Overview of the Internet File System
Authors: Herman Chung-Hwa Rao, Ming-Feng Chen, Feng-Jian Wang
Venue: Proceedings of the 21st International Computer Software and Applications Conference (1997)

The Internet File System (IFS) extends the scope of file systems from LANs to the Internet, encouraging collaboration and information dissemination on a much broader scale. In addition, Internet resources (e.g., Web pages, Gopher Information, and Network News) become {\it files} in IFS, allowing file system APIs and existing tools and commands to be used to manipulate Internet resources just like conventional files. IFS is unique in that it introduces a logical layer between applications and operating systems, and integrates widely-used protocols like FTP, HTTP, GOPHER, NNTP, RSH in this layer. The system is transparent to applications and operating systems, and requires no modification of software nor change in management of Internet file servers. A prototype of IFS is currently running on Sun OS 4.1, Solaris, HP-UX, SVR4, SGI MIPS, and Linux