ppxscal/embedding_network huggingface dataset:
Block-cutvertex trees and block-cutvertex partitions
Authors: Curtis Barefoot
Venue: Discrete Mathematics (2002)

The block-cutvertex graph of the connected graph G, denoted bc(G), is the graph whose vertices are the blocks and cutvertices of G. The edges of bc(G) join cutvertices with those blocks to which they belong. Gallai, Harary and Prins defined this concept and showed that a graph G is the block-cutvertex graph of some connected graph H if and only if G is a tree in which the distance between any two leaves is even. A block-cutvertex partition of the tree T is a collection {T1,..., Tk} of block-cutvertex trees such that each Ti is a subtree of T and each edge of T is in exactly one Ti. We prove that a tree has a block-cutvertex partition if and only if it does not have a perfect matching. Various concepts and algorithms related to block-cutvertex partitions will be presented.
Embedded Robustness IPs for Transient-Error-Free ICs
Authors: Eric Dupont, Michael Nicolaidis, Peter Rohr
Venue: IEEE Design Test (2002)

Shrinking process geometries will make it imperative for designers to start paying attention to transient-error protection. Self-correcting intelligence embedded in ICs protects electronic systems against such unpredictable and insidious errors. Infrastructure IPs that focus on transient faults are a leading type of self-correcting intelligence.
Accuracy of Memory Reference Traces of Parallel Computations in Trace-Drive Simulation
Authors: M. A. Holliday, C. S. Ellis
Venue: IEEE Transactions on Parallel and Distributed Systems (1992)

For given input the global trace generated by a parallel program in a shared memory multiprocessing environment may change as the memory architecture, and management policies change. A method is proposed for ensuring that a correct global trace is generated in the new environment. This method involves a new characterization of a parallel program that identifies its address change points and address affecting points. An extension of traditional process traces, called the intrinsic trace of each process, is developed. The intrinsic traces maximize the decoupling of program execution from simulation by describing the address flow graph and path expressions of each process program. At each point where an address is issued, the trace-driven simulator uses the intrinsic traces and the sequence of loads and stores before the current cycle, to determine the next address. The mapping between load and store sequences and next addresses to issue, sometimes, requires partial program reexecution. Programs that do not require partial program re-execution are called graph-traceable.
AltiVec Extension to PowerPC Accelerates Media Processing
Authors: Keith Diefendorff, Pradeep K. Dubey, Ron Hochsprung, Hunter Scales
Venue: IEEE Micro (2000)

Designed around the premise that multimedia will be the primary consumer of processing cycles in future PCs, AltiVec¿which Apple calls the Velocity Engine¿increases performance across a broad spectrum of media processing applications.
The Importance of Static Structures in Software Construction
Authors: Jorge L. Diaz-Herrera
Venue: IEEE Software (1993)

The static structure is the physical organization of a system's functional modules in terms of their structural relations. It is the packaging of the dynamic structure into textually self-contained modules, taking into consideration the construction strategy and how much of module's internal part should be visible to other modules. Hierarchical modular diagrams (HMD), a module-interface-oriented graphics language that develops can specify the structural relations among modules and map design concepts into a hierarchy of program components independently of the implementation language, is described. The application of HMD to manage a real-time system in a library of separately compiled Ada units is described. It is shown that by using HMD in conjunction with modern software engineering languages like Ada, the static structure can be built earlier in the design process. This lets designers evaluate safety-critical issues as well as reusability concerns long before they make safety checks and implementation decisions. More important, engineers can analyze the effect of approaches to incremental construction before committing additional resources.
Optimal Structuring Elements for the Morphological Pattern Restoration of Binary Images
Authors: D. Schonfeld
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1994)

In this paper, we derive the optimal structuring elements of morphological filters in image restoration. The expected pattern transformation of random sets is presented. An estimation theory framework for random sets is subsequently proposed. This framework is based on the least mean difference (LMD) estimator. The LMD estimator is defined to minimize the cardinality of the expected pattern transformation of the set-difference of the parameter and the estimate. Several important results for the determination of the LMD estimator are derived. The LMD structuring elements of morphological filters in image restoration are finally derived.
On Computing Complete Histograms of Images in Log (n) Steps Using Hypercubes
Authors: T. Bestul, L. S. Davis
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1989)

An algorithm for the computation of the histogram of limited-width (such as gray-level) values on a SIMD (single-instructions multiple-data) hypercube multiprocessor is proposed, which does not require the use of a general interconnection capability such as that on the connection machine. The computation of the complete histogram of n such values takes place in a series of log n steps, after which the histogram for value i can be found in the lowest-addressed processor whose address ends in i. The algorithm makes use of the association of suffixes of data values of increasing width with suffixes of processor addresses.
Partitions which are simultaneously t1and t2-core
Authors: Jaclyn Anderson
Venue: Discrete Mathematics (2002)

For a positive integer t, a partition is t-core if each of the hook numbers from its Ferrers-Young diagram is not divisible by t. For two relatively prime t values, say t1 and t2, there are only finitely many partitions which are both t1- and t2-core. Moreover, the number of partitions has a nice combinatorial representation.
TRACER: an EXCEL workbook to calculate mean residence time in groundwater by use of tracers CFC-11, CFC-12 and tritium
Authors: Serdar Bayari
Venue: Computers Geosciences (2002)

An EXCEL workbook is presented for calculating the mean residence time of groundwater based on the environmental tracers, tritium, CFC-11 and CFC-12. The program TRACER is written in Visual Basic for Application language and uses piston, exponential, linear, exponential-piston and linear-piston flow types of lumped-parameter models. Input and output data are stored in worksheets and a graph of results that are best fitted to observations is drawn for visual evaluation. Recharge temperature and altitude are used to convert atmospheric partial pressures of CFC-11 and CFC-12 to dissolved concentrations to provide a direct comparison between the models' output and observed data. The model can also be used to check whether an inferred flow type could be valid in the groundwater system being investigated. Other radioactive and gaseous environmental tracers and reactions such as, sorption and degradation can be included either as decay constant or with modifications in the program code. TRACER matches, satisfactorily, the results obtained from other softwares.
Generating random numbers of prescribed distribution using physical sources
Authors: Daniel Neuenschwander, Hansmartin Zeuner
Venue: Statistics and Computing (2003)

When constructing uniform random numbers in [0, 1] from the output of a physical device, usually n independent and unbiased bits Bj are extracted and combined into the machine number Y := \sum^n_{j=1}2^{-j}B_j. In order to reduce the number of data used to build one real number, we observe that for independent and exponentially distributed random variables Xn (which arise for example as waiting times between two consecutive impulses of a Geiger counter) the variable Un : &equals; X2n &minus; 1/(X2n &minus; 1 + X2n) is uniform in [0, 1]. In the practical application Xn can only be measured up to a given precision &thetav; (in terms of the expectation of the Xn)&semi; it is shown that the distribution function obtained by calculating Un from these measurements differs from the uniform by less than &thetav;/2.We compare this deviation with the error resulting from the use of biased bits Bj with P&epsiv;&lcub;Bj &equals; 1&rcub; &equals; \frac{1}{2} + \varepsilon (where &epsiv; &isin;] &minus; \frac{1}{2}, \frac{1}{2}[) in the construction of Y above. The influence of a bias is given by the estimate that in the p-total variation norm &Verbar;Q&Verbar;TVp &equals; (\sum_{\omega}&verbar;Q(&omega;)&verbar;p)1/p (p &ge; 1) we have &Verbar;P&epsiv;Y &minus; P0Y&Verbar;TVp &le; (cn\sqrt{n} &middot; &epsiv;)1/p with cn &rarr; p \sqrt{8/\pi} for n &rarr; &infin;. For the distribution function &Verbar;F&epsiv;Y &minus; F0Y&Verbar; &le; 2(1 &minus; 2&minus;n)&verbar;&epsiv;&verbar; holds.
A Resource Guide to Year 2000 Tools
Authors: Nicholas Zvegintzov
Venue: Computer (1997)

The question of what tools are available to handle the Y2K problem would normally be answered in the low-profile, pragmatic environment of software maintenance. But the Y2K problem has tremendous visibility, creating a heated atmosphere in which it is difficult to evaluate tools. The purpose of this article is to provide an outline resource guide to tools to support a Y2K project. A Y2K maintenance project involves most of the activities of software maintenance and management, and thus a guide to Y2K technology could become a guide to all technology that supports software maintenance and management. However, here I focus on technology specialized to handle the unusual aspects of the Y2K project. The tools are organized in six categories: inventory analysis, recovering source from object, project estimation, analysis and conversion, time simulators, and date libraries. Here I include tools only, not service providers or toolsets that are supplied only as part of a service offering. I include only those tools that have been substantially developed, marketed, supported, and documented. The 50 tools included here are technically sophisticated tools aimed at analyzing or controlling software artifacts of industrial size-software engineering tools in the real world.
Detection, Localization, and Estimation of Edges
Authors: J. S. Chen, G. Medioni
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1989)

A method to detect, locate, and estimate edges in a one-dimensional signal is presented. It is inherently more accurate than all previous schemes as it explicitly models and corrects interaction between nearby edges. The method is iterative with initial estimation of edges provided by the zero crossings of the signal convolved with Laplacian of Gaussian (LoG) filter. The necessary computations necessitate knowledge of this convolved output only in a neighborhood around each zero crossing and in most cases, could be performed locally by independent parallel processors. Results on one-dimensional slices extracted from real images, and on images which have been proposed independently in the row and column directions are shown. An analysis of the method is provided including issues of complexity and convergence, and directions of future research are outlined.
Fault Tolerance in Multiprocessor Systems Without Dedicated Redundancy
Authors: P. Agrawal
Venue: IEEE Transactions on Computers (1988)

An algorithm called RAFT (recursive algorithm for fault tolerance) for achieving fault tolerance in multiprocessor systems is described. Through the use of a combination of dynamic space- and time- redundancy techniques, RAFT achieves fault tolerance in the presence of permanent as well as intermittent faults. Performance and reliability of multiprocessor systems using RAFT are determined as a function of individual processor reliability and the total number of fault modes in a processor. RAFT-based systems are superior to triple modular redundancy (TMR) systems in hardware economy and provide comparable reliability. A multiprocessor architecture adopting RAFT is given.
Comments on "Area-Time Optimal Adder Design"
Authors: Chien-In Henry Chen, A. Kumar
Venue: IEEE Transactions on Computers (1994)

A previous paper by Wei and Thompson (1990) defined a family of adders based on a modular design and presented an excellent systematic method of implementing a VLSI parallel adder using three types of component cells designed in static CMOS. Their approach to the adder design was based on the optimization of a formulated dynamic programming problem with respect to area and time. The authors first explicitly demonstrate the optimal 32-bit fast carry generator, described by Wei and Thompson, is incorrect. With suitable corrections, a correct 32-bit fast carry generator design is then presented. Next, BiCMOS technology is applied to implement the subcircuit of fast carry generator to accelerate the critical path. The authors show that the critical path delay of 16-bit, 32-bit and 66-bit adders is respectively shortened to 83.89%, 86.89% and 90.62% after introducing the BiCMOS drivers.
Towards a characterisation of Pfaffian near bipartite graphs
Authors: Charles H. C. Little, Franz Rendl, Ilse Fischer
Venue: Discrete Mathematics (2002)

A bipartite graph G is known to be Pfaffian if and only if it does not contain an even subdivision H of K3,3 such that G - VH contains a 1-factor. However a general characterisation of Pfaffian graphs in terms of forbidden subgraphs is currently not known.The 2-ear theorem of Lovász and Plummer is likely to play a crucial rôle in such a characterisation. The theorem asserts that every 1-extendible graph G has an ear decomposition K2 = G0, G1,...,Gt = G such that the 1-extendible graph Gi is obtained from the 1-extendible graph Gi-1 by the adjunction of one or two ears. In this paper we first show that we can restrict the study of Pfaffian graphs to 1-extendible graphs which have an ear decomposition with a unique 2-ear adjunction. Motivated by that result we start a characterisation of Pfaffian graphs with an ear decomposition where the unique 2-ear adjunction is the final adjunction, i.e., Gt is obtained from Gt-1 by the adjunction of two ears. Such graphs are called 'near bipartite'.
Compiling for Distributed Memory Architectures
Authors: A. Rogers, K. Pingali
Venue: IEEE Transactions on Parallel and Distributed Systems (1994)

The lack of high-level languages and good compilers for parallel machines hinders their widespread acceptance and use. Programmers must address issues such as process decomposition, synchronization, and load balancing. We have developed a parallelizing compiler that, given a sequential program and a memory layout of its data, performs process decomposition while balancing parallelism against locality of reference. A process decomposition is obtained by specializing the program for each processor to the data that resides on that processor. If this analysis fails, the compiler falls back to a simple but inefficient scheme called run-time resolution. Each process's role in the computation is determined by examining the data required for execution at run-time. Thus, our approach to process decomposition is data-driven rather than program-driven. We discuss several message optimizations that address the issues of overhead and synchronization in message transmission. Accumulation reorganizes the computation of a commutative and associative operator to reduce message traffic. Pipelining sends a value as close to its computation as possible to increase parallelism. Vectorization of messages combines messages with the same source and the same destination to reduce overhead. Our results from experiments in parallelizing SIMPLE, a large hydrodynamics benchmark, for the Intel iPSC/2, show a speedup within 60% to 70% of handwritten code.
A Personal Chronicle: Creating Better Information Systems, with Some Guiding Principles
Authors: C. W. Bachman
Venue: IEEE Transactions on Knowledge and Data Engineering (1989)

The author identifies four guiding principles which have come into play in this work of creating information systems and tools to support information systems. The first principle, open-eyes, is used to characterize information systems that remain open to new information, and consequently can compensate for changes in their mission or inaccuracies in their execution of that mission. The second principle involves abstraction levels, which in information systems are similar to differentiation in calculus. They are used to study the changes within a group of heterogeneous objects, with respect to an object type classification, so as to understand and make use of their patterns and ultimately to control the new objects of each type. The third principle, layered architecture, is used to identify a pattern of successive reimplementations of a set of functions, so as to isolate specific environmentally oriented issues. The fourth principle involves relationships, used to define associations between objects and constraints on those associations and to provide access to objects based on their associations. Reference is made to several specific projects which revealed the operation of these principles.
Behavioral Specification of Distributed Software Component Interfaces
Authors: Cynthia Della Torre Cicalese, Shmuel Rotenstreich
Venue: Computer (1999)

Networked computers are finding their way into a broader range of environments, from corporate offices to schools, homes, and shirt pockets. This new computing model fosters the development of distributed software components that communicate with one another across the underlying networked infrastructure. A distributed software component can be plugged into distributed applications that may not have existed when it was created. The intention is that many developers will reuse distributed software components to build new systems. An interface definition language usually is used to describe a distributed software component's interface. However, a notable limitation of current IDLs is that they generally only describe the names and type signatures of the component's attributes and operations. Current IDLs don't formally specify the behavior of the software component's operations. To help solve these problems, the authors have developed Biscotti (behavioral specification of distributed software component interfaces), a Java extension that enhances Java remote method invocation interfaces with Eiffel-style preconditions, postconditions, and invariants.
IDDQ Testing of Opens in CMOS SRAMs
Authors: Victor H. Champac, José Castillejos, Joan Figueras
Venue: Journal of Electronic Testing: Theory and Applications (1999)

The behavior of a CMOS SRAM memory in the presence of open defects is analyzed. It has been found that destructive read-out depends on the level of the precharge. A technique to test open defects producing data retention faults is proposed. An initial condition is forced during the writing phase. In this way, intermediate voltages appear during the memorizing phase. Hence, the quiescent current consumption (I_DDQ) increases and the fault can be detected sensing the I_DDQ. The testability regions for the defective memory cell were determined using state diagrams. Conditions to obtain the optimum vector have been stated. A DFT circuitry has been proposed. The cost of the proposed approach in terms of area, test time, and performance degradation is analyzed.
Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip
Authors: Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen
Venue: Journal of Electronic Testing: Theory and Applications (2002)

Test access mechanisms (TAMs) and test wrappers are integral parts of a system-on-chip (SOC) test architecture. Prior research has concentrated on only one aspect of the TAM/wrapper design problem at a time, i.e., either optimizing the TAMs for a set of pre-designed wrappers, or optimizing the wrapper for a given TAM width. In this paper, we address a more general problem, that of carrying out TAM design and wrapper optimization in conjunction. We present an efficient algorithm to construct wrappers that reduce the testing time for cores. Our wrapper design algorithm improves on earlier approaches by also reducing the TAM width required to achieve these lower testing times. We present new mathematical models for TAM optimization that use the core testing time values calculated by our wrapper design algorithm. We further present a new enumerative method for TAM optimization that reduces execution time significantly when the number of TAMs being designed is small. Experimental results are presented for an academic SOC as well as an industrial SOC.
Parallel Median Splitting and k-Splitting with Application to Merging and Sorting
Authors: R. Xiong, T. Brown
Venue: IEEE Transactions on Parallel and Distributed Systems (1993)

Multiple-instruction multiple-data (MIMD) algorithms that use multiple processors to domedian splitting, k-splitting and parallel splitting into t equal sections are presented. Bothconcurrent read, exclusive write (CREW) and exclusive read, exclusive write (EREW)versions of the algorithms are given. It is shown that a k-splitting problem can be easilyconverted into a median-splitting problem. Methods for finding multiple split points quickly and application of k-splitting to merging and sorting are discussed.
Tools for Multiple-CPU Environments
Authors: Warren Harrison
Venue: IEEE Software (1990)

A brief overview precedes ten separate tool reviews. Five of the tools address the problems of performance analysis, testing, and debugging in a multiple-CPU environment. The first set of tools-Graspin PPSE, and Integral-supports this activity by providing specification or design languages for concurrent applications. The next pair of tools-Pie and Total-supports the development of multiple-CPU software by representing the software's behavior in a parallel or concurrent environment. The next set of five tools is aimed at the problem of serial-to-parallel conversions. The first three tools-E/SP, Mimdizer, and PRETS-recapture the design of the original source code and display it in a graphical form for analysis. The remaining tools-Pat and Aspar-support direct source-to-source transformations. These ten tools are representative of current approaches being taken to address the problem of multiple-CPU computing.
The Push to Make Software Engineering Respectable
Authors: Gilda Pour, Martin L. Griss, Michael Lutz
Venue: Computer (2000)

Software engineering (SE) is maturing as a discipline and profession, but three decades after the first NATO Conference on Software Engineering, it is still not regarded by some to be a legitimate, respectable engineering profession. In 1995, Gary Ford and Norman Gibbs of the Software Engineering Institute evaluated what it means for a profession to be mature and how SE was doing. Their study found that, relative to other fields and engineering branches, most elements that make SE a profession were quite immature.Five years later, SE has had countless practitioners (a.k.a. software developers), thousands of published articles, dozens of conferences and workshops, and a respectable number of education and training programs. But despite all this progress, SE, while recognizable, is still immature-- as evidenced by the significant gap among vision, education, and standard practice. The reasons are legion, but they boil down to one simple fact: The field is still young.The authors present their assessment of SE immaturity in this article. Although they believe time will eventually mature SE, a calculated push can accelerate the maturation process. By "push," they mean defining, accrediting, and evaluating new curricula that stress CS and SE fundamentals.