ppxscal/embedding_network huggingface dataset:
Flexible Software Development: From Software Architecture to Process
Authors: Dharini Balasubramaniam, Ron Morrison, R Mark Greenwood, Brian Warboys
Venue: Proceedings of the Sixth Working IEEE/IFIP Conference on Software Architecture (2007)

Modern software development practices show that there is significant diversity in the product, process and geographical location of software development due to economical, technical and logistical constraints. Such diverse development demands flexibility in the software engineering methodology. In this paper, we propose the Cellular Development Methodology (CDM), an architecture-driven approach to flexible software development. CDM derives the development process and its architecture from the software architecture of product. The software development process is structured and customised as a network of cooperating cells. Our contribution is a cellular approach to software development based on the software architecture of the end product whereby a network of configurable cells yield customisable, potentially distributed software development processes which in turn produce software that is highly tailored to user requirements.
Analyzing the Elements of the Business Model for Mobile Payment Service Provision
Authors: Key Pousttchi, Max Schiessler, Dietmar G. Wiedemann
Venue: Proceedings of the International Conference on the Management of Mobile Business (2007)

In this paper, we use literature review and multi case study analysis in order to identify and analyze different elements of a mobile payment business model. The result is a set of six partial models:: market model, value proposition model, implementation model, capital model, distribution and communication model, and threat model. These models allow for categorization of any given mobile payment business model and, based on this, structured comparison of different business models. Moreover, the set may also support mobile payment service providers in defining and evaluating business models.
Automated size analysis for OCL
Authors: Fang Yu, Tevfik Bultan, Erik Peterson
Venue: Proceedings of the the 6th joint meeting of the European software engineering conference and the ACM SIGSOFT symposium on The foundations of software engineering (2007)

An essential tool in object oriented modeling is the specification of cardinalities of associations between classes. In Object Constraint Language (OCL) such constraints are expressed as conditions on the sizes of the collections that correspond to associations. In this paper we present tools and techniques for automated verification of size properties of collection types in OCL. We automatically verify invariants related to the sizes of the collections of a class with respect to the pre and post-conditions of the methods of that class. Our approach is based on a size abstraction that abstracts away the contents of the collections, but preserves the constraints on their sizes. We implemented a tool which automates this abstraction by converting OCL expressions on collections to arithmetic expressions on their sizes. Following this translation, we employ an infinite state model checker, called Action Language Verifier (ALV), for size analysis. Size abstraction reduces the state space of the system and, hence, the cost of automated verification, and by focusing on size properties, enables us to use efficient, domain specific model checking techniques for automated verification. To demonstrate the effectiveness of our approach we conducted a case study on the OCL specification of the Java Card API. The OCL specification of the Java Card API consists of 31 classes and 150 methods. Using our tool, we translated the OCL specification of each class to Action Language and verified the size properties using ALV. Verification with ALV took only a few seconds per class and we revealed errors in 26 out of the 150 method specifications.
Socio-Technological Systems Integration to Support Tsunami Warning and Evacuation
Authors: Richard G. Little, William A. Wallace, Thomas A. Birkland, Pannapa Herabat
Venue: Proceedings of the 40th Annual Hawaii International Conference on System Sciences (2007)

On December 26, 2004, countries in the Indian Ocean basin were struck by a tsunami generated by a large magnitude earthquake just south of the western tip of Sumatra. Observations made during a post-tsunami visit to coastal Thailand suggest that the value of the proposed emergency warning system (EWS) for the Indian Ocean would be greatly enhanced if it was augmented by an on-shore cyber-based warning and evacuation system. Such a system would greatly increase safety with minimal disruption to the normal activities involved in tourism and other coastal industries. An integrated, cyber-based system to inform and assist the tsunami detection, warning, and evacuation process would, in essence, expand time and shorten distances. This paper describes the elements of such a cyber-infrastructure system, how system triggers could be calibrated using decision principles from judgment theory, and how the system could be tested through simulations employing agentbased models.
Algorithms and architectures for soft-decoding reed-solomon codes
Authors: Naresh R. Shanbhag
Venue:  (2006)

This thesis describes algorithmic and architectural techniques for reducing the complexity of soft-decoding Reed-Solomon codes. The three soft-decoding algorithms considered are algebraic soft-decoding, generalized minimum distance decoding, and ordered-statistics decoding. An algorithmic technique to reduce algebraic soft-decoding complexity is proposed using intermediate interpolation results to check for decodability of the received word. The proposed technique combines intermediate interpolation checks with interpolation point re-encoding and co-ordinate transformation. A technique for reducing the number of intermediate interpolation checks is also proposed. At the architectural level, it is shown that efficient computation of discrepancy polynomials reduces interpolation latency by a factor of eight over a direct mapped interpolation architecture. A high-speed systolic architecture for generalized minimum distance decoding is derived by mapping the iterative erasure decoding algorithm proposed by Koetter onto a systolic array. The proposed architecture is based on the systolic architecture by Sarwate and Shanbhag for implementing the Berlekamp-Massey algorithm. A low-latency, reduced-memory architecture for ordered-statistics decoding is proposed. Starting with a reduced subset of test-cases, the latency and memory requirements of ordered-statistics decoding are further reduced by substituting the row operations of the original ordered-statistics algorithm with equivalent column operations. Finally, the applicability of soft-decoding for disk-drive applications is studied. Based on performance improvements and complexity requirements, generalized minimum distance decoding with maximum a priori soft-detection is selected, and the corresponding architecture is developed. The generalized minimum distance decoder is expected to give 0.5 dB gain over a hard-decoder at the target bit error-rate of 10-12 for the disk-drive channel. The architecture is synthesized using the Virtual Silicon standard cell library in a 0.13-&mu;m CMOS process. It has an area of 7.29 mm&sup2; and achieves a throughput of 8 Gbps.
Streaming Algorithms for Robust, Real-Time Detection of DDoS Attacks
Authors: Sumit Ganguly, Minos Garofalakis, Rajeev Rastogi, Krishan Sabnani
Venue: Proceedings of the 27th International Conference on Distributed Computing Systems (2007)

Effective mechanisms for detecting and thwarting Distributed Denial-of-Service (DDoS) attacks are becoming increasingly important to the success of today's Internet as a viable commercial and business tool. In this paper, we propose novel data-streaming algorithms for the robust, real-time detection of DDoS activity in large ISP networks. The key element of our solution is a new, hashbased synopsis data structure for network-data streams that allows us to efficiently track, in guaranteed small space and time, destination IP addresses in the underlying network that are "large" with respect to the number of distinct source IP addresses that have established potentially-malicious (e.g., "half-open") connections to them. Our work is the first to address the problem of efficiently tracking the top distinct-source frequencies over a general stream of updates (insertions and deletions) to the set of underlying network flows, thus enabling us to effectively distinguish between DDoS activity and flash crowds. Preliminary experimental results verify the effectiveness of our approach.
Searching for type-error messages
Authors: Benjamin S. Lerner, Matthew Flower, Dan Grossman, Craig Chambers
Venue: Proceedings of the 2007 ACM SIGPLAN conference on Programming language design and implementation (2007)

Advanced type systems often need some form of type inference to reduce the burden of explicit typing, but type inference often leads to poor error messages for ill-typed programs. This work pursues a new approach to constructing compilers and presenting type-error messages in which the type-checker itself does not produce the messages. Instead, it is an oracle for a search procedure that finds similar programs that do type-check. Our two-fold goal is to improve error messages while simplifying compiler construction. Our primary implementation and evaluation is for Caml, a language with full type inference. We also present a prototype for C++ template functions, where type instantiation is implicit. A key extension is making our approach robust even when the program has multiple independent type errors.
Architectural Misalignment: An Experience Report
Authors: Matthew Bass, Vesna Mikulovic, Len Bass, James Herbsleb, Marcelo Cataldo
Venue: Proceedings of the Sixth Working IEEE/IFIP Conference on Software Architecture (2007)

It has been well documented that there is a correlation between the structure of an architecture and the organization that produces it. More concretely there is a correlation between task interdependencies and coordination among the people or teams realizing these tasks. The amount of coordination needed among teams is related to the nature of these task interdependencies. As the scale and complexity of organization and systems grow it is not uncommon to have factors such as geographic boundaries, organization boundaries, cultural differences, and so forth impede the ability of certain individuals or teams to coordinate effectively. While there is some understanding of the factors that impede the ability of teams to coordinate, the factors that cause task interdependence in software systems is less well understood. The current view is that it is the interactions across module boundaries (assuming a module is assigned as a task or work item to a single team) that cause task interdependence; we have found that this view is not sufficient. In this paper we present three cases where additional architectural mechanisms created task interdependencies that the organizations were unable to accommodate. We go on to discuss the implications of these findings and suggest future research activities.
Towards a framework for handling disputes in payment systems
Authors: N. Asokan, Els Van Herreweghen, Michael Steiner
Venue: Proceedings of the 3rd conference on USENIX Workshop on Electronic Commerce - Volume 3 (1998)

The ability to support disputes is an important, but often neglected aspect of payment systems. In this paper, we present a language for expressing dispute claims in a unified manner, independent of any specific payment system. We illustrate how to support claims made in this language with evidence tokens from an example payment system. We also describe an architecture for dispute handling. Our approach may be generalised to other services where accountability is a requirement.
Operating system support for planetary-scale network services
Authors: Andy Bavier, Mic Bowman, Brent Chun, David Culler, Scott Karlin, Steve Muir, Larry Peterson, Timothy Roscoe, Tammo Spalink, Mike Wawrzoniak
Venue: Proceedings of the 1st conference on Symposium on Networked Systems Design and Implementation - Volume 1 (2004)

PlanetLab is a geographically distributed overlay network designed to support the deployment and evaluation of planetary-scale network services. Two high-level goals shape its design. First, to enable a large research community to share the infrastructure, PlanetLab provides distributed virtualization, whereby each service runs in an isolated slice of PlanetLab's global resources. Second, to support competition among multiple network services, PlanetLab decouples the operating system running on each node from the network-wide services that define PlanetLab, a principle referred to as unbundled management. This paper describes how Planet-Lab realizes the goals of distributed virtualization and unbundled management, with a focus on the OS running on each node.
TopoLayout: Multilevel Graph Layout by Topological Features
Authors: Daniel Archambault Tamara Munzner
Venue: IEEE Transactions on Visualization and Computer Graphics (2007)

We describe TopoLayout, a feature-based, multilevel algorithm that draws undirected graphs based on the topological features they contain. Topological features are detected recursively inside the graph, and their subgraphs are collapsed into single nodes, forming a graph hierarchy. Each feature is drawn with an algorithm tuned for its topology. As would be expected from a feature-based approach, the runtime and visual quality of TopoLayout depends on the number and types of topological features present in the graph. We show experimental results comparing speed and visual quality for TopoLayout against four other multilevel algorithms on a variety of data sets with a range of connectivities and sizes. TopoLayout frequently improves the results in terms of speed and visual quality on these data sets.
Enhancement of the introductory computer science curriculum
Authors: R. Price Jones
Venue: Proceedings of the 26th Annual Frontiers in Education - Volume 01 (1996)

An emphasis on derivation, analysis, and correctness verification throughout the problem-solving and program-development processes is the main thrust of the project. Interactive web-based laboratories are the most obvious of the curricular materials developed to dare. They support sophomore level courses covering the traditional content of courses in data structures, algorithms and programming language concepts. In order to develop the hundreds of web pages necessary for the laboratories, the project team found it necessary to create an HTML compiler called HtX. In the same way as LaTeX can abstract the style properties of static documents, HtX abstracts both static and dynamic features of web documents, enabling rapid development, multi-authoring and consistent appearance of large web structures. We are now in a position to disseminate not only the course materials, but also the powerful tools that will enable educators everywhere to produce effective classroom presentations and laboratory materials, concentrating only on the content of the documents and leaving style and format considerations for automatic treatment.
Speech interface VLSI for car applications
Authors: M. Shozakai
Venue: Proceedings of the Acoustics, Speech, and Signal Processing, 1999. on 1999 IEEE International Conference - Volume 01 (1999)

A user-friendly speech interface for car applications is highly needed for safety reasons. This paper describes a speech interface VLSI designed for car environments, with speech recognition and speech compression/decompression functions. The chip has a heterogeneous architecture composed of ADC/DAC, DSP, RISC, hard-wired logic and peripheral circuits. The DSP not only executes acoustic analysis and output probability calculation of HMMs for speech recognition, but also does speech compression/decompression. On the other hand, the RISC works as a CPU of the whole chip and Viterbi decoder with an aid of hard-wired logic. An algorithm to recognize a mixed vocabulary of speaker-independent fixed words and speaker-dependent user-defined words in a seamless way is proposed. It is based on acoustic event HMMs which enable a template creation from one sample utterance. The proposed algorithm embedded in the chip is evaluated. Promising results of the algorithm for multiple languages are shown. The ACM Portal is published by the Association for Computing Machinery. Copyright © 2010 ACM, Inc. Terms of Usage Privacy Policy Code of Ethics Contact Us Useful downloads: Adobe Acrobat QuickTime Windows Media Player Real Player
Predicting short-transfer latency from TCP arcana: a trace-based validation
Authors: Martin Arlitt, Balachander Krishnamurthy, Jeffrey C. Mogul
Venue: Proceedings of the 5th ACM SIGCOMM conference on Internet Measurement (2005)

In some contexts it may be useful to predict the latency for short TCP transfers. For example, a Web server could automatically tailor its content depending on the network path to each client, or an "opportunistic networking" application could improve its scheduling of data transfers. Several techniques have been proposed to predict the latency of short TCP transfers based on online measurements of characteristics of the current TCP connection, or of recent connections from the same client. We analyze the predictive abilities of these techniques using traces from a variety of Web servers, and show that they can achieve useful accuracy in many, but not all, cases. We also show that a previously-described model for predicting short-transfer TCP latency can be improved with a simple modification. Ours is the first trace-based analysis that evaluates these prediction techniques across diverse user communities.
Linking programs in a single address space
Authors: Luke Deller, Gernot Heiser
Venue: Proceedings of the annual conference on USENIX Annual Technical Conference (1999)

Linking and loading are the final steps in preparing a program for execution. This paper assesses issues concerning dynamic and static linking in traditional as well as single-address-space operating systems (SASOS). Related loading issues are also addressed. We present the dynamic linking model implemented in the Mungi SASOS and discuss its strengths and limitations. Benchmarking shows that dynamic linking in a SASOS carries significantly less overhead than dynamic linking in SGI's Irix operating system. The same performance advantages could be achieved in Unix systems, if they reserved a portion of the address space for dynamically linked libraries, and ensured that each library is always mapped at the same address.
An analytical approach to file prefetching
Authors: Hui Lei, Dan Duchamp
Venue: Proceedings of the annual conference on USENIX Annual Technical Conference (1997)

File prefetching is an effective technique for improving file access performance. In this paper, we present a file prefetching mechanism that is based on on-line analytic modeling of interesting system events and is transparent to higher levels. The mechanism, incorporated into a client's file cache manager, seeks to build semantic structures that capture the intrinsic correlations between file accesses. It then heuristically uses these structures to represent distinct file usage patterns and exploits them to prefetch files from a file server. We show results of a simulation study and of a working implementation. Measurements suggest that our method can predict future file accesses with an accuracy around 90%, that it can reduce cache miss rate by up to 47% and application latency by up to 40%. Our method imposes little overhead, even under antagonistic circumstances.
Flying embedded: the industrial scene and challenges for embedded systems in aeronautics and space
Authors: Jean Botti
Venue: Proceedings of the conference on Design, automation and test in Europe (2007)

This keynote address, given by an executive representative of the European aeronautics and space industry, introduces the strategic stakes and the international competitive landscape, for further development and understanding of the sizing dimensions of technology transfer all along the special day. The ACM Portal is published by the Association for Computing Machinery. Copyright © 2010 ACM, Inc. Terms of Usage Privacy Policy Code of Ethics Contact Us Useful downloads: Adobe Acrobat QuickTime Windows Media Player Real Player
Using Clock-Vdd to Test and Diagnose the Power-Switch in Power-Gating Circuit
Authors: Hsiang-Hui Huang, Ching-Hwa Cheng
Venue: Proceedings of the 25th IEEE VLSI Test Symmposium (2007)

Power-gate is a well-known technology used to decrease static (leakage) power consumption in low-power circuit currently. Several PMOS transistors are used as power switches (p-switches) to control the power source within the power-gating circuit. The p-switches are attached between the Vdd and the virtual Vdd power rail which served as the power source of circuit. The system of power management unit will turn off the power supply of the idle core by switching off the p-switches. As we know, the performance of a circuit depends on whether the supplied current is sufficient or not, and it relies on how much the channel width of p-switches could turn on simultaneously. Some defects will make the p-switches channel width diminished. The phenomenon of reducing channel width will not only affect the circuit performance but also cause chip reliability degrades because the current flow of p-switches overloaded. Therefore, it is important to diagnose/test the failed/defective p-switches. In this paper, the proposed CKVdd technique could easily identify the performance degradation caused by the failed/defective p-switches within the power-gating circuit.
Software Systems Engineering with Model-Based Design
Authors: Christopher Davey, Jon Friedman
Venue: Proceedings of the 4th International Workshop on Software Engineering for Automotive Systems (2007)

Today's original equipment manufacturers (OEMs) and suppliers face the seemingly conflicting goals of reducing development time while improving quality, and reducing system complexity while delivering technical innovations. To meet these challenges, design engineers are increasingly reliant on embedded software solutions to deliver innovative functionality. Luxury vehicles produced today contain as many as 90 embedded electronic control units (ECUs) that use four different network protocols and execute binary code generated from over 6 million lines of source code (MLOC). Even economy vehicles can contain as many as 50 ECUs that deliver mission-critical, distributed, embedded software systems.
Student use of personal digital assistants in a computer engineering course
Authors: R. Avanzato
Venue: Proceedings of the Frontiers in Education Conference, 2001. 31st Annual - Volume 02 (2001)

Penn State Abington has integrated the student use of personal digital assistant (PDA) technology to foster active and collaborative learning experiences in the classroom and laboratory. Palm/sup TM/ PDA technology was introduced into a sophomore-level digital systems course in the fall of 2000. The students have investigated handheld software tools for enhancing learning and instruction in both the lecture and laboratory components of the course. Handheld databases, simple CAD tools, C programming, image capture, web-based tools, and robotics applications have been explored. The ACM Portal is published by the Association for Computing Machinery. Copyright © 2010 ACM, Inc. Terms of Usage Privacy Policy Code of Ethics Contact Us Useful downloads: Adobe Acrobat QuickTime Windows Media Player Real Player