ppxscal/embedding_network huggingface dataset:
An Empirical Study of Two Approaches to Sequence Learning for Anomaly Detection
Authors: Terran Lane, Carla E. Brodley
Venue: Machine Learning (2003)

This paper introduces the computer security domain of anomaly detection and formulates it as a machine learning task on temporal sequence data. In this domain, the goal is to develop a model or profile of the normal working state of a system user and to detect anomalous conditions as long-term deviations from the expected behavior patterns. We introduce two approaches to this problem: one employing instance-based learning (IBL) and the other using hidden Markov models (HMMs). Though not suitable for a comprehensive security solution, both approaches achieve anomaly identification performance sufficient for a low-level &ldquo;focus of attention&rdquo; detector in a multitier security system. Further, we evaluate model scaling techniques for the two approaches: two clustering techniques for the IBL approach and variation of the number of hidden states for the HMM approach. We find that over both model classes and a wide range of model scales, there is no significant difference in performance at recognizing the profiled user. We take this invariance as evidence that, in this security domain, limited memory models (e.g., fixed-length instances or low-order Markov models) can learn only part of the user identity information in which we're interested and that substantially different models will be necessary if dramatic improvements in user-based anomaly detection are to be achieved.
Query Evaluability in Statistical Databases
Authors: F. M. Malvestuto, M. Moscarini
Venue: IEEE Transactions on Knowledge and Data Engineering (1990)

The evaluability of queries on a statistical database containing joinable tables connected by an intersection hypergraph is considered. A characterization of evaluable queries is given, which allows one to define polynomial-time procedures both for testing evaluability and for evaluating queries. These results are useful in designing an 'informed query system' for statistical databases which promotes an integrated use of stored information. Such a query system allows the user to formulate a query involving attributes from several joinable tables as if they were all contained in a single universal table.
Comparisons of Seven Neural Network Models on Traffic Control Problems in Multistage Interconnection Networks
Authors: N. Funabiki, Y. Takefuji, K. C Lee
Venue: IEEE Transactions on Computers (1993)

The performances of seven neural network models for traffic control problems in multistage interconnection networks are compared. The decay term, three neuron models, and two heuristics were evaluated. The goal of the traffic control problems is to find conflict-free switching configurations with the maximum throughput. The simulation results show that the hysteresis McCullock-Pitts neuron model without the decay term and with two heuristics has the best performance.
Blind Source Separation, ISI Cancellation and Carrier Phase Recovery in SDMA Systems for Mobile Communications
Authors: João Xavier, Victor Barroso
Venue: Wireless Personal Communications: An International Journal (1999)

Current rates of demand for radio cellular services will soon reach the saturation point of the actual cellular infrastructures. Thus, spectral bandwidth-saving multiple access schemes are necessary to expand the actual networks&lsquo; capacity. In the Spatial Division Multiple Access (SDMA) approach, users within the same cell share the same time/frequency channel and the base station receiver exploits the spatial dimension of the radio resource to remove crosstalk. In this paper, we present a blind multi-user equalization technique for SDMA architectures which performs the separation of digital sources, in the presence of intersymbol interference (ISI) and phase carrier drifts. We take advantage of the sources&lsquo; joint finite alphabet and statistical properties, and use only second-order statistics in order to produce valid channel estimates based on short data packets. Computer simulations using the TU-GSM multipath channel model for radio communications in urban environments demonstrate the potential of our technique.
A JPL Report: AI Takes on Space Tasks
Authors: Ware Myers
Venue: IEEE Expert: Intelligent Systems and Their Applications (1990)

The growing use of artificial intelligence (AI) at the Jet Propulsion Laboratory in mission operations and other areas of the space program is discussed. Mission operations is furthest along, two systems having begun operation in parallel with existing methods in time for Voyager 2's Neptune encounter in August 1989. One is called Sharp (spacecraft health automated reasoning prototype) and the other is called Marvel (monitor/analyzer of real-time Voyager engineering link). Both systems are described, focusing on the use of AI. Research on other applications of AI in space, in the areas of resource scheduling, scientific data analysis, sensor monitoring, and robotics, is examined.
Tools to Engineer New Technologies into Applications
Authors: Rodney Bell, David Sharon
Venue: IEEE Software (1995)

Computer technology is exploding. Friendly interfaces, a full range of media, and unlimited connectivity are pushing technology ever deeper into the fabric of society. How can developers incorporate all this new technology into their applications? Today's development environments are taking advantage of emerging integration standards to offer specialized tools.
Delay Fault Testing: Choosing Between Random SIC and Random MIC Test Sequences
Authors: A. Virazel, R. David, P. Girard, C. Landrault, S. Pravossoudovitch
Venue: Journal of Electronic Testing: Theory and Applications (2001)

The combination of higher quality requirements and sensitivity of high performance circuits to delay defects has led to an increasing emphasis on delay testing of VLSI circuits. In this context, it has been proven that Single Input Change (SIC) test sequences are more effective than classical Multiple Input Change (MIC) test sequences when a high robust delay fault coverage is targeted. In this paper, we show that random SIC (RSIC) test sequences achieve a higher fault coverage than random MIC (RMIC) test sequences when both robust and non-robust tests are under consideration. Experimental results given in this paper are based on a software generation of RSIC test sequences that can be easily generated in this case. For a built-in self-test (BIST) purpose, hardware generated RSIC sequences have to be used. This kind of generation will be shortly discussed at the end of the paper.
Planar Hamiltonian chordal graphs are cycle extendable
Authors: Tao Jiang
Venue: Discrete Mathematics (2002)

A cycle C in a graph G is extendable if there exists a cycle C' in G such that V(C) ⊆ V(C') and |V(C')| = |V(C)| + 1. A graph G is cycle extendable if G contains at least one cycle and every non-Hamiltonian cycle in G is extendable. Hendry (Discrete Math. 85 (1990) 59) asked if every Hamiltonian chordal graph is cycle extendable. We prove that every planar Hamiltonian chordal graph is cycle extendable.
Component-Based Systems: A Classification of Issues
Authors: Pearl Brereton, David Budgen
Venue: Computer (2000)

Developing and using various component forms as building blocks can significantly enhance software-based system development and use. The authors describe software components as units of independent production, acquisition, and deployment that interact to form a functional system.Both the academic and commercial sectors have devoted considerable effort to defining and describing the terms and concepts involved in component-based software development.The component-based systems approach could potentially overcome difficulties associated with developing and maintaining monolithic software applications. The authors believe that this approach should result in better quality products, rapid development, and an in-creased capability to accommodate change.The authors identify a set of issues within an overall framework that software developers must address for component-based systems to achieve their full potential. They contend that using this framework leads to a more effective understanding of components because it helps clarify aspects of the component concept that are largely independent of architectural and implementation issues.
Efficient Dilation, Erosion, Opening, and Closing Algorithms
Authors: Joseph (Yossi) Gil, Ron Kimmel
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (2002)

We propose an efficient and deterministic algorithm for computing the one-dimensional dilation and erosion (max and min) sliding window filters. For a p\hbox{-}{\rm{element}} sliding window, our algorithm computes the 1D filter using 1.5 + o(1) comparisons per sample point. Our algorithm constitutes a deterministic improvement over the best previously known such algorithm, independently developed by van Herk and by Gil and Werman (the HGW algorithm). Also, the results presented in this paper constitute an improvement over the Gevorkian et al. (GAA) variant of the HGW algorithm. The improvement over the GAA variant is also in the computation model. The GAA algorithm makes the assumption that the input is independently and identically distributed (the i.i.d. assumption), whereas our main result is deterministic. We also deal with the problem of computing the dilation and erosion filters simultaneously, as required, e.g., for computing the unbiased morphological edge. In the case of i.i.d. inputs, we show that this simultaneous computation can be done more efficiently then separately computing each. We then turn to the opening filter, defined as the application of the min filter to the max filter and give an efficient algorithm for its computation. Specifically, this algorithm is only slightly slower than the computation of just the max filter. The improved algorithms are readily generalized to two dimensions (for a rectangular window), as well as to any higher finite dimension (for a hyperbox window), with the number of comparisons per window remaining constant. For the sake of concreteness, we also make a few comments on implementation considerations in a contemporary programming language.
On Transaction Processing with Partial Validation and Timestamp Ordering in Mobile Broadcast Environments
Authors: Victor C. S. Lee, Kwok-Wa Lam, Sang H. Son, Eddie Y. M. Chan
Venue: IEEE Transactions on Computers (2002)

Conventional concurrency control protocols are inapplicable in mobile broadcast environments due to a number of constraints of wireless communications. Previous studies are focused on efficient processing of read-only transactions at the mobile clients, neglecting update transactions. In this paper, we design a new protocol for processing both read-only and update mobile transactions. The protocol can detect data conflicts at an early stage at the mobile clients and resolve data conflicts flexibly using dynamic adjustment of timestamp ordering. Early data conflict detection saves processing and communication resources, while dynamic adjustment of timestamp ordering allows more schedules of transaction executions such that unnecessary transaction aborts can be avoided. We performed extensive simulation studies to evaluate the effectiveness of these two features for the performance of the new protocol. The analysis of simulation results showed that both features are effective and contribute differently to the satisfactory performance of the protocol.
Transparent (Cut-Through) Bridging of CSMA/CD Networks: Performance Analysis and Implementation
Authors: C. K. Kwok, B. Mukherjee
Venue: IEEE Transactions on Computers (1994)

The increasing popularity of local area networks (LANs) and the limitations of a single LAN (on its geographical coverage, information-carrying capacity, and number of stations) have triggered tremendous interest in the study and implementation of interconnected LANs. The authors address the problem of interconnecting the widely deployed CSMA/CD LANs (or LAN segments) via a transparent bridge. A transparent bridge is so called because it "learns" about the network structure and organization during its operation, i.e., it learns about the location of the network stations relative to the bridge in order to do the forwarding of frames selectively; also, the stations need not be aware of the presence of the bridge. The authors make two important contributions. First, they present an approximate analytical model of a transparent CSMA/CD bridge which can be either of the normal store-and-forward type or of the novel cut-through variety (introduced by Kwok and Mukherjee). Using the analytical model, which is also verified via simulation, the performance of the cut-through bridge is compared with (and found to be superior than) that of the normal bridge. Secondly they present the design of a cut-through bridge which can be easily implemented using off-the-shelf components.
Benchmarking Software-Development Productivity
Authors: Katrina D. Maxwell, Pekka Forselius
Venue: IEEE Software (2000)

This article examines a statistical analysis of a productivity variation involving a unique database containing 206 business software projects from 26 Finnish companies. The authors examine differences in the factors explaining productivity in the banking, insurance, manufacturing, wholesale/retail, and public administration sectors. The authors provide productivity benchmarking equations that are useful both for estimating expected productivity at the start of a new project and for benchmarking a completed project for each business sector.
Alpha 21164 Testability Strategy
Authors: Dilip K. Bhavsar, John H. Edmondson
Venue: IEEE Design Test (1997)

We describe the testability strategy and design-for-test features of the Alpha 21164 microprocessor. We discuss the specific testability and manufacturability issues of the chip and the innovative solutions employed to solve them.The Alpha 21164 microprocessor is a superscalar implementation of Digital's 64-bit RISC architecture designed to meet the requirements of a wide variety of systems ranging from PC clients to enterprise server systems.
Codesign of Embedded Systems: Status and Trends
Authors: Rolf Ernst
Venue: IEEE Design Test (1998)

The concurrent design of hardware and software is one of the key challenges in embedded system design. New methodologies and CAD tools are needed to support an integrated hardware-software codesign process. The article starts with an overview on the state of the practice in embedded system design and discusses the achievements and limitations of currently available tools. While the current focus is on coverification and design integration, research has moved on to support a unified hardware and software development with design space exploration and reuse of system functions across hardware and software platforms. Then, it discusses the challenges and trends in codesign research. It shows how to evolve the current design process into a coherent and versatile codesign process supporting design space exploration and reuse across technologies and applications.
Hierarchical Design and Test of Integrated Microsystems
Authors: Tamal Mukherjee, Gary K. Fedder, R. D. (Shawn) Blanton
Venue: IEEE Design Test (1999)

The advent of monolithic integration of mechanical structures with electronics has ushered in an era in which microchips can sense and act as well as compute and communicate. The complex device, component, and system design issues involving such integrated chips require the development of new CAD representations, methodologies, and tools. In this article, we present a suite of tools that simultaneously considers the mechanical and electromechanical nature of such microsystems versus traditional electronics. These tools are based on a design methodology that partitions the micromechanical and electromechanical components in a hierarchical fashion into low-level reusable elements. This mixed-domain circuit representation is combined with Kirchhoffian network theory for an integrated microsystem simulation environment. Behavioral models from this hierarchical representation are combined with optimization into a tool that generates microstructure layouts meeting specified performance criteria. A feature-recognition-based extractor translates layout geometry into the mixed-domain circuit representation, enabling layout verification. Models that integrate the effects of process contaminations on a microstructure form the basis of a MEMS testing methodology.
Optimal software multicast in wormhole-routed multistage networks
Authors: Hong Xu, Ya-Dong Gui, Lionel M. Ni
Venue: Proceedings of the 1994 ACM/IEEE conference on Supercomputing (1994)

Multistage interconnection networks are a popular class of interconnection architecture for constructing scalable parallel computers (SPCs). The focus of this paper is on wormhole routed multistage networks supporting turnaround routing. Existing machines characterized by such a system model include the IBM SP-1, TMC CM-5, and Meiko CS-2.Efficient collective communication among processor nodes is critical to the performance of SPCs. A system-level multicast service, in which the same message is delivered from a source node to an arbitrary number of destination nodes, is fundamental in supporting collective communication primitives including the application-level broadcast, reduction, and barrier synchronization. This paper addresses how to efficiently implement multicast services in wormhole-routed multistage networks, in the absence of hardware multicast support, by exploiting the properties of the switching technology. An optimal multicast algorithm is proposed. The results of implementations on a 64-node SP-1 show that the proposed algorithm significantly outperforms the application-level broadcast primitives provided by currently existing collective communication libraries including the public domain MPI.
Accelerated Two-Level Carry-Skip Adders-A Type of Very Fast Adders
Authors: V. Kantabutra
Venue: IEEE Transactions on Computers (1993)

This paper describes a new type of carry-skip adder, which can be faster than the conventional two-level carry-skip adders. A way to design optimum adders of this new type is described. In optimum adders of this type, the sizes of the sections of bit positions are bimodal, but the sizes of the blocks in each section are unimodal, unlike the bimodal block sizes in Guyot et al.'s traditional two-level carry-skip adders. A 60-b 2- mu m CMOS adder of this type is designed. This adder's simulated delay is approximately 12.6 ns.
Legacy Systems: Coping with Success
Authors: Keith Bennett
Venue: IEEE Software (1995)

Legacy software was written years ago using outdated techniques, yet it continues to do useful work. Migrating and updating this baggage from our past has technical and nontechnical challenges, ranging from justifying the expense to dealing with offshore contractors to using program-understanding and visualization techniques.
Implementing a Software Metrics Program at Nokia
Authors: Tapani Kilpi
Venue: IEEE Software (2001)

Model solutions for implementing a measurement program do not always fit an organization without tailoring. The sizes and maturities of the processes vary from organization to organization. In an organization with mature software processes, carefully adjusting the created solution for a measurement program to the environment-specific needs and options can save considerable effort. This article demonstrates the real-world application of the Nokiaway software metrics program and how it benefited in its divergence from a typical Goal-Question-Metric approach.
Deep performance analysis of refined harmonic bin packing algorithm
Authors: Gu Xiaodong, Chen Guoliang, Xu Yinlong
Venue: Journal of Computer Science and Technology (2002)

Refined Harmonic (RH) is one of the best on-line bin packing algorithms. The algorithm was first proposed by Lee&Lee in 1985 and the upper bound of the worst-case performance ratio has been proved to be 1.63596..., In this paper, it is proved that 1.63596... is also the lower bound. The average performance of RH is also studied for the first time. It is shown that the average-case performance ratio of RH is 1.28243... under the uniform distribution.
Recursive Array Layouts and Fast Matrix Multiplication
Authors: Siddhartha Chatterjee, Alvin R. Lebeck, Praveen K. Patnala, Mithuna Thottethodi
Venue: IEEE Transactions on Parallel and Distributed Systems (2002)

The performance of both serial and parallel implementations of matrix multiplication is highly sensitive to memory system behavior. False sharing and cache conflicts cause traditional column-major or row-major array layouts to incur high variability in memory system performance as matrix size varies. This paper investigates the use of recursive array layouts to improve performance and reduce variability. Previous work on recursive matrix multiplication is extended to examine several recursive array layouts and three recursive algorithms: standard matrix multiplication and the more complex algorithms of Strassen and Winograd. While recursive layouts significantly outperform traditional layouts (reducing execution times by a factor of 1.2-2.5) for the standard algorithm, they offer little improvement for Strassen's and Winograd's algorithms. For a purely sequential implementation, it is possible to reorder computation to conserve memory space and improve performance between 10 percent and 20 percent. Carrying the recursive layout down to the level of individual matrix elements is shown to be counterproductive; a combination of recursive layouts down to canonically ordered matrix tiles instead yields higher performance. Five recursive layouts with successively increasing complexity of address computation are evaluated and it is shown that addressing overheads can be kept in control even for the most computationally demanding of these layouts.
Summarizing archived discussions: a beginning
Authors: Paula S. Newman, John C. Blitzer
Venue: Proceedings of the 8th international conference on Intelligent user interfaces (2003)

This paper describes an approach to digesting threads of archived discussion lists by clustering messages into approximate topical groups, and then extracting shorter overviews, and longer summaries for each group.
Design and Assurance Strategy for the NRL Pump
Authors: Myong H. Kang, Andrew P. Moore, Ira S. Moskowitz
Venue: Computer (1998)

In the past 20 years, only a handful of high-assurance, multilevel, secure computers have been built, and even these are rarely used in operational environments. Such systems suffer a host of disadvantages: They cost too much, lack user-friendly features and development environments, take too much time to evaluate and certify, and do not scale well for secure distributed computing. This lack of satisfactory security solutions is disturbing in light of the trend toward open and distributed computing, which increases a system's vulnerability to attack. The authors propose basing security solutions instead on a multiple single-level security architecture, which uses commercial (nonsecure) products for general-purpose computing and special- purpose high-assurance devices to separate data at different security levels. A multiple single-level architecture is a viable and practical solution to distributed multilevel secure computing. The keystone of this architecture is a trusted device that "pumps" data from a low security level to a higher one. The authors describe the software design and assurance argument strategy for this device, the Network NRL Pump, which can be used in any multilevel secure distributed architecture.