ppxscal/embedding_network huggingface dataset:
Bit-Level Systolic Array for Fast Exponentiation in GF(2/sup m/)
Authors: Chin-Liang Wang
Venue: IEEE Transactions on Computers (1994)

This paper presents a new parallel-in-parallel-out bit-level systolic array with unidirectional data flow for computing exponentiation in GF(2/sup m/). The array is highly regular, modular, and thus well suited to very-large-scale-integration implementation. In addition, it can provide the maximum throughput in the sense of producing new results at a rate of one per clock cycle. As compared with a previously known systolic GF(2/sup m/) exponentiator with the same throughput performance, the proposed system requires much less chip area, has small latency, and is easier to incorporate fault-tolerant design.
The Constructive Solution of Linear Systems of Partial Difference and Differential Equations with Constant Coefficients
Authors: Ulrich Oberst, Franz Pauer
Venue: Multidimensional Systems and Signal Processing (2001)

This paper gives a survey of past work in the treated subject and also contains several new results. We solve the Cauchy problem for linear systems of partial difference equations on general integral lattices by means of suitable transfer operators and show that these can be easily computed with the help of standard implementations of Gr&ouml;bner basis algorithms. The Borel isomorphism permits to transfer these results to systems of partial differential equations. We also solve the Cauchy problem for the function spaces of convergent power series and for entire functions of exponential type. The unique solvability of the Cauchy problem implies that the considered function spaces are large injective cogenerators for which the duality between finitely generated modules and behaviours holds. Already in the beginning of the last century C. Riquier considered and solved problems of the type discussed here.
A Coarse-to-Fine Deformable Contour Optimization Framework
Authors: Yusuf Sinan Akgul, Chandra Kambhamettu
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (2003)

This paper introduces a novel coarse-to-fine deformable contour optimization framework, which is composed of two main components. The first component uses scale-space and information theories to produce a coarser representation of the input image to be used in a coarse-to-fine optimization scheme. The employment of information theory ensures that maximal image information is propagated to the coarse images and employment of scale spaces provides a mechanism to change the image coarseness locally based on the deformable contour model definition. The second component of this framework uses a novel combination of dynamic programming and gradient descent methods to optimize the contour energy on coarser representations and then use the obtained coarse contour positions in finer optimizations. The motivation in using a combination of dynamic programming and gradient descent method is to take advantage of each method's efficiency and avoid their drawbacks. In order to verify the performance of this framework, we constructed a deformable contour model for the spatiotemporal tracking of closed contours and optimized the model energy under this framework. Experiments on this system performed using synthetic images and real world echocardiographic sequences demonstrated the effectiveness and practicality of this framework.
Why haven't more quantum algorithms been found?
Authors: Peter W. Shor
Venue: Journal of the ACM (JACM) (2003)

I examine the question of why so few classes of quantum algorithms have been discovered. I give two possible explanations for this, and some thoughts about what lines of research might lead to the discovery of more quantum algorithms.
Test Engineering Education is Rational, Feasible, and Relevant
Authors: Richard Absher
Venue: IEEE Design Test (1991)

The author discusses the lack of qualified test engineers and the inadequacy of coordinated test engineer education in institutes of higher learning. He offers a basic curriculum that any university can employ to correct the deficiency. Both undergraduate and graduate programs are outlined.
Power grid transient simulation in linear time based on transmission-line-modeling alternating-direction-implicit method
Authors: Yu Min Lee, Charlie Chung Ping Chen
Venue: Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design (2001)

The soaring clocking frequency and integration density demand robust and stable power delivery to support tens of millions of transistors switching. To ensure the design quality of power delivery, extensive transient power grid simulations need to be performed during design process. However, the traditional circuit simulation engines are not scaled as well as the complexity of power delivery, as a result, it often takes a long runtime and huge memory requirement to simulate a medium size power grid circuit. In this paper, we develop and present a new efficient transient simulation algorithm for power distribution. The proposed algorithm, TLM-ADI (Transmission-Line-Modeling Alternating-Direction-Implicit), first models the power delivery structure as transmission line mesh structure, then solves the transient MNA matrices by the alternating-direction-implicit method. The proposed algorithm, with linear runtime and memory requirement, is also unconditionally stable which ensures that the time-step is not limited by any stability requirement. Extensive experimental results show that the proposed algorithm is not only orders of magnitude faster than SPICE but also extremely memory saving and accurate.
Equivalence Proofs of Some Yield Modeling Methods for Defect-Tolerant Integrated Circuits
Authors: Y. Savaria, C. Thibeault, J. l. Houle
Venue: IEEE Transactions on Computers (1995)

In this paper, two equivalence proofs of yield modeling methods for defect-tolerant integrated circuits (ICs) are presented. These proofs are generalizations of those found in [3]; one of the proofs presented in this paper is valid for any defect-tolerant IC, while the other one is valid for defect-tolerant ICs with two levels of hierarchy.
Survival Patterns in Fast-Moving Software Organizations
Authors: Lena Holmberg, Lars Mathiassen
Venue: IEEE Software (2001)

To survive, fast-moving software organizations must respond quickly to changing market needs and technological options as well as deliver high-quality products and services at competitive prices. They must therefore constantly improve their capabilities. The authors learned important lessons on how to deal effectively with the dilemmas and opportunities involved in such a goal.
Software Quality Assessment and Standards
Venue: Computer (1993)

The development of software product-quality assessment methods is reviewed. Much of the software quality standards work has been performed under the aegis of international organizations such as the IEEE Computer Society and the International Standard Organization/International Electrotechnical Committee Joint Technical Committee No.1 Subcommittee on Software Engineering (ISO JTC1 SC7). An alternative approach that defines a set of requirements for members of a class of software product and certifies those that meet the requirements is described.
Compiler-Assisted Multiple Instruction Rollback Recovery Using a Read Buffer
Authors: Shyh-Kwei Chen, Neal J. Alewine, W. Kent Fuchs, Wen-mei W. Hwu
Venue: IEEE Transactions on Computers (1995)

Multiple instruction rollback (MIR) is a technique that has been implemented in mainframe computers to provide rapid recovery from transient processor failures. Hardware-based MIR designs eliminate rollback data hazards by providing data redundancy implemented in hardware. Compiler-based MIR designs have also been developed which remove rollback data hazards directly with data-flow transformations. This paper describes compiler-assisted techniques to achieve multiple instruction rollback recovery. We observe that some data hazards resulting from instruction rollback can be resolved efficiently by providing an operand read buffer while others are resolved more efficiently with compiler transformations. The compiler-assisted scheme presented consists of hardware that is less complex than shadow files, history files, history buffers, or delayed write buffers, while experimental evaluation indicates performance improvement over compiler-based schemes.
The Softbot Approach to OS Interfaces
Authors: Oren Etzioni, Henry M. Levy, Richard B. Segal, Chandramohan A. Thekkath
Venue: IEEE Software (1995)

Modern, menu-based interfaces make it easier for naive users to issue basic requests, but they do not reduce the difficulty of specifying more sophisticated queries or operations. Sophisticated requests will always require users to combine or customize system-provided primitives -- such as commands or menu operations -- in an ad hoc way because command-language and interface designers cannot anticipate every possible user need. We present a new, goal-oriented approach to the operating-system command interface. A goal-oriented interface lets a user specify what to accomplish, leaving the decision of how to accomplish it to the system. This idea is widely accepted in the functional- and logic-programming communities, but current operating-system interfaces do not support it. In typical modern operating systems, primitives are not available for many common user requests. Currently, the user must write a script or program that composes existing commands. Our approach obviates the need for any programming by the user. We have designed and implemented software robots called softbots: agents that perform high-level tasks on the user's behalf. Softbots use a database that describes the available system primitives. This database describes each primitive in terms of its input, its output, and any conditions that must be met for the primitive to be used. Given a user-specified goal, the softbot constructs a sequence of primitives and invokes them to accomplish that goal, making decisions along the way based on intermediate results and existing conditions. The softbot chooses the most effective means of accomplishing a particular task, relying on commands or information the user may not know.
A Logic-Based Transformation System
Authors: Jeffrey J. P. Tsai, Bing Li, Thomas Weigert
Venue: IEEE Transactions on Knowledge and Data Engineering (1998)

In spite of advances in various transformation systems [5], [8], the transformation of a nonmonotonic-logic-based requirements specification into a procedural (imperative) language program has not been investigated. This paper presents a logic-based transformation system that can transform a nonmonotonic-logic-based specification, the Frame-and-Rule Oriented Requirement Specification Language (FRORL) [12], into procedural language programs. We discuss how to handle nonmonotonic inheritance in FRORL and then establish a matrix-based data flow and dependency analysis mechanism to find all the possible data transformation paths in a logic-based specification. Using a newly developed algorithm, we can adjust the execution sequence of a logic-based specification so that the functions included in the logic-based specification can be represented by a sequential procedural language program.
Energy spectra of quantum rings
Authors: A. Fuhrer, S. L&#x00FC;scher, T. Ihn, T. Heinzel, K. Ensslin, W. Wegscheider, M. Bichler
Venue: Microelectronic Engineering (2002)

High quality quantum rings are fabricated by nano-lithography with a scanning force microscope. The electron occupancy as well the tunneling contacts to source and drain are controlled by in-plane and top gate voltages. Coulomb blockade oscillations in the conductance through the quantum ring give information about the energy spectrum and the wave functions. The Coulomb blockade peak positions as well as the amplitudes oscillate periodically as a function of magnetic field. The period is given by an Aharonov-Bohm-type argument, i.e., one flux quantum h/e through the area defined by the ring. Some states show a pronounced zig-zag behavior as a function of field in agreement with the energy spectrum of a perfect ring. Other states display a rather flat magnetic field dispersion. We argue that the magnetic field behavior of a given state depends on the degree to which its wave function is localized or extended along the circumference around the quantum ring.
Sources of Failure in the Public Switched Telephone Network
Authors: D. Richard Kuhn
Venue: Computer (1997)

The US portion of possibly the largest distributed system in the world, the PSTN is also among the most reliable. But why? The author studied outage records maintained by the US Federal Communications Commission to find out. The FCC data tallies the number and duration of outages as well as the number of customers affected. Although such data are interesting as separate entities, it became clear that a meaningful comparison required their combination. The author used the concept of customer minutes-the number of affected customers multiplied by the length of the outage in minutes-to provide this comparison. The author also used a classification technique that is general enough to compare with other large distributed systems. Major categories of failure include human error, acts of nature, hardware and software failures, overloads, and vandalism. Analysis of the FCC records shows that although human error causes almost half the outages, such outages are relatively short. Overloads-outages accepted as a cost-performance trade-off for the telephone system-affect the most customers for the most minutes. The capability for human intervention is one key to the PSTN's reliability. This system also achieves an excellent trade-off between loose coupling and interaction simplicity, showing that the balance between these characteristics is an important consideration in any distributed-system design. Telephone switch manufacturers also produce extremely reliable software.
Hardware Approaches to Cache Coherence in Shared-Memory Multiprocessors Part 2
Authors: Milo Tomasevic, Veljko Milutinovic
Venue: IEEE Micro (1994)

Improving performance and scalability in shared-memory multiprocessors requires an appropriate solution to the well-known cache coherence problem. Hardware schemes-highly convenient because of their transparency for software-offer fully dynamic solutions, with an ability to achieve high performance. In Part 1 of this two-part series, we discussed the principles of the two major groups of hardware protocols and summarized relevant representatives. Here, we also briefly consider the coherence problem in multilevel cache hierarchies and large-scale, shared-memory multiprocessors.
The Effect of Electronic Markets on Forecasts of New Product Success
Authors: Thomas S. Gruca, Joyce Berg, Michael Cipriano
Venue: Information Systems Frontiers (2003)

In this paper, we extend field experiments of real money prediction markets to the problem of forecasting the success of a new product. We collect forecasts using a traditional survey mechanism and a market mechanism. Our results suggest that market prices summarize the information contained in survey forecasts and improve those forecasts by reducing the variability of the forecast. However, we find no evidence of a &ldquo;crystal ball&rdquo; equilibrium. Our markets have considerable variability and predict only as well as the public signal provided by the HSX movie market game.
A comparative study of arbitration algorithms for the Alpha 21364 pipelined router
Authors: Shubhendu S. Mukherjee, Federico Silla, Peter Bannon, Joel Emer, Steve Lang, David Webb
Venue: ACM SIGARCH Computer Architecture News (2002)

Interconnection networks usually consist of a fabric of interconnected routers, which receive packets arriving at their input ports and forward them to appropriate output ports. Unfortunately, network packets moving through these routers are often delayed due to conflicting demand for resources, such as output ports or buffer space. Hence, routers typically employ arbiters that resolve conflicting resource demands to maximize the number of matches between packets waiting at input ports and free output ports. Efficient design and implementation of the algorithm running on these arbiters is critical to maximize network performance.This paper proposes a new arbitration algorithm called SPAA (Simple Pipelined Arbitration Algorithm), which is implemented in the Alpha 21364 processor's on-chip router pipeline. Simulation results show that SPAA significantly outperforms two earlier well-known arbitration algorithms: PIM (Parallel Iterative Matching) and WFA (Wave-Front Arbiter) implemented in the SGI Spider switch. SPAA outperforms PIM and WFA because SPAA exhibits matching capabilities similar to PIM and WFA under realistic conditions when many output ports are busy, incurs fewer clock cycles to perform the arbitration, and can be pipelined effectively. Additionally, we propose a new prioritization policy called the Rotary Rule, which prevents the network's adverse performance degradation from saturation at high network loads by prioritizing packets already in the network over new packets generated by caches or memory.
Reliability Through Consistency
Authors: Kenneth P. Birman, Bradford B. Glade
Venue: IEEE Software (1995)

In many distributed computing environments, failures are reported in a way that violates even the simplest notions of consistency. The authors argue that such practices are at the root of reliability problems, examine several distributed computing technologies in terms of their consistency, and present strategies for implementing consistent failure reporting.
Bipartite graphs without a skew star
Authors: Vadim V. Lozin
Venue: Discrete Mathematics (2002)

A skew star is a tree with exactly three vertices of degree one being at distance 1, 2, 3 from the only vertex of degree three. In the present paper, we propose a structural characterization for the class of bipartite graphs containing no skew star as an induced subgraph and discuss some applications of the obtained result.
Beyond Bits: The Future of Quantum Information Processing
Authors: Andrew M. Steane, Eleanor G. Rieffel
Venue: Computer (2000)

Today's computers operate on the same fundamental principle as the mechanical devices dreamed up by Charles Babbage in the 19th century and later formalized by Alan Turing: One stable state of the machine represents one number. Even seemingly nonstandard computation models, such as the one based on DNA, share this basic principle. Recently, physicists and computer scientists have realized that not only do their ideas about computing rest on partly accurate principles, but they miss out on a whole class of computation. Quantum physics offers powerful methods of encoding and manipulating information that are not possible within a classical framework. The potential applications of these quantum information-processing methods include provably secure key distribution for cryptography, rapid integer factoring, and quantum simulation. The authors discuss the directions that quantum information theory appears to be heading and the research and applications it has accrued.
Symmetries in trees and parking functions
Authors: Louis H. Kalikow
Venue: Discrete Mathematics (2002)

We investigate a particular symmetry in labeled trees first discovered by Gessel, which can be stated as follows: In the set of rooted labeled trees on n + 1 vertices rooted at the smallest vertex, the number of trees with a descents and b + 1 leaves equals the number of trees with b descents and a + 1 leaves. We present two new ways to prove the symmetry resulting from decompositions of trees, which lead to three different bijections from trees to trees in which leaves and descents are swapped. We also interpret the symmetry in terms of parking functions: the number of parking functions on [n] with a descents and b unfavorable spaces (defined in this paper) equals the number of parking functions on [n] with b descents and a unfavorable spaces. We conclude with a generalization of these results to binary trees.
A Scheduler ASIC for a Programmable Packet Switch
Authors: L. Louis Zhang, Brent Beacham, Massoud Reza Hashemi, Paul Chow, Alberto Leon-Garcia
Venue: IEEE Micro (2000)

We designed a generic, single-queue scheduler engine for use in a programmable packet switch/router to handle IP packets, ATM cells, or a combination of both. Comprising 275,000 gates, the 0.35-micron ASIC is incorporated into a prototype programmable packet switch.
Reducing Interference Among Vector Accesses in Interleaved Memories
Authors: R. Raghavan, J. P. Hayes
Venue: IEEE Transactions on Computers (1993)

Memory interference occurs when two or more concurrent data requests are addressed to the same main memory bank. In vector superconductors, this problem is serious due to the periodic interaction among vectors accesses, and can significantly reduce memory bandwidth and overall system performance. Two techniques can be used to reduce the effects of memory interference. First, vector data can be placed in the main memory such that, when accessed concurrently, the vectors do not interfere with one another. Second, buffers can be used at the memory banks to hold conflicting requests and to allow vector streams to continue to access other banks. Conditions for arbitrary numbers of vector streams to access an interleaved memory system without conflict are derived. It is shown that when three or more vector streams must be accessed concurrently, vector data placement to avoid conflicts becomes increasingly difficult, and that bank buffers can be effective under these conditions in increasing the effective memory bandwidth.
Some Methods Based on the D-Gap Function for Solving Monotone Variational Inequalities
Authors: Michael V. Solodov, Paul Tseng
Venue: Computational Optimization and Applications (2000)

The D-gap function has been useful in developing unconstrained descent methods for solving strongly monotone variational inequality problems. We show that the D-gap function has certain properties that are useful also for monotone variational inequality problems with bounded feasible set. Accordingly, we develop two unconstrained methods based on them that are similar in spirit to a feasible method of Zhu and Marcotte based on the regularized-gap function. We further discuss a third method based on applying the D-gap function to a regularized problem. Preliminary numerical experience is also reported.
Synthesis of CMOS domino circuits for charge sharing alleviation
Authors: Ching Hwa Cheng, Shih Chieh Chang, Shin De Li, Wen Ben Jone, Jinn Shyan Wang
Venue: Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design (2000)

The Charge Sharing (CS) problem is one of notorious noise problems in domino circuits design and test. In this paper, this problem is thoroughly investigated by considering circuit topology and circuit function. The sensitivity of each domino gate to the CS problem is represented by the concept of CS-vulnerability. A method to derive the CS-vulnerability and the test pattern for each domino gate is suggested. We also propose a transistor reordering method to dramatically reduce the CS-vulnerabilities for all domino gates, so that the CS problem can be alleviated. Simulation results demonstrate that our transistor reordering method can efficiently reduce the CS-vulnerabilities for most of domino circuits.
Fault-Tolerant de Bruijn and Shuffle-Exchange Networks
Authors: J. Bruck, R. Cypher, C. T. Ho
Venue: IEEE Transactions on Parallel and Distributed Systems (1994)

This paper addresses the problem of creating a fault-tolerant interconnection network fora parallel computer. Three topologies, namely, the base-2 de Bruijn graph, the base-m deBruijn graph, and the shuffle-exchange, are studied. For each topology an N+k nodefault-tolerant graph is defined. These fault-tolerant graphs have the property that givenany set of k node faults, the remaining N nodes contain the desired topology as asubgraph. All of the constructions given are the best known in terms of the degree of thefault-tolerant graph. We also investigate the use of buses to reduce the degrees of thefault-tolerant graphs still further.