ppxscal/embedding_network huggingface dataset:
Interactive blackbox debugging for concurrent languages
Authors: G. Goldszmidt, S. Katz, S. Yemini
Venue: ACM SIGPLAN Notices (1989)

We describe a novel approach to the design of portable integrated debugging tools for concurrent languages. Our design partitions the tools set into two categories. The language specific tools take into account the particular features of a programming language for on-line experimenting with and monitoring of distributed programs. The language independent tools support off-line presentation and analysis of the monitored information. The separation of the language independent tools from the language specific tools allows adapting the tools to support debugging for a broad category of concurrent programming languages. The separation of interactive experimentation from off-line analysis provides for efficient exploitation of both user time and machine resources. We present an overview of our design and describe the implementation of a prototype debugging facility for OCCAM.
Random number generation on parallel processors
Authors: M. Fushimi
Venue: Proceedings of the 21st conference on Winter simulation (1989)

Recent development of high speed supercomputers has enabled us to perform large scale Monte Carlo simulations which need a tremendous amount of random numbers. There are two types of supercomputers, i.e. pipeline type and processor array type, and we will confine ourselves in this paper to the random number generation on a computer of the latter type. It is desired that not only a sequence of random numbers generated on each processor is of good quality but also sequences generated on different processors are uncorrelated. If we use a linear congruential method on a 32-bit supercomputer, the whole period may be consumed in several seconds to several minutes. Random numbers with a much longer period can be generated by a GFSR algorithm. Using this algorithm, we will propose a method to generate uncorrelated series of random numbers on parallel processors.
Emulation of Hypercube Architecture on Nearest-Neighbor Mesh-Connected Processing Elements
Authors: S. Matic
Venue: IEEE Transactions on Computers (1990)

The problem of emulating a hypercube architecture on nearest-neighbor mesh (NNM) connected processing elements is addressed. The motivation for this study was the recent promotion of the transputer as a possibly very powerful building block of large highly parallel, scalable computer architectures. It is an attempt to achieve hypercubes of different dimensions with a constant, small number of links per processing element. The idea was investigated by means of some less abstract ways of reasoning and computer simulation in an attempt to find the best form of NNM connected processing element structures form the viewpoint of the optimization of certain parameters of the emulated hypercube.
Experiments in automated analysis of concurrent software systems
Authors: G. Avrunin, J. Wileden, L. Dillon
Venue: Proceedings of the ACM SIGSOFT '89 third symposium on Software testing, analysis, and verification (1989)

It is unlikely that any single approach to analysis of concurrent software systems will meet all the needs of software developers throughout the development process. Thus, experimental evaluation of different analysis techniques is needed to determine their relative strengths and practical limitations. Such evaluation requires automated tools implementing the analysis techniques. This paper describes a prototype toolset automating the constrained expression approach to the analysis of concurrent software systems. The results of preliminary experiments with the toolset are reported and the implications of these experiments are discussed.
Microprogramming instruction systolic arrays
Authors: P. M. Lenders, H. Schröder, P. Strazdins
Venue: Proceedings of the 22nd annual workshop on Microprogramming and microarchitecture (1989)

The instruction systolic array (ISA) is a programmable parallel architecture suitable for VLSI implementation. This paper presents a generalization of the ISA, called the microprogrammed ISA, which uses simple microprogramming techniques. Microprogrammed ISAs use dynamic microcodes whose length and contents are tailor made to the current program to be executed, and this can be efficiently implemented in VLSI. Here, microprogramming has the novel advantage of extending the range of algorithms that can be implemented on a given ISA. In particular, microprogramming can extend an ISA's effective communication abilities. Also, the reduction of the program input bandwidth (and pinout) afforded by microprogramming is even more important on large-scale MIMD architectures, such as the ISA. This paper also presents a weakest precondition semantics for the (microprogrammed) ISA model, which provides a means for verifying microprogrammed ISA programs. The semantics is modeled at the micro level, and has potential in the optimization of the microcodes of ISA programs.
Using mathematical logic and formal methods to write correct microcode
Authors: David Shepherd
Venue: ACM SIGMICRO Newsletter (1988)

This paper describes how "correct" microcode can be produced through the use of mathematical logic and formal design methods. The use of these techniques to derive correct microcode for the IMS T800 floating point transputer from a mathematical specification is discussed. This experience on the IMS T800 has shown that this approach provides the opportunity to produce designs with a higher certainty of correctness in significantly less time as compared with "traditional" design techniques. These techniques are currently being applied to the construction of correct specifications at the hardware description language level. This work is attempting to incorporate mathematical logic and formal design methods into the INMOS CAD system so that their use becomes the standard way of producing correct VLSI devices.
Visual metaphors for teaching programming concepts
Authors: Leslie J. Waguespack,  Jr.
Venue: ACM SIGCSE Bulletin (1989)

This paper presents a system of visual metaphors used in a introductory programming course using Pascal. The visual metaphors represent programming concepts (data types, variables, arrays, records, files, modules, module interfaces and parameter passing, and dynamic storage) that are often difficult for beginning students to learn. The metaphors are used to accelerate the students' learning process and improve the overall comprehension of programs as structured objects. The system of metaphors is used in the first course for majors, Foundations of Programming, in the Computer Information Systems curriculum at Bentley College.
Unification theory
Authors: Jörg H. Siekmann
Venue: Journal of Symbolic Computation (1989)

Most knowledge based systems in artificial intelligence (AI), with a commitment to asymbolic representation, support one basic operation: ''matching of descriptions''. This operation, called unification in work on deduction, is the ''addition-and-multiplication'' of AI-systems and is consequently often supported by special purpose hardware or by a fast instruction set on most AI-machines. Unification theory provides the formal framework for investigations into the properties of this operation. This article surveys what is presently known in unification theory and records its early history.
Decision tree reduction
Authors: J. R. B. Cockett, J. A. Herrera
Venue: Journal of the ACM (JACM) (1990)

The reduction algorithm is a technique for improving a decision tree in the abseence of aproecise cost criterion. The result of applying the algorithm is an irreducible tree that is no less efficient than the original, and may be more efficient. Irreducible trees arise in discrete decision theory as an algebraic form for decision trees. This form has significant computational properties. In fact, every irreducible is optimal with respect to some expected testing cost criterion and is strictly better than any given distinct tree with respect to some criterion. Many irreducibles are decision equivalent to a given tree; onely some of these are reductions of the tree. The reduction algorithm is a particular way of finding one of these. It tends to preserve the overall structure of the tree by reducing the subtrees first. A bound on the complexity of this algorithm with input tree t is O(hgt9t)2). usize(t) is the uniform size of the tree (the number of leaves less one) and hgt(t) is the height of the tree. This means that decision tree reduction has the same worst-case order of complexity as most heuristic methods for building suboptimal trees. While the purpose of using heuristics is often rather different, such comparisons are an indication of the efficiency of the reduction algorithms.
Optimal Diagnosis Procedures for k-out-of-n Structures
Authors: M.-F. Chang, W. Shi, W. K. Fuchs
Venue: IEEE Transactions on Computers (1990)

Diagnosis strategies are investigated for repairable VLSI and WSI structures based on integrated diagnosis and repair. Knowledge of the repair strategy, the probability of each unit being good, and the expected test time of each unit is used by the diagnosis algorithm to select units for testing. The general problem is described, followed by an examination of a specific case. For k-out-of-n structures, a complete proof is given for the optimal diagnosis procedure of Y. Ben-Dov (1981). A compact representation of the optimal diagnosis procedure is described, which requires O(n/sup 2/) space and can be generated in O(n/sup 2/) time. Simulation results are provided to show the improvement in diagnosis time over online repair and offline repair.
Integrating Region Growing and Edge Detection
Authors: T. Pavlidis, Y.-T. Liow
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1990)

A method that combines region growing and edge detection for image segmentation is presented. The authors start with a split-and merge algorithm wherein the parameters have been set up so that an over-segmented image results. Region boundaries are then eliminated or modified on the basis of criteria that integrate contrast with boundary smoothness, variation of the image gradient along the boundary, and a criterion that penalizes for the presence of artifacts reflecting the data structure used during segmentation (quadtree in this case). The algorithms were implemented in the C language on a Sun 3/160 workstation running under the Unix operating system. Simple tool images and aerial photographs were used to test the algorithms. The impression of human observers is that the method is very successful on the tool images and less so on the aerial photograph images. It is thought that the success in the tool images is because the objects shown occupy areas of many pixels, making it is easy to select parameters to separate signal information from noise.
Parallel join algorithms on a network of workstations
Authors: X. Wang, W. S. Luk
Venue: Proceedings of the first international symposium on Databases in parallel and distributed systems (2000)

We propose a non-traditional system architecture for backend database processing, i.e., a network of workstations. By moving data dynamically to otherwise idle workstations over a local area network, a high degree of processing parallelism could be achieved through load sharing. In this paper, three load sharing join algorithms are developed and implemented on a network of Sun workstations. These join algorithms are designed on the basis of different assumptions, e.g., whether indices are available and whether join result is required to be sorted. Based on the analyical results and empirical performance data for each algorithm, we are able to show that the load sharing strategy in each case is an effective method to achieve processing speedups. However, the network bandwidth of 10Mbits/second becomes a bottleneck, when more than a dozen or so workstations are deployed, which indicates that a higher bandwidth network is needed for further improvement in performance.
APL descriptions of functional building blocks for connectionist computer models
Authors: A. Surkan
Venue: ACM SIGAPL APL Quote Quad (1989)

APL functions provide concise, array-oriented expressions for describing connection-based computing. These give insights into a variety of neural network-like computer models. Functional decomposition into inherently parallel operation of collective or memory-based computing is effected with the identification of several command-like APL simulation functions.These functions serve to: (a) generate and configure initial values and structures for network layers, connection weights and thresholds, (b) strategically sample training sets to provide acyclic sequences of patterns, (c) update weights for memorizing or learning from the training set, (d) locate units effective for storing and retrieving memories, and (e) use a cue or noise-corrupted pattern for recalling or reconstructing memory associations established during training. Also, APL functions are used to accomodate for data values missing from the training patterns. Other simply described functions generate random fixed reference addresses and initialize modifiable weight values. Test patterns with specified levels of noise contamination are generated by simple APL expressions.
Partitioning and Permuting Properties of CC-Banyan Networks
Authors: V. Cherkassky, M. Malek
Venue: IEEE Transactions on Computers (1989)

A multicomputer network, called rectangular CC-banyan, is presented and formally defined. A graph-theoretic approach is used to study this network's permuting and partitioning properties. It is shown that a CC-banyan has a modular structure and hence can be recursively defined. A method for evaluation of the total number of permutations in CC-banyans is presented. Using this method, the analytical expressions for the number of permutations in CC-banyans with fan-outs of two and three are derived.
Early Computing and Numerical Analysis at the National Bureau of Standards
Authors: William Aspray, Michael Gunderloy
Venue: IEEE Annals of the History of Computing (1989)

By the mid-1950s, computing became a radically new, highly complex, capital-intensive technology - one which required resources that universities were unable and the companies were unwilling to provide. This article tells the story of one government agency, the National Bureau of Standards, whose efforts in those early years helped to bridge this gap and to initiate modern computing.
Optical interconnection using ShuffleNet multihop networks in multi-connected ring topologies
Authors: M. J. Karol
Venue: Symposium proceedings on Communications architectures and protocols (1988)

In many applications, such as metropolitan area, campus, and local area networks, multicomputer interconnection networks, and the interconnection of cabinets, shelves, and boards, optical interconnection is increasingly favored over electrical. Recently, ShuffleNet multihop lightwave networks were proposed as a way to tap the vast bandwidth potential of optical fiber for multiuser packet communications. We consider the use of ShuffleNet multihop networks for optical interconnection, and study their implementation in ring topologies with each node connected to several other nodes of the ring (i.e., multi-connected ring topologies). To minimize fiber cabling congestion, the design procedure uses a new representation of the ShuffleNet connectivity graph and a generalization of Gray code patterns. As an example, only six fibers (without wavelength-division multiplexing) are required to interconnect 24 Network Interface Units (NIUs), providing a total network throughput of 1.47 Gb/s for an optical transmission rate of 100 Mb/s. The design also provides for easy, modular growth of multi-connected rings.
Teaching users to fish: hooks, lines and sinkers for reading computer documentat
Authors: Denise A. Troll
Venue: Proceedings of the 16th annual ACM SIGUCCS Conference on User Services (1988)

Though indeed we are &ldquo;Still Sailing,&rdquo; the sea is not without troubled waters. As Documentation and Training Coordinator for Academic Computing at Carengie Mellon, I have observed that we &ldquo;user advocates&rdquo; spend a great deal of time writing and distributing computer documentation and answering users' questions &mdash; questions that are often already answered in the documents we provide. The inefficiency is apparent, rampant and expensive. Faced with limited resources and a continually expanding list of software and hardware for which we must provide support, the situation can only worsen unless we take direct action. I contend that besides proliferating documents, consultants and trainers, we ought to teach users how to read the documents that we provide, and we ought to raise their expectations of what &ldquo;computer literacy&rdquo; entails. This paper discusses an integrated training procedure designed to accomplish these goals. Two basic assumptions billow the sails of the discussion. They are both moral imperatives based on my ideological understanding of genuine &ldquo;user advocacy.&rdquo; The first is that we ought to provide not only documentation, consultants and trainers, but also a path through the quagmire that these present to novice users. The second is that we ought to define and implement &ldquo;computer literacy&rdquo; in such a way that it leads to the user's independence, not continued dependence on quick answers from easily accessible consultants. The adage &ldquo;If you give a man [sic] a fish, you feed him for a day. But if you teach a man to fish, you feed him for life&rdquo; serves our purposes well. The training procedure presented here attempts to meet these moral imperatives within the financial and academic context in which Carnegie Mellon users set sail.
A unified design representation can work
Authors: P. Kollaritsch, S. Lusky, D. Matzke, D. Smith, P. Stanford
Venue: Proceedings of the 26th ACM/IEEE Design Automation Conference (1989)

A unified design representation can work. This has always been considered impractical due to major problems of run time, space, tool interdependencies, and multiple representations. We have addressed these problems and found them tractable. We present our solutions to these problems, gained through the experience of developing the Droid design system.
On radical zero-dimensional ideals
Authors: Hidetsune Kobayashi, Shuichi Moritsugu, Robert W. Hogan
Venue: Journal of Symbolic Computation (1989)

This paper shows an algorithm to construct the Grobner bases of radicals of zero-dimensional ideals. Computing radicals is equivalent to solving systems of algebraic equations without counting the multiplicities of solutions. We prove that the Grobner basis of a radical zero-dimensional ideal takes a special form after a suitable transformation of coordinates.
Exploiting parallel microprocessor microarchitectures with a compiler code generator
Authors: W. W. Hwu, P. P. Chang
Venue: ACM SIGARCH Computer Architecture News (1988)

With advances in VLSI technology, microprocessor designers can provide more microarchitectural parallelism to increase performance. We have identified four major forms of such parallelism: multiple microoperations issued per cycle, multiple result distribution buses, multiple execution units, and pipelined execution units. The experiments reported in this paper address two important issues: The effects of these forms and the appropriate balance among them. A central microarchitecture is identified as the comparison basis. We separately vary each form of the microarchitectural parallelism in the central to measure their individual effects on performance. In addition, we vary two forms of the microarchitectural parallelism in the central to derive an appropriate balance between them. To make fair comparisons, our compiler generates different code sequences optimized for different microarchitectural configurations. For each given set of technology constraints, these experiments can be used to derive a cost-effective microarchitecture to execute each given set of workload programs at high speed.
The NSFNET backbone network
Authors: D. L. Mills, H. Braun
Venue: Proceedings of the ACM workshop on Frontiers in computer communications technology (1987)

The NSFNET Backbone Network interconnects six supercomputer sites, several regional networks and ARPANET. It supports the DARPA Internet protocol suite and DCN subnet protocols, which provide delay-based routing and very accurate time-synchronization services. This paper describes the design and implementation of this network, with special emphasis on robustness issues and congestion-control mechanisms.
AT/sup 2/-Optimal Galois Field Multiplier for VLSI
Authors: Martin Fürber, Kurt Mehlhorn
Venue: IEEE Transactions on Computers (1989)

VLSI designs for Galois field multipliers, which are central in many encoding and decoding procedures for error-detecting and error-correcting codes, are presented. An AT/sup 2/-optimal Galois-field multiplier based on AT/sup 2/-optimal integer multipliers for a synchronous VLSI model is exhibited. Galois field multiplication is done in two steps. First two polynomials (of degree n-1) over Z/sub p/ are multiplied, and then the resulting polynomial is reduced modulo a fixed irreducible polynomial (of degree n). Multiplication of polynomials is done by discrete Fourier transform (DFT). For p=2, the procedure is more involved for Z/sub p/(x) than for Z(x). An extension to the case of variable p is included and some open problems are stated.
Modular attribute grammars
Authors: G. D. P. Dueck, G. V. Cormack
Venue: The Computer Journal (1990)

Attribute grammars provide a formal declarative notation for describing the semantics and translation of programming languages. Describing any real programming language is a significant software engineering challenge. From a software engineering viewpoint, current notations for attribute grammars have two flaws: tedious repetition of essentially the same attribute computations is inevitable, and the various components of the description cannot be decomposed into modules.&hellip; &mdash;From the Authors' Abstract
Toward an ideal competency-based computer science teacher certification program: the Delphi approach
Authors: J. Wey Chen
Venue: Proceedings of the twentieth SIGCSE technical symposium on Computer science education (1989)

The downward migration of computer science courses from university to secondary and even junior high school level is accelerated by the increasing computer usage in schools and the increasing demands of both parents and students for quality computer education. Teacher training is a major vehicle to the success of this migration. However, at this time, there is no consensus concerning how the secondary school computer science teacher should be certified and what should be included in the study of a computer science teacher certification program. This paper collects data from various computer expert groups through the use of Delphi technique to provide valuable guidelines for establishing a computer science teacher certification program as well as a model curriculum based on the minimum competency required of a successful secondary school computer science teacher.
Type reconstruction with first-class polymorphic values
Authors: J. W. O'Toole,  Jr., D. K. Gifford
Venue: ACM SIGPLAN Notices (1989)

We present the first type reconstruction system which combines the implicit typing of ML with the full power of the explicitly typed second-order polymorphic lambda calculus. The system will accept ML-style programs, explicitly typed programs, and programs that use explicit types for all first-class polymorphic values. We accomplish this flexibility by providing both generic and explicitly-quantified polymorphic types, as well as operators which convert between these two forms of polymorphism. This type reconstruction system is an integral part of the FX-89 programming language. We present a type reconstruction algorithm for the system. The type reconstruction algorithm is proven sound and complete with respect to the formal typing rules.