ppxscal/embedding_network huggingface dataset:
Power Analysis of System-Level On-Chip Communication Architectures
Authors: Kanishka Lahiri, Anand Raghunathan
Venue: Proceedings of the international conference on Hardware/Software Codesign and System Synthesis: 2004 (2004)

For complex System-on-chips (SoCs) fabricated in nanometer technologies, the system-level on-chip communication architecture is emerging as a significant source of power consumption. Managing and optimizing this important component of SoC power requires a detailed understanding of the characteristics of its power consumption. Various power estimation and low-power design techniques have been proposed for the global interconnects that form part of SoC communication architectures (e.g., low-swing buses, bus encoding, etc). While effective, they only address a limited part of communication architecture power consumption. A state-of-the-art communication architecture, viewed in its entirety, is quite complex, comprising several components, such as bus interfaces, arbiters, bridges, decoders, and multiplexers, in addition to the global bus lines. Relatively little research has focused on analyzing and comparing the power consumed by different components of the communication architecture. In this work, we present a systematic evaluation and analysis of the power consumed by a state-of-the-art communication architecture (the AMBA on-chip bus), using a commercial design flow. We focus on developing a quantitative understanding of the relative contributions of different communication architecture components to its power consumption, and the factors on which they depend. We decompose the communication architecture power into power consumed by logic components (such as arbiters, decoders, bus bridges), global bus lines (that carry address, data, and control information), and bus interfaces. We also perform studies that analyze the impact of varying application traffic characteristics, and varying SoC complexity, on communication architecture power. Based on our analyses, we evaluate different techniques for reducing the power consumed by the on-chip communication architecture, and compare their effectiveness in achieving power savings at the system level. In addition to quantitatively reinforcing the view that on-chip communication is an important target for system-level power optimization, our work demonstrates (i) the importance of considering the communication architecture in its entirety, and (ii) the opportunities that exist for power reduction through careful communication architecture design.
A Nonlinear Technique for Enhancement of Color Images: An Architectural Perspective for Real-Time Applications
Authors: Hau T. Ngo, Li Tao, Vijayan K. Asari
Venue: Proceedings of the 33rd Applied Imagery Pattern Recognition Workshop (2004)

In this paper, an efficient hardware design for a nonlinear technique for enhancement of color images is presented. The enhancement technique works very effectively for images captured under extremely dark environment as well as non-uniform lighting environment where 'bright' regions are kept unaffected and 'dark' objects in 'bright' background. For efficient implementation of the nonlinear technique on a targeted FPGA board, estimation techniques for logarithm and inverse logarithm are introduced. The estimation method helps to reduce the computational time and FPGA resources significantly compared to conventional implementations of computational intensive operations such as logarithm. The enhancement technique is further analyzed and rearranged into hardware algorithmic steps to better suit the high performance implementation. A number of parallel functional modules are designed to operate simultaneously to optimally utilize the operation-level parallelism available in the technique. Sequential operations are partitioned into well-balance workload stages of a pipelined system based on the inter-data-dependency of the algorithmic steps to better utilize the resources in a FPGA such as on-chip RAM and logic-blocks. The image enhancement system is designed to target the high-performance for real time color image enhancement with minimum 25 frames per second.
Domain Specific Reconfigurable Architecture of Turbo Decoder Optimized for Short Distance Wireless Communication
Authors: Imran Ahmed, Tughrul Arslan, Sajid Baloch, Ian Underwood, Robin Woodburn
Venue: Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04 (2005)

This paper describes low power, reconfigurable architectures for Turbo Decoder. Currently most of the reconfigurable solutions in research target reconfiguration between different convolution based decoders for example Viterbi-Sova or Sova-LogMap. The reconfigurable Turbo decoder array presented in this paper not only provides flexibility to choose between different constraint lengths, frame lengths and code rates but also different levels of quantization. Similarly, dynamic or static mapping of different algorithms can be done to meet various performance constraints in terms of reduced power, improved speed and different levels of error correction. The architecture can support channel decoding for most of the current communication systems.
Multi-Instance Learning Based Web Mining
Authors: Zhi-Hua Zhou, Kai Jiang, Ming Li
Venue: Applied Intelligence (2005)

In multi-instance learning, the training set comprises labeled bags that are composed of unlabeled instances, and the task is to predict the labels of unseen bags. In this paper, a web mining problem, i.e. web index recommendation, is investigated from a multi-instance view. In detail, each web index page is regarded as a bag, while each of its linked pages is regarded as an instance. A user favoring an index page means that he or she is interested in at least one page linked by the index. Based on the browsing history of the user, recommendation could be provided for unseen index pages. An algorithm named Fretcit-kNN, which employs the Minimal Hausdorff distance between frequent term sets and utilizes both the references and citers of an unseen bag in determining its label, is proposed to solve the problem. Experiments show that in average the recommendation accuracy of Fretcit-kNN is 81.0% with 71.7% recall and 70.9% precision, which is significantly better than the best algorithm that does not consider the specific characteristics of multi-instance learning, whose performance is 76.3% accuracy with 63.4% recall and 66.1% precision.
Convex Optimal Control Problems with Smooth Hamiltonians
Authors: Rafal Goebel
Venue: SIAM Journal on Control and Optimization (2005)

Optimal control problems with convex costs, for which Hamiltonians have Lipschitz continuous gradients, are considered. Examples of such problems, including extensions of the linear-quadratic regulator with hard and possibly state-dependent control constraints, and piecewise linear-quadratic penalties are given. Lipschitz continuous differentiability and strong convexity of the terminal cost are shown to be inherited by the value function, leading to Lipschitz continuity of the optimal feedback. With no regularity assumptions on the limiting problem, epi-convergence of costs, which can be equivalently described by pointwise convergence of Hamiltonians, is shown to guarantee epi-convergence of value functions. Resulting schemes of approximating any concave-convex Hamiltonian by continuously differentiable ones are displayed. Auxiliary results about existence and stability of saddle points of quadratic functions over polyhedral sets are also proved. Tools used are based on duality theory of convex and saddle functions.
Using a common architecture in Australian e-Government: the case of smart service Queensland
Authors: Nigel Martin, Shirley Gregor, Dennis Hart
Venue: Proceedings of the 6th international conference on Electronic commerce (2004)

In this paper, we present the findings of a case study which examines the use of enterprise architectures in the context of the development and implementation of an Electronic Government (e-Government) Services Delivery initiative by the Queensland State government of Australia. The paper employs strategic alignment theory to critically examine the progress of the initiative from the development of public policy and business case documents, through to the pilot program, and progressive implementation of an electronic government environment that includes a number of redesigned Internet gateways, integrated contact (call) centres, electronic kiosks, and web-enabled customer service counters. The case is also compared with similar e-Government initiatives and provides an interesting example of how governments can use the electronic domain to service a diverse range of clients in a large and wide spread community.
Techniques for Efficient Road-Network-Based Tracking of Moving Objects
Authors: Alminas Civilis Christian S. Jensen
Venue: IEEE Transactions on Knowledge and Data Engineering (2005)

With the continued advances in wireless communications, geo-positioning, and consumer electronics, an infrastructure is emerging that enables location-based services that rely on the tracking of the continuously changing positions of entire populations of service users, termed moving objects. This scenario is characterized by large volumes of updates, for which reason location update technologies become important. A setting is assumed in which a central database stores a representation of each moving object's current position. This position is to be maintained so that it deviates from the user's real position by at most a given threshold. To do so, each moving object stores locally the central representation of its position. Then, an object updates the database whenever the deviation between its actual position (as obtained from a GPS device) and the database position exceeds the threshold. The main issue considered is how to represent the location of a moving object in a database so that tracking can be done with as few updates as possible. The paper proposes to use the road network within which the objects are assumed to move for predicting their future positions. The paper presents algorithms that modify an initial road-network representation, so that it works better as a basis for predicting an object's position; it proposes to use known movement patterns of the object, in the form of routes; and, it proposes to use acceleration profiles together with the routes. Using real GPS-data and a corresponding real road network, the paper offers empirical evaluations and comparisons that include three existing approaches and all the proposed approaches.
Component vs. Component: Why We Need More Than One Definition
Authors: Bernhard Grone, Andreas Knopfel, Peter Tabeling
Venue: Proceedings of the 12th IEEE International Conference and Workshops on Engineering of Computer-Based Systems (2005)

This paper discusses the different meanings of the word component in various contexts of software engineering. To overcome this ambiguity we propose to distinguish between two fundamental meanings of the term which should be emphasized by using different names.
2.5GHz PLL with current matching charge-pump for 10Gbps transmitter design
Authors: Jaehong Ko, Wookwan Lee, Soo-Won Kim
Venue: Proceedings of the 15th ACM Great Lakes symposium on VLSI (2005)

In this paper, we describe a mixed PLL architecture for low jitter clock generation that use a proposed charge pump and output buffer. The newly designed charge-pump circuit is composed of two differential inputs, the signals of UP and DN from the PFD, and an op-amp that matches between the upper current and the lower current. If the two currents are matched in charge-pump there is a low ripple voltage, which is VCO control voltage. The new charge pump circuit has a good immunity from MOSFET width and length variation. Also, we build the differential current driving output buffer for high speed signal processing on a chip. In the newly designed output buffer circuits, the push-pull source follower is added to the previous differential current driving output buffer. As the result, the jitter characteristic has been improved. The PLL with current matching charge-pump has been designed by 0.18͘m one-poly four metal CMOS technology and simulated by HSPICE. From the simulation results, it is shown that the VCO control voltage is at least 0.6mV.
An efficient method for the numerical solution of one-phase Stefan problems (abstract)
Authors: L. F. Shampine, R. J. Thompson
Venue: ACM SIGNUM Newsletter (1975)

The purpose of this talk is to discuss an implicit numerical method for the solution of a class of Stefan problems. The method is efficient in the sense that, although the location of the moving boundary is determined by solving a sequence of problems, the amount of computation done to advance the solution one time step is little more than would be required if the boundary were fixed.
A new tractable class of constraint satisfaction problems
Authors: Víctor Dalmau
Venue: Annals of Mathematics and Artificial Intelligence (2005)

In this paper we consider constraint satisfaction problems where the set of constraint relations is fixed. Feder and Vardi (1998) identified three families of constraint satisfaction problems containing all known polynomially solvable problems. We introduce a new class of problems called para-primal problems, incomparable with the families identified by Feder and Vardi (1998) and we prove that any constraint problem in this class is decidable in polynomial time. As an application of this result we prove a complete classification for the complexity of constraint satisfaction problems under the assumption that the basis contains all the permutation relations. In the proofs, we make an intensive use of algebraic results from clone theory about the structure of para-primal and homogeneous algebras.
On Event Spaces and Probabilistic Models in Information Retrieval
Authors: Stephen Robertson
Venue: Information Retrieval (2005)

A basic notion of probability theory is the event space, on which the probability measure is defined. A probabilistic model needs an event space. However, some classes of events (which we may want to model probabilistically) exhibit structure which does not fit well into the traditional event space notion. A simple one-to-many example is discussed at length. The information retrieval case, involving queries, documents and relevance, is analysed. The event space issue makes for some difficulty in comparing different probabilistic models in IR.
The impact of grain size on the efficiency of embedded SIMD image processing architectures
Authors: Antonio Gentile
Venue: Journal of Parallel and Distributed Computing (2004)

Pixel-per-processing element (PPE) ratio-the amount of image data directly mapped to each processing element-has a significant impact on the area and energy efficiency of embedded SIMD architectures for image processing applications. This paper quantitatively evaluates the impact of PPE ratio on system performance and efficiency for focal-plane SIMD image processing architectures by comparing throughput, area efficiency, and energy efficiency for a range of common application kernels using architectural and workload simulation. While the impact of grain size is affected by the mix of executed instructions within an application program, the most efficient PPE ratio often does not occur at PE grain size extremes (i.e., one pixel per processor or one processor per image). In this study, a set of four image processing application tasks is implemented on eight different SIMD configurations. Each configuration has a different PPE ratio and a different amount of local memory. Cycle accurate simulation and analytical technology modeling allows assessment of execution performance, area efficiency, and energy efficiency for each configuration. Results show the highest area and energy efficiency are achieved at PPE ratios between 16 and 256. Using these evaluation techniques (application grain size retargeting combined with area and energy technology modeling), a new class of efficient, embedded SIMD architectures for image processing can be designed.
Towards a framework for source code instrumentation measurement validation
Authors: Haleh Najafzadeh, Seth Chaiken
Venue: Proceedings of the 5th international workshop on Software and performance (2005)

Ignoring monitoring overhead and not validating measurements are two common mistakes in benchmarking. We extend, apply and evaluate for a practical FFT library our own methodologies for overhead compensation and over-all validation. The overhead and error sources we address include the source instrumentation and separate activities unrelated to the phenomena under study. We are able to quantify the differences with simpler compared with more portable probe technology and relate them to compiler optimization effects. Finally we formulate our framework for validating performance measurement using software accessible counters within existing framework for general software measurements.
A Tensor Decomposition for Geometric Grouping and Segmentation
Authors: Venu Madhav Govindu
Venue: Proceedings of the 2005 IEEE Computer Society Conference on Computer Vision and Pattern Recognition (CVPR'05) - Volume 1 - Volume 01 (2005)

While spectral clustering has been applied successfully to problems in computer vision, their applicability is limited to pairwise similarity measures that form a probability matrix. However many geometric problems with parametric forms require more than two observations to estimate a similarity measure, e.g. epipolar geometry. In such cases we can only define the probability of belonging to the same cluster for an n-tuple of points and not just a pair, leading to an n-dimensional probability tensor. However spectral clustering methods are not available for tensors. In this paper we present an algorithm to infer a similarity matrix by decomposing the n-dimensional probability tensor. Our method exploits the super-symmetry of the probability tensor to provide a randomised scheme that does not require the explicit computation of the probability tensor. Our approach is fast and accurate and its applicability is illustrated on two significant problems, namely perceptually salient geometric grouping and parametric motion segmentation (like affine, epipolar etc.)
The on demand computing paradigm - what it is, why it emerged, and where it's going
Authors: Bob Yellin
Venue: Journal of Computing Sciences in Colleges (2004)

Bob Yellin in Vice President of Technology for IBM Tivoli Systems, a prominent Austin based startup that was acquired by IBM in 1996. In this capacity he is responsible for the technical architecture of IBM's systems management product line. Bob has 30 years of experience in many facets of the IT industry. He began his career as Director of Database and Data Communication at Aetna Life and Casualty, then moved on to build the development team as VP of Development for Business Systems Technology Inc, a Boston area based startup that specialized in change control and configuration management software. BST was acquired by Legent Corporation, a systems management vendor. There, Bob assumed the role of Senior Vice President of Development and Technology. The ACM Portal is published by the Association for Computing Machinery. Copyright © 2010 ACM, Inc. Terms of Usage Privacy Policy Code of Ethics Contact Us Useful downloads: Adobe Acrobat QuickTime Windows Media Player Real Player
On the structure of (P5,gem)-free graphs
Authors: Andreas Brandstädt, Dieter Kratsch
Venue: Discrete Applied Mathematics (2005)

We give a complete structure description of (P5,gem)-free graphs. By the results of a related paper, this implies bounded clique width for this graph class. Hereby, as usual, the P5 is the induced path with five vertices a, b, c, d, e and four edges ab, bc, cd, de, and the gem consists of a P4 a, b, c, d with edges ab, bc, cd plus a universal vertex e adjacent to a, b, c, d.
Programming Php
Authors: Kevin Tatroe
Venue:  (2005)

Programming PHP, 2nd Edition, is the authoritative guide to PHP 5 and is filled with the unique knowledge of the creator of PHP (Rasmus Lerdorf) and other PHP experts. When it comes to creating websites, the PHP scripting language is truly a red-hot property. In fact, PHP is currently used on more than 19 million websites, surpassing Microsoft's ASP .NET technology in popularity. Programmers love its flexibility and speed; designers love its accessibility and convenience.As the industry standard book on PHP, all of the essentials are covered in a clear and concise manner. Language syntax and programming techniques are coupled with numerous examples that illustrate both correct usage and common idioms. With style tips and practical programming advice, this book will help you become not just a PHP programmer, but a good PHP programmer. Programming PHP, Second Edition covers everything you need to know to create effective web applications with PHP. Contents include:Detailed information on the basics of the PHP language, including data types, variables, operators, and flow control statementsChapters outlining the basics of functions, strings, arrays, and objectsCoverage of common PHP web application techniques, such as form processing and validation, session tracking, and cookiesMaterial on interacting with relational databases, such as MySQL and Oracle, using the database-independent PEAR DB library and the new PDO LibraryChapters that show you how to generate dynamic images, create PDF files, and parse XML files with PHPAdvanced topics, such as creating secure scripts, error handling, performance tuning, and writing your own C language extensions to PHPA handy quick reference to all the core functions in PHP and all the standard extensions that ship with PHPPraise for the first edition:"If you are just getting into the dynamic Web development world or you are considering migrating from another dynamic web product to PHP, Programming PHP is the book of choice to get you up, running, and productive in a short time."--Peter MacIntrye, eWeek"I think this is a great book for programmers who want to start developing dynamic websites with PHP. It gives a detailed overview of PHP, lots of valuable tips, and a good sense of PHP's strengths."--David Dooling, Slashdot.org
A Reconfigurable Processor Based on ALU Array Architecture with Limitation on the Interconnection
Authors: Makoto Okada, Tatsuo Hiramatsu, Hiroshi Nakajima, Makoto Ozone, Katsunori Hirase, Shinji Kimura
Venue: Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04 (2005)

Dynamic reconfigurable processor based on ALU array architecture for consumer appliances is described. To implement reconfigurable system on portable or mobile products, we have tried to develop smaller and powerful reconfigurable processor. We have proposed the ALU array architecture with the limitation on the interconnection for area reduction. By the proposed architecture, we could reduce gate size by 63% on interconnections. Also, we have shown that the performance of proposed architecture is almost the same as one without limitations. The proposed processor is a parallel processing processor that consists of a sequencer and an ALU array, adopted multi threading technology. We have developed compilation tools from source codes written in C language for the proposed processor. We demonstrate the software model of the processor using MPEG-4 video decoding application.