ppxscal/embedding_network huggingface dataset:
Evaluating the Effect of Coherence Protocols on the Performance of Parallel Programming Constructs
Authors: Ricardo Bianchini, Enrique V. Carrera, Leonidas Kontothanassis
Venue: International Journal of Parallel Programming (1998)

The different implementations of parallel programming constructs interact heavily with a multiprocessor's coherence protocol and thus may have a significant impact on performance. The form and extent of this interaction have not been established so far however, particularly in the case of update-based coherence protocols. In this paper we study the running time and communication behavior of ticket and MCS spin locks; centralized, dissemination, and tree-based barriers; parallel and sequential reductions; linear broadcasting and producer and consumer-driven logarithmic broadcasting; and centralized and distributed task queues, under pure and competitive update coherence protocols on a scalable multiprocessor; results for a write invalidate protocol are presented mostly for comparison purposes. Our experiments indicate that parallel programming techniques that are well-established for write invalidate protocols, such as MCS locks and task queues, are often inappropriate for update-based protocols. In contrast, techniques such as dissemination and tree barriers achieve superior performance under update-based protocols. Our results also show that update-based protocols sometimes lead to different design decisions than write invalidate protocols. Our main conclusion is that indeed the interaction of the parallel programming constructs with the multiprocessor's coherence protocol has a significant impact on performance. The implementation of these constructs must be carefully matched to the coherence protocol if ideal performance is to be achieved.
Constraint analysis for DSP code generation
Authors: Bart Mesman, Marino T. J. Strik, Adwin H. Timmer, Jef L. van Meerbergen, Jochen A. G. Jess
Venue: Proceedings of the 10th international symposium on System synthesis (1997)

Code generation methods for DSP applications are hampered by the combination of tight timing constraints imposed by the performance requirements of DSP algorithms, and resource constraints imposed by a hardware architecture. In this paper, we present a method to analyze resource- and timing constraints in a single model. The analysis identifies sequencing constraints between operations additional to the precedence constraints. Without the explicit modeling of these sequencing constraints, a scheduler is often not capable of finding a solution that satisfies the timing and resource constraints. The presented approach results in an efficient method of obtaining high quality instruction schedules.
On the Optimization Criteria Used in Two-View Motion Analysis
Authors: Zhengyou Zhang
Venue: IEEE Transactions on Pattern Analysis and Machine Intelligence (1998)

The three best-known criteria in two-view motion analysis are based, respectively, on the distances between points and their corresponding epipolar lines, on the gradient-weighted epipolar errors, and on the distances between points and the reprojections of their reconstructed points. The last one has a better statistical interpretation, but is, however, significantly slower than the first two. In this paper, I show that, given a reasonable initial guess of the epipolar geometry, the last two criteria are equivalent when the epipoles are at infinity, and differ from each other only a little even when the epipoles are in the image, as shown experimentally. The first two criteria are equivalent only when the epipoles are at infinity and when the observed object/scene has the same scale in the two images. This suggests that the second criterion is sufficient in practice because of its computational efficiency. Experiments with several thousand computer simulations and four sets of real data confirm the analysis. The result is valid for both calibrated and uncalibrated images.
Formal derivation of efficient parallel programs by construction of list homomorphisms
Authors: Zhenjiang Hu, Hideya Iwasaki, Masato Takechi
Venue: ACM Transactions on Programming Languages and Systems (TOPLAS) (1997)

It has been attracting much attention to make use of list homomorphisms in parallel programming because they ideally suit the divide-and-conquer parallel paradigm. However, they have been usually treated rather informally and ad hoc in the development of efficient parallel programs. What is worse is that some interesting functions, e.g., the maximum segment sum problem, are basically not list homomorphisms. In this article, we propose a systematic and formal way for the construction of a list homomorphism for a given problem so that an efficient parallel program is derived. We show, with several well-known but nontrivial problems, how a straightforward, and &ldquo;obviously&rdquo; correct, but quite inefficient solution to the problem can be successfully turned into a semantically equivalent &ldquo;almost list homomorphism.&rdquo; The derivation is based on two transformations, namely tupling and fusion, which are defined according to the specific recursive structures of list homomorphisms.
UCL+P&mdash;Defining and Implementing Persistent Common Lisp
Authors: J. H. Jacobs, M. R. Swanson
Venue: Lisp and Symbolic Computation (1997)

The Persistent Lisp language was defined and an implementation, UCL+P, 1 was designed and constructed. Persistent Lisp is a superset of Common Lisp which fully supports the development of programs manipulating persistent data while maintaining Lisp semantics across the storage/retrieval of values. Persistence features provided are concurrent atomic transactions, demand loading of values, and transparent load and store of persistent values.All Common Lisp data types (with the exception of streams) can be made persistent. Nonsymbolic values are initially created as transient values on the runtime heap. When a transaction completes, transient values which are reachable from a persistent symbol become persistent. The package mechanism has been extended to add a persistence attribute to packages. When symbols are interned in a package with the persistence attribute, they become persistent, as do values reachable from them.UCL+P was created to support these features, by making extensive low-level modifications to the UCL compiler and runtime system. A new runtime data structure, the indirection vector, was created to support the relocation of newly persistent values from the runtime heap to the persistent heap.
Deriving Logic Systems for Path Delay Test Generation
Authors: Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal
Venue: IEEE Transactions on Computers (1998)

We present an algorithm to derive logic systems for various classes of path delay test problems. In these logic systems, the value of a signal represents the relevant conditions that occur during a set of consecutively applied vectors. Starting from a set of basic values for valid signals at primary inputs, a state transition graph is constructed to enumerate all possible signal states relevant to path activation that are reachable by Boolean operations. These states include all incompletely specified states, composed as combinations of basic values. A distinguishability analysis then finds all state-pairs that need to be distinguished during test generation. The final step minimizes the number of states. For forward and backward implications of test generation in combinational or sequential circuits, the procedure provides optimal logic systems. We define optimality as the smallest set of logic states that provides the least possible ambiguity in implications. Thus, an optimal set of logic states will minimize the number of backtracks in test generation. A 10-valued logic described in the literature is found to be optimal for generating tests for single path delay faults. Other problems addressed in this paper include compact test generation through activation of many single path delay faults, test generation for rated-clock test application, and test generation for multiple path delay faults. The limitations and capabilities of various logic systems are illustrated by examples.
Hypercubes and Multicommodity Flows
Authors: B. Yu, J. Cheriyan, P. E. Haxell
Venue: SIAM Journal on Discrete Mathematics (1997)

The average degree of a subgraph $H$ of the $r$-dimensional hypercube $Q_r$ equals at most the maximum Hamming distance of any two nodes in $H$. A corollary is that the minimum number of edges to delete from $Q_r$ such that any two nodes at Hamming distance $\ell$ are separated is $(r+1-\ell) 2^{r-1}$. This corollary has applications to multicommodity flows.
Approximation Algorithms for PSPACE-Hard Hierarchically and Periodically Specified Problems
Authors: Madhav V. Marathe, Harry B. Hunt,  III, Richard E. Stearns, Venkatesh Radhakrishnan
Venue: SIAM Journal on Computing (1998)

We study the efficient approximability of basic graph and logic problems in the literature when instances are specified hierarchically as in [T. Lengauer, J. Assoc. Comput. Mach., 36(1989), pp. 474--509] or are specified by one-dimensional finite narrow periodic specifications as in [E. Wanke, Paths and cycles in finite periodic graphs, in Lecture Notes in Comp. Sci. 711, Springer-Verlag, New York, 1993, pp. 751--760]. We show that, for most of the problems $\Pi$ considered when specified using k-level-restricted hierarchical specifications or k-narrow periodic specifications, the following hold. Let $\rho$ be any performance guarantee of a polynomial time approximation algorithm for $\Pi$, when instances are specified using standard specifications. Then $\forall \epsilon > 0$, $ \Pi$ has a polynomial time approximation algorithm with performance guarantee $(1 + \epsilon) \rho$. $\Pi$ has a polynomial time approximation scheme when restricted to planar instances. These are the first polynomial time approximation schemes for PSPACE-hard hierarchically or periodically specified problems. Since several of the problems considered are PSPACE-hard, our results provide the first examples of natural PSPACE-hard optimization problems that have polynomial time approximation schemes. This answers an open question in Condon et al.\ [Chicago J. Theoret. Comput. Sci., 1995, Article 4].
Efficient Solution of Constrained Least Squares Problems with Kronecker Product Structure
Authors: Anders Barrlund
Venue: SIAM Journal on Matrix Analysis and Applications (1998)

A computational method for efficient solution of linear constrained least squares problems with Kronecker product structure is presented. The equality constraints are assumed to be linearly independent. The computational efficiency of the method is analyzed. Conditions for uniqueness of solutions are given.
ASK digital demodulation scheme for noise immune infrared data communication
Authors: Hiroshi Uno, Keiji Kumatani, Hiroyuki Okuhata, Isao Shirakawa, Toru Chiba
Venue: Wireless Networks (1997)

A high performance architecture is proposed for the ASK (Amplitude Shift Keying) digital demodulation, which is dedicated to the noise immune wireless infrared data communication. In this architecture, an infrared subcarrier detected by a photodetector is digitized into TTL interface level pulses, and the digitized subcarrier is demodulated by a 1-bit digital demodulator. To improve the noise immunity against fluorescent lamps, the optical noises from the lamps are analyzed and the behavior of an ASK infrared communication link is modeled under these noises. On the basis of this model, a digital demodulator is synthesized by means of a high level synthesis tool, aiming at implementing an algorithm of discriminating the subcarrier from optical noises. A part of experimental results shows that the ASK receiver realized with the use of this digital demodulator can achieve an error free infrared link even under the intense noises from fluorescent lamps.
A new paradigm for manufacturing enterprise modeling: reusable, multi-tool modeling
Authors: Dursun Delen, David B. Pratt, Manjunath Kamath
Venue: Proceedings of the 28th conference on Winter simulation (1996)

The power of modeling of manufacturing systems can be enhanced through the application of reusable and pluggable modeling constructs. In this paper we discuss a framework for model reusability and how the seperation concept together with object oriented paradigm support this capability. We then discuss the importance of reusable and pluggable organizational controls in a modeling environment. Several important issues related to the implementation of reusability and pluggability are summarized. Examples are presented to illustrate our approach for implementing reusable and pluggable organizational controls.
Split circuit model for test generation
Authors: Wu-Tung Cheng
Venue: Proceedings of the 25th ACM/IEEE Design Automation Conference (1988)

Over the years, the D-algorithm has been successfully used to generate tests for sequential circuits and combinational circuits. There are 5-valued and 9-valued circuit models used for the D-algorithm. The disadvantage of a model with lower value count is its inability to assign a more precise value for a test generation requirement without some undue assumptions or decisions which may cause backtracks or even may find no test for testable faults. However, the availability of more values increases the search space and makes enumeration more complicated. In this paper, we will present a new circuit model SPLIT which is a modified 9-valued circuit model. SPLIT has the precision of the 9-valued model and the simplicity of the 5-valued model, such that the D-algorithm will have better performance using the SPLIT model than using the 5-valued model or the 9-valued model.
The design and implementation of the GILENA natural language interfaces specification system
Authors: John A. Atkinson-Abutridy, Anita A. Ferreira-Cabrera
Venue: ACM SIGPLAN Notices (1998)

This paper considers a finite-state parsing algorithm for implementing natural language interfaces. The algorithm has some practical improvements compared to other recognizing algorithms. Resolution of syntax ambiguity, programming facilities and post execution of semantic actions are discussed too.Our approach was implemented in order to design the GILENA software tool which automatically allows to generate natural language interfaces. In addition, our designed algorithm, its implementation and its results are discussed.
Images and Preimages in Random Mappings
Authors: Michael Drmota, Michèle Soria
Venue: SIAM Journal on Discrete Mathematics (1997)

We present a general theorem that can be used to identify the limiting distribution for a class of combinatorial schemata. For example, many parameters in random mappings can be covered in this way. In particular, we can derive the limiting distribution of those points with a given number of total predecessors.
Md2 is not Secure Without the Checksum Byte
Authors: N. Rogier, Pascal Chauvaud
Venue: Designs, Codes and Cryptography (1997)

In 1989, Ron Rivest introduced the MD2 Message Digest Algorithm which takes as input a message of arbitrary length and produces as output a 128-bit message digest, by appending some redundancy to the message and then iteratively applying a 32 bytes to 16 bytes compression function. MD2 Message Digest Algorithm is one of the most frequently used hashing function with MD4, MD5, SHA, SHA-1. Some attacks against MD4 and MD5 have been presented by Dobbertin. Up to now, no attack against MD2 has been presented.This function has been updated in 1993 in the RFC 1423 document. It was conjectured that the number of operations needed to get two messages having the same message digest is on the order of 2^64 (using the birthday paradox), and that the complexity of inverting the hash function is on the order of 2^128 operations. No attack against this function has been published so far. In this paper, we propose a low complexity method to find collisions for the compression function of MD2. The easiness to find these collisions could imply that the first conjecture is false if these collisions can be used to make global collisions for MD2.
Verification of Real-Time Systems using Linear Relation Analysis
Authors: Nicolas Halbwachs, Yann-Erick Proy, Patrick Roumanoff
Venue: Formal Methods in System Design (1997)

Linear Relation Analysis [11] is an abstract interpretation devoted to the automatic discovery of invariant linear inequalities among numerical variables of a program. In this paper, we apply such an analysis to the verification of quantitative time properties of two kinds of systems: synchronous programs and linear hybrid systems.
Using Level 3 BLAS in Rotation-Based Algorithms
Authors: Bruno Lang
Venue: SIAM Journal on Scientific Computing (1998)

This paper presents a technique that allows using level 3 BLAS in a number of rotation-based algorithms. In particular, the update of an orthogonal transformation matrix which often involves the vast majority of operations can be done with a matrix--matrix product. As a case study, the technique is applied to the QR and QL algorithms for computing the eigensystem of a symmetric tridiagonal matrix. The modifications do not affect the convergence properties of the algorithms nor do they significantly increase the overall number of operations. Thus, the computations can be sped up by more than 50% on machines with a distinct memory hierarchy, like the Intel i860 or IBM RS/6000, provided the block size is set appropriately. We also present a simple theoretical analysis that allows selecting an almost-optimal block size.
Efficient Algorithms for the Reduce-Scatter Operation in LogGP
Authors: Giulio Iannello
Venue: IEEE Transactions on Parallel and Distributed Systems (1997)

We consider the problem of efficiently performing a reduce-scatter operation in a message passing system. Reduce-scatter is the composition of an element-wise reduction on vectors of n elements initially held by n processors, with a scatter of the resulting vector among the processors. In this paper, we present two algorithms for the reduce-scatter operation, designed in LogGP. The first algorithm assumes an associative and commutative reduction operator and it is optimal in LogGP within a small constant factor. The second algorithm allows the reduction operator to be noncommutative, and it is asymptotically optimal when values to be combined are large arrays. To achieve these results, we developed a complete analysis of both algorithms in LogGP, including the derivation of lower bounds for the reduce-scatter operation, and the study of the m-item version of the problem, i.e., the case when the initial elements are vectors themselves. Reduce-scatter has been included as a collective operation in the MPI standard message passing library, and can be used, for instance, in parallel matrix-vector multiply when the matrix is decomposed by columns. To model a message passing system, we adopted the LogGP model, an extension of LogP that allows the modeling of messages of different length. While this choice makes the analysis somewhat more complex, it leads to more realistic results in the case of gather/scatter algorithms.
BECOME: behavior level circuit synthesis based on structure mapping
Authors: Ruey-Sing Wei, Steven Rothweiler, Jing-Yang Jou
Venue: Proceedings of the 25th ACM/IEEE Design Automation Conference (1988)

The BECOME system for behavior level circuit synthesis is presented. BECOME accepts circuit models written in C-like behavior level modeling languages and synthesizes them into different technologies such as PLA, PLD and standard cells. The system assumes a finite state machine circuit model with an external view of only primary inputs and outputs. A minimal set of register/latches are created automatically when necessary as implied by the behavioral model. A front-end extracts the circuit's Boolean behavior from the behavioral model using an approach called structure mapping, described in this paper. Logic minimization sub-systems then minimize this Boolean description according to the chosen implementation technology. BECOME extracts and exploits behavioral don't-cares; supports multiple assignments, symbolic states, parallel ( non-procedural ) constructs, and macro facilities using pre-designed logic libraries. Experimental data of models from two modeling languages are presented.
System-Level Power Optimization of Video Codecs on Embedded Cores: A Systematic Approach
Authors: Lode Nachtergaele, Dennis Moolenaar, Bart Vanhoof, Francky Catthoor, Hugo De Man
Venue: Journal of VLSI Signal Processing Systems (1998)

A battery powered multimedia communication device requires a very energy efficient implementation. The required efficiency can only be acquired by careful optimization at all levels of the design. System-level power optimizations have a dramatic impact on the overall power budget. We have proposed a system-level step-wise methodology to reduce the power in hardware realizations of data-dominated applications, which is partly supported with our ATOMIUM environment. In this paper, we extend the methodology to the realization of embedded software on processor cores. Starting from a high level algorithm description (e.g., in C), a set of optimizations gradually refine the code and the corresponding memory organization of the array data types. These array data types represent a fully detailed optimized data storage and transfer organization. Instead of creating the physical memories, a mapping can be done either on a general memory architecture, including a cache, or on a custom memory architecture. First, typical optimizations addressed by our methodology are applied on a didactical example. The effectiveness of this methodology is then demonstrated by the optimization of two complex applications in an embedded processor context: a MPEG2 and a H.263 video decoder. The impact of the power optimizations on the typical power consumption is demonstrated by simulating the optimized decoders with real video streams.
An Algorithm for Total Symmetric OBDD Detection
Authors: Yuke Wang, Mostafa Abd-el-Barr, Carl McCrosky
Venue: IEEE Transactions on Computers (1997)

This paper presents an elegant and efficient algorithm for detection of symmetry in Boolean functions represented by OBDDs.
A Compiler Optimization Algorithm for Shared-Memory Multiprocessors
Authors: Kathryn S. McKinley
Venue: IEEE Transactions on Parallel and Distributed Systems (1998)

This paper presents a new compiler optimization algorithm that parallelizes applications for symmetric, shared-memory multiprocessors. The algorithm considers data locality, parallelism, and the granularity of parallelism. It uses dependence analysis and a simple cache model to drive its optimizations. It also optimizes across procedures by using interprocedural analysis and transformations. We validate the algorithm by hand-applying it to sequential versions of parallel, Fortran programs operating over dense matrices. The programs initially were hand-coded to target a variety of parallel machines using loop parallelism. We ignore the user's parallel loop directives, and use known and implemented dependence and interprocedural analysis to find parallelism. We then apply our new optimization algorithm to the resulting program. We compare the original parallel program to the hand-optimized program, and show that our algorithm improves three programs, matches four programs, and degrades one program in our test suite on a shared-memory, bus-based parallel machine with local caches. This experiment suggests existing dependence and interprocedural array analysis can automatically detect user parallelism, and demonstrates that user parallelized codes often benefit from our compiler optimizations, providing evidence that we need both parallel algorithms and compiler optimizations to effectively utilize parallel machines.
A Note on the Superlinear Convergence of GMRES
Authors: Igor Moret
Venue: SIAM Journal on Numerical Analysis (1997)

In the paper it is shown how the rate of convergence of the GMRES method for solving a linear operator equation $(\lambda I + K) u = f$ in a Hilbert space is related to the degree of compactness of $K$ measured by the products of its singular values.