aaron brennan
Staff IC Design Engineer - Analog / Mixed Signal Design, Methodology Improvement at Cirrus Logic
team oriented innovator | problem solver | mixed-signal ic design engineer | cadence , python , matlab , unix
aaron brennan persistent innovator belief candid , respectful teamwork empowers individual brilliant work . aaron cultivates generation implementation innovative idea augment sustained company growth . experience entire integrated circuit development cycle concept production , aaron creates meaningful solution development high volume mixed-signal ic . orientation system thinking drive analysis problem design solution multiple level abstraction . mixed-signal ic design engineer interest signal processing , analog circuit design , digital design , device physic , aaron utilizes wide breadth tool including python/matlab programming , rf/analog spice simulation , verilog ams/dms simulation , linux scripting . conduct research find elegant solution optimize balance risk performance experience δς adc/dacs , amplifier , afes , bgs , ldos , comparators , hv driver , charge pump , digital filter , state machine rtl , ams/dms modeling verification , chip architecture , esd protection . value team feedback constraint cooperatively uncover right solution design challenge . 𝗦𝘁𝗿𝗲𝗻𝗴𝘁𝗵𝗙𝗶𝗻𝗱𝗲𝗿𝘀 𝗧𝗼𝗽 𝟱 ideation - find connection seemingly disparate phenomenon . strategic - creates alternative way proceed . quickly spot relevant pattern issue . achiever - work hard ha great deal stamen . learner - great desire learn continuously improve . futuristic - inspired future could . inspires others see better future . 𝗔𝗰𝗰𝗼𝗺𝗽𝗹𝗶𝘀𝗵𝗺𝗲𝗻𝘁𝘀 • played key role generating $ 125m+ revenue design manager chip lead • architected first always voice wake input path design manager • initiated improved online project documentation bug tracking infrastructure • communicated directly customer successfully resolve high visibility silicon bug • patent : named inventor 21 patent amis , cypress , cirrus logic
Cirrus Logic
https://www.linkedin.com/company/cirrus-logic
Staff IC Design Engineer - Analog / Mixed Signal Design, Methodology Improvement
Austin, Texas, United States
https://media-exp1.licdn.com/dms/image/C4E0BAQFHOSsCC0RMPQ/company-logo_100_100/0/1603306184390?e=1655942400&v=beta&t=iUMP2AUpv_ctaAHwRT95-9kWmLkTYS-XCrcyzfmktCA
Cirrus Logic
https://www.linkedin.com/company/cirrus-logic
IC Design Engineering Manager - Analog / Mixed Design, Product Development
Austin, Texas, United States
https://media-exp1.licdn.com/dms/image/C4E0BAQFHOSsCC0RMPQ/company-logo_100_100/0/1603306184390?e=1655942400&v=beta&t=iUMP2AUpv_ctaAHwRT95-9kWmLkTYS-XCrcyzfmktCA
Cirrus Logic
https://www.linkedin.com/company/cirrus-logic
Senior IC Design Engineer - Analog / Mixed Signal Design, Chip Lead
Austin, Texas, United States
https://media-exp1.licdn.com/dms/image/C4E0BAQFHOSsCC0RMPQ/company-logo_100_100/0/1603306184390?e=1655942400&v=beta&t=iUMP2AUpv_ctaAHwRT95-9kWmLkTYS-XCrcyzfmktCA
Cypress
https://www.linkedin.com/company/cypress-semiconductor
Principal IC Design Engineer - Analog / Mixed Signal Design, Chip Lead
Moscow, Idaho, United States
https://media-exp1.licdn.com/dms/image/C560BAQFjbezqxbZ9Kw/company-logo_100_100/0/1588109690784?e=1655942400&v=beta&t=gCTYVHOsq-x3oWT6xJDcW8SmDaj6svlEO8P5D1w9EEA
Cypress
https://www.linkedin.com/company/cypress-semiconductor
Senior Staff IC Design Engineer - Analog / Mixed Signal Design, Unix Sysadmin
Moscow, Idaho, United States
https://media-exp1.licdn.com/dms/image/C560BAQFjbezqxbZ9Kw/company-logo_100_100/0/1588109690784?e=1655942400&v=beta&t=gCTYVHOsq-x3oWT6xJDcW8SmDaj6svlEO8P5D1w9EEA
AMIS
https://www.linkedin.com/company/onsemi
IC Design Engineer - Analog / Mixed Signal, Unix Sysadmin
Moscow, Idaho, United States
https://media-exp1.licdn.com/dms/image/C560BAQFi30eQoynqxw/company-logo_100_100/0/1628089032445?e=1655942400&v=beta&t=KO1b1ZrrgvsTcVnQszTnS7DmucrZsDODBe0PjZEe8p4
AHA Products Group
https://www.linkedin.com/company/aha-products-group-comtech-efdata-corp
IC Design Engineer
Pullman, Washington, United States
https://media-exp1.licdn.com/dms/image/C4E0BAQHDNtQMM_Qgbw/company-logo_100_100/0/1628692418966?e=1655942400&v=beta&t=JNfKbjOtGgWioaDbyC4P_W_psBSreWLdjp8cPvhevqQ
MSEE
University of Idaho
https://www.linkedin.com/school/university-of-idaho/
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BSEE
University of Idaho
https://www.linkedin.com/school/university-of-idaho/
https://media-exp1.licdn.com/dms/image/C4D0BAQFKi3yEauRBjA/company-logo_100_100/0/1625153733606?e=1655942400&v=beta&t=-JyAAIm-43lwYsxEjacjSUTtPvy3t7OhfJ3GUhYu8Ow
IEEE
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Systems and methods for dynamic range enhancement using an open-loop modulator in parallel with a closed-loop modulator
United States
An integrated circuit may have two signal paths: an open-loop modulator (which may comprise a digital-input Class-D amplifier) and a closed-loop modulator (which may comprise an analog-input Class-D amplifier). A control subsystem may be capable of selecting either of the open-loop modulator or the closed-loop modulator as a selected path based on one or more characteristics (e.g., signal magnitude) of an input audio signal. For example, for higher-magnitude signals, the closed-loop modulator may be selected while the open-loop modulator may be selected for lower-magnitude signals. In some instances, when the open-loop modulator is selected as the selected path, the closed-loop modulator may power off, which may reduce power consumption. In addition, one or more techniques may be applied to reduce or eliminate user-perceptible audio artifacts caused by switching between the open-loop modulator and the closed-loop modulator, and vice versa.
10720888
10720888
https://patents.google.com/patent/US10720888B2/en
Charge pump input current limiter
United States
A system may include a charge pump configured to operate in a plurality of modes including a first mode in which the ratio of an output voltage to an input voltage of the charge pump is a first ratio and a second mode in which the ratio is a second ratio and a controller configured to limit current flowing between a power source of the charge pump to the charge pump, wherein the power source provides the input voltage, by limiting a transfer of charge between the power source and the charge pump during a switching cycle of the charge pump responsive to a change in operation between modes of the plurality of modes.
10581322
10581322
https://patents.google.com/patent/US10581322B2/en
Combined boost converter and power converter
United States
In accordance with embodiments of the present disclosure, a system may include a series combination of a boost converter and a power converter coupled together in series, such that the series combination boosts an input voltage to the series combination to an output voltage greater than the input voltage such that a voltage boost provided by the series combination is greater than a voltage boost provided by the boost converter alone. The system may also include an amplifier, wherein an input of the amplifier is coupled to an output of the series combination of the boost converter and the power converter.
10284090
10284090
https://patents.google.com/patent/US10284090B2/en
Variable ratio charge pump with peak current and average current limiting circuitry
United States
A method of increasing a multiplication ratio of a charge pump, the multiplication ratio defining a relationship between an output voltage of the charge pump and an input voltage of the charge pump, comprising: analyzing a first efficiency of the charge pump when the multiplication ratio is at a first ratio, calculating a second efficiency of the charge pump when the multiplication ratio is a second ratio lesser than the first ratio, and based on the first efficiency and the second efficiency, determining at least one of a target output power and a target output voltage at which to change the multiplication ratio from the second ratio to the first ratio.
10114392
10114392
https://patents.google.com/patent/US10114392B2/en
Transconductance with capacitances feedback compensation amplifier
United States
In accordance with embodiments of the present disclosure, a transconductance with capacitances feedback compensation amplifier may include a capacitor in parallel with an inner feedback loop of the amplifier for providing cascade compensation to the amplifier.
9941848
9941848
https://patents.google.com/patent/US9941848B1/en
Analog-to-digital converter (ADC) dynamic range enhancement for voice-activated systems
United States
The dynamic range and power efficiency of a voice-activated system may be improved by dynamically adjusting the configuration of the voice-activated system's input path. In one embodiment, a first portion of audio may be received through an input path of the voice-activated system having a first configuration. A characteristic of the first portion of audio may be determined and the input path may be adjusted to a second configuration based on the determined characteristic. A second portion of audio may then be received through the input path having the second configuration, and speech analysis may be performed on the second portion of audio.
9799349
9799349
https://patents.google.com/patent/US9799349B2/en
Phase shorting switch
United States
An analog-to-digital converter (ADC) may include capability to sense and/or compensate for undesired effects when receiving input from a microphone. For example, a sense node may be provided between differential inputs, and that sense node separated from the differential inputs by two or more switches. The sense node may allow for a measurement of an average voltage of the differential inputs. The average voltage may be obtained activating the switches to sample the sampling capacitors coupled to the differential inputs. That average voltage may be used as common mode (CM) data. A controller may receive the CM data, along with differential mode (DM) data, and use the CM and DM data to determine undesired effects, such as DC or AC mismatch at the microphone interface. The controller may then generate a signal for applying compensation to the differential inputs to reduce or eliminate the undesired effects.
9762257
9762257
https://patents.google.com/patent/US9762257B2/en
Dual processing paths for differential mode and common mode signals for an adaptable analog-to-digital converter (ADC) topology
United States
One method of processing microphone input in an ADC to determine microphone configuration is to process the microphone input signals in two processing paths, in which one processing path processes a difference between differential input signals and another processing path processes an average value of the differential input signals. The outputs of these processing paths may be combined to generate a digital signal representative of the analog signal from the microphone. The digital signal contains a digital version of the audio in the environment around the microphone, but may also be used to detect microphone topology and configure aspects of the processing paths to match the detected microphone topology. An apparatus for an ADC may implement the two processing paths as two delta-sigma modulator loops.
9729164
9729164
https://patents.google.com/patent/US9729164B2/en
Random telegraph signal identification and measurement
United States
In accordance with embodiments of the present disclosure, a method for identifying a location of an integrated circuit that is sensitive to RTS noise may include applying localized heat to a scan area of the integrated circuit, observing any change in one or more electrical parameters of the integrated circuit in response to the localized heat being applied to the scan area indicative of sensitivity to RTS noise, and identifying the location sensitive to RTS noise responsive to observing change in one or more electrical parameters of the integrated circuit indicative of sensitivity to RTS noise in response to the localized heat being applied to the scan area.
9723578
9723578
https://patents.google.com/patent/US9723578B2/en
Non-linearity cancellation in a dual-path ADC
United States
The overall performance of a dual-path ADC system may be improved by using a VCO-based ADC for small-amplitude signals and employing non-linear cancelation to remove nonlinearities in signals output by the VCO-based ADC. In particular, VCO-based dual-path ADC systems of this disclosure may be configured to receive a first digital signal from a first ADC and a second digital signal from a second ADC, wherein the second digital signal is more non-linear than the first digital signal. The dual-path systems may also be configured to determine one or more non-linear coefficients of the second digital signal based, at least in part, on processing of the first and second digital signals. The dual-path systems may be further configured to modify the second digital signal based, at least in part, on the determined one or more non-linear coefficients to generate a more linear second digital signal.
9722620
9722620
https://patents.google.com/patent/US9722620B1/en
Headphone responsive to optical signaling
United States
An optical sensor may be integrated into headphones and feedback from the sensor used to adjust an audio output from the headphones. For example, an emergency vehicle traffic preemption signal may be detected by the optical sensor. Optical signals may be processed in a pattern discriminator, which may be integrated with an audio controller integrated circuit (IC). When the signal is detected, the playback of music through the headphones may be muted and/or a noise cancellation function turned off. The optical sensor may be integrated in a music player, a smart phone, a tablet, a cord-mounted module, or the earpieces of the headphones.
9609416
9609416
https://patents.google.com/patent/US9609416B2/en
Ring frequency divider
United States
A circuit for a divider or counter may include a frequency divider having multiple rings for dividing an input frequency to obtain an output frequency. The first and second rings may include an odd-numbered plurality of elements, such as inverters, wherein each inverter of a ring is coupled to another inverter of the ring in a circular chain. An input frequency may be input to a power supply input of inverters of the first ring. The second ring inverters may be coupled at a power supply input to output nodes of the first ring inverters, which results in the second ring operating at a divisional rate of the first frequency given by (N−1), where N is the number of inverters in the ring. The circuits may be used in frequency dividers and counters, such as in phase-locked loops (PLLs) and analog-to-digital converters (ADCs).
9595971
9595971
https://patents.google.com/patent/US9595971B2/en
Voltage-controlled oscillator (VCO) as first stage in an analog-to-digital converter (ADC) in combination with a digital filter for second or higher-order noise shaping
United States
A delta-sigma modulation analog-to-digital converter (ADC) may be constructed by combining a VCO used for a first order filter with a digital loop filter used for a second or higher order of the ADC. One such ADC would include an analog input node configured to receive an analog signal; a voltage-controlled oscillator (VCO) comprising a first input configured to receive the analog signal, wherein the voltage-controlled oscillator is configured to implement a first order noise-shaping function; a digital loop filter comprising a second input configured to receive an output of the voltage-controlled oscillator (VCO); and a digital output node configured to output a digital signal based on an output of the digital loop filter. The digital loop filter may be configured to implement at least a first order noise-shaping function, but may also implement higher order noise-shaping functions.
9397692
9397692
https://patents.google.com/patent/US9397692B1/en
Reducing kickback current to power supply during charge pump mode transitions
United States
Kickback current from a charge pump to a power management integrated circuit (PMIC) may be reduced by dissipating charge from fly and hold capacitors during mode transitions. A switch may be placed in series between the charge pump and the PMIC to disconnect the charge pump and prevent kickback current from reaching the PMIC. Further, additional loads, as switches, may be coupled to the charge pump outputs to dissipate charge from the fly and hold capacitors. Additionally, a closed feedback loop may be used to monitor and discharge excess charge from the fly and hold capacitors during mode transitions. Furthermore, charge may be redistributed between the fly and hold capacitors during mode transitions to reduce the time period of the transition.
9293986
9293986
https://patents.google.com/patent/US9293986B2/en
Poly-phase frequency synthesis oscillator
United States
A frequency synthesis/multiplication circuit and method for multiplying the frequency of a reference signal. In one embodiment, multiple versions of the reference signal are generated having different phases relative to one another, and these multiple versions are combined to form an output signal having a frequency that is a multiple of the frequency of the reference signal.
8085100
8085100
https://patents.google.com/patent/US8085100B2/en
Oscillator circuit
United States
Described is a circuit comprising an oscillator, an amplifier unit and a control unit. The amplifier unit is coupled to the oscillator and to the control unit; and the control unit is arranged to regulate a load capacitance to the oscillator at startup.
7902933
7902933
https://patents.google.com/patent/US7902933B1/en
Regulated capacitive loading and gain control of a crystal oscillator during startup and steady state operation
United States
An oscillator circuit and system are provided having a peak detector that can determine a peak voltage value from the oscillator. The peak voltage value can then be compared against a predetermined voltage value by a controller coupled to the peak detector. The comparison value is then used to change a bias signal if the peak voltage value is dissimilar from the predetermined voltage value. A variable capacitor or varactor can be formed from a transistor and is coupled to the oscillator for receiving the bias signal upon a varactor bias node. The bias signal is used to regulate the capacitance within the varactor as applied to the oscillator nodes. Another controller can also be coupled to the peak detector to produce a second bias signal if the peak voltage is dissimilar from a second predetermined voltage value. The second bias signal can then be forwarded into an amplifier having a variable gain to regulate the gain applied to the oscillator. The combination of a varactor and variable gain amplifier regulate the negative resistance applied to the resonating circuit during startup and steady state operations to ensure a relatively fast startup, and to maintain optimal loading and accurate steady state amplitude after startup has completed.
7859355
7859355
https://patents.google.com/patent/US7859355B2/en
Nonvolatile programmable crystal oscillator circuit
United States
According to embodiments of the invention, a nonvolatile memory such as a flash memory is used to configure a single die after packaging of the die has occurred. Thus, numerous applications may be supported by a single die or optimization within a given application may occur. According to embodiments of the invention, the nonvolatile memory may be accessed through a programming interface, and preferably, through a two-pin programming interface, to normalize parameters such as package parasitics, crystal variations, output dividers, output duty cycle, output edge rates, I/O configuration, and oscillator gain. According to an embodiment of the invention, an XO circuit configuration includes a nonvolatile memory and a stand-alone XO, where the XO circuit configuration does not require a PLL to synthesize a reference frequency produced by the XO.
7221233
7221233
https://patents.google.com/patent/US7221233B2/en
Oscillator amplifier circuit operable to provide symmetric current limiting and method of same
United States
An amplifier circuit operable to provide symmetric current limiting. The amplifier circuit includes a common source amplifier for sourcing a current and receiving an voltage input, a current source, and a current limiting device coupled between the common source amplifier and the current source. The current limiting device is operable to limit the current sourced by the common source amplifier. A bias network coupled to the current limiting device biases the current limiting device. An output is coupled to the current limiting device. The amount of current that is sourced to the output of the amplifier circuit may be limited, such that current limiting is symmetrical.
7196586
7196586
https://patents.google.com/patent/US7196586B1/en
Regulated, symmetrical crystal oscillator circuit and method
United States
An oscillator circuit is provided that is preferably a crystal oscillator, where voltage placed across the crystal is regulated. The regulated voltage or amplitude of the cyclical signal across the crystal is monitored and maintained through a regulation circuit that measures a peak voltage across the crystal. Once the peak voltage exceeds a predetermined setpoint value, then a controller within the regulation circuit will reduce a biasing current through an amplifying transistor within the amplifier coupled across the crystal input and output nodes. By regulating the biasing current, gain from the amplifier is also regulated so that unwanted non-linearities and harmonic distortion is not induced within the crystal to cause frequency distortion and unwanted modes of oscillation within the crystal. The amplifier is preferably symmetrical in that the amplifier sources and sinks equal current to reduce unwanted peaks at the negative or positive half cycles of the sinusoidal signal.
7123113
7123113
https://patents.google.com/patent/US7196586B1/en
Runtime programmable Reed-Solomon decoder
United States
A runtime programable RS decoder that can operate on multiple pieces of data during one clock cycle in order to generate, reduce, and evaluate polynomials involved in the decoding of an RS code, and which allows a user to choose the RS code after the circuit has been implemented.
6704901
6704901
https://patents.google.com/patent/US6704901B1/en
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        I had the pleasure of working with Aaron  over a five year period. Aaron passionately combined his exceptional technical expertise and design methodology proposals in practice, resulting in great strides towards alignment of Austin and Edinburgh development sites at Cirrus Logic. 

He invests time in developing great working relationships, for every person he works with and is very good at stakeholder management. His greatest assets are ability to think beyond today's problems and ability to adjust to needs of a team or organisation. 

The sharp technical mind, visionary outlook and growth mindset are what makes Aaron great. Pleasure to have worked with him and grateful for all the knowledge he shared so selflessly over the years.  Galen Stansell
      
          



            
              
        
              
  

    
        This is the guy you want on your team - I don't care what the nature of the problem is.  He is adaptable, he finds a way, he delivers with an innovative solution.  I am hesitant to categorize him - he can be a top notch analog designer or digital designer - whatever is required to deliver a world class solution.  Was privileged to work with him at Cypress and know he will have the same impact at whatever place is lucky enough to have him further his career at.
Aaron Brennan
https://www.linkedin.com/in/aaron-brennan
Member Board Of Trustees at San Diego French-American School
San Diego County, CA
Aaron Brennan
https://uk.linkedin.com/in/aaron-brennan-839928141
Head of Web and Mobile - Germany
City of London
Aaron Brennan
https://uk.linkedin.com/in/aaron-brennan-443438222
Finished Vehicle Logistics Engineer
Sunderland
Aaron Brennan
https://www.linkedin.com/in/aaron-brennan-963b8148
AVP/Recruiting Manager at Robert Half  202-626-0280  aaron.brennan@roberthalf.com
Washington, DC
Aaron Brennan
https://ie.linkedin.com/in/brennanaaron
Director of IT Operations at Genuity Science
Ireland