Aaditya Chaudhary
Design Engineer 2 at Ampere
Design Engineer 2 at Ampere Computing
-> Graduate student at North Carolina State University majoring in Computer Engineering with                                                                                specialization in ASIC / SoC / FPGA / RTL / CPU design/verification and CPU / GPU Architecture

-> TECHNICAL SKILL:
Verilog, System Verilog ( UVM / OVM ), C++, C, Python, Embedded C, CUDA, OpenCL

-> TOOLS/ENVIRONMENT:
Synopsys Design Compiler, Mentor Graphics Questasim / ModelSim, Xilinx Vivado, Xilinx ISE and LATEX

-> HARDWARE INTERFACING:
Virtex 6 FPGA, Spartan 3AN FPGA, Artix-7 FPGA, Zynq Z7010 SoC, Raspberry pi 3, MSP430, MSP 432, GPGPUsim

-> OPERATING SYSTEM:
Windows - 98 / XP / 7 / 8 / 10
Linux - Ubuntu / Manjaro / CentOS / Raspbian

-> GRADUATE COURSES:
ECE 564 - ASIC and FPGA design
ECE 506 - Architecture of Parallel Computers
ECE 563 - Microprocessor Architecture
ECE 745 - ASIC Verification
ECE 748 - Advanced Functional Verification with UVM
ECE 786 - Advanced Computer Architecture: Data Parallel Processors (GPU Architecture)
ECE 542 - Neural Networks
UDEMY - Learn to build OVM & UVM Testbenches from scratch, SOC Verification using SystemVerilog

-> PROJECTS:
1) Verification of I2C multiple bus controller
2) Functional Verification of LC3 Controller using UVM Framework
3) Convolution Neural Network - ASIC Implementation of LSTM Cell
4) Light runtime system for OpenCL on FPGA and GPU, providing configurable scheduling
5) MIPS-like 5-Stage Pipeline Processor Simulator
6) L1 and L2 Cache Simulator
7) Bus Based Cache Coherence Simulator
8) 2-D Convolution with Tiling and Coarsening
9) Radix Sort in OpenMP

Please contact me at achaudh9@ncsu.edu to find out how I might contribute and add value to your organization.
Ampere
https://www.linkedin.com/company/amperecomp
Design Engineer 2
Portland, Oregon, United States
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North Carolina State University
https://www.linkedin.com/company/north-carolina-state-university
Graduate Student Researcher
NPS Lab (Dr. Michela Becchi):
Designed a light runtime system for OpenCL applications running on FPGA and GPU, providing configurable scheduling mechanisms.
Raleigh, North Carolina, United States
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North Carolina State University
https://www.linkedin.com/company/north-carolina-state-university
Graduate Teaching Assistant
MBA555 - Product Design and Development
Raleigh, North Carolina, United States
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Indian Institute of Management Bangalore
https://www.linkedin.com/company/indian-institute-of-management-bangalore
Incubatee
Bangalore, India
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Soil
Co-Founder
Bengaluru Area, India
Indian Institute of Technology, Kanpur
https://www.linkedin.com/company/indian-institute-of-technology-kanpur
Winter Research Intern
Hardware-software coprocessor design: Designed Co-processor using AXI bus interface and custom IP cores. Implemented AXI Uartlite, AXI Timer, Block Ram and System Cache IPs.
Kanpur Area, India
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Bhabha Atomic Research Centre
https://www.linkedin.com/company/bhabha-atomic-research-centre
Summer Research Intern
Evaluated an AES module implemented on FPGA and compared its correctness and performance with OpenSSL cryptographic library on linux platform. It involved the study and development of test benches and host interface modules using a python based hardware description language(MYHDL) and an in-house developed FHPClib framework.
Mumbai Area, India
Telcoma Technologies
https://www.linkedin.com/company/telcoma-technologies
Summer Intern
During this internship, I did RF survey, 2G ARFCN planning for Mohali(using MCOM software and Ericsson engineering tool), 3G planning for Mohali, 4G backbone planning(TEMS 17.x software used for drive testing and network optimization) and 4G network simulation(using Cisco Packet Tracer software).
Chandigarh Area, India
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Robosapiens Technologies(P) Ltd.
Trainee
In this training, I learned the basic image processing tools in MATLAB, color detection technique, Object tracking and the GUIDE tool.
Noida Area, India
Computer Engineering
Master of Science - MS
North Carolina State University
https://www.linkedin.com/school/north-carolina-state-university/
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Electronics and Telecommunication Engineering
Bachelor of Technology (B.Tech.)
National Institute of Technology Raipur
https://www.linkedin.com/school/national-institute-of-technology-raipur/
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D.A.V Public School Bilaspur
Click Club
Head Coordinator
It was the photography club of NIT Raipur.
Unnat Bharat Abhiyan
Committee member
Electronics Engineering Association (ASSETS)
Committee member
It was NIT Raipur's official committee for electronics enthusiasts.
Winner of Texas Instrument Innovation Challenge - India Design Contest 2016
Texas Instruments
Among top 10 winners of Texas Instruments Inc. India Innovation Challenge Design Contest 2016 with over 11000 participants from 624 colleges of India. Got incubation for 1 year at IIM Bangalore and a funding of INR2500000/- from Texas Instruments, IIM Banglore and DST for this project.
ASIC Verification
ECE 745
ASIC and FPGA Design
ECE 564
Advanced Computer Architecture - Data Parallel Processors (GPGPU)
ECE 786
Advanced Verification with UVM
ECE 748
Architecture of Parallel Computers
ECE 506
Microprocessor Architecture
ECE 563
Neural Networks
ECE 542
Strategy Management
BUS 501
Light Runtime for OpenCL applications on FPGA and GPU
Designed a light runtime system for OpenCL applications running on FPGA and GPU, providing configurable scheduling mechanisms.
Musical Notes Generation with FPGA
Generated discrete frequencies pertaining to 64 musical notes over 5 octaves using a binary counter to toggle a GPIO pin connected to a speaker.
Functional Verification of LC3 Controller using UVM Framework
Developed a vertically and horizontally reusable layered testbench to verify block to chip level functionality. Functional coverage was achieved using a regression of directed and random testing with different seeds. Block level as well as propagated bugs were found by the predictor-scoreboard functionality. The simulation was speeded up by making the testbench emulatable and running it on an veloce emulator.
Verification of I2C multiple bus controller
Constructed a layered test bench using System Verilog to verify I2C and Wishbone protocol functionality of the DUT. Implemented verification plan, test with constrained randomization, generator, env_configuration, environment, predictor, scoreboard, coverage and Agent(Driver + Monitor). Analyzed functional coverage for closing holes.
2-D Convolution using CUDA
kernel function with parallelized 2-D convolution algorithm tested on NVIDIA GT740M. Benchmarked the performance with different grid and block size.
Bus Based Cache Coherence Protocol Simulator
Implemented a bus-based cache coherent simulator supporting 4 protocols - MSI, MESI, MOSI and MOESI and analyzed performance for varying cache configurations and protocols.
Convolution Neural Network - ASIC implementation of LSTM Cell
LSTM cell is used in convolution neural networks. Fetched data from SRAM and performed mathematical operations - matrix multiplication, addition and truncation. Optimized the design by adding pipelines to it. Performance: Area - 7243 um2 and Clock Period -9.1 ns.
MIPS-like 5-Stage Pipeline Processor Simulator
Data path and control path with support for integer and floating point unit. Handled
Structural, control and data hazards.
L1 and L2 Cache Simulator
Deployed a two-level cache hierarchy exhibiting LRU and LFU policies with
write-back and write-allocate.
Radix Sort in openMP
Parallelized the radix sort algorithm with openMP and compared its performance with non-parallel radix sort algorithm.
Design and Simulation of a router on FPGA
A 3x3 non-blocking virtual cut-through switching router has been designed and simulated on Xilinx Vivado.
Web crawlers for newspaper agency
It was part of a freelancing project. In this project, I used the beautiful soup and scrapy library of python to scrape text from various national newspaper websites and save it in a database, which was used by the local newspaper agency to get its content automatically.
https://github.com/adi-007/webCrawler
Design and Simulation of Physical Layer Blocks of ZigBee Transmitter
In this project, we have developed an architectural design of the Zigbee Transmitter through Verilog HDL. As the transmitter is an integration of various blocks, so each block has been individually simulated. The architecture has been simulated using post route simulations.
Pick & Place robot
Detects the correct box using RFID and pick and place it at the desired location. Locomotion of vehicle is controlled using an android application which uses Bluetooth as a means of communication. The purpose of this project is automation of industry.
Wireless USB Data Transfer Module using Raspberry pi 3
The basic idea of the project was to create a single battery powered WIFI module of the size of our fist which would transfer data from normal USB stick to any WIFI enabled device and act as a data sharing hub. This device can also be configured for sharing wireless Internet connection.
https://github.com/adi-007/Wireless-USB-transfer-module
Automatic door bell and light system
It’s a basic project using 555 timer IC and IR sensor. The 555 IC is used in bistable
mode so whenever the voltage drops at the trigger pin(which is connected to IR
sensors), the output becomes high and a musical bell starts.
Education
Unnat Bharat Abhiyan, NIT Raipur
Teacher
Unnat Bharat Abhiyan is inspired by the vision of transformational change in rural development processes by leveraging technical institutions to help build the architecture of an inclusive India. Under this organization, I used to visit Guma village to teach Mathematics and English to higher secondary students in a government school.
ASIC Design Project - Summer Camp (2020)
North Carolina State University
http://www.linkedin.com/learning/programming-foundations-data-structures-2
Programming Foundations: Data Structures
www.linkedin.com
LinkedIn
https://www.udemy.com/certificate/UC-9437c10e-9cb4-414e-8b19-7907047ea68c/
Learn to build OVM & UVM Testbenches from scratch
UC-9437c10e-9cb4-414e-8b19-7907047ea68c
www.udemy.com
Udemy
https://www.udemy.com/certificate/UC-e89f182f-d89f-4b68-805f-9b655abaae64/
SOC Verification using SystemVerilog
UC-e89f182f-d89f-4b68-805f-9b655abaae64
www.udemy.com
Udemy
https://www.qwiklabs.com/public_profiles/71af4ab2-9096-45fe-af2a-80b1e65ce6cd
Compute and Networking
www.qwiklabs.com
Amazon Web Services (AWS)
https://www.coursera.org/account/accomplishments/verify/2J2VXPMR3E7L
The Raspberry Pi Platform and Python Programming for the Raspberry Pi
2J2VXPMR3E7L
www.coursera.org
Coursera Course Certificates
https://www.udemy.com/certificate/UC-0V2FEK8U/
Automate the Boring Stuff with Python Programming
UC-0V2FEK8U
www.udemy.com
Udemy
https://www.udemy.com/certificate/UC-X2PVKQ1L/
Github introduction to version control and remote files
UC-X2PVKQ1L
www.udemy.com
Udemy
https://www.udemy.com/certificate/UC-AGYCPX2V/
Mastering Microcontroller with Embedded Driver Development
UC-AGYCPX2V
www.udemy.com
Udemy
https://www.linkedin.com/in/pranav-bhave
Pranav Bhave
Architectural Design Verification Engineer at Ampere Computing
Sunnyvale, CA
https://www.linkedin.com/in/aravind-sampathkumar
Aravind Sampathkumar
CPU Verification Engineer at Ampere
Raleigh, NC
https://www.linkedin.com/in/shrihari-sundararaj-407704145
Shrihari Sundararaj
Silicon Design Engineer 2 at AMD
Austin, TX
https://www.linkedin.com/in/akshata-maltare
Akshata Maltare
CPU Verification Engineer at Ampere
Portland, OR
https://www.linkedin.com/in/girish-george-46884051
Girish George
Senior CPU Verification Engineer at Nvidia
San Jose, CA
https://www.linkedin.com/in/ankith-muralidhar
Ankith Muralidhar
Silicon Design Engineer 2 at AMD
Orlando, FL
https://www.linkedin.com/in/chaitrali-joshi-539ab742
Chaitrali Joshi
Emulation Engineer at Ampere
Santa Clara, CA
https://www.linkedin.com/in/mysorena
Praveen Mysore
Physical Design Engineer at Ampere
Santa Clara, CA
https://www.linkedin.com/in/anjanapadmanabhan98
Anjana Padmanabhan
Masters Student at NCSU Computer Engineering| Looking for full time opportunities in digital VLSI and Comp Arch.
Raleigh, NC
https://www.linkedin.com/in/jharupesh
Rupesh Jha
Graduate Student at Portland State University | Physical Design Intern at Ampere Computing
Portland, OR
https://www.linkedin.com/in/noufalputhukkudi
Noufal Puthukkudi
RTL Design Engineer at Amazon
Austin, TX
https://www.linkedin.com/in/atharva-dole
Atharva Dole
Actively seeking Co-op/Internship in Digital Design/Verification
Portland, OR
https://www.linkedin.com/in/sriram-sundararaj-93a84a12b
Sriram Sundararaj
Silicon Design Engineer 2 at AMD
Raleigh, NC
https://www.linkedin.com/in/rsindhu
Sindhu Ramamurthy
Design Verification Engineer at Cirrus Logic
Austin, TX
https://www.linkedin.com/in/madhuranadgouda
Madhura Nadgouda
Design Engineer at Analog Devices
United States
https://www.linkedin.com/in/hari-priya-vankineni-2ba963bb
Hari Priya Vankineni
CPU Design Engineer at Intel Corporation
Austin, TX
https://www.linkedin.com/in/suresh-natarajan-a5756abb
Suresh Natarajan
CPU Design Verification Engineer at AMD
San Francisco Bay Area
https://www.linkedin.com/in/mandar-nevpurkar-415b6363
Mandar Nevpurkar
Design Verification Engineer at Apple
San Francisco Bay Area
Sathish Pathakota
      
          



            
              
        
              
  

    
        I was a business mentor for a startup co-founded by Aaditya at IIMB NSRCEL, Bangalore and had regular interactions with him in formal and informal settings. In addition to his technical prowess, Aaditya attitude and behavior impressed the most. He was always positive, smiling and took any feedback well. I would hire Aaditya without any hesitation based on his technical and personal skills and behavior. I am positive that he will succeed in any venture or activity he is involved in. I wish him the best . Dr. Shubhankar Majumdar
      
          



            
              
        
              
  

    
        Aaditya worked under me for more than a year, during which I was impressed by his verilog & python programming skills and his ability to quickly grab new concepts. His commitment to the project was highly appreciable, and the significant contribution he gave to meet the objectives even when they were over the team capacity made the success of the whole team happen. Despite the high pressure, he consistently delivered top quality work and always used to pick the most challenging tasks. Also, it's worth mentioning that he was considered as a reference by other project mates. Thus, I would be delighted to recommend him to anybody.
A journey towards Data Science started in Dec-2021 and in between, have successfully completed 7-week Python and SQL programming Bootcamp by…
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AadiTya ChauDhary
https://in.linkedin.com/in/aaditya-chaudhary-b63722108
Owner at THE NEXT CERAMIC HOUSE
Gujarat, India
Aaditya Chaudhary
https://in.linkedin.com/in/aaditya-chaudhary-862a5a98
Senior Engineer at Montecarlo Limited
Ahmedabad
Aaditya Chaudhary
https://ca.linkedin.com/in/aaditya-chaudhary-a79134187
Cloud Software Infrastructure Intern At Nvidia
Greater Toronto Area, Canada
Aaditya Chaudhary
https://in.linkedin.com/in/aaditya-chaudhary-18770a21
Manager HR at Bajaj Consumer Care
Mumbai
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RTL Verification Professionals
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College Grad Recruiting
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ASIC & FPGA Experts Group
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Microsoft University Recruiting Team
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FPGA — Design and Programmable Devices
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UVM Verification Professionals Group
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Semiconductor Professional's Group
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Exascale Computing
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ASIC and FPGA Design and Verification Contract  Openings
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RTL to GDSII
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OpenACC Developers
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Verification Academy
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Student Conferences, Opportunities & Connections
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Entry Level Jobs and Internships: College Recruiter
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