aakanksha patil
GPU Compiler Engineer at AMD
gpu compiler engineer amd
AMD
https://www.linkedin.com/company/amd
GPU Compiler Engineer
Greater Boston Area
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CycleSCP
Embedded Systems Intern
San Francisco Bay Area
KPMG India
https://www.linkedin.com/company/kpmgindia
Associate Consultant
Mumbai Area, India
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KPMG
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Forensic Analyst
Mumbai Area, India
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Electrical and Computer Engineering (Computer Engineering)
Master’s Degree
North Carolina State University
https://www.linkedin.com/school/north-carolina-state-university/
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Electronics Engineering
Bachelor’s Degree
Sardar Patel Institute Of Technology
ASIC Design
ECE 564
Advanced Computer Architecture
ECE 786
Architecture of Parallel Computers
ECE 506
Code Generation and Optimization
ECE 566
Computer Design and Technology
ECE 521
Embedded System Architecture
ECE 560
Embedded System Design
ECE 561
Internet Protocols
ECE 573
Operating Systems
ECE 592
Python in Engineering
ECE 592
Design of 2-layer Convolutional Neural Network ASIC
Designed an ASIC to compute 2-layer Convolutional Neural Network in hardware to achieve maximum performance per unit area. Implemented the design in Verilog HDL, simulated the hardware using ModelSim and synthesized using Synopsys Design Vision to achieve a performance of 4.636×109 results per second per um2.
Digital Control for lighting
Explored different control techniques such as bang-bang, proportional and PID control for a buck converter driving a high brightness LED to find the ideal CPU load and responsiveness. Optimizations to eliminate ADC busy waiting and boosting the control loop and switching frequencies results in average CPU utilization of about 85%.
Implementation of virtual memory management and demand paging in Xinu
Added Virtual Memory and demand paging support to the x86 based Xinu OS. 
This involved studying the x86 virtual memory system documentation and adding support to the existing codebase for a two-level page table with LRU based demand paging. 
In addition, virtual memory management functions (malloc/free) were implemented. Finally, a series of simple microbenchmarks were devised to test the newly added virtual memory system and memory management.
Implementation of synchronization mechanisms and scheduling algorithms in Xinu
Implemented Shortest Time-to-Completion First and Multi-Level Feedback Queue scheduling policies in Xinu and verified their correct operation with representative test cases. 
Augmented various lock primitives in Xinu and added support for deadlock detection and prevention of deadlocks. 
Also, implemented Priority Inheritance Protocol to avoid the problem of Priority Inversion.
Alternative Thread Block Scheduling for improved GPGPU Resource Utilization
Implemented alternative thread block scheduling techniques like LCA (Lazy CTA scheduling) by leveraging a greedy warp scheduler and BCS (Block CTA scheduling) by assigning consecutive thread blocks to the same core on GPGPU-Sim and achieved maximized resource utilization and improved overall performance.
Peer-to-Peer with Centralized Index (P2P-CI) System for Downloading RFCs
Built a P2P-CI system in which peers who wish to download an RFC that they do not have in their hard drive download it from another active peer who does. 
All communication among peers or between a peer and the server is over TCP.
Latency optimization for Real Time Systems
Worked on optimizing an embedded I2C driver running on Cortex-M0+ by implementing interrupt handling to decrease the turnaround time for processing the I2C payload. 
Further optimizations were implemented by taking advantage of the thread features of CMSIS-RTOS RTX to make about 81.55% of the total time available as idle time during I2C message transmission.
Code Optimization using LLVM IR
Implemented different scalar code optimization strategies using LLVM. 
Wrote the following Optimization Passes:
-CSE (Common Sub-Expression Elimination)
-LICM (Loop Invariant Code Motion)
-SLP (Superword Level Parallelism)
Dynamic Instruction Scheduling for an Out-of-order Superscalar Processor
Developed a trace based simulator for a 9 stage out-of-order 4-way (configurable) superscalar CPU pipeline for a simple ISA.
This included a Reorder buffer, Instruction Queue (Reservation Station) and full renaming support for dynamic instruction scheduling.
 A simple hardware prefetching mechanism and different types of branch predictors were also modeled.
Language Used: C++
Branch Predictor Simulator
•Modeled a Branch Predictor Simulator and used it to calculate the branch misprediction rate for different Branch Predictors
•Branch Predictors: Bimodal, Gshare, Hybrid, Yeh/Patt
•A set associative Branch Target Buffer (BTB) 
•Language used: C++
Cache Coherence Protocol Simulator
Designed a trace driven simulator to model MSI, MOSI and MOESI coherence protocols with both bus based and directory based implementations.
Cache Hierarchy Design Simulator
•Implemented a cache hierarchy simulator to estimate the cache miss rates for different cache configurations when running different workloads.
•The multilevel Cache Simulator could be used with a combination of different replacement policies and inclusion policies as given below:
•Replacement policies: LRU, FIFO, Pseudo LRU
•Inclusion policies: Inclusive, Exclusive, NINE
•Language used: C++
LLVM Bit Code Generator for a Subset of the C language
Programmed an LLVM Bit Code Generator for features of the C language.
Defined tokens using Flex as the parser generator. 
Implemented support for if-then-else, while, for loop and expression statements.
Wireless Transmission and Online Monitoring of Patient Vitals
Prototyped a portable device to sense patient vitals (heart rate and temperature) using real time controls on ATMega64. 
Wirelessly transmitted this data using RF transceivers and uploaded to a webpage. 
In case of an emergent situation, the patient’s doctor and emergency contacts were alerted via an email and SMS notifications.
https://ca.linkedin.com/in/cgmillette
Chris Millette
MTS Software Development Engineer at AMD
Calgary, AB
https://www.linkedin.com/in/alexander-freij
Alexander Freij
PhD Candidate at NC State University
Raleigh, NC
https://ca.linkedin.com/in/oak-zeng-443b4322
Oak Zeng
GPU driver engineer at AMD
Toronto, ON
https://www.linkedin.com/in/srividya-karumuri-8959063b
Srividya Karumuri
GPU Compiler Engineer at Apple
San Jose, CA
https://www.linkedin.com/in/hyundokcho
Hyun Dok Cho
Compiler Software Engineer at NVIDIA
San Francisco Bay Area
https://www.linkedin.com/in/rishisurendran
Rishi Surendran
Deep Learning Compiler Engineer at NVIDIA
San Francisco Bay Area
https://www.linkedin.com/in/rishkul-kulkarni-3b77482a
Rishkul Kulkarni
Compiler Software Engineer at NVIDIA
Austin, TX
https://www.linkedin.com/in/samyukthagiriswamy
Samyuktha Giriswamy
Software Engineer 2 at Cisco
San Jose, CA
https://www.linkedin.com/in/kashish-shah
Kashish Shah
Engineer at NXP Semiconductors
San Francisco Bay Area
https://www.linkedin.com/in/shivashankargurumurthy
Shiva Gurumurthy
Senior Product Marketing Manager at AMD
San Francisco Bay Area
https://in.linkedin.com/in/sameerds
Sameer Sahasrabuddhe
Principal Member Of Technical Staff at AMD
Bengaluru
https://www.linkedin.com/in/namratakedia
Namrata Kedia
Product Manager @ Identity, Microsoft
Redmond, WA
https://www.linkedin.com/in/priyankapashte
Priyanka Pashte
Software Engineer II at Microsoft
Redmond, WA
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Afsana Chowdhury
MS-ECE Student at Duke University
Raleigh-Durham-Chapel Hill Area
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Emine Fidan
Ph.D. Candidate at North Carolina State University
Raleigh-Durham-Chapel Hill Area
https://www.linkedin.com/in/sagarupadhyay212
Sagar Upadhyay
Engineer at Intel Corporation
Sacramento, CA
https://www.linkedin.com/in/prashant-joshi
Prashant Joshi
DevOps Engineer at SkyCreek Corporation
Washington DC-Baltimore Area
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Arutika Sood
Senior Design Verification Engineer at Arm | Computer Engineer | Hardware Design and Verification
Chandler, AZ
https://www.linkedin.com/in/ankitaharmalkar
Ankita Harmalkar
Senior Digital Design Engineer at Intel Corporation
San Francisco Bay Area
https://www.linkedin.com/in/harshpreetkaursondh
Harshpreet Kaur Sondh
Senior Silicon Design Engineer at AMD
Austin, Texas Metropolitan Area
@Skillshare onboards Aayur Kaul as the India Market HeadRead More:https://lnkd.in/g7-XaPM4
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While we are at it, just a shout out to my amazing friend & senior from college, Saurabh Naresh Netravalkar who is currently the captain of (no…
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Aakanksha Patil
https://www.linkedin.com/in/aakanksha-patil
Master of Science in Data Science,  Actively seeking Internship opportunities for Summer '22| Data Science | Data Analysis | Machine Learning
Rochester, NY
Aakanksha Patil
https://in.linkedin.com/in/aakankshapatiljadhav
Associate Analyst BI at Eaton | Data Enthusiast | Business Analytics | MBA | Ex-GE India | COEP
Pune
Aakanksha Patil
https://in.linkedin.com/in/aakanksha-patil-9084a219b
SAP MM CONSULTANT
Maharashtra, India
Aakanksha Patil
https://in.linkedin.com/in/aakanksha-patil-0907a9190
Research Analyst - Technical Content Developer at AI Probably
Mumbai
Aakanksha P.
https://www.linkedin.com/in/patilaakanksha
Technology Sr. Analyst at Accenture
Duluth, GA