aanchal sharma
Product Manager at Astera Labs
product manager astera lab
Astera Labs
https://www.linkedin.com/company/astera-labs
Product Manager
San Francisco Bay Area
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Intel Corporation
https://www.linkedin.com/company/intel-corporation
Strategic Business Development Manager | Chief of Staff & TA to VP/GM (Datacenter Business Division)
•	Strategic partner to VP/GM responsible for developing, managing, and evangelizing holistic business unit strategy
•	Managed Business Unit’s yearly Goals – Revenue, P&L, Product Margin, LRP
•	Lead business development for Platform security, responsible for growth and long/short term strategy of the market segment 
•	Built BU-wide view of the state of the business with narratives for executive consumption for the quarterly business reviews
•	Drove low-end product definition to successful scheduled roll out in alignment with Intel Xeon Platforms roadmap
•	Managed technical marketing & customer requirements (new features & devices) to support segment growth
•	Led prioritization and tradeoff decisions for Cloud Business product requirements (Silicon and IP)
•	Drove execution efforts to resolve supply shortages at CSPs by creating short term & long-term mitigation strategy
San Francisco Bay Area
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Intel Corporation
https://www.linkedin.com/company/intel-corporation
Senior Field Application Engineer
•	Delivered 15+ key design wins ($$$M) for a diverse set of customer accounts (Cloud, Enterprise, Embedded)
•	Trained customers in FPGA chip design, tools (Quartus Prime), Code Optimizations, Configuration, PCIe and EMIF
•	Developed system level reference designs for Intel’s FPGAs and Ips
•	Specialized in PCIe based acceleration cards – lead successful qualification efforts for OEMs and SIs
San Jose, California
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Intel Corporation
https://www.linkedin.com/company/intel-corporation
Applications Engineer
•	Trained Neural nets on GPUs and ran inference on FPGA, GPU and CPU to evaluate competitor’s inference solution
•	Provided feedback to the strategy office for decision making
•	Resolved customer issues in the areas of timing Closure, RTL -Optimizations, Configuration and Flash Interface
•	Created a configuration tool using TCL (add on to Quartus) to enable sales debug in the field
San Jose, California
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University of Florida
https://www.linkedin.com/company/uflorida
Graduate Research Assistant
•	Explored applications to suit reconfigurable aspects of NOVO-G (FPGA based supercomputer) for National Science foundation funded CRI project 
•	Developed Lattice Boltzmann Kernel using VHDL and Verilog, data streaming through DMA interfacing

• Performed Simulations using modelsim and Signaltap to study behavioral flow of fluids
Gainesville, Florida Area
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POWERGRID
https://www.linkedin.com/company/powergrid
Intern
Worked on substation automation system (SAS).
Gurgaon, India
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Metso
https://www.linkedin.com/company/metso
Intern
Gurgaon, India
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Electrical and Computer Engineering
Master’s Degree
University of Florida
https://www.linkedin.com/school/uflorida/
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Electrical and Electronics Engineering
Bachelor’s Degree
PES University
https://www.linkedin.com/school/pesuniversity/
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85.2%
High School
Delhi public school
IEEE
Student Member
Achievement Award Scholarship for New Engineering Graduate Student
University of Florida
Achievement Award of First Class with Distinction in the Coursework.
PES Institute of Technology
Ranked amongst the top 0.1% of successful candidates in English Core at the national level
Central Board of Secondary Examination(CBSE)
Advanced Analog Electronic Circuits
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Advanced Power Electronics
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Analog Electronic Circuits
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Digital System Design
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Embedded Systems
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Microprocessers and Micro-controller
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Power Electronics
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Advanced vlsi circuits and design
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Computer Architecture
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Computer vision
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Digital Image Processing
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Embedded Systems Seminar
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Mixed Signal IC test 1
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Parallel Computer Architecture
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Reconfigurable Computing
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VLSI Circuits and Design
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Wireless Communications
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Independent Study
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Low Power MIPS Processor
-￼Design and implementation of a low-power five stage pipelined MIPS-8 architecture using Verilog.
-Specialized 16 bit Instruction set architecture (ISA) Design
-Power Optimization done using Dual ALUs and clock gating up to 46%
-Synthesis and APR done using Design Vision and Encounter.
-LVS and DRC matched
￼
Pedestrian Detection using Parallel HoG on Tegra TXI SoC
-Pedestrian detection application for the using HoG descriptor 
-Contrast improvement done using Contrast Limited Adaptive Histogram Equalisation (CLAHE)
-Pre-trained the SVM classifier used to identify the objects extracted by the descriptor
-implemented using Cuda and OpenMP
1D Time Domain Convolution on a Zynq processor based FPGA (ZedBoard) using VHDL.
•	Realized a customized circuit for 1D Time Domain Convolution.
•	Including DRAM DMA Interface, Convolution pipeline, Signal Buffer and Kernel Buffer.
•	with synchronization of data in different clock domains using Xilinx Vivado.
Design of a Synchronous 8x4 SRAM Core based on 0.25um TSMC Technology using Cadence Virtuoso.
•	Minimum transistor sizing was achieved by adjusting cell ratio(CR) and pull up ratio(PR).
•	The schematics, layouts and simulations were analyzed and evaluated.
•	Hold Stability, Read Stability and Write Stability (static noise margins), gate and diffusion capacitances, SRAM Cell and Core Area, read and write access time were recorded within desired and expected limits.
•	Layout design in Virtuoso, and meeting DRC and LVS constraints.
Cache replacement using Adaptive Scoring Technique
•	The aim of this technique is to enhance the performance of Cache lines based on both frequency as well as the time based use.
•	The Cache line with the least score is evicted.
•	Scores are determined using an algorithm, currently used for ranking web traffic, which is based on exponential decay. 
•	The dynamic initial weights were determined by monitoring the zero reuse lines.
•	Outstood traditional policies (LRU,FIFO,RANDOM) in 12 out of 18 benchmarks that were run using Simplescalar.
Automation of toll system using non-conventional energy resources:
•	Real time project designed to do the toll collection automatically.
•	Worked on interfacing of the arm controller and the RFID system.
•	Spontaneous error detection and formulation of the turbine.
Distance Range Sensor using ultrasound
•	This project offers a solution to short range distance sensing by using a proximity sensor.
•	 Implemented using an Arduino uno.
Designed and Fabricated an RC Airboat
•	Used for recording underwater movements.
•	Implemented using a 8051 micro controller, ESC, RC SET, battery and an AC motor.
•	Excellent maneuverability and speed of 2m/sec.
•	Presented it on a national level competition.
https://www.linkedin.com/in/ecehan-uludag-750104112
Ecehan Uludag
Chief of Staff/Technical Assistant to VP Embedded Acceleration Division at Intel Corporation
San Jose, CA
https://www.linkedin.com/in/shreyamehrotra
Shreya Mehrotra
Product Marketing Manager at Intel Corporation
Austin, Texas Metropolitan Area
https://www.linkedin.com/in/justinefig
Justine Figuerres
Field Sales Engineer at Intel Corporation
San Francisco Bay Area
https://www.linkedin.com/in/rishab-goel
Rishab Goel
Machine learning | Deep Learning | Computer Vision for Edge , AR/VR, Self-Driving and other devices / applications.
San Francisco Bay Area
https://www.linkedin.com/in/benjamin-reynolds-666a28b7
Benjamin Reynolds
Application Engineer at Intel Corporation - Programmable Solutions Group
San Jose, CA
https://www.linkedin.com/in/deepalic
Deepali Trehan
Vice President & General Manager at Intel Corporation | Visionary | Turnaround | Innovation
San Francisco Bay Area
https://www.linkedin.com/in/jake-bosset-a76971113
Jake Bosset
Field Sales Engineer at Intel Corporation
San Jose, CA
https://www.linkedin.com/in/christopher--george
Christopher George
Chief of Staff to the CEO at Intel Corporation
Portland, OR
https://www.linkedin.com/in/poojatyagi09
Pooja Tyagi
Technical Program Manager at Amazon Web Services (AWS)
San Jose, CA
https://www.linkedin.com/in/prasad-reddy-5197553
Prasad Reddy
Field Applications Engineering Management - Intel Corporation
San Jose, CA
https://www.linkedin.com/in/dhvanic1993
Dhvani Chheda
Software development engineer at Intel Corporation
Hillsboro, OR
https://www.linkedin.com/in/nga178
Nga deGrassi
Business Management at Intel Corporation
San Francisco Bay Area
https://www.linkedin.com/in/jimdworkin
Jim Dworkin
Vice President & General Manager, Cloud Business Unit at Intel PSG
San Jose, CA
https://www.linkedin.com/in/shweta-malik-4a812423
Shweta Malik
Platform PnP Architect | Innovator | People Connector | NFT Nerd
Hillsboro, OR
https://www.linkedin.com/in/meenakshi-bhatia-6781565a
Meenakshi Bhatia
Senior ASIC Design Engineer at Nvidia
Austin, TX
https://www.linkedin.com/in/ankur-vora-aa39b9a0
Ankur Vora
Strategic Wireless Business Developer at Intel Corporation
San Francisco Bay Area
https://www.linkedin.com/in/bassamdourassi
Bassam Dourassi (He/Him)
Serving the best way I can
San Francisco, CA
https://www.linkedin.com/in/ukorat
Uday Korat
Design Engineer at Microsoft
Folsom, CA
https://www.linkedin.com/in/afsyaw
Samuel Amoako-Frimpong
System Development Engineer at Amazon Web Services
Greater Sacramento
https://www.linkedin.com/in/simranjuneja
Simran Juneja
Lead- Business Development Representative at Click2Cloud | Former Program Manager at Microsoft
Bellevue, WA
Every master was once a novice. You have to start somewhere. Right?Be okay with being terrible in the beginning. Be okay with being mediocre in…
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Liked by Aanchal Sharma
Aanchal Sharma
https://in.linkedin.com/in/aanchal-sharma-81b0591bb
Pre -sales Associate at BYJU'S
Bengaluru
aanchal sharma
https://in.linkedin.com/in/aanchal-sharma-b38b041a
Human Resource  at Greenrock Enterprises
Greater Delhi Area
Aanchal Sharma
https://in.linkedin.com/in/aanchal-sharma-aa300b26
Human Resource
India
Aanchal Sharma
https://in.linkedin.com/in/aanchal-sharma-6273a7221
Key Account Manager at Grayquest
New Delhi
Aanchal Sharma
https://in.linkedin.com/in/aanchal-sharma-0a990b84
SharePoint Lead at Tata Consultancy Services
Delhi, India
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PRSSA - University of Florida
https://www.linkedin.com/groups/1806027
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FPGA - Field Programmable Gate Array
https://www.linkedin.com/groups/54049
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ASIC, FPGA, SoC Engineers
https://www.linkedin.com/groups/52741
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The University of Florida (Gator) Alumni
https://www.linkedin.com/groups/50263
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UF Postdocs
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Hardware Engineers - Bringup, Validation, Unit Testing, Debugging, Firmware
https://www.linkedin.com/groups/3860419
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VLSI open position
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VLSI
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PESIT Alumni Network
https://www.linkedin.com/groups/23034
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ECE Florida
https://www.linkedin.com/groups/4885286