aaron cook
Principal Design Engineer at Eta Wireless, Inc.
principal design engineer - team lead - analog mixed signal
electrical ic design engineer extensive success semiconductor industry . expertise integrated circuit design , revision control , model based design requirement management . guru git , matlab , simulink , scripting cadence . creating robust innovative new product passion .
Eta Wireless, Inc.
https://www.linkedin.com/company/eta-wireless
Principal Design Engineer
Cambridge, Massachusetts, United States
https://media-exp1.licdn.com/dms/image/C560BAQES6emgOFxkhg/company-logo_100_100/0/1519885140933?e=1655942400&v=beta&t=wf32MSj0bTtLNqoUbBvjRTh2sx9-jkQJjmBpSRSdNCo
Allegro MicroSystems, Inc.
https://www.linkedin.com/company/allegro-microsystems
Senior Electrical Design Engineer
• Lead team development of first 3D linear sensor ALS313131 and several flagship Allegro current sensors, ACS724 and ACS722. All are highly successful products and further spawned into a larger product family.
• Lead development of early GMR product
• Supported early development of corporate IP blocks found at the core of most Allegro products today. Designed early prototypes of charge pump system for EEPROM programming
• Designed, verified and synthesized complex speed and direction detecting Functional State Machines using Verilog code. These state machines are an integral piece of Allegro’s industry-leading speed and direction sensors
• Tuned and modified key analog signal processing circuitry
• Designed digital temperature compensation algorithms for world-class temperature-independent performance
• Performed automated verification and validation of silicon using MATLAB
• Simulated system-level silicon functionality in Cadence mixed-signal environment
• Wrote specification and designed simple single wire programming protocol for sensors
• Designed “LBIST” (Logic built-in self-test) controller widely used in Allegro Sensors for improving reliability.
Manchester, New Hampshire
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Allegro MicroSystems, Inc.
https://www.linkedin.com/company/allegro-microsystems
Principal Design Engineer - Team Lead
• Lead team development of automotive-grade 3D sensors
• Implemented design process changes that increased overall design process efficiency
• Designed and verified key digital algorithms and analog blocks
Manchester, New Hampshire
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Allegro MicroSystems
https://www.linkedin.com/company/allegro-microsystems
Intern
Allegro Microsystems: Internship	Manchester, NH Summer 2007

• Evaluated of test chip and Design of voltage regulator. Evaluated performance of a test chip for new process technology. Compared laboratory results with simulation results to determine the accuracy of the provided models. Blocks of the test chip evaluated included buffers, a delta-sigma A/D converter, and a bandgap reference. A follow was designing a voltage regulator in Cadence that supplied power for the digital portion of a future test chip. 

• Developed Rails website for Ocean Scripting. Designed a website using Ruby on Rails that generated ocean script templates for the Cadence design environment. The website’s purpose was to aid in PVT simulation, reducing the time by hours to run desired corner simulations. Required expertise of ocean scripts, the Cadence ADE, and Ruby.
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Linear Technology
https://www.linkedin.com/company/linear-technology
Intern
Linear Technology: Lab Internship Bedford, NH Summers 2005/2006

• Designed and created PCB Layout of Fast Active Load. Designed the active load’s power supply and an over-temperature protection circuit.  Used SwitcherCAD (LTSpice) to simulate and verify circuit operation. Designed PCB layout for the fast active load. Utilized PADS Logic and Layout to create a Gerber file for board manufacturing. After designing, populated PCB board and tested the operation of the fast active load.

• Created Inventory and Organization of Laboratory Supplies using Access Database. Designed an Access database and website that cataloged Linear Technology’s laboratory supplies and generated purchase orders when the supplies diminished.
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Electrical and Electronics Engineering
Bachelor of Science - BS
University of Maine
https://www.linkedin.com/school/university-of-maine/
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Supply voltage disturbance immunity for digital circuits
United States
A sensor integrated circuit includes a disturb immune memory configured to store data and a digital processor coupled to the disturb immune memory and including a main register. The digital processor is configured to perform one of a fast reset or slow reset of the main register according to a level of a supply voltage to the integrated circuit. The fast reset includes resetting the main register according to the data stored in the disturb immune memory and the slow reset includes resetting the main register according to a default state.
10635539
10635539
https://patents.justia.com/patent/10635539
Magnetic Field Sensor With Shared Path Amplifier And Analog-To-Digital-Converter
United States
A magnetic field sensor comprises at least one magnetic field sensing element configured to generate a measured magnetic field signal responsive to an external magnetic field; a diagnostic circuit configured to generate a diagnostic signal, wherein the diagnostic signal is not dependent on a measured magnetic field; a signal path comprising an amplifier and an analog-to-digital converter for processing the measured magnetic field signal to generate a sensor output signal indicative of the external magnetic field during a measured time period and for processing the diagnostic signal during a diagnostic time period; and a switch coupled to receive the measured magnetic field signal and the diagnostic signal and direct the measured magnetic field signal to the signal path during the measured time period and direct the diagnostic signal to the signal path during the diagnostic time period.
20180011140
20180011140
https://patents.justia.com/patent/20180011140
MAGNETIC FIELD SENSOR AND ASSOCIATED METHODS INCLUDING DIFFERENTIAL CHOPPING
United States
A magnetic field sensor includes a first magnetic field sensing element configured to generate a first magnetic field signal indicative of a magnetic field associated with a target, a second magnetic field sensing element spaced from the first magnetic field sensing element and configured to generate a second magnetic field signal indicative of the magnetic field associated with the target. A switching module coupled to receive the first and second magnetic field signals is configured to generate a combined signal having alternating portions associated with the first and second magnetic field signals.
20190302196
20190302196
https://patents.justia.com/patent/20190302196
Efficient Signal Path Diagnostics For Safety Devices
United States
An apparatus comprises a first measurement circuit having a first magnetic field sensing element to detect a measured magnetic field and produce a first signal representing the measured magnetic field, and a first signal processing circuit to process the first signal to produce a first processed signal. A second measurement circuit comprises a second magnetic field sensing element to detect a measured magnetic field and produce a second signal representing the measured magnetic field, and a second signal processing circuit to process the second signal to produce a second processed signal. A diagnostic processing circuit is coupled to receive the first signal and the second signal and configured to process the first signal during a first time period to produce a first diagnostic signal, and process the second signal during a second time period. A logic circuit determines if an error is present.
20190113584
20190113584
https://patents.justia.com/patent/20190113584
Circuits and methods for fault testing
United States
An integrated circuit sensor includes circuitry and methods for generating a high speed delay fault test clock signal. A trimmable oscillator generates a master clock signal for use by an output protocol processor to provide the sensor output signal. A fault test clock signal generator is responsive to the master clock signal and to a test trigger signal for generating the test clock signal having a launch pulse and a capture pulse, each having edges substantially coincident with like edges of pulses of the master clock signal and a spacing between launch and capture pulses established by the trimmable master clock signal.
US20130116945A1
US20130116945A1
https://patents.google.com/patent/US20130116945A1/en?assignee=aaron+cook&page=1
BANDGAP REFERENCE CIRCUIT
United States
A bandgap reference circuit includes a voltage reference circuit configured to generate a reference voltage at a first output and a proportional to absolute temperature (PTAT) current source configured to generate a PTAT current reference at a second output. A divider circuit is coupled to the reference voltage and configured to generate a divided reference voltage at a third output of the bandgap reference circuit. The bandgap reference circuit further includes a tunable current source coupled to the divider circuit and configured to generate a tunable current reference at a fourth output of the bandgap reference circuit based, at least in part, on the divider circuit. A method of generating a tunable current with a bandgap circuit is also provided.
20170269627
20170269627
https://patents.justia.com/patent/20170269627
Methods and Apparatus for Sensor Having Fault Trip Level Setting
United States
Methods and apparatus for a sensor having non-ratiometric fault trip level setting. In embodiments, a sensor has a sensing element with a fixed gain. A signal processing module receives the fault trip level setting and maintains the fault trip level setting constant during changes in the supply voltage.
https://patents.justia.com/patent/20170115362
Electronic Circuit For Driving A Hall Effect Element With A Current Compensated For Substrate Stress
United States
An electronic circuit can be disposed upon a semiconductor substrate. An epitaxial layer can be disposed over the semiconductor substrate. The electronic circuit can include a Hall effect element, at least a portion of the Hall effect element disposed in the epitaxial layer. The electronic circuit can further include a current generator configured to generate a drive current that passes through the Hall effect element. The current generator can include a resistor disposed in the epitaxial layer and having characteristics such that a resistance of the resistor can vary with a stress of the semiconductor substrate, resulting in changes of the drive current, to compensate for variations in the sensitivity of the Hall effect element with the stress of the substrate.
https://patents.justia.com/patent/20160299199
RubyGen
A ruby based register map generation tool.
https://github.com/cookacounty/rubyreg.git
GitPack
Multiple Git Repository Package Manager
https://github.com/GitPack/GitPackRuby
Design Team Lead ALS31300
The ALS31300 is Allegro's first 3d linear hall effect sensor. As design lead I was challenged with implementing a complex mixed signal system while keeping power and area to a minimum. I was responsible for a majority of the analog design and for the signal processing portion of the digital design. I take great pride in this product as well as techniques myself and the design team employed during the device's inception.
http://www.allegromicro.com/en/Products/Magnetic-Linear-And-Angular-Position-Sensor-ICs/Linear-Position-Sensor-ICs/ALS31300.aspx
Design Team Lead A1454
The A1454 is an I2C based linear Hall effect sensor IC which provides a 12-bit digital output word that is proportional to the strength of the magnetic field that is present. The A1454 was my first opportunity to explore my own limitations as a designer and I am proud to say that it is one of the best works of my career.
http://www.allegromicro.com/en/Products/Magnetic-Linear-And-Angular-Position-Sensor-ICs/Linear-Position-Sensor-ICs/A1454.aspx
Design Lead ACS724
The ACS724 is a Current Sensor IC With Common-Mode Field Rejection. The ACS724 was my second major design lead role at Allegro and involved major rework from existing products as well as translating from Cadence 5 to 6. Some of the key challenges in the design I was responsible for:
   - Writing scripts to reduce the manual effort of translating schematics between versions of software.
   - Analog design of several critical high performance blocks
   - Mixed signal verification of the top level IC
http://www.allegromicro.com/en/Products/Current-Sensor-ICs/Zero-To-Fifty-Amp-Integrated-Conductor-Sensor-ICs/ACS724.aspx
Design Lead ACS722
The ACS722 current sensor IC is an economical and precise solution for AC or DC current sensing in industrial, commercial, and communications systems. The ACS722 was my first design lead role and I was responsible for:
   - Modifying and improving the performance of existing analog circuitry
   - Mixed signal verification of the top level IC
   - Coordinating with layout engineers
http://www.allegromicro.com/en/Products/Current-Sensor-ICs/Zero-To-Fifty-Amp-Integrated-Conductor-Sensor-ICs/ACS722.aspx
CdsGit
CdsGit is a SKILL++ library written that allows a user to use Git to manage their cadence libraries. Unlike other Git clients, CdsGit is tailored to the cadence DFII infastructure and makes interfacing with Cadence cells easy.
https://github.com/cdsgit/cdsgit
https://www.linkedin.com/in/johnhoversten
John Hoversten
Founder/CTO at Eta Wireless, Inc.
Greater Boston
https://www.linkedin.com/in/gchen32
George Chen
Sr. Automotive HW Product Manager/PMM at Monolithic Power Systems, Inc.
San Francisco Bay Area
https://in.linkedin.com/in/shyam-narayan-gupta-482b596a
SHYAM NARAYAN GUPTA
Engineer -II, DEG Design at Micron Technology,Inc. Stdcell Design || Charecterization || Validation || DRAM ||DDR4,5 ||LPDDR4,5
Hyderabad
https://in.linkedin.com/in/dr-akhilesh-verma-65636720
Dr. Akhilesh Verma
Sr. Engineer (R & D) at Bhumi Entech Equipments Private Limited|Mentor at University of California, San Diego
Delhi, India
https://www.linkedin.com/in/athanasios-ramkaj
Athanasios (Thanos) Ramkaj, Ph.D.
Postdoctoral Research Fellow at Stanford University | Visiting Researcher at Kilby Labs
San Francisco, CA
https://www.linkedin.com/in/ajinkya-ambre
Ajinkya Ambre
Software Test Engineer at Qualcomm
San Diego, CA
https://www.linkedin.com/in/deborahbunting
Deborah Bunting, CIR
Senior Recruiter at Skyworks Solutions, Inc.
Cedar Rapids, IA
https://se.linkedin.com/in/christian-st%C3%A5hlberg-1271a527
Christian Ståhlberg
Senior Software Developer
Stockholm County, Sweden
https://www.linkedin.com/in/suresh-kariyadan-8300813
Suresh Kariyadan
Engineering Manager/Principal Power Architect at Apple
San Jose, CA
https://www.linkedin.com/in/abhorkar
Abhay Bhorkar
Product@Amazon | Smart Home | Alexa | CX | Day 1
Cupertino, CA
https://www.linkedin.com/in/tim-comer-b2a249139
Tim Comer
Mechanical / Manufacturing / Facilities Engineering
Princeton, WV
https://www.linkedin.com/in/sanchezleo
Leo Sanchez
Purpose driven investment leader passionate about helping people achieve their fullest potential! @mynd | ex-Zillow | #proptech #sfr #b2r
El Paso, TX
https://in.linkedin.com/in/nithin-kamath-81136242
Nithin Kamath
Founder & CEO at Zerodha
Bengaluru
https://www.linkedin.com/in/analogjedi
D. Jamie Haas
VP, Global Design Engineering, AIStorm
Concord, NH
https://www.linkedin.com/in/adam-lawrence-598b7b3
Adam Lawrence
Design Manager at Allegro MicroSystems
Goffstown, NH
https://www.linkedin.com/in/hong-xiao-55160332
HONG XIAO
Principal IC Design Engineer at Allegro MicroSystems
Greater Boston
https://www.linkedin.com/in/srujansj
Srujan Shivanakere
Electronic Design Engineer
Greater Boston
https://www.linkedin.com/in/loren-mclaury-16379311
Loren McLaury
Principal Design Engineer at Lattice Semiconductor
Hillsboro, OR
https://www.linkedin.com/in/jacob-w-reese
Jacob Reese
Principal Design Engineer at MACOM
Portland, OR
https://www.linkedin.com/in/gregwardle
Gregory Wardle
Principal Design Engineer at Maxim Integrated
San Jose, CA
D. Jamie Haas
      
          



            
              
        
              
  

    
        Simply stated, Aaron far exceeding my expectations during his internship at Allegro. Aaron is very talented and picked up technical concepts extremely fast. He was able to quickly understand complex problems presented to him. During his internship, Aaron developed a Web2.0 simulation worst casing tool for writing/modifying Cadence Ocean scripts for analog IC design. My group still uses this tool exclusively for design worst casing!
The dawn of a new era! Perhaps a 14 year old designing a chip is a bit of a stretch unless we are talking about connecting IP’s or logic gates…
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Liked by Aaron Cook
View my verified achievement from Cadence Design Systems.
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Liked by Aaron Cook
I have recently discovered Chisel. Think Object Oriented abstracted Verilog/VHDL. It is a hardware design language that facilitates advanced circuit…
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Liked by Aaron Cook
Aaron Cook
https://www.linkedin.com/in/aaron-cook-696b5626
Owner, Prestige Marble & Granite Inc.
Columbia, TN
Aaron Cook
https://au.linkedin.com/in/aaron-cook-73428061
WHS&E Coordinator
Nerang, QL
Aaron Cook
https://www.linkedin.com/in/aaron-cook-72633a33
Media Technician at Judicial Council of California
Greater Sacramento
Aaron Cook
https://au.linkedin.com/in/aaron-cook-5b820383
Director at Cie-Elle Digital Imaging
Greater Sydney Area
Aaron Cook
https://www.linkedin.com/in/aaron-cook-934a1aab
Head Football Coach at Galena HS
Greater Reno Area
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Analog Mixed-Signal and RF (AMS/RF) IC Design and Development Group
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ANALOG MIXED SIGNAL
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Analog & Mixed Signal Society
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Rubyists
https://www.linkedin.com/groups/120725
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MATLAB Users and Integrators
https://www.linkedin.com/groups/134533