For the given job description <<Calling all data nerds who love finance! 
If you're a data wiz but tired of sitting behind systems 100 percent of the time, this role offers the best of both worlds: 50% technical Tableau ownership and 50% FP&A support. The FP&A component means building relationships  you can work your magic in Tableau while developing your professional presentation and relationship-building skills. This role is the perfect next step if you want to be a well-rounded, polished, highly technical analyst. Apply today! Or message Lizzie to learn more: lizzie.schaut@ambrion.com

Responsibilities:Build reports and dashboards using Tableau Support annual budget preparation and forecastingPartner with business leaders to analyze financial data and present key trends and resultsDevelop financial forecasting models through data collection and analysis
Qualifications:Bachelor's degree in accounting, finance, or business administration4+ years of experience in an accounting or finance-related roleTableau experience (required)Advanced proficiency with Microsoft Excel 

Job Reference # 9323>> the resume: <<SummaryMS degree accredited Embedded Software Engineerwith wide-ranging expertise and in depth knowledge in research and development of real-time automotive diagnostic applications, digital logic design, network and software application
*Practical experience with embedded firmware, real-time operating system (RTOS), and HW/SW interactions    
*Established skills in design and implementation of multitasking, event driven firmware using C/C++
*Deep understanding vehicles communication system diagnostic protocols
*Mastering OS concepts of Resource Management, Interrupts, Service Routines, Timers and Threads
*Solid working knowledge of microcontroller based platforms and development processes - ColdFire, ARM, PPC, 68K
*Familiar with Information Security, Cryptography, biometric access control and identity authentication technologies
*Strong technical background in OOD/P,  Design Patterns and Multi-Threading in software application development
*Direct experience working closely with the ASIC/FPGA development processes and technologies including an in-depth understanding of system verification, debugging and testing environments 
*Experience with Portable Embedded Graphic User Interface - SWELL Software
*Good analytical, integration, support, and debugging skills on embedded systems
SkillsCAN, SPI, USB, I2C, USART, Eink EPDProtocols:     Bluetooth, WiFi, on-board vehicle diagnostics systems, vehicle bus standardLAN, WAN, Ethernet Spec, TCP/IP, IPSEC, MPLS, ATM, SONET/SDHSecurity background:    Multi-Factor authentication, Cryptography Algorithms, 3-DES, MD5, SHA, FIPS, PIVMicrocontroller:     ARM processors, Atmel, MicroChip ColdFireReal-time Operating System:     Micro Digital SMX RTOSProgramming Languages:    C, C++, C#, XML, VHDL, VerilogPlatforms:    Real-Time Operating System (RTOS), .NET, WindowsS/W tools:       Enterprise Architect, Code Warrior IDE, IAR, MS Visual StudioASIC backend:     Static timing analysis, P&R, LVS, DRC, ECO, gate-level simulation, vector generation
Experience03/2011toCurrentSr.  Embedded Platforms Software EngineerCaterpillar–Franklin,IN,Work on embedded software design, analysis, and development of real-time automotive diagnostic applications and Vehicle Communication System (VCS), running on Windows OS and microprocessor based (ARM, ColdFire) handheld platforms.Involved in different development areas of the Windows OS and Global Embedded Platforms Automotive Diagnostic Scanner products such as vehicle communication protocols, online expert vehicle repair information tools - CodeView, SureTrack & Troubleshooter Content Support, Graphical User Interface and Articles Rendering, sustain and enhance software releases bugs and issues.Revise and enhance current CAN driver of the ColdFire MCF5234 processor for the new diagnostic scanner products that employed the ARM STM32F769 processor for supporting current existing vehicle CAN protocols.Develop a Vehicle Repairs Information XML Rendering Engine to embed in the scanner diagnostic software for supporting online access for intelligence based on vehicles in service bays nationwide.Work on various Portable Embedded Graphical User Interface (GUI) aspects of Snap-on's diagnostic application and VCS software to enhance customers GUI experiences.Define and design of new custom user graphical interface objects, integrate hardware user interface components such as touch screen and keypad into the C/PEG development package.Sustain legacy scanner product lines, which operate on limited memory footprint and a small size database of vehicle information, to ensure forward compatibility with new generations of scanners installed with large internal system memory to work with the ever-increasing vehicle repaired system information.Lead the database size reduction development project. Develop methodologies for limited memory scanner devices to support vehicles with large information database.Redesign the architecture of the existing embedded scanner diagnostic memory system to improve memory usage by an order of magnitude. The tasks include investigating and migrating embedded product platforms from a multi-heap architecture to single heap architecture to resolve system lockup issues due to memory leaks and corruptions.Develop methodologies for handling of wireless system recovery from lost communication during a diagnostic scan session.Develop in-house debugging tools for embedded and Windows platforms development environment such as a "link Monitor" app to send logging data from embedded device to PC for viewing during debug session; Write Windows automation regression scripts for touch screen device; Develop embedding automation testing coverage features which helps QA engineers to speed up the products identification during debug cycles.Restructure and refactor the embedded product legacy "C" code base during the developing of software features requirement.A major contributor in the team effort to maintain bugs counts under control throughout the software release cycles.Provide fixes for several challenging technical bugs in many areas of the vehicle diagnostic system such as memory leak, corruption, and performance, vehicle protocols, scope and component tests, Graphical User Interface.11/2001to03/2011Sr.  Design EngineerPriva Technologies Inc–City,STATE,Developed authentication security products, involved in all development processes in hardware, firmware and software. My accomplishments were demonstrated by the following successful projects:Wrote specification for Priva ClearedPIV device, targeting to enhance US government requirement for Personal Identity Verification (PIV) Standard and the Smart Card Technology.Wrote specification, designed, implemented and tested the firmware of Priva ClearedBadge Identification Card, a key component of the Priva Airport Access Control System.Developed the embedded codes for Microchip micro-controllers embedded in the card.Designed and developed test & manufacturing automation software for Priva ClearedBadge device to verify firmware code, screen the device at assembly house and diagnose the device at installation site.Wrote specification, designed, implemented and tested the firmware of a fingerprint matching controller of the Priva Bio Match system.Ported the bio-matching on chip substantially improves the speed and the security of authentication in comparison to performing the task against an authentication server over the Internet.Using C++ and the ARM compiler for code development on the ARM based Atmel micro-controller (AT91FR40162).Designed and developed Priva in-house ASICs verification strategy. Tasks included:Developed emulation suites for the ASICs before tape-out. Tasks includes mapping the designed RTL codes into the Xilinx FPGA device on the ARM RealView development platform and developed software functional test drivers for the RTL code verification. Using Xilinx ISE FPGA development tools and .NET platform.Designed and developed Priva's software systems to test high volume chip production. Enabling detailed characterization and chip bring-up evaluation.  This system test resulted in high yield in chip production and significantly help shortening time for hardware development.Developed operational tests required by the Derived Test Requirement (DTR) to validate cryptographic modules of Priva designed security chip in compliance with the Federal Information Processing Standards Publication (FIPS PUB) 140-2.Worked with InfoGuard Labs to successfully obtain FIPS 140-2 Level 3 government-certified for Priva designed ClearedChip.Developed software evaluation kit for Priva's designed Secure-Key-Storage IC (SKSIC) being used by commercial users and defense contractors.Developed automation production tools to test, program and track the ClearedKey , a personal bio-metric authentication device incorporating the ClearedChip, prior to releasing to customers. The tasks included specifying the hardware test platform, developing the firmware for the system controller and providing the graphical user interface (GUI) test driver application.Developed the diagnostic test for the ClearedKey for sale/support engineers to use at the customer enrollment site to quickly identify defects.Developed firmware for the ARM based Atmel controller on the hardware platform for the GUI test and diagnostic applications.Developed the ClearedKey Manager Evaluation Module for Priva Retail Solution. This software module is used as a middle-ware to authenticate shopper against his Priva ClearedKey device.Developed the Cleared Access Evaluation Module for Priva's secured screening products evaluation. This software module is used as a middle-ware to authenticate user at the secured site.02/2000to11/2001Sr. ASIC/FPGA Design EngineerCorona Networks, Inc–City,STATE,Developed a 3-million gates Xilinx FPGA protocol converter from Flexbus4 (SPI-4) interface on the AMCC S19205 Khatanga 10 Gigabytes WAN PHY to the Focus Bus FPGA.The FPGA also had the capability to process MPLS packets at high speed (OC-192) to enhance router-based Quality of Service (QoS) and Traffic Engineering features.In addition, the FPGA converter had built-in statistic flow counters to keep track of the packet flows for billing calculation.Developed networking related ASIC/FPGA devices for the company's Service Edge Router 12000 products.Defined the specification and architecture of the Security and Compression Manager ASIC used in the IP Service Switch Products for supporting virtual private networks (VPN) technology.Completed the development of a high speed Altera FPGA (APEX 20K) that was used to speed up and load-balance incoming security packets of an IP Service Switch.Worked closely with system test engineers for the FPGA board bring-up and debugging.08/1995to02/2000Sr. ASIC/FPGA Design EngineerHolontech Corporations–City,STATE,Developed networking ASIC/FPGA devices for the company's Load Balancing Switching Products.Completed several FPGA prototypes and finalized ASICs: a PCI-compliant multi-layer switching ASIC for IP switch/router, a Search Engine ASIC used in a LAN/ATM switch, a 10/100 Mb Fast Multi-port Ethernet Controller (MPEC) ASIC.Designed several sub-modules of the ASICs such as a 100 MHz synchronous DRAM memory controller, a generic CPU interface module for the Search Engine ASIC, a Command Interpreter module to optimize the bandwidth of one of the ASIC's system PCI bus.Responsible for the back-end verification of the ASIC: Performing static timing analysis, blocks and chip level simulation, generate test vectors, develop functional and gate level test scripts.Worked closely with NEC and MITEL semiconductor vendors to support the back-end process (P&R, LVS, DRC, ECO, and Pre/Post timing analysis) of the ASICs.Involved in coding part of the system diagnostic test for the company's Hyperflow3 switch-load balancer system.01/1991to08/1995ASIC/FPGA Design EngineerStanford Telecom, Inc–City,STATE,Developed  telecommunication ASIC/FPGA devices for the Satellite Milstar and Low Cost Terminals projects: Tasks included:.Designed several sub-modules of the ASIC such as a Frequency Synthesizer, a Universal Asynchronous Receiver Transmitter (UART), a Discrete Fourier Transform (DFT) and a Viterbi Decoder etc.Developed software for the ASIC test fixtures, simulation models and simulation tools net list translators.
Education and TrainingExpected inDecember 2000totoBachelor of Science:Electrical/Electronic EngineeringSan Jose State University-San Jose,CaliforniaGPA:Expected in1990toto:Electrical/Electronic EngineeringCalifornia State University, Sacramento-Sacramento,CAGPA:
SkillsHardware and Software development, Networking, Authentication Security Systems, Vehicles Diagnostics Scanners. C/C++, .NET. ASIC/FPGA development.>>. The result is, No Fit

Fit assessment: No Fit