For the given job description <<Calling all innovators  find your future at Fiserv.
Were Fiserv, a global leader in Fintech and payments, and we move money and information in a way that moves the world. We connect financial institutions, corporations, merchants, and consumers to one another millions of times a day  quickly, reliably, and securely. Any time you swipe your credit card, pay through a mobile app, or withdraw money from the bank, were involved. If you want to make an impact on a global scale, come make a difference at Fiserv.
What does a successful Software Engineering Manager do at Fiserv?Fiserv is looking for a Software Engineering Manager to join our Core Acquiring Front End engineering group within Fiservs Global Business Solutions (Payment Acceptance) business.You will be joining an organization responsible for mission critical platforms that support our payments acquiring business. We process over 350 million payment transactions per day with a peak throughput of over 8,000 transactions per second all while maintaining millisecond fast response time. All this is done for some of the largest merchants in the US.This fast-paced online transaction processing environment requires a passionate critical problem solver who can balance platform stability and resiliency along with modern engineering practices and solutions.
What you will do:Manage cross-functional engineering teamsHands-on engineer  pickup stories, code reviews, and support production End-to end platform owner and engineer: design, build, and support resilient services  solutionsPartner with business owners to define platform roadmaps and scope for initiatives  featuresDrive prioritization of technical investment on in-scope platformsDesign performant, efficient, effective, and reusable technical solutions (partnering with architecture)Provide thought leadership across acquiring enginesPartner effectively with DevOps, Production Support, and peer platform teams
What you will need to have: 15+ years of experience in software engineering roles using C and Java10+ years of experience leading high-performing software engineering teams5+ years of experience in financial services or payments processingAbility to clearly communicate with executive leadership
What would be great to have:Bachelor's degree in computer science, engineering, or equivalent work experienceExperience in AIXExperience building solutions in public cloud (AWS, Azure, GCP)
Perks at work:Were #FiservProud of our commitment to your overall well-being with a growing offering of physical, mental, emotional, and financial benefits from day one.Maintain a healthy work-life balance with paid holidays, generous time off policies, including Unlimited Recharge & Refuel for qualifying associates, and free counseling through our EAP.Plan for your future with competitive salaries, the Fiserv 401(k) Savings Plan, and our Employee Stock Purchase Plan.Recognize and be recognized by colleagues with our Living Proof program where you can exchange points for a variety of rewards.Prioritize your health with a variety of medical, dental, vision, life, and disability insurance options and a range of well-being resources through our Fuel Your Life program.Advance your career with training, development, certification, and internal mobility opportunities.Join Employee Resource Groups that promote our diverse and inclusive culture where associates can share perspectives, exchange ideas, and elevate careers.
What you should know about us:Fiserv is a global fintech leader with 40,000-plus (and growing) associates proudly serving clients in more than 100 countries. As a FORTUNE 500 company, one of Fast Companys Most Innovative Companies, and a top scorer on Bloombergs Gender-Equality Index, we are committed to excellence and purposeful innovation.
Our commitment to Diversity and Inclusion:Fiserv is an Equal Opportunity Employer, and we welcome and encourage diversity in our workforce that reflects our world. All qualified applicants will receive consideration for employment without regard to race, color, religion, sexual orientation, gender identity, national origin, disability, protected veteran status, or any other category protected by law.
We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation.
Warning about fake job posts:Please be aware of fraudulent job postings that are not affiliated with Fiserv. Fraudulent job postings may be used by cyber criminals to target your personally identifiable information andor to steal money or financial information.
Any communications from a Fiserv representative will come from a legitimate business email address. We will not hire through text message, social media, or email alone, and any interviews will be conducted in person or through a secure video call. We wont ask you for sensitive information nor will we ask you to pay anything during the hiring process. We also wont send you a check to cash on Fiservs behalf.
If you see suspicious activity or believe that you have been the victim of a job posting scam, you should report it to your local FBI field office or to the FBIs Internet Crime Complaint Center.>> the resume: <<ProfileOver 20+ years of experience in Unix Kernel and Device Drivers development Highly experienced in architecture and design of PCI-Express and IO Virtualization Strong experience with PCI-Express hardware bringup on Oracle SPARC and Intel Platforms Highly focused, motivated and hard working engineer, always met the targets Experienced in working with geographically distributed teams in large and multiple organizations Member of PCI-SIG Software Working Group
Core QualificationsPCI-Express, SR-IOV, Virtualization (LDOMs, KVM, Xen), Hotplug, High Availability, Predictive Self HealingProtocols: PCI-Express, NVMe, TCP/IP, Fiber Channel, Infiniband, PCI, USBHardware: SPARC Systems (M-series, T-Series), Intel ServersOperating Systems: Solaris, Linux, Mac OS, Windows, Unix SVR 3.4Languages: C, C++, Assembly LanguageTools: PCI-Express, PCI and USB Analyzers, Debugging tools such as mdb, kmdb
Professional ExperienceSenior Principal Software Engineer,01/2010-PresentRtx–Indian Hills,CO,Working with Hardware team to architect and re-design next generation SPARC PCI-Express Root- Complex hardware for better error isolation to support high availability for Oracle Engineering and Cloud Platforms.Plus, exploring options to support PCI-Express QOS and ATS features for improved IO performance for Cloud Applications Worked with Hardware team to architect and design new SPARC PCI-Express Root-Complex to support NVMe surprise removal using PCIe DPC feature, IO Cache Scaling, DTU (IO Accelerator), SR-IOV IO Exerciser and Error Injector hardware.Worked on PCI-Express FMA Case Study for Oracle Platforms, identified all PCIe/IO FMA gaps and presented to wider engineering and management teams Lead engineer responsible for PCI-Express Hardware bringup and all Solaris IO software development for SPARC M7/T7 Systems Worked with Hardware team on new SPARC Interrupt Architecture based on priority based Event Queues (EQ) to deliver MSI/Xs, PCIe TLP Processing Hints and Atomics Ops features for SPARC M7/T7 Systems.Plus, lead software design and development for these features Led architecture, design and development of Solaris, and SPARC Logical Domains (LDOMs) support for Dynamic PCIe Bus Assignment to support multiple Root-domains Involved in the definition or direction of IO Resiliency (High Availability) feature for LDOMs that allows rebooting of PCIe Fabric owner while a VM with an SR-IOV VF continue to run.Led architecture, design and development of Solaris and SR-IOV support for LDOMs and Solaris Kernel Zones virtualizations for SPARC and Intel systems including design and development for SR-IOV NIC, Fiber Channel and Infiniband devices.Senior Staff Engineer,01/2003-01/2010Zendesk–KS,State,Founding member of the development team for Solaris PCI-Express Software Stack for Sun's SPARC and Intel Systems Led the design and development for Solaris PCI-Express Framework including SPARC and Intel PCI-Express Root-Complex, PCI-Express Switch and Bridge drivers Led the design and development for Solaris Interrupt Framework to support PCI-Express interrupts MSI, MSI-X, INTx and Messages including NUMA (device locality) based interrupt assignment and distribution and Solaris DDI interrupt interfaces for device drivers Led architecture, design and development for Solaris DMA Framework to support SPARC PCI-Express Root-complex ATU hardware (Multiple TSBs, Large IOMMU pages) including Solaris DDI DMA interfaces Led the design and development for Solaris Hotplug Framework including Virtual hotplug feature used to support IO Virtualization (PCIe Bus, Slot and VF assignments) Lead engineer responsible for majority of PCI-Express Hardware Bringup on all Sun's SPARC and Intel Servers and Workstations.Staff Engineer,01/1997-01/2003Nestle International–Daytona Beach,FL,Founding member of the development team for Solaris Universal Serial Bus (USB) software stack for Sun's SPARC and Intel and Workstations e.g., plug-n-play USB Storage, Keyboard, Mouse, Printer, Audio and more.Design and development of Solaris USB Framework Design and development of USB 1.1 (OHCI) and USB 2.0 (EHCI) Host Controller Drivers Lead engineer responsible for majority of USB Hardware Bringup on all Sun's servers and workstations Represented USB projects to different Architectural and Steering Committees at Sun Microsystems.Senior Software Engineer,01/1993-01/1997Soona–Los Angeles,CA,INDIADesign and development of Real-time drivers for Philips R300 MIPS CPU such as I2C, SIB, and IR drivers for pSOS+ and VxWorks.Design and development of Embedded STREAMS for pSOS+ including porting of communication protocol stacks X.25, SXB (Streams Cross-Bus), PIO (Parallel I/O) and Intellicom8 (Intelligent Async I/O) Streams drivers from UNIX to pSOS environment.Design and development of multi protocol gateway for Indian defense (DLRL, Hyderabad, India).Each gateway supported TCP/IP, X.25, Serial I/O and Parallel I/O stacks.As part of this big project, worked on the following sub-projects and key responsibility includes.Design and development of streams drivers for 8 port serial I/O controller and SLIP protocol.Design and development of streams Cross Bus (Intel 80386 based X.25 controller) host device driver.Configuring and testing of RIP and OSPF routing daemons.
EducationBS:Computer Science,Expected inAugust 1993-Mysore University-,GPA:Status-Computer Science
Skillsarchitect, Assembly Language, Audio, C, C++, Hardware, Controller, CPU, Debugging, direction, Drivers, engineer, features, gateway, Intel, Keyboard, Linux, Mac OS, Windows, MSI, next, NIC, Operating Systems, Oracle, OSPF, PCI, Printer, Protocols, Express, Real-time, RIP, routing, Scaling, Servers, software design and development, software development, Solaris, Sun, Sun Microsystems, SPARC, Switch, TCP/IP, UNIX, USB 1.1, USB 2.0, USB, VM, VxWorks, X.25>>. The result is, Potential Fit

Fit assessment: Potential Fit