For the given job description <<We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions help manufacturers to develop and deliver products quickly, efficiently and cost-effectively. Together, Teradyne companies deliver manufacturing automation across industries and applications around the world!
Organization & Role
If you are excited at the prospect of being part of a globally recognized technology company, Teradyne has an immediate opening for a Financial Analyst within the Semiconductor Test Division. This position works primarily with engineering project management and finance. This role offers hybrid flexibility, but does require on-site presence at our headquarters in North Reading, MA.
Responsibilities
 Managing R&D Spend for product roadmap.  Performing ROI analysis on current and future engineering investments.  Working closely with project managers to track and forecast spend to help make accounting judgements.  Prepare quarter-end journal entries and any necessary reporting functions.  Collecting, analyzing, and reporting on our quarterly expense, headcount and capital budgets.  Consistently improving processes to improve spending predictability. 
Basic Qualifications & Skills
 0-2 years of experience in finance or accounting (relevant co-op  internship experience will be considered).  Strong verbal and written communication skills  Proficiency in MS Excel. Experience with Oracle Financials and Microsoft BI  Ability to work independently with solid problem solving skills and attention to detail.  A desire to communicate with a diverse group of stakeholders. 
Education
 Bachelors degree in Accounting or Finance>> the resume: <<SummaryProficient engineer with keen analytical skills; adept at quickly identifying, creating, and implementing solutionsto complex problems. Extensive RF electronic design, development, and test experience as an RF Electrical Engineerand Engineering Technician.Easily adaptable, flexible, and open to any challenging, engineering opportunities within any technology areaor industry.Willing to relocateAuthorized to work in the US for any employer
HighlightsDiagnostic testingTest equipment operationClear communicatorProficient multi-taskerElectronic test toolsFeed-back amplifiersRFPA designSolderingRF designRF system troubleshootingPCB layoutMass production supervision for troubleshooting/repair radio system design
ExperienceRF Electrical Design Engineer,05/2009toCurrentIntel Corp.–New York,NY,Analog, RF and digital circuits design and test for next generation two way radios and telecommunication mobile devices.Design Projects: Test system design for power amplifier parameter testing using lab view (NI), Individual blocks in transmitter line up, analysis, design and testing, three stages PA, RF switch, harmonic filter, layout supervision especially the PA PCB layout, ground plane, ground relief, impedance mismatch, and characterization.Oversea travel for Mass production supervision for the radio system and individual blocks, PAs troubleshoot during mass production.FCC PA analysis, design, testing and FCC certification per FCC, EUROPE, ASIA requirements and regulations.1 Watt Power Amplifier design, ISM band (900MHz band) for digital radio 5 watts Broadband VHF Power Amplifier Design, for two way radio.4 Watts broadband UHF Power Amplifier Design for two way radio.3 Watts Broadband UHF Power Amplifier Design for two way radio Responsible for the transmitter line up section on the radio architecture.RF Harmonic Filter Design and Test for UHF Two way Radio, for both Asia, Europe and USA bands RF Harmonic Filter Design and Test for VHF two way radio, for both Asia, Europe and USA bands Band Pass filter design for UHF and VHF radio receiver, for both Asia, Europe and USA bands Current budget analysis for Transmitter, receiver and the whole radio system current analysis for the RF chip implementation.Led circuitry design for receive and transmit operation for two way radios.RF Power amplifier design line up, analysis and test for Transmitters and Transceivers.Test and Measurements Projects: Load pull analysis and measurements for power amplifier, RF Harmonics measurements, Conducted and Radiated measurements based on FCC requirements RF power measurements both Conducted and Radiated, for the two way radios Intermodulation rejection and adjacent channel rejection measurements and analysis Bluetooth analysis and measurements for the next generation two way radio Participation in the next generation wireless Transceiver chip Design for two way radio.Sensitivity measurements  both conducted and radiated, SINAD, Distortion etc..    highly involved in component selection for the radio systemdesign cost analysis.    Tune RFPA for Radio system transmitter power.    Collaborated with system, software and test engineers to establishcircuit performance specifications for multiple bands  radio systemtransmitter projects.Analog Engineer,05/2008to11/2008INTEL CORPORATION–City,STATE,Graduate Intern Technical: (Analog I/O, Mixed Signal, Analog Special Circuits Design Group, Visual Computing Group) Project1: PLL Design and Validation, clocking for next Generation GPU.Responsibilities: Analysis and design/validation of a LC-PLL Mega block chip using Cadence, Cadence Specman language, schematics, validate the PLL lock time in each chip block before Full chip validation, Analysis of LC-VCO, Phase Detector and charge pump, preparing all PLL technical specs docs, schematics, waveforms using MS Visio.Project2: Design and Modeling of 2GHz Buffered Clock Tree Distribution for GPU Chip.Analysis, design and modeling transistor level buffered clock tree distribution for the next generation GPU.Design and modeling the clock tree chip size based on GPU chip size and maintain low power and low delay, Using FTRC model to determine the length of the wire and size of the clock tree chip.
EducationBachelor of Science:Electrical and Computer Engineering,Expected inMarch 2006toThe Ohio State University-Columbus,OHGPA:GPA: 3.08Electrical and Computer EngineeringM.S.E.E:,Expected inDecember 2008to-,GPA:GPA: 3.727GPA: 3.727Associate of Science Degree, (A.S):Electrical and Computer engineering focus,Expected inDecember 2002toColumbus State Community College-Columbus,OHGPA:GPA: 3.10 Columbus State Community College Dean's listElectrical and Computer engineering focus GPA: 3.10 Columbus State Community College Dean's listMaster of Science:Electrical Engineering,Expected in2008toWright State University-Dayton,OHGPA:Electrical Engineering
SkillsAgilent Design Software ADS, AutoCAD, basic, Broadband, budget analysis, Cadence, Circuit Design,  Electronics, Flash, internet protocols, IP, LAN, layout, Law, Logic, MATLAB, office, Win, Microwave 4, Microwave, Minitab, Modeling, modem, NEC, Network, next, Oscilloscope, PSpice, quality, Radio, router, FM, schematics, shell, simulation, Spectrum Analyzer, supervision, switch, system design, TCP/IP, technical support, telecommunication, phones, Transmission, Troubleshoot, UHF, Validation, Verilog, VHDL, VHF, Video, View, Visio, VLSI, lab view experience, Network Analyzer, Signal Generator, Power Meter,>>. The result is, No Fit

Fit assessment: No Fit