For the given job description <<Shifts: Mon  Fri 8-5 (HYBRID onsite)3 month contract (No extensions)Start Date: 952023
Day-to-Day:Reviews, analyzes, reconciles, and interprets financial results in lower risk areas with business managers. Maintains a basic understanding of financial systems and data elements. Assists in the preparation of management reporting and analytical tools. Researches financial anomalies and makes corrections as necessary. Participates in the monthly financial statement close for assigned entity, division, profit center, or cost center Monitors compliance of processes, transactions, and balances with accounting and finance policies.
Must Haves:1 year with a Fortune 500multi-national consumer product companySAP ExperienceExperience with purchase orders and invoicesComfortable working in an ambiguous environment
Duties and ResponsibilitiesRun reports from eProcurement system, format and analyze dataCommunicate with internal and external stakeholders to resolve open POs, identify issues and offer solutions for resolutionUtilize Nike procurement, financial, and accounting software systems such as Coupa, Aravo, Akritiv, and SAPReview catalog supplier statements and advise resolution for submitting invoices and resolve outstanding payment issues
WHO YOU WILL WORK WITHYou will work with the Purchasing Integrity Team, as well as both internal and external business partners, and suppliers throughout Nike, Inc. to successfully support strategic capabilities for the Global Finance Operations team. You will assist in ensuring the cleanest data possible as we move to our future state.Seniority LevelEntry levelIndustryAutomation Machinery ManufacturingEmployment TypeContractJob Functions>> the resume: <<ProfileOver 20+ years of experience in Unix Kernel and Device Drivers development Highly experienced in architecture and design of PCI-Express and IO Virtualization Strong experience with PCI-Express hardware bringup on Oracle SPARC and Intel Platforms Highly focused, motivated and hard working engineer, always met the targets Experienced in working with geographically distributed teams in large and multiple organizations Member of PCI-SIG Software Working Group
Core QualificationsPCI-Express, SR-IOV, Virtualization (LDOMs, KVM, Xen), Hotplug, High Availability, Predictive Self HealingProtocols: PCI-Express, NVMe, TCP/IP, Fiber Channel, Infiniband, PCI, USBHardware: SPARC Systems (M-series, T-Series), Intel ServersOperating Systems: Solaris, Linux, Mac OS, Windows, Unix SVR 3.4Languages: C, C++, Assembly LanguageTools: PCI-Express, PCI and USB Analyzers, Debugging tools such as mdb, kmdb
Professional ExperienceSenior Principal Software Engineer,01/2010-PresentRtx–Indian Hills,CO,Working with Hardware team to architect and re-design next generation SPARC PCI-Express Root- Complex hardware for better error isolation to support high availability for Oracle Engineering and Cloud Platforms.Plus, exploring options to support PCI-Express QOS and ATS features for improved IO performance for Cloud Applications Worked with Hardware team to architect and design new SPARC PCI-Express Root-Complex to support NVMe surprise removal using PCIe DPC feature, IO Cache Scaling, DTU (IO Accelerator), SR-IOV IO Exerciser and Error Injector hardware.Worked on PCI-Express FMA Case Study for Oracle Platforms, identified all PCIe/IO FMA gaps and presented to wider engineering and management teams Lead engineer responsible for PCI-Express Hardware bringup and all Solaris IO software development for SPARC M7/T7 Systems Worked with Hardware team on new SPARC Interrupt Architecture based on priority based Event Queues (EQ) to deliver MSI/Xs, PCIe TLP Processing Hints and Atomics Ops features for SPARC M7/T7 Systems.Plus, lead software design and development for these features Led architecture, design and development of Solaris, and SPARC Logical Domains (LDOMs) support for Dynamic PCIe Bus Assignment to support multiple Root-domains Involved in the definition or direction of IO Resiliency (High Availability) feature for LDOMs that allows rebooting of PCIe Fabric owner while a VM with an SR-IOV VF continue to run.Led architecture, design and development of Solaris and SR-IOV support for LDOMs and Solaris Kernel Zones virtualizations for SPARC and Intel systems including design and development for SR-IOV NIC, Fiber Channel and Infiniband devices.Senior Staff Engineer,01/2003-01/2010Zendesk–KS,State,Founding member of the development team for Solaris PCI-Express Software Stack for Sun's SPARC and Intel Systems Led the design and development for Solaris PCI-Express Framework including SPARC and Intel PCI-Express Root-Complex, PCI-Express Switch and Bridge drivers Led the design and development for Solaris Interrupt Framework to support PCI-Express interrupts MSI, MSI-X, INTx and Messages including NUMA (device locality) based interrupt assignment and distribution and Solaris DDI interrupt interfaces for device drivers Led architecture, design and development for Solaris DMA Framework to support SPARC PCI-Express Root-complex ATU hardware (Multiple TSBs, Large IOMMU pages) including Solaris DDI DMA interfaces Led the design and development for Solaris Hotplug Framework including Virtual hotplug feature used to support IO Virtualization (PCIe Bus, Slot and VF assignments) Lead engineer responsible for majority of PCI-Express Hardware Bringup on all Sun's SPARC and Intel Servers and Workstations.Staff Engineer,01/1997-01/2003Nestle International–Daytona Beach,FL,Founding member of the development team for Solaris Universal Serial Bus (USB) software stack for Sun's SPARC and Intel and Workstations e.g., plug-n-play USB Storage, Keyboard, Mouse, Printer, Audio and more.Design and development of Solaris USB Framework Design and development of USB 1.1 (OHCI) and USB 2.0 (EHCI) Host Controller Drivers Lead engineer responsible for majority of USB Hardware Bringup on all Sun's servers and workstations Represented USB projects to different Architectural and Steering Committees at Sun Microsystems.Senior Software Engineer,01/1993-01/1997Soona–Los Angeles,CA,INDIADesign and development of Real-time drivers for Philips R300 MIPS CPU such as I2C, SIB, and IR drivers for pSOS+ and VxWorks.Design and development of Embedded STREAMS for pSOS+ including porting of communication protocol stacks X.25, SXB (Streams Cross-Bus), PIO (Parallel I/O) and Intellicom8 (Intelligent Async I/O) Streams drivers from UNIX to pSOS environment.Design and development of multi protocol gateway for Indian defense (DLRL, Hyderabad, India).Each gateway supported TCP/IP, X.25, Serial I/O and Parallel I/O stacks.As part of this big project, worked on the following sub-projects and key responsibility includes.Design and development of streams drivers for 8 port serial I/O controller and SLIP protocol.Design and development of streams Cross Bus (Intel 80386 based X.25 controller) host device driver.Configuring and testing of RIP and OSPF routing daemons.
EducationBS:Computer Science,Expected inAugust 1993-Mysore University-,GPA:Status-Computer Science
Skillsarchitect, Assembly Language, Audio, C, C++, Hardware, Controller, CPU, Debugging, direction, Drivers, engineer, features, gateway, Intel, Keyboard, Linux, Mac OS, Windows, MSI, next, NIC, Operating Systems, Oracle, OSPF, PCI, Printer, Protocols, Express, Real-time, RIP, routing, Scaling, Servers, software design and development, software development, Solaris, Sun, Sun Microsystems, SPARC, Switch, TCP/IP, UNIX, USB 1.1, USB 2.0, USB, VM, VxWorks, X.25>>. The result is, 

Fit assessment: No Fit