Job description:
about the position seeking remote position description perform all tasks appropriate to role, including technical analysis, database design, prototyping, coding and unit testing of applications with high quality deliverables. assist with application architecture design. responsible for writing technical documentation as necessary by the unos development methodology and standards. responsible for the security, quality, and performance of developed applications. apply and acquire business and product knowledge in the performance of assigned projects. provide direct input into the on-going improvement of standards and processes. incorporate innovative ideas and approaches to the software development team. key responsibilities: full stack developer with an emphasis on azureapiangular. write application and database codes based on business requirements or user stories, architectural requirements, and established coding standards. participate in the review of business epics and stories. validate code against business and architectural requirements. create and test prototypes. perform application unit testing. participate in peer code reviews. troubleshoot applications and resolve defects. work within an agile framework. prioritize and execute tasks. communicate ideas in both technical and user friendly language. update and maintain product documentation. escalate issues and impediments in a timely manner. work within established framework and processes. provide constructive feedback to team members at all levels of the organization. participatelead development cops. participate in se cops, research committees, and subcommittees. participate in test and code reviews. design, build, and test applications and database solutions. assist the release engineer with implementation plans. provide on call support as needed. utilize skills in data analysis, data verification, and problem solving. provide accurate breakdown tasks and estimates for coding and development unit testing efforts. mentor team members. assist with technical interviews and talent recruitment. hold team accountable for unos agile framework. other duties as directed. minimum requirements 2 years of software development experience required must have a demonstrated proficiency in an object oriented programming language must have a demonstrated knowledge of software design and development principles uiux principles required.responsive andor adaptive design knowledge required. critical skills .net c# api development experience required. mvcpattern proficiency required. experience with native application development (kotlin, java, objectivec, swift, etc.) a plus. strong knowledge of team-oriented and collaborative working environments. proven ability in relational database design and development principles. understanding of agile methodology principles preferred. software configuration management skills desired. continuous integration and deployment knowledge is a plus. mobile development skills preferred. active participation in the technical community desired. additional skills & qualifications excellent problem solving skills. excellent listening and feedback skills. exceptional interpersonal and consensus-building skills. excellent verbal, telephone, and written communication skills. education this position requires a four year degree in computer science or related field, or 5 years of related professional it experience. physical requirements general office demands qualifications. action is taken to ensure the fulfillment of this policy as to all phases of the employment process including hiring, placement, training, upgrading, transfers andor demotions, recruiting, layoffs and termination of employment. unos invites individuals with disabilities and . such communication will be kept as confidential as possible and will be used only in accordance with the law. candidates may contact the eeoaa officer at to self-identify or request an accommodation. eeo is the law eeo is the law supplement e-verify participation englishspanish right to work right to work spanish pay transparency

Resume:
<<summaryskilled at analyzing design specifications and applying verification techniques in verilog/vhdl. over 4 years of experience working on fpga design & verification, synthesis, place & route using synopsys synplify-pro/libero soc/xilinx-ise, c programming for arm/freescale cpus, testing with hyperlynx & pspice simulators. highlightshardware description languages: verilog, systemverilog for design/assertion,vhdl programming languages: c, tcl/perl scripting, c++, 8051/freescale/arm assembly tools: modelsim simulators, synopsys synplify pro, microsemi/actel libero soc 11.7, smarttime (static timing analysis tool), xilinx ise, synopsys design/ic compiler, primetime (sta), hyperlynx/lt/pspice simulators, orcad schematic capture/layout experience 04/2012tocurrentsenior electrical engineerhdr, inc.–raleigh.design, debug and verification of source code written in verilog for microsemi fpgas.worked with 2 fpga designs at the same time, handling both design and verification.simulation using modelsim and verifying the quality of testbench with code coverage.writing timing constraints and build scripts for fpga image release process using tcl.wrote systemverilog assertions & ovl assertions for asynchronous fifo verification.redesigned finite state machines (fsm) to meet max delay (setup time) timing goals.fixed clock domain crossing timing problems using smarttime static timing analyzer.reduced the overall resource utilization (area) of an existing fpga design by about 10%.writing digital core test plan for interfaces of fpga and freescale cpus (mpc5644).used hyperlynx simulation for signal integrity testing and directed 2 lab technicians. 10/2011to 01/2012test systems electrical engineer intern–,co,analog/digital circuit design, motor control using ti dsp and semiconductor testing.pcb (orcad) capture/layout and design of test fixtures in c and labview programs.designing in verilog hdl & verification using test benches (modelsim) for fpgas. 01/2011to 09/2011research assistant–.worked on low power optimization of fpga and asic using design and ic compiler.role was to write scripts (tcl), apply design constraints, perform power/timing analysis.included rtl synthesis, place and route, sta, test bench verification using verilog. 07/2008to 07/2009embedded engineeruniversity of north carolina greensboro–city.indiadesigning and debugging in embedded c/c++/assembly for 8051/8086/arm cpus.worked with robotics team on controlling the movement of robot using arm9 mcu.used stepper motors, serial interfaces, embedded web server & linux/windows os.jessica claire projects undertaken electronics injection/ignition driver control and diagnostics (at woodward inc.) fpga provides the control logic for the power electronics which in turn drives the injector and ignition coils.fpga also monitors and provides the diagnostics (open fault, short to gnd +/-, short to battery +/-) for each output/coil and sends this information to cpu via spi.apart from providing diagnostics information, fpga also protects the hardware instantly when some kind of critical fault is encountered.time to reach peak current was also reported by the fpga for diagnostics purposes for each output/coil (kv detection).trigger and discrete outputs control and diagnostics (at woodward inc.) fpga provides the control logic for power electronics which in turn drives the trigger and discrete outputs (high side, low side and push-pull/totem pole output).fpga also monitors and provides the diagnostics (open fault, short to gnd, short to battery) for each output and sends this information to cpu via spi.apart from providing diagnostics information, fpga also protects the hardware instantly when some kind of critical fault is encountered.power optimization in fpga/asic design using synopsys design and ic compiler tools.a 32-bit alu designed using verilog hdl using bottom up approach and horizontal/vertical partitioning techniques was taken as the design example.this project involved completing a low power asic design flow in 45 nm technology using synopsys design compiler and ic compiler in order to generate the gate level net list, perform placement, routing, clock tree synthesis and then optimize the power, area and timing of the design.implementation and design of dice game controller using xilinx spartan 3e fpga.this project involved implementing and designing the dice game controller using finite state machine (fsm) in vhdl and running the dice game on the spartan 3e fpga board.it mainly consisted of 2 counters, one adder to add the outputs of the 2 counters, a comparator to compare the sum and the point, register to store the point, control logic to find if the player wins or loses. education expected inmay 2011totomaster of science (ms):electrical engineeringcalifornia state university-,gpa:electrical engineeringexpected injune 2008totobachelor of engineering:electronics and communicationatria institute of technology (vtu)-,gpa:electronics and communication skills approach, asic, c++, circuit design, hardware, controller, cpu, debugging, designing, dsp, electronics, embedded c, image, labview, layout and design, layout, linux, logic, max, windows os, monitors, optimization, orcad, peak, perl scripting, programming, pspice, quality, robotics, routing, scripts, simulation, tcl, verilog, vhdl, web server, written.