Job description:
role: senior software engineer type: full-time as a senior software engineer, you'll lead modern tech projects using java, docker, and data modeling. what you'll do: define product architecture with leadership.translate business needs into technical solutions.mentor junior engineers for scalable cloud apps.stay updated on evolving technologies.what we're looking for: 5+ years in java (11 or 17+) development.aws cloud platform architecting.data modeling, relational, and nosql database skills.microservices, docker, kubernetes proficiency.python programming and gitgitops experience.innovative, collaborative mindset.strong communication and passion for sustainability.bsms in software engineering or related field.shape a w with us. apply for senior software engineer now.

Resume:
<<summaryproficient engineer with keen analytical skills; adept at quickly identifying, creating, and implementing solutionsto complex problems. extensive rf electronic design, development, and test experience as an rf electrical engineerand engineering technician.easily adaptable, flexible, and open to any challenging, engineering opportunities within any technology areaor industry.willing to relocateauthorized to work in the us for any employer highlightsdiagnostic testingtest equipment operationclear communicatorproficient multi-taskerelectronic test toolsfeed-back amplifiersrfpa designsolderingrf designrf system troubleshootingpcb layoutmass production supervision for troubleshooting/repair radio system design experience rf electrical design engineer, 05/2009tocurrentintel corp.– , and digital circuits design and test for next generation two way radios and telecommunication mobile devices.design projects: test system design for power amplifier parameter testing using lab view (ni), individual blocks in transmitter line up, analysis, design and testing, switch, harmonic filter, layout supervision especially the pa pcb layout, ground plane, ground relief, impedance mismatch, and characterization.oversea travel for mass production supervision for the radio system and individual blocks, pas troubleshoot during mass production.fcc pa analysis, design, testing and fcc certification per fcc, europe, asia requirements and regulations.1 watt power amplifier design, ism band (900mhz band) for digital radio 5 watts broadband vhf power amplifier design, for two way radio.4 watts broadband uhf power amplifier design for two way radio.3 watts broadband uhf power amplifier design for two way radio responsible for the transmitter line up section on the radio architecture.rf harmonic filter design and test for uhf two way radio, for both asia, europe and usa bands rf harmonic filter design and test for vhf two way radio, for both asia, europe and usa bands band pass filter design for uhf and vhf radio receiver, for both asia, europe and usa bands current budget analysis for transmitter, receiver and the whole radio system current analysis for the rf chip implementation.led circuitry design for receive and transmit operation for two way radios.rf power amplifier design line up, analysis and test for transmitters and transceivers.test and measurements projects: harmonics measurements, conducted and radiated measurements based on fcc requirements rf power measurements both conducted and radiated, for the two way radios intermodulation rejection and adjacent channel rejection measurements and analysis bluetooth analysis and measurements for the next generation two way radio participation in the next generation wireless transceiver chip design for two way radio.sensitivity measurements both conducted and radiated, sinad, distortion etc. highly involved in component selection for the radio systemdesign cost analysis. tune rfpa for radio system transmitter power. collaborated with system, software and test engineers to establishcircuit performance specifications for multiple bands radio systemtransmitter projects.analog engineer, 05/2008to 11/2008intel corporation–city,state,graduate intern technical: (analog i/o, mixed signal, analog special circuits design group, visual computing group) project1: pll design and validation, clocking for next generation gpu.responsibilities: analysis and design/validation of a lc-pll mega block chip using cadence specman language, schematics, validate the pll lock time in each chip block before full chip validation, analysis of lc-vco, phase detector and charge pump, preparing all pll technical specs docs, schematics, waveforms using ms visio.project2: design and modeling of 2ghz buffered clock tree distribution for gpu chip.analysis, design and modeling transistor level buffered clock tree distribution for the next generation gpu.design and modeling the clock tree chip size based on gpu chip size and maintain low power and low delay, using ftrc model to determine the length of the wire and size of the clock tree chip. education bachelor of science:electrical and computer engineering,expected inmarch 2006tothe ohio state university-columbus,ohgpa:gpa: 3.08electrical and computer engineeringm.s.e.e:,expected indecember 2008to-,gpa:gpa: 3.727gpa: 3.727associate of science degree, (a.s):electrical and computer engineering focus,expected indecember 2002tocolumbus state community college-columbus,ohgpa:gpa: 3.10 columbus state community college dean's listelectrical and computer engineering focus gpa: 3.10 columbus state community college dean's listmaster of science:electrical engineering,expected in2008towright state university-dayton,ohgpa:electrical engineering skills agilent design software ads, autocad, basic, broadband, budget analysis, cadence, circuit design, electronics, flash, , lan, layout, law, logic, matlab, office, win, microwave 4, microwave, minitab, modeling, modem, nec, network, next, oscilloscope, pspice, quality, radio, , schematics, shell, simulation, spectrum analyzer, supervision, switch, system design, tcp/ip, technical support, telecommunication, phones, transmission, troubleshoot, uhf, validation, verilog, vhdl, vhf, video, view, visio, vlsi, lab view experience, network analyzer, signal generator, power meter.