Products > FPGA & CPLD > CrossLink CrossLink Low power FPGA featuring hardened MIPI D-PHY, LVDS, SLVS, subLVDS, & Open LDI bridging Small Footprint, Big Features – Do you need to bridge, aggregate, or split signals for cameras and displays? CrossLink is the most versatile device and has a footprint as small as 6 mm2. How Low Can We Go – Up to 50% lower power than competition. < 100 mW for many use cases and the first programmable bridging solution with a built-in sleep mode. Sets the Bar in Performance – Industry’s fastest MIPI D-PHY bridging solution supporting 4K UHD resolution at speeds up to 12 Gbps. Also supports LVDS, SLVS, subLVDS, and OpenLDI (OLDI). Features Two 4-lane MIPI D-PHY transceivers at 6 Gbps per PHY 15 programmable source synchronous I/O pairs for camera and display interfacing Available in amazingly small 2.46 mm x 2.46 mm WLCSP packages and BGA packages with 0.4 mm, 0.5 mm and 0.65 mm pitch Flexible device configuration with OTP non-volatile configuration memory and I2C/SPI programming More than 5900 LUTs with up to 81 I/O pins Soft IP available for multiple bridging solutions here Contact Sales Jump to Family Table Example Solutions Video Design Resources Documentation Support Family Table CrossLink Device Selection Guide Features LIF-MD6000-36 LIF-MD6000-64 LIF-MD6000-81 LIA-MD6000-81 LIF-MD6000-80 LIA-MD6000-80 LIF-MD6000-80 LIA-MD6000-80 LUTs 5936 5936 5936 5936 5936 5936 5936 5936 Embedded Memory (kbits) 180 180 180 180 180 180 180 180 Distributed RAM (kbits) 47 47 47 47 47 47 47 47 GPLL 1 1 1 1 1 1 1 1 D-PHY PLL 1 2 2 2 2 2 2 2 Embedded I2C Blocks 2 2 2 2 2 2 2 2 Embedded RX/TX MIPI D-PHY 1 (4 Data + 1 Clock) 2 (8 Data + 2 Clock) 2 (8 Data + 2 Clock) 2 (8 Data + 2 Clock) 2 (8 Data + 2 Clock) 2 (8 Data + 2 Clock) 2 (8 Data + 2 Clock) 2 (8 Data + 2 Clock) 48 MHz Oscillator 1 1 1 1 1 1 1 1 10 KHz Oscillator 1 1 1 1 1 1 1 1 NVCM Yes Yes Yes Yes Yes Yes Yes Yes Dual Boot1 Yes Yes Yes Yes Yes Yes Yes Yes Power Management Unit Yes Yes Yes Yes Yes Yes Yes Yes Low Power Sleep Mode Yes Yes Yes Yes Yes Yes Yes Yes Typical Operational Power 5 mW - 135 mW 5 mW - 135 mW 5 mW - 135 mW 5 mW - 135 mW 5 mW - 135 mW 5 mW - 135 mW 5 mW - 135 mW 5 mW - 135 mW Footprint 2.5 mm x 2.5 mm 3.5 mm x 3.5 mm 4.5 mm x 4.5 mm 4.5 mm x 4.5 mm 6.5 mm x 6.5 mm 6.5 mm x 6.5 mm 7.0 mm x 7.0 mm 7.0 mm x 7.0 mm Package Pitch 0.4 mm 0.4 mm 0.5 mm 0.5 mm 0.65 mm 0.65 mm 0.65 mm 0.65 mm Programmable I/O 17 29 37 37 37 37 37 37 Automotive No No No Yes No Yes No Yes 1. Dual Boot supported with external boot Flash Example Solutions Expand Image ADAS Application Bridge multiple CSI-2 image sensors into one single MIPI CSI-2 output for 360 degree camera application. Camera input support from a variety of interfaces like CSI-2, LVDS, Sub-LVDS and LVCMOS. Multiple camera interfaces supported to bridge to the Application Processor. Stitch data together into larger horizontal video frame. Expand Image Multi CSI-2 Image Sensor Interface Bridging Solutions Bridge multiple CSI-2 image sensors into one MIPI CSI-2 output Configure multiple image sensors with same I2C slave address from one I2C master Trigger and synchronize image sensors with GPIO control Stitch data together into larger horizontal video frame Arbitrate data from image sensors and append unique virtual channel numbers Click here for more information Expand Image Multi MIPI DSI Display Bridging Drive multiple MIPI DSI displays or display requiring two MIPI DSI interfaces Replicate video to both displays or reduce the bandwidth by half on output over two PHYs Control peripheral functions and power sequencing of displays with additional GPIO Click here for more information Expand Image Display Interface Conversion Bridging Convert to/from MIPI DSI, OpenLDI/LVDS, and RGB/CMOS Support all data types and number of lanes Support additional functions such as display and peripheral initialization, control and sequencing Crop & scale video data to match special formatting needs Click here for more information Expand Image Camera Interface Conversion Bridging Convert to/from MIPI CSI-2, SubLVDS, LVDS, CMOS, HiSPi and other image sensor interfaces Control frame and line readout controls for slave driven image sensors Convert I2C to SPI for image sensor and peripheral control Crop & scale video data to match special formatting needs Click here for more information Video Expand Image Introduction to CrossLink Learn how CrossLink can solve interfacing problems including implementing multi CSI-2 bridges for mixing, merging, arbitrating, converting multiple image sensor interfaces to a single applications processor. Expand Image CrossLink IP Cores for Mobile Influenced Markets Check out how CrossLink's collection of IP cores helps you solve design challenges with MIPI interface adoption. Expand Image Using Lattice CrossLink FPGA for 360 Surround View Applications Taking a simple camera and converting it regular image into a 360 surround view doesn't have to be difficult. Learn how our CrossLink FPGA can help. Expand Image Adding CrossLink IP Using Clarity Designer Check out how easy it is to add CrossLink IPs to your designs. Expand Image Debug Your Project with Reveal This video shows you how to add Reveal to debug a project. Awards Expand Image Embedded World Awards 2017 Hardware Product Nominee Expand Image EEPW Magazine (China) 2016 Editor's Choice Award Best FPGA Product Design Resources Development Kits & Boards Our development boards & kits help streamline your design process Development Kits & Boards for CrossLink Intellectual Property & Reference Designs Simplify your design efforts by using pre-tested, reusable functions IP and Reference Designs for CrossLink Software Complete Design Flows, High Ease of Use Lattice Diamond Documentation To subscribe, or modify your subscription, to Document Notifications please login to your Lattice account Quick Reference Key Documents Data Sheet Application Note Pin & Package Technical Resources Product Change Notification Schematic Symbols Information Resources Product Brochure Quality Assurance White Paper Infographic Downloads Delphi Models IBIS Model TITLE NUMBER VERSION DATE Select All Advanced CrossLink I2C Hardened IP Reference Guide FPGA-TN-02020 1.1 1/31/2021 CrossLink Memory Usage Guide FPGA-TN-02017 1.2 1/31/2021 CrossLink High-Speed I/O MIPI D-PHY and DDR Interfaces FPGA-TN-02012 1.3 4/28/2021 CrossLink Hardware Checklist FPGA-TN-02013 1.3 1/7/2021 CrossLink I2C Hardened IP Usage Guide FPGA-TN-02019 1.1 1/7/2021 CrossLink sysCLOCK PLL/DLL Design and Usage Guide FPGA-TN-02015 1.5 4/27/2021 CrossLink sysI/O Usage Guide FPGA-TN-02016 1.3 4/6/2020 CrossLink Programming and Configuration Usage Guide FPGA-TN-02014 1.5 7/20/2021 MIPI D-PHY Bandwidth Matrix and Implementation FPGA-TN-02090 1.2 6/19/2019 Power Management and Calculation for CrossLink Devices FPGA-TN-02018 1.1 10/25/2018 PCB Layout Recommendations for BGA Packages FPGA-TN-02024 4.7 9/21/2021 CrossLink Family Data Sheet FPGA-DS-02007 2.0 8/31/2021 CrossLink Automotive Family Data Sheet FPGA-DS-02013 1.7 12/10/2020 Package Diagrams FPGA-DS-02053 6.7 11/9/2021 CrossLink LIF-MD6000 Pinout 1.5 7/12/2019 *By clicking on the "Notify Me of Changes" button, you agree to receive notifications on changes to the document(s) you selected. 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