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Samsung and LG are using Cadence's Tensilica HiFi Audio in their DTVs. Home: IP Portfolio > Verification IP > Productivity Tools Design IP Tensilica IP Verification IP Simulation VIP Memory Models Accelerated VIP Assertion-Based VIP Productivity Tools Interconnect Solution Productivity Tools Boost Productivity with Products that Complement Our VIP System-on-chip (SoC) verification is a big job. That's why high-level verification languages like e and SystemVerilog were developed along with companion methodologies like the Universal Verification Methodology (UVM). But language and methodology only take you so far. Cadence provides additional productivity-boosting tools to help you configure, run, and analyze your design. With these products, you get up and running quickly and shorten your overall verification project. Indago Protocol Debug App View Demo Product Description Verifying the standard interfaces in IP blocks and SoCs can be one of the most resource-intensive tasks for verification teams. Popular interface specification families such as ARM® AMBA®, DDR, MIPI, PCIe Express, USB and others have undergone major expansions in recent years. Verification engineers seldom have more than a couple weeks to ramp up on a new protocol before they have to start verifying designs incorporating it. Commercial VIP helps offload part of the verification effort, but engineers still need a window into the protocol-specific interactions between the design, the VIP, and the testbench to find the root causes of bugs. Such a window is provided by the Indago Protocol Debug App, which presents a holistic picture of the verification environment in four views. Key Features Visualization of data and control traffic in protocol terminology Ability to go back and forth in simulation time All debug information automatically collected from Verification IP View of complete testbench with multiple protocols/ instances Synchronized view of messages, state machines, parameters and data traffic Supports all simulators Channel Viewer Graphical presentation of transactions clarifies design behavior Select data types or packets to see preferred level of detail Error highlighting reveals design bugs Highlights connection between different transactions State Machine Viewer State machine diagrams relate design behavior to specification terminology See what states were visited during simulation View reasons for state changes and see event timing Drill down to lower-level state machines Smart Log Simple, intuitive way to filter the log file to your specific needs Set up multi-level queries to save and share Warnings and errors highlighted and connected to relevant packets Life Story See everything that happened to a given object during simulation View registers, packets, state machines, lanes, queues configuration space, etc. Filter history to focus on important events Merge object histories from multiple simulations Hierarchy Viewer Lists the VIP instances of the recorded simulation for multiple protocols Displays the values of VIP attributes of each instance such as Configuration, Call backs, Registers, Internal queues, Interesting events Acts as a starting point in the simulation analysis Enables opening the more specific viewers – such as channel, memory, and FSM – per instance The Channel Viewer portrays the communication between the design and VIP with a lab equipment-style view showing the sequence of transactions with protocol-specific labeling. The State Machine Viewer shows a graphical view of the state machines within the VIP components along with the causes of state transitions. The Life Story and Smart Log provide detailed views of all events pertaining to simulation objects and smart filtering of messages. Together, these views present an integrated picture of the design and verification environment to simplify the debugging process. Resources Downloads Indago Protocol Debug App Datasheet Videos Play Cadence Indago PureView PureView is a graphical cockpit used to configure all our VIP products. Many interface protocols have dozens of configuration options. To match a VIP component to your design, each option needs to be set correctly. It would be time-consuming and error-prone to set every parameter with a text command, but PureView makes it easy. The tool walks you through a hierarchy of menus to configure a VIP component. It only shows you relevant options based on previous choices and prevents illegal settings. PureView is also used to configure memory model options and TripleCheck tests. Example PureView menus for PCI Express VIP configuration Resources Downloads PureView Productivity Tools Datasheet TripleCheck for MIPI UniPro 1.6 TripleCheck for MIPI UniPro 1.6 helps you verify that your design complies with the interface specification. This is different than a post-silicon compliance test that measures electrical parameters. TripleCheck works during pre-silicon logic simulation to stress-test functional behavior. TripleCheck is the third-generation compliance product to be offered by Cadence, delivering an enhanced test suite, coverage model, and verification plan. PureView Integration TripleCheck is integrated with our PureView solution for quick set-up. When you configure a VIP with PureView, the TripleCheck test suite, coverage model, and vPlan are automatically configured to match the VIP. Test Suite TripleCheck provides an extensive library of test sequences to stimulate the design under test. The test library contains directed tests (providing quick checks for common protocol compliance issues) as well as constrained-random test sequences for exhaustive testing to detect corner-case bugs hidden in the design. The tests support error injection in each layer of the protocol stack to check operation of the design when faced with non-compliant stimulus. This combination of directed and constrained-random tests results in high functional coverage, right out of the box. Coverage Model Coverage models are provided in both SystemVerilog and e verification languages. These pre-defined coverage models capture all data items and state machine transitions to track and measure verification progress. The coverage models are open and documented, which allows you to extend them with application-specific coverage definitions. Verification Plan TripleCheck provides a verification plan that mirrors the protocol specification. All the requirements in the protocol specification are listed in the plan and organized into the same chapter and paragraph hierarchy. The vPlan is linked to the coverage model so that the coverage data captured during simulation runs is automatically mapped against the plan. This makes it easy to track verification progress and determine how much work remains. The vPlan is written in XML to enable portability between simulation environments. In the Cadence Incisive Simulation environment, TripleCheck integrates with the Incisive vManagert tool to enable a number of productivity-boosting features, such as bucket analysis to analyze coverage details and test profiling to sort out unproductive test sequences. MIPI UniPro Features Feature Name Description Advanced error reporting Stimuli and coverage collection of all applicable error scenarios State machines Stimuli and coverage collection of all state machine transitions Transaction formation rules Stimuli and coverage collection of all applicable transactions Third-Generation Solution TripleCheck is a third-generation pre-silicon compliance test suite solution. It combines the features from Cadence's other test suite solutions to deliver the most advanced pre-silicon compliance test suite on the market. Test Suite Comparison Basic CMS PureSuite TripleCheck Constrained-random example tests Directed compliance tests Constrained-random compliance tests Tests targeting all protocol layers 3rd party simulator test execution SystemVerilog functional coverage model efunctional coverage model Verification plan mapped to protocol specification Verification plan integration with Cadence vManager metric-driven analysis system Verification plan integration with 3rd party simulator environments Resources Downloads MIPI UniPro TripleCheck Datasheet MIPI Family Brochure Press Release Cadence Announces TripleCheck IP Validator for Faster IP Compliance Testing Article How to Pick the Best Verification IP for Your Application Cadence supports development of the cloud 4 VIP user types, 2 different approaches How TripleCheck IP Validator Eases Use of Verification IP (VIP) Industry Insights: "Best Practices for Selecting and Using Verification IP" Training VIP Training TripleCheck for PCI Express TripleCheck for PCI Express helps you verify that your design complies with the interface specification. This is different than a post-silicon compliance test that measures electrical parameters. TripleCheck works during pre-silicon logic simulation to stress-test functional behavior. TripleCheck is the third-generation compliance product to be offered by Cadence, delivering an enhanced test suite, coverage model, and verification plan. PureView Integration For quick set-up, TripleCheck is integrated with our PureView solution. When you configure a VIP with PureView, the TripleCheck test suite, coverage model, and vPlan are automatically configured to match the VIP. Test Suite TripleCheck provides an extensive library of test sequences to stimulate the design under test. The test library contains directed tests (providing quick checks for common protocol compliance issues) as well as constrained-random test sequences for exhaustive testing to detect corner-case bugs hidden in the design. The tests support error injection in each layer of the protocol stack to check operation of the design when faced with non-compliant stimulus. This combination of directed and constrained-random tests results in high functional coverage, right out of the box. Coverage Model Coverage models are provided in both SystemVerilog and e verification languages. These pre-defined coverage models capture all data items and state machine transitions to track and measure verification progress. The coverage models are open and documented, which allows you to extend them with application-specific coverage definitions. Verification Plan TripleCheck provides a verification plan that mirrors the protocol specification. All the requirements in the protocol specification are listed in the plan and organized into the same chapter and paragraph hierarchy. The vPlan is linked to the coverage model so that the coverage data captured during simulation runs is automatically mapped against the plan. This makes it easy to track verification progress and determine how much work remains. The vPlan is written in XML to enable portability between simulation environments. In the Cadence® Incisive® Simulation environment, TripleCheck integrates with the Incisive vManager tool to enable a number of productivity-boosting features, such as bucket analysis to analyze coverage details and test profiling to sort out unproductive test sequences. PCI Express Features Feature Name Description Advanced Error Reporting Stimuli and coverage collection of all applicable error scenarios Full LTSSM Transitions Stimuli and coverage collection of all LTSSM transitions Equalization Procedure Stimuli and coverage collection of all aspects of equalization process Packet Formation Rules Stimuli and coverage collection of all applicable TLPs Third-Generation Solution TripleCheck is a third-generation pre-silicon compliance test suite solution. It combines the features from Cadence's other test suite solutions to deliver the most advanced pre-silicon compliance test suite on the market. Test Suite Comparison Basic CMS PureSuite TripleCheck Constrained-random example tests Directed compliance tests Constrained-random compliance tests Tests targeting all protocol layers 3rd party simulator test execution SystemVerilog functional coverage model efunctional coverage model Verification plan mapped to protocol specification Verification plan integration with Cadence vManager metric-driven analysis system Verification plan integration with 3rd party simulator environments Resources Downloads TripleCheck for PCIe Productivity Tools Datasheet Press Release Cadence Announces TripleCheck IP Validator for Faster IP Compliance Testing M31 Technology Adopts Cadence Verification IP to Achieve 2.5X Faster Verification Article How to Pick the Best Verification IP for Your Application Cadence supports development of the cloud 4 VIP user types, 2 different approaches How TripleCheck IP Validator Eases Use of Verification IP (VIP) Industry Insights: "Best Practices for Selecting and Using Verification IP" Training VIP Training TripleCheck for MIPI CSI-2 TripleCheck for MIPI CSI-2 helps you verify that your design complies with the interface specification. This is different than a post-silicon compliance test that measures electrical parameters. TripleCheck works during pre-silicon logic simulation to stress-test functional behavior. TripleCheck is the third-generation compliance product to be offered by Cadence, delivering an enhanced test suite, coverage model, and verification plan. PureView Integration TripleCheck is integrated with our PureView solution for quick set-up. When you configure a VIP with PureView, the TripleCheck test suite, coverage model, and vPlan are automatically configured to match the VIP. Test Suite TripleCheck provides an extensive library of test sequences to stimulate the design under test. The test library contains directed tests (providing quick checks for common protocol compliance issues) as well as constrained-random test sequences for exhaustive testing to detect corner-case bugs hidden in the design. The tests support error injection in each layer of the protocol stack to check operation of the design when faced with non-compliant stimulus. This combination of directed and constrained-random tests results in high functional coverage, right out of the box. Coverage Model Coverage models are provided in both SystemVerilog and e verification languages. These pre-defined coverage models capture all data items and state machine transitions to track and measure verification progress. The coverage models are open and documented, which allows you to extend them with application-specific coverage definitions. Verification Plan TripleCheck provides a verification plan that mirrors the protocol specification. All the requirements in the protocol specification are listed in the plan and organized into the same chapter and paragraph hierarchy. The vPlan is linked to the coverage model so that the coverage data captured during simulation runs is automatically mapped against the plan. This makes it easy to track verification progress and determine how much work remains. The vPlan is written in XML to enable portability between simulation environments. In the Cadence Incisive Simulation environment, TripleCheck integrates with the Incisive vManagert tool to enable a number of productivity-boosting features, such as bucket analysis to analyze coverage details and test profiling to sort out unproductive test sequences. MIPI UniPro Features Feature Name Description Advanced error reporting Stimulus and coverage collection for all applicable error scenarios. State machines Stimulus and coverage collection for all state machine transitions. Transaction formation rules Stimulus and coverage collection for all applicable transactions. Physical layer 4 D-PHY/C-PHY data lanes CSI-2 receiver DUT. Multi lane distribution and merging Distribution and merging of data between D-PHY data lanes. Low level protocol CSI-2 frames and packet structures. Data Formats All valid CSI-2 data types. Annex C - CSI-2 recommended receiver error behavior Error scenarios in the PHY, packet and frame layers. CPHY Errors Multiple error scenarios for C-PHY physical layer MIPI CSI-2 Receiver Protocol Conformance Test Suite The Triple-check test suite includes the implementation of all CTS tests that are defined in CSI-2 Receiver Protocol Conformance Test Suite Version 1.01 PHY new features The suite supports the DPHY 1.2 skew calibration feature (Initial and Periodic) + low-power data after triggers Third-Generation Solution TripleCheck is a third-generation pre-silicon compliance test suite solution. It combines the features from Cadence's other test suite solutions to deliver the most advanced pre-silicon compliance test suite on the market. Test Suite Comparison Basic CMS PureSuite TripleCheck Constrained-random example tests Directed compliance tests Constrained-random compliance tests Tests targeting all protocol layers 3rd party simulator test execution SystemVerilog functional coverage model efunctional coverage model Verification plan mapped to protocol specification Verification plan integration with Cadence vManager metric-driven analysis system Verification plan integration with 3rd party simulator environments Resources Downloads MIPI CSI-2 TripleCheck Press Release Cadence Announces TripleCheck IP Validator for Faster IP Compliance Testing Article How to Pick the Best Verification IP for Your Application Cadence supports development of the cloud 4 VIP user types, 2 different approaches How TripleCheck IP Validator Eases Use of Verification IP (VIP) Industry Insights: "Best Practices for Selecting and Using Verification IP" TripleCheck for MIPI SoundWire TripleCheck for MIPI Soundwire helps you verify that your design complies with the interface specification. This is different than a post-silicon compliance test that measures electrical parameters. TripleCheck works during pre-silicon logic simulation to stress-test functional behavior. TripleCheck is the third-generation compliance product to be offered by Cadence, delivering an enhanced test suite, coverage model, and verification plan. PureView Integration TripleCheck is integrated with our PureView solution for quick set-up. When you configure a VIP with PureView, the TripleCheck test suite, coverage model, and vPlan are automatically configured to match the VIP. Test Suite TripleCheck provides an extensive library of test sequences to stimulate the design under test. The test library contains directed tests (providing quick checks for common protocol compliance issues) as well as constrained-random test sequences for exhaustive testing to detect corner-case bugs hidden in the design. The tests support error injection in each layer of the protocol stack to check operation of the design when faced with non-compliant stimulus. This combination of directed and constrained-random tests results in high functional coverage, right out of the box. Coverage Model Coverage models are provided in both SystemVerilog and e verification languages. These pre-defined coverage models capture all data items and state machine transitions to track and measure verification progress. The coverage models are open and documented, which allows you to extend them with application-specific coverage definitions. Verification Plan TripleCheck provides a verification plan that mirrors the protocol specification. All the requirements in the protocol specification are listed in the plan and organized into the same chapter and paragraph hierarchy. The vPlan is linked to the coverage model so that the coverage data captured during simulation runs is automatically mapped against the plan. This makes it easy to track verification progress and determine how much work remains. The vPlan is written in XML to enable portability between simulation environments. In the Cadence Incisive Simulation environment, TripleCheck integrates with the Incisive vManagert tool to enable a number of productivity-boosting features, such as bucket analysis to analyze coverage details and test profiling to sort out unproductive test sequences. MIPI SoundWire Features Feature Name Multi-Lane Payload Transport High-PHY Mode Synchronization Enumeration Data payload traffic Bank switching Resets Error scenarios Interrupts Multicast and broadcast slave accesses Test data modes Slave command responses Command ownership Flow control Bulk Payload Third-Generation Solution TripleCheck is a third-generation pre-silicon compliance test suite solution. It combines the features from Cadence's other test suite solutions to deliver the most advanced pre-silicon compliance test suite on the market. Test Suite Comparison Basic CMS PureSuite TripleCheck Constrained-random example tests Directed compliance tests Constrained-random compliance tests Tests targeting all protocol layers 3rd party simulator test execution SystemVerilog functional coverage model efunctional coverage model Verification plan mapped to protocol specification Verification plan integration with Cadence vManager metric-driven analysis system Verification plan integration with 3rd party simulator environments Resources Downloads Triplecheck for SoundWire Datasheet TripleCheck for Bluetooth 5 TripleCheck for Bluetooth 5 helps you verify that your design complies with the interface specification. This is different than a post-silicon compliance test that measures electrical parameters. TripleCheck works during pre-silicon logic simulation to stress-test functional behavior. TripleCheck is the third-generation compliance product to be offered by Cadence, delivering an enhanced test suite, coverage model, and verification plan. PureView Integration TripleCheck is integrated with our PureView solution for quick set-up. When you configure a VIP with PureView, the TripleCheck test suite, coverage model, and vPlan are automatically configured to match the VIP. Test Suite TripleCheck provides an extensive library of test sequences to stimulate the design under test. The test library contains directed tests (providing quick checks for common protocol compliance issues) as well as constrained-random test sequences for exhaustive testing to detect corner-case bugs hidden in the design. The tests support error injection in each layer of the protocol stack to check operation of the design when faced with non-compliant stimulus. This combination of directed and constrained-random tests results in high functional coverage, right out of the box. Coverage Model Coverage models are provided in both SystemVerilog and e verification languages. These pre-defined coverage models capture all data items and state machine transitions to track and measure verification progress. The coverage models are open and documented, which allows you to extend them with application-specific coverage definitions. Verification Plan TripleCheck provides a verification plan that mirrors the protocol specification. All the requirements in the protocol specification are listed in the plan and organized into the same chapter and paragraph hierarchy. The vPlan is linked to the coverage model so that the coverage data captured during simulation runs is automatically mapped against the plan. This makes it easy to track verification progress and determine how much work remains. The vPlan is written in XML to enable portability between simulation environments. In the Cadence Incisive Simulation environment, TripleCheck integrates with the Incisive vManagert tool to enable a number of productivity-boosting features, such as bucket analysis to analyze coverage details and test profiling to sort out unproductive test sequences. Bluetooth 5 Features Feature Name Description Advertiser High Duty-Low Duty, Directed-Undirected, Connectable-NonConnectable Advertisement Scanner/Initiator Active-Passive Scanning Master/Slave Support for all Control Procedures e.g. Connection Update, PHY Update LE Encryption Counter with Cipher Block Chaining-Message Authentication Code (CCM) Mode LL Privacy Generation of Resolvable Private Address Host Controller Interface LE HCI commands/events/data fully supported HCI transport Layer UART/USB/User-Defined protocol as a HCI transport layer Mbps LE 2 Ms/s packets transmission and reception capability LE Long Range Configurable Coded PHY for FEC2 Block with S=2/S=8 LE Advertising Extensions Advertisement/Connection on Primary/Secondary Channels using EXT/AUX PDUs, Periodic Advertisement LE Channel Selection Algorithm#2 Counter based Channel Selection Algorithm for Secondary Channels Third-Generation Solution TripleCheck is a third-generation pre-silicon compliance test suite solution. It combines the features from Cadence's other test suite solutions to deliver the most advanced pre-silicon compliance test suite on the market. Test Suite Comparison Basic CMS PureSuite TripleCheck Constrained-random example tests Directed compliance tests Constrained-random compliance tests Tests targeting all protocol layers 3rd party simulator test execution SystemVerilog functional coverage model efunctional coverage model Verification plan mapped to protocol specification Verification plan integration with Cadence vManager metric-driven analysis system Verification plan integration with 3rd party simulator environments Subscribe to Newsletter IP Portfolio Design IP Tensilica IP Verification IP Applications Mobile Handsets Home Entertainment PCs and Printers Automotive Storage / SSD Internet of Things (IoT) Convolutional Neural Networks (CNN) HiFi Integrator Studio Knowledge Center Standards-Based and Analog IP Tensilica Processors Verification IP Embedded Neural Network Summit Support Free Software Evaluation Training Benchmarks and Evaluations Xtensa Processor Generator Tensilica Support Center Partners Overview Operating Systems Emulation & Probes Silicon & Services EDA & ESL Tools Libraries, Memories & Interconnect Application Software Imaging/Video Software Audio Software About Overview News and Events University Program Customer Profiles Contact Careers Social Media ©2016 Cadence Design Systems, Inc. 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