Tensilica Fusion G3 DSP Exceptional out-of-the-box performance for compute-intensive applications GET DETAILS News VIEW ALL Tensilica Vision DSP IP The performance needed for complex algorithms Latest News 27 Sep Cadence Recognized with Four TSMC Partner of the Year Awards 27 Sep Cadence Announces General Availability of Tensilica Xtensa LX7 Processor Architecture, Increasing Floating-Point Scalability with 2 to 64 FLOPS/Cycle Events VIEW ALL November 2-3 in San Jose, CA Get the Latest Formal Verification Tips Upcoming Events 11 Oct MemCon 2016 12 Oct - 13 Oct ICCAD 2016 18 Oct Technology on Tour: Ankara Blogs VIEW ALL Paul McLellan's Breakfast Bytes Fresh every morning - Industry news and analysis Latest Blogs The Innovus Implementation System routing capability enables us to drive those defects even lower for our automotive customers. Dragomir Nikolic, Worldwide CAD Director, Cypress Semiconductor Read More Emulating Nvidia GPUs RTL Design, Genus Style: The scoop on how you can get hours of your life back Verify Smarter with Industry's First Datacenter-Class Emulation System Tools System Design and Verification Digital Design and Signoff Custom IC / Analog / RF Design IC Package Design and Analysis PCB Design and Analysis Tools A-Z IP Tensilica Processors Interface IP Denali Memory IP Analog IP Systems/Peripheral IP Verification IP Support Online Support Training Software Downloads University Software Program Resource Library News Press Releases Newsroom Blogs Forums Company Cadence Overview Investor Relations Alliances Executive Team Events Careers A Great Place to Do Great Work! Second year on the FORTUNE 100 list Our Culture Join the Team Contact Us General Inquiry Customer Support Media Relations Global Office Locator Subscribe to Monthly Newsletter Email * Worldwide Terms of Use Privacy Policy US Trademarks © 2016 Cadence Design Systems, Inc. All Rights Reserved. Connect with Us