Log In|Register|Resource Library|Worldwide ToolsIPSolutionsServicesSupport and TrainingAlliancesCommunityCompany Home > About Cadence > Events > Event Details ARM TechCon 2014 Type: Industry Conference Date: 01 Oct 2014 - 03 Oct 2014 Location: Santa Clara Convention Center, Santa Clara, CA Register » Visit Cadence at ARM TechCon to learn more about our ARM® optimized solutions, from system to silicon. Our technical experts will be on hand to present papers and speak at the sponsored sessions on Wednesday, October 1. Cadence Sponsored Sessions Wednesday, October 1 Time Description 11:00am – 11:50am Realizing a High-Performance, Power-Efficient ARM Cortex®-A57 Processor Implementation at 16nm 12:00pm – 12:50pm ARMv8 SoC HW/SW Integration and Verification Solution 2:00pm – 2:50pm Addressing MCU Mixed-Signal Design Challenges 3:00pm – 3:50pm Case Study: Cutting Performance Verification Time with Automated Characterization Tests and Analysis Tools 4:00pm - 4:50pm Pushing the Performance Boundaries of ARM Cortex-M for Future Embedded Processor Design Cadence Conference Papers Wednesday, October 1 Ballroom F Time Description 11:00am – 11:50am Deploying Signoff DFM Checks to Fulfill 28 and16FF Foundry Requirements 4:00pm - 4:50pm Comprehensive HW-SW Debug for ARM Based Designs Friday, October 3 Ballroom G Time Description 11:30am - 12:20pm Reducing Time to Point of Interest with Accelerated OS Boot Cadence Demos In the exhibit hall, at booth #313, you'll see demos in the following areas: Exploring the performance envelope of an ARMv8 mobile compute sub-system Demonstrate the results of the auto-generated Cadence® Interconnect Workbench Performance Characterization (IPC) test suite when applied to an ARMv8 mobile compute sub-system Cadence mixed-signal flow for embedded ARM Cortex-M0 designs Functional and low-power verification covering analog, digital, and software Smooth path to silicon using integrated mixed-signal physical implementation flow Cadence digital RTL-to-signoff solution Physically aware synthesis and place-and-route technologies for delivering optimal performance, power, and area (PPA) on ARM Cortex cores Integrated power, timing, and physical verification signoff for reducing signoff closure time while minimizing pessimism and power Characterization link to implementation and accurate signoff Cadence’s Virtuoso® Liberate™ and Spectre® characterization solution. The Liberate tool generates electrical cell views for timing, power, and signal integrity. Flow implemented by ARM to characterize advanced 16nm FinFET libraries for designing high-performance, low-power SoCs at advanced geometries System-to-silicon verification for ARMv8 and ARMv7 designs Accelerates hardware/software development and system integration and is optimized for ARMv8 based designs Reduces development risk through a suite of connected platforms for virtual prototyping, RTL simulation, acceleration and emulation, and FPGA-based prototyping Combines with cross-platform solutions and technologies to raise the level of verification above RTL Questions About this Event? Send email to events@cadence.com Register » About Cadence| Investor Relations| Careers| Terms of Use| Privacy Policy| US Trademarks © Cadence Design Systems, Inc. All Rights Reserved.