English | 日本サイ ト | 中文网站 | SOLVNET HOME TOOLS IMPLEMENTATION & SIGNOFF PHYSICAL IMPLEMENTATION IC COMPILER II - GDSII PLACE AND ROUTE SYSTEM Language: 日本語 Introducing IC Compiler II Antun Domic Introduces IC Compiler II IC Compiler II is a complete place and route system that enables 10X faster throughput for designs across all process nodes. Hear what Antun Domic, executive vice president and general manager of Synopsys' Design Group, has to say about this new physical implementation solution. View More IC Compiler II Videos IC Compiler II IC Compiler II is a complete netlist to GDSII place-and-route system that enables 10X faster throughput for designs across all process nodes, while improving final quality of results (QoR). IC Compiler II is specifically designed to address today's hypersensitive time-to-market pressures while delivering best-in-class solutions for flat and hierarchical design planning, early design exploration and prototyping, placement and optimization, clock tree synthesis, routing, manufacturing compliance, and low-power challenges. IC Compiler at DAC 2014 IC Compiler II is a complete netlist to GDSII place-and-route system that enables 10X faster throughput for designs across all process nodes, while improving final quality of results (QoR). IC Compiler II is specifically designed to address today's hypersensitive time-to-market pressures while delivering best-in-class solutions for flat and hierarchical design planning, early design exploration and prototyping, placement and optimization, clock tree synthesis, routing, manufacturing compliance, and low-power challenges. IC Compiler II Launch at SNUG-SV The IC Compiler II launch at SV SNUG was well received by large in-person audiences. This video captures the keynote address, the luncheon event where key customers shared their experiences using IC Compiler II, and the R&D panel where the Synopsys technologists shared deep insights into the inner workings of the new architecture and algorithms. Share the launch experience through this short video. R&D Insights IC Compiler II Core Infrastructure Mark Bales, Synopsys Scientist, explains the new IC Compiler II infrastructure and how it enables 10X faster throughput. Download Whitepaper IC Compiler II Optimization Thomas Andersen, Group Director R&D, provides an overview of physical optimization in IC Compiler II and how the new global-analytics- based framework enables high QoR along with fast, hierarchical full chip closure. Download Whitepaper IC Compiler II Clock Synthesis Aiqun Cao, Principal Engineer, discusses how IC Compiler II’s new clock synthesis delivers faster design convergence with automated variation-tolerance. Download Whitepaper IC Compiler II Design Planning Neeraj Kaul, Group Director R&D, discusses hierarchical design planning in IC Compiler II and how the new data and tool architectures enable unprecedented design capacity and throughput. Download Whitepaper INTRODUCING IC COMPILER II Visit the web resource for information on this new place-and-route system CUSTOMER EVENT AT DAC 2014 Addressing Advanced Design Needs IC Compiler and IC Compiler II CUSTOMER TESTIMONIALS See what designers are saying about IC Compiler II IC COMPILER II DATASHEET The Leader in Place and Route Now with the Power of 10X WHITE PAPERS IC Compiler II and place and route design white papers Click thumbnail to enlarge photo News Articles White Papers Webinars Videos LYNX DESIGN SYSTEM GALAXY PLATFORM IC VALIDATOR PLATFORM RELEASES SOLVNET SNUG © 2014 Synopsys, Inc. All Rights Reserved. Contact us | Locations | Privacy | Legal