DESIGN TEST PRODUCTION LAB e-SHOP SUPPORT Boundary Scan Technology CPLD/FPGA Programming CPU Emulation Flash Programming FPGA Control Test Functional Test High Speed I/O IJTAG Intel® IBIST JTAG JTAG Boundary Scan Test Microprocessor Test P1687 Software Debug Software Trace Structural Test System Level Test The Test Portal TEST: The Boundary Scan Technology | High Density Boards | BGA packaging | System Level Test | Flash | CPLD/FPGA | Tutorial | Books | Training CPLD/FPGA reprogrammable logic on the boards PROBLEM In-System Configuration (also known as In-System Programming (ISP) or on-board programming) is the process of programming CPLDs (complex programmable logic devices) after they have been soldered to a board. ISC is accomplished using tools provided by programmable device vendors, on ATE/ICT testers, or by PC-based tools designed for boundary-scan test such as ASSET. Device-vendor tools support only devices from that vendor and have limited scan path management support. Each tool has a unique user interface to learn and a unique connection to the board. These tools use the PC parallel port for access to the board. As a result, designs that use more than one device type require you to switch between vendor tools to program each device type. ISC with ATE/ICT allows ISC to be integrated with test operations, but it is expensive. Time on ATE/ICT systems can cost as much as $1.00 per second and programming times typically range between 5 seconds and two minutes. Programming file sizes for ATE/ICT can also be very large, exceeding the capability of the testers. SOLUTIONS Implementing ISC with PC-based tools solves many of the problems associated with your other options. This is a universal solution, supporting devices from all major vendors via one user interface and one connection to the board. This also allows the integration of ISC and test on a low cost test platform (typical costs - $0.05 per second). With sophisticated scan path management capabilities, the system provides safer scan path integrity testing and is able to maintain a board state that is safe for programming. It also enables ISC across complex scan paths such as system backplanes. Finally, using hardware optimized for boundary-scan application enables significant reduction in programming times. [2015-08-13] Full advantage of Intel Trace Hub [2015-07-28] In-System Flash Programming 1,000x Faster [2015-05-27] Trace debug cuts through complexity of SoC [2014-03-31] Press Release | Sarokal RBS Test [2015-11-10] Productronica 2015 [2015-11-24] Nordic Test Forum 2015 [2016-02-23] Embedded World 2016 [2016-04-25] IEEE VLSI Test Symposium 2016 [2016-11-08] Electronica 2016 ABOUT US | CONTACT | SUPPORT ISS Group Box 14049 SE-167 14 Bromma SWEDEN Tel +46 (0)8 506 181 00