IC MANUFACTURING COMPOUND SEMICONDUCTORS WAFER LEVEL PACKAGING TECH PAPERS COMPANY INVESTORS CONTACT IC Manufacturing The industry’s most advanced wafer cleaning technologies for current and future processing nodes Improved cleaning—an increasingly critical need… New digital devices rely on the development of progressively faster, more powerful, smaller and lower cost semiconductors chips. However, as device features continue to shrink, smaller and smaller defects become “killer defects” which reduce yields—and profits. These defects can originate from many sources, so chip fabrication must include many cleaning steps. With increasing chip complexities, each wafer can now require as many as 200 cleaning steps during its manufacture. And advanced wafer cleaning systems must be smarter than ever. Today’s wafer cleaning is facing unprecedented challenges. On the one hand, it must be thorough and aggressive enough to remove very small defects in hard-to-reach areas across the entire surface of the wafer. On the other hand, the cleaning process must be gentle enough not to damage the smallest and most fragile 2D and 3D circuit structures. Advanced wafer cleaning systems: the problems with previous technologies As process nodes shrank below 100nm, fabs switched from batch processes to single wafer cleaning tools using either jet spraying or megasonic vibration to improve cleaning performance. Jet spray cleaning shoots high-velocity water droplets at a wafer surface to remove defects. Megasonic cleaning transmits acoustic waves through a fluid bath to produce bubble oscillation, in a process known as “transient cavitation,” to dislodge defects that were difficult to clean by jet spray. However, in conventional megasonics the bubbles collapsed quickly and generated energy that could damage smaller, more delicate chip features. Also, those tools did not deliver energy uniformly across the wafer surface, which resulted in inadequate and uneven cleaning. With process nodes shrinking to 14nm and below, the cleaning process becomes even more complicated, challenging—and critical: Random defects are harder to remove as killer-defect sizes decrease. Newer 3D structures such as FinFET transistors are often more fragile and susceptible to damage than older conventional 2D structures. Cleaning challenges increase with increased aspect ratios — in vias, for example. While conventional 2D structures typically have aspect ratios of 3:1 or less, FinFET structures may have aspect ratios of 5:1 currently and more than 10:1 in the future. And other new 3D structures may have aspect ratios as high as 60:1. ACM’s Smart Megasonix™—the industry’s most advanced cleaning For all of these reasons ACM has developed innovative single wafer wet cleaning technologies and advanced wafer cleaning systems that can be used at existing and future process nodes across the range of processing steps—to achieve thorough, comprehensive cleaning, evenly across the wafer, and without damage to device features. These proprietary new ACM technologies are able to precisely control both the power intensity and the distribution of megasonic cleaning—with a dramatically positive effect. SAPS™ cleaning technology: for flat and patterned wafers–to 14nm and beyond ACM’s proprietary Space Alternated Phase Shift (SAPS™) technology employs alternating phases of megasonic waves to deliver megasonic energy to flat and patterned wafer surfaces in a highly uniform manner on a microscopic level. This enables it to remove random defects across an entire wafer much more efficiently than conventional jet spray processes. SAPS technology has demonstrated its advanced cleaning capabilities as nodes shrink from 32nm to 10nm and even beyond, for which jet spray technology is becoming less effective. Moreover, users of SAPS equipment have already expanded their application of ACM tools, adding cleaning to more processing steps to increase yields and reduce chemical usage. (See more on ACM’s SAPS cleaning systems.) TEBO™ advanced wafer cleaning system: for high-aspect-ratio 2D and advanced 3D patterned wafers For advanced wafer cleaning systems, ACM’s Timely Energized Bubble Oscillation (TEBO™) technology provides efficient, damage-free cleaning for both conventional 2D and 3D patterned wafers at advanced process nodes. It enables precise, multi-parameter control of bubble cavitation during megasonic cleaning by using a sequence of rapid pressure changes to force bubbles to oscillate in specific sizes and shapes. And because these bubbles oscillate instead of imploding or collapsing, TEBO technology avoids the pattern damage caused by the transient cavitation that is seen in traditional megasonic cleaning. ACM has already demonstrated TEBO’s damage-free cleaning capabilities on patterned wafers as small as 1xnm (16nm to 19nm), and the technology looks extremely promising for even smaller process nodes. TEBO technology is designed for efficient, damage-free cleaning of patterned chips with 3D structures such as FinFET, DRAM, 3D NAND and 3D cross point memory, even devices with very high aspect ratios. (See more on ACM’s TEBO cleaning systems.) A comprehensive portfolio of advanced systems for front end IC manufacturing ACM is a market leader in advanced technology development to support a wide variety of front end semiconductor manufacturing applications. Learn more about how we support today’s—and tomorrow’s—manufacturing requirements: Tahoe Cleaning Systems Backside Cleaning Systems Wet Bench Cleaning Systems Scrubber Systems Dual Damascene Electroplating Systems TSV Electroplating Systems Furnace Systems Contact us to learn more about how ACM can support your manufacturing needs. Interested in Technologies? Contact Us News © 2021 ACM Research, Inc.. All rights reserved.