Technology Patents The Core of Atomera’s IP Portfolio Atomera is a technology licensing company, so our patents are a fundamental building block of our business. We partner with customers through licensing arrangements, providing them access to our patents and proprietary know-how to enable integration of our MST® technology into their semiconductor manufacturing processes. Below is a list of our issued US patents. We also hold foreign counterparts in all the major jurisdictions where our customers, prospects and partners do business, and have a number of patents pending. [#7071119] - A Method for Making a Semiconductor Device Including Band-engineered Superlattice Having 3/1-5/1 Germanium Layer Structure [#10355151] - CMOS Image Sensor Including Photodiodes With Overlying Superlattices To Reduce Crosstalk [#10529757] - CMOS Image Sensor Including Pixels With Read Circuitry Having A Superlattice [#10367028] - CMOS Image Sensor Including Stacked Semiconductor Chips And Image Processing Circuitry Including A Superlattice [#10615209] - CMOS Image Sensor Including Stacked Semiconductor Chips And Readout Circuitry Including A Superlattice [#10276625] - CMOS Image Sensor Including Superlattice To Enhance Infrared Light Absorption [#10304881] - CMOS Image Sensor With Buried Superlattice Layer To Reduce Crosstalk [#7123792] - Configurable Aperiodic Grating Device [#10109342] - Dram Architecture to Reduce Row Activation Circuitry Power And Peripheral Leakage [#10367064] - DRAM With Recessed Channel Array Transistor (RCAT) Including A Superlattice And Related Methods [#7446334] - Electronic Device Comprising Active Optical Devices with an Energy Band Engineered Superlattice [#6741624] - Fabry-Perot Laser with Wavelength Control [#7202494] - FinFET Including a Superlattice [#10580867] - FinFET Including Source And Drain Regions With Dopant Diffusion Blocking Superlattice Layers To Reduce Contact Resistance [#7279699] - Integrated Circuit Comprising a Waveguide Having an Energy Band Engineered Superlattice [#7432524] - Integrated Circuit Comprising an Active Optical Device Having an Energy Band Engineered Superlattice [#10763370] - Inverted T Channel Field Effect Transistor (ITFET) Including A Superlattice [#10840337] - Method For Making A FinFET Having Reduced Contact Resistance [#10854717] - Method For Making A FinFET Including Source And Drain Dopant Diffusion Blocking Superlattices To Reduce Contact Resistance [#7700447] - Method for Making a Semiconductor Device Comprising a Lattice Matching Layer [#7018900] - Method for Making a Semiconductor Device Comprising a Superlattice Channel Vertically Stepped above Source and Drain Regions [#7446002] - Method for Making a Semiconductor Device Comprising a Superlattice Dielectric Interface Layer [#10879357] - Method For Making A Semiconductor Device Having A Hyper-Abrupt Junction Region Including A Superlattice [#7491587] - Method for Making a Semiconductor Device Having a Semiconductor-On-Insulator (SOI) Configuration And Including a Superlattice on a Thin Semiconductor Layer [#10593761] - Method For Making A Semiconductor Device Having Reduced Contact Resistance [#7265002] - Method for Making a Semiconductor Device Including a MOSFET Having a Band-engineered Superlattice with a Semiconductor Cap Layer Providing a Channel [#10249745] - Method For Making A Semiconductor Device Including A Resonant Tunneling Diode Structure Having A Superlattice [#10170604] - Method For Making A Semiconductor Device Including A Resonant Tunneling Diode With Electron Mean Free Path Control Layers [#11094818] -Method for making a semiconductor device including a superlattice and an asymmetric channel and related methods [#11075078] -Method for making a semiconductor device including a superlattice within a recessed etch [#7045377] - Method for Making a Semiconductor Device Including a Superlattice and Adjacent Semiconductor Layer With Doped Regions Defining a Semiconductor Junction [#7229902] - Method for Making a Semiconductor Device Including a Superlattice With Regions Defining a Semiconductor Junction [#7153763] - Method for Making a Semiconductor Device Including Band-engineered Superlattice Using Intermediate Annealing [#10727049] - Method For Making A Semiconductor Device Including Compound Semiconductor Materials And An Impurity And Point Defect Blocking Superlattice [#10879356] - Method For Making A Semiconductor Device Including Enhanced Contact Structures Having A Superlattice [#10741436] - Method For Making A Semiconductor Device Including Non-Monocrystalline Stringer Adjacent A Superlattice-STI Interface [#7535041] - Method for Making a Semiconductor Device Including Regions of Band-Engineered Semiconductor Superlattice to Reduce Device-On Resistance [#7812339] - Method for Making a Semiconductor Device Including Shallow trench isolation (STI) regions with maskless superlattice deposition following STI formation and related structures [#7514328] - Method for Making a Semiconductor Device Including Shallow Trench Isolation (STI) Regions with a Superlattice Therebetween [#10191105] - Method For Making A Semiconductor Device Including Threshold Voltage Measurement Circuitry [#10937888] - Method For Making A Varactor With A Hyper-Abrupt Junction Region Including Spaced-Apart Superlattices [#10868120] - Method For Making A Varactor With Hyper-Abrupt Junction Region Including A Superlattice [#7517702] - Method for Making an Electronic Device Including a Poled Superlattice Having a Net Electrical Dipole Moment [#7109052] - Method for Making an Integrated Circuit Comprising a Waveguide Having an Energy Band Engineered Superlattice [#10461118] - Method for Making CMOS Image Sensor Including Photodiodes With Overlying Superlattices to Reduce Crosstalk [#10529768] - Method For Making Cmos Image Sensor Including Pixels With Read Circuitry Having A Superlattice [#10608027] - Method For Making CMOS Image Sensor Including Stacked Semiconductor Chips And Image Processing Circuitry Including A Superlattice [#10608043] - Method For Making Cmos Image Sensor Including Stacked Semiconductor Chips And Readout Circuitry Including A Superlattice [#10361243] - Method For Making CMOS Image Sensor Including Superlattice To Enhance Infrared Light Absorption [#10396223] - Method For Making Cmos Image Sensor With Buried Superlattice Layer To Reduce Crosstalk [#10636879] - Method For Making Dram With Recessed Channel Array Transistor (RCAT) Including A Superlattice [#9721790] - Method for Making Enhanced Semiconductor Structures in Single Wafer Processing Chamber with Desired Uniformity Control [#7288457] - Method for Making Semiconductor Device Comprising a Superlattice with Upper Portions Extending above Adjacent Upper Portions of Source and Drain Regions [#6830964] - Method for Making Semiconductor Device Including Band-engineered Superlattice [#6878576] - Method for Making Semiconductor Device Including Band-engineered Superlattice [#6833294] - Method for Making Semiconductor Device Including Band-engineered Superlattice [#7033437] - Method for Making Semiconductor Device Including Band-engineered Superlattice [#10840335] - Method For Making Semiconductor Device Including Body Contact Dopant Diffusion Blocking Superlattice To Reduce Contact Resistance [#10818755] - Method For Making Semiconductor Device Including Source/Drain Dopant Diffusion Blocking Superlattices To Reduce Contact Resistance [#10937868] - Method For Making Semiconductor Devices With Hyper-Abrupt Junction Region Including Spaced-Apart Superlattices [#10811498] - Method For Making Superlattice Structures With Reduced Defect Densities [#10381242] - Method of a Semiconductor wafer including a Superlattice as a Gettering layer and related methods [#7863066] - Method of Making a Multiple-Wavelength Opto-electronic Device Including a Superlattice [#10109479] - Method Of Making A Semiconductor Device With A Buried Insulating Layer Formed By Annealing A Superlattice [#9558939] - Methods for Making a Semiconductor Device Including Atomic Layer Structures Using N2O as an Oxygen Source [#7625767] - Methods of Making Spintronic Devices With Constrained Spintronic Dopant [#7586165] - Microelectromechanical Systems (MEMS) Device Including a Superlattice [#7880161] - Multiple-Wavelength Opto-electronic Device Including a Superlattice [#8389974] - Multiple-Wavelength Opto-electronic Device Including a Superlattice [#6993222] - Optical Filter Device with Aperiodically Arranged Grating Elements [#7718996] - Semiconductor Device Comprising a Lattice Matching Layer [#7436026] - Semiconductor Device Comprising a Superlattice Channel Vertically Stepped above Source and Drain Regions [#7279701] - Semiconductor Device Comprising a Superlattice with Upper Portions Extending above Adjacent Upper Portions of Source and Drain Regions [#7586116] - Semiconductor Device Having a Semiconductor-on-insulator Configuration and a Superlattice [#7659539] - Semiconductor Device Including a Floating Gate Memory Cell with a Superlattice Channel [#7531850] - Semiconductor Device Including a Memory Cell with Negative Differential Resistance (NDR) Device [#7928425] - Semiconductor Device Including a Metal-to-Semiconductor Superlattice Interface Layer and Related Methods [#7435988] - Semiconductor Device Including a MOSFET Having a Band-engineered Superlattice with a Semiconductor Cap Layer Providing a Channel [#10170603] - Semiconductor Device Including A Resonant Tunneling Diode Structure With Electron Mean Free Path Control Layers [#7598515] - Semiconductor Device Including a Strained Superlattice and Overlying Stress Layer and Related Methods [#7531828] - Semiconductor Device Including a Strained Superlattice Between at Least One Pair of Spaced Apart Stress Regions [#7612366] - Semiconductor Device Including a Strained Superlattice Layer Above a Stress Layer [#7227174] - Semiconductor Device Including a Superlattice and Adjacent Semiconductor Layer With Doped Regions Defining a Semiconductor Junction [#9722046] - Semiconductor Device Including a Superlattice and Replacement Metal Gate Structure and Related Methods [#10084045] - Semiconductor Device Including a Superlattice and Replacement Metal Gate Structure and Related Methods [#10410880] - Semiconductor Device Including A Superlattice As A Gettering Layer [#7045813] - Semiconductor Device Including a Superlattice With Regions Defining a Semiconductor Junction [#7034329] - Semiconductor Device Including Band-engineered Superlattice Having 3/1-5/1 Germanium Layer Structure [#6958486] - Semiconductor Device Including Band-engineered Superlattice [#6891188] - Semiconductor Device Including Band-engineered Superlattice [#6952018] - Semiconductor Device Including Band-engineered Superlattice [#6927413] - Semiconductor Device Including Band-engineered Superlattice [#10847618] - Semiconductor Device Including Body Contact Dopant Diffusion Blocking Superlattice Having Reduced Contact Resistance [#10468245] - Semiconductor Device Including Compound Semiconductor Materials And An Impurity And Point Defect Blocking Superlattice [#10777451] - Semiconductor Device Including Enhanced Contact Structures Having A Superlattice [#7303948] - Semiconductor Device Including MOSFET Having Band-Engineered Superlattice [#6897472] - Semiconductor Device Including MOSFET Having Band-engineered Superlattice [#7531829] - Semiconductor Device Including Regions of Band-Engineered Semiconductor Superlattice to Reduce Device-On Resistance [#10453945] - Semiconductor Device Including Resonant Tunneling Diode Structure Having A Superlattice [#10580866] - Semiconductor Device Including Source/Drain Dopant Diffusion Blocking Superlattices To Reduce Contact Resistance [#10566191] - Semiconductor Device Including Superlattice Structures With Reduced Defect Densities [#10107854] - Semiconductor Device Including Threshold Voltage Measurement Circuitry [#10884185] - Semiconductor Device Including Vertically Integrated Optical And Electronic Devices And Comprising A Superlattice [#7781827] - Semiconductor Device with a Vertical Mosfet Including a Superlattice and Related Methods [#10840336] - Semiconductor Device With Metal-Semiconductor Contacts Including Oxygen Insertion Layer To Constrain Dopants And Related Methods [#10825901] - Semiconductor Devices Including Hyper-Abrupt Junction Region Including A Superlattice [#9406753] - Semiconductor Devices Including Superlattice Depletion Layer Stack and Related Methods [#9716147] - Semiconductor Devices with Enhanced Deterministic Doping and Related Methods [#10170560] - Semiconductor Devices with Enhanced Deterministic Doping and Related Methods [#9941359] - Semiconductor Devices with Superlattice and Punch through Stop (PTS) Layers at Different Depths and Related Methods [#9899479] - Semiconductor Devices with Superlattice Layers Providing Halo Implant Peak Confinement and Related Methods [#10840388] - Varactor With Hyper-Abrupt Junction Region Including A Superlattice [#10825902] - Varactor With Hyper-Abrupt Junction Region Including Spaced-Apart Superlattices [#9972685] - Vertical Semiconductor Devices Including Superlattice Punch Through Stop Layer and Related Methods [#9275996] - Vertical Semiconductor Devices Including Superlattice Punch Through Stop Layer and Related Methods [#6141361] - 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