Silicon Drafting Institute (SDI) HOME COURSE OUTLINE SCHEDULE QUALITY JOB PLACEMENT TUITION TESTIMONIALS CADENCE PHOTOS CONTACT US The following are the ALL topics that will be covered in this 32 week program. CMOS/BiCMOS Circuit Theories Transistor, schematic, logic & complex logic fundamentals Truth table, boolean equations & timing diagram concepts Resistance, capacitance and inductance theories and calculations in layout Theories on parasitic R&C, and the RC delay concept CMOS IC power dissipation 0.1um 5-layer metal BiCMOS process sequence and theories Bipolar transistor fundamentals BiCMOS circuit fundamentals Analog circuit and device matching theories Clock circuit & clock skew issues Antenna issue Latch-up theory & prevention High voltage circuit theory HSPICE netlist fundamentals I/O circuit, noise and ground bounce theories IC design methodology and terminology IC packaging and bonding techniques Layout Techniques Use industrial advanced 0.1um 5-layer metal mixed-signal BiCMOS technology to complete our class layout project (entire chip) Layout techniques on devices: CMOS transistors, bipolar transistors, resistors, capacitors, and diodes Transistors in series and parallel. Finger & bend gates Stick diagrams, strapping and guard-ring techniques Advanced digital and analog mixed-signal layout techniques High speed layout techniques High voltage, HVMOS, LDD MOS & DMOS layout techniques Various inductor layouts in RF circuits Introduction to FinFET and its device & layout structures Latch-up prevention techniques Reverse engineering techniques ESD and peripheral output driver and I/O cell layout techniques Placement and routing techniques Chip floor-planning techniques Bonding pad, seal-ring, scribe-line layout techniques Power bus routing, bus slotting, and clock net routing techniques Final project: "Digital/Analog mixed-signal BiCMOS transceiver" chip (each student completes his/her own chip)﻿ Cadence Opus Software Training All students will use Cadence Software for ALL the classwork Each student will have his/her own workstation to do the class project from START to FINISH (All 8 months) The following Cadence Software tools will be used for his/her ENTIRE class projects - Virtuoso Layout Editor (VLE) - Virtuoso - XL layout editor (a schematic driven layout editor) - Assura and Diva LVS/DRC/SCHECK physical verification & extraction software - Dracula LVS / DRC physical verification & extraction software - Cadence Chip Assembly Router (CCAR) - Advanced place & route and chip floor-planning tools - Virtuoso schematic composer - Import / Export / stream-out / stream-in tools Linux Training All Cadence tools run on Linux Operation System (OS) from Red Hat. Linux Commands Linux vi(m) editor COURSE INFORMATION Total length = 8 Months Total Weeks = 32 weeks Total Lecture Hours = 256 hours Total Lab Hours = 512 hours IC 100 Introduction to CMOS IC layout (2 months): Basic theories, concepts, layouts and tools 64 Lecture Hours & aprox. 128 lab Hours (24 total hours/week) Basic and complex logic conversion techniques Stick diagrams and standard cell layouts, design rules Finger and bend gate layout techniques Transistor width/length, strength and current IDs Concepts of PN junctions, taps, guard rings and bulk connections Units of measurements: nm, µm, Å and mil Cadence Virtuoso Layout Editor (VLE) Stream-out & Stream-in in VLE Cadence Assura DRC verification & extraction software IC 200 Intermediate level BiCMOS IC layout (3 months): Custom block layout & planning and IC Manufacturing 96 Lecture Hours & approx. 192 lab Hours (24 total hours/week) Full custom layouts of various digital circuit blocks Cell/block planning techniques Logic functions, truth table, boolean equations & timing diagrams Sequential logics and IC design flow CMOS fabrication procedures, and sequence of integrated circuit layer processing. Device cross-sectional views Resistance, capacitance & inductance theories & calculations, and layouts of various resistors and capacitors Parasitic R & C in layout and related issues, RC delay and time constant High speed layout techniques Concepts of balanced clock tree routing, clock delay and clock skew reduction Antenna issue and various solutions Reverse Engineering techniques Cadence Assura LVS verification & extraction software Cadence Assura soft-connection check software Cadence PCELL utility software IC 300 Advanced BiCMOS mixed-signal IC layout (3 months): Chip-floor planning and Cadence Place & Route tools. 96 Lecture Hours & approx. 192 lab Hours. (24 total hours/week) Full custom layouts of various analog and mixed-signal blocks Advanced analog layout techniques: device matching techniques and various Noise reduction techniques: ground bounce, cross-talk and substrate noise Theory on inductance and layouts of various inductors in RF circuits ESD and peripheral device (I/O cell) layouts Latch-up theory and its prevention SPICE netlist fundamentals Theories on IC power consumption, IC packaging and bonding techniques Chip floor-planning, power rail bussing techniques Bus slotting technique and electro-migration issue and solutions Bipolar junction transistor fundamentals and layouts of various NPN, PNP and diodes in BiCMOS technology finFET fundamentals and sample layouts with finFETs Final chip layout of a mixed-signal transceiver project Cadence Virtuoso XL Layout Editor (VXL) Cadence Virtuoso schematic composer Cadence Dracula DRC/LVS physical design verification software Cadence Chip Assembly Router (CCAR) ﻿ After the successful completion of this course, a CERTIFICATE will be issued to the students. Other School Information School Catalog School Performance Fact Sheet Brochure School Annual Report Link to the BPPE: Bureau for Private Postsecondary Education Silicon Drafting Institute's school code # 4305771 Silicon Drafting Institute 1879 Lundy Avenue, Suite 189 San Jose, CA 95131 | +1 (408) 828-2323 Copyright 2020 Silicon Drafting Institute. All rights reserved.