Specman Fundamentals for Block-Level Environment Developers Enroll Online Subscription Online Courses Instructor-Led Schedule Length : 5 days Course Description In this course, you learn how to create a reusable block-level verification environment with the e language for the Xcelium™ simulator. The course provides an introduction to the e language and the Coverage-Driven Verification (CDV) methodology. The reusable verification environment is built using the industry-standard Universal Verification Methodology (UVM-e). Learning Objectives After completing this course, you will be able to: Describe the differences between Coverage-Driven Verification (CDV) and directed tests Create reusable verification components (UVCs) that comply with the UVM methodology Control stimulus generation using sequences, virtual sequences, and the built-in sequence API Write and debug regular methods and time consuming methods (TCMs) Use Specman® and SimVision™ debugging features Define, collect, and analyze functional coverage information Use scoreboarding and assertions to perform data and timing checks Implement the end of test and reset methodologies Software Used in This Course Xcelium Single-Core Software Release(s) XCELIUM1710 Modules in this Course Introduction to Coverage-Driven Verification (CDV) e Language Basics Generation When Inheritance (AOP Inheritance) Connecting and Interacting with the DUT Checking DUT Behavior Developing Coverage Development of an Interface UVM Verification Component Developing Sequences Development of Module/Sub-System UVM Verification Components Handling Reset and End-Of-Test Audience Design and Verification Engineers Prerequisites You must have experience with or knowledge of the following: Any Object-Oriented Language, such as C++, C#, SystemVerilog for Testbenches, Java or Python Related Courses Specman Advanced Verification Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here. Course ID: 85034 CONTACT TRAINING INSTRUCTIONAL VIDEOS Training Bytes Log into Cadence Online Support to watch our short videos to explore an element of a language, make sense of a methodology, or learn how to do a task VIEW NOW “The training has helped me to get a better understanding on how to make the verification environment more structured. The pace was good. All the labs were effective.” Sindhu Joseph, Intel Tools System Design and Verification Digital Design and Signoff Custom IC / Analog / RF Design IC Package Design and Analysis PCB Design and Analysis Tools A-Z IP Tensilica Processors Interface IP Denali Memory IP Analog IP Systems/Peripheral IP Verification IP Support Online Support Training Software Downloads University Software Program Resource Library News Press Releases Newsroom Blogs Forums Company Cadence Overview Investor Relations Alliances Executive Team Events Careers A Great Place to Do Great Work! Fourth year on the FORTUNE 100 list Our Culture Join the Team Contact Us General Inquiry Customer Support Media Relations Global Office Locator Subscribe to Monthly Newsletter Email * Worldwide Terms of Use Privacy Policy US Trademarks © 2018 Cadence Design Systems, Inc. All Rights Reserved. Connect with Us Please see our Privacy Policy to learn more about how we use cookies and how to change your settings if you do not want cookies on your computer. By continuing to use this site without changing your cookies settings, you consent to the use of our cookies. Accept and close X