Log In|Register|Resource Library|Worldwide ToolsIPSolutionsServicesSupport and TrainingAlliancesCommunityCompany Home > About Cadence > Customer Success > Customer Success Videos Customer Success Videos Latest Success Videos By Category Select Category All System Design and Verification Functional Verification Logic Design Digital Implementation Custom IC Design RF Design PCB Design IC Packaging and SiP Design Manufacturability Signoff Advanced Node Low-Power Analog/Mixed-signal Design Mixed-Signal System Development Enterprise Verification Alliances Services Design Support Thomas Moerth Design Support Engineers at ams AG were frustrated at how long it was taking to verify their mixed-signal designs. If there wasn't enough time in the schedule, the trade-off was to not verify everything, but risk having chips that didn't work as expected. Knowing that they had reached their limits with the hardware, the ams team turned to software for an answer. In this short video, Thomas Moerth, the company's manager of Design Support, Full-Service Foundry, talks about how Cadence® Virtuoso® AMS Designer helped ams complete 2X the number of simulations as was previously possible and how Cadence Spectre® Extensive Partitioning Simulator helped boost simulation speed by 10X. Watch Video » STMicroelectronics Samuele Raffaelli STMicroelectronics Samuele Raffaelli, a digital designer at STMicroelectronics, talks about how he and his team used, as a first step in verification, a formal verification methodology based on Cadence's Incisive® Formal Verifier and Incisive Enterprise Verifier for "exhaustive verification of the RTL." Watch the video to learn how the team reduced its verification time from 12 to 8 weeks. Watch Video » Test and Verification Solutions Mike Bartley Test and Verification Solutions What do you do when you've got an SoC verification project involving a testbench with a mix of different languages? In this 1.5-minute clip, Mike Bartley, CEO of Test and Verification Solutions, talks about how using open-source UVM-ML has allowed his team to reuse its legacy multi-language verification environment in a new UVM testbench environment. The team was able to wrap its Cadence® Incisive® Enterprise Specman Elite® Testbench in a UVM framework. Watch Video » Dialog Semiconductor Steven Holloway Dialog Semiconductor In this video from CDNLive EMEA 2014, Steven Holloway, Principal Verification Engineer of Dialog Semiconductor, discusses how he needed to successfully verify the register map in his parametric projects, while working around complex access policies, rapidly changing specifications, and the need to complete verification in an overnight regression run. Using Cadence's RegVal formal app flow, Holloway was able to automatically generate properties based on specifications, allowing him to run a validation regression on all 900 registers on the chip in six hours of CPU time and quickly debug any problems, all with less set-up time than it would take to put together a test bench. Watch Video » Methods2Business Marleen Boonen Methods2Business In this video from CDNLive EMEA 2014, Marleen Boonen, CEO and Founder of Methods2Business, discusses the company's need to build MAC layers for Wi-Fi 802.11n standards to get to market quickly without compromising on verification. Using the Cadence® C-to-Silicon Compiler's High-Level Synthesis Technology and Unified SystemC Modeling Methodology for high-level synthesis, virtual prototyping, and all verification, Methods2Business built not just working IP, but a MAC layer that is highly customizable in terms of power, performance, area, and functionality. Watch Video » Test and Verification Solutions Mike Bartley Test and Verification Solutions An SoC developer needed to speed up the time for verifying the DDR memory controller in its SoC. Mike Bartley, CEO of Test and Verification Solutions, found a faster way to do this by building a testbench with Denali™ memory models and using automated testbench generation via Cadence's Incisive® Enterprise Specman Elite® Testbench. Watch this 3-minute video to hear Mike explain how these tools helped save 50% of the effort on the 4-month project. Watch Video » Freescale Semiconductor Amitesh Khandelwal Freescale Semiconductor In this video, Amitesh Khandelwal, a Freescale Semiconductor design manager working on verification and validation domains, talks about the different challenges his organization faces in its SoC environments, from the lack of synergy and reuse to gaps in coverage in its test cases. With the Palladium XP platform, Freescale has gained critical coverage of the gap as well as a solution to quickly find critical bugs. Watch Video » Dialog Semiconductor Rajesh Aiyandra Dialog Semiconductor Dialog Semiconductor faced a potentially daunting challenge: reduce the size and cost of its PCBs via embedded passive devices at the substrate level. The company needed a tool that could help migrate from a two-layer BGA substrate to four layers. Rajesh Aiyandra, package design and simulation team leader at Dialog, explains how Cadence SiP Digital Layout helped deliver a smooth migration, from the change in the number of layers to the change in the via specifications. Watch Video » IBM Sangtae Bae IBM Transistor-Level Reliability Analysis for Advanced Node Description: Sangtae Bae, an analog/mixed-signal circuit designer at IBM, designs high-speed interfaces for IBM's server chips. Bae and his team needed a method to verify circuits will operate in silicon, reliably well over expected life of products. In this 4-minute video, Bae explains how reliability simulation in Cadence® Spectre® Accelerated Parallel Simulator (APS) ran from Cadence Virtuoso® Analog Design Environment (ADE) helped IBM perform reliability analysis efficiently and get to market faster with its server chips. Watch Video » ARM Rob Kaye ARM Rob Kaye, a technical specialist at ARM, covers the advantages of using ARM® Fast Models with Cadence's Palladium® XP verification computing platform and Virtual System Platform in a hybrid use model. With a hybrid approach, you can achieve as much as 60X faster OS boot up over emulation and execute test cases up to 10X faster. Watch the video to learn about other benefits. Watch Video » Next » About Cadence| Investor Relations| Careers| Terms of Use| Privacy Policy| US Trademarks © Cadence Design Systems, Inc. All Rights Reserved.