Functional Safety Reduce your ISO26262 compliance effort by 50% Advanced Driver Assistance System Automotive Ethernet Infotainment Electronic Control Unit Functional Safety From staying up-to-date on the latest standards to managing all of the associated data, complying with functional safety requirements has traditionally been a time-consuming, manual effort. Cadence is transforming this process by automating fault injection and result analysis for intellectual property (IP), system-on-chip (SoC), and system designs. Built on the proven Cadence® Incisive® verification platform, our end-to-end functional safety solution reduces the automotive ISO 26262 compliance effort by 50%. The solution is available as part of the Cadence System Development Suite. Safety Analysis to Measure Continuous Operation Meeting functional safety requirements calls for: Checkers, which monitor the systems and trigger error recovery features when necessary Redundancy, which provides continuous function in the event of errors For their part, safety engineers must implement requirements tracing from the system to components, and ensure that their development flow aligns with tool confidence level (TCL). Functional verification should take place at all levels of abstraction and for all system elements. Safety verification, which measures response of systems to undesired/unplanned events, is another critical step. Finally, to be in full compliance, safety engineers must record and report on all functional safety measures. Built on Proven Incisive Platform Fulfilling the traceability, safety verification, and TCL requirements of ISO 26262, Cadence’s functional safety solution includes Incisive Functional Safety Simulator and a functional safety analysis capability in the Incisive vManager™ solution. Incisive Functional Safety Simulator delivers: Seamless reuse of functional and mixed-signal verification environments to accelerate the time to develop safety verification Fault identification during elaboration Reuse of the existing functional verification environment (with support for SystemVerilog, Universal Verification Methodology (UVM), and e) Simulation of the unaltered design under test (DUT) Support for multiple fault types, including single event upset (SEU), stuck-at-0/stuck-at-1, and single event transient The functional safety analysis capability in the Incisive vManager solution: Automatically generates a safety verification plan from the fault dictionary created by the simulator. The Incisive vManager solution can then track millions of detected, partially detected, and undetected faults introduced into simulation to verify the safety systems in a design. Highlights potential and undetected fault runs for further debugging Cadence will continue to expand its functional safety solution to encompass additional hardware, software, and IP components. Related Products Incisive vManager White Paper At SAE Convergence 2014, Cadence announced a new functional safety solution, built on the Incisive verification platform, that reduces the automotive ISO 26262 compliance effort by half. In this Whiteboard Wednesdays video, Charles Qi talks about automotive functional safety and reliability standards and their importance to the automobile industry and to IP and software developers. Videos Cadence Functional Safety Solution Integrating Chip Verification into an ISO2626 Flow Automotive Functional Safety and Reliability Requirements News Releases VIEW ALL Cadence Debuts PSpice Web Portal and Ecosystem to Help Designers Address System Level Mixed-Signal Wireless and IoT Challenges 06/22/2016 Uurmi Fog Removal Software Now Available on Cadence Tensilica Vision DSPs 05/16/2016 Cypress Adopts Cadence Digital Implementation and Circuit Simulation Tools for 40nm Automotive Designs 05/10/2016 Cadence Announces New Tensilica Vision P6 DSP Targeting Embedded Neural Network Applications 05/02/2016 Building the Car of the Future Today-Cadence Showcases Automotive Solutions at embedded world 2016 02/08/2016 Blogs VIEW ALL Tools System Design and Verification Digital Design and Signoff Custom IC / Analog / RF Design IC Package Design and Analysis PCB Design and Analysis Tools A-Z IP Tensilica Processors Interface IP Denali Memory IP Analog IP Systems/Peripheral IP Verification IP Support Online Support Training Software Downloads University Software Program Resource Library News Press Releases Newsroom Blogs Forums Company Cadence Overview Investor Relations Alliances Executive Team Events Careers A Great Place to Do Great Work! Second year on the FORTUNE 100 list Our Culture Join the Team Contact Us General Inquiry Customer Support Media Relations Global Office Locator Subscribe to Monthly Newsletter Email * Worldwide Terms of Use Privacy Policy US Trademarks © 2016 Cadence Design Systems, Inc. All Rights Reserved. Connect with Us