PCI Express 5.0 - Comprehensive 5-Day Course View all Public Courses All Available Public Courses PCI Express 5.0 - Comprehensive 5-Day Course (9am-5pm PST (California Time): 11/29/2021) PCI Express - Fundamentals 1-Day Course (9am-5pm PST (California Time): 11/29/2021) USB4 - Comprehensive 4-Day Course (9am-5pm PST (California Time): 11/30/2021) USB4 - Fundamentals 1-Day Course (9am-5pm PST (California Time): 11/30/2021) Compute Express Link (CXL) 2.0 - Comprehensive 4-Day Course (9am-5pm PST (California Time): 12/7/2021) Compute Express Link (CXL) - Fundamentals 1-Day Course (9am-5pm PST (California Time): 12/7/2021) DRAM (DDR5/LPDDR5) - Comprehensive 4-Day Course (9am-5pm PST (California Time): 12/7/2021) DRAM (DDRx/LPDDRx) - Fundamentals 1-Day Course (9am-5pm PST (California Time): 12/7/2021) DRAM (DDR5/LPDDR5) - Comprehensive 4-day Course (9am-5pm US Pacific Time: 3/8/2022) DRAM (DDRx/LPDDRx) - Fundamentals 1-Day Course (9am-5pm US Pacific Time: 3/8/2022) PCI Express 5.0 - Comprehensive 5-Day Course (9am-5pm US Pacific Time: 3/21/2022) PCI Express - Fundamentals 1-Day Course (9am-5pm US Pacific Time: 3/21/2022) Compute Express Link (CXL) 2.0 - Comprehensive 4-Day Course (9am-5pm US Pacific Time: 3/29/2022) Compute Express Link (CXL) - Fundamentals 1-Day Course (9am-5pm US Pacific Time: 3/29/2022) USB4 - Comprehensive 4-Day Course (9am-5pm US Pacific Time: 3/29/2022) USB4 - Fundamentals 1-Day Course (9am-5pm US Pacific Time: 3/29/2022) PCI Express 5.0 - Comprehensive 5-Day Course Location 9am-5pm PST (California Time) Date 11/29/2021 - 12/3/2021 Duration 5-Days Instructor Mike Jackson Price $2,995.00 Comprehensive PCI Express 5.0 Architecture Course Details: MindShare's PCI Express System Architecture course starts with a high-level view of the technology to provide the big-picture context and then drills down into the details for each topic, providing a thorough understanding of the hardware and software protocols. This course describes additional features added to the architecture when moving from PCIe specification revision 1.1 to 5.0. There is a very large number of features and optional behaviors for PCIe. MindShare will customize this course to cover those features requested by the audience given we cannot cover all topics in the limited training time. You Will Learn: Features of PCIe Gen1, Gen2, Gen3, Gen4, Gen5 The definition and responsibilities of each of the layers in the interface How the hardware-based automatic error detection and correction mechanism works The various additional levels of error detection and reporting The details of the packet-based protocol used by PCIe The address space and packet-routing methods used How the various power management techniques work The details of the configuration registers that provide control and status visibility to software What changes are needed to run the link at 16.0 GT/s (Gen4 speeds) and 32 GT/s (Gen5 speeds) Course Length: 5-Days US Pacific Time Zone Times: Start time each day: 9:00am End time each day: 5:00pm Lunch break between noon-1:00pm Location: Virtual-Classroom Who Should Attend? This in-depth course is hardware oriented, but is designed for both hardware and software engineers. The course contains numerous practical examples of transactions on the link, including relevant analyzer captures of some error conditions. It also covers the rules required for a device to be compliant with the spec. This makes the course ideal for system validation engineers who are evaluating an RTL-level, chip-level, system-level or system board-level design. Course Outline: PCI Architecture Background Foundation PCI concepts important for understanding PCI Express PCI Express Features and Architecture Overview Layered Architecture TLP, DLLP and Ordered Set Packet Format Overview Protocol Overview Configuration Overview Legacy and Enhanced Configuration Access Mechanism (ECAM) Type 0 and Type 1 Headers, Capability and Extended Capability Register Overview Bus Enumeration HANDS-ON ARBOR LAB: Scan your system and determine topology Address Space and Transaction Routing Clarification of Memory space System memory vs MMIO Prefetchable vs Non-prefetchable IO space Setting up the BARs (Base Address Registers) as well as the Base and Limit registers Switch Routing Mechanism HANDS-ON ARBOR LAB: Debug problem with plug-and-play address mapping TLP Format Details Quality of Service and Arbitration Overview Flow Control Overview Transaction Ordering Simplified Ordering Table Relaxed Ordering ID-Based Ordering DLLP Format Details ACK / NAK Protocol Overview TLP Error Recovery Mechanism Examples of Numerous Error Scenarios Nullified Packets and Store-and Forward Switches vs. Cut-Through Mode Switches Physical Layer Logic (2.5GT/s and 5.0GT/s) Ordered Sets Byte Striping/Unstriping Scrambling/Unscambling 8b/10b Encoding/Decoding Serializing/Deserializing Spread Spectrum Clocking (SSC) SRIS (Separate Refclk Independent SSC) Physical Layer Logic (8.0GT/s and 16.0GT/s) 128b/130b Encoding/Decoding Ordered Set Blocks and Data Blocks Data Streams and Packet Framing Physical Layer Electrical (all speeds) Differences Between Speeds 2.5GT/s and 5.0GT/s De-emphasis 8.0GT/s and 16.0GT/s Equalization 16.0GT/s Lane Margining Link Initialization and Training (LTSSM) Detect, Polling, Configuration, L0 States Recovery (Retraining) State Link Speed Change 8.0GT/s Equalization Training 16.0GT/s Equalization Training Link Width Change L0s, L1, L2, Hot Reset, Link Disable and Loopback States Interrupt Support MSI Interrupts MSI-X Interrupts HANDS-ON ARBOR LAB: Investigate source of MSI(-X) interrupt and delivery Error Detection and Handling Correctable, Non-Fatal and Fatal Errors Advisory Non-Fatal Errors Advanced Error Reporting (AER) HANDS-ON ARBOR LAB: Determine source and error reporting mechanism Power Management Overview Device Power States Link Power States Active State Power Management (ASPM) - hardware controlled Software Controlled Power Management Power Management Events (PME, Beacon and #WAKE) Dynamic Power Allocation (DPA), Optimized Buffer Flush Fill (OBFF), Latency Tolerance Reporting (LTR), L1 Sub-States (L1.0, L1.1 and L1.2), Emergency Power Reduction State System Resets Conventional Reset Mechanisms: Cold, Warm and Hot Reset Function Level Reset (FLR) Other Features Introduced with PCIe 2.x and 3.x (select topics covered on class request): Internal Error Reporting Multi-Casting Atomic Operations Resizable BARs Alternative Routing-ID Interpretation (ARI) TLP Processing Hints (TPH) and Steering Tags Downstream Port Containment (DPC) and Enhanced DPC (eDPC) Lightweight Notification (can be used for lightweight cache coherency) Process Address Space ID (PASID) Precision Time Measurement (PTM) Protocol Multiplexing (PMUX) Address Translation Services (ATS) Access Control Services (ACS) Device Readiness Status (DRS) and Function Readiness Status (FRS) Other Features Introduced with PCIe 4.0 (select topics covered on class request): Flattening Portal Bridge (FPB) Enhanced Allocation Hierarchy ID Reporting Support for Retimers Receiver Margining Designated Vendor-Specific Extended Capability (DVSEC) Other Features Introduced with PCIe 5.0 (select topics covered on class request): Negotiation for skipping parts or all of Tx Equalization Alternate Protocol Negotiation System Firmware Intermediary Support Link Activation Recommended Prerequisites: A solid understanding of one or more bus protocols such as PCI or similar architecture is highly recommended but not required. Training Materials: MindShare eBook PCI Express Technology 3.0 by Mike Jackson and Ravi Budruk PDF version of the presentation slides used in class. MindShare Arbor software tool, used for student labs in the class. PCI Express 5.0 eLearning course which can be used to review content covered in class or additional topics not covered in class. PCI Express® is a registered trademark of the PCI-SIG © MindShare, Inc. All rights reserved. Full Course List | About MindShare | Careers with MindShare Contact Us | Privacy Policy | Terms of Use