Virtuoso ADE Explorer S1: Set Up and Run Analog Simulations Using the Spectre Simulator Instructor-Led Schedule Course Description This course is taught as half day session (4 hours) This course introduces you to the maestro cellview in IC 617 and the Virtuoso ADE Explorer tool that uses it. You set up and run simulations on analog designs. You use design variables in your setup, sweep system parameters and run simulations on a single testbench, using Spectre as the simulator, and view results in the ViVA XL waveform viewer. This course is part of the Virtuoso ADE Explorer Series of courses: Virtuoso ADE Explorer S1: Set Up and Run Analog Simulations Using the Spectre Simulator Virtuoso ADE Explorer S2: Analyzing Simulations Using the ViVA XL Waveform Tool Virtuoso ADE Explorer S3: Corner Analysis and Monte Carlo Simulations Virtuoso ADE Explorer S4: Real-Time Tuning, Checks/Asserts, and Reliability Analysis Learning Objectives After completing this course, you will be able to: Start the Virtuoso ADE Explorer tool and create maestro cellviews in IC 617. Set up varied analysis (dc, ac, transient) on a single test. Work with design variables and device parameters. Run simulations using the Spectre simulator. Display simulation results in the Virtuoso Visualization and Analysis (ViVA) XL waveform window. Software Used in This Course Virtuoso Schematic Editor Virtuoso ADE Explorer Virtuoso Visualization & Analysis XL Virtuoso ADE Assembler Software Release(s) IC 6.1.7 ISR4, MMSIM 15.1 Course Agenda Day 1 About This Course The Virtuoso Design Environment (Optional) Introducing the Virtuoso ADE Explorer Analog Simulation Setup and Details Audience Analog/Mixed-Signal Design Engineers Prerequisites You must have experience with or knowledge of the following: Analog/mixed signal design concepts Analyzing design schematics Related Courses Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here. Course ID: 86184 CONTACT TRAINING View Learning Map Download Training Brochure Tools System Design and Verification Digital Design and Signoff Custom IC / Analog / RF Design IC Package Design and Analysis PCB Design and Analysis Tools A-Z IP Tensilica Processors Interface IP Denali Memory IP Analog IP Systems/Peripheral IP Verification IP Support Online Support Training Software Downloads University Software Program Resource Library News Press Releases Newsroom Blogs Forums Company Cadence Overview Investor Relations Alliances Executive Team Events Careers A Great Place to Do Great Work! Second year on the FORTUNE 100 list Our Culture Join the Team Subscribe to Monthly Newsletter Email * Contact Us General Inquiry Customer Support Media Relations Global Office Locator A Great Place to Do Great Work! Second year on the FORTUNE 100 list Our Culture Join the Team Subscribe to Monthly Newsletter Email * Worldwide Terms of Use Privacy Policy US Trademarks © 2016 Cadence Design Systems, Inc. All Rights Reserved. Connect with Us