Low-Power Synthesis Flow with Encounter RTL Compiler (Libraries not included) Enroll Online Subscription Online Courses Instructor-Led Schedule Course Description This is an Engineer Explorer course for designers familiar with synthesis using Encounter® RTL Compiler. In this course, you explore and implement several low-power techniques to reduce both dynamic and leakage power during synthesis. You use multiple supply voltage (MSV) design, power shutoff (PSO) synthesis and dynamic voltage frequency scaling (DVFS)synthesis. You run low-power flow using CPF and IEEE-1801 and troubleshoot a low-power design. You apply formal verification to validate your power constraints and ensure the functionality of a low-power design. Special authorization is required to enroll in this online course. Learning Objectives After completing this course, you will be able to: Explore power reduction techniques Run low-power synthesis Enable clock gating and operand isolation Annotate switching activity and run RTL power estimation Run optimizations to reduce dynamic and leakage power consumption Implement a power shutoff (PSO), dynamic frequency voltage scaling (DVFS) and multiple supply voltage (MSV) design using the common power format (CPF) Use IEEE-1801 for designs with MSV and PSO methodology Analyze power results Troubleshoot low-power design Check a low-power design with Encounter Conformal® software Software Used in This Course Encounter Conformal Low Power XL Encounter RTL Compiler XL Software Release(s) RTL Compiler 14.1, Conformal 14.1 Modules in this Course Overview of the low-power implementation solution Power reduction Low-power synthesis flow Dynamic and leakage power optimization Multi-supply voltage design and power shutoff synthesis Low-power flow with common power format IEEE-1801 for designs with MSV and PSO methodology Troubleshooting low-power design Low-power analysis Checking a low-power design with Encounter Conformal software Audience ASIC Designers Chip Designers Digital IC Designers Prerequisites You must have experience with or knowledge of: Synthesis Encounter® RTL Compiler System Requirements for Online Courses For system requirements click here Cadence software as listed above installed and licensed Related Courses Encounter RTL Compiler Low-Power Verification with Encounter Conformal Click here to view course learning maps, and here for complete course catalogs. Course ID: 86055 CONTACT TRAINING View Learning Map Download Training Brochure Tools System Design and Verification Digital Design and Signoff Custom IC / Analog / RF Design IC Package Design and Analysis PCB Design and Analysis Tools A-Z IP Tensilica Processors Interface IP Denali Memory IP Analog IP Systems/Peripheral IP Verification IP Support Online Support Training Software Downloads University Software Program Resource Library News Press Releases Newsroom Blogs Forums Company Cadence Overview Investor Relations Alliances Executive Team Events Careers A Great Place to Do Great Work! Second year on the FORTUNE 100 list Our Culture Join the Team Subscribe to Monthly Newsletter Email * Contact Us General Inquiry Customer Support Media Relations Global Office Locator A Great Place to Do Great Work! Second year on the FORTUNE 100 list Our Culture Join the Team Subscribe to Monthly Newsletter Email * Worldwide Terms of Use Privacy Policy US Trademarks © 2016 Cadence Design Systems, Inc. All Rights Reserved. Connect with Us