Log In|Register|Resource Library|Worldwide ToolsIPSolutionsServicesSupport and TrainingAlliancesCommunityCompany Home > About Cadence > Newsroom > Cadence Articles > Get 10X Faster Power Signoff with New Voltus IC Power Integrity Solution Massively Parallel Execution: High Performance for Up to One Billion Instances Videos Learn 3 key benefits of Voltus solution Watch Video » Product Details Voltus IC Power Integrity Solution White Paper How to Achieve 10X Faster Power Integrity Analysis and Signoff Blog Voltus – Massive Parallelism Speeds Power Integrity Analysis and Signoff Closure Press Releases Cadence Introduces Voltus IC Power Integrity Solution, Delivering Exceptional Performance and Capacity in Power Signoff New Cadence Voltus IC Power Integrity Solution Gives IDT Up to 10X Power Signoff Speed-Up Mobile computing and the Internet of Things are driving more complexity into chip design. There are challenges stemming from complex design rules on advanced process nodes, low-power circuitry design techniques, and design tool integration, to name a few. Power integrity analysis remains a critical part of design signoff and, until now, this step no longer needs to be a bottleneck. With the new Cadence® Voltus™ IC Power Integrity Solution, you can achieve power analysis 10X faster than with competing solutions. Developed with advanced algorithms and a new power integrity analysis engine with massively parallel execution, Voltus IC Power Integrity Solution: Performs 10X faster than other solutions on the market Supports very large designs—up to one billion instances—with its hierarchical architecture Delivers SPICE-level accuracy Enhances physical implementation quality via physically aware power integrity optimization What Does Voltus IC Power Integrity Solution Do? Voltus IC Power Integrity Solution is a full-chip, cell-level power integrity solution that provides: IR drop and electromigration analysis and optimization Power consumption calculation and analysis Analysis of power impact on design closure, from chip to package to PCB “As power issues began playing an ever-growing role in SoCs, we realized that existing technology would not meet the needs for complex designs,” said Anirudh Devgan, senior vice president, Digital and Signoff Group at Cadence. “Voltus IC Power Integrity Solution is Cadence’s answer to these challenges, and all our early adopters are reporting great successes on its performance and capacity, including on-time tapeout for one of the industry’s largest chips.” Fastest Design Closure Flow Voltus IC Power Integrity Solution is certified by TSMC for the foundry’s 16nm FinFET manufacturing process (Design Rule Manual version 0.5). By meeting TSMC’s electronic design automation (EDA) tool certification criteria, the Voltus solution will enable you to achieve accurate static and dynamic IR drop analysis, and meet accuracy requirements for 16nm FinFET’s advanced electromigration design rules. Cadence is working with TSMC to complete certification for Design Rule Manual version 1.0. Available now, Voltus IC Power Integrity Solution can be used as a standalone solution; however, when integrated with other key Cadence tools, the overall solution provides the industry’s fastest design closure flow. Used with Cadence Tempus™ Timing Signoff Solution, you get a unified electrical signoff solution Used with Cadence Encounter® Digital Implementation System, you have an early rail analysis capability that brings power grid design to the early stage of physical implementation Used with Cadence Virtuoso® Power System, you can analyze the custom/analog intellectual property (IP) in analog/mixed-signal system-on-chip (SoC) designs Used with Cadence Palladium® technology, you get accurate IC power integrity analysis, driven by real-world power simulation vectors Used with Cadence Allegro® Sigrity® technology, you get chip-package-PCB co-simulation and analysis Feature stories archive » About Cadence| Investor Relations| Careers| Terms of Use| Privacy Policy| US Trademarks © Cadence Design Systems, Inc. All Rights Reserved.