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ARMv7 eLearning modules (unlimited access for 90 days) PDF of Course Slides (yours to keep, does not expire) A La Carte Course: NOTE: This eLearning course is a subset of the Comprehensive ARM Architecture eLearning course. If you want or need the full, comprehensive course, please visit that page. Course Outline: Module 1: ARM Overview - Intro to ARM the company, RISC vs CISC, ARMv7 vs v8, Architecture Profiles (-A, -R, -M), Intro to SoCs Module 2: v7 Architecture Introduction - Overview of v7 instruction sets and extensions, compatibilities and incompatibilities Module 3: v7 Integer Registers - Application registers, PC (r15), APSR, Register Banking Module 4: v7 Instructions - ARM - Three register format, Immediates, Shifts, Multiply and Accumulate, Divide, Moves and Returns, Branch, Branch and Link, Instruction Format, Condition Codes Module 5: v7 Instructions - Thumb and Jazelle - Thumb and Thumb2 vs ARM, Low Registers, If Then Else (Conditional Execution), Immediates, Switching Between ARM and Thumb, Jazelle-RCT, Jazelle DBX, ThumbEE Module 6: v7 Instructions - Vector Floating Point / Neon - VFPv3 and VFPv4, VFP Registers, Floating Point Types, Advanced SIMD (Neon) Registers, SIMD Data Types Module 7: v7 Memory Accesses - Endianness, Alignment, Load/Store Architecture, Stack Usage, Memory Copy, Device Access, Memory Types, Memory Ordering, Barrier Instructions, Shareability Domains, Semaphores, v7-M Bit Banding, v7-M and v7-R Tightly Coupled Memory (TCM) Module 8: v7 Privilege, Mode, State - User vs Privileged, v7 TrustZone Extension, Normal vs Secure World, Monitor Mode, v7 Coprocessor Concept, Detecting and Accessing Coprocessors Module 9: v7 Exceptions and Interrupts - IRQ vs FIQ, GIC, Exception Table, Exception Tables with TrustZone, Taking an Exception, Returning from an Exception Module 10: v7-M Memory Map and v7-R Memory Protection - -M Fixed Memory Map, -R Memory Regions, Memory Access Faults Module 11: v7-A Memory Management (Paging) - Paging Concepts, TLBs, Page and Section Sizes (4KB, 64KB, 1MB, 16MB), Table Access (TTBR0 and TTBR1), TLB Maintenance, Page Table Descriptors, Domains, ASIDs Module 12: v7 Large Physical Address Extension (LPAE) - Three Level Table Walk, 64-bit Descriptor, Large Pages (2MB and 1GB) Module 13: v7 Hardware Virtualization - Hardware Extension vs Software, Trap and Emulate, Banked Registers, HCR, HSR, Virtualization and Paging, Virtualization and Interrupts Module 14: v7 Debug and Analysis Support - Performance Monitors, Monitor Mode, Halting Debug Mode, Debug Port, Breakpoints and Watchpoints, Breakpoint Instruction (BKPT), Vector Catch, Trace Module 22: Caches - Cache Line, Way, Tag, Cache Line State (MESI, MOESI, MESIF), Management of Coherency, Cortex-A9 Caches, Cache Prefetch Hints, Cache, TLB and Branch Prediction, Cache and TLB Maintenance (v8) Module 23: Pipelines: Cortex-M and Cortex-R4 - Cortex-M0/1 Pipeline, Cortex-M4 Pipeline, Cortex-R4 Pipeline Module 24: Pipelines: Cortex-A8 / A9 / A5 - Cortex-A8 Pipeline, Caches and more; Cortex-A9 Pipeline, Caches and more; Cortex-A5 Pipeline, Caches and more Module 25: Pipelines: Cortex-A15 / A57 / A7 / A12 - Cortex-A15 Pipeline, Caches and more; Cortex-A57 Pipeline, Qualcomm Krait (Snapdragon s4), Cortex-A7 Pipeline, Cortex-A12 Pipeline Module 26: AMBA: AXI 3, APB and PCIe Bridges - SoC Interconnects, AMBA Versions, AXI Master and Slave Channels, AXI Transaction Types, APB Bridge to Slave, APB Transaction Examples, AXI to PCIe Bridge Module 27: AMBA 4 ACE, big.LITTLE and AMB5 - Coherence Channels, ACE Transaction Types, ACE Lite, AMB5 Coherent Hub Interconnect (CHI), Server Soc Interconnect Considerations Module 28: Power Management, Embedded Issues, Tools and Support - Platform Power Management, Cortex-A9 Power Modes, WFI, WFE, SEV, Dormant / Shutdown Modes, Core Power Domains, Predictability, Realtime - Interrupt Latency, ARM Supplied Software and Hardware Tools, GNU / Linux / Android / Microsoft and ARM, Real Time OS Considerations, Linaro Course Modules Module Length Module 1: ARM Overview 48 minutes Module 2: v7 Architecture Introduction 32 minutes Module 3: v7 Integer Registers 34 minutes Module 4: v7 Instructions - ARM 42 minutes Module 5: v7 Instructions - Thumb and Jazelle 32 minutes Module 6: v7 Instructions - Vector Floating Point / Neon 20 minutes Module 7: v7 Memory Accesses 65 minutes Module 9: v7 Exceptions and Interrupts 47 minutes Module 8: v7 Privilege, Mode, State 33 minutes Module 10: v7-M Memory Map and v7-R Memory Protection 21 minutes Module 11: v7-A Memory Management (Paging) 57 minutes Module 12: v7 Large Physical Address Extension (LPAE) 14 minutes Module 13: v7 Hardware Virtualization 34 minutes Module 14: v7 Debug and Analysis Support 28 minutes Module 22: Caches 50 minutes Module 23: Pipelines: Cortex-M and Cortex-R4 17 minutes Module 24: Pipelines: Cortex-A8 / A9 / A5 42 minutes Module 25: Pipelines: Cortex-A15 / A57 / A7 / A12 55 minutes Module 26: AMBA: AXI 3, APB and PCIe Bridges 53 minutes Module 27: AMBA 4 ACE, big.LITTLE and AMB5 39 minutes Module 28: Power Management, Embedded Issues, Tools and Support 35 minutes © MindShare, Inc. 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