Patent Document ID: 10133840
Application ID: 14958957

Base Claim:
1. A computer-implemented method comprising: receiving, by one or more processor(s), a text-based description of a logic circuit comprising a plurality of logic sub-circuits, wherein the text-based description comprises hierarchical hardware description language statements that define the logic circuit and the plurality of logic sub-circuits; determining within the text-based description, by the one or more processor(s), a set of circuit priority indicators that are explicitly indicated within the text-based description, for a corresponding set of the logic sub-circuits; synthesizing, by the one or more processor(s), the logic circuit according to the set of circuit priority indicators to provide a synthesized circuit description without requiring, or waiting for, estimation of a circuit slack for any of the plurality of logic sub-circuits; and fabricating the logic circuit using the synthesized circuit description wherein a circuit priority indicator is a function parameter.

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Claim 5:
5. The method of claim 1 , wherein synthesizing includes physical synthesis.