Patent Document ID: 4415766
Application ID: 06157296

Base Claim:
1. A system for recognizing codes representative of any one of a first, second, third or fourth conditions, and for recognizing transitions between selected ones of said conditions, and for providing a first output signal having a first and second state and a second output signal having a first and second state representative of said conditions and said transitions; said system comprising: a first circuit for recognizing the code representative of said first condition and the code representative of said second condition, and for providing a first state of said first output signal when said first condition is recognized and a second state of said first output signal when said second condition is recognized; a second circuit for recognizing the code representative of said third condition and the code representative of said fourth condition, and for providing a first state of said second output signal when said third condition is recognized, and a second state of said second output signal when said fourth condition is recognized; the transition from said first condition to said second condition comprising a first change in state in said second output signal; the transition from said third condition to said fourth condition comprising a second change in state in said second output signal; a transition from said first condition to said third condition comprising a first change in state in said first output signal; and the transition from said second condition to said fourth condition comprising a second change in state in said first output signal.

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Claim 2:
2. A system as defined in claim 1 and comprising a data bus, and having a plurality of signal lines, for receiving said coded input signals; (1) said first circuit comprising: a. first gate means having a plurality of input terminals, said signal lines being connected to respective ones of said input terminals, said gate means also comprising an output terminal; b. first flip-flop means having two input terminals and an output terminal, said output terminal of said first gate means being connected to the first input terminal of said first flip-flop means; (2) said second circuit comprising: a. second gate means having a plurality of input terminals connected to respective ones of said input lines, and having a first output terminal and a second output terminal; b. second flip-flop means having a first input terminal and a second input terminal and an output terminal, said first output terminal of said second gate means being connected to the first input terminal of said flip-flop, and said second output of said second gate means being connected to the second input terminal of said second flip-flop means; c. third gate means having a first input terminal and a second input terminal and an output terminal, the output terminal of said second gate means being connected to one input terminal of said fourth gate means, and the output terminal of said third gate means being connected to the other input terminal of said fourth gate means; (3) and further including: a. fifth gate means having two input terminals and an output terminal, said output terminal of said first gate means being connected to one input terminal of said fifth gate means, and the output terminals of said fourth gate means being connected to the other input terminal of said fifth gate means, the output terminal of said fifth gate means being connected to the second input terminal of said first flip-flop means.