Patent Document ID: 8612945
Application ID: 12992162

Base Claim:
1. An Extensible Markup Language (XML) processing device which converts and outputs an XML inputted asynchronously from outside according to a conversion rule, comprising: a storage unit that stores the conversion rule written in an XML processing language and an output destination solution table that defines an output destination of the XML, the output destination of the XML corresponding to identifiers contained in the conversion rule; a cache memory that temporarily stores the XML; a cache reference module that acquires the XML from the cache memory; a cache update module that adds the XML to the cache memory and erases the XML from the cache memory; an XML conversion module that refers to the XML of the cache memory by the cache reference module and converts the XML according to the conversion rule read out from the storage unit, when the XML is inputted; an output destination interpretation module that interprets the output destination corresponding to the identifiers contained in the conversion rule and written in an attribute or an element of the XML converted by the XML conversion module based on a content defined by the output destination solution table; and an output distribution module that outputs the converted XML to the cache update module when the output destination of the converted XML is the cache update module defined in the output destination solution table, and outputs the converted XML to an XML transmission module that transmits the converted XML to an external output device by using Hypertext Transfer Protocol (HTTP) protocol when the output destination of the converted XML is the XML transmission module.

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Claim 3:
3. The XML processing device as claimed in claim 1 , comprising: a plurality of the cache memories; and a named cache update module that relates the output destination written in the outputs from the output distribution module with the plurality of cache memories, and adds and erases the XML to/from the plurality of cache memories.