Patent Document ID: 7810056
Application ID: 11711950

Base Claim:
1. A computer implemented method for assertion synthesis of circuitry comprising: using at least one computer system which comprises at least one processor and is programmed for performing: converting an assertion formula to a sequence implication form using one or more semantic preserving rewrite rules, wherein the sequence implication form converted by the one or more semantic preserving rewrite rules is semantically equivalent to the assertion formula; optimizing a resulting formula, which is converted from the assertion formula, to reduce a number of states in a state machine that represents the circuitry; synthesizing the resulting formula to the state machine using context aware sequence synthesis, wherein the context aware sequence synthesis synthesizes the resulting formula based at least in part upon context of one or more sequences in the resulting formula; and verifying the circuitry using the state machine.

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Claim 3:
3. The method of claim 1 , wherein the assertion formula comprises an SVA (System Verilog Assertions) formula.