Patent Document ID: 9335982
Application ID: 14698809

Base Claim:
1. A system comprising: a memory area associated with a computing device in a target processing architecture, said memory area storing a dispatcher table, a first translated binary with a first marker table, and a second translated binary with a second marker table, the dispatcher table mapping a subset of instructions from a source binary to corresponding instructions in the first translated binary; and a processor programmed to: execute, by a dispatcher via the dispatcher table stored in the memory area, the first translated binary; upon encountering a branch instruction in the first translated binary with a target that is addressable in the first translated binary, branch to a target address in the first translated binary and execute an instruction at the target address in the first translated binary; upon encountering a branch instruction in the first translated binary with a target that is not addressable in the first translated binary, access the second translated binary, the second translated binary including one or more marker values corresponding to a second set of instructions in the second translated binary; wherein the processor is further programmed to branch to a target address, in the second translated binary, described by a marker value in the second marker table and execute an instruction at the target address in the second translated binary; and return to the first translated binary from the second translated binary after reaching a subsequent branch instruction in the second translated binary by branching directly to the dispatcher for every branch instruction that leaves a current function from the second translated binary.

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Claim 5:
5. The system of claim 1 , wherein the target processing architecture executes the instruction without just-in-time compilation or generating executable machine code at runtime.