Patent Document ID: 7752417
Application ID: 11447189

Base Claim:
1. A computer-implemented method, comprising, during execution of a first application: receiving, on behalf of said first application, a first memory request directed to a first virtual memory address; translating said first virtual memory address to a corresponding first physical address according to a first address translation technique; analyzing performance of said first application; dynamically selecting a second address translation technique for translating virtual memory addresses to corresponding physical memory addresses on behalf of said first application; and subsequent to said selecting a second address translation technique, receiving, on behalf of said first application, a second memory request directed to a second virtual memory address, and translating said second virtual memory address to a corresponding second physical address according to said second address translation technique; wherein said dynamically selecting a second address translation technique is dependent, at least in part, on a user policy and on results of said analyzing; and wherein said dynamically selecting and said translating according to said second address translation technique are performed transparently to said first application.

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Claim 5:
5. The method of claim 1 , further comprising, during said execution, reorganizing a memory in conjunction with said selecting a second address translation technique, wherein said reorganizing said memory comprises one or more of: reducing fragmentation of a portion of said memory, reorganizing a page table corresponding to said memory, changing one or more mappings between a virtual address space and a corresponding physical address space of said memory, and allocating a different portion of said memory to said first application.