Patent Document ID: 8732630
Application ID: 13831958

Base Claim:
1. A computer implemented method for implementing analog behavioral modeling and IP (intellectual property) integration using a Hardware Description Language, comprising: at least one processor or at least one processor core executing a process, the process comprising: detecting an incompatible connection that interacts with a wire in a digital modeling environment that is represented using digital signals; representing a real-valued net of a built-in nettype in the digital modeling environment with 4-state logic signals; correlating the real-valued net with a corresponding resolution function that is defined natively in the digital modeling environment; and coercing the incompatible connection to the wire based at least in part upon the corresponding resolution function.

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Claim 12:
12. The computer implemented method of claim 1 , the process further comprising: coercing the concatenation of nets to real-valued nets; and determining a type of real-valued nets based at least in part a resolution function of a net in the array of nets of the built-in nettype, wherein the concatenation of nets is determined not to be collapsible.