Patent Document ID: 9195789
Application ID: 14324004

Base Claim:
1. A method for incrementally verifying a circuit design, the method comprising: (a) representing a first subset of modules in the circuit design by one or more interpretive computer programming modules, wherein the circuit design is used to manufacture integrated circuits; (b) representing a second subset of modules in the circuit design by one or more hardware descriptive language (HDL) modules; (c) performing simulation of a mixed design which represents the first subset of the circuit design by the one or more interpretive computer programming modules and represents the second subset of the circuit design by the one or more HDL modules; (d) translating a part of the first subset of modules into a HDL module to include the part of the first subset in the second subset of modules and remove the part from the first subset of modules, responsive to the simulation of the mixed design being successful; and (e) repeating (a) through (d) at least once until no module for translation remain in the first subset of modules.

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Claim 2:
2. The method of claim 1 , wherein the interpretive programing language module is a C module and the hardware description language (HDL) module is a register transfer level (RTL) module.