Patent Document ID: 8127264
Application ID: 12510122

Base Claim:
1. A method of designing an integrated circuit employing a hierarchical design flow, comprising: (a) creating a functional circuit for a functional block of an IC design; (b) verifying said functional circuit satisfies a rule-set for said IC design, wherein said rule-set is context-based with respect to said hierarchical design flow; (c) synthesizing a logical circuit based on said functional circuit; (d) verifying said logical circuit satisfies said rule-set; (e) implementing a physical layout of said logical circuit; and (f) verifying said physical layout satisfies said rule-set, wherein each step of said method is carried out by at least one EDA tool.

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Claim 4:
4. The method as recited in claim 1 wherein said hierarchical design flow includes a functional context, a logical context and a physical context.