Patent Document ID: 9600616
Application ID: 15264336

Base Claim:
1. A computer-implemented method for assuring a reliability of a chip comprising: verifying a parity with a processor; traversing, via the processor, a netlist back from a plurality of netlist outputs; identifying, via the processor, one or more parity protected structures and one or more gates, wherein protected parity structures comprises a duplication protection; and generating, via the processor, a driver based on a logic structure and an assertion indicative of a parity validity.

---

Claim 6:
6. The computer-implemented method of claim 1 , wherein identifying the one or more parity protected structures comprises: retrieving a design netlist with a processor; statistically analyzing the design netlist; extracting checking logic information from the design netlist; and extracting gating information from the design netlist by identifying a plurality of protected structures and a plurality of gating structures; and identifying the logic structure in the design netlist based on a statistical analysis of the design netlist, the logic information, and gating information.