Patent Document ID: 9471734
Application ID: 14599827

Base Claim:
1. A computer system comprising: one or more processors which process program instructions; a memory device connected to said one or more processors; and program instructions residing in said memory device for verifying liveness of a logic design by receiving a circuit description for the logic design which includes vertices representing gates and edges representing interconnections between the gates wherein portions of the gates represent different state elements which are evaluated to determine a state of the logic design, designating an initial subset of the state elements for inclusion in an abstraction of the logic design, performing liveness verification on the abstraction based on the initial subset of the state elements, detecting a liveness counterexample in response to said performing the liveness verification, by executing fourth instructions in the computer system, and refining the abstraction by designating a second subset of the state elements different from the initial subset for inclusion in a refined abstraction.

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Claim 6:
6. The computer system of claim 1 wherein the liveness verification includes liveness-to-safety conversion on the initial subset of the state elements.