Patent Document ID: 5572708
Application ID: 08074725

Base Claim:
1. A logic simulator comprising: a descriptor memory for memorizing descriptors descriptive of a logic circuit as memorized descriptors, each descriptor of said memorized descriptors being one of variables and functional operators; a first register connected to said descriptor memory for memorizing each variable of said memorized descriptors as a first datum; a second register for memorizing a second datum, said second register being coupled to said first register via a signal path for selectively supplying said second datum from said second register to said first register; calculating means connected to said first and said second registers and said descriptor memory for carrying out calculation on said first and said second data on the basis of one of said functional operators of said memorized operators to provide a result of calculation, said one of the functional operators joining said first and said second data; refreshing means connected to said second register and said calculating means for carrying out refreshment of said second datum by said result of calculation; and control means connected to said descriptor memory, said first and said second registers, said calculating means, and said refreshing means for controlling transfer of said each variable and said one of the functional operators from said descriptor memory to said first register, said calculating means, and said refreshing means, said control means controlling the transfer of said variables and functional operators to said first and second registers, and said calculating means sequentially in a serial fashion.

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Claim 2:
2. A logic simulator as claimed in claim 1, wherein: said descriptor memory memorizes a first, a second, and a third variable and a first and a second functional operator as said memorized descriptors, said first functional operator joining said first and said second variables; said control means controlling said transfer, said calculation, and said refreshment in response to an output of said descriptor memory, and including means for causing said first and said second registers to memorize a first set of data including said first and said second variables as said first and said second data before refreshment of said refreshing means and for causing said first and said second registers to memorize, after refreshment of said refreshing means, as said first and said second data a second set of data including said third variable and a first result of calculation of said calculating means which carries out calculation on said first and said second variables on the basis of said first functional operator, said third variable and said first result being used as said first and said second data in said calculating means to be produced as a second result of calculation of said calculating means on the basis of said second functional operator.