Patent Document ID: 3938103
Application ID: 05452819

Base Claim:
1. An inherently microprogrammable high level language processor which includes an electrical interconnection with a storage device for executing an interpretable language string stored in said storage device, wherein said string includes machine level operation codes, and for executing one of a plurality of elementary language programs stored in said storage device, each program being represented by a machine level operation code, comprising: a. first extration means for extracting a machine level operation code via said electrical interconnection from said interpretable language string stored in said storage device for use in locating the one of the elementary language programs stored in said storage device which is represented by the extracted code; b. second extraction means for extracting an elementary language operation code via said electrical interconnection from said one elementary language program stored in said storage device; c. decoding means for decoding the extracted elementary language operation code; and d. logic means connected to said decoding means for executing the elementary operation which is represented by the elementary language operation code.

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Claim 7:
7. A processor as set forth in claim 1 wherein said first extraction means further comprises: a. a program character counter for providing a word address, and a bit address within said word which indicate the character in said interpretable language string to be extracted, and for further providing an indication of when a word needs to be transferred out of storage; b. a first shift register, corresponding in length to the length of a word in storage, for receiving a word transferred from said storage device via said electrical interconnection, said transferred word being uniquely identified by the word address portion of said program character counter; c. a second shift register corresponding in length to the length of a word in storage connected to said first shift register, for receiving from said first shift register bits that are left shifted; d. bit counter means for controlling left shifting of bits from said first register to said second register; e. control means for incrementing said bit address in said program character counter by one unit with each left shift and for decrementing said bit counter means by one unit for each left shift; and f. means for retrieving from said second shift register the right adjusted program character extracted.