Patent Document ID: 8332787
Application ID: 12940762

Base Claim:
1. A method comprising: removing, based on execution of an instruction by a processor, a part of a logic from a hardware description language design to create a modified hardware language design, the part of the logic comprising at least one time sensitive path in the hardware description language design; comparing the modified hardware language design to a physical representation that is logically equivalent to the hardware description language design to create a delta list of differences; creating a modified physical representation that includes a part of the physical representation that includes the logical equivalent of the part of the logic comprising the at least one time sensitive path, using the delta list of differences; creating a structured hardware description language design of the part of the logic comprising the at least one time sensitive path using the modified physical representation, the structured hardware description language design comprising a physical implementation requirement of at least one component; and modifying the structured hardware description language design, wherein the modifying updates the structured hardware description language design to comply with requirements of a synthesis operation of a synthesis tool, and wherein the modifying precludes the synthesis tool from modifying the physical implementation requirement of the at least one component.

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Claim 4:
4. The method of claim 1 , wherein the physical implementation requirement comprises at least one of a placement of a component and a requirement of a wire coupling components together.