Patent Document ID: 8522181
Application ID: 13357544

Base Claim:
1. A method to design an integrated circuit comprising: creating a plurality of canonical hierarchical models to represent the integrated circuit, the plurality of canonical hierarchical models including at least a first type canonical model to capture a first capacitance of a device having a plurality of first conductors, and a second type canonical model to capture a second capacitance between at least a portion of the device and one or more second conductors of the integrated circuit, wherein the second type canonical model represents a portion of the integrated circuit comprising the one or more second conductors outside the device; and determining a capacitance in the design of the integrated circuit based on the plurality of canonical hierarchical models.

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Claim 7:
7. The method of claim 1 , further comprising receiving a layout of the integrated circuit; applying the canonical hierarchical models to the layout; calculating capacitance values associated with portions of the layout based on the models; determining a capacitance for the layout based on the capacitance values.