Patent Document ID: 6076182
Application ID: 08767180

Base Claim:
1. A method of storing data in a computer system memory, comprising: receiving a data word having a plurality of consecutive data bits; determining a first error correction code for a first sub-word of the data word, the first sub-word including a first subset of the data bits of the data word, the first subset comprising alternate data bits of the data word, the first error correction code including a plurality of check bits and being determined based on all of the data bits of the first sub-word; determining a second error correction code for a second sub-word of the data word, the second sub-word including a second subset of the data bits of the data word, the second subset comprising alternate data bits of the data word that are interleaved with the data bits included in the first subset, the second error correction code including a plurality of check bits and being determined based on all of the data bits of the second sub-word; entering and storing the data word and the first and second error correction codes in the memory; retrieving the data word and the first and second error correction codes from the memory; determining from the first error correction code which of the data bits of the first sub-word was altered in error, if any, between entering the data word in the memory and retrieving the data word from the memory; if a data bit of the first sub-word is determined to have been altered in error, then correcting the data bit; determining from the second error correction code which of the data bits of the second sub-word was altered in error between entering the data word in the memory and retrieving the data word from the memory; and if a data bit of the second sub-word is determined to have been altered in error, then correcting the data bit.

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Claim 4:
4. The method of claim 1, further including: determining a third error correction code for a third sub-word of the data word, the third sub-word including a third subset of the data bits of the data word, the third subset comprising non-consecutive data bits of the data word, the third error correction code including a plurality of check bits and being determined based on all of the data bits of the third sub-word; and determining a fourth error correction code for a fourth sub-word of the data word, the fourth sub-word including a fourth subset of the data bits of the data word, the fourth subset comprising non-consecutive data bits of the data word that are intermediate data bits included in the third subset, the fourth error correction code including a plurality of check bits and being determined based on all of the data bits of the fourth sub-word, wherein each data bit of the first sub-word is immediately followed by a data bit of the second sub-word, each data bit of the second sub-word is immediately followed by a data bit of the third sub-word, each data bit of the third sub-word is immediately followed by a data bit of the fourth sub-word, and at least one of the data bits of the fourth sub-word is immediately followed by a data bit of the first sub-word when the data word is received.