Patent Document ID: 7724094
Application ID: 11440656

Base Claim:
1. A digital phase locked loop, comprising: a first terminal configured to receive a first frequency word and a second terminal configured to receive a second frequency word; a value-discretely tunable oscillator configured to generate and output a signal having a frequency; an integrator comprising an input coupled to the first and the second terminals, and comprising an output coupled to a loop filter that is configured to provide a digital multi-bit setting word to a set input of the value-discretely tunable oscillator; a feedback path comprising a counting device, the counting device configured to output a word derived from the signal of the value-discretely tunable oscillator and a reference signal, wherein an output of the counting device and the first frequency word combine at a combining element to form a third frequency word; and a correction circuit comprising an input coupled to an input of the integrator, and an output coupled to an output of the integrator, wherein the correction circuit is configured to generate a correction word derived from the third frequency word fed to the input of the integrator and a word derived from the second frequency word.

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Claim 3:
3. The phase locked loop of claim 1 , wherein the correction circuit further comprises a control circuit comprising a first input that forms the input of the correction circuit, and a second input configured to receive a start value and generate the correction word based on the presence of a specific word at the first input and the start value.