Patent Document ID: 8239590
Application ID: 12689636

Base Claim:
1. An apparatus comprising a circuit that includes: first and second data interfaces for parallel transfer of data having respective first and second word widths that are each multi-bit and different; a data transfer portion that manipulates data arriving at the first data interface with the first word width into data with the second word width, the data transfer portion transferring the manipulated data to the second data interface; and configurable structure that specifies one of the first or second word widths is a selected one of a plurality of different word widths, including a field-programmable device that includes the circuit, wherein during field programming of the device the configurable structure is configured to specify the selected one of the plurality of different word widths.

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Claim 7:
7. An apparatus according to claim 1 , wherein the second word width is an integer multiple of the first word width; wherein the data transfer portion carries out the manipulation in a manner that includes assembling a plurality of first data words with the first word width received successively from the first data interface into a single second data word having the second word width; wherein the data transfer portion carries out the transferring in a manner that includes supplying the second data word to the second data interface; wherein the data transfer portion includes a storage portion having a plurality of independently controlled storage elements; wherein the data transfer portion carries out the assembling in a manner that includes storing each of the plurality of first data words in the storage portion, including arranging the first data words into groups such that each storage element contains a respective one of the groups; and wherein the supplying includes simultaneously supplying the plurality of first data words from the storage portion to the second data interface.