Patent Document ID: 5559718
Application ID: 08234410

Base Claim:
1. A system for model-based verification of local design rules in a physical integrated circuit design, the system comprising: a processing unit having an input and an output, for performing the model-based local design rule verification of the physical integrated circuit design according to a sequence of program instruction steps; a verification database having an input and an output, for storing a cell reference graph representing the physical integrated circuit design as a set of cells, each cell representing one of a constituent model and a shape model on a physical mask design, each constituent model comprising a reference to one of a shape model and a reference to a second cell at a lower hierarchical level, the output of the verification database coupled to the input of the processing unit, the input of the verification database coupled to the output of the processing unit, said verification database further comprising: a reference graph register having an input and an output, for storing the cell reference graph representation of the physical integrated circuit design, the output of the reference graph register coupled to the input of the processing unit, the input of the reference graph register coupled to the output of the processing unit; a results register having an input and an output, for storing a verification result, the input of the results register coupled to the output of the processing unit, and the output of the results register coupled to the input of the processing unit; said processing unit overriding one of said verification results and said results register storing a new verification result associated with a first cell of said set of cells if a position of one of a second cell of said set of cells and a shape model violates said verification function; and a verification memory having an input and an output, for storing said verification function and one or more models during model-based local design rule verification, the output of the verification memory coupled to the input of the processing unit.

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Claim 23:
23. The system of claim 1, wherein each of said cells comprises one of a reference to another of said cells and a reference to one of a plurality of shape models.