Patent Document ID: 8635571
Application ID: 13656361

Base Claim:
1. A method comprising: generating, by or using a computer system, a hardware description language (HDL) implementation of a circuit design to be implemented on a programmable logic device (PLD) device; partitioning, by or using the computer system, the circuit design into a public portion and a secret portion; generating, by or using the computer system, an HDL implementation or a netlist implementation of the public portion without the secret portion included; generating, by or using the computer system, an HDL implementation or a netlist implementation of an interface for coupling the public portion and the secret portion; generating, by or using the computer system, a programming file containing configuration settings for only the secret portion based on the HDL implementation of the secret portion of the circuit design for use in programming the secret portion of the circuit design into a PLD device.

---

Claim 8:
8. The method of claim 1 , wherein the circuit design is to be implemented on a field-programmable gate array (FPGA) type of PLD device.