Patent Document ID: 9536342
Application ID: 14461047

Base Claim:
1. An apparatus, comprising: a processor circuit; and non-transitory computer-readable storage media having stored thereon instructions for execution by the processor circuit to: determine one or more respective suitability metrics for each of one or more candidate partitioning policies for a set of pixel shader inputs for a graphics frame, each candidate partitioning policy comprising one or more rules for partitioning the set of pixel shader inputs for multi-phase pixel shading based on quality sensitivity values for the pixel shader inputs; select a partitioning policy for the set of pixel shader inputs from among the one or more candidate partitioning policies based on the determined suitability metrics; and construct a multi-phase pixel shader for the graphics frame by partitioning the set of pixel shader inputs into multiple classes according to the selected partitioning policy.

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Claim 5:
5. The apparatus of claim 1 , the non-transitory computer-readable storage media having stored thereon instructions for execution by the processor circuit to partition the set of pixel shader inputs into a coarse-rate class and a standard-rate class based on a coarse-rate quality sensitivity threshold defined by the selected partitioning policy.