Patent Document ID: 4437155
Application ID: 06207059

Base Claim:
1. In a data processing system including a host processor for issuing addressing signals specifying data to be accessed, a mass memory, a cache store for storing segments, and a segment descriptor table for storing segment descriptors, there being a segment descriptor associated with each data segment in said cache store and including age information defining, from the most recently accessed to the least recently accessed, the relative lengths of time since each associated data segment has been accessed, the system including means for transferring to said mass memory the least recently accessed segments in said cache store in order to make room for more data segments, the improvement comprising: means connected to said host processor, said mass memory and said cache store for transferring from said mass memory to said cache store not only a data segment containing data specified by said addressing signals but not resident in said store, but also a number of additional segments; and, age modifying means for modifying said age information in said segment descriptors each time data segments are transferred from said mass memory to said cache store to produce modified age information, said modified age information indicating that the data segment containing the data specified by said addressing signals is the most recently accessed data segment, and indicating that said number of additional segments have an age intermediate the most recently accessed and the least recently accessed.

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Claim 3:
3. The improvement as claimed in claim 1 and further comprising: means for storing a first value representing a maximum number of segments of data which may be transferred between said mass memory and said cache store; means for computing a second value representing the number of segments to be transferred from said mass memory to said cache store which contain data specified by said host processor; and, difference determining means for determining the difference between said first value and said second value, said means for transferring data segments from said mass memory to said cache store being responsive to said difference determining means for transferring a number of said additional segments which is equal to said difference.