Patent Document ID: 9003339
Application ID: 14200839

Base Claim:
1. A non-transitory computer-readable storage medium having instructions stored therein for causing a processor to perform a process of synthesizing a behavioral description of a circuit into a structural description of the circuit, the process comprising: receiving the behavioral description of the circuit, the behavioral description including a first statement that is associated with a condition; identifying the condition associated with the first statement; identifying one or more other statements associated with the first statement, including: determining a downstream statement that depends on the first statement, and/or determining an upstream statement upon which the first statement depends; inferring one or more potential clock domains gated by the condition for logic associated with the first statement and the one or more other statements; scheduling the logic associated with the first statement and the one or more other statements according to the one or more potential clock domains; and generating the structural description of the circuit, the structural description including a structural description of the scheduled logic.

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Claim 9:
9. The non-transitory computer-readable storage medium of claim 1 , wherein the scheduling comprises: iteratively: evaluating the scheduled logic against at least a timing constraint and/or a power constraint; and scheduling the logic associated with the first statement and the one or more other statements to a subset of the one or more inferred potential clock domains based on the evaluating.