Patent Document ID: 9355033
Application ID: 13789083

Base Claim:
1. A method of facilitating translation of memory addresses, said method comprising: providing, by a hypervisor executing within a computing environment, a first type of translation support for a first type of guest operating system supported by the hypervisor, the first type of translation support comprising a paravirtualization support in which the first type of guest operating system assists in handling address translation faults corresponding to host translations of guest memory addresses by at least updating, at least in part, an address translation data structure of the host; and providing, by the hypervisor, a second type of translation support for a second type of guest operating system supported by the hypervisor, the second type of translation support comprising a virtualization support in which address translation faults corresponding to host translations of guest memory addresses are handled by a component of the computing environment other than the second type of guest operating system, wherein the second type of guest operating system does not update the address translation data structure of the host.

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Claim 6:
6. The method of claim 1 , further comprising: determining that an address translation fault has occurred, the address translation fault corresponding to an address translation relating to the second type of guest operating system; and providing an indication of the address translation fault to an adjunct component coupled to the second type of guest operating system and the hypervisor, the adjunct component to assist in handling the address translation fault.