Patent Document ID: 7971167
Application ID: 12032117

Base Claim:
1. A semiconductor design support device for designing a semiconductor integrated circuit, the device comprising: a behavioral description configured to describe an algorithm of processing performed by hardware in a motion level; an RTL description generated by reading the behavioral description, the RTL description configured to recognize a concept including register and clock synchronism particular to the hardware; a latency analyzer configured to analyze a result of a logic simulation performed on the RTL description to calculate a latency in each block representing an operation in a predetermined unit in the behavioral description; a correspondence table in which each block in the behavioral description corresponds to a state in the RTL description; and a correspondence table generator configured to generate the correspondence table.

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Claim 2:
2. The semiconductor design support device according to claim 1 , wherein the latency analyzer refers to the result of the logic simulation and the correspondence table generated by the correspondence table generator to calculate the latency in each block in the behavioral description.