Patent Document ID: 9026475
Application ID: 12581948

Base Claim:
1. A method for manufacturing integrated circuits (“ICs”), the method comprising: providing a standard IC cell library to one or more customers for generating a standard IC design; providing one or more slim IC cell libraries having a layout size reduction in comparison with the standard IC cell library, wherein the slim IC cell libraries include technology files stored on a computer; providing the one or more slim IC cell libraries to the one or more customers for generating a slim IC design; receiving a tape-out file of the slim IC design from a customer, wherein the tape-out file is formed by selecting at least one cell from the one or more slim IC cell libraries and placing it in a layout file for an integrated circuit, wherein the layout file is used by the computer to generate the tape-out file; manufacturing a plurality of wafers including slim ICs from the slim IC design using the tape-out file, wherein the manufacturing includes fabricating a number of chips per wafer that include the at least one cell from the one or more slim IC cell libraries; calculating a per-wafer premium associated with the manufacturing the plurality of wafers, wherein the calculating the per-wafer premium includes: determining a percentage of additional chips per wafer of the plurality of wafers provided when using the at least one cell from the slim IC cell library in the tape-out file in comparison with using a cell of the standard IC cell library in the tape-out file; and using the determined percentage to calculate the per-wafer premium; charging the customer the per-wafer premium to manufacture the slim ICs, the premium being paid by the customer to a manufacturer of the slim ICs; providing a first portion of the premium to a first entity, wherein the first entity is a contributor of technology for enabling creation of the slim IC cell library and the first portion is provided to the first entity by the manufacturer; and providing a second portion of the premium to a creator of the slim IC cell library.

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Claim 3:
3. The method of claim 1 , wherein more slim ICs fit per wafer than would fit using standard ICs from the standard IC design.