Patent Document ID: 6154156
Application ID: 09264188

Base Claim:
1. A message processing device for sending and receiving a message composed of one or more elements between different kinds of devices, comprising: parse tree holding means having a function of holding a parse tree generated from syntax descriptions defining structure of a message sent or received; parse tree scanning means connected to said parse tree holding means and having a function of, as message data to be processed is applied, scanning said parse tree to encode and decode a value and outputting encoded and decoded values; preamble processing means connected to said parse tree scanning means and having a function of processing a preamble field of a message for use in indicating whether an element exists or not in message data sent or received; and index processing means connected to said parse tree scanning means and having a function of processing an index field of a message for use in indicating what number of element is selected in message data whose one of a plurality of elements is selected to be sent or received.

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Claim 2:
2. The message processing device as set forth in claim 1, wherein said preamble processing means comprises: a counter having a function of receiving input of a signal indicating whether a node being scanned is omissible and when said signal indicates that the node is omissible, counting up a count value and outputting the count value, a decoder having a function of decoding a count value of said counter and outputting the decoded value as a write enable signal to each of flip-flops constituting a register which will be described later, a first multiplexer having a function of receiving input of a signal indicating which processing of encoding and decoding is being executed, and when the signal indicates encoding, outputting a signal indicating whether an element corresponding to a node in the parse tree being scanned exists or not to a register which will be described later and when the signal indicates decoding, outputting a preamble field input signal, a register having a function of receiving input of the signal from said first multiplexer and the write enable signal from said decoder, and for a flip-flop to which said write enable signal is effective, reading the signal from said multiplexer and holding the contents of the signal and for a flip-flop to which said write enable signal is not effective, keeping holding the currently held contents, as well as outputting the currently held contents as a preamble field output signal, and a second multiplexer having a function of receiving input of the preamble field output signal from said register and the count value from said counter and outputting the contents of a bit at a bit position corresponding to the count value in a preamble field as an instruction signal giving an instruction to decode an element corresponding to the subsequent node.