Patent Document ID: 8813043
Application ID: 12347398

Base Claim:
1. A memory coupled to a processor, the memory having stored thereon computer executable instructions causing the processor to execute a process, the process comprising: translating a program code to a logical representation that includes type-safety assertions by asserting at least one type-safety invariant at one or more program points of the logical representation, wherein the at least one type-safety invariant states that a memory location is well-typed such that a value at the memory location corresponds to a type declared for the memory location, and wherein the type-safety assertions include a portion containing user-defined types input directly into the logical representation, and wherein the translating of the program code comprises translating the program code other than the user-defined types into the logical representation; generating a verification condition from the translated program code; if the generated verification condition includes one or more universal quantifiers, removing the one or more universal quantifiers from the generated verification condition; and executing a decision procedure to prove or disprove the generated verification condition.

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Claim 5:
5. The memory according to claim 1 , wherein the translating the program code to the logical representation includes asserting the at least one type-safety invariant after every program point by modeling a type-safety invariant for a heap and for local variables, if any.