Patent Document ID: 7617469
Application ID: 11842317

Base Claim:
1. An assertion description conversion device comprising: verification target identification unit parsing the syntax of a high-level assertion description described by a high-level assertion description language for verification of an inputted design description of a broader term to identify a verification target; design description searching unit searching a description on the verification target in a design description of a broader term; verification target description conversion unit converting the description of the verification target into a design description of a narrower term according to the design description of the narrower term corresponding to the description searched by the design description searching unit; verification content analysis unit for analyzing verification contents for the verification target described in the high-level assertion description; verification content description conversion unit for converting the verification contents analyzed by the verification content analysis unit into the description format of a low-level assertion description language for verification of a design description of the narrower term; and wherein, in the verification target description conversion unit, when converting the description of the verification target description into the design description of the narrower term, a description for timing adjustment is added according to synthesis result information at the time when synthesizing the design description of the narrower term according to the design description of the broader term.

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Claim 4:
4. The assertion description conversion device according to claim 1 , wherein the high-level assertion description is an assertion description of the transaction level and the low-level assertion description is an assertion description of the I/O cycle operation level.