Patent Document ID: 9966970
Application ID: 14682244

Base Claim:
1. A method, comprising: operating on, by a design tool executing on a computer system, a first plurality of data words, wherein each data word of the first plurality of data words includes N data bits, wherein N is a positive integer greater than one; operating on, by the design tool executing on the computer system, a second plurality of data words, wherein each data word of the second plurality of data words includes M data bits, wherein M is a positive integer greater than N, wherein a value of M is based upon a predetermined simultaneous switching out (SSO) noise threshold level, and wherein a number of data words in the second plurality of data words is greater than a number of data words in the first plurality of data words; starting, by the design tool executing on the computer system, at a first bit position of a particular data word of a first subset of the first plurality of data words, generating a comparison of data bits of the particular data word to a first N data bits of each data word of a second subset of the second plurality of data words; determining, by the design tool executing on the computer system, a respective number of matching data bits between the particular data word and the first N data bits of each data word of the second subset of the second plurality of data words based on results of the comparison; selecting, by the design tool executing on the computer system, a given data word of the second subset whose bit value at a most-significant-bit (MSB) position is the same as a bit value at a MSB of the particular data word, and that has a largest number of matching data bits with the particular data word; generating, by the design tool executing on the computer system, a mapping between the particular data word to the given data word; generating, by the design tool executing on the computer system, a description of the mapping between the particular data word and the given data word using a hardware description language; and synthesizing, by the design tool executing on the computer system, a design of an encoder circuit using the description of the mapping, wherein the encoder circuit is executable to encode a particular data word that includes N data bits to generate an encoded data word that includes M data bits, and transmit, in parallel, the M data bits of the encoded data word.

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Claim 2:
2. The method of claim 1 , wherein the first subset of the first plurality of data words includes an upper half of the first plurality of data words, and wherein the second subset of the second plurality of data words includes an upper half of the second plurality of data words.