Patent Document ID: 8271918
Application ID: 12559343

Base Claim:
1. A computer implemented method for performing verification of a device design comprising: identifying a plurality of clock domain crossing boundaries within a device design; performing on a computer a formal clock domain crossing verification process on ones of the plurality of clock domain crossing boundaries, the formal clock domain crossing verification process generating a set of clock domain crossing boundaries to be promoted; and saving the set of clock domain crossing boundaries to a memory storage location.

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Claim 3:
3. The computer implemented method recited in claim 1 , wherein the formal clock domain crossing verification process comprises: selecting a clock domain crossing boundary from the verification queue; extracting a portion of the device design, the extracted portion of the device design containing the selected clock domain crossing boundary; synthesizing a clock domain crossing assertion based at least in part on the selected clock domain crossing boundary and the extracted portion of the device design; applying a clock domain crossing protocol check on the synthesized clock domain crossing assertion, the clock domain crossing protocol check producing an outcome; and determining if the selected clock domain crossing boundary should be included in the set of clock domain crossing boundaries to be promoted based on the outcome.