Patent Document ID: 8886856
Application ID: 13165762

Base Claim:
1. An integrated circuit configured to communicate a low-latency word category over a bi-directional multi-lane link, the integrated circuit comprising: a transmitter that transmits a first plurality of words over the multi-lane link to a receiver of another integrated circuit; a transmitter controller that sends words of the first plurality of words that belong to the low-latency word category only over a designated lane of the multi-lane link and stripes words of the first plurality of words that belong to non-low-latency word categories over next available lanes of the multi-lane link; a receiver that receives a second plurality of words over the multi-lane link from a transmitter of the other integrated circuit; and a receiver controller that determines a word category of a word in the second plurality of words, responsive to a determination that the word is of the low-latency word category, reads the word from the designated lane before lane-to-lane deskew is completed, and responsive to a determination that the word is of a non-low-latency word category, reads the word received from the designated lane after lane-to-lane deskew is completed.

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Claim 9:
9. The integrated circuit of claim 1 , wherein the lanes of the multi-lane link have measurable latencies, and wherein the designated lane is configured for low-latency.