Patent Document ID: 8156452
Application ID: 11143003

Base Claim:
1. A method for importing a design in hardware description language (HDL) into a system designer, comprising: generating a function operable to specify a number of input and output ports that are in the design in HDL; setting a sample time for sampling signals of a simulation model, wherein the sample time is associated with a clock signal in the design in HDL; generating a simulation model template based on the function and the sample time rendering a plurality of selectable simulation model types; receiving a user selected simulation model type; and generating the simulation model from the simulation model template, wherein the simulation model is operable to be rendered in response to the user selected simulation model type, wherein at least one of the setting, rendering, receiving and generating procedures is performed by a computer.

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Claim 3:
3. The method of claim 1 , wherein the clock signal is user identifiable from the design in HDL.