Patent Document ID: 8863055
Application ID: 13972464

Base Claim:
1. A method to provide a capacitance to a design an integrated circuit comprising: receiving using a processor a layout of the integrated circuit; applying canonical hierarchical models to the layout, wherein the canonical hierarchical models include a first type canonical model representing a device having a plurality of first conductors to capture a first capacitance and a second type canonical model representing at least a portion of the device and one or more second conductors of the integrated circuit outside the device to capture a second capacitance; and determining a capacitance for the layout based on the applying.

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Claim 3:
3. The method of claim 1 , wherein the canonical hierarchical models include a third type canonical model to capture a third capacitance between the second conductors of the integrated circuit, and wherein the second type canonical model is configured to bridge the first type canonical model and the third type canonical model.