Patent Document ID: 9287893
Application ID: 14702420

Base Claim:
1. An integrated circuit, comprising: a decompression block that receives as input a compressed input stream made up of symbols in M words, each word having up to N symbols, where M and N are a positive integers, and that outputs an uncompressed output stream made up of an array of literals, the array of literals being original literals before compression; the decompression block is configured as a pipeline that includes a length module and a distance module, the length module evaluates a length for each symbol, the distance module resolves the distances in the at least one length-distance pair; the length module comprising: a shifter stage configured to store two consecutive words, and control a sliding window of S symbols, where S is a positive integer, in accordance with end word values in order to extract literals or distances, the end word values represent the number of uncompressed words between the start of the first symbol and the end of a current symbol; a mapper stage configured to receive the literals or distances from the sliding window and using end byte values map the literals or distances to positions in the output stream, the end byte values represent the absolute position in the output stream where a given symbol ends; the distance module comprising: a pointer replacement stage configured to replace distances, represented as pointers within an output word, with either literals or other pointers to prior words; a resolution stage configured to replace the other pointers with literals, and output literals and the replacement literals to the uncompressed output stream.

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Claim 5:
5. The integrated circuit of claim 1 , wherein the shifter stage uses the end word values to determine that remaining bits in the sliding window are read from the second of the two consecutive words, and to determine that a new word needs to be accepted from a prior stage.