Patent Document ID: 7881089
Application ID: 12392049

Base Claim:
1. A method for operating content addressable memory, the method comprising: providing a plurality of memory cells in parallel circuit, the memory cells being electrically coupled to a match line, the match line configured to receive a collective current from the memory cells during a memory search operation; receiving a data word of bit length L for storage in the memory cells; transforming the data word into a code word of bit length greater than L such that at least one code word bit in the code word depends on at least two data word bits in the data word, the code word guaranteeing a mismatch of at least two code word bits of different binary values during the memory search operation when the data word does not match a search word; and storing the code word in the memory cells.

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Claim 9:
9. The method of claim 1 , further comprising: receiving at the content addressable memory the search word of length L for comparison against the data word during the search operation; transforming at the content addressable memory the search word into a search code for comparison against the code word during the search operation; and determining if the collective current from the memory cells is below a threshold value during the memory search operation.