Patent Document ID: 7634396
Application ID: 10512611

Base Claim:
1. A method of creating a Bus Functional Model of an Integrated Circuit wherein said method comprising the steps of: (a) providing ( 102 ) a detailed specification of said Integrated Circuit, (b) defining ( 104 ) an architecture for said Bus Functional Model, (c) mapping ( 106 ) between said Integrated Circuit specification and said defined Bus Functional Model architecture wherein said Bus Functional Model architecture contains at least one of the following constructs: Interface Tasks ( 202 ), Internal Data Elements ( 204 ), Processes ( 208 ), Finite State Machines ( 210 ), Conditions ( 206 ), Actions ( 212 ), Signals ( 214 ), wherein the step of mapping comprises allocating a data from said Integrated Circuit specification to a respective construct of the at least one of the constructs, depending on what the data is related to, (d) Creating ( 110 ) formal description of said Bus Functional Model in a Formal Description Language in a computer readable form; wherein said Integrated Circuit specification is provided to a computer in computer readable form and steps (b) to (d) are performed automatically in said computer.

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Claim 2:
2. A method according to claim 1 further comprising the steps: (e) providing ( 112 ) said formal description of said Bus Functional Model (BFM) in a computer readable form to a computer; (f) providing ( 114 ) templates for generation of BFM in particular target language to said computer; (g) generating ( 116 ) BFM source code in said target language by applying said formal description on said templates; wherein steps (b) to (d) are performed automatically in said computer.