Patent Document ID: 8392666
Application ID: 12582591

Base Claim:
1. A hardware apparatus for detecting a load-store collision within a microprocessor between a load operation and an older store operation each of which accesses data in the same cache line, the apparatus comprising: a load byte mask that specifies which bytes contain the data specified by the load operation within a word of the cache line in which the load data begins; a store byte mask that specifies which bytes contain the data specified by the store operation within a word of the cache line in which the store data begins; a load word mask that specifies which words contain the data specified by the load operation within the cache line; a store word mask that specifies which words contain the data specified by the store operation within the cache line; and combinatorial logic, configured to use the load and store byte masks to detect the load-store collision if the data specified by the load and store operations begin in the same word of the cache line, and configured to use the load and store word masks to detect the load-store collision if the data specified by the load and store operations do not begin in the same word of the cache line.

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Claim 2:
2. The apparatus of claim 1 , wherein the number of bits of the byte masks is equal to the number of bytes of a word.