Patent Document ID: 7941771
Application ID: 12133085

Base Claim:
1. A method for on-demand functional verification by a computer processing system of a software model of an Application Specific Integrated Circuit (ASIC), comprising deploying the functional verification of the software model using a computer processing system, the computer processing system including a computer readable storage medium upon which is encoded a sequence of instructions, which when executed by the computer processing system, causes the following: forming, in a first mode, a first autonomous circuit emulator for the ASIC by automatically replacing a plurality of first instructions comprising a software model of the ASIC with a plurality of second instructions comprising the first autonomous circuit emulator; receiving stimuli at the first autonomous circuit emulator; generating, by the first autonomous circuit emulator, test response data based on the received stimuli; outputting, in a second mode for verification, the test response data generated by the first autonomous circuit emulator to a verification platform that includes the plurality of first instructions comprising the software model; operably coupling interfaces of the software model of the verification platform in parallel to a second previously-validated autonomous circuit emulator and to an environment emulator; validating the test response data output by the first autonomous circuit emulator by comparing the test response data with expected response data provided by the second autonomous circuit emulator of the verification platform; and outputting an error notification if said validation comparison does not match for debugging functional tests for the software model, wherein the first instructions are provided in accordance with a low-level programming language and comprise a physical description of the ASIC, and wherein the second instructions are provided in accordance with a high-level language and comprise an abstract description of data structures of the response data based on a functional specification of the ASIC design.

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Claim 3:
3. The method according to claim 1 , wherein the stored input stimuli sequences are specified using the high-level language, and wherein the functional specification is specified using the low-level programming language for specifying functional models of circuits.