Patent Document ID: 3938103
Application ID: 05452819

Base Claim:
1. An inherently microprogrammable high level language processor which includes an electrical interconnection with a storage device for executing an interpretable language string stored in said storage device, wherein said string includes machine level operation codes, and for executing one of a plurality of elementary language programs stored in said storage device, each program being represented by a machine level operation code, comprising: a. first extration means for extracting a machine level operation code via said electrical interconnection from said interpretable language string stored in said storage device for use in locating the one of the elementary language programs stored in said storage device which is represented by the extracted code; b. second extraction means for extracting an elementary language operation code via said electrical interconnection from said one elementary language program stored in said storage device; c. decoding means for decoding the extracted elementary language operation code; and d. logic means connected to said decoding means for executing the elementary operation which is represented by the elementary language operation code.

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Claim 3:
3. Apparatus as set forth in claim 1 wherein said first extraction means further comprises: a. first register means for providing a word address and a bit address within said word which indicates the machine level operation code in said interpretable language string to be extracted; b. second register means for receiving via said electrical interconnection with said storage device the stored word uniquely identified by said word address; and c. means for outputting the machine level operation code from the word in said second register means.