Patent Document ID: 5517637
Application ID: 08352934

Base Claim:
1. A method for testing a test architecture within a circuit, the method comprising the steps of: receiving circuit netlist information for the circuit where the circuit netlist information is stored via a circuit netlist data file in computer memory, the circuit netlist information including test architecture topology information of the test architecture; generating a boundary scan description of the test architecture based on the test architecture topology information wherein the boundary scan description describes various characteristics of the test architecture in a boundary scan description file stored in computer memory; selecting a test from a predetermined set of test methodologies for testing the test architecture to result in a selected test; generating test parameters for use with a logic simulation, the test parameters being based on both the boundary scan description and the selected test and being stored in the computer memory; and testing the test architecture with the logic simulation utilizing the test parameters and the test architecture topology information.

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Claim 2:
2. The method of claim 1 further comprises verifying the boundary scan description by verifying syntax, consistency, and standard compliance of the boundary scan description.