Patent Document ID: 10108767
Application ID: 15282627

Base Claim:
1. A computer implemented method for implementing deadlock detection with formal verification techniques in an electronic design, comprising: executing, at at least one deadlock detection module coupled to one or more micro-processors, a sequence of instructions to perform a process, the process comprising: identifying one or more inputs that include an initial state of an electronic design; identifying a deadlock candidate by searching at least a portion of a state space of the electronic design in a first formal search using formal verification techniques; reducing a total number of deadlock candidates into a reduced set of real deadlocks at least by determining, at the at least one deadlock detection module coupled to the one or more micro-processors, whether the deadlock candidate is a real deadlock using a second formal search with the formal verification techniques; and modifying the electronic design into a modified electronic design in a data structure at least by performing one or more fixes on the real deadlock.

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Claim 3:
3. The computer implemented method of claim 1 , identifying the deadlock candidate comprising: invoking one or more formal engines; and initiating the first formal search at the one or more formal engines.