Patent Document ID: 10120968
Application ID: 14958179

Base Claim:
1. A computer-implemented method for defining and processing hardware description language (HDL) groups for use with an electronic circuit design to be fabricated comprising: mapping, using a processor, one or more tool-specific objects into a group graph having one or more groups arranged as nodes in the group graph, wherein each of the one or more groups includes at least one sub-group, library information, and HDL design information, wherein the group graph is configured as a data structure; generating a search order associated with each of the one or more groups within the group graph, wherein the search order associated with each of the one or more groups is based upon, at least in part, a hierarchical design configuration of the group graph and wherein the search order is determined, based upon, at least in part, a command line structure; identifying one or more undefined references from within a first group of the one or more groups within the group graph; binding one or more defined references from within the first group to one or more electronic circuit design components; and identifying the one or more undefined references from within a second group of the one or more groups within the group graph, wherein the second group is selected based upon, at least in part, the one or more undefined references and the search order associated with the first group of the one or more groups.

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Claim 2:
2. The computer-implemented method of claim 1 , further comprising: acquiring the second group from the one or more groups of the group graph at least partially concurrently with the identification of the one or more undefined references.