Patent Document ID: 5581722
Application ID: 08311911

Base Claim:
1. A memory management unit for communicating with a CPU and a memory of a computer system to control said CPU's right to access said memory in order to initiate performance of an operation, wherein the memory comprises a single address space, said memory management unit comprising; a plurality of domains, each individual domain corresponding to an address-oriented service and a set of addresses in the single address space of the memory, wherein each address in the single address space is only associated with one of the plurality of domains; a plurality of environments, wherein an environment controls access by an associated task to the plurality of domains; a translator coupled to receive a virtual address signal and an access type signal issued by said CPU during execution of a task, wherein said translator translates said virtual address signal into a physical address signal and issues said physical address signal to said memory in order to initiate performance of said operation, and wherein said translator issues a domain number signal that indicates one of said plurality of domains in which said virtual address resides based on said virtual address, and further wherein said translator determines if faults occur during translation of said virtual address and issues a first fault indication if one or more faults occur during translation of said virtual address; and an environment controller coupled to receive said domain number signal, wherein said environment controller permits access by said task to said one of said plurality of domains if said one of said plurality of domains is within a set of allowed domains, said environment controller issuing a second fault indication if said domain number signal does not correspond to an allowed domain number, such that said CPU's right to access said memory is denied if said first fault indication, said second fault indication, or both said first fault indication and said second fault indication are generated.

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Claim 2:
2. A memory management unit as recited in claim 1, wherein said translator comprises: a domain classifier coupled to receive said virtual address signal for generating said domain number signal in response to a portion of the virtual address signal and issuing a domain fault indication if there is no domain number associated with said virtual address signal; an address translator coupled to receive said virtual address signal for translating said virtual signal into said physical address signal if a corresponding physical address exists, but issuing a translation fault indication if there is no physical address corresponding to said virtual address signal; and a permission translator for receiving said virtual address signal and said access type signal and translating said virtual address signal into a permission signal if an access type corresponding to said access type signal is allowed by a permission corresponding to said permission signal, but issuing a permission fault indication if said access type corresponding to said access type signal is not allowed by said permission.