Patent Document ID: 8677312
Application ID: 10815228

Base Claim:
1. A computer implemented method of generating a compiler description from an architecture description, comprising: extracting information from an architecture description describing an architecture, the extracted information including instruction latencies and data hazard information of the architecture resulting from temporal input/output behavior of instructions; transmitting instructions to present a graphical user interface; receiving, via an interaction with the graphical user interface, definitions for a plurality of abstract elements of a compiler that have no direct representative in the architecture description; extracting a mapping of compiler rules to instructions included in the architecture description; and automatically generating a compiler description of the compiler for the architecture based on the extracted information, the received definitions for the plurality of abstract elements, and the extracted mapping.

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Claim 5:
5. The method of claim 1 , wherein the extracted information describes a register of the architecture and through the graphical user interface, a user provides instructions to not use the register in generating the compiler description.