Patent Document ID: 7949851
Application ID: 11966919

Base Claim:
1. A system that facilitates access of at least one memory, comprising: the at least one memory that is configured to include a plurality of memory locations; and a memory controller component that is configured to generate and execute a configuration sequence, comprising at least two configuration sequence portions, in a specified order to facilitate performance of a logical block address to physical block address translation associated with the at least one memory based at least in part on the configuration sequence, wherein the configuration sequence is configured to comprise at least a first configuration sequence portion to facilitate performance of a first translation function of a plurality of available translation functions and a second configuration sequence portion to facilitate performance of a second translation function of the plurality of available translation functions, wherein the available translation functions comprise at least two of a calculation function, a table look-up function, or a search function, and wherein one of the calculation function, the table look-up function, or the search function is selected as the first translation function based at least in part on its higher efficiency in determination of a first translation attribute, which relates to the logical block address to physical block address translation, relative to efficiency of other of the available translation functions not selected as the first translation function.

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Claim 10:
10. The system of claim 1 , further comprising an initialization component that is configured to facilitate initialization of a configuration of at least one of the memory controller component or the at least one memory, and facilitates initialization of translation functions associated with the logical block address to physical block address translation.