Patent Document ID: 8555234
Application ID: 12553224

Base Claim:
1. A method for verification of soft error resilience of devices from design data for a logic design, comprising: selecting a statistically relevant set of Soft Error Rate (SER) sensitive logic devices deemed critical to a SER robustness for a test process of the logic design by using a SER categorization tool to generate a SER sensitive device test set, and further comprising: successively filtering the design data through a series of heuristic rule-based device identifiers that group and annotate the SER sensitive logic devices by parsing a netlist representing the logic design for identification nomenclature, device type and connectivity; selecting, grouping, and associating related devices for testing according to a list of predetermined SER sensitive device types; and reducing a number of the devices in the SER sensitive device test set based on symmetry of structures joined to a common bus and further reducing flow device vectors to scalars; and inducing a logic state fault in successive ones of said reduced number of devices in said test process of the logic design for functional design verification which provides a sufficient delay after injection for the logic design to detect a logic fault for those reduced number of devices in said test process; and providing logic fault information of said detected logic fault of said reduced number of devices to facilitate corrective action.

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Claim 5:
5. The method according to claim 1 wherein selecting a statistically relevant set of Soft Error Rate (SER) sensitive logic devices deemed critical to a SER robustness for a test process of logic design uses feedback of behavior of devices to further refine a set of SER devices for said test process.