Patent Document ID: 5414716
Application ID: 08107240
Patent Flag: 1

Claim One:
1. A system for reducing testing time of digital integrated circuits by decreasing the number of test vectors utilized while maintaining high fault coverage without deterministic testing, comprising: means for first determining all faults for a predetermined integrated circuit and for generating a set of calculated weights; means for testing said integrated circuit with said set of calculated weights for generating a reduced list of undetected faults; means for iteratively testing said integrated circuit with calculated weights from successively reduced lists of undetected faults by calculating additional weights directly from the reduced list of undetected faults from the previous iteration, said iteration to continue until a predetermined low number of undetected faults exists; a weighted pattern generator for producing test vectors coupled to inputs to said integrated circuit; and, means for applying said calculated sets of weights to said weighted pattern generator, thereby to provide said generator with an optimal set of weights that decrease the number of test vectors provided by said weighted pattern generator to reduce said testing time.