Patent Document ID: 9043194
Application ID: 10244434
Patent Flag: 1

Claim One:
1. A method of emulation in a multiprocessor system, said method comprising: receiving, on a processor of a host multiprocessor system, an instruction to be emulated of a target multiprocessor system, said host multiprocessor system having a memory barrier (mbar) instruction that guarantees that all results of all memory operations before executing said mbar instruction have been registered by all processors in said host multiprocessor system before registering any results of any later instructions; determining whether execution of said mbar instruction is required for said received instruction to be emulated before said received instruction is emulated; and selectively executing said mbar instruction, based on said determining, said selectively executing of said mbar instruction thereby permitting performing an emulation that is efficient, even in a condition in which the host multiprocessing system of said multiprocessor system supports a weak consistency model and the target multiprocessing system of the multiprocessor system supports a strong consistency model, by reason that said mbar instruction is executed for said received instruction only if said determining determines that said execution of said mbar instruction is necessary for emulating said received instruction.