Patent Document ID: 8006216
Application ID: 12134849
Patent Flag: 1

Claim One:
1. A computer-implemented method for routing topological interconnections for a package, the method comprising: receiving, using one or more processors associated with one or more computer systems, information associated with a chip; determining an escape routing of a bump array for the chip, the escape routing indicative of a set of I/Os along a set of escape boundaries; determining a set of obstructions on a set of package layers; determining a scale of via staggering pitches on the set of package layers; for each build-up layer in the set of package layers, from a top layer to a bottom layer: performing a topologically planar routing of each I/O in the set of I/Os to a location substantially vertical to a center of a corresponding ball, wherein at least a first net is dynamically pushed in response to the topologically planar routing of a second net, and transferring a stopping point associated with an I/O for a failed net to another build-up layer by stack vias; assigning vias for one or more successfully routed nets; analyzing a congestion associated with each build-up layer to generate a congestion map; and generating, with the one or more processors associated with the one or more computer systems, information indicative of a set of topological interconnections, the congestion map, and a set of fail-routed nets and storing the information in a storage device associated with the one or more computers systems.