Patent Document ID: 20020176281
Application ID: 09863697
Patent Flag: 0

Claim One:
1. A reading method for performing program verify, erase verify, and over-erase-correction verify modes of operations on a selected memory core cell in an array of Flash EEPROM memory core cells, said method comprising the steps of: applying a fixed control gate bias voltage to the control gate of a core cell transistor whose state is to be verified for generating a core cell drain current; applying varied control gate bias voltages to the control gate of a single reference cell transistor for generating different reference currents corresponding to predetermined modes of operations; and comparing a sensed voltage corresponding to the core cell drain current and a references voltage corresponding to one of said different reference currents and generating an output signal which is at a high logic when said sensed voltage is less than said reference voltage and which is at a low logic level when said sensed voltage is higher than said reference voltage.