Patent Document ID: 20150268293
Application ID: 13663258
Patent Flag: 0

Claim One:
1. A post-silicon validation method for debugging a semiconductor device with one or more observable connections, the method comprising: performing a test on the semiconductor device, wherein the test is associated with an expected test outcome and causes the semiconductor device to produce an actual output and one or more signals, wherein each signal is associated with an observable connection; logging a group of signatures for the signals; dividing the group of signatures into a passing group if the actual output conforms with the expected test outcome or a failing group if the actual output does not conform with the expected test outcome; determining a model of signal behavior for each of the one or more signals, wherein the model includes (i) a passing group band representative of mean passing group signature values over a plurality of time intervals, and (ii) a failing group band representative of mean failing group signature values over the plurality of time intervals; identifying a divergence for one or more signals where the failing band is outside the passing band by a threshold amount; and identifying (i) the signals associated with the failing band diverging outside of the passing band in excess of the threshold amount, and (ii) a time interval from among the plurality of time intervals associated with the divergence.