Patent Document ID: 20140164865
Application ID: 14236166
Patent Flag: 0

Claim One:
1. An apparatus comprising a processor configured to at least perform or cause the apparatus to at least perform: receiving a representation of a codeword that includes a plurality of bits; associating the bits with a respective plurality of one-bit hard-bit values and multiple-bit soft-bit values, the hard-bit values being initially set according to the representation of the codeword and representing the bits of the codeword, and the soft-bit values representing measures of reliability of respective hard-bit values; and updating at least some of the hard-bit values or soft-bit values of the bits including for each of a plurality of iterations, computing an updated hard-bit value or soft-bit value of one or more bits of a respective subset of the bits as a function of current hard-bit values of the bits of the subset, and the current hard-bit value and soft-bit value of the respective bit, wherein for two iterations in which the current hard-bit value for each bit of a subset of the bits for both iterations is the same, and in which the current soft-bit value for each bit of the subset for both iterations is the same, the updated hard-bit value or soft-bit value computed for any bit of the subset during one of the two iterations is the same as the updated hard-bit value or soft-bit value computed for the respective bit during the other of the two iterations.