Patent Document ID: 9015649
Application ID: 12838577
Patent Flag: 1

Claim One:
1. A method comprising: modeling a system block of a system-on-chip (SoC) in a computer-implemented untimed functional model at an untimed functional level; generating a computer-implemented transaction level (TL) model of the system block at a transaction level (TL) by reusing the untimed functional model, wherein generating the TL model includes encapsulating the untimed functional model in a wrapper logic module configured to modify an interface between the untimed functional model and an external memory module; generating a computer-implemented cycle accurate (CA) model of the system block at a cycle accurate (CA) level by directly reusing the TL model, wherein the CA level has cycle accuracy at SoC signal level using signal-level timing granularity of the SoC, and wherein generating the CA model includes encapsulating the TL model in a transactor module configured to communicate with the wrapper logic module and a CA bus; and verifying functionality of the SoC by operating a processor to execute a software program using at least one of the TL model and the CA model.