Patent Document ID: 9939488
Application ID: 14564004
Patent Flag: 1

Claim One:
1. A method for testing a semiconductor device, the method comprising: reading a pinmap file associated with the semiconductor device; for pins to be tested, creating a first test set comprising second individual tests that include a pin to ground curve trace, a checkerboard curve trace, an automatic pin to pin curve trace, and an interactive pin to pin curve trace; wherein the pins to be tested comprise a portion of a set of pins identified in the pinmap file; routing data channels associated with the semiconductor device to the pins to be tested; responsive to said routing, executing the first test set; accessing golden data associated with the semiconductor device; determining at least one allowable variance from the golden data responsive to a result of the execution of the first test set; detecting any of the pins of the portion of the set of pins whose curves exceed the allowable variance from the golden data, and flagging the detected pins as failing pins; running a selected one of the second individual tests on only the set of failing pins, wherein the selected test of the second individual tests comprises the automatic pin to pin curve trace; and for each pin in the set of failing pins, setting the pin to 0 and all other pins to X; defining the pin set to 0 as a reference pin; curve tracing each of the test pins relative to the reference pin; and presenting the test results to a screen display.