Patent Document ID: 6080201
Application ID: 09021135
Patent Flag: 1

Claim One:
1. A method for improving timing convergence in computer aided semiconductor circuit design, the method comprising the steps of: generating a behavioral model of a desired semiconductor circuit, the behavioral model including timing constraints for individual paths in the circuit; synthesizing the behavioral model to produce a netlist which represents an implementation of the desired semiconductor circuit mapped to a specific semiconductor technology, the netlist including a list of components in the circuit and a list of nets which connect the components in the circuit, the step of synthesizing including performing a timing analysis on the implementation set forth in the netlist so that the paths in the circuit represented by the netlist meet the timing constraints, the timing analysis being performed using estimated wire lengths for the nets; placing the components in the netlist into an image representing a predefined area of a semiconductor chip, the step of placing including determining actual wire lengths for the nets in the netlist; performing a timing analysis on the implementation set forth in the netlist using the actual wire lengths for the nets in the netlist; modifying the netlist in the event the timing analysis using the actual wire lengths indicates a violation of any of the timing constraints; placing the components in the modified netlist into the image representing the predefined area of the semiconductor chip, the step of placing the components in the modified netlist including determining actual wire lengths for the nets in the modified netlist; performing a timing analysis on the implementation set forth in the modified netlist using the actual wire lengths for the nets in the modified netlist; repeating the steps of modifying the netlist, placing the components in the modified netlist, and performing the timing analysis on the implementation set forth in the modified netlist using the actual wire lengths for the nets in the modified netlist until said timing analysis on the implementation set forth in the modified netlist indicates no violation of any of the timing constraints; and routing the circuit represented by the modified netlist after the timing analysis on the implementation set forth in the modified netlist indicates no violation of any of the timing constraints.