Patent Document ID: 20140114640
Application ID: 14142567
Patent Flag: 0

Claim One:
1. A method for simulating multiple processors in parallel, the method comprising: mapping, by a scheduler, debug interface information of a to-be-simulated processor requiring debugging onto the scheduler; creating, by the scheduler, at least one slave thread by using a master thread, and determining to-be-simulated processors corresponding to the master thread and the at least one slave thread, so as to obtain the determined to-be-simulated processors, wherein the to-be-simulated processors corresponding to the master thread comprise the to-be-simulated processor requiring the debugging; and invoking, by the scheduler, by using the master thread and the at least one slave thread via a first execute interface, the determined to-be-simulated processors to execute a corresponding instruction, and debugging the to-be-simulated processor requiring debugging by using the master thread via a debug interface of the to-be-simulated processor requiring debugging, wherein the first execute interface registers with the scheduler through the determined to-be-simulated processors, and the debug interface information points to the debug interface.