Patent Document ID: 3934231
Application ID: 05446968
Patent Flag: 1

Claim One:
1. A digital logic circuit, hereinafter referred to as an element, which is a basic building block of learning machines formed by interconnection of a plurality of said elements into a network, which network under the control of an agent hereinafter referred to as a control unit, during a training period can learn a boolean function of n variables, the latter applied by said control unit through a scheme of multiple connections and connections with inversion to certain inputs of said network, the action of each said element in forming the relationship between the said n variables and the network output being to process information as a two-input, one-output combinational circuit the logical operation of which depends on the internal state of said element, which internal state may be altered by the control unit's applying a training procedure to said network; and which element comprises: input-and-output means comprising a first input lead, hereinafter referred to as the left input lead, a second input lead, hereinafter referred to as the right input lead, and an output lead; control signal input means for receiving control signals, comprising a clock lead and a desired network output lead; heuristic responsibility input-and-output means comprising a heuristic responsibility input lead, a left heuristic responsibility ouput lead, and a right heuristic responsibility output lead; output computation means; a first function value unit means; a second function value unit means; a first heuristic responsibility unit means, hereinafter also referred to as the left heuristic responsibility unit means; a second heuristic responsibility unit means, hereinafter also referred to as the right heuristic responsibility unit means; and interconnection means for connecting the aforementioned means as hereinafter required comprising direct connections and connections through inverters; whereby said output computation means is a combinational circuit receiving signals from said left input lead, said right input lead, said first function value unit, and said second function value unit, and sending its output signal directly to said output lead via said interconnection means, the value of said output signal being equal to xy + xyv.sub.10 + xyv.sub.01, where x is the value on said left input lead, y is the value on said right input lead, v.sub.10 is the value of the output of said first function value unit means, and v.sub.01 is the value of the output of said second function value unit means; and whereby said first and second function value unit means are connected via said interconnection means to said control signal input means; and whereby said first function value unit means can change its internal state, which determines its output, only when a clock pulse occurs on said clock lead while x is ONE and y is ZERO, and said second function value unit means can change its internal state, which determines its output, only when a clock pulse occurs on said clock lead while x is ZERO and y is ONE; and whereby the output of said first heuristic responsibility unit means is connected via said interconnection means directly to said left heuristic responsibility output lead, and the output of said second heuristic responsibility unit means is connected via said interconnection means directly to said right heuristic responsibility output lead; and whereby a change of state of said first and second function value unit means and said first and second heuristic responsibility unit means may occur only at the occurrence of a clock pulse on said clock lead while the value on said heuristic responsibility input lead is a certain fixed value indicating "heuristic responsibility" of said element for the current input n-tuple presented to the machine during training.