Patent Document ID: 10146286
Application ID: 14995263
Patent Flag: 1

Claim One:
1. A processor comprising: a plurality of cores; and a power controller coupled to the plurality of cores, the power controller including: a first hardware logic to receive performance monitoring information from at least some of the plurality of cores and determine, according to a power management model, a performance state for one or more of the plurality of cores based on the performance monitoring information and communicate digital information to at least one voltage regulator to cause the at least one voltage regulator to provide an updated voltage for the performance state to the one or more of the plurality of cores; and a second hardware logic to receive the performance monitoring information from the at least some of the plurality of cores and dynamically update the power management model according to a reinforcement learning process, wherein the second hardware logic is to cause the first hardware logic to update the performance state for the one or more of the plurality of cores randomly for a first portion of evaluation intervals and according to the power management model for a remaining portion of the evaluation intervals.