Patent Document ID: 20020190745
Application ID: 09845384
Patent Flag: 0

Claim One:
1 ) A method for determining P/N ratios in static logic gates comprising: a) identifying directly-connected FETs of a first type connected to an output node; b) identifying directly-connected FETs of a second type connected to said output node; c) identifying branches of a first type created by said first type FETs connected to said output node; d) identifying branches of a second type created by said second type FETs connected to said output node; e) selecting an allowable input voltage; f) storing width values of all said first type FETs activated by said chosen input values; g) storing width values of all said second type FETs activated by said chosen input values; h) determining an effective width of said stored width values in step (f); i) determining an effective width of said stored width values in step (g); j) dividing the effective width in step (h) by the effective width in step (i); k) repeating steps (e) through (j) until all possible input voltage combinations have been exhausted.