Patent Document ID: 10068306
Application ID: 14574606
Patent Flag: 1

Claim One:
1. An apparatus comprising: a processing device coupled to memory, wherein the processing device facilitates: coalescing kernels logic to generate a command buffer having a plurality of kernels relating to a plurality of workloads to be processed by a graphics processor; dependency checking logic to check, in runtime, availability of resource threads of the graphics processor that remain idle due to one or more pending dependency contingencies associated with one or more kernels of one or more workloads in relation to other kernels of the plurality of kernels of the command buffer; and state management logic to acquire, in runtime, one or more idle resource threads to facilitate pipelining of other workloads in parallel execution based on the other kernels that do not have one or more pending dependency contingencies, wherein the other workloads are processed by the graphics processor using the one or more idle resource threads without having to stall the graphics processor for processing of the one or more workloads based on the one or more kernels and without seeking resolution of the one or more pending dependency contingencies associated with the one or more kernels, and wherein the state management logic is further to set up interface descriptors for the plurality of kernels prior to processing the respective kernel and wherein the dependency checking logic checks availability, in part, by loading a descriptor by returning the data last written by the respective kernel, and wherein the state management logic pushes a write cycle in a pipelined workload based on a subsequent read as determined using a respective interface descriptor.