Patent Document ID: 6122320
Application ID: 09180781
Patent Flag: 1

Claim One:
1. Circuit for motion estimation in a video encoder intended to encode a sequence of digitised pictures, which circuit receives aggregates of pixels of a current picture and, for each of said aggregate of pixels (hereinafter referred to as `current aggregate`), generates one or more vectors representing the displacement of said aggregate with respect to a corresponding aggregate of pixels (hereinafter referred to as `reference aggregate`) in a search window belonging to a reference picture, characterised in that it comprises at least one integrated circuit component (IM; IM1. .. IMn) including: at least a pair of operating units (M1, M2) which are independently programmable and are arranged to concurrently process different data of the current picture and of the search window according to a multiple instruction, multiple data processing technique, to perform one of the following functions: determination of a set of candidate motion vectors for each current aggregate and of an estimation error associated with each candidate vector, each vector in the set being the vector associated with the lowest estimation error for a given prediction mode chosen within a pre-defined set of prediction modes identifying a reference aggregate that best matches the current aggregate; vector refinement, for improving the identification of the best-matching reference aggregate by effecting a further search in a limited portion of the window itself and by weighting each candidate vector by a weight associated with the amount of bits required for transmitting the vector itself; a first internal bus (15), to which said operating units (M1, M2) are connected and which is intended for transferring to the component (IM; IM1. .. IMn) programming and initialisation information or processing parameters coming from an external controller (CP), for conveying monitoring information from the component (IM; IM1. .. IMn) to said external controller and for allowing information exchange between different units in the circuit; a second internal bus (16), to which said operating units (M1, M2) are connected and which is intended for conveying video data, processing parameters and vectors associated with the relevant errors obtained as processing result, which are to be written into an external memory (SD) associated with the component (IM, IM1. .. IMn) or which are read from said external memory (SD); first interface means (IC) for connecting said first internal bus (15) to a line (12) for information exchange between the component (IM; IM1. .. IMn) and said external controller (CP); second interface means (B1. .. B3, IB) for connecting said second internal bus (16) to input/output lines (6. .. 10) conveying to the component (IM; IM1. .. IMn) or outputting from the component (IM; IM1. .. IMn) video data, processing parameters and processing results; third interface means (IS) for connecting said second internal bus (16) to a line (11) conveying video data, processing information and vector/error pairs to and from said external memory (SD), and for controlling the access to the external memory (SD); an internal controller (GC), which is connected to said first and second internal buses (15, 16) and which has to: identify and enable circuit units concerned by a data transfer over said second bus (16); allot different portions of a processing cycle to different units; generate and distribute the general synchronisation to the circuit units; control the global flow of operations in the circuit; synchronise the internal circuit activity with an external synchronisation; and initiate the operations of the operating units (M1,M2).