Patent Document ID: 5448713
Application ID: 08218958
Patent Flag: 1

Claim One:
1. A semiconductor device for an operation processing, comprising: a first storage area including a plurality of first memory cells disposed in rows and columns for storing first data in a first bit mapping, said first data representing a first relationship between a first input signal and a first output signal, said first storage area receiving the first input signal as a column designating signal and generating the first output signal as a row designating signal, said plurality of first memory cells transferring signal potentials according to storage data onto associated rows in response to the first input signal; a second storage area including a plurality of second memory cells disposed in rows and columns for storing second data in a second bit mapping, said second data representing a second relationship between a second input signal and a second output signal, said second storage area receiving the second input signal as a column designating signal and generating the second output signal as a row designating signal, said plurality of second memory cells transferring signal potentials according to storage data onto associated rows in response to the second input signal; and means responsive to signal potentials on individual rows of said first and second storage area for determining a relationship in magnitude between the first and second output signals.