Patent Document ID: 20030115563
Application ID: 10313866
Patent Flag: 0

Claim One:
1. A method of processing an integrated circuit (IC) layout design describing a victim net of an IC as having a plurality of sections and describing at least one aggressor net of the IC as having a plurality of sections, wherein at least one aggressor net section is proximate to at lest one victim net section, wherein the method estimates peak crosstalk noise in a an output signal of the victim net, the method comprising the steps of: a. processing the IC layout design to generate a separate model representing each aggressor net section that is proximate to a section of the victim net; b. processing the IC layout design to generate a crosstalk model for the victim net, wherein the crosstalk model includes a separate section corresponding to each victim net section modeling an impedance of its corresponding victim net section, and wherein each crosstalk model section corresponding to a section of the victim net that is proximate to an aggressor net section also includes the model of that aggressor net section generated at step a; c. evaluating the crosstalk model to determine a behavior of the output signal in response to an input signal applied as input to the victim net; and d. estimating the peak crosstalk noise from the behavior of the output signal determined at step c.