Patent Document ID: 4228518
Application ID: 05945736
Patent Flag: 1

Claim One:
1. A microprocessor having circuitry for multiplying or dividing, comprising: an arithmetic and logic unit; a first register for holding a multiplier and for holding a least significant portion of a binary number to be divided and for containing a quotient upon completion of a division; a second register for holding a most significant portion of a product obtained from a multiplication routine and for holding the most significant portion of the binary number to be divided and for storing a remainder obtained from a divide routine, the second register being coupled to the arithmetic and logic unit; a shift network coupled to the arithmetic and logic unit and coupled to the first and second registers for shifting data outputted by the arithmetic and logic unit; logic circuitry coupled to the arithmetic and logic unit and to the first register for controlling the multiplying and dividing; and a counter coupled to the logic circuitry for counting microprocessor clock cycles elapsed during multiplication and during division.