Patent Document ID: 20020112207
Application ID: 10073389
Patent Flag: 0

Claim One:
1. A fault propagation path inference system for inferring a logic state in a combinational logic circuit by repeating logic state decisions and implications and comparing the logic state with an expected value, which corresponds to a logic state that prevails when the combinational logic circuit operates normally, thereby inferring a fault propagation path in the combinational logic circuit, comprising: decision-limit discrimination means for providing an upper limit on a decision level that represents a number of logic state decisions and, if the number of logic state decisions exceeds the upper limit on the decision level, switching the logic state decision to simple retrieval of a fault propagation path; and fault propagation path simple retrieval means for extracting a fan-in cone by tracing a net-list of the combinational logic circuit in an input direction from an undetermined gate whose output signal is faulty and whose input/output signal lines have a signal line the logic state of which is unknown, and registering, as a fault propagation path, a signal line, which is included in the fan-in cone, the logic state of which has not been decided.