Patent Document ID: 9092591
Application ID: 14249765
Patent Flag: 1

Claim One:
1. A method, in a data processing system comprising at least one processor and at least one memory, for pruning a layer trait library for use in wire routing in an integrated circuit design process, comprising the following operations performed by the data processing system: receiving a plurality of wirecodes and a metal stack definition; generating a verbose layer trait library based on all possible combinations of the wirecodes and layers of the metal stack definition, wherein generating the pruned layer trait library comprises: pruning the verbose layer trait library to remove redundant layer traits to generate a first pruned layer trait library, wherein pruning the verbose layer trait library to remove redundant layer traits comprises: identifying layer traits in the verbose layer trait library having a similar resistance-capacitance (RC) characteristic to generate one or more layer trait groups having a similar RC characteristic; and selecting a representative layer trait from each group of the one or more layer trait groups to represent the layer traits in the group to be included in the first pruned layer trait library; performing clustering of layer traits in the first pruned layer trait library; and pruning the first layer trait library based on the clustering of layer traits in the first pruned layer trait library to generate a second pruned layer trait library; generating a pruned layer trait library by pruning the verbose layer trait library to remove redundant layer traits from the verbose layer trait library; storing the pruned layer trait library for performing wire routing of an integrated circuit design; and fabricating an integrated circuit device based on the integrated circuit design, including the wire routing performed based on the stored pruned layer trait library.