Patent Document ID: 8949759
Application ID: 14071159
Patent Flag: 1

Claim One:
1. A method of configuring an asynchronous reconfigurable logic fabric for use in an integrated circuit, the method comprising: providing an electronic design tool; configuring the electronic design tool to operate in accordance with asynchronous dataflow representations, the asynchronous dataflow representations being selected from a group comprising at least one of merge, copy, function, split, sink, source, or initiate; and using the electronic design tool to configure an embedded array comprising asynchronous logic elements that include one or more of the asynchronous dataflow representations, said asynchronous logic elements being programmable to carry out logic operations on signals provided at asynchronous logic element inputs and to asynchronously provide operation results at asynchronous logic element outputs, and said asynchronous logic elements include at least one multiplier unit coupled to at least one memory unit.