Patent Document ID: 4716564
Application ID: 06798649
Patent Flag: 1

Claim One:
1. A method for determining a group of test vectors for testing an integrated circuit network including a plurality of gates interconnected at nodes including input reveal a predetpermined categoriyu of faults in said network, and output terminals of said integrated circuit network to reveal a predetermined category of faults in said network, comprising the steps of: measuring the testability of said integrated circuit network according to a test counting procedure including propagation of sensitivity test counts forwardly from input terminals to a principal output terminal and rearwardly back to said input terminals through gates between said input and output terminals of said network to provides test count matrices for the nodes of said network including said input and output terminals, enumerating the test counts from said matrices by driving individual sensitivity values from test count matrices at said input terminals forwardly to a said output terminal and rearwardly back to said input terminals in a number of successive passes in order to accumulate the test counts described by said matrices at said nodes, and separately storing a set of sensitivity values to which said input terminals are driven for each such pass, each set comprising a test vector for said network.