Patent Document ID: 20050102596
Application ID: 10706228
Patent Flag: 0

Claim One:
1. A system for providing coverage analysis of functional verification of integrated circuit designs comprising: a) a test generator that creates test programs using machine readable test attribute specifications; b) a simulator that compares the test programs against the simulated behavior of design models; c) a database containing the traces of the simulation generated by the verification process; d) a program for mining and analyzing the simulation database; e) a database of all test programs generated by the test generators and engineers; f) a program for mining and analyzing the test program database; g) a database of all functional coverage analysis data and coverage model results; h) a program for mining and analyzing the functional coverage database; i) a program for analysis and monitoring of the coverage models; j) a program for automatic test spec generation from design HDL; k) a program for test spec adjustment and optimization; l) a coverage analysis program for creating architectural coverage models of the test programs; and m) functional coverage database for storage of the created coverage models.