Patent Document ID: 4156920
Application ID: 05811731
Patent Flag: 1

Claim One:
1. A digital electronic computing system architecture for performing a discrete Fourier Transform on a plurality (N) of electrical input signals, wherein N is selected to be factorable into a plurality of mutually prime factors (n.sub.l) chosen from the group 2, 3, 4, 5, 7, 8, 9, 13 and 16, said system incorporating a nested loop solution method characterized by performing only vector additions and subtractions in the outer loops and scalar additions, subtractions and multiplies in the innermost loop, each loop operation being controlled by a unique control mechanism, dedicated to each said loop, said system comprising a system parameter read only memory for storing system constants related to the permissible factors 2, 3, 4, 5, 7, 8, 9, 13 and 16, and an allowable values of N table, a system random access memory for storing precomputed constants to be used during the actual transform evaluation procedure, and a data random access memory for storing the input and output data signals and intermediate results computed during the transform operation, an arithmetic and logic unit for performing the requisite additions, subtractions and multiplications, comprising the transform operations, input and output registers for storing data input to, and to be output from, the system while being transformed into and out of the data memory, a plurality of working registers for storing the intermediate results of the arithmetic and logic unit, and control unit means for effecting the transfer of data into and out of said system, into and out of said memories and for controlling operations of the arithmetic and logic unit to effect individual loop operational sequences which perform the said nested loop Fourier Transform operation, means for automatically transferring control from one operational sequence in said control unit to another whenever loop transitions are called for, said last named means comprising a decoder which recognizes an apparent multiply operation whenever such is encountered during an outer loop operational sequence, further means resident in said control unit for performing the evaluation of the Fourier Transform of the input signal vector utilizing said precomputed system constants, and means to selectively perform as many Fourier Transforms of successive different N-dimensioned input signal vector sets as desired utilizing the same precomputed system constants.