Patent Document ID: 20150199266
Application ID: 14157040
Patent Flag: 0

Claim One:
1. A three-dimensional (3D) integrated circuit (3DIC) memory chip, comprising: at least one memory layer comprising a primary memory configured to store data; a plurality of vertical interconnect access structures (VIAs) interconnected with the primary memory; and a computational logic-in-memory (LiM) layer comprising at least one LiM block, the at least one LiM block comprising: local memory interconnected with functional logic units to process the data from the primary memory that is accessed through the VIAs; wherein the functional logic units are configured to: load one or more data subsets of the data from the primary memory over the VIAs into the local memory; access the one or more data subsets loaded into the local memory; computationally process the one or more data subsets accessed from the local memory to generate a computational result; and store the computational result.