Patent Document ID: 8316336
Application ID: 12643813
Patent Flag: 1

Claim One:
1. A non-transitory computer accessible medium having stored thereupon a program which, when executed by at least one processor, causes the at least one processor to implement a method for modeling interconnects for integrated circuit designs using a test structure, the method comprising: forming the test structure with variations in at least some of the at least three local interconnects or of the at least three distant interconnects, and forming an interconnect model based at least in part upon an effect, which is determined by using the at least one processor, of the variations on the test structure, wherein the test structure comprises: at least three local interconnects; and at least three distant interconnects on either side of the at least three local interconnects that are on a same layer as the at least three local interconnects, in which the at least three local interconnects are associated with a first local interconnect width value and a first local interconnect spacing value, and a first distant interconnect of the at least three distant interconnects is associated with a first distant interconnect width value and a first distant interconnect spacing value, and either or both of the first local interconnect width value and the first local interconnect spacing value are different from the first distant interconnect width value and the first distant interconnect spacing value.