Patent Document ID: 9875326
Application ID: 14959121
Patent Flag: 1

Claim One:
1. A method, in a data processing system comprising a processor and a memory coupled to the processor, for addressing coupled noise-based violations, the method comprising: for each net in an integrated circuit (IC) design with coupled noise-based violations, determining, by the data processing system, whether an associated delta wire delay is below a predetermined threshold; responsive to the associated delta wire delay failing to be below the predetermined threshold, forming, by the data processing system, a subset of nets; sorting, by the data processing system, the subset of nets by endpoints affected by each net thereby forming sets of nets with common affected endpoints; and for each set of nets with a common affected endpoint in the sets of nets with common affected endpoints: identifying, by the data processing system, a net in the set of nets with a common affected endpoint having a largest noise impact; adjusting, by the data processing system, a stage delay side model of the net to emulate a noise impact on timing of the net; applying, by the data processing system, an optimization using the stage delay side model of the net before applying optimization to the other nets associated with the common endpoint; determining, by the data processing system, whether the optimization has improved an overall delta wire delay of the common affected endpoint; responsive to the optimization degrading the overall delta wire delay of the common affected endpoint, backing out, by the data processing system, the applied optimization; responsive to the optimization improving the overall delta wire delay of the common affected endpoint, determining, by the data processing system, whether the optimization has improved an overall delta wire delay of the common affected endpoint to be greater than or equal to zero; responsive the optimization failing to improve the overall delta wire delay of the common affected endpoint to be greater than or equal to zero: performing, by the data processing system, a full retiming of the set of nets with a common affected endpoint; and repeating, by the data processing system, the identifying, adjusting, applying, and determining for the set of nets with a common affected endpoint; and responsive to the optimization improving the overall delay of each of the sets of nets with common affected endpoints to be greater than or equal to zero, outputting, by the data processing system, an integrated circuit design without coupled noise-based violations for fabricating an integrated circuit according to the integrated circuit design without coupled noise-based violations.