Patent Document ID: 20030115568
Application ID: 10354636
Patent Flag: 0

Claim One:
1. A method for designing, fabricating, testing and interconnecting an integrated circuit (IC) to external circuit nodes, the method comprising the steps of: a. providing a cell library including a plurality of component cells and a plurality of interconnect component cells, wherein each component cell corresponds to a separate IC component and includes a structural model and a behavior model of its corresponding IC component, wherein each interconnect component cell corresponds to a separate component of an interconnect system forming a signal path between at least one internal circuit node of the IC and at least one external circuit node, wherein each interconnect component cell includes structural and behavioral models of its corresponding interconnect system component, and wherein at least one of said interconnect component cells corresponds to a interconnect system component that is external to said IC; and b. selecting IC components to be included in said IC and selecting components of a plurality of interconnect systems to provide signal paths between said IC and an external circuit node by selecting corresponding ones of said plurality of component cells and interconnect component cells.