Patent Document ID: 20100017774
Application ID: 12439132
Patent Flag: 0

Claim One:
1. A system that is generative configuration data for reconfiguring a reconfigurable device, wherein the device includes a plurality of processing elements and a routing matrix for connecting the plurality of processing elements and is reconfigured by changing functions of respective processing elements in the plurality of processing elements and/or changing at least some connections of the routing matrix, the plurality of processing elements are divided into a plurality of groups, processing elements included in each group are connected in a range of a first delay by a first-level routing matrix included in the routing matrix, and processing elements included in different groups are connected with a different delay to the first delay via a second-level routing matrix included in the routing matrix, and the system comprises: a database for storing hardware information that includes definition data for the plurality of processing elements included in respective groups and definition data for the routing matrix; and a mapping apparatus that is generative a mapping of a circuit design onto the plurality of processing elements for implementing the circuit design in the device by the configuration data, wherein the mapping apparatus generates the mapping of the circuit design onto the plurality of processing elements by carrying out an iterative algorithm that minimizes a cost function based on the hardware information, the cost function including an item that minimizes usage of the second-level routing matrix.