Patent Document ID: 20170344372
Application ID: 15220986
Patent Flag: 0

Claim One:
1. A method of power management in a computer processor, the computer processor comprising a branch prediction unit, the branch prediction unit comprising a local branch predictor and a plurality of global branch predictors, the method comprising: for each of a plurality of branch instructions: performing, by the local branch predictor, a local branch prediction; performing, by each of the global branch predictors, a global branch prediction; determining to utilize the local branch prediction over the global branch predictions as a branch prediction for the branch instruction; incrementing a value of a counter; determining whether the value of the counter exceeds a predetermined threshold; and if the value of the counter exceeds the predetermined threshold, powering down at least one of the global branch predictors and configuring the branch prediction unit to bypass the powered down global branch predictor for branch predictions of subsequent branch instructions.