Patent Document ID: 6052524
Application ID: 09079448
Patent Flag: 1

Claim One:
1. A hardware-software design verification system, the system comprising: a cycle-accurate simulator that simulates hardware and software components in a desired electronic device, wherein X-number of simulator cycles correspond to Y-number of cycles on a simulated hardware component, wherein the cycle-accurate simulator is event-driven, and events are used to determine timing behavior and interactions of simulated hardware and software components in the desired electronic device; a simulator library including a plurality of built-in routines for modeling and verifying internal and external hardware components for a desired electronic device, wherein the simulator library allows internal and external hardware components to be modeled and verified with the plurality of built-in routines and wherein one or more of the plurality of built-in routines return a number of cycles executed on the cycle-accurate simulator during a simulated operation; a simulator extension application programming interface that provides an interface to the plurality of built-in routines in the simulator, wherein the simulator application programming interface also allows external and internal hardware components to be modeled with user-customized routines used with the cycle-accurate simulator.