Patent Document ID: 10120685
Application ID: 14932672
Patent Flag: 1

Claim One:
1. An apparatus comprising: a plurality of processing elements, each processing element (PE) comprising a hardware device providing a runtime mechanism for executing program code instructions including a loop, a single PE concurrently running multiple iterations of the same loop and prioritizing execution of instructions such that instructions of an oldest iteration of said same loop for which all data dependencies are satisfied are selected for processing; and a load and storage unit (LSU) including multiple banks of load storage queues (LSQ) operatively coupled with said plurality of PEs for receiving and storing load instructions and store instructions issued by the PEs associated with the multiple iterations of the same loop and enabling completion of iterations in order, wherein each PE comprises: a pluralilty of register files, each register file for storing temporary results of a computation or results of a load and/or store operation, wherein said plurality of register files comprises: local register files for storing variable data that is passed across a commit boundary, a commit boundary being defined a loop entry, iteration boundary, and loop exit points; and output register files for storing register data that is consumed within a commit boundary, and said local register files are organized according to multiple logical banks, wherein one logical bank of said multiple banks is configured to hold data used by all iterations, n logical banks of said multiple banks configured to hold data for n concurrent iterations in flight, and one bank is configured for storing data of a last committed iteration, said PE implementing a rotating head pointer to point to a first bank associated with an oldest iteration of an innermost loop, wherein upon committing the oldest iteration, said PE starting a new iteration, and for a new iteration started, a new oldest iteration corresponds to a second bank, and moving said pointer to point to said second bank, wherein said pointer rotates to always point to a bank associated with an oldest iteration amongst said n logical banks; and an execution control unit (ECU) for synchronizing operations performed at each said PE and the LSU including tracking of the iterations that have completed, which iterations are already running, and which iterations are yet to begin, the ECU for communicating signals to and receiving signals from each PE and LSU to synchronize initiating and completing of said multiple concurrent iterations on all or a sub-set of the plurality of PEs.