Patent Document ID: 8464126
Application ID: 12674492
Patent Flag: 1

Claim One:
1. An LDPC (low density parity check) decoder comprising: a plurality of check nodes and a plurality of variable nodes; each of the check nodes functionally connected to receive a respective at least one APPR (a posteriori probability ratio) message from at least one variable node, each of the check nodes comprising processing circuitry that performs check node processing using the received at least one APPR message and outputs at a respective APPD (a posteriori probability difference) message to at least one variable node; each of the variable nodes functionally connected to receive a respective at least one APPD message from at least one check node and to receive an intrinsic input, each of the variable nodes comprising variable node processing circuitry that performs variable node processing using the received at least one APPD message and the intrinsic inputs and outputs a respective APPR message to at least one check node; wherein the LDPC decoder is implemented using at least one of: a first circuit for each variable node and a second circuit for each check node with physical interconnections between the nodes for message passing; a processor with instructions to implement the functionality of the check nodes and the variable nodes.