Patent Document ID: 8799880
Application ID: 13420691
Patent Flag: 1

Claim One:
1. A programmable logic controller (PLC) for executing a program written in one or more high-level functional languages, the controller comprising a plurality of resources for executing various portions of the program; and a compiler including a processor and non-transitory computer readable media containing instructions that, when executed by the processor, perform functional parallelism by: parsing the program into a plurality of program organization units (POUs); identifying blocks within the high-level functional languages of each POU that include one or more time delay functions that delay an output by one execution cycle, such that operations before and after the time delay functions can be executed in parallel; partitioning at least one of the blocks into first and second program fragments by separating at an identified time delay function, the first and second fragments comprising operations before and after the identified time delay function, respectively; and scheduling the first and second program fragments across separate processor resources of the plurality of resources to be executed concurrently.