Patent Document ID: 6125416
Application ID: 08960757
Patent Flag: 1

Claim One:
1. A single chip integrated circuit device comprising: a bus system for effecting communication of parallel data on chip; functional circuitry connected to said bus system for executing an operation in response to parallel data received from said bus system; an external port comprising a serial data input connector and a serial data output connector for supplying serial data packets between an external device and the integrated circuit device, said serial data packets each including a packet identifier indicating the length of the data packet and information defining an operation to be executed by said functional circuitry; and a serial to parallel data packet converter interconnecting said parallel bus system and said external port and operable to read the packet identifier to determine the length of serial packets which are input through said port and to convert them into parallel data for supply in a forward direction to said bus system such that if the serial data packet has a length which exceeds the bus width, the serial data packet is converted into successive sets of parallel data and placed sequentially on the bus system, said serial to parallel converter further comprising flow control logic for indicating that it is ready to receive a subsequent data packet by transmitting a flow control signal in the reverse direction, and for requesting access to the bus system when the parallel data is ready to be output to the functional circuitry, wherein the serial to parallel conversion of the serial packets into parallel data is effected without involving the functional circuitry, and wherein the parallel data causes the functional circuitry to execute an operation dependent on said information contained in the serial packets from which it has been converted.