Patent Document ID: 9317636
Application ID: 11637374
Patent Flag: 1

Claim One:
1. A method for debugging an electronic hardware design, the electronic hardware design comprising a plurality of simulated hardware modules configured to operate in parallel and having a simulated state, the method comprising: receiving, during execution of a simulation of the simulated hardware modules, a plurality of simulation stop requests requesting stoppage of the simulation from a plurality of simulation stoppers associated with a plurality of debuggers for the simulated hardware modules, the simulation stop requests including a first simulation stop request corresponding to a first simulated hardware module and generated in response to hitting of a breakpoint during execution of the simulation, the simulation stop requests including a second simulated stop request corresponding to a second simulated hardware module and generated during execution of the simulation; responsive to receiving the simulation stop requests including the first simulation stop request and the second simulation stop request, creating a plurality of active simulation stopper entries for the plurality of simulation stoppers in a list of active simulation stoppers; reaching a synchronization point of the simulation that is subsequent to the simulation stop requests, the simulated state of the simulation hardware modules being synchronized at the synchronization point; at the synchronization point of the simulation, stopping the simulation and repeatedly performing the following steps until the list of active simulation stoppers is empty: executing a corresponding investigative agent for the corresponding active simulation stopper entry; removing the corresponding active simulation stopper entry from the list of active simulation stoppers; and continuing the simulation responsive to the list of active simulation stoppers being empty.