Patent Document ID: 20090307548
Application ID: 12133830
Patent Flag: 0

Claim One:
1. A method for performing a logic built-in self-test (LBIST) of an integrated circuit comprising a plurality of scan chains selectively driven by design-for-test logic supporting LBIST and functional combinational logic, said method comprising: performing a flush and scan test to determine whether each of said plurality of scan chains functions correctly; in response to a determination that one of said plurality of scan chains does not function correctly, terminating said logic built-in self-test; in response to a determination that each of said plurality of scan chains functions correctly, performing a structural test of said design-for-test logic to determine whether said design-for-test logic functions correctly; in response to a determination that said design-for-test logic does not function correctly, terminating the logic built-in self-test; in response to a determination that said design-for-test logic functions correctly, performing a level sensitive scan design test of said functional combinational logic using said design-for-test logic to determine if said integrated circuit functions correctly.