Patent Document ID: 20020196809
Application ID: 09841209
Patent Flag: 0

Claim One:
1. A method for dynamically multiplexing a plurality of signals &lsqb;S 1,S 2,...,Sn&rsqb; onto a driven conductor line within the interconnect &lsqb; 101, 102 &rsqb; of an FPGA, where said FPGA &lsqb; 100 &rsqb; has variably granulatable building elements &lsqb; 124 - 126 &rsqb; that may be folded-together during configuration to define differently-sized dynamic multiplexers, said method comprising the steps of: (a) using a first subset of the variably granulatable building elements of the FPGA during configuration to implement a first dynamic multiplexer &lsqb; 124 a &rsqb; of a first size that is minimally sufficient for dynamically selecting one signal from among said plurality of signals; and (b) configuring a first coupling &lsqb; 711 / 712 &rsqb; for coupling the selected one signal &lsqb; 761 &rsqb; or a derivative &lsqb; 765 &rsqb; thereof to said conductor line &lsqb;Bp&rsqb;.