Patent Document ID: 5537057
Application ID: 08388300
Patent Flag: 1

Claim One:
1. A programmable logic array device having first and second substantially orthogonal array dimensions and comprising: a plurality of regions of programmable logic arranged in rows and columns substantially along said two orthogonal array dimensions, each of said regions having a plurality of terminals comprising a plurality of inputs and a plurality of outputs, and producing an output signal on said outputs which is a programmable function of an input signal applied to said inputs of said region, said regions being grouped into logic subsets, each of said logic subsets comprising a plurality of said regions, each of said regions belonging to only one of said logic subsets; a first group of conductors for conveying signals among said regions, each conductor of said first group of conductors extending substantially parallel to one of said rows and said columns over at least a substantial portion of one of said array dimensions, each of said regions being adjacent at least one conductor of said first group of conductors; a second group of conductors for conveying at least one of (a) signals within one of said logic subsets of said plurality of regions, (b) signals between adjacent ones of said logic subsets, and (c) signals between nearby ones of said logic subsets, each conductor of said second group of conductors extending parallel to one of said rows and columns and having a length at least equal to about a dimension of one of said regions and at most equal to about a dimension of said logic subset, each of said regions being adjacent at least one conductor of said second group of conductors; a third group of conductors for conveying both (a) signals between any one of said regions and each other region that is (i) adjacent said one of said regions, and (ii) in one of a same row and a same column as said one of said regions, and (b) signals between any one of said regions and each other region that is (i) diagonally adjacent said one of said regions, and (ii) in one of said logic subsets with said one of said regions; a first group of connectors for programmably selectively connecting conductors adjacent to any one of said regions to said terminals of said one of said regions; and a second group of connectors for programmably selectively connecting any conductor in one of said first and second groups of conductors to one of (a) another conductor in said one of said first and second groups of conductors, and (b) a conductor in another of said first and second groups of conductors.