Patent Document ID: 20090144674
Application ID: 12275246
Patent Flag: 0

Claim One:
1. A method of designing an integrated circuit (IC) containing a plurality of circuit blocks, said method comprising: receiving a first model and a second model of a first circuit block contained in said plurality of circuit blocks, said first circuit block containing a plurality of ports, each operable to communicate with one or more of other blocks; combining said first model and said second model to generate a third model for said first circuit block, with said third model being generated to contain portions of said first model corresponding to a first set of ports, and to contain portions of said second model corresponding to a second set of ports, wherein said first set of ports and said second set of ports are contained in said plurality of ports; and performing timing analysis of said first circuit block with at least one external block using said third model of said first circuit block, said one external block being contained in said plurality of circuit blocks.