Patent Document ID: 6128775
Application ID: 09097713
Patent Flag: 1

Claim One:
1. A method for performing register promotion, that optimizes placement of load and store operations of a computer program, within a compiler, comprising the steps of: (1) accessing a static single assignment (SSA) representation of the computer program; (2) performing static single assignment partial redundancy elimination (SSAPRE) on said SSA representation to remove at least one redundant load operation, comprising the steps of: (a) inserting .PHI. functions at iterated post-dominance frontiers of loads and their left occurrences, where different values of said loads assigned values of left occurrences reach common points in the computer program, a result of each of said .PHI. functions being stored in a hypothetical variable h; (b) assigning an SSA version to each said hypothetical variable h in the computer program; (c) determining whether each of said .PHI. functions in the computer program is down safe; (d) determining whether each of said loads or their assigned values will be available at each of said .PHI. functions following eventual insertion of code into the computer program for purposes of partial redundancy elimination; (e) transforming said SSA representation of the computer program having said hypothetical variables h to an SSA graph that includes some insertion information reflecting eventual insertions of code into the computer program for purposes of partial redundancy elimination; and (f) updating said SSA graph based on said insertion information to introduce real temporary variables t for each of said hypothetical variables h; thereby obtaining a first optimized SSA representation; and (3) performing static single use partial redundancy elimination (SSUPRE) on said first optimized SSA representation, said SSUPRE internally using a single static use (SSU) representation to remove at least one redundant store operation, thereby obtaining a second optimized SSA representation; whereby the compiler can produce more efficient, register-promoted executable program code from said second optimized SSA representation.