Patent Document ID: 4807168
Application ID: 07060201
Patent Flag: 1

Claim One:
1. A hybrid analog-digital neural network comprising a first random access memory for storing an N.times.N matrix of synaptic information in the form of binary 1 and 0 digits, an array of N analog amplifiers for performing the neuron function of said network, said array of amplifiers being numbered 1 through N corresponding to columns of said matrix, a first array of N electronic switches, each having an input terminal, an output terminal and a control terminal, one switch for each column having its control terminal connected to receive a binary signal of said synaptic information matrix stored in said first memory to enable current to flow through the switch from an input terminal to an output terminal thereof, a first summing amplifier having input and output terminals and a first array of N resistors, one resistor for each of said switches, connecting said switches to the input terminal of said summing amplifier, a first array of N sample-and-hold devices for sampling and holding an output signal at the output terminal of said summing amplifier in response to a control signal, said array of N sample-and-hold devices having its output terminals connected to said array of analog amplifiers, each device being connected to a corresponding one of said amplifiers numbered 1 through N in sequence, means for generating first and second timing signals where said first consists of N timing signals for every one of said second timing signals, means for producing and sequentially applying said control signal to said first array of N sample-and-hold devices in response to said first timing signal, said first array of N sample-and-hold devices having its output terminals connected to said array of analog amplifiers, each device being connected to a corresponding one of said amplifiers numbered 1 through N in sequence, a second array of N sample-and-hold devices having its input terminals connected to said array of analog amplifiers for sampling analog signals in response to said second timing signals, each device being connected to a corresponding one of said amplifiers numbered 1 through N in sequence, and having its output terminals connected to said array of N electronic switches, each device being connected to a corresponding one of said switches numbered 1 through N in sequence, and means for addressing said memory one row at a time to read out in parallel one row of binary digits from said matrix at a time in response to N timing signals to enable said switches in response to said binary digits.