Patent Document ID: 9519740
Application ID: 13562189
Patent Flag: 1

Claim One:
1. A method for optimizing a circuit design, the method comprising: optimizing, in a computer system, a portion of the circuit design that includes a driver gate that drives one or more inputs of each gate in a set of gates, wherein said optimizing the portion of the circuit design comprises: modeling a gate optimization problem for the portion of the circuit design based on circuit information that includes generic logical effort values of each gate in the set of gates, an input capacitance value and a specific logical effort value of the driver gate, and wire resistance and capacitance values of a net that electrically connects an output of the driver gate with one or more inputs of each gate in the set of gates, wherein said modeling includes constructing a differentiable objective function that minimizes a maximum delay from an input of the driver gate to an output of each gate in the set of gates; executing a conjugate-gradient based numerical solver to solve the gate optimization problem; incrementally computing a gradient of the differentiable objective function; and providing the computed gradient to the conjugate-gradient based numerical solver.