Patent Document ID: 9793897
Application ID: 15251444
Patent Flag: 1

Claim One:
1. A programmable array field matrix of reconfigurable logic gates, the matrix comprising: at least two reconfigurable logic gates connected to each other using a programmable rewiring, wherein a plot of each logic gate directs an output of the reconfigurable logic gates to at least one input interface block or towards an output interface block, wherein blocks inlet and outlet are placed on a periphery of the matrix; wherein each reconfigurable logic gate of the matrix forming the field programmable reconfigurable logic gates employs a circuit having three blocks: a) an input block, b) an adder block, and c) an output window detector block; wherein each reconfigurable logic gate forming the field programmable matrix of reconfigurable logic gates is characterized in that the input block has at least two signal inputs for the operation of the reconfigurable logic gate; and two comparators one for each input of the logic gate, in order to receive two logic signals respectively through inputs; the two logic signals are received, then a decision tree starts where: i) If the input signal is greater than the reference voltage, then the output signal of the first comparator is set to a predefined voltage; ii) If the input signal is less than the reference voltage, then the output signal of the first comparator is zero volts; iii) If the input signal is greater than the reference voltage, then the output signal of the second comparator is set to a predefined voltage; iv) If the input signal is less than the reference voltage, then the output signal of the second comparator is zero volts; wherein the adder block receives the output signals of the comparators respectively in the input blocks and a compensation signal, the compensation signal is a control parameter for programming of logical operation of the reconfigurable logic gate and gets the different logical operations; the output of the adder block is a result of adding the signals from the comparators and the compensation signal, and wherein said sum is performed by an adder in the adder block; and the output window detector block comprises a comparator block defining a logical level at the output as follows: d) if the absolute value of the sum obtained by the adder block is less than the window detector block reference; then a “high” logic level is obtained at the output; and e) if the absolute value of the sum obtained by the adder block is greater than the window detector block reference; then a logic “low” is obtained at the output.