Patent Document ID: 6110220
Application ID: 09024839
Patent Flag: 1

Claim One:
1. A method for designing the architecture of an embedded system, comprising: (a) a pre-processing phase comprising the step of parsing one or more aperiodic task graphs, one or more system/task constraints, and a resource library for the embedded system; and (b) a synthesis phase, following the pre-processing phase, comprising the step of allocating one or more groups of one or more tasks in the aperiodic task graphs to one or more processing elements (PEs) in the resource library and allocating one or more edges in the aperiodic tasks graphs to one or more communication links in the resource library, based on performance evaluation of one or more possible allocations for each of the groups and edges in light of the system/task constraints, wherein the aperiodic task graphs have hard real-time constraints and deadlines for the aperiodic task graphs are always met.