Patent Document ID: 9075111
Application ID: 14047869
Patent Flag: 1

Claim One:
1. A generalized modular redundancy fault tolerance method for a combinational circuit, comprising the steps of: setting a protection threshold thr for identifying dominant combinations at the outputs of the combinational circuit, wherein a combination S is dominant if probability of occurrence for the combination S is greater than the threshold thr; generating a truth table of the combinational circuit; for each output i of the combinational circuit, calculating probability of occurrence P i (0), P i (1), based on the truth table; for all remaining outputs j calculating probability of occurrence P ij (00), P ij (01), P ij (10), P ij (11) based on the truth table; choosing a best candidate j where thr has been met with minimum N P ij ; synthesizing a first single protection correction circuit operable with the combinational circuit when decision criteria P(D i )>thr and N P ij >2 are met, wherein D i represents a dominant combination at the output i; synthesizing a second single protection correction circuit operable with the combinational circuit when decision criteria P(D i )>thr and N P ij ≦2 and P(D i )≧P(D ij ) are met, wherein D ij represents dominant combinations when pairing the outputs i,j; synthesizing a first pair protection correction circuit operable with the combinational circuit when decision criteria P(D i )>thr and N P ij ≦2 and P(D i )<P(D ij ) are met; synthesizing a second pair protection correction circuit operable with the combinational circuit when decision criterion P(D i )>thr is not met and when decision criterion N P ij ≦3 is met; synthesizing a triple modular redundancy (TMR) protection correction circuit operable with the combinational circuit when decision criteria for single and pair protection have not been met; and wherein P(D i ) is the probability of occurrence for the dominant combination at output i, P(D ij ) is the probability of occurrence for the dominant combinations at paired outputs i,j, P i is the probability of occurrence of the combination Sat output i, P ij is the probability of occurrence of the combination S when pairing outputs i, j, and N P ij is a number of protected combinations when pairing outputs i, j, the first and second single protection correction circuits, the first and second pair protection correction circuits and the TMR protection correction circuit providing fault protected outputs, ensuring minimum Hamming distance of 3 between the protected combinations and minimum Hamming distance of 1 between the protected combinations and their respective faulty combinations.