Patent Document ID: 5555506
Application ID: 08385849
Patent Flag: 1

Claim One:
1. A method of fabricating an integrated circuit chip, which contains a victim net and a set of aggressor nets with each aggressor net having a line segment that lies next to said victim net, such that crosstalk voltages coupled to said victim and aggressor nets are within an acceptable level; said method including the steps of: providing a trial layout for said victim net and said aggressor nets; assigning to said trial layout of said victim net, the parameters of--a line capacitance, a line resistance, and a driver output resistance; and assigning to said trial layout of each aggressor net, the parameters of--a coupling capacitance to said victim net, a voltage transition, and a cycle time for said transition; estimating, for each aggressor net, a respective mean crosstalk voltage V.sub.M which the aggressor net couples into said victim net as a function ##EQU4## where K, X, and Y are products of said parameters; modifying said trial layout and repeating said assigning and estimating steps until a summation of the estimated mean crosstalk voltages in the victim net is within said acceptable level; and, building said chip with the modified layout for which said summation is within said acceptable level.