Patent Document ID: 20020157080
Application ID: 09931879
Patent Flag: 0

Claim One:
1. A logic circuit design method in which a logic circuit on a register transfer level or a behavior level, generated at a first site, is transferred to a second site at which logic synthesis on the circuit is performed, comprising: receiving a first logic circuit on the register transfer level or behavior level and a second logic circuit on a gate level output from logic synthesis executed on said first site by using a first library and under synthesis constraints for said first logic circuit, sent from said first site; evaluating said second logic circuit performance and confirming that evaluated performance agrees with the performance of said second logic circuit evaluated on said first site; generating a third logic circuit on the gate level by executing logic synthesis on said first logic circuit, using said first library and under the synthesis constraints for said first logic circuit; evaluating said third logic circuit performance and evaluating performance improvement by comparing the third logic circuit performance with the second logic circuit performance which was evaluated and confirmed as the agreed one; and sending said third logic circuit and information on the performance improvement to said first site.