Patent Document ID: 5381515
Application ID: 07972024
Patent Flag: 1

Claim One:
1. A two-layer synaptic array fabricated on a semiconductor substrate comprising: a first layer comprising: a plurality of first electrically-adaptable synaptic elements disposed in at least one row and at least one column, each of said first electrically-adaptable synaptic elements in said first layer of said array comprising an input node, an adapt-control signal node, a floating node, electron injecting means coupled to said floating node for injecting electrons on to said floating node while the voltage on said floating node is within the normal operating range of said synaptic element, negative feedback means, coupled between said floating node and said electron injecting means, and responsive to a first adapt signal on said adapt control signal node, for controlling said electron injecting means to vary the rate of injection of electrons on to said floating node in response to the magnitude of the voltage on said floating node, and an output node for supplying a current required by said synaptic element in response to a signal on said input node and said voltage on said floating node; a row input line associated with each row of said first layer of said array, each said row input line connected to the input nodes of all of said first electrically adaptable synaptic elements associated with its row; and a column sense line associated with each column of said first layer of said array, each column sense line connected to the output nodes of all of said first electrically adaptable synaptic elements associated with its column; a plurality of interlayer processing elements, each of said interlayer processing elements having an input connected to one of said column-sense lines, each of said interlayer processing elements further having an output node; a second layer comprising: a plurality of second electrically-adaptable synaptic elements disposed in at least one row and at least one column, each of said second electrically-adaptable synaptic elements in said second layer of said array comprising an input node, an adapt-control signal node connected to, a floating node, electron injecting means coupled to said floating node for injecting electrons on to said floating node while the voltage on said floating node is within the normal operating range of said synaptic element, negative feedback means, coupled between said floating node and said electron injecting means, and responsive to a second adapt signal on said adapt-control signal node, for controlling said electron injecting means to vary the rate of injection of electrons on to said floating node in response to the magnitude of the voltage on said floating node, and an output node for supplying a current required by said synaptic element in response to a signal on said input node and said voltage on said floating node; a second layer column input line associated with each column of said second layer of said array, each second layer column input line connected to the output node of the one of said interlayer processing elements associated with its column and to the input nodes of each of said second electrically-adaptable synaptic elements in said second layer of said array associated with its column; a second layer row output line associated with each row in said second layer of said array, each said second layer row output line connected to the output nodes of all of said second electrically-adaptable synaptic elements in said second layer associated with its row; a column adapt control line associated with each column of said first and second layer of said array, each said column adapt control line connected to the adapt control signal nodes of all of said first and second electrically adaptable synaptic elements associated with its column; and means for placing adapt control signals on selected ones of said column adapt control lines to activate an adapt mode of operation of said array.