Patent Document ID: 8516413
Application ID: 13468933
Patent Flag: 1

Claim One:
1. A method for compiling a hardware description language (HDL) specification for simulation of a circuit design, the method comprising: using one or more processors to perform operations including: elaborating the circuit design from the HDL specification; determining first nets of the elaborated circuit design that are not placed in a forced state during simulation, and second nets of the elaborated circuit design that are placed in a forced state at some time during simulation; and generating simulation code that models the circuit design, the simulation code configured and arranged to, during simulation runtime: update one or more of the first nets using one or more respective update functions of a first type, each function of the first type configured to update a value of the net each time the update function is executed; and update one or more of the second nets using one or more respective update functions of a second type, each function of the second type configured to update a value of the net only in response to the net being in the forced state at time of execution of the update function.