Patent Document ID: 9147074
Application ID: 13114831
Patent Flag: 1

Claim One:
1. A system, comprising: a processor; a boot flash storage area storing a boot image; and a field programmable gate array (FPGA) configured to: validate an integrity of the FPGA and a microloader; and cause the validated microloader to be passed to the processor; and wherein the microloader, when executed by the processor, performs an operation comprising: retrieving the boot image from the boot flash storage area; validating the boot image; and sending, to the FPGA, at least one validation result indicating the boot image is authorized to be loaded by the system, wherein the FPGA is configured to prevent the processor from executing the boot image until the FPGA: (i) validates the integrity of the FPGA and the microloader, and (ii) receives the at least one validation result from the microloader.