Patent Document ID: 4670838
Application ID: 06578348
Patent Flag: 1

Claim One:
1. A single chip microcomputer selectively operable in a normal and a debug mode in response to internal and external instructions, respectively, said external instructions being given from at least one external device, said microcomputer comprising: a program memory for storage of a program consisting of said internal instructions; principal mode signal producing means for selectively producing a normal and a debug mode signal representative of said normal and said debug modes, respectively; a predetermined number of port groups comprising a first, a second, a third, and a fourth group of ports; subsidiary mode signal producing means coupled to said principal mode signal producing means for producing a first and a second subsidiary mode signal representative of first and second subsidiary modes, respectively, only when said subsidiary mode signal producing means is supplied with said debug mode signal from said principal mode signal producing means; decoding means coupled to said program memory and said principal and said subsidiary mode signal producing means for decoding said external instructions to produce a first and a second set of control signals in response to said first and said second subsidiary mode signals, respectively, and for decoding the internal instructions produced by said program memory to produce a third set of control signals when said decoding means is supplied with said normal mode signal from said principal mode signal producing means; and selectively operable port control means between said first through said fourth groups of ports and said decoding means for putting said first through said fourth groups of ports into operation in said normal mode in response to said third-set control signals, for allotting, in response to said first-set control signals, said external instructions and a specific one of data sets related to said external instructions to said first and said second groups of ports, respectively, and for allotting, in response to said second-set control signals, said external instructions and a particular one of the data sets to said third and said fourth groups of ports, respectively.