Patent Document ID: 20150121319
Application ID: 14064031
Patent Flag: 0

Claim One:
1. A method for using circuit design computing equipment, the method comprising: with the circuit design computing equipment, receiving a path description for a path that electrically couples a source node to a destination node in an integrated circuit, wherein the path description includes a plurality of path implementations for the path, and wherein a predetermined number of pipeline registers is associated with each path implementation in the plurality of path implementations; with the circuit design computing equipment, receiving a target criterion for the path, wherein the target criterion for the path are selected from the group consisting of: performance, area usage, number of registers, power dissipation, clock rate, throughput, and latency; with the circuit design computing equipment, receiving a pipeline optimization constraint for the path, wherein the pipeline optimization constraint specifies at least one allowable number of pipeline registers for the path; and with the circuit design computing equipment, selecting a target path implementation that satisfies the target criterion, the target path implementation being selected from the plurality of path implementations, and the predetermined number of pipeline registers associated with the target path implementation is one of the at least one allowable number of pipeline registers for the path.