Patent Document ID: 8024681
Application ID: 12314615
Patent Flag: 1

Claim One:
1. A Hardware Description Language (HDL) processing method, to be implemented in a computer, for processing a HDL file which is written in HDL having a hierarchical structure including three or more hierarchical levels in a Computer-Aided Design (CAD) which supports hardware design, comprising: analyzing the hierarchical structure of the HDL and obtaining an analysis result; and processing the HDL one at a time for each hierarchical level based on the analysis result said processing including compiling a logic synthesis or a logic simulation with respect to the HDL, and wherein said analyzing analyzes the hierarchical structure of the HDL based on an entity table which stores position information of the HDL file for each entity, a high-level entity list table which stores a number allocated to the high-level entity list and a list of links to the entity table indicating a list of numbers allocated to the entity table, and an execution preparation list which is input with entities for which a number of low-level entities is 0 from the entity table.