Patent Document ID: 5412670
Application ID: 07983659
Patent Flag: 1

Claim One:
1. A parity detecting neural network operating on an N-bit input field for providing a binary output signal that indicates if an even or odd number bits in the N-bit input field have been asserted, the neural network comprising: (a) a multiplicity of N input terminals, each terminal for accepting a distinct bit from the N-bit input field; (b) a hidden layer having a first neural cell and a second neural cell, each neural cell including: (i) a set of N equally weighted synapses, each synapse connected to a distinct input terminal for producing a set of weighted output signals, (ii) a synaptic summing network for accepting the set of weighted output signals and for forming an output signal with a level proportional to a count of asserted bits in the N-bit input field, (iii) a nonlinear activation network with an input connected to the synaptic summing network output signal for producing an output signal that is a sum of a first signal with a signal level proportional to the synaptic summing network output signal for producing an output signal and a second signal that alternates polarity, having a first polarity if the synaptic summing network output signal level is proportional to an odd count of asserted bits and having an opposite second polarity if the synaptic summing network output signal level is proportional to an even count of asserted bits, the second neural cell nonlinear activation network having a second signal that is of opposite polarity to that of the first neural cell nonlinear activation network second signal; (c) an output layer having a single neural cell with a first synaptic input and a second synaptic input respectively connected to the first neural cell output signal and the second neural cell output signal for producing a binary output signal with a first state indicating an even count of asserted bits in the N-bit input field and a second state indicating an odd count of asserted bits in the N-bit input field by forming a difference signal representative of a difference between the output signal of the hidden layer first and second neural cell output signal, the binary output signal state being representative of the difference signal polarity.