Patent Document ID: 7725852
Application ID: 11428986
Patent Flag: 1

Claim One:
1. A method comprising: accessing by one or more computer systems: a description of a chip comprising a plurality of sequential elements and a clock mesh, the description identifying the sequential elements, indicating locations of the sequential elements on the chip, specifying interconnections among the sequential elements on the chip, and specifying a layout of the chip; information for modeling the sequential elements and interconnections; and a set of parameters of the clock mesh; using the description of the chip, the information for modeling the sequential elements and interconnections, and the set of parameters of the clock mesh: determining by the one or more computer systems a plurality of window locations covering the clock mesh, each window location comprising one or more of the sequential elements on the chip; and for each window location: generating by the one or more computer systems a mesh simulation model comprising a detailed model and an approximate model, the detailed model detailing all components inside the window location and the approximate model approximating all components outside the window location, wherein for each of one or more mesh nodes outside the window location, all components within a unit region covered by the mesh node are approximated at the mesh node using at least a sum of clock-input pin capacitances of all the components within the unit region to obtain a single capacitance at said each mesh node; simulating by the one or more computer systems the mesh simulation model; and measuring by the one or more computer systems clock timing for the sequential elements in the window location based on the simulation of the mesh simulation model; and collecting by the one or more computer systems timing information on all the sequential elements on the chip based on the measured clock timing for the sequential elements in the window locations.