Patent Document ID: 20060294485
Application ID: 11169362
Patent Flag: 0

Claim One:
1. A method for routing nets within an integrated circuit, comprising: receiving a representation for the integrated circuit, wherein the representation includes block boundaries for physical partitions of the integrated circuit generated from a hierarchical design placement of the integrated circuit; classifying each net in the integrated circuit based on the location of pins associated with the net, wherein the pins are locations where the net is coupled to circuit elements or block boundaries within the integrated circuit; generating routing constraints for each net based on the classification of the net; applying a feedthrough constraint to the physical partitions, wherein the feedthrough constraint restricts nets from feeding through physical partition boundaries; and routing each net using the routing constraints for the net and the feedthrough constraints for the physical partitions; wherein routing is performed based on the block boundaries prior to finalizing the hierarchical design placement, thereby facilitating early detection of congestion or timing violations which can be corrected early in the design process.