Patent Document ID: 7861195
Application ID: 12022860
Patent Flag: 1

Claim One:
1. A computer-implemented method, wherein at least one processor following a sequence of software instructions contained in a memory is caused to perform steps comprising: compiling, using the at least one processor, process assumptions regarding physical features on a semiconductor wafer, the physical features including wafer patterns; generating, responsive to the compiled process assumptions, modeling parameters to reflect expected process variation; generating, responsive to the modeling parameters, a predictive process contour of the wafer patterns, derived from a Process Variability Band (PVBAND) simulation; compiling data describing the predictive process contour of the wafer patterns into a cumulative distribution function (CDF) for key metrics by varying patterns and alignment between patterns a finite number of times, taking a nominal condition in an inner and outer band of the enhanced contours, interpolating between the inner and outer band, and running a statistical Monte Carlo algorithm using values of the varied patterns and alignment between patterns as inputs to the Monte Carlo algorithm to generate the CDF; and manufacturing a semiconductor circuit based on the CDF.