Patent Document ID: 20030156481
Application ID: 10372604
Patent Flag: 0

Claim One:
1. A semiconductor memory device in which operations for writing and reading data are controlled by using a system clock that is supplied from the outside and a data strobe signal that is received as input and supplied as output in synchronization with said data; said semiconductor memory device comprising: a plurality of FIFO memories for temporarily holding write data, which are received as input from the outside and which are the object of writing; a plurality of write amplifiers for writing said write data to memory cells that correspond to addresses that are received as input from the outside; a first write-system control circuit for generating a first control signal for causing said write data to be transmitted from said FIFO memories to said write amplifiers in synchronization with said data strobe signal that is received together with, of said write data that have been received as burst input for one write command, the final item of write data of every prefetch number of items of write data; a Y-system control circuit for generating a second control signal for driving a plurality of switches, which connect said write amplifiers with bit lines that connect to memory cells that correspond to addresses to which said write data are written, in synchronization with, of said system clock, the pulse edge of a prescribed cycle following completion of input of said final item of write data; and a second write-system control circuit for generating a third control signal for causing a write voltage, which is a voltage that is required for writing data to said memory cells, to be supplied as output from said write amplifiers based on said write data in synchronization with, of said system clock, the pulse edge after a prescribed cycle following the completion of input of said final item of write data.