Patent Document ID: 4110831
Application ID: 05811214
Patent Flag: 1

Claim One:
1. In combination with a multistage decimal adder/subtractor, an apparatus for rounding up the more precise one of two BCD encoded numbers to the least significant digit position of the less precise number, pairs of digits of like order being applied to corresponding stages, nonsignificant digits I being uniquely coded, said apparatus comprising: means for comparing the significance of the digits of each pair and for causing the resultant digit of the corresponding adder/subtractor stage to be changed to I if at least one digit of the pair was of value I; means for causing a first carry to be applied to the adder/subtractor stage next in higher order than a given stage when one digit of the pair applied to the given stage is significant and has a value &gt;b, b being sent by a rounding rule, the other digit having the value I; and means for causing a second carry to be applied to the stage next in higher order than the given stage when the digit pair values and carries incident upon the given stage exceed an amount K and for causing the corresponding resultant digit to be changed to 0, said means including means also for generating a second carry in the event the given stage subtracts one digit from another and either the minuend digit has value I and the subtrahend digit &lt;b or the subtrahend digit has value I.