Patent Document ID: 9563851
Application ID: 13491212
Patent Flag: 1

Claim One:
1. A probability processor configured to perform computations of an inference task specified by a factor graph, the probability processor comprising: a factor table memory for storing factor table records of the factor graph; and one or more computation units, each computation unit comprising an inputs and outputs memory for storing inputs and outputs of a succession of instructions; an arithmetic logic unit for (1) performing the succession of the instructions based on factor table records accessed from the factor table memory and the inputs accessed from the inputs and outputs memory and (2) storing the outputs to the inputs and outputs memory; and an input message caching element including a register that stores a message value, wherein the input message caching element receives a message value from the inputs and outputs memory, the input message caching element receives an indicator from the factor table memory, if the indicator indicates a first logical value, the input message caching element stores the message value in the register and the input message caching element passes the message value to the arithmetic logic unit, and if the indicator indicates a second logical value, the input message caching element passes a previous message value to the arithmetic logic unit.