Patent Document ID: 4760544
Application ID: 06876533
Patent Flag: 1

Claim One:
1. An arithmetic logic and shift device comprising: an arithmetic logic unit; first and second input multiplexers connected to respective inputs of said arithmetic logic unit; a data shift means; a third input multiplexer connected to an input of said data shift means; first and second data input ports connected respectively to an input of the first input multiplexer and to an input of the third input multiplexer; a first connective feedback path connected to the third input multiplexer to feedback data output from the arithmetic logic unit; a second and independent connective feedback path connected to the second input multiplexer to feedback data output from the data shift means; a third and independent connective feedback path connected to the first input multiplexer to feedback only data output from the arithmetic logic unit; a data output port; and an output multiplexer, connected at respective inputs to receive data from the arithmetic logic unit and from said data shift mean, and connected at output to the data output port to select and pass data thereto.