Patent Document ID: 7784004
Application ID: 11111135
Patent Flag: 1

Claim One:
1. A skew lot for a CMOS integrated circuit design including a plurality of interconnected field-effect transistors, the skew lot comprising: a plurality of integrated circuits, with each integrated circuit including a plurality of n-channel and p-channel field-effect transistors interconnected according to the integrated circuit design, wherein each transistor of the plurality of interconnected field-effect transistors in the design has a nominal gate-insulator thickness and a nominal channel length, wherein each field-effect transistor in the plurality of integrated circuits has a fabricated gate-insulator thickness and a fabricated channel length, and the fabricated gate-insulator thickness is skewed from the nominal gate-insulator thickness, and the fabricated channel length is skewed from the nominal channel length to exhibit process variance of an electrical characteristic other than transconductance, and wherein in each transistor having the fabricated gate-insulator thickness skewed to be greater than the nominal gate-insulator thickness, the fabricated channel length of the transistor is skewed to be less than the nominal channel length, and in each transistor having the fabricated gate-insulator thickness skewed to be less than the nominal gate-insulator thickness, the fabricated channel length of the transistor is skewed to be greater than the nominal channel length.