Patent Document ID: 5511162
Application ID: 08082289
Patent Flag: 1

Claim One:
1. In an apparatus comprising a plurality of expert knowledge tables associated respectively with a plurality of failure categories, each of the expert knowledge tables mapping relationships between a plurality of test patterns and a plurality of fault modes, means for storing memories with a plurality of expert rules respectively associated with said expert knowledge tables, each of the stored expert rule memories defining a tree of successively traceable nodes interconnected by decision branches leading to a plurality of fault modes, each of the nodes defining one of said test patterns of the associated expert knowledge table and a corresponding expected value, a method of using said apparatus comprising the steps of: a) deriving a test result from an LSI (large scale integration) chip under test and analyzing the test result and identifying the test result as one of said failure categories; b) selecting one of said stored expert rule memories corresponding to the identified category; c) specifying one of the nodes of the selected stored expert rule memory corresponding to a chip failure; d) applying a test pattern defined by the specified node to said chip and deriving a result signal therefrom; e) comparing the result signal with the expected value defined by the specified node to produce a comparison result; f) tracing the tree of the selected stored expert rule memory according to the comparison result of step e) from the specified node to a subsequent node and specifying the subsequent node instead of the node previously specified; g) repeating the steps (d) to (f) until one of said fault modes is reached; and h) identifying said chip failure as the fault mode reached by the step (g).