Patent Document ID: 9965575
Application ID: 15266455
Patent Flag: 1

Claim One:
1. A method for accurate logic simulation of a logic circuit, said method being embodied as a set of computer instructions stored on computer readable media, said computer instructions, when loaded into a computer, causing the computer to perform the steps of said method, said logic circuit having a multiplicity of inputs and one output, each of said inputs and output taking either the logic value 0, or the logic value 1, or a symbolic value, said symbolic value indicating that the said input or output is either unknown, unspecified or not determined to be 0 or 1, said symbolic value represented by a symbol X, said logic circuit being part of a digital integrated circuit, said logic simulation being performed for the purpose of ensuring error-free operation of said digital integrated circuit to be fabricated, the method comprising: performing, prior to said logic simulation, a Boolean analysis of said logic circuit to determine all input value combinations for said logic circuit so that the value of the logic-circuit output determined by a logic simulator for each of said input value combinations would be the symbol X, whereas the value of the logic-circuit output in the logic circuit to be fabricated would be 0 for said input value combination; performing, prior to said logic simulation, a Boolean analysis of said logic circuit to determine all additional input value combinations for said logic circuit so that the value of the logic-circuit output determined by the logic simulator for each of said additional input value combinations would be the symbol X, whereas the value of the logic-circuit output in the logic circuit to be fabricated would be 1 for said additional input value combination; storing in computer readable media, prior to said logic simulation, each of said value combinations of logic-circuit inputs along with the corresponding value of said logic-circuit output in the logic circuit to be fabricated, in such a manner that each of said stored combinations of inputs and output can be retrieved by the logic simulator during said logic simulation of said digital integrated circuit; said stored value combinations of said logic-circuit inputs and output being represented in a graphical form, said graphical form being a Binary Decision Diagram or a Multi-Valued Decision Diagram, and stored in same said graphical form; during said logic simulation of said digital integrated circuit, when the observed value combination in said logic simulation at said logic-circuit inputs matches one of said stored logic-circuit input combinations, retrieving said logic-circuit output value stored along with said observed logic-circuit input value combination, said step of matching and retrieval being termed value-lookup, and forcing the logic simulator to apply in said logic simulation at the current simulation time said retrieved logic-circuit output value at said logic-circuit output, said step of forcing being termed X-correction; and in response to said logic simulation satisfying error free operation of said integrated circuit, providing said error free integrated circuit to a fabrication facility to fabricate said error free integrated circuit.