Patent Document ID: 10162917
Application ID: 15282936
Patent Flag: 1

Claim One:
1. A computer-implemented method for implementing transformations for verifying a circuit design, comprising: analyzing a circuit design comprising a plurality of components; accessing power intent information for the circuit design; receiving observable points for the circuit design and accessing one or more verification tasks corresponding to the observable points; identifying one or more phases for a power sequence associated with the circuit design; for a phase from the one or more phases, identifying a subset of components from the plurality of components within the circuit design for transformation in a logical representation of the circuit design, wherein a component is identified for the transformation if corruption for the component is observable for the observable points; executing, at a transformation module stored partially in memory and functioning in conjunction with at least one microprocessor of a computing system, the transformation on the component identified for the transformation to generate a transformed component in the logical representation of the circuit design while skipping execution of the transformation on one or more remaining components in the circuit design; and performing the verification with the logical representation of the circuit design having the transformed component and the one or more remaining components.