Patent Document ID: 20130117619
Application ID: 13290511
Patent Flag: 0

Claim One:
1. A computer-implemented method of verifying logic in a simulation-based behavioral latch model by performing actions comprising: inserting a value checking module in the behavioral latch model, the value checking module connected to one of a set of latches outside of a scan chain within the behavioral latch model, wherein the set of latches outside of the scan chain includes all latches in the behavior latch model that are outside of the scan chain; comparing a value of a latch signal for the one of the set of latches outside of the scan chain with a delta value of the latch signal for the one of the set of latches outside of the scan chain, the delta value representing a time delayed value of the latch signal, wherein the comparing is initiated using a dial switch, wherein the dial switch is initially set to an off value, and wherein the comparing includes switching the dial switch from the off value to an on value; and providing an error message in response to determining the value and the delta value are distinct.