Patent Document ID: 8515695
Application ID: 12421481
Patent Flag: 1

Claim One:
1. A method performed by a processor for evaluating small delay defect coverage of a set of test patterns on an integrated circuit, comprising the following steps: (a) selecting a transition fault of an integrated circuit detected by a test pattern set, said transition fault occurring at a fault site of said integrated circuit; (b) identifying path delays of a longest testable path and a longest tested path of said integrated circuit, wherein both said longest testable path and said longest tested path include said fault site; (c) determining a small delay defect detection probability for both said longest testable path and said longest tested path, wherein said small delay defect detection probability for said longest testable path is a probability that if a delay defect occurs, said delay defect at said fault site is equal to or greater than a difference between a system clock period and a path delay of said longest testable path and said small delay detection probability for said longest tested path is a probability that if a delay defect occurs, said delay defect at said fault site is equal to or greater than a difference between a test clock period and a path delay of said longest tested path; and (d) calculating small delay defect coverage for said transition fault by dividing said small delay defect detection probability of said longest tested path by said small delay defect detection probability of said longest testable path; wherein step (c) is performed by said processor.