Patent Document ID: 5398299
Application ID: 08126868
Patent Flag: 1

Claim One:
1. In a fuzzy inference system comprising a plurality of fuzzy rules, a plurality of input labels and a plurality of output labels, each of the fuzzy rules including a subset of the input labels as antecedents and one of the output labels as a consequent, a min-max computing circuit for executing a min-max computation on input label grades, comprising: a) rule memory means for storing a plurality of digital values, each of the digital values corresponds to one of the plurality of fuzzy rules and each of the digital values comprises an ordered plurality of digital bits, each of the digital bits of each of the digital values corresponds to one of the plurality of input labels, the ordered plurality of digital bits of each of the digital values is arranged so that an Nth one of the plurality of input labels corresponds to an Nth bit in each of the plurality of digital values, each of the digital bits of a particular one of the digital values is in a first binary state if the corresponding input label is an antecedent of the fuzzy rule corresponding to that particular one of the digital values, and is in a second binary state if the corresponding input label is not an antecedent of the fuzzy rule corresponding to that particular one of the digital values; b) an input label sorter circuit comprising: i) a plurality of storage means, each of the storage means having a first portion for storing a one of a plurality of digital grade values and a second portion for storing a one of a plurality of label codes corresponding to the one of the plurality of digital grade values stored in the first portion, the one of the plurality of label codes identifies one of the plurality of input labels; and ii) sorting means coupled to the plurality of storage means for sorting the plurality of digital grade values and the plurality of label codes within the plurality of storage means according to a magnitude of each of the plurality of digital grade values; c) first accessing means coupled to the plurality of storage means for sequentially retrieving from the plurality of storage means, in a predetermined order, the plurality of digital grade values and corresponding ones of the plurality of label codes; d) grade bus means for carrying the plurality of digital grade values retrieved from the plurality of storage means by the first accessing means; e) second accessing means coupled to receive the plurality of label codes retrieved from the plurality of storage means by the first accessing means and for retrieving from the rule memory means, in response to each of the plurality of label codes, each of the digital bits corresponding to the input label identified by a corresponding one of the plurality of label codes; f) an output label register coupled to the grade bus means; and g) digital logic means coupled to receive the digital bits retrieved from the rule memory means by the second accessing means for causing the output label register to store the plurality of digital grade values received from the grade bus means at times determined by the values of the digital bits received from the rule memory means so that, after the first accessing means has retrieved all of the plurality of digital grade values and corresponding ones of the plurality of label codes from the plurality of storage means, the output label register will contain a digital grade value corresponding to a min-max computed grade for one of the plurality of output labels.