Patent Document ID: 20140359396
Application ID: 13907736
Patent Flag: 0

Claim One:
1. A system for iterative read channel operation, the system comprising a processor and logic integrated with and/or executable by the processor, the logic being configured to: execute one or more digital front-end (DFE) functions on a block of signal samples employing a set of decisions provided by a detector executing a detection algorithm, the one or more DFE functions comprising asymmetry cancellation; execute a decoding algorithm of an error correcting code (ECC) on the signal samples using a decoder employing the set of decisions provided by the detector to generate a set of decisions provided by the decoder; store the signal samples, the set of decisions provided by the detector, and the set of decisions provided by the decoder; and in an iterative process until a maximum number of iterations has been reached or a valid codeword is produced: execute the one or more DFE functions on the signal samples employing the set of decisions provided by the decoder; execute the detection algorithm on the signal samples using the detector employing the set of decisions provided by the decoder to regenerate the set of decisions provided by the detector; execute the decoding algorithm of the ECC using the set of decisions provided by the detector to regenerate the set of decisions provided by the decoder; output decoding information relating to the signal samples when the decoding algorithm produces a valid codeword; and store the signal samples, the set of decisions provided by the detector, and the set of decisions provided by the decoder when the decoding algorithm does not produce a valid codeword.