Patent Document ID: 9864004
Application ID: 15073001
Patent Flag: 1

Claim One:
1. A method for diagnosing failure locations in one or more electronic circuits comprising: generating, using at least one processor, a plurality of core instances of at least one core, for each electronic circuit of the one or more electronic circuits, with one or more outputs; compressing the one or more outputs of each of the plurality of core instances into one or more primary output pins based upon, at least in part, one or more compression equations; applying one or more test patterns to the plurality of core instances using an automatic test equipment device; identifying one or more failures based upon, at least in part, one or more compressed test patterns received at the one or more primary output pins; performing fault selection on a single core instance for each of the one or more failures associated with the plurality of core instances; performing fault simulations on the single core instance for each of one or more candidate faults associated with the plurality of core instances; generating one or more fault signatures for each of one or more detected faults based upon, at least in part, the plurality of core instances associated with each of the one or more detected faults; and analyzing each of the one or more fault signatures to determine one or more failure locations for each of the one or more failures.