Patent Document ID: 9449134
Application ID: 14751048
Patent Flag: 1

Claim One:
1. A method for dynamically reconfiguring logic circuits on a field-programmable gate array (FPGA), the logic circuits comprising a plurality of look-up tables (LUTs), the method comprising the steps of: classifying a given general function into a set of one or more static functions and a set of one or more modal functions to be implemented on the FPGA; for each of the one or more modal functions, generating a list of one-active actions; devising a circuit topology comprising at least a subset of the plurality of LUTs such that any one of the one or more modal functions can be implemented at a time on the devised circuit topology; for each modal function, associating the devised circuit topology with a controller adapted to load a LUT configuration corresponding to a prescribed one of the one-active actions; implementing a single fixed circuit on the FPGA including devised circuit topologies for each of the modal functions; and updating contents of LUTs corresponding to the LUT configuration in the devised circuit topology when a change in modal function to be implemented on the FPGA is required.