Patent Document ID: 20100262394
Application ID: 12421481
Patent Flag: 0

Claim One:
1. A method performed by a computer for evaluating small delay defect coverage of a set of test patterns on an integrated circuit, comprising the following steps: (a) selecting a transition fault of an integrated circuit detected by a test pattern set, said transition fault occurring at a fault site of said integrated circuit; (b) identifying path delays of a longest testable path and a longest tested path of said integrated circuit, wherein both said longest testable path and said longest tested path include said fault site; (c) determining a small delay defect detection probability for both said longest testable path and said longest tested path based on a probability that a small delay defect will be detected if present at said fault site; and (d) calculating small delay defect coverage for said transition fault by dividing said small delay defect detection probability of said longest tested path by said small delay defect detection probability of said longest testable path.