Patent Document ID: 20020010840
Application ID: 09878984
Patent Flag: 0

Claim One:
1. A computer system, comprising: an interconnect; a plurality of processor nodes, coupled to the interconnect, each processor node including: at least one processor core, each processor core having an associated memory cache for caching memory lines of information; an interface to a local memory subsystem, the local memory subsystem storing a multiplicity of memory lines of information; and a protocol engine implementing a predefined cache coherence protocol; and a plurality of input/output nodes, coupled to the interconnect, each input/output node including: no processor cores; an input/output interface for interfacing to an input/output bus or input/output device; a memory cache for caching memory lines of information; an interface to a local memory subsystem, the local memory subsystem storing a multiplicity of memory lines of information; and a protocol engine implementing the predefined cache coherence protocol.