Patent Document ID: 20030218911
Application ID: 10423350
Patent Flag: 0

Claim One:
1. In a digital memory system including a memory cell arranged to store charge corresponding to first logical value when the quantity of stored charge lies within a first range of values and corresponding to a second logical value when the quantity of stored charges lies within a second range of values, apparatus testing the integrity of the data represented by the charge comprising: a bit line with a voltage responsive to charge stored in the cell; and a charge integrity estimating module operative during a first mode of operation to detect whether the quantity of the charge lies within the first range of values or the second range of values, operative during a second mode of operation to detect whether the quantity of the charge lies within a third range of values comprising a subset of the first range of values and operative during a third mode of operation to detect whether the quantity of the charge lies within a fourth range of values comprising a subset of the second range of values.