Patent Document ID: 20120046921
Application ID: 12858562
Patent Flag: 0

Claim One:
1. A method, comprising: generating a first behavioral model of a circuit, the first behavioral model describing a physical circuit in a first configuration; wherein the first configuration comprises a first logic structure, the first logic structure configured to receive a first plurality of inputs, the first logic structure further configured to generate a first intermediate signal based on the first plurality of inputs; wherein the first configuration further comprises a logic cone configured to receive the first intermediate signal, to receive a plurality of scan inputs, and to generate a scan output based on the first intermediate signal and the plurality of scan inputs; modifying the first behavioral model to generate a second behavioral model, the second behavioral model describing the physical circuit in a second configuration; wherein the second configuration comprises an error circuit configured to receive the scan output and the first intermediate signal; generating a testability model based on the second behavioral model, the testability model comprising a first structural representation, based on the first logic structure; determining, based on the testability model, whether the first logic structure causes a first coverage problem; and in the event the first logic structure causes a first coverage problem, modifying the testability model to include an inversion structure; wherein the inversion structure is configured based on the first logic structure, wherein the inversion structure is configured to generate an inversion structure output; and modifying the testability model to couple the inversion structure output as an input to the error circuit, to generate a modified testability model.