Patent Document ID: 20020152449
Application ID: 09835313
Patent Flag: 0

Claim One:
1. A method for generating an instance-based representation of a set of geometrical features that comprise a layout of a circuit on a semiconductor chip, comprising: receiving a design hierarchy specifying the layout of the circuit, including a set of hierarchically-organized nodes; wherein a given node in the design hierarchy specifies a geometrical feature that is comprised of lower-level geometrical features that are represented by lower-level nodes that appear under the given node in the design hierarchy; wherein the layout of the given node in the design hierarchy is specified by a first cell that specifies the layout of one or more nodes in the design hierarchy; for each node within the design hierarchy, determining how interactions with the node's siblings change the layout of the node as specified by the first cell, determining how environmental attributes specified by a parent of the node change the layout of the node as specified by the first cell, and if the changes result in a new node for which no instance has been created, creating a new instance for the node.