Patent Document ID: 9928211
Application ID: 13641070
Patent Flag: 1

Claim One:
1. A parallel self-timed digital adder, without look-ahead, the adder being an electronic processor having the structure of a digital logic circuit for performing arithmetic operations, the adder comprising: two or more single bit adders, each single bit adder being a half-adder; and two multiplexers connected with each of the two or more half-adders, thereby forming two or more adder blocks, the multiplexers being operable to selectively provide inputs to the half-adders with which they are connected; wherein the adder as an initial condition generates the result of a single bit summation as the first operation, whereafter in subsequent operations the sum bit from each adder block is connected recursively with itself through one of the multiplexers for addition with the carry in from the previous adder block and wherein the multiplexers enable the timing of inputs provided to the half adders for said subsequent operations at each adder block to be tuned to avoid delays in carry propagation from the previous adder block; and further wherein each adder block transfers any carry generated thereby modifying its own recursive carry to zero, and the arithmetic operations terminate when the carry signals from all of the two or more adder blocks are zero, signaling completion of the arithmetic operations.