Patent Document ID: 7496884
Application ID: 11510415
Patent Flag: 1

Claim One:
1. A method for verifying a simulated wafer image against an intended design, comprising: receiving a design which comprises one or more cell placements, wherein each of the cell placements comprises a set of geometries; generating a skeleton from the design, wherein the skeleton is a layout hierarchy which includes a bounding box for each cell placement, but does not include the geometries associated with the cell placements; computing environments for the cell placements based on the skeleton; generating templates for the cell placements, which involves: for each cell, identifying placements of the cell associated with unique environments; and generating templates for the placements associated with the unique environments; grouping templates that were generated from the same cell to form one or more template groups; generating the simulated wafer image by performing model-based simulations, which involves: for each template within a template group, retrieving geometries for the template from the design; computing a signature for the template based on the geometries within the template; comparing the signature for the template against signatures for previously-simulated templates to determine whether model-based simulations have previously been performed on the geometries within the template; if so, discarding the template; and otherwise, performing a model-based simulation on the geometries in the template.