Patent Document ID: 9026964
Application ID: 14206385
Patent Flag: 1

Claim One:
1. A method for modeling a circuit comprising: storing a plurality of design variable ranges for a circuit component in a non-transient electronic data memory; performing transistor-level simulations at a plurality of sample points for the circuit component using a processor to generate a plurality of design variable samples for the circuit component and generating a plurality of circuit response samples; selecting and storing a neural network architecture in the non-transient electronic data memory that models the plurality of design variable samples for the circuit component; and generating a performance metric metamodel and a circuit parameter metamodel based on the neural network architecture using a processor operating Verilog-AMS; storing the performance metric metamodel and the circuit parameter metamodel; training the neural network architecture with a processor using the design variable samples and the circuit response samples; and generating one or more analog block metamodels using the trained neural network architecture.