Patent Document ID: 20060267577
Application ID: 11343209
Patent Flag: 0

Claim One:
1. A method for augmenting quality/reliability of semiconductor units, comprising: (a) providing at least two populations of semiconductor units that are subject to quality/reliability testing; the populations include at least one quality/reliability fail candidate population and at least one other population; (b) associating test flows to said populations; each test flow includes stress testing sequence; the stress testing sequence for at least one of said quality/reliability fail candidate populations includes a stress test of increased duration compared to duration of a stress test in the test flow of a population of at least one of said other populations; the stress test sequence for at least one of said other populations includes a stress test of increased voltage compared to corresponding operating voltage specification for a semiconductor unit of said semiconductor units; (c) applying, within a sort testing stage, the corresponding test-flow to each population and identifying any unit which failed the stress sequence.