Patent Document ID: 7864083
Application ID: 12470469
Patent Flag: 1

Claim One:
1. A computer system configured to compress and decompress data, the system comprising a processor and a memory, and configured by instructions in the memory when executed by the processor to: receive a one dimensional time series of floating point numbers as an input; predict with a plurality of submodels what the next bit of the input sequence will be, before it is compressed, to form a plurality of predictions, where one or more of the submodels uses an adaptive filter to compute all or part of its context; combine said plurality of predictions with a mixer to produce a combined prediction; refine the combined prediction using zero or more secondary symbol estimator (SSE) stages; code the bit dependent on an output of a final of the SSE stages; update said submodels to reduce their respective prediction errors; update said mixer to favor a more accurate of the submodels; update said SSE stages to reduce their respective output prediction errors; and if the coded bit is the last bit of a floating point number, update the weights of all adaptive filters to reduce their respective prediction errors.