Patent Document ID: 20100241261
Application ID: 12705640
Patent Flag: 0

Claim One:
1. A pattern generating method comprising: preparing design layout data of a semiconductor integrated circuit pattern; performing pattern formation simulations based on the design layout data subjected to OPC processing with a plurality of process parameters set in process conditions in a predetermined range; calculating, as a worst condition, based on risk points having likelihood of causing a pattern formation failure higher than a predetermined value, a process condition having a process parameter that brings about a worst result when pattern formation is performed among the process parameters, the risk point being extracted from simulation results of the pattern formation simulations; and changing the design layout data or the OPC processing such that when a pattern is formed under the worst condition based on the changed design layout data or the changed OPC processing a number of the risk points or a risk degree of the risk points of the pattern is smaller than the simulation result.