Patent Document ID: 5546562
Application ID: 08395324
Patent Flag: 1

Claim One:
1. A method of emulating a complex circuit in a simulated system on a logic simulator with no upper simulation time limit, comprising the following steps: a) providing a simulator interface to control and accumulate any functionally complete architecturally visible update from said logic simulator to said complex circuit, b) providing a model debug and user interface to manipulate any architecturally visible registers and status within said complex circuit, c) providing a control mechanism to keep said complex circuit in an architecturally unaltered state by providing necessary clocks and data signals to keep said complex circuit operating in a quiescent state, d) providing a control and routing mechanism to accept and to submit simulator updates and user interface debug updates to said complex circuit after bringing said complex circuit out of said quiescent state, e) providing a control and routing mechanism for monitoring responses from said complex circuit, putting said complex circuit back into quiescent state, and routing said responses to said logic simulator and to said model debug and user interface, whereby the complex circuit is continually emulated within the simulated system with the ability to view or to alter or to set breakpoints on architecturally visible internal state of the complex circuit so as to provide a powerful debugging environment prior to building a real prototype of the system under development.