Patent Document ID: 8769452
Application ID: 13665315
Patent Flag: 1

Claim One:
1. A method of parasitic extraction for multi-patterning in an integrated circuit design, the method comprising: determining resistance solutions and capacitance solutions for a netlist of the integrated circuit design using a processor; performing parasitic extraction of the resistance solutions and the capacitance solutions to generate mean values within a manufacturing space for the determined resistance solutions and the determined capacitance solutions; capturing a multi-patterning source of variation for each of the determined resistance solutions and the determined capacitance solutions during the parasitic extraction; determining a sensitivity for each captured source of variation to a respective vector of parameters or collection of parameters; determining statistical parasitics by multiplying each of the determined resistance solutions and the determined capacitance solutions by the determined sensitivity for each respective captured source of variation; and generating as output the statistical parasitics in at least one of a vector form and a collapsed reduced vector form based on the respective vector of parameters or the collection of parameters.