Patent Document ID: 20160092230
Application ID: 14534841
Patent Flag: 0

Claim One:
1. A processor, comprising: an instruction cache; an execution engine; an instruction buffer; and a loop predictor that: trains a branch instruction to determine a trained loop count of a loop, wherein the loop comprises a sequence of instructions beginning with a target of the branch instruction and ending with the branch instruction; and determines whether a size of the loop is not greater than a size of the instruction buffer; and wherein, when the size of the loop is not greater than the size of the instruction buffer, the processor: stops fetching from the instruction cache; sends the loop instructions to the execution engine from the instruction buffer without fetching them from the instruction cache; maintains a loop pop count that indicates a number of times the branch instruction is sent to the execution engine from the instruction buffer without being fetched from the instruction cache; and predicts the branch instruction is taken when the loop pop count is less than the trained loop count and otherwise predicts the branch instruction is not taken.