Patent Document ID: 8341586
Application ID: 12611560
Patent Flag: 1

Claim One:
1. A computer implemented method for modeling cells for an integrated circuit design router, comprising: using at least one processor to perform a process, the process comprising: representing at least a portion of a layout with multiple cells by dividing the layout with a first set of grids; identifying a plurality of cells of the multiple cells from the layout; representing each cell of the plurality of cells with a set of nodes which comprises at least one node; and modeling routing among at least two cells of the plurality of cells by using at least a corner of a grid in the first set of grids of at least two cells of the plurality of cells based at least in part upon congestion analysis results determined by using at least the first set of grids, wherein each of the at least two cells is modeled with a grid having four or more edges for modeling the routing among the at least two cells.