Patent Document ID: 8990661
Application ID: 13785848
Patent Flag: 1

Claim One:
1. An LDPC decoder for decoding low-density parity check (LDPC) encoded data, the LDPC encoded data comprising a plurality of log-likelihood ratios (LLRs), each of the plurality of LLRs representing one of a plurality of bits of an LDPC codeword encoded using a parity check matrix having a plurality of layers, the decoder comprising: an attenuation factor matrix comprising a plurality of coefficients, each of the plurality of coefficients identifying a layer specific attenuation factor for each layer of the plurality of layers of the parity check matrix; a check node processor coupled to the attenuation factor matrix, the check node processor having circuitry for performing check node processing for each layer of the parity check matrix associated with the LDPC encoded codeword utilizing a layered min-sum algorithm having at least one layer specific attenuation factor associated with at least one layer of the parity check matrix; a variable node processor coupled to the check node processor, the variable node processor having circuitry for performing variable node processing for each layer of the parity check matrix; and a codeword estimate check processor coupled to the variable node processor, the codeword estimate check processor having circuitry for performing a check of the estimate of the LDPC encoded codeword to determine if the codeword estimate is a codeword.