Patent Document ID: 9992057
Application ID: 14262592
Patent Flag: 1

Claim One:
1. A neurosynaptic network circuit, comprising: multiple neurosynaptic devices comprising a plurality of neurosynaptic core circuits for processing one or more data packets; and said multiple neurosynaptic devices further comprising a routing system for routing said one or more data packets between said plurality of neurosynaptic core circuits; wherein each neurosynaptic core circuit has a corresponding set of bits indicative of whether said neurosynaptic core circuit is available for processing said one or more data packets; and wherein said routing system is configured for selectively bypassing at least a portion of said neurosynaptic network circuit based on a recovery mechanism when processing and routing said one or more data packets, said recovery mechanism selected from a set of different recovery mechanisms with different yield tolerances and different costs based on a type of faulty neurosynaptic device detected in said neurosynaptic network circuit, a location of said faulty neurosynaptic device, and a corresponding set of bits of at least one neurosynaptic core circuit of said plurality of neurosynaptic core circuits, and said recovery mechanism transitions to another recovery mechanism selected from said set of different recovery mechanisms in response to a change of one or more bits of said corresponding set of bits.