Patent Document ID: 8689070
Application ID: 12781695
Patent Flag: 1

Claim One:
1. A method of scan chain diagnosis, executed by at least one processor of a computer, comprising: receiving faulty scan chain information of an integrated circuit, the faulty scan chain information including information identifying one or more faulty scan chains and fault models associated with the one or more faulty scan chains; masking scan patterns based on the faulty scan chain information to filter out loading-caused failures, the scan patterns being applied to the integrated circuit, wherein masking scan patterns comprises X-masking sensitive bits in the scan patterns; simulating the masked scan patterns to determine failing probability information for cells on one of the one or more faulty scan chains, wherein simulating the masked scan patterns includes simulating the X-masked scan patterns to obtain sensitive bit capture counts and failing bit counts for the cells, and calculating failing probabilities for identification of the one or more faulty scan chains based upon the sensitive bit capture counts and the failing bit count counts; and determining defective cell information based on the failing probability information.