Patent Document ID: 9323994
Application ID: 12638759
Patent Flag: 1

Claim One:
1. A device, comprising: pattern-recognition processor, comprising: a plurality of logical groups, wherein each group comprises first route lines, a first feature cell, and a second feature cell, wherein each of the first and the second feature cells of each group comprises an enable input and an enable output, wherein the first and the second feature cells of each group are selectively coupled to the first route lines by first connections, and wherein the first connections comprise enable input connections that couple the enable input of the first and the second feature cells to the first route lines and enable output connections that couple the enable output of the first and the second feature cells to the first route lines, wherein a given feature cell of a given group is configured to transmit a state output signal from the enable output of the given feature cell to an enable input of another feature cell of the given group along one of the first route lines, wherein the first feature cell and the second feature cell of each group of the plurality of logical groups are separate and distinct from feature cells of any other group of the plurality of logical groups; a plurality of logical rows, wherein each row comprises one or more of the plurality of groups, wherein the one or more groups of each row are coupled to second route lines by second connections, wherein the second route lines are selectively coupled to the enable inputs of each of the first and the second feature cells of each group by the second connections, wherein the given group is configured to transmit a second state output signal generated by the given feature cell, the another feature cell, or a combination thereof to a first feature cell of a second group along the second route lines, wherein the first route lines are distinct route lines separate from the second route lines; and a plurality of logical blocks, wherein each block comprises one or more of the plurality of rows, wherein the one or more rows of each block are coupled to third route lines by third connections, wherein a given row is configured to transmit the second state output signal to a first feature cell of a third group of a second row along the third route lines; wherein the plurality of blocks are coupled to fourth route lines by fourth connections, wherein a given block is configured to transmit the second state output signal to a first feature cell of a fourth group of a second block along the fourth route lines.