Patent Document ID: 20170161407
Application ID: 14959121
Patent Flag: 0

Claim One:
1. A method, in a data processing system comprising a processor and a memory coupled to the processor, for addressing coupled noise-based violations, the method comprising: for each net in an integrated circuit (IC) design, determining, by the data processing system, whether an associated delta wire delay is below a predetermined threshold; responsive to the associated delta wire delay failing to be below the predetermined threshold, forming, by the data processing system, a subset of nets; for each net in the subset of nets: adjusting, by the data processing system, a stage delay side model of the net to emulate a noise impact on timing of the net, and applying, by the data processing system, an optimization using the stage delay side model of the net; performing, by the data processing system, a full retiming of the set of nets; and for each net in the subset of nets: determining, by the data processing system, whether the net has degraded slack; and responsive to the net having degraded slack, backing out, by the data processing system, the applied optimization.