Patent Document ID: 9971713
Application ID: 14701371
Patent Flag: 1

Claim One:
1. A parallel computing structure comprising: a plurality of processing nodes interconnected by multiple independent networks, each node including a plurality of processing elements for performing computation or communication activity as required when performing parallel algorithm operations, a first of said networks includes an n-dimensional torus network, n is an integer equal to or greater than 5, including communication links interconnecting said nodes for providing point-to-point and multicast packet communications among said nodes or independent partitioned subsets thereof; said n-dimensional torus network for enabling point-to-point, all-to-all, collective and global barrier and notification functions among said nodes or independent partitioned subsets thereof, wherein combinations of said networks interconnecting said nodes are collaboratively or independently utilized according to bandwidth and latency requirements of an algorithm for optimizing algorithm processing performance; wherein each said processing element is multi-way hardware threaded supporting transactional memory execution and thread level speculation, wherein said plurality of processing elements are configured to run speculative threads in parallel; a cache memory associated with each said processing element at each node, said associated cache memory including a second level (L2) cache supporting thread-level speculative operations (TLS), said TLS operations handling multiple versions of data, and a DMA (direct memory access) network interface for transferring data to/from a cache memory, said DMA interface enabling internode communications that overlap with computations running concurrently on the nodes, wherein a processing element retrieves data by issuing a command and passing the command to each of a stream prefetch engine and a list prefetch engine, the stream prefetch engine and the list prefetch engine for prefetching data to be needed in subsequent clock cycles in a hardware processor of a processing element in response to the passed command, wherein the stream prefetch engine and the list prefetch engine work simultaneously; and wherein the stream prefetch engine is configured to: store the addresses associated with prefetch requests that have been previously issued by the one or more simultaneously operating prefetch engines in a single prefetch data array; determine a slowest data or instruction stream and a fastest data or instruction stream, based on speeds of data or instruction streams processed by the hardware processor, wherein a fast data stream includes data which is requested by the hardware processor but not resident in said single prefetch data array; decrease a prefetching depth of the slowest data or instruction stream, the prefetching depth referring to a specific amount of data or instructions to be prefetched; increase the prefetching depth of the fastest data or instruction stream by the decreased prefetching depth of the slowest data or instruction stream.