Patent Document ID: 9417797
Application ID: 14299195
Patent Flag: 1

Claim One:
1. A storage system comprising: a nonvolatile memory (NVM) comprising at least a first flash memory die having a plurality of flash memory cells; and a solid-state disk (SSD) controller in communication with the NVM memory via a first interface (I/F) that interfaces the NVM with the SSD controller, the SSD controller being configured to execute read commands in order to read the memory cells, and wherein the SSD controller is configured to perform a soft read process during which the SSD controller repeatedly reads one or more pages of the memory cells N times using N respective read reference voltages, V 1 to V N , where N is a positive integer that is equal to or greater than 2, and wherein during the soft read process, the SSD controller calculates N disparity values, ΔV 1 to ΔV N , for the N reads, respectively, and generates a disparity vector comprising the N disparity values, wherein each disparity value is calculated by taking a ratio of a number of 1 bits in a bit sequence corresponding to the respective pages or pages read to a total number of bits in the bit sequence, and wherein during the soft read process, after generating the disparity vector, the SSD controller takes a derivative of the disparity vector to obtain a derivative vector having N−1 derivative values, δ(V 1 ) to δ(V N−1 ), and then uses the disparity vector and the derivative vector to estimate an optimal read reference voltage, V REF,DD , to be used by the SSD controller in a subsequent hard read process to read said one or more pages.