Patent Document ID: 8442825
Application ID: 13200034
Patent Flag: 1

Claim One:
1. A device for voice identification, comprising: a) a receiver, having an input, and having an output; b) a segmenter, having a first input, having a second input, having a third input, and having one output; c) a plurality of infinite impulse response (IIR) resonator digital filters, where each of said plurality of IIR resonator digital filters has an input connected to said output of said segmenter, an output, and further comprises: i. a first register, having a first input, having a second input, having a third input, having a fourth input, having a fifth input, having a first output, having a second output, having a third output, having a fourth output, and having a fifth output; ii. a multiplexer/demultiplexer, having a first input connected to said first output of said first register, having a second input connected to said second output of said first register, having a third input connected to said third output of said first register, having a fourth input connected to said fourth output of said first register, having a fifth input connected to said fifth output of said first register, having a sixth input, having a seventh input, having a control input, having a first output connected to said first input of said first register, having a second output connected to said second input of said first register, having a third output connected to said third input of said first register, having a fourth output connected to said fourth input of said first register, having a fifth output connected to said fifth input of said first register, having a sixth output, having a seventh output, and having an eighth output; iii. a first multiplier, having a first input connected to said sixth output of said multiplexer/demultiplexer, having a second input, and having an output; iv. a second multiplier, having a first input connected to said seventh output of said multiplexer/demultiplexer, having a second input, and having an output; v. a third multiplier, having a first input, having a second input, and having an output connected to said sixth input of said multiplexer/demultiplexer; vi. an adder, having a first input connected to said output of said first multiplier, having a second input connected to said output of said second multiplier, having a third input connected to said output of said third multiplier, and having an output; vii. a subtractor, having a first input connected to said output of said adder, having a second input connected to said eighth output of said multiplexer/demultiplexer, having an output connected to said seventh input of said multiplexer/demultiplexer; and viii. a second register, having a first input, having a first output connected to said first input of said third multiplier, having a second output connected to said second input of said second multiplier, having a third output connected to said second input of said first multiplier, and having a fourth output; d) a resolver, having a plurality of outputs equal to said plurality of IIR resonator digital filters plus 3 additional outputs, and having a plurality of inputs equal to said plurality of IIR resonator digital filters plus one additional input, where each of said plurality of inputs is connected to each of said outputs of each of said plurality of IIR resonator digital filters; e) a first advancer, having an input connected to one of said plurality of outputs of said resolver and an output connected to said second input of said segmenter; f) a second advancer, having an input connected to one of said plurality of outputs of said resolver and an output connected to said one additional input of said resolver; g) a buffer, having a plurality of inputs, three less than said outputs of said resolver that are connected to said plurality of outputs of said resolver, and a plurality of outputs equal to a value of P; h) a display means, where said display has a plurality of inputs such that each of said plurality of inputs of said display means is connected to one of said plurality of outputs of said buffer and said fourth output of said second register; and i) an artificial neural network having a plurality of outputs equal to a value of C and having a plurality of inputs equal to said value of P, where each of said plurality of inputs is connected to each of said plurality of outputs of said buffer.