Patent Document ID: 9928212
Application ID: 14121895
Patent Flag: 1

Claim One:
1. A method for digital signal processing on a device comprising at least one adaptive processor both employing large numbers of adaptation weights (‘M’) and implementing partial-update using adapt-path operations to tune said adaptive processor according to any adaptation criterion, to process a set of signals during and after tuning, said method comprising: operating with lower update set sizes for each adaptation event having M-dimensions by: performing a dimensionality reduction comprising a linear transformation of any processor parameters being adapted from M-dimensions to (M 1 +L)-dimensions in said adaptation event, wherein M 1 weights are adapted without constraints; and, M 0 =M−M 1 weights are subjected to L soft constraints that force those M 0 weights into an L-dimensional subspace spanned by those M 0 weights; applying said dimensionality reduction to any input data; and, then adapting the reduced-dimensionality weights using exactly that same optimization strategy employed by the adaptive processor, except with said input data to which said dimensionality reduction has been applied; thereby effecting in said digital signal processing on said adaptive processor any of the set of: reduction or elimination of misadjustment effects, reduction in complexity and therefore cost of processing, reducing the repetitive processing and comparison, improving efficiency, and providing an inherently more stable approach on a block-by-block basis without introducing explicit hard constraints that lead to jitter.