Patent Document ID: 20070089001
Application ID: 11537043
Patent Flag: 0

Claim One:
1. A method for defect-based scan analysis comprising: for each node in a first circuit, determining its neighborhood net; injecting defects and modeling the defects with stuck-at-0 and stuck-at-1 fault models; generating at least one test pattern and applying the at least one test pattern to the neighborhood net with the injected defects; determining whether the injected defects are observable as faults; adding the test pattern to a set of effective test patterns in response to the defect is observable as a fault; mapping the test patterns in the set of effective test patterns to possible stuck-at-0 fault or stuck-at-1 fault and collecting stuck-at-0 fault test patterns and stuck-at-1 fault test patterns; performing stuck-at-0 fault simulation using the stuck-at-0 fault test patterns and generating a first fault list; performing stuck-at-1 fault simulation using the stuck-at-1 fault test patterns and generating a second fault list; combining the first and second fault lists and deriving a description of the combined fault lists using a complete set of fault models; filtering the combined fault lists to yield a collection of effective faults; and determining a defect for each fault in the collection of effective faults.