Patent Document ID: 9460022
Application ID: 13977688
Patent Flag: 1

Claim One:
1. An apparatus comprising: a processing device to facilitate: translation logic to translate code blocks into code translation blocks, wherein the code translation blocks are submitted for execution; and inference/prediction logic to track, in runtime, dynamic system behavior of the code translation blocks, wherein the dynamic system behavior includes branch behavior being responded to by translating of the code blocks based on static analysis or retranslating of the code blocks based on dynamic analysis, wherein the inference/prediction logic is further to infer translation lookaside buffer (TLB) prefetching based on the dynamic system behavior, wherein tracking further includes detecting, using static analysis or dynamic analysis, TLB patterns based on the TLB prefetching, wherein the inference/prediction logic is further to predict future TLB lookups based on the detected TLB patterns, wherein the inference/prediction logic is further to control the TLB prefetching by enabling or disabling one or more hardware prefetchers or one or more software prefetchers.