Patent Document ID: 20030060985
Application ID: 10224469
Patent Flag: 0

Claim One:
1. A computer-implemented method of defect analysis for a device in which an integrated circuit is formed on each of a plurality of chips on a wafer through a plurality of process steps, comprising the steps of: (a) detecting defects after performing at least one of said plurality of process steps; (b) judging pass/fail of said integrated circuit of each of said plurality of chips after said plurality of process steps; (c) judging presence/absence of any of said defects which satisfies a predetermined discriminating condition on each of said plurality of chips in every said at least one process step; (d) obtaining chip classification data in which said plurality of chips are classified into four sorts on the basis of combination of a judgment result of said step (b) and that of said step (c) in every said at least one process step; (e) calculating the random probability of failure which is a probability that faulty chips not less than the corresponding number of faulty chips with defect should be included in chips of the corresponding number of defective chips which are randomly extracted out of said plurality of chips on the basis of said chip classification data, said corresponding number of defective chips being equal to the number of chips which are judged to have a defect in said step (c), said corresponding number of faulty chips with defect being equal to the number of chips which are judged to have a defect in said step (c) and judged to be failed in said step (b); and (f) judging adoption/rejection of said chip classification data on the basis of said random probability of failure and performing a defect analysis processing on the basis of said chip classification data if adopted, to output an analysis result.