Patent Document ID: 5581742
Application ID: 08352680
Patent Flag: 1

Claim One:
1. A method for emulating a microelectronic device using physically implemented functional modules, the emulation method being adapted for emulating the operation of a proposed design of said microelectronic device having at least two functional modules controlled by a system clock, said method comprising the steps of: (1) testing a plurality of chips, each of said having a plurality of physical functional modules, to identify which of said physical functional modules are defective and which are non-defective, and saving in a megacell library any of said chips having both defective and non-defective physical functional modules; (2) specifying two or more proposed functional modules which will make up said proposed design of said microelectronic device; (3) selecting from said megacell library two or more of said chips, each having both defective and non-defective physical functional modules, each of said selected non-defective physical functional modules being an operational physical implementation of one of said proposed functional modules and comprising more than 1,000 transistors, each of said selected non-defective physical functional modules being physically and functionally identical to one of said two or more proposed functional modules of said proposed design of said microelectronic device; (4) physically interconnecting said selected non-defective physical functional modules from said chips selected from step 3 such that said selected non-defective physical functional modules communicate directly with each other; (5) selecting and applying a clock rate to said interconnected physical functional modules; and (6) applying one or more test vectors to said proposed design using said interconnected physical functional modules, wherein the results of each test vector better simulate in actual function and at operational speed said proposed design as compared to a comparable software- or field-programmable gate array-based simulation of said proposed design.