Patent Document ID: 20150178429
Application ID: 14415275
Patent Flag: 0

Claim One:
1. A method for modeling an SOI (silicon-on-insulator) MOS (metal-oxide semiconductor) device, wherein the SOI MOS device is an SOI MOS device having source-drain injection not reaching a bottom, and the method comprises: establishing an overall model comprising a primary MOS device model simulating an SOI MOS device having the source-drain injection reaching the bottom, a source body PN junction bottom capacitance model simulating a source body PN junction bottom capacitance, and a drain body PN junction bottom capacitance model simulating a drain body PN junction bottom capacitance; and extracting parameters respectively for the primary MOS device model, the source body PN junction bottom capacitance model, and the drain body PN junction bottom capacitance model in the overall model.