Patent Document ID: 9171117
Application ID: 14003361
Patent Flag: 1

Claim One:
1. A method for ranking paths for power optimization of an integrated circuit design, comprising: identifying, by a computer system, a plurality of paths of the integrated circuit design, each path comprising one or more instances of electronic devices; providing an instance power estimate for each instance in the identified paths; providing, for each identified path, at least one weighted power estimate based on the instance power estimates for instances in the path; providing a ranking of the paths based on the least one weighted power estimate, wherein the at least one weighted power estimate comprises at least one of: (a) a distance weighted power estimate for each path calculated as D = 1 I · ∑ i ⁢ ⁢ p i ⁢ wherein pi corresponds to the instance power estimate of instance i in the path and I corresponds to the total number of instances in the path; (b) a logic distance weighted power estimate for each path calculated as L = ∑ i ⁢ ⁢ p i c i wherein pi corresponds to the instance power estimate of instance i in the path and ci corresponds to a predetermined complexity value assigned to instance I; and (c) a timing weighted power estimate for each path calculated as T = ∑ i ⁢ ⁢ p i s i wherein pi corresponds to the instance power estimate of instance i in the path and si corresponds to the time a signal needs to propagate through instance i; and producing an integrated circuit based on the ranking of the paths in the integrated circuit design.