Patent Document ID: 7908131
Application ID: 11554887
Patent Flag: 1

Claim One:
1. A method for creating a reduced-order IC interconnect model comprising: representing an interconnect system of at least one integrated circuit (IC) die by at least one modified nodal analysis equation that is based on frequency, wherein the at least one modified nodal analysis equation comprises at least one system matrix; creating a series expansion for each system matrix that is dependent on interconnect process parameters; and substituting the series expansion for each system matrix that is dependent on interconnect process parameters into the at least one modified nodal analysis equation to create the at least one parameterized modified nodal analysis equation explicitly matching interconnect process parameter terms in the at least one parameterized modified nodal analysis equation to create at least one parameterized system equation; creating a projection from the at least one parameterized system equation to implicitly match frequency terms; creating the reduced-order IC interconnect model using the projection.