Patent Document ID: 20160034808
Application ID: 14716718
Patent Flag: 0

Claim One:
1. A system comprising a computer processor, a computer-readable hardware storage device, and program code embodied with the computer-readable hardware storage device for execution by the computer processor to implement a method for simulating slowest and fastest neural dynamics of a neural model, the method comprising: maintaining neuronal states for multiple neurons in a memory device, wherein each neuron represents an instance of said neural model, and each neuronal state is expressed by one or more variables of said neural model; maintaining neuronal state transition information representing said slowest and fastest neural dynamics of said neural model in a delta-based lookup table, wherein said neuronal state transition information comprises delta values for at least one variable of said neural model; and updating a neuronal state for a neuron based on incoming spike events targeting said neuron and said neuronal state transition information.