Patent Document ID: 5422317
Application ID: 08237325
Patent Flag: 1

Claim One:
1. An integrated circuit simulation methodology for manufacturing an integrated circuit, comprising the steps of: providing a model of electronic devices, each device having an input node, an output node and a time duration between activation of said input node and said output node; applying a computer simulated input signal upon each said input node; sizing select said plurality of electronic devices to achieve a first computer simulated output signal from each said output node having a first time duration and voltage magnitude; configuring a model of each said device at specific locations within an integrated circuit area, and connecting a model of routing between each said device; reapplying said computer simulated input signal upon each said input node; resizing select said electronic devices based on variability of said routing length in order to achieve a second computer simulated output signal from each said output node of a second time duration and voltage magnitude, wherein said second time duration and voltage magnitude is closer than said first time duration and voltage magnitude to an actual time duration and voltage magnitude of an actual output signal emitted during times in which actual said electronic devices are physically embodied within an integrated circuit semiconductor substrate; and obtaining a final layout configuration and processing said final layout configuration upon a silicon substrate to produce an integrated circuit.