Patent Document ID: 9336053
Application ID: 14289756
Patent Flag: 1

Claim One:
1. A method of constructing a logical tree topology in a parallel computer, the parallel computer comprising a plurality of compute nodes, each compute node executing a number of tasks, wherein at least one compute node executes a number of tasks that is different than the number of tasks executed by another one of the compute nodes, the method comprising: identifying a compute node from the plurality of compute nodes executing a greatest number of tasks; selecting, as a global root in a logical tree topology, a task from the identified compute node, including assigning the task as a local root of the identified compute node and assigning each of the other tasks of the identified compute node as a child of the local root; selecting, from each of the other compute nodes, one task to be a local root in the logical tree topology, including assigning each task other than the local root as a child of the local root; and assigning each local root of the other compute nodes to be a child of one of the tasks of the identified compute node other than the global root; performing a reduce operation in the logical tree topology including: transmitting, by each task of a compute node other than the identified compute node, reduce data to the local root of the compute node through shared memory, including performing a reduction operation on the reduce data; transmitting, in parallel by each local root of a compute node other than the identified compute node, the reduce data to the task of the identified compute node assigned to be a parent of the local root, including performing the reduction operation on the reduce data; and transmitting, through shared memory by each of the tasks of the identified compute node, the reduce data to the global root including performing the reduction operation on the reduce data.