Patent Document ID: 7506294
Application ID: 11601601
Patent Flag: 1

Claim One:
1. A method for modeling an integrated circuit (IC), comprising: specifying a first layout for the integrated circuit, wherein the first layout includes a plurality of devices and a specification of parameters, placement and routing for the devices; specifying a second layout for the integrated circuit by changing placement of at least one device in the specification of the first layout; approximating an operating point for the first layout by separating a plurality of first-layout voltage values into nearby components and far-away components; approximating an operating point for the second layout that corresponds to the operating point of the first layout by separating a plurality of second-layout voltage values into nearby components and far-away components, wherein nearby components of the first-layout voltage values and the second-layout voltage values are calculated from equivalent matrix operations on corresponding first-layout current values and second-layout current values, and far-away components of the first-layout voltage values and the second-layout voltage values are calculated from equivalent matrix operations on corresponding first-layout current values and second-layout current values including a shifting of values corresponding to differences between the first layout and the second layout; and saving at least some values for the integrated circuit.