Patent Document ID: 8782591
Application ID: 13732364
Patent Flag: 1

Claim One:
1. A method of designing an integrated circuit, the method comprising: translating a register transfer level (RTL) input file describing an integrated circuit design into a plurality of Boolean logic equations; translating the plurality of Boolean logic equations into a plurality of logic primitives; placing the plurality of logic primitives into a floorplan of the integrated circuit design, the placement of the plurality of logic primitives defining wire interconnects between the plurality of logic primitives; calculating wire timing delays associated with the defined wire interconnects in response to placement coordinates of the placement of the plurality of logic primitives; and optimizing each of the plurality of Boolean logic equations in response to the wire timing delays associated with the defined wire interconnects; wherein one or more of the translating, the placing, the calculating, and the optimizing are performed with a processor.