Patent Document ID: 5577262
Application ID: 08522163
Patent Flag: 1

Claim One:
1. An interconnection system for a plurality of processing elements (PEs) each having a plurality of I/O ports for transmitting and receiving data and instructions, the interconnection system comprising: coupling means for interconnecting the plurality of PEs, the 6 coupling means including all of the inter-PE couplings present in a square torus configuration having an equal number of PEs as in said plurality of PEs, the coupling means implementing half the number of inter-PE couplings required in the torus configuration by sharing each non-diagonal PE's (PE.sub.ij) I/O ports with its associated symmetrical PE (PE.sub.ji), thereby forming a symmetric PE including PE.sub.ij and PE.sub.ji, where i and j are column and row designators, respectively, of corresponding PEs in the torus configuration, and where i and j are non-equal non-zero positive integers, and wherein the coupling means further includes means for transmitting and receiving data and instructions in one of four selectable modes: a) transmit east/receive west mode for transmitting data to an east PE over a portion of the I/O ports while receiving data from a west PE over a remaining portion of the I/O ports; b) transmit north/receive south mode for transmitting data to a north PE over a portion of the I/O ports while receiving data from a south PE over a remaining portion of the I/O ports; c) transmit south/receive north mode for transmitting data to the south PE over a portion of the I/O ports while receiving data from the north PE over a remaining portion of the I/O ports; and d) transmit west/receive east mode for transmitting data to the west PE over a portion of the I/O ports while receiving data from the east PE over a remaining portion of the I/O ports.