Patent Document ID: 4689740
Application ID: 06317693
Patent Flag: 1

Claim One:
1. A system for data transmission comprising: (A) at least one master transmitting station which is capable of controlling data transmission, comprising: (a) a clock terminal; (b) a data terminal; (c) means for producing a clock signal at the clock terminal by allowing the clock terminal to assume a second voltage level for each of a series of periodic clock pulse intervals and by forcing the clock terminal to a first voltage level at all other times during production of the clock signal; (d) means for producing a start signal which indicates that the master station is prepared to control data transmission by allowing the voltage level at the data terminal to assume a second voltage level for a first fraction of a clock pulse interval and by then forcing the voltage at the data terminal to a first voltage level during the same clock pulse interval; (e) means for producing a stop signal which indicates that the master station has finished controlling data transmission by forcing the voltage level at the data terminal to the first voltage level during a first fraction of a clock pulse interval and then allowing the voltage at the data terminal to transition to the second voltage level during the same clock pulse interval; (f) means for transmitting binary data by forcing the voltage at the data terminal to the first voltage level during an entire clock pulse interval to transmit a first data value and by allowing the voltage at the data terminal to assume the second voltage level during an entire clock pulse interval to transmit a second data value; and (g) at least all but one of the master transmitting stations further comprising means for establishing priority when a plurality of master stations simultaneously attempt to control data transmission which detect the voltage level at the data terminal and which cause the master station which contains said means for establishing priority to cease attempted control of data transmission by allowing the data terminal and the clock terminal to assume the second voltage level for at least a predetermined interval after detection of the first voltage level during a clock interval in which that master station has allowed the data terminal to assume the second voltage level; (B) at least one receiving station comprising a data terminal and a clock terminal; (C) a data bus which interconnects the data terminals of all the stations; (D) a clock bus which interconnects the clock terminals of all the stations; and (E) means which maintain the buses at the second voltage level in the absence of forcing by the stations.