Patent Document ID: 20090204767
Application ID: 12030501
Patent Flag: 0

Claim One:
1. A method for cache and memory performance analysis and modeling, the method comprising: receiving a cache-line set associative parameter input value; receiving input values in regard to a number of LRU tree levels that are to be analyzed; receiving input values in regard to a number of LRU-analysis groups per LRU tree level into which a cache-line set is to be divided; determining if a total of the input values for the LRU analysis groups per LRU tree level for a cache-line set is equal to the cache-line set associative parameter input value; identifying the analysis group within a cache-line set that comprises an oldest MRU for all but a root level of the LRU tree; identifying a LRU set-index within a root level analysis group comprising the oldest MRU within a preceding parent LRU-tree level; and returning a LRU set-index for replacement that is identified by a true-LRU that is retrieved from the root level analysis group.