Patent Document ID: 8312402
Application ID: 12423714
Patent Flag: 1

Claim One:
1. A method of determining a distribution of voltages or currents in an integrated circuit (IC) in response to energizing the circuit design with an exemplary bias, wherein the IC includes one or more layers that each include a top wall, a bottom wall and a sidewall that connects the top wall and the bottom wall and the one or more layers are disposed on a substrate, the method comprising: discretizing an exemplary current that flows in each layer in response to an application of an exemplary bias into a plurality of current vector elements on said layer, wherein the current-vector elements include top-wall current-vector elements that discretize current flow in the top wall of said layer, bottom-wall current-vector elements that discretize current flow in the bottom wall of said layer, and sidewall current-vector elements that discretize current flow in the sidewall that connects the top wall and the bottom wall of said layer; projecting the top-wall current-vector elements, the bottom-wall current-vector elements and the sidewall current-vector elements onto a grid that includes a plurality of sub-grids that each include multiple grid points, wherein the sub-grids include one or more top grids for the one or more top walls and one or more bottom grids for the one or more bottom walls; determining for each layer from the projected current vector elements a spectrum of an electromagnetic (em) field induced in the layer by using impedance values for the one or more layers and the substrate to extend the em field across the IC; determining a distribution of voltages induced in each layer from the spectrum of the em field induced in said layer; and saving one or more values for the voltages in a computer-readable medium.