Patent Document ID: 10095814
Application ID: 14185514
Patent Flag: 1

Claim One:
1. A device, comprising: one or more processors to: determine that a model is associated with an optimization, the model including a plurality of model elements and a plurality of delay elements, the optimization including: modifying throughput associated with the model, modifying a critical path associated with the model, and pipelining the model; the model being associated with a total quantity of delay; receive delay information that identifies a model element, of the plurality of model elements, and a constraint quantity of delay associated with the model element; determine a quantity of accumulated delay associated with the model element based on the model; determine one or more retiming values associated with the plurality of model elements based on comparing the quantity of accumulated delay associated with the model element to the constraint quantity of delay associated with the model element; redistribute, via distributed pipelining and based on the optimization, quantities of delay among the plurality of delay elements associated with the model to obtain a redistributed model, based on the one or more retiming values, to satisfy the constraint quantity of delay associated with the model element, and to maintain the total quantity of delay associated with the model, where the quantities of delay are redistributed to shorten the critical path between two of the plurality of delay elements without adding additional latency, where latency is a time delay between an input of the model and output of the model generated based on the input; and provide the redistributed model.