Patent Document ID: 20050156626
Application ID: 11025785
Patent Flag: 0

Claim One:
1. A system for improved optimal mapping of LUT based FPGAs comprising: a Directed Acyclic Graph (DAG) representation of the network to be mapped, a sorter that operates on said DAG to reduce its complexity, a Dependency Definer that determines the dependency of each node in the DAG, a Reconvergent Path Locator (RPL) that determines feasible reconvergent paths from transitive fan-ins of each said node, a Priority Determiner (PD) that determines the priority of all the child nodes of each said node, a Node Sorter (NS) that sorts the list of child nodes in descending order of priority, a Mapper (M) that assigns LUT's to the child nodes from the beginning of said sorted list until the node dependency is less than one plus the number of LUTs, an Assignor (A) that assigns an LUT to each output of a particular node.