Patent Document ID: 10133841
Application ID: 15282792
Patent Flag: 1

Claim One:
1. A computer implemented method for implementing three-dimensional or multi-layer integrated circuit designs, comprising: identifying, with one or more connectivity modules including or coupled with at least one micro-processor of a computing system, an electronic design and a plurality of inputs for implementing connectivity for the electronic design; reducing at least one first data structures storing the electronic design to at least one first reduced data structure based at least in part upon an identification of an interface portion between at least two layers in the electronic design; reducing the at least one first reduced data structure into at least one second reduced data structure at least by performing one or more net distribution analyses that generate net distribution analysis results; and implementing the connectivity between multiple layers in the electronic design at least by assigning a bump in a bump array in the second reduced electronic design to a net connecting a first layer and a second layer in the electronic design based in part or in whole upon the net distribution analysis results.