Patent Document ID: 6091263
Application ID: 08989746
Patent Flag: 1

Claim One:
1. A field programmable gate array (FPGA) comprising: a first array of configurable logic blocks having a corresponding first set of configuration memory cells; a first configuration cache memory array coupled to the first array of configurable logic blocks, wherein the first configuration cache memory array stores values to be loaded into the first set of configuration memory cells, thereby reconfiguring the first array of configurable logic blocks; a second array of configurable logic blocks having a corresponding second set of configuration memory cells; a second configuration cache memory array coupled to the second array of configurable logic blocks, wherein the second configuration cache memory array stores values to be loaded into the second set of configuration memory cells, thereby reconfiguring the second array of configurable logic blocks; and a control circuit for transferring values between the first configuration cache memory array and the first set of configuration memory cells, and for independently transferring values between the second configuration cache memory array and the second set of configuration memory cells.