Patent Document ID: 8165861
Application ID: 11795511
Patent Flag: 1

Claim One:
1. Simulation method of an electronic circuit or a printed circuit, represented in the form of masks and connections, comprising: a) defining, on one hand, inputs and outputs of circuit networks of the electronic circuit, and, on the other, internal components of each network, b) forming a reduced model of each network comprising: b1)•forming a conductance matrix or a resistance matrix, and also forming: a susceptance matrix; a susceptance and inductance matrix; or a susceptance, inductance and reluctance matrix, of inputs and internal components of the network, b2)•forming a first reduced digital model of said conductance or resistance matrix, and of said susceptance matrix; susceptance and inductance matrix; or susceptance, inductance and reluctance matrix, c) simulating the network using the first reduced digital model, d) in an event of an unsatisfactory simulation result, modifying part of the masks and/or connections of one or more networks, forming a second reduced digital model, and simulating with said new reduced model, e) in an event of a satisfactory simulation result, producing the circuit, wherein couplings between the circuit networks are low couplings, a network being subject to low coupling if the number n e of external nodes of the network is below the number n i of specific internal nodes of the network.