Patent Document ID: 20080209385
Application ID: 12117656
Patent Flag: 0

Claim One:
1. A method for mapping look-up table (LUT) based field programmable gate arrays (FPGAs), the method comprising: representing a network to be mapped using a Directed Acyclic Graph (DAG), the DAG including a plurality of nodes v; traversing individual nodes v in the DAG; computing a dependency variable dv for individual traversed nodes v based on its input(s) and output(s); and assigning a LUT to a traversed node v if at least one of the following conditions is satisfied: if its dv>k, with k representing a number of LUT inputs; if its dv>1 and a number of fanouts from that traversed node v is >2; or if a number of fanouts from that traversed node v is >3.