Patent Document ID: 7636857
Application ID: 10878729
Patent Flag: 1

Claim One:
1. A data processor for ciphering and transferring data between a first memory unit and a second memory unit, the data processor comprising: a ciphering engine for ciphering data while it is being transferred between the memory units; a multiplexer (MUX); first and second data registers electrically coupled to an output of the MUX; a data-mover controller, separate from the ciphering engine, the data-mover controller including at least one register having a first field specifying whether the data should be allowed to pass through the ciphering engine, which outputs the data to the MUX via a first path after ciphering the data, or whether the data should be transferred directly to the MUX via a second path without passing through the ciphering engine; a processor electrically coupled to the first memory unit and the second memory unit for writing a control block into the first memory unit, the control block including control parameters needed to configure the data-mover controller, and for outputting a control signal to the data-mover controller to initiate a data moving operation; a first controller electrically coupled to the first memory unit and the first data register, the data mover controller and the processor for controlling the first memory unit; and a second controller electrically coupled to the second memory unit and the second data register, the data mover controller and the processor for controlling the second memory unit, wherein the data-mover controller retrieves the control block from the first memory unit in response to receiving the control signal from the processor, and the data-mover controller determines which type of function is to be performed based on the control parameters in the retrieved control block.