Patent Document ID: 8719736
Application ID: 13838845
Patent Flag: 1

Claim One:
1. A method for correcting topography proximity effects (TPE) for an integrated circuit (IC) design, the method comprising: dividing the IC design into a plurality of levels; for each level, decomposing the level into one or more elementary geometries; comparing the one or more elementary geometries to primitives in a library, the library being a transfer matrix library generated by accurate simulation or an empirical data set; generating a transfer matrix using matching primitives provided by said comparing the one or more elementary geometries; calculating, using a computer, a disturbance matrix based on the transfer matrix, the disturbance matrix capturing a spectrum of a reflective electric field from a spectrum of an incident electric field; performing wave propagation through a layer or layers using the disturbance matrix for the plurality of levels; and computing a light intensity for TPE correction based on the wave propagation.