Patent Document ID: 7603656
Application ID: 11036896
Patent Flag: 1

Claim One:
1. A method of modeling concurrent execution language, comprising: providing a hardware description language (HDL) code; mapping a modular structure of said HDL code onto a hierarchical structure of a Rose diagram type, said hierarchical structure of said Rose diagram type comprising multiple classes, each of said multiple classes representing a group of multiple objects, and one or more of said multiple classes being defined to represent a respective function module of said HDL code; and using said hierarchical structure as a framework to develop an object oriented language code; wherein at least one function module of said HDL code comprises one or more properties and one or more functions; and wherein one or more objects of at least one of said multiple classes represents said one or more properties of said HDL code function module; and wherein one or more operations of at least one of said multiple classes represents said one or more functions of said HDL code function module.