Patent Document ID: 20170032075
Application ID: 14810428
Patent Flag: 0

Claim One:
1. A system for discovering unknown problematic circuit patterns in a chip design layout of manufactured semiconductor devices, comprising: a critical signature library constructed by configuring a storage device, said critical signature library having at least one critical signature database stored in said storage device, each critical signature database including a plurality of known problematic circuit patterns extracted from said chip design layout, each problematic circuit pattern having associated physical data measured from the manufactured semiconductor devices and simulation data generated based on said chip design layout; a statistical model creator interfacing with said critical signature library and creating at least one statistical model based on said plurality of known problematic circuit patterns according to a target specification based on deviation between the associated physical data and simulation data or design data, said at least one statistical model being saved in the corresponding critical signature database having said plurality of known problematic circuit patterns; a statistical model based predictor interfacing with said critical signature library, receiving a plurality of candidate circuit patterns, predicting and labeling each of said plurality of candidate circuit patterns as being problematic or not according to said at least one statistical model; wherein said statistical model predictor further saves each candidate circuit pattern labelled as being problematic in the corresponding critical signature database if the candidate circuit pattern labelled as being problematic does not match any of said plurality of known problematic circuit patterns in the corresponding critical signature database.