Patent Document ID: 20140033162
Application ID: 13562189
Patent Flag: 0

Claim One:
1. A method for optimizing a circuit design, the method comprising: receiving the circuit design; selecting a portion of the circuit design that includes a driver gate that drives one or more inputs of each gate in a set of gates; modeling a gate optimization problem for the portion of the circuit design based on circuit information that includes generic logical effort values of each gate in the set of gates, an input capacitance value and a specific logical effort value of the driver gate, and wire resistance and capacitance values of a net that electrically connects an output of the driver gate with one or more inputs of each gate in the set of gates, wherein said modeling includes constructing a differentiable objective function that minimizes the maximum delay from the driver gate to each gate in the set of gates; executing a conjugate-gradient based numerical solver to solve the set of gate optimization problems; incrementally computing a gradient of the differentiable objective function; and providing the gradient to the conjugate-gradient based numerical solver.