Patent Document ID: 20040225978
Application ID: 10435129
Patent Flag: 0

Claim One:
1. A computer implemented method of deriving gated clock circuitry in an integrated circuit design comprising: identifying sequential elements in the design; identifying respective feedback loops in the design associated with respective identified sequential elements in the design; wherein respective identified feedback loops can alternatively provide load data or provide reload data to their associated sequential elements; for each of respective one or more identified sequential elements with respective at least one associated feedback loop, producing a feedback loop signature associated with such sequential element, that indicates respective feedback elements, indicates respective positions of the indicated feedback elements and indicates respective feedback control signals applied to the indicated feedback elements; evaluating the feedback loop signature associated with such sequential element so as to generate associated stimulus logic that, receives as input at least one associated feedback loop control signal; and provides as output an associated clock control signal that has a clock enable value during clock intervals when an associated load value would be provided to such sequential element by its associated feedback loop and that has a clock disable value during clock intervals when an associated reload value would be provided to such sequential element by its associated feedback loop; generating associated load logic by breaking the at least one associated feedback loop and removing at least one feedback element associated with the at least one broken feedback loop, so as to generate associated load logic that, receives as input at least one associated feedback loop control signal; and provides as output at least one load data signal during clock intervals when the associated stimulus logic signature produces an associated clock control signal with a clock enable value.