Patent Document ID: 20070296438
Application ID: 11420104
Patent Flag: 0

Claim One:
1. A method of designing a probe card for electrically testing die on a wafer in parallel, comprising: determining a plurality of parameters; creating an initial population of individual probe card contactor test site patterns having a selected size; copying the initial population to a current population and incrementing a generation counter by one; determining which individuals in the current population are fittest and assigning a fitness value to each individual; determining whether to at least one of alter and reproduce a plurality of selected individuals determined to be fittest from the current population; copying the selected individuals and fitness values to a new population; determining if the new population has reached the selected size; continuing to determine selected individuals to copy to the new population until the new population reaches the selected size; evaluating each individual of the new population against a stop criteria and ending the method if a stop criteria is obtained; copying the new population to a current population and incrementing the generation counter by one; and continuing with determining which individuals in the current population are fittest until the stop criteria are obtained.