Patent Document ID: 5490266
Application ID: 08192185
Patent Flag: 1

Claim One:
1. A logic simulator for simulating the operation of a logic network in a computer system, said logic simulator comprising: means for defining a plurality of signals using state information associated with each signal of said plurality of signals in an execution cycle, said state information including a definition of a current state of a current execution cycle and a prior state of a prior execution cycle of each signal of said plurality of signals; means for defining a logic process associated with a group of said plurality of signals, said logic process having input corresponding to one or more signal inputs of said group of said plurality of signals associated with said logic process, said logic process having output corresponding to one or more signal outputs of said group of said plurality of signals associated with said logic process, said logic process including simulation logic defining a relationship between said input of said logic process and said output of said logic process, said simulation logic further including a definition of interconnections between signals of said group of signals associated with said logic process; means for defining sensitivity information including a definition of which of said plurality of signals affect said output of said logic process; means for applying input signals to said input of said logic process; means for executing in successive execution cycles said simulation logic of said logic process to produce output signals on said output of said logic process, said means for executing further including means for updating said state information; means for executing in successive execution cycles only said simulation logic associated with a signal specified in said sensitivity information that has changed state since said signal was last evaluated or that has an unknown prior state; means for determining if said output of said logic process is either no longer changing state or changing state in a predictable manner thereby indicating that the logic process is stable; and means for continuing to propagate, evaluate and update said simulation logic in successive execution cycles until said output of said logic process is either no longer changing state or changing state in a predictable manner thereby indicating that the logic process is stable.