Patent Document ID: 9430442
Application ID: 13954857
Patent Flag: 1

Claim One:
1. A method for using a constraints solver to solve a gate optimization problem for a portion of a circuit design, the method comprising: creating a constraints problem based on the gate-sizing optimization problem for the portion of the circuit design, wherein the constraints problem comprises: (1) a constraint for each equation in the gate-sizing optimization problem, (2) a set of upper bound constraints that impose an upper bound on one or more variables that are used in the objective function of the gate-sizing optimization problem, (3) constraints that impose upper bounds, lower bounds, or both upper bounds and lower bounds on capacitance variables based on one or more of (i) estimated capacitance values, (ii) maximum capacitance values of gates in a technology library, and (iii) minimum capacitance values of gates in the technology library, and (4) a task definition that computes the value of the objective function of the gate-sizing optimization problem; and solving the gate-sizing optimization problem by repeatedly solving the constraints problem using a constraints solver that is executing on a processor, wherein prior to each invocation of the constraints solver the upper bound is increased or decreased based at least on a result returned by a previous invocation of the constraint solver.