Patent Document ID: 6138209
Application ID: 08924272
Patent Flag: 1

Claim One:
1. A data processing system, comprising: (a) a memory configured to store information at a plurality of memory addresses; (b) a processor configured to issue a memory access request for information referenced by a selected memory address; (c) a first cache coupled to the processor and the memory and configured to cache a first portion of information from the memory, the first cache including a first cache directory including a plurality of first cache directory entries; (d) a second cache coupled to the processor and configured as a multi-way set associative cache that caches a second portion of information from the memory, the second cache including a second cache directory including a plurality of second cache directory entries, each of which is associated with one of a plurality of classes, wherein the selected memory address is related to a set of corresponding second cache directory entries respectively associated with the plurality of classes; (e) a class predict data structure separate from the first cache directory and including a plurality of predict entries of predicted classes, at least one of the plurality of predict entries including a predicted class for the set of corresponding second cache directory entries related to the selected memory address, wherein the class predict data structure comprises a class predict table including a plurality of table entries, each including a plurality of array elements, each array element associated with a different one of the plurality predict entries; (f) a first access unit configured to initiate an access to the class predict data structure during processing of the memory access request by the first cache to determine the predicted class for the set of corresponding second cache directory entries related to the selected memory address; and (g) a second access unit configured to access the corresponding second cache directory entry associated with the predicted class from the set of corresponding second cache directory entries to determine a cache hit or miss for the selected memory address.