Patent Document ID: 9912341
Application ID: 13783054
Patent Flag: 1

Claim One:
1. An apparatus, comprising: a first array of capacitances coupled to a common node, each successive capacitance of the first array having a capacitance value that is less than a capacitance value of a previous adjacent capacitance, according to a predetermined non-binary numerical pattern; and a second array of capacitances coupled to the common node, each capacitance of the first array having an associated capacitance within the second array with an approximately equivalent capacitance value, the first array and the second array in combination arranged to determine a digital approximation for an analog input value, wherein the voltage at the common node is based on one or more capacitors of the first array being coupled to a reference voltage or to the ground potential and the voltage at the other common node is based on one or more capacitors of the second array being coupled to the reference voltage or to the ground potential, the one or more capacitors of the first array and/or the one or more capacitors of the second array being coupled to the reference voltage or to the ground potential in pairs, each pair comprising a capacitor of the first array and an associated capacitor of the second array, according to a search algorithm.