Patent Document ID: 20150039664
Application ID: 13954857
Patent Flag: 0

Claim One:
1. A method for using a constraints solver to solve a gate optimization problem for a portion of a circuit design, the method comprising: creating a constraints problem based on the gate-sizing optimization problem for the portion of the circuit design, wherein the constraints problem comprises: a constraint for each equation in the gate-sizing optimization problem, a set of upper bound constraints that impose an upper bound on one or more variables that are used in the objective function of the gate-sizing optimization problem, and a task definition that computes the value of the objective function of the gate-sizing optimization problem; and solving the gate-sizing optimization problem by repeatedly solving the constraints problem using a constraints solver that is executing on a processor, wherein prior to each invocation of the constraints solver the upper bound is increased or decreased based at least on a result returned by a previous invocation of the constraint solver.