Patent Document ID: 20030140287
Application ID: 10047344
Patent Flag: 0

Claim One:
1. A method for the elimination of one or more redundant tests and the reordering of one or more inefficient tests in digital integrated circuits (IC's), further comprising: for each test of a sequence of N tests, compiling L common defective dice, wherein said N tests comprise one or more redundant tests and one or more inefficient tests; representing each test of the sequence of N tests as a correlation vector such that the sequence of N tests is represented as N correlation vectors; finding a first correlation vector of the N correlation vectors that has the most non-zero components and initialize a vector W to be the complement of the first correlation vector; for each correlation vector of the remaining N-1 correlation vectors, calculating a product of the complement of each correlation vector and the vector W; calculating a length of a projection of each calculated product vector onto a unit vector; finding the correlation vector of the N-1 correlation vectors that has a smallest value of the projection length; updating the vector W to be a product of vector W and a compliment of the determined correlation vector in the previous step; and repeating the previous four elements, until the length of the projection of vector W onto the unit vector is zero.