Patent Document ID: 7937678
Application ID: 12137298
Patent Flag: 1

Claim One:
1. A method for planar netlist interpretation of an integrated circuit, the method comprising: reading the planar netlist of the integrated circuit from a first computer-readable medium, wherein the planar netlist comprises atomic elements of the integrated circuit and nodes between the atomic elements; converting, using a computer system, the planar netlist into a graphical description, wherein graph vertices represent the atomic elements, the nodes, or both, and wherein graph edges represent the nodes, the atomic elements, or connections between the atomic elements and the nodes, respectively; identifying, using the computer system, combinations of the vertices and edges that match library device elements; substituting, using the computer system, the device elements for the respective combinations of the vertices and edges; generating, using the computer system, a compressed netlist comprising the device elements and nodes between the device elements; and storing the compressed netlist in a second computer-readable medium.