Patent Document ID: 8612501
Application ID: 12601453
Patent Flag: 1

Claim One:
1. A method for generating binary random bits (S (DOA)i ) based on a dual oscillator architecture with a continuous-time chaotic oscillator and relying on generating non-invertible random binary bits from one state which corresponds to one signal of the continuous-time chaotic oscillator, the method comprising: obtaining x 1j , x 2j ,. .. or x nj values at rising edges of an external periodical pulse signal by using one of a plurality of states x 1 , x 2 ,. .. or x n of the continuous-time chaotic oscillator at times t satisfying f s H (x 1(f) , x 2(f) ,. .. or x n(f) )t mod 2π=0, where f s is a center frequency of a slower clock and f s H( ) is a transfer function of a voltage-controlled oscillator (VCO) or a current-controlled oscillator (CCO); obtaining the slower clock periods T slow1j , T slow2j ,. .. or T slownj values by 1/(f s H (x 1j , x 2j ,. .. or x nj )); obtaining a sum of the slower clock periods T slow1j , T slow2j ,. .. or T slownj values from j=1 to j=i; dividing the sum of the slower clock periods to T fast /2 where T fast is the period of the fast clock; performing mod 2 (modulo 2 operator) operation on the obtained division result of the sum of the slower clock periods; and generating a random binary sequence S (DOA)i , which is the logical inverse of the mod 2 operation result, or S (DOA)i , by S (DOA)i =S (DOA)(i-1) , if the logical inverse of the mod 2 operation result is 0, and S (DOA)i =the logical inverse of S (DOA)(i-1) , if the logical inverse of the mod 2 operation result is 1.