Patent Document ID: 5521837
Application ID: 08376138
Patent Flag: 1

Claim One:
1. A method for laying out a logic design made up of logic elements and connections onto a logic device having logic blocks, wire segments, and means for connecting said wire segments to form routes, comprising the steps of: specifying said logic design in machine readable form; placing each of said logic elements into one of said logic blocks; estimating lower bound connection delays L(c) for connections in said logic design; selecting delay limits U(c) for each of said connections, each of said delay limits being selected to be greater than or equal to a corresponding one of said lower bound connection delays; routing said connections wiring segments of said logic device to connect said logic elements which have been placed in said logic blocks, for which actual delays D(c) result, said routing step being performed such that at least some of said delay limits U(c) are not exceeded by said actual delays D(c).