Patent Document ID: 20060190912
Application ID: 11065409
Patent Flag: 0

Claim One:
1. A method for identifying an area in a mask layout which is likely to cause manufacturing problems, the method comprising: creating an on-target process model that models a semiconductor manufacturing process under nominal (e.g., optimal) process conditions; creating one or more off-target process models that model the semiconductor manufacturing process under one or more arbitrary (e.g., non-optimal) process conditions; computing a process-sensitivity model using the on-target process model and the one or more off-target process models, wherein the process-sensitivity model can be represented by a multidimensional function; and identifying a problem area in the mask layout using the process-sensitivity model, wherein identifying the problem area allows it to be corrected, thereby improving the manufacturability of the mask layout; wherein using the process-sensitivity model to identify the problem area reduces the computational time required to identify the problem area.