Patent Document ID: 20060090150
Application ID: 10972899
Patent Flag: 0

Claim One:
1. A method for reducing timing pessimism during Static Timing Analysis (STA), the method comprising: receiving parametric variation data which describes the variation of timing-related parameters over a chip; computing region-specific derating factors using the parametric variation data; identifying a set of worst-case violating paths using the region-specific derating factors; computing path-specific derating factors for one or more paths in the set of worst-case violating paths using the parametric variation data; and identifying zero or more realistic-case violating paths from the set of worst-case violating paths using the path-specific derating factors; wherein the method reduces the timing pessimism because the method identifies realistic-case violating paths using the fine-grained path-specific derating factors instead of using the coarse-grained region-specific derating factors; wherein the method saves computational time by first identifying a set of worst-case violating paths and then identifying the realistic-case violating paths from the set of worst-case violating paths, instead of directly identifying the realistic-case violating paths from the set of all possible paths.