Patent Document ID: 9400311
Application ID: 14675365
Patent Flag: 1

Claim One:
1. A method of detecting and diagnosing failures and faults in a plurality of chips implementing a common design, the method comprising: for each chip in the plurality of chips: receiving, by a chip failure detection device, one or more input patterns of one or more inputs predetermined under a testing scheme predetermined for the common design of the plurality of chips, the testing scheme including an expected output pattern of one or more expected outputs for each input pattern, for each supplied input pattern, capturing a resulting output pattern and comparing the resulting output pattern with the expected output pattern, and for each resulting output pattern that does not match the expected output pattern, recording one or more real failures, each real failure representing at least one unexpected output of the resulting output pattern and recorded in association with the chip and the input pattern; generating, in a chip modeling module, a simulated chip model having the common design of the plurality of chips; running, in a chip simulation module using the simulated chip model, a simulation, in which the one or more input patterns are applied in the simulation to each of a plurality of simulated faults, and each simulated unexpected output pattern resulting from a simulated input pattern and a simulated fault is recorded as one or more simulated failures, each simulated failure representing at least one unexpected output of the simulated unexpected output pattern and recorded in association with the simulated input pattern and the simulated fault; for each simulated fault, compiling a simulation report including all simulated failures associated with the simulated fault; and for each chip in the plurality of chips, compiling a chip failure report including all real failures associated with the chip, for each simulated fault, comparing the real failures of the chip failure report to the simulated failures of the simulation report of the simulated fault, and generating a chip diagnosis report including at least one result of the comparison.