Patent Document ID: 9152606
Application ID: 14016698
Patent Flag: 1

Claim One:
1. A digital hardware logic system for exchanging information between an array of processing cores for processing a set of data processing tasks and task-specific memory segments, the system comprising: a first set of multiplexers, wherein each multiplexer of the first set of multiplexers is specific to one of the task-specific memory segments; a second set of multiplexers, wherein each multiplexer of the second set of multiplexers is specific to one of the processing cores of the array; and a hardware logic module, referred to as a controller, which is configured to periodically, for each of the processing cores in the array of processing cores, assign an individual data processing task of said set of data processing tasks for processing, provide input selection configuration for at least one multiplexer among said first set of multiplexers, and provide input selection configuration for at least one multiplexer among said second set of multiplexers.