Patent Document ID: 20080320422
Application ID: 11574496
Patent Flag: 0

Claim One:
1. A design rule checking system for checking compliance of an integrated circuit design with one or more design rules, the design rule checking system comprising: means for applying a model of the variation of systematic yield loss with respect to a geometric parameter of said integrated circuit design, a limit value of said geometric parameter being specified in a design rule of said one or more design rules, the means for applying includes calculation means adapted to apply a non-binary model of how systematic yield loss varies with respect to said geometric parameter whereby to calculate a value for systematic yield loss when said geometric parameter takes a value specified in said integrated circuit design; means for detecting conflict between design rules specifying respective limit values for a first geometric parameter, and means for selecting a value for said first geometric parameter by modelling systematic yield loss for each of said conflicting designs using a respective non-binary model, and determining what is the minimum achievable value of systematic yield loss, according to said respective non-binary models, if the conflicting design rules are respected.