Patent Document ID: 10140405
Application ID: 15387958
Patent Flag: 1

Claim One:
1. A method for finding logical equivalence between a register transfer level abstraction and a synthesized netlist comprising: receiving a register transfer level abstraction and a synthesized netlist of the register transfer level abstraction in an apparatus, wherein the apparatus comprises a processor configured to run a simulation for the synthesized netlist and the register level abstraction and further comprises a memory configured to store an equivalence representation model of the synthesized netlist and the register level abstraction, wherein the apparatus is configured to provide a mechanism for bug-fixing in a circuit design software; storing the register transfer level abstraction and the synthesized netlist into the equivalence representation model in the memory; associating, via the processor configured to run the simulation for the synthesized netlist and the register level abstraction, one or more netlist terminals with one or more corresponding register transfer level entities based on a name of the register transfer level entity matching a name of a netlist terminal; simplifying the register transfer level abstraction and the synthesized netlist by removing a set of unneeded register transfer level entities in the equivalence representation model stored in the memory; minimizing one or more nets in the netlist by: determining immediate operands for each of the one or more nets; determining if the one or more nets of the netlist are logical equivalents based on the determined immediate operand; and associating the one or more determined nets and storing the associations in the equivalence representation model; matching each register transfer level wire to a netlist net by: traversing the register transfer level abstraction from a bottom wire to a top wire of the abstraction; and minimizing each wire in the register transfer level abstraction by: determining immediate operands for each of the one or more register transfer level wires; determining if the register transfer level wire is a logical equivalent to one or more of the stored associated nets; and associating each register transfer wire with a determined equivalent net and storing the associations in the equivalence representation model; determining from the associations of the entities and terminals if each register transfer level wire is associated with a net of the same name; determining if each wire and net of the same name are logically equivalent by running simulations and comparing a set of simulation results using the processor; and determining a new candidate for a net if a wire and net of the same name are not logically equivalent and storing the new candidate net in the equivalence representation model stored in the memory.