Patent Document ID: 20090300323
Application ID: 12475393
Patent Flag: 0

Claim One:
1. A system comprising: a plurality of floating point execution units compatible with operation according to a plurality of execution threads; a plurality of memory channels each configured to access at least one Dynamic Randomly Accessible read/write Memory (DRAM) element; a memory buffer switch unit coupled between the floating point execution units and the memory channels; an instruction control unit configured to control the floating point execution units according to a stream of vector instructions; and a processor interface compatible with an x86 processor and configured to receive the stream of vector instructions from the x86 processor, wherein the memory buffer switch is configured to consolidate at least two memory requests from the floating point execution units into a single memory access operation directed to one of the memory channels; and wherein the at least two memory requests are processed according to a coherency domain implemented by the x86 processor where the coherency of the vector instructions with respect to the x86 processor is maintained through hardware, the coherency of the plurality of floating point execution units is maintained through software and the coherency of the x86 processor is maintained though software.