Patent Document ID: 5477474
Application ID: 07969943
Patent Flag: 1

Claim One:
1. A method for improving the performance of computer logic simulation in a computer system in which the operation of a logic design is simulated by compiling a network list representative of the logic design to obtain a simulator network list and applying predetermined input vectors to the simulator network list representative of the logic design in order to generate output vectors representative of the response of the simulator network list, said method comprising the steps of: (A) identifying one or more portions of the network list; (B) preventing the identified portions from the network list from being compiled to produce a modified network list; (C) creating one or more dynamic device models in the form of executable code to perform the simulation of one or more of the identified portions, wherein one or more of the dynamic device models can be used to more quickly simulate the compiled portion of the network it replaces, wherein said network list includes a plurality of individual networks at least some of which are coupled to operationally non-replaceable keeper nodes, further performing the substeps of: (I) identifying all keeper nodes by (a) identifying those networks to be replaced by a dynamic device model, including (i) tracing through a given network between all sources to that network and the associated keeper node; (ii) determining the total number of logic elements encountered in step (i); and (iii) selecting the network for replacement with a dynamic device model if the total number exceeds a preselected value; and (b) forming a dynamic device model corresponding to each such network identified in step (a), and (II) selectively replacing individual networks coupled to at least some of said keeper nodes with dynamic device models; (D) compiling the compilable portions of the modified network list to produce a simulator network list; and (E) using the dynamic device models and the simulator network list to perform the simulation process, thereby improving the performance of the simulation.