Patent Document ID: 7562330
Application ID: 11556837
Patent Flag: 1

Claim One:
1. A method for routing interconnections between terminals in a circuit layout comprising: specifying, by a processor, a global routing constraint on placement of routing objects between the terminals such that an interconnect solution for the terminals is obtained only by said placement satisfying said global constraint; iteratively executing, by a processor, a plurality of routing passes for respectively routing a plurality of interconnections between terminals in the circuit layout, each said routing pass including: determining whether said global routing constraint remains unsatisfied and specifying responsive to said determination a local routing constraint on placement of said routing objects to form a direct route for a direct connection between a pair of the terminals; and, placing said routing objects to form said route satisfying said local routing constraint; modifying, by a processor, said local routing constraint responsive to said determination for at least one said routing pass indicating that placed routing objects do not satisfy said global routing constraint.