Patent Document ID: 8250010
Application ID: 12470403
Patent Flag: 1

Claim One:
1. A method comprising: receiving a pre-synaptic spike in an electronic component; receiving a post-synaptic spike in said electronic component; in response to said pre-synaptic spike, generating a pre-synaptic pulse that occurs a predetermined period of time after said received pre-synaptic spike; in response to said post-synaptic spike, generating a post-synaptic pulse that starts at a baseline value and reaches a first voltage value a first period of time after said post-synaptic spike, followed by a second voltage value a second period of time after said post synaptic spike, followed by a return to said baseline voltage a third period of time after said post-synaptic spike; applying said generated pre-synaptic pulse to a pre-synaptic node of a synaptic device that includes a uni-polar, two-terminal bi-stable device in series with a rectifying element, wherein said synaptic device comprises a phase change memory (PCM), and said PCM has a set voltage, a reset voltage and a threshold voltage, and said rectifying element has a turn-on voltage, and wherein said pre-synaptic pulse has a magnitude greater than said turn-on voltage but less than the sum of said turn-on voltage and the threshold voltage; and applying said generated post-synaptic pulse to a post-synaptic node of said synaptic device, wherein said synaptic device changes from a first conductive state to a second conductive state based on the value of input voltage applied to its pre and post-synaptic nodes, wherein the resultant state of the conductance of said synaptic device after said pre- and post-synaptic pulses are applied thereto depends on the relative timing of said received pre-synaptic spike with respect to said post synaptic spike.