Patent Document ID: 7480601
Application ID: 11335021
Patent Flag: 1

Claim One:
1. An apparatus comprising: a central processing unit (CPU) an output device for displaying simulated fatigue results; an input device for receiving input; and a memory, the CPU, memory, input device and output device being connected to one another via a bus, and the memory comprising: instructions for predicting a probability of failure of a component, the instructions comprising: obtaining a Finite Element Model (FEM) of the component; analyzing said FEM to obtain stresses at nodes of said FEM; determining a Representative Volume Element (RVE) for at least one of said nodes; building a microstructure-based failure model for at least one said RVE and including the microstructure-based failure model in the RVE; simulating a component life using at least one RVE microstructure-based failure model, said simulating producing a result related to component life; performing said simulating a plurality of times to produce results related to component life; using the results to predict a probability of failure for said component; and instructions for displaying a result from said predicting.