Patent Document ID: 20050220185
Application ID: 10732408
Patent Flag: 0

Claim One:
1. For use in equalizing a transfer function of an inter-chip high-speed bus wire trace on a circuit board, wherein the inter-chip high-speed bus wire trace electrically couples an output pad of a first semiconductor chip to an input pad of a second semiconductor chip, the second semiconductor chip comprising: the input pad that couples to the inter-chip high-speed bus wire; a 1-bit sampling circuit coupled to said input pad and operative to convert an analog signal received on said input pad to a stream of 1-bit digital sample values, wherein the sampling circuit produces its stream of 1-bit digital sample values at a specified sampling rate; an equalizer that processes said stream of 1-bit digital sample values using a multiplier free adder-based circuit to produce a recovered signal symbol sequence, wherein the symbol sequence has a symbol rate that is at least two times less than said sampling rate, wherein said equalizer further comprises at least one decision feedback stage, and wherein the equalizer is characterized in that its coefficient vector substantially minimizes the l ∞ norm of a residual error function and is solved for using a linear programming optimization algorithm; and a decision circuit coupled to receive the recovered signal sequence and operative to quantize it to generate a stream of recovered symbol values.