Patent Document ID: 7483824
Application ID: 11308039
Patent Flag: 1

Claim One:
1. A self-checking test generation system comprising: a computer with one or more processors and a memory storing a program of instructions executable by the one or more processors, the program of instructions comprising a self-checking test generator comprising: a device-under-test (DUT) model of a target device, the DUT model having interconnected models for modeling interconnected blocks of the target device; a plurality of fuzzy models, each fuzzy model being a model of operation of one of the interconnected models in the DUT model; a plurality of unknown models in the DUT model, each unknown model outputting one or more model outputs in an unknown logic state; wherein a fuzzy model that receives a model output from an unknown model propagates the unknown logic state for at least some combinations of model inputs to the fuzzy model; a state storage that receives model outputs from the plurality of fuzzy models, the state storage storing state signals; an instruction writer that writes a selected instruction, operand or pointer values, and a self-check instruction to a self-check test program, the self-check test program for executing on the target device for testing the target device, whereby the self-check test program is generated using the fuzzy models.