Patent Document ID: 8291303
Application ID: 12190191
Patent Flag: 1

Claim One:
1. A memory device with an error detection and correction system formed therein, the error detection and correction system being configured to detect and correct errors in read out data by use of a BCH code, wherein the error detection and correction system is 4-bit error correctable, and searches error locations in such a way as to: calculate syndromes based on the read out data; calculate an error location searching biquadratic equation so that coefficients of the error location searching biquadratic equation correspond to the calculated syndromes; divide the error location searching biquadratic equation into two or more factor equations; convert the factor equations to have unknown parts and syndrome parts separated from each other for solving them; and compare indexes of solution candidates of the factor equations with those of the syndromes, corresponding relationships between both of the indexes being previously obtained as a table, thereby obtaining error locations.