Patent Document ID: 7769982
Application ID: 11884362
Patent Flag: 1

Claim One:
1. An apparatus for processing data under control of a program having program instructions including sequences of individual program instructions corresponding to computational subgraphs identified within said program, each computational subgraph having a number of input operands and producing one or more output operands, said apparatus comprising: an operand store operable to store the input and output operands; processing logic operable to execute individual program instructions from said program; configurable accelerator logic operable, in response to reaching an execution point within said program corresponding to a sequence of individual program instructions corresponding to a computational subgraph, to evaluate one or more output functions associated with said computational subgraph, the evaluation of each output function generating an output operand for storing in the operand store, and each output operand corresponding to an output that would have been generated had the sequence of individual program instructions corresponding to the computational subgraph have been executed by the processing logic; configuration storage operable to store a single look-up table (LUT) configuration for each output function; for each output function to be evaluated, the accelerator logic being configured dependent on the associated single LUT configuration from the configuration storage such that on receipt of the input operands of the computational subgraph, the accelerator logic will generate the output operand; wherein the sequence of individual program instructions corresponding to the computational subgraph consist of logical instructions requiring only bitwise level operations on the input operands of the instructions, and further comprise one or more arithmetic instructions requiring carry propagation operations; the configuration storage comprises, for each arithmetic instruction, a set of carry determination LUT configurations; the accelerator logic comprises, for each arithmetic instruction, carry generation logic configured by the associated set of carry determination LUT configurations to generate a carry operand from the input operands of the computational subgraph; and for each output function, the associated single LUT configuration consists of 2 n+m bits, where n is less than or equal to the number of input operands of the computational subgraph and where m is the number of arithmetic instructions within the sequence of individual program instructions corresponding to the computational subgraph.