Patent Document ID: 20080144812
Application ID: 11640918
Patent Flag: 0

Claim One:
1. A method of performing scalar multiplication which is protected against address bit attack, comprising the steps of: (1) providing an arithmetic processing unit, first, second, third and fourth registers, and first, second, third and fourth multiplexers; (2) defining point values Q[ 0 ], Q[ 1 ], Q[ 2 ] and Q[ 3 ] held in the first, second, third and fourth registers, respectively, and further defining initial point values P and 2P, (3) setting Q[ 2 ] equal to P and Q[ 3 ] equal to 2P, (4) establishing a control selection line in communication with the first and second multiplexers, and further establishing a current scalar bit value k i and feeding k i to the first multiplexer through the control selection line, and feeding 1−k i to the second multiplexer through the control selection line; (5) starting from the next most significant bit, repeating the following steps (6) through (10) until all bits of the scalar are processed; (6) performing the two following simultaneous register access operations: (i) a first simultaneous register access operation to establish the operand of a doubling operation, which is also the operand of an addition operation in the first register; (ii) a second simultaneous register access operation to establish the second operand of an addition operation in the second register; (7) storing the result of the doubling operation in the third register; (8) storing the result of the addition operation in the fourth register; (9) performing the following two simultaneous register access operations: (i) a first simultaneous register access operation to transfer the result of either the doubling operation, which is stored in the third register, or the addition operation, which is stored in the fourth register, to the first register; (ii) a second simultaneous register access operation to transfer the other register, which is either the third or fourth register, correspondingly, to the second register; and, (10) in parallel, transfer the contents of the first register to the third register and the contents of the second register to the fourth register independently from the scalar bit value.