Patent Document ID: 20160140273
Application ID: 14546065
Patent Flag: 0

Claim One:
1. An integrated circuit performance modeling system comprising: a memory storing a design layout of an integrated circuit; an integrated circuit design layout analyzer in communication with said memory, said integrated circuit design layout analyzer accessing said memory and analyzing said design layout in order to identify, within said design layout, a diffusion boundary shape of a semiconductor device, a first conductive shape on said diffusion boundary shape, any second conductive shapes connected to said first conductive shape and, for each second conductive shape identified as being connected to said first conductive shape, a corresponding interface location between said second conductive shape and said first conductive shape relative to said diffusion boundary shape; a model library storing a plurality of connectivity-based condensed resistance models for conductive shapes; a model selector in communication with said integrated circuit design layout analyzer and said model library, said model selector accessing said model library and selecting, from said model library, a specific condensed resistance model for said first conductive shape based on any corresponding interface locations between said first conductive shape and any second conductive shapes relative to said diffusion boundary shape; a netlist extractor in communication with said model selector and generating a condensed netlist for said first conductive shape based on said specific condensed resistance model; and a simulator in communication with said netlist extractor and simulating a performance of said integrated circuit using said condensed netlist for said first conductive shape.