Patent Document ID: 8818786
Application ID: 14049128
Patent Flag: 1

Claim One:
1. A method comprising: providing a system graph of an electronic circuit; identifying each branch of the system graph as at least one of a tree branch or a link, wherein the tree branches form a tree of the system graph; partitioning the tree into at least a first subtree and a second subtree; forming the first subtree by repeatedly adding branches of the tree to the first subtree; forming the second subtree by repeatedly adding branches of the tree to the second subtree, wherein the branches added to the second subtree have not been not assigned to the first subtree; identifying a first link of the system graph as a first global link when the first link forms a path from a branch of the first subtree to a branch of the second subtree; using at least one processor, calculating a solution to the first subtree independently of the second subtree, while ignoring the first global link; using at least one processor, calculating a solution to the second subtree independently of the first subtree, while ignoring the first global link; and after the calculating a solution to the first subtree and the calculating a solution to the second subtree, using the solution to the first subtree, the solution to the second subtree, and the first global link to calculate a solution for a tree branch comprising the first and second subtrees.