Patent Document ID: 9378021
Application ID: 14181032
Patent Flag: 1

Claim One:
1. A processor, comprising: a cache; a prefetcher module to select information according to a prefetcher algorithm and to send the selected information to a destination module; and a prefetcher algorithm selection module, including: a first logic to select a first candidate prefetcher algorithm; a second logic to determine and store memory addresses of predicted memory accesses of the first candidate prefetcher algorithm when performed by the prefetcher module; a third logic to determine cache lines accessed during execution of one or more memory operations; a fourth logic to evaluate whether any of the determined cache lines match any of the stored memory addresses of predicted memory accesses of the first candidate prefetcher algorithm; a fifth logic to, based upon whether determined cache lines match stored memory addresses, adjust an accuracy ratio of the first candidate prefetcher algorithm; a sixth logic to compare the accuracy ratio of the first candidate prefetcher algorithm with a threshold accuracy ratio; and a seventh logic to determine whether to apply the first candidate prefetcher algorithm to the prefetcher module based upon the comparison of the accuracy ratio with the threshold accuracy ratio.