Patent Document ID: 9659115
Application ID: 14133840
Patent Flag: 1

Claim One:
1. A method for analyzing a tiered semiconductor structure, comprising: defining one or more segments for a tiered semiconductor structure, the one or more segments comprising a first segment; determining a set of thermal properties for the first segment; performing electrical analysis on the first segment based upon an initial temperature and a time period to obtain a first power metric; determining a new temperature for the first segment based upon the first power metric and the set of thermal properties; utilizing the new temperature to determine a thermal analysis characteristic for the first segment, the thermal analysis characteristic identifying a potential reliability issue associated with the first segment; and responsive to the new temperature exceeding a temperature threshold, inserting one or more thermal release structures into the first segment to reduce a temperature of the first segment to mitigate the potential reliability issue, wherein at least one of the defining, the determining a set of thermal properties, the performing, the determining a new temperature, the utilizing, or the inserting is performed at least in part by a processing unit.