Patent Document ID: 9165103
Application ID: 14318507
Patent Flag: 1

Claim One:
1. A computer implemented method for tessellating and labeling routing space for routing electronic designs, comprising: using a computing system having at least one processor or at least one processor core to perform a process, the process comprising: creating, at a tessellation mechanism including or functioning in tandem with the at least one processor, routing grids that define multiple tessellated regions for at least a portion of a layer of an electronic design; determining, at a region labeling mechanism coupled with the tessellation mechanism, a tentative track pattern label by identifying the tentative track pattern label from multiple track pattern labels for at least one tessellated region of the multiple tessellated regions based in part or in whole upon one or more criteria, wherein the tentative track pattern label indicates which track pattern comprising an arrangement of tracks in a permissible order is to be used for physical implementation of the at least one tessellated region; and performing, at one or more routing mechanisms including or function in tandem with the at least one processor and coupled with the region labeling mechanism, routing for the portion of the layer by referencing the tentative track pattern label for the at least one tessellated region to interconnect circuit component designs in the layer of the electronic design.