Patent Document ID: 20090288059
Application ID: 12429772
Patent Flag: 0

Claim One:
1. A computer-executable program product for designing asynchronous circuits, the program product comprising a computer-readable storage medium with resident computer-readable instructions, which when loaded in a computer system causes the computer system to: (A) receive as an input a synchronous netlist corresponding to a synchronous circuit; (B) create a model of an asynchronous circuit corresponding to the synchronous circuit, wherein the model includes a directed graph, wherein in the directed graph edges represent channels and nodes represent communication processes where each edge has a weight associated with the latency of a node computation and a channel communication such that the maximum delay of any cycle represents (i) the algorithmic cycle time of the circuit, (ii) a lower bound on the throughput of the circuit, and (iii) the maximum delay from inputs to outputs represents the latency of the circuit; and (C) produce as an output an asynchronous netlist of an asynchronous circuit corresponding to the synchronous circuit.