Patent Document ID: 20140064269
Application ID: 13777725
Patent Flag: 0

Claim One:
1. A system, comprising: a memory to store computer-executable components; and a processor, coupled to the memory, that executes or facilitates execution of at least one of the computer-executable components, the computer-executable components comprising: a switch component that comprises multiple stages of switches and intermediate-stage shared buffering of packets of information to facilitate communication of the packets in a communication network, wherein the switch component comprises an input component comprising a plurality of switches associated with an input stage of the multiple stages, an intermediate component comprising a plurality of switches associated with an intermediate stage of the multiple stages, and an output component comprising a plurality of switches associated with an output stage of the multiple stages; and a memory component that comprises a plurality of memory sub-components and is associated with the intermediate component of the intermediate stage, wherein memory sub-components of the plurality of memory sub-components are shared with the plurality of switches of the input component and the plurality of switches of the output component to facilitate buffering of the packets via the intermediate-stage shared buffering and scheduling of the packets for output from the switch component.