Patent Document ID: 7913066
Application ID: 12045243
Patent Flag: 1

Claim One:
1. A circuit arrangement implemented in at least one integrated circuit device, comprising: a vector register file including a plurality of vector registers; a vector floating point execution unit including a multi-stage vector floating point execution pipeline; an issue unit coupled to the vector floating point execution unit and configured to issue instructions associated with an iterative refinement algorithm to the vector floating point execution unit, wherein the instructions associated with the iterative refinement algorithm include a floating point instruction having a read after write dependency relative to another instruction and configured to write back to the vector register file; dependency logic coupled to the issue unit and configured to selectively stall issuance of instructions having read after write dependencies by the issue unit; programmable early exit detection logic configured to detect an early exit condition during execution of the iterative refinement algorithm by the vector floating point execution unit by comparing an exponent associated with an intermediate error value for the iterative refinement algorithm against a programmable threshold, wherein the programmable early exit detection logic is further configured to set the programmable threshold responsive to decode of an instruction associated with the iterative refinement algorithm; and early exit logic configured to, in response to detection of the early exit condition by the early exit detection logic prior to completing the iterative refinement algorithm, disable write backs to the register file and stalls of subsequent instructions having read after write dependencies by the dependency logic until completion of execution of the iterative refinement algorithm.