Patent Document ID: 5459798
Application ID: 08060579
Patent Flag: 1

Claim One:
1. An apparatus for performing pattern recognition procedures regarding an unknown pattern, said apparatus for interfacing to a computer system having a computer system bus, said apparatus comprising: programmable multiprocessing means for executing pattern recognition instructions, each pattern recognition instruction comprising arithmetic, pointer and control operations which are executed in parallel, wherein said programmable multiprocessing means further comprises: (i) two arithmetic pipelines for executing two arithmetic instructions in parallel, a first arithmetic pipeline optimized for performing distance computations between segments of said unknown pattern and segments of reference patterns and a second arithmetic pipeline optimized for performing best path computations in response to previously computed distance computations; (ii) two pointer pipelines for executing two pointer instructions in parallel, a first pointer pipeline for supplying pointer information for said first arithmetic pipeline and a second pointer pipeline for supplying pointer information for said second arithmetic pipeline; and (iii) a control pipeline for providing instruction flow control for said pattern recognition procedures; internal memory means for providing storage for temporary results of said pattern recognition instructions and for providing temporary storage for said unknown pattern and selected reference patterns; and external memory means for providing storage for a library of said reference patterns, said external memory means communicatively coupled to said internal memory means via a private and dedicated communication bus separate from said computer system bus.