Patent Document ID: 5424964
Application ID: 08046532
Patent Flag: 1

Claim One:
1. A method for designing a transistor on a computer modeling system, wherein a plurality of modeling parameters raze associated with various operating points of said transistor and certain ones of said plurality of modeling parameters having constraints associated with said certain ones of said plurality of parameters, said method comprising: measuring values of operating variables associated with various operating points of a transistor to be modeled using a transistor testing system; calculating initial values of said operating variables at the various operating points using an initial set of modeling parameters such that for each of the operating points there is a measured value and an initial calculated value; storing said initial calculated values and said measured values in a computer memory; calculating an initial objective function as a measure of the error between said calculated values and said measured values; calculating a next set of modeling parameters from said objective function; determining if any particular parameter within said next set of modeling parameters violates a constraint associated with the particular parameter; calculating a new next set of modeling parameters, responsive to said step of determining, wherein any particular parameter which violates the constraint associated with said parameter is ignored in said calculating of said new next set of modeling parameters; reiterating said calculating a new next set of modeling parameters until a final set of modeling parameters is found to be within said constraints; and designing a circuit comprising circuit transistors having similar operational characteristics as said transistor to be modeled using a circuit design system operable to use said final set of modeling parameters.