Patent Document ID: 8490042
Application ID: 12608434
Patent Flag: 1

Claim One:
1. A method for concurrently optimizing multiple routing objectives during routing of an integrated circuit (IC) chip design, the method comprising: receiving a routing solution for the IC chip design and a set of routing objectives; partitioning the IC chip design into a set of partitions; and optimizing, by a computer, the routing solution by concurrently processing each partition in the set of partitions, wherein for each partition in the set of partitions, said processing involves performing an iterative process comprising: analyzing the routing solution within the partition to determine a set of weights for the set of routing objectives for the partition; constructing a cost function based on the set of weights for the set of routing objectives for the partition; if the cost function is not optimal, modifying the routing solution within the partition; and wherein said iterative process repeats said analyzing, said constructing, and said modifying to attempt to optimize the cost function.