Patent Document ID: 4326135
Application ID: 06125409
Patent Flag: 1

Claim One:
1. A differential input to single-ended output converter fabricated as an integrated circuit comprising: (a) first and second transistors each having emitter, base and collector electrodes, the emitter electrodes of the first and second transistors being coupled to each other, the base electrodes of the first and second transistors being coupled to first and second input terminals, respectively, for receiving a differential input signal; (b) a first current source connected between a power supply conductor and the emitter electrodes of the first and second transistors for supplying a current of a first magnitude; (c) a first inverted transistor having emitter, base, and first and second collector electrodes, the emitter electrode being coupled to a reference conductor, the base and first collector electrodes being coupled to the collector electrode of the first transistor, and the second collector electrode being coupled to the collector electrode of the second transistor; (d) a second inverted transistor having emitter and base electrodes, and having N collector electrodes where N is an integer greater than 1, the emitter electrode being coupled to the reference conductor, and the base electrode being coupled to the second collector electrode of the first inverted transistor; (e) a source of injection current being connected between each of said N collector electrodes of the second inverted transistor and the power supply conductor and having a second magnitude which is 1/N times said first magnitude such that offset error associated with the differential input to single-ended output converter is substantially zero; and (f) integrated injection logic means for performing a switching function including an inverted switching transistor, the inverted switching transistor having emitter and base electrodes and having a plurality of collector electrodes, the emitter electrode being coupled to the reference conductor and the base electrode being coupled to at least one of said N collector electrodes of the second inverted transistor.