Patent Document ID: 6028989
Application ID: 09059220
Patent Flag: 1

Claim One:
1. A program method for calculating crosstalk voltage and modeling for a planned chip design, comprising the steps of running in a first process a program for routing and crosstalk routines for routing exact topologies/paths of the victim and perpetrator nets of the planned chip design and for creating crosstalk rules for the planned chip design and in which program if said crosstalk rules are loaded before wire routing has been completed, the routing program will attempt to obey said crosstalk rules and avoid crosstalk and cause a crosstalk report to be generated; loading crosstalk rules into said program for routing and crosstalk routines after routing is completed for network analysis, whereby action of said program causes a crosstalk report to be generated at that time; and in a second process calculating a noise voltage of the planned chip design based on said exact topologies/paths of the victim and perpetrator nets of the planned chip design by path tracing and outputting a polish program file which contains the calculated noise voltage and a complete tabulation of key physical and electrical parameters the victim and perpetrator nets of the planned design, and then in a third process, modeling using a network analysis topology simulation modeling program for selected nets on selected nets of the planned chip design which exceed allowed noise limitations and obtaining the planned chip design net's network topology as an output while using said polish program file as an input to the network analysis topology circuit simulation modeling program and outputting the nodal voltages vs. time at each receiver location on a victim net as well as key nodes on any perpetrator nets of said planned chip design.