Patent Document ID: 8566529
Application ID: 12030501
Patent Flag: 1

Claim One:
1. A method for cache and memory performance analysis and modeling, the method comprising: receiving a cache-line set associative parameter input value; receiving input values in regard to a number of least recently used (LRU) tree levels that are to be analyzed; receiving input values in regard to a number of LRU-analysis groups per LRU tree level into which a cache-line set is to be divided; determining whether a total of the input values for the LRU-analysis groups per LRU tree level for a cache-line set is equal to the cache-line set associative parameter input value; identifying an analysis group within a cache-line set for an LRU tree level of a plurality of tree levels, the cache line set comprises an oldest most recently used (MRU) for all but a root level of the LRU tree, the identifying of the analysis group based on the total of the input values for the LRU-analysis groups per LRU tree level for the cache-line set being equal to the cache-line set associative parameter input value; identifying a LRU set-index within a root level analysis group comprising the oldest MRU within a preceding parent LRU-tree level of the plurality of tree levels; and returning a LRU set-index for replacement that is identified by a true-LRU that is retrieved from the root level analysis group.