Patent Document ID: 8601414
Application ID: 12945020
Patent Flag: 1

Claim One:
1. A method for verifying a hardware design for an electronic circuit, comprising: providing a hardware design description for the electronic circuit; extracting a set of design constraints from the hardware design description, where the set of design constraints represents the electronic circuit in terms of signals and logical operations performed on the signals; creating an abstraction model from the set of design constraints, where the abstraction model abstracts one or more of the logical operations in the set of design constraints by replacing the abstracted logical operations with uninterpreted functions while the signals in the set of design constraints remain unabstracted in the abstraction model; and property checking the abstraction model in relation to one or more design properties, thereby yielding an assignment of variables that represent a violation of the design properties; and checking feasibility of the violation in the electronic circuit by conjoining the violation with the set of design constraints to form a conjoined set of constraints, and inputting the conjoined set of constraints into a satisfiability solver, wherein at least the steps of creating an abstraction model and property checking are executed by a computer processor.