Patent Document ID: 9824001
Application ID: 14617217
Patent Flag: 1

Claim One:
1. A processor-implemented performance test steady-state determination method, comprising: executing, via one or more hardware processors, a performance test of a web-based application; calculating, via the one or more hardware processors, a plurality of output metrics based on the performance test; calculating, via the one or more hardware processors, an overall steadiness score based on a matrix of a plurality of rows and a plurality of columns, wherein each of the plurality of rows corresponds to each of the plurality of output metrics, each of the plurality of columns corresponds to each of a plurality of time windows, and one of the plurality of columns corresponds to a priority of each of the plurality of output metrics, wherein each cell of the matrix comprises at least one of a steadiness computation value or a priority weight; and providing, via the one or more hardware processors, an overall steadiness indication based on the overall steadiness score, wherein the overall steadiness score is based on a determination of whether each of the plurality of output metrics has achieved a steady state within the plurality of time windows; and wherein, for each of the plurality of output metrics, the determination of whether the output metric has achieved the steady state within the plurality of time windows comprises: for each of the plurality of time windows: calculating an average value for the output metric within the time window; determining whether a maximum value for the output metric within the time window deviates by less than a predetermined threshold value from the average value; and determining whether a minimum value for the output metric within the time window deviates by less than a predetermined threshold values from the average value.