Patent Document ID: 20080263486
Application ID: 12122988
Patent Flag: 0

Claim One:
1. An Electronic Design Automation (EDA) tool stored on a machine readable medium storing code, which when executed by the machine, to cause generation of an apparatus, comprising: a model of an entire set of the hardware components making up an interconnect that facilitates communications between IP blocks in an integrated circuit, where the model is coded in a software programming language at a Transaction Layer 1 level (TL1) and is cycle accurate to a corresponding Register Transfer Level (RTL) description of the hardware components making up the interconnect, wherein the software programming language model of the interconnect at the Transaction Layer 1 level is made up of two or more individual models of one or more of the hardware components making up the interconnect which were simulated and verified at the same time with corresponding individual models coded in a hardware description language at RTL of those one or more hardware components making up the interconnect; and a TL1-to-TL0 adapter wrapped around each individual model of the one or more hardware components making up an interconnect coded in the software programming language at TL1 in order to provide output signals that are cycle accurate compared to the model of the one or more hardware components making up an interconnect coded in RTL.