Patent Document ID: 5475695
Application ID: 08033775
Patent Flag: 1

Claim One:
1. A method for identifying frequently occurring fabrication defects for an integrated circuit design and a fabrication process, the method comprising the steps of: (1) analyzing the integrated circuit design and the fabrication process to identify a plurality of electrical faults that can be caused by fabrication defects; (2) analyzing the integrated circuit design to determine a plurality of electrical responses to a plurality of input patterns, the electrical responses corresponding to the electrical faults; (3) generating a response matrix relating the electrical responses to the input patterns as a function of the fabrication defects; (4) generating a set of test vectors using the response matrix and parameters of a specific integrated circuit test system; (5) applying the test vectors to an integrated circuit having the integrated circuit design; (6) recording responses of the integrated circuit to the test vectors; (7) analyzing the responses of the integrated circuit to the test vectors using the response matrix to identify particular fabrication defects; (8) repeating steps (5) through (7) for other integrated circuits having the integrated circuit design; (9) storing failure information related to the particular fabrication defects identified in steps (1) through (8) in a data base; (10) generating statistical failure information using the failure information; and (11) identifying frequently occurring fabrication defects from among the particular fabrication defects using the statistical failure information, the frequently occurring fabrication defects having a frequency above a threshold level.