Patent Document ID: 4145733
Application ID: 05721083
Patent Flag: 1

Claim One:
1. A digital data processor comprising: (a) active memory means for holding at least a record of active instructions, said active memory means containing a plurality of cells, each cell holding one instruction of said record of active instructions and each cell having a unique index; (b) operation means for managing signals in the execution of arithmetic and logical operations on signals representing data values; (c) decision means for managing signals in the execution of comparison and testing operations on signals representing data values; (d) control identity means for managing signals in the execution of identity operations on signals representing control values; (e) first arbitration means operatively connected between said active memory means and said operation means and between said active memory means and said decision means for concurrently transmitting signals representing a plurality of first information packets from said active memory means to said operation means and said decision means, each of said signals representing first information packets consisting of signals representing an instruction of said record of active instructions together with data values required for its execution; (f) second arbitration means operatively connected between said active memory means and said control identity means for concurrently transmitting signals representing a plurality of second information packets from said active memory means to said control identity means, each of said signals representing second information packets consisting of signals representing control values necessary to insure correct operation of said digital data processor; (g) first control means operatively connected between said decision means and said active memory means for concurrently transmitting signals representing a plurality of third information packets from said decision means to said active memory means, each of said signals representing third information packets consisting of signals representing Boolean values computed by said decision means and required for the execution of said record of active instructions contained in said cells of said active memory means; (h) second control means operatively connected between said control identity means and said active memory means for concurrently transmitting signals representing a plurality of fourth information packets from said control identity means to said active memory means, said signals representing fourth information packets consisting of signals representing control values necessary to insure correct operation of said digital data processor; and (i) distribution means operatively connected between said operation means and said active memory means for concurrently transmitting signals representing a plurality of fifth information packets from said operation means to said active memory means, said signals representing fifth information packets consisting of signals representing data values computed by said operation means and required for execution of said record of active instructions contained in said active memory means.