Patent Document ID: 5426721
Application ID: 08080490
Patent Flag: 1

Claim One:
1. A circuit for mapping an n-bit binary input sequence into an m-bit binary output sequence, wherein n is a positive integer and m is a positive integer, said circuit comprising n input neurons, each said input neuron adapted to receive one bit of the n-bit binary input sequence; a plurality of hidden neurons, each of said hidden neurons having a threshold value; and m output neurons, each said output neuron adapted to output one bit of the m-bit binary output sequence; wherein said input neurons, said hidden neurons, and said output neurons comprise a plurality of neural networks, wherein each of said output neurons is associated with one of said neural networks, and wherein each of said neural networks comprises: (a) said output neuron associated with said neural network; (b) at least one of said hidden neurons; (c) at least one of said input neurons; (d) means, associated with each of said input neurons in said neural network, for distributing an input bit received by that neuron to at least one of said hidden neurons in said neural network; (e) means, associated with each of said hidden neurons in said neural network, for receiving an input bit distributed from at least one of said input neurons in said neural network; (f) means, associated with at least one of said hidden neurons in said neural network, for weighting at least one bit received by that hidden neuron; (g) means, associated with each of said hidden neurons in said neural network, for sending a high signal to the output neuron of said neural network if, and only if, the arithmetic sum of the arithmetic products of each bit received by that hidden neuron multiplied by the weight given to that bit by said weighting means for that bit, or multiplied by zero if there be no said weighting means for that bit, exceeds the threshold value for that hidden neuron, and for outputting a low signal to the output neuron of said neural network otherwise; (h) means, associated with said output neuron of said neural network, for weighting each high signal received by that output neuron equally with a fixed weight; and (i) means, associated with said output neuron of said neural network, for outputting a high signal if said output neuron is sent a high signal by at least one of said hidden neurons of said neural network, and for outputting a low signal otherwise; wherein for each of a plurality of said hidden neurons in said circuit, if the said hidden neuron is a component of one of said neural networks comprising one of said output neurons, then the said hidden neuron is not a component of any of said neural networks which comprises any other of said output neurons.