Patent Document ID: 20120239178
Application ID: 13048282
Patent Flag: 0

Claim One:
1. A method comprising: (a) computing respective regression models for each of a plurality of failure bins based on a plurality of failures identified during wafer electrical tests, each regression model outputting a wafer yield measure as a function of a plurality of device performance variables; (b) for each failure bin, determining sensitivity of the wafer yield measure to each of the plurality of device performance variables, and ranking the device performance variables with respect to sensitivity of the wafer yield measure; (c) selecting a subset of the device performance variables which have highest rankings and which have less than a threshold correlation with each other; (d) combining the wafer yield measures for each failure bin corresponding to one of the selected subset of device performance variables, to provide a combined wafer yield measure; (e) selecting at least one new process parameter value to effect a change in the one device performance variable, based on the combined wafer yield measure, the at least one new process parameter value to be used to process at least one additional wafer.