Patent Document ID: 9087002
Application ID: 13512046
Patent Flag: 1

Claim One:
1. An addition/subtraction hardware operator, comprising: a plurality of no more than three addition/subtraction hardware modules; and a plurality of transmission links between the modules, on one hand, and between inputs and outputs of the operator and the modules, on the other hand, according to a pre-determined structure for performing arithmetical calculations, wherein at least a part of the addition/subtraction hardware modules and at least a part of the links between the modules can be configured by at least one programmable parameter, at least between a first configuration in which the operator finalizes a computation of real parts of fast Fourier transform coefficients, a second configuration in which the operator finalizes a computation of imaginary parts of fast Fourier transform coefficients, a third configuration in which the operator carries out a computation of path metrics and survivors values of a Viterbi algorithm implementation, a fourth configuration in which the operator carries out several independent addition and/or subtraction operations, or a fifth configuration in which the operator finalizes a cascade of three sequential addition and/or subtraction operations, and wherein the addition/subtraction hardware operator further comprises: a first addition/subtraction hardware module that is configurable by means of a first binary parameter between an adder configuration and a subtractor configuration; a second addition/subtraction hardware module that is configurable by means of a second binary parameter between an adder configuration and a subtractor configuration; a third addition/subtraction hardware module that is configurable by means of a third binary parameter between an adder configuration and a subtractor configuration; first link for furnishing an operand value to the first configurable module, through a first multiplexing parameter, between a configuration for providing input data of the operator and a configuration for providing the output of the second configurable module; a second link for furnishing a first operand value to the second configurable module, through a second multiplexing parameter, between a configuration for providing input data of the operator and a configuration for providing the output of the first configurable module; a third link for furnishing a second operand value to the second configurable module, through a third multiplexing parameter, between a configuration for providing input data of the operator and a configuration for providing the output of the third configurable module; and a fourth link for furnishing an operand value to the third configurable module, through a fourth multiplexing parameter, between a configuration for providing input data of the operator and a configuration for providing the output of the second configurable module, wherein each configurable link contains a dual input multiplexer with a single output and with a selection of one of the two inputs using a binary parameter, such that the addition/subtraction hardware operator includes no more than four dual input multiplexers and the three addition/subtraction modules for causing the addition/subtraction hardware operator to be configured between the first, second, third, fourth, or fifth configurations.