Patent Document ID: 10108538
Application ID: 15664842
Patent Flag: 1

Claim One:
1. An apparatus for increasing a speed at which a processing unit performs machine learning computations, the apparatus comprising: a plurality of address offset value elements that each comprise hardware storage circuitry configured to store an address offset value; for each address offset value element, a plurality of address computation elements that each comprise hardware storage circuitry configured to store a value used to determine the address offset value stored in the address offset value element; one or more hardware processors configured to: receive a program for performing computations using tensor elements of an N-dimensional tensor; identify, in the program, a prologue or epilogue loop having a corresponding data array for storing values of the prologue or epilogue loop; populate, for a first address offset value element that corresponds to the prologue or epilogue loop, the address computation elements for the first address offset value element with respective values based at least on a number of iterations of the prologue or epilogue loop, the address computation elements for the first address offset elements including a first step value for the prologue or epilogue loop; populate, for a second address offset value element for each dimension of the N-dimensional tensor, the address computation elements for the second address offset value element with respective values based at least on a number of iterations of a loop in the program that corresponds to the dimension, the address computation elements for each dimension of the N-dimensional tensor including a second step value for the dimension, wherein the second step value for each dimension and the first step value for the prologue or epilogue loop are determined based on the number of elements included in each dimension of the N-dimensional tensor and the number of iterations of the prologue or epilogue loop such that each data element of the prologue or epilogue loop and each tensor element of the N-dimensional tensor is assigned a unique memory address; determine, for each data element of each data array, a memory address for the data element using a current value of the first address offset value for the data array at a time at which the memory address for the data element is determined, wherein the first address offset value for the data array is adjusted using the first step value for the prologue or epilogue loop after each determination of a memory address for a data element of the data array; determine, for each tensor element of the N-dimensional tensor, a memory address for the tensor element using a current value of each second address offset value at a time at which the memory address for the tensor element is determined, wherein the second address offset value for each of one or more of the dimensions of the N-dimensional tensor is adjusted using the second step value for the dimension after each determination of a memory address for a tensor element of the N-dimensional tensor; and output, to the processing unit that performs the machine learning computations, data indicating the determined memory address for each tensor element and each data element.