Patent Document ID: 9152827
Application ID: 13965459
Patent Flag: 1

Claim One:
1. An apparatus for performing matrix-vector multiplication approximation, comprising a first crossbar array of memristive devices for positive elements of a matrix; a second crossbar array of memristive devices for negative elements of a matrix; wherein said first and said second crossbar array further comprise a plurality of word lines and a like plurality of bit lines with each of said word lines having an input and each of said bit lines having an output; a subtraction amplifier having a positive input, a negative input, and an output; said subtraction amplifier being connected to each corresponding pair of bit lines from said first and said second crossbar array, said subtraction amplifier having a positive input connected to an output of a bit line from said first crossbar array and having a negative input connected to an output of a corresponding bit line from said second crossbar array; and an output in common with said output of said subtraction amplifier, wherein when an input voltage vector is applied to said word lines, an output vector is produced at said output approximately according to 
 VO=A×VI where VO represents said output voltage vector; VI represents said input voltage vector, and A represents a matrix with element values in the range of [−1.0, 1.0] being a function of the conductance of said memristive devices.