Patent Document ID: 5544311
Application ID: 08526472
Patent Flag: 1

Claim One:
1. An on-chip debug system for a programmable VLSI processor, said on-chip debug system referred to as a debug port, said debug port comprising: (a) a plurality of units, said units including (1) a debug bus unit, (2) a debug command unit, (3) a debug instruction unit, (4) a debug inject/extract unit, and (5) a program flow unit; (b) a first internal bus referred to as the internal debug bus; (c) a second internal bus referred to as the move controller bus; (d) said debug bus unit being operatively coupled (i) to receive debug information from at least one other of said plurality of units via the internal debug bus and (ii) to send debug information to at least one other of said plurality of units via the move controller bus, said debug bus unit having (1) means for sending signals to and receiving signals from an external interface module at an external interface data exchange rate, (2) means for receiving a service-request signal from at least one other of said plurality of units and for arbitrating and acknowledging said service-request signal, (3) means for storing debug information received from at least one other of said plurality of units, and (4) means for synchronizing the external interface data exchange rate and an internal debug port data exchange rate; (e) said debug command unit operatively coupled (i) to receive a debug command from at least one other of said plurality of units via the move controller bus, said debug command unit having (1) means for receiving a debug command from the VLSI processor, (2) means for selecting and decoding a debug command, (3) a status latch register for selectively latching one or more status signals received from at least one of said plurality of units, (4) means for sending said one or more selectively latched status signals to at least one of said plurality of units, (5) an enable latch register for selectively latching one or more enable signals received from at least one of said plurality of units, (6) means for sending said one or more selectively latched enable signals to at least one other of said plurality of units, (7) a timer, (8) means for sending timer information to the VLSI processor, (9) means for sending timer information to at least one other of said plurality of units via the internal debug bus, (10) means for sending debug information to at least one other of said plurality of units via the internal debug bus, (11) means for sending a service-request signal to the debug bus unit, and (12) means for receiving a service-request acknowledgment signal from the debug bus unit; (f) said debug instruction unit being operatively coupled (i) to receive debug information from at least one other of said plurality of units via the move controller bus and (ii) to send debug information to at least one other of said plurality of units via the internal debug bus, said debug instruction unit having (1) means for sending a VLSI instruction to a first register internal to the VLSI processor, (2) means for sending VLSI data associated with said VLSI instruction to a second register internal to the VLSI processor, (3) means for receiving data from one or more registers internal to said VLSI processor, (4) means for sending a service-request signal to the debug bus unit, and (5) means for receiving a service-request acknowledgment signal from the debug bus unit; (g) said debug inject/extract unit being operatively coupled to (i) receive debug information from at least one other of said plurality of units via the move controller bus and (ii) send debug information to at least one other of said plurality of units via the internal debug bus, said debug inject/extract unit having (1) means for sending data to a register internal to the VLSI processor, (2) means for receiving data from a register internal to the VLSI processor, (3) means for sending a service-request signal to the debug bus unit, and (4) means for receiving a service-request acknowledgment signal from the debug bus unit; and (h) said program flow unit configured to monitor a task being executed by the VLSI processor, said task having a branch execution behavior, said program flow unit being operatively coupled to send debug information to at least one other of said plurality of units via the internal debug bus, said program flow unit having (1) means for monitoring said branch execution behavior, (2) means for reporting said branch execution behavior to the debug bus unit, (3) means for sending a service-request signal to the debug bus unit, and (4) means for receiving a service-request acknowledgment signal from the debug bus unit.