Patent Document ID: 20100281448
Application ID: 12773686
Patent Flag: 0

Claim One:
1. A method of placing and routing application logic within an FPGA fabric having multiple supply voltage levels, V ddx , levels, comprising: (a) receiving a net list; (b) assigning critical circuit paths defined within said net list to high supply voltage levels within the FPGA; (c) determining timing slack on non-critical circuit paths defined in said net list; (d) determining power sensitivity of circuit non-critical circuit paths; (e) assigning circuit paths with high power sensitivity and sufficient timing slack to logic blocks operating at a low supply voltage level; (f) updating timing information; (g) reversing assignment to logic blocks operating at a low supply voltage level if delay constraints are not met; and (h) continuing, iteratively, to execute steps (e) through (g) until all circuit paths within said net list have been assigned to blocks and routes within said FPGA.