Patent Document ID: 8225244
Application ID: 12303638
Patent Flag: 1

Claim One:
1. A large scale integration (LSI) design apparatus for designing an LSI having both a normal system for performing normal functions, and a diagnosis system for communicating with a diagnosis micro-program which is executed externally to interject diagnosis data of said diagnosis micro-program into said normal system during momentary interruption of said normal system, to perform real-time detection of the occurrence of a fault of said normal system, comprising: a behavior model design device which generates first behavior level design data, in which the logic of said normal system in said LSI is described, and including a plurality of variables; a high level synthesis device which inputs said first behavior level design data, and, on the basis of said first behavior level design data, generates both first register transfer level (RTL) design data in which the logic of said normal system is described and in which a plurality of hardware registers are included, and a high level synthesis log which specifies said plurality of hardware registers within said first RTL design data; a diagnosis candidate analysis device which inputs said first behavior level design data and said high level synthesis log, and, on the basis of said first behavior level design data and said high level synthesis log, detects, from a plurality of variables within said first behavior level design data, a plurality of diagnosis candidate variables which respectively correspond to said plurality of hardware registers within said first RTL design data, and generates diagnosis candidate information in which said mutually corresponding plurality of diagnosis candidate variables and said plurality of hardware registers are specified, where said plurality of diagnosis candidate variables are useable during said momentary interruption of said normal system, to perform said real-time detection of the occurrence of a fault during said operation of said normal system; a register address setting device which inputs said diagnosis candidate information, maps said plurality of hardware registers which are specified in said diagnosis candidate information onto a software address space to be used by said diagnosis micro-program during said momentary interruption of said normal system, to perform said real-time detection of the occurrence of a fault during said operation of said normal system, and generates diagnosis address definition information which specifies the address positions of a plurality of registers in said software address space; and a diagnostic logic automatic generation device which inputs said first behavior level design data and said diagnostic address definition information, and, on the basis of said first behavior level design data and said diagnostic address definition information, generates second behavior level design data for said LSI, in which both said normal system and said diagnosis system are included; wherein said high level synthesis device further inputs said second behavior level design data, and, on the basis of said second behavior level design data, generates second RTL design data, in which is described completed logic which includes logic for said normal system, as well as diagnostic system logic to be used by said diagnosis micro-program during said momentary interruption of said normal system, to perform said real-time detection of the occurrence of a fault during said operation of said normal system; and said LSI design apparatus further comprising a logic synthesis device which inputs said second RTL design data, and, on the basis of said second RTL design data, generates gate level design data in which said completed logic is described.