Patent Document ID: 6023422
Application ID: 09163229
Patent Flag: 1

Claim One:
1. In an array of N-channel MOS transistors formed in a p-type substrate, said N-channel MOS transistors each including a drain electrode, a source electrode, a control gate and a floating gate on which electrons may be stored to establish a floating gate potential, said array arranged in rows and columns and having a unique row line associated with each row of said array and a unique column line associated with each column of said array, said source electrodes of all of said N-channel MOS transistors in a row connected to said unique row line associated with that row and said drain electrodes of all of said N-channel MOS transistors in a column are connected to said unique column line associated with said column, a method for selectively decreasing said floating gate potential of a selected one of one of said N-channel MOS transistors comprising the steps of: injecting minority electrons into said substrate; applying a positive potential of at least 3.2 volts to the one of said row lines and the one of said column lines associated with said selected one of said N-channel MOS transistors while simultaneously maintaining all other ones of said row and column lines at voltages less than less than about 1.5 volts.