Patent Document ID: 20020162094
Application ID: 10103349
Patent Flag: 0

Claim One:
1. A method of emulation or functional testing of a first microprocessor ( 34 ) in its functional environment including one or several peripherals ( 32, 342 ) and at least one internal bus ( 36 ) of communication between this first microprocessor and its peripherals, from a second microprocessor ( 10 ), consisting of: deactivating the first microprocessor; using the communication bus(es) ( 36 ) to communicate between the two microprocessors and the peripheral(s); and activating the second microprocessor; wherein the first microprocessor ( 34 ) communicates with the second microprocessor ( 10 ) over a series link ( 2 ), and wherein the second microprocessor ( 10 ) is realized by a simulation model.