Patent Document ID: 20110085662
Application ID: 12903782
Patent Flag: 0

Claim One:
1. A logistic map circuit comprising: a collection of j logistic map circuits, where for each logistic map circuit r (r=1 to j) comprising: a first MOSFET device with a p-channel type configuration with a gate coupled to an r th input voltage (Vinr), a source coupled to a first current source (I 1 r ) to establish a first MOSFET source current; a second MOSFET device with an n-channel type configuration with a gate coupled to the voltage source (Vinr), a drain coupled to a second current source (I 2 r ), to establish a second MOSFET drain current; and a common summing point for the first MOSFET source current and the second MOSFET drain current, the summing point formed as a current mirror with a common gate coupled to a drain of the first MOSFET device and a source of the second MOSFET device, where the current mirror produces a summed non-linear output current Io = ∑ r = 1 j Kr ( Vinr - V T ) 2 that corresponds to one of a plurality of different logic gates responsive to adjusting input voltage (Vinr), where Kr is a conductivity constant attribute of at least one of the first MOSFET device and the second MOSFET device and V T is a threshold voltage attribute of at least one of the first MOSFET device and the second MOSFET device, and the first MOSFET source current and the second MOSFET drain current limit a value of output current (Io), where Vinr is the input voltage Kr is a MOSFET device conductivity constant and V T is a MOSFET device threshold voltage.