Patent Document ID: 20070150843
Application ID: 11315695
Patent Flag: 0

Claim One:
1. A method for generating an input vector to reduce the leakage current in an integrated circuit by using heuristics, said method comprising the steps of: transforming said integrated circuit into a logic representation with PMOS and NMOS parts, and P and N devices of said integrated circuit into edges; selecting between said PMOS and said NMOS logic representations the one with deepest serial stack; and for said selected PMOS or NMOS logic representation, assigning weights to said edges in said selected PMOS or NMOS logic representation, thereby generating a weighted graph, the weight assignment starting from the output terminal in said PMOS or NMOS logic representation to the Power V dd or Ground V ss in said PMOS or NMOS logic representation, and weight assigned to each said edge being in a non-increasing order.