Patent Document ID: 20150347640
Application ID: 14288794
Patent Flag: 0

Claim One:
1. A method of performing physical aware technology mapping in a logic synthesis phase of design of an integrated circuit, the method comprising: subdividing a core area representing a sub-block of the integrated circuit into equal-sized grids, the core area including one or more input ports and one or more output ports; determining, using a processor, a location of each of one or more latches in a logic design based on an algorithm; determining, using the processor, a location of each of one or more combinational logic gates in the logic design based on the locations of the one or more latches, the one or more input ports, or the one or more output ports; and obtaining the technology mapping based on the locations of the one or more latches, the locations of the one or more combinational logic gates, and associated path delays.