Patent Document ID: 7653673
Application ID: 11184118
Patent Flag: 1

Claim One:
1. A method of finding the largest ‘k’ clock delay values from ‘n’ clock delay values, the method comprising: providing an input set of ‘n’ clock skew delay from clock paths of a digital integrated circuit design; using a sort algorithm to sort the input set of ‘n’ clock delay values to generate a sorted list of clock delay values X={x 1 , x 2 ,. .. , x n }, where x 1 <x 2 <. .. x n ; from the sorted list of clock delay values X, creating an optimal solution space Y by selecting the k(k+1)/2 clock delay values, where k is the number of largest clock delay values and Y={x n −x i , i=1, 2,. .. k; x n−1 −x i−1 ; x n−2 −x i−2 ;. .. ; x n−(i−1) −x 1 }; and using a partial sort algorithm to sort the optimal solution space Y to identify the ‘k’ largest clock delay values.