Patent Document ID: 4464726
Application ID: 06300219
Patent Flag: 1

Claim One:
1. A charge domain parallel processing network, comprising: A. a charge coupled device (CCD) comprisng a single multi-stage tapped delay line including means for establishing a succession of charge packets therein in response to a succession of applied input signals, means for shifting said charge packets from stage-to-stage along said delay line, and a plurality of floating gate sensing electrodes, each of said electrodes overlying one of said stages and being adapted to provide a potential thereon representative of the magnitude of a charge packet currently within its underlying stage, B. a plurality of charge domain digital-analog multipliers, each of said multipliers including means for generating a charge packet therein having a magnitude proportional to the product of a potential applied to an analog input port and a digital signal, and C. means for coupling said sensing electrodes to the analog input ports of associated ones of said digital-analog multipliers.