Patent Document ID: 20010025367
Application ID: 09781421
Patent Flag: 0

Claim One:
1. A semiconductor modeling method comprising: a first step of storing data on an SiO 2 layer; a second step of storing data on an Si layer formed so as to be in contact with the SiO 2 layer; a third step of dividing the Si layer into a plurality of regions, and setting an amount of impurity contained in the respective regions; a fourth step of setting an inter-regional migration amount of the impurity contained in the respective regions for a unit of time; a fifth step of constituting an impurity pileup part in the vicinity of an interface between the SiO 2 layer and the Si layer; and a sixth step of calculating impurity distribution in the respective regions for every unit of time after completion of the first, second, third, fourth and fifth steps.