Patent Document ID: 20120036491
Application ID: 12849973
Patent Flag: 0

Claim One:
1. A bus-interconnectivity aware method for assigning macro-block pins in a hierarchical integrated circuit (IC) floorplan comprising: a) using a computer, accessing information related to the floorplan of said IC chip; b) grouping macro-block pins into buses based on connectivity; c) formulating a constraint programming (CP) model for macro-block pin-assignment corresponding to said floorplan, and optimizing said formulation by solving said CP model; d) minimizing length of interconnects linking said macro-blocks; e) placing said macro-block pins at a periphery of selected macro-blocks maintaining bus-ordering and pin-spacing constraints of all nets forming said floorplan; and f) reducing wire crossing by computing said macro-pins relative order within each bus-pin group.