Patent Document ID: 8661305
Application ID: 13179536
Patent Flag: 1

Claim One:
1. A method for generating test vectors, the method comprises: obtaining a plurality of configuration parameters associated with a plurality of integrated circuit chips; generating an Executable Verification Plan (EVP) pertaining to the plurality of configuration parameters associated with the plurality of integrated circuit chips in one or more execution PCs (EPs); decoding one or more data packets received from the execution PCs; creating a plurality of data structures corresponding to the plurality of configuration parameters associated with the plurality of integrated circuit chips, and wherein the plurality of data structures comprises one or more data packets, a real handle and a virtual handle; communicating the plurality of data structures created to a DCMS server, and wherein the DCMS server comprises a packet decoding module for decoding one or more data packets received from the one or more Execution PCs, and a data structure module for creating the plurality of data structures corresponding to a plurality of configuration parameters associated with the plurality of integrated chips; mapping a plurality of data structures of the one or more Execution PCs with the plurality of data structures present in a database of the DCMS server, and wherein the database is adapted to store one or more branch numbers created for each of the one or more Execution PCs; customizing the executable verification plan based on changes in the plurality of configuration parameters associated with the plurality of integrated circuit chips; generating a unique set of test vectors based on a mapping of the plurality of data structures; and performing an automatic design verification of the plurality of integrated circuit chips thereby eliminating a duplication of test vector across a plurality of regressions and a duplication of test vectors across a plurality of computing machines that are different, in a single regression.