Patent Document ID: 5432476
Application ID: 08044949
Patent Flag: 1

Claim One:
1. A circuit comprising: first and second (V.sub.cc and ground).supply nodes; first and second differential input nodes for receiving first and second differential input signals (V.sub.IN+ and V.sub.IN-), respectively; an output node (N2) for providing a single-ended output signal; first and second npn transistors (Q1 and Q2) having their collectors coupled to the first supply node, and having their bases coupled to the first and second differential input nodes, respectively; first and second resistors (R1 and R5) coupled in series between the first and second supply nodes to establish a common mode voltage level at a first node (N1) between said first and second resistors; third and fourth resistors (R2 and R3) coupled between the first node and the first differential input node, and the first node and the second differential input node, respectively, to establish a common mode voltage about which the differential input signals swing; a third npn transistor (Q3) having its collector and base coupled to the emitter of the first npn transistor; a fourth npn transistor (Q4) having its collector and base coupled to the emitter of the second npn transistor; fifth and sixth resistors (R4 and R6) coupled between ground and the emitters of the third and fourth npn transistors, respectively; means (R7 and RS) for establishing a voltage reference at a reference node (N3); a fifth npn transistor (Q6) having its base coupled to the base of the third npn transistor; a sixth npn transistor (Q8) having its base coupled to the base of the fourth npn transistor; a first field effect transistor (Q5) having its source coupled to the first power terminal, its drain coupled to the collector of the fifth npn transistor, and its gate coupled to its drain; a second field effect transistor (Q7) having a its source coupled to the first power terminal, its drain coupled to the collector of the sixth npn transistor, and the ouput node and its gate coupled to the gate of the first field effect transistor; seventh and eighth resistors (R9 and R11) coupled between ground and the emitters of the fifth and sixth npn transistors, respectively; and a tenth resistor (R10) coupled between the reference node and the output node.