Patent Document ID: 4777614
Application ID: 06800691
Patent Flag: 1

Claim One:
1. A digital data processor for multiplying an input vector having multibit coefficients by a matrix having coefficients +1, -1 and 0 to provide a product vector, and wherein: (1) the processor includes an array of clock activated processing cells each associated with a respective matrix coefficient and having a row and column position in the array in accordance with the position of respective coefficient in the matrix transpose; (2) each cell is arranged to perform a two's complement arithmetic operation upon clock activation, the operation comprising: (a) receiving input of a cumulative sum bit, a vector coefficient bit and a recirculated carry bit from a prior computation, (b) generating an output carry bit and an output cumulative sum bit resulting from addition of the input sum and carry bits to the product of the vector coefficient bit with the respective cell coefficient, and (c) outputting the vector coefficient bit and the output cumulative sum bit and recirculating the output carry bit; (3) interconnection lines connect each cell to its row and column neighbours as appropriate for vector coefficient bits to propagate along rows and cumulative sum generation to be cascaded down columns; (4) clock activated data input means are arranged to input vector coefficients to respective rows bit serially, least significant bit (lsb) leading in a temporally skewed manner as appropriate for cumulative sum generation cascaded down each array column to produce respective product vector coefficients bit serially; and (5) clocking means are arranged to activate the processing cells and data input means and effect bit input to each array row and cell operation cyclically.