Patent Document ID: 7890915
Application ID: 11918760
Patent Flag: 1

Claim One:
1. A method for determining delay in static timing analysis of an integrated circuit of interest, said integrated circuit comprised of a plurality of logic cells, where said delay as determined is expressed as a parametric function, said parametric function containing statistical manufacturing process variations introduced by the process of manufacturing said logic cells of said integrated circuit, said method comprising the steps of: a) calculating, said calculating performed by means of a computational device said computational device including a CPU, a driving circuit for a first logic cell of said integrated circuit of interest, said driving circuit containing in parametric form manufacturing process variations of said integrated circuit, said calculating said driving circuit including the sub-steps of: 1. calculating a compact interconnect load for said first logic cell, said compact interconnect load containing in parametric form manufacturing process variations, wherein said calculating said compact interconnect load for said first logic cell further includes matching the statistical moment of the non-compacted interconnect load of said first logic cell where said statistical moment contains parametric form of manufacturing process variations, and wherein calculating said statistical moment includes the substeps of: evuluating, said non-compacted interconnect load of said first logic cell and calculating the corresponding moment sensitivity from the parametric sensitivity of said non-compacted interconnect load of said first logic cell by the substeps of: calculating, by applying adjoint circuit techniques said moment sensitivities, and calculating said moment sensitivities through multiple evaluations of different adjoint circuits under variant voltage and current sources; 2. calculating, using said compact interconnect load of sub-step 1, an effective capacitance with respect to said first logic cell, said effective capacitance representing a distribution of load, and where said calculation of said effective capacitance is derived by matching the current that goes through said statistical compact load in sub-step 1 with the current that goes through an effective capacitance, as described in the equations i π = β Δ ⁢ ( 1 + k τ1 · τ 1 Δ ⁢ ( ⅇ - Δ τ 1 - 1 ) + k τ2 · τ 2 Δ ⁢ ( ⅇ - Δ τ 2 - 1 ) ) ( 1 ) i ceff = c eff Δ ⁢ ( 1 + τ Δ ⁢ ( ⅇ - Δ τ - 1 ) ) ( 2 ) and further calculating the variation for said effective capacitance from application of an equilibrium equation, 
 C eff( si,π,w ) =F (π, C eff, S ( si,w,C eff), T ( si,w,C eff))  (3) where S(si,w,Ceff) is output slew, and T(si,w,Ceff) is time constant, si is input slew and w represents variational cell process parameters, said equilibrium equation containing in parametric form manufacturing process variations, said manufacturing process variations in said equilibrium equation (represented by the variable “w”) from three variation sources: the transition time of the input waveform, the intrinsic cell variations and the variations of compact load from sub-step 1, and wherein, using iterative methods, the nominal solution of said equilibrium equation is calculated and said nominal solution is defined as the operating point of said equilibrium equation where the derivative of said three variation sources is equal to zero, such that taking the derivative of said equilibrium equation with respect to said three variation sources and setting the resulting derivative equations to zero, calculates the parametric variation sensitivities of said effective capacitance; 3. calculating, using said compact interconnect load and said effective capacitance of sub-steps 1 and 2, an equivalent driving circuit of said first logic cell, wherein said equivalent driving circuit contains a voltage source connected with a resistance, and where said voltage source and said resistance are functions of said three variations sources discussed in sub-step 2, (i.e. input transition, intrinsic cell variations and compact load variations) and further said voltage source and said resistance are also functions of the statistical effective capacitance calculated in sub-step 2, and wherein variations with respect to said voltage source are calculated directly by taking the derivatives of said equivalent driving circuit with respect to said three variation sources discussed in sub-step 2, and wherein by further calculating the effective capacitance introduced variations by calculating the derivatives of said equivalent driving circuit with respect to said effective capacitance and by mapping said effective capacitance variation with respect to said three variation sources using chain rule, and calculating, (after mapping said derivatives of the effective capacitance to the derivatives of said three variation sources), the parametric variation of said equivalent driving circuit by combining the derivatives and the variations of said three variation sources; b) calculating, said calculating performed by means of said computational device, delay and transition for said driving circuit of step (a), including the substeps of: 4. calculating transfer function to fanout pins, said transfer function including in parametric form manufacturing process variations; 5. calculating, using said transfer function of substep 4, voltage waveforms at fanout pins, said voltage waveforms including in parametric form manufacturing process variations; 6. calculating, using said voltage waveforms at fanout pins from substep 5, delay and transition from said voltage waveforms; and c) repeating steps a) and b) for each logic cell comprising said integrated circuit of interest, and then outputting results, where said results map manufacturing process variations in logic cells comprising said integrated circuit of interest to performance variations of said integrated circuit of interest.