Patent Document ID: 5457410
Application ID: 08101197
Patent Flag: 1

Claim One:
1. A programmable logic circuit comprising: an input means for inputting a signal to said programmable logic circuit; a plurality of cells coupled to said input means, each of said cells capable of performing a digital function to said signal; a first set of routing lines for coupling a plurality of cells to form logical clusters of cells, wherein each output of each of said cells of each logical cluster can be programmably coupled to at least one input of each of the other cells of said logical cluster, each of said cells of said logical cluster is further programmably coupled through the first set of routing lines to at least one input of each of the other cells of other logical clusters of cells; a second set of routing lines for coupling a plurality of logical clusters to form a logical block of logical clusters of cells, wherein each input and each output of every cell of said logical block can be programmably coupled to said second set of routing lines; a first set of switches for coupling an output of one cell of a first logical cluster to an input of at least one cell of said first logical cluster by selecting one routing line of said first set of routing lines associated with said first logical cluster; a second set of switches for coupling outputs or inputs of said cells of a first logical block to said routing lines said associated second set of routing lines, wherein said second set of switches can be used to couple one routing line of said second set of routing lines to another routing line of said second set of routing lines; a third set of switches for coupling one routing line of said first set of routing lines of said first logical cluster to an adjacent routing line of said first set of routing lines of an adjacent second logical cluster; and a fourth set of switches for coupling one routine line of said second set of routing lines of said first logical block to an adjacent routing line of said second set of routing lines of an adjacent second logical block.