Patent Document ID: 5544066
Application ID: 08076729
Patent Flag: 1

Claim One:
1. In an ECAD system, a method of creating and validating a low level description of an electronic design from a higher level, behavior-oriented description thereof, comprising: entering on an ECAD system a specification of a desired behavior of an electronic design, including high-level timing goals, in a high-level, behavior-oriented language; on the ECAD system, iteratively simulating and changing the electronic design at the behavioral-level until the desired behavior is obtained; on the ECAD system, partitioning the electronic design into a number of architectural blocks and constraining the architectural choices to those which meet the high-level timing goals; on the ECAD system, directing the various architectural blocks to logic synthesis programs, said logic synthesis programs also running in the ECAD system, thereby providing a low level description of the electronic design; comparing one or more constraints on one or more respective low-level characteristics of the electronic design against one or more respective estimates of the low-level characteristics of the electronic design, as partitioned; and if any of the one or more constraints is not met, iteratively re-partitioning the electronic design, re-estimating the one or more low-level characteristics of the re-partitioned design and comparing them against the one or more respective constraints until the constraints are met.