Patent Document ID: 8122403
Application ID: 12425095
Patent Flag: 1

Claim One:
1. A method, performed by execution of instructions loaded into a computer system, of identifying trace-containment over sequential circuitry design netlists n 1 and n 2 by using constraint-based uncorrelated equivalence checking, the method comprising: obtaining, by the execution of said instructions, candidate input sets i 1 and i 2 of the netlists n 1 and n 2 ; uncorrelating, by the execution of said instructions, the input set it from the input set i 2 wherein the uncorrelating allows the input set i 1 and the input set i 1 to be independently manipulated; checking equivalence of the netlists n 1 and n 2 by the execution of said instructions to identify trace-containment; identifying, by the execution of said instructions, a mismatch between the netlists n 1 and n 2 ; and imposing, by the execution of said instructions, at least one constraint to avoid said mismatch; wherein said at least one constraint avoids said mismatch by artificially limiting a stimulus that can be applied in checking equivalence between the netlist n 1 and the netlist n 2 using uncorrelated inputs of the input sets i 1 and i 2 ; wherein the netlist n 2 is a simplified version of, or alternate implementation of, the netlist n 1 ; and wherein a relationship of equivalency of the netlists n 1 and n 2 is validated after imposing the at least one constraint to preclude said identified mismatch.