Patent Document ID: 9892649
Application ID: 14667337
Patent Flag: 1

Claim One:
1. An audio noise reduction circuit, comprising: an audio input circuit, comprising a first microphone, a second microphone and an input switching circuit, wherein the input switching circuit comprises a microphone change-over switch chip; the first microphone is connected with a first pin of the microphone change-over switch chip, the second microphone is connected with the first pin of the microphone change-over switch chip; both the first microphone and the second microphone are used to input the acquired audio signals including noise to the input switching circuit and output such audio signals from a common pin after switching processing through the microphone change-over switch chip; after being switched, the audio signals output from the common pin are output to a first output end after passing through a filter inductor L 530 ; an audio amplification buffer circuit, comprising a circuit designed to respectively perform amplification and buffer for the audio signals input by the first microphone and the second microphone, wherein the circuit designed to perform amplification and buffer for the audio signals input by the first microphone comprises capacitors C 888 , C 889 , C 890 , C 891 , C 892 and C 893 as well as an operation amplifier U 544 A and resistors R 831 , R 832 , R 833 , R 834 , R 835 and R 836 ; after the switched audio signals output from the common pin of the microphone change-over switch chip have passed through a filter inductor L 530 and a blocking capacitor C 888 , the switched audio signals are output from the first output end to 3# pin of the operation amplifier U 544 A; after having been amplified and buffered by the operation amplifier U 544 A, these audio signals are output from 1# pin of the operation amplifier U 544 A; after passing through DC blocking capacitor C 889 , these audio signals reach the output end XMIC_ 0 ; the circuit designed to perform amplification and buffer for the audio signals input by the second microphone comprise capacitors C 895 , C 896 , C 897 , C 898 and C 899 , an operation amplifier U 544 B and resistors R 838 , R 839 , R 840 , R 841 , R 842 and R 843 ; the input end MIC_ 1 is connected with the first pin of the microphone change-over switch chip through a test point TP 24 ; after passing through the DC blocking capacitor C 895 , the input end MIC_ 1 is input to 5# pin of the operation amplifier U 544 B; after being amplified and buffered by the operation amplifier U 544 B, these audio signals are output by the 7# pin of the operation amplifier U 544 B; after passing through DC blocking capacitor C 896 , these signals are output to the output end XMIC_ 1 ; an audio noise reduction processing chip, comprising a clock interface, an USB interface, an audio interface, a dual channel I2S DAC interface, a digital microphone interface and a dual channel I2S ADC interface, wherein the clock interface comprises a 12 MHz crystal input pin XTAL_I, a 12 MHz crystal output pin XTAL_O and a clock input pin D_CLK_IN; the USB interface comprises a USB_DM pin and a USB_DP pin; the audio interface comprises a common mode input signal reference pin XACREFL/XACREFR, a left channel microphone input pin XMICL, a right channel microphone input pin XMICR, a differential input pin D_MIC 1 _N of analog microphone 1 , a differential input pin D_MIC 0 _N of analog microphone 0 , a differential input pin D_MIC 1 _P of analog microphone 1 and a differential input pin D_MIC 0 _P of analog microphone 0 ; the dual channel I2S DAC interface comprises a I2S master clock pin DAC_MCLK, a I2S bit clock pin DAC_BCLK, a I2S serial data pin DAC_DOUT, a I2S left/right clock pin DAC_LRCK and a data input pin DAC_DIN; the dual channel I2S interface comprises a I2S bit clock D_I2S_BCLK, a I2S data input D_I2S_DI, a I2S left/right clock D_I2S_LRCK and a 2S serial data D_I2S_DO; the digital microphone interface comprises a digital microphone clock input pin D_DMO_CLK, a digital microphone clock out pin D_DMI_CLK, a digital microphone data input pin D_DMI_DAT, a digital microphone data output pin D_DMO_DAT; the dual channel I2S ADC interface comprises an analog-digital conversion data output pin ADC_DOUT, a I2S left/right clock pin ADC_LRCK, a I2S serial data input pin ADC_DIN, a I2S bit clock pin ADC_BCLK and a I2S master clock pin ADC_MCLK; wherein, after having been amplified and buffered by the audio amplification buffer circuit and having passed through the output end XMIC_ 0 , the audio signals of the first microphone are input to the left channel microphone input pin XMICL; after having been amplified and buffered by the audio amplification and buffer circuit and having passed through the output end XMIC_ 1 , the audio signals of the second microphone are input to the right channel microphone input pin XMICR; the audio noise reduction processing chip is used to abate the noise for the input two-way audio signals through the analog microphone and digital microphone interface array, perform blind source analysis through ICA algorithm to separate steady-state noise and non-steady state noise, perform voice extraction and separation, and output the extracted and separated voice signals through the left channel line output pin XLNOUTL and right channel line output pin XLNOUTR of the audio noise reduction processing chip; a filter circuit, comprising input ends LOUT_L_OUT, LOUT_R_OUT, filter inductors L 546 and L 547 , DC blocking capacitors C 944 and C 945 ; after noise reduction processing through the audio noise reduction processing chip, the extracted and separated voice signals pass through the left channel line output pin XLNOUTL and are output by the input end LOUT_L_OUT to the filter inductor L 546 for filtering processing, then pass through the DC blocking capacitor C 944 and then output by the LOUT_L end; after noise reduction processing by the audio noise reduction processing chip, the extracted and separated voice signals pass through the right channel line output pin XLNOUTR and are input by the input end LOUT_R_OUT to the filter inductor L 547 for filtering processing, pass through the DC blocking capacitor C 945 and then output by the LOUT_R end; and a power amplification circuit, comprising DC blocking capacitors C 875 and C 876 , a power amplification chip U 543 and filter inductors L 531 , L 533 , L 535 and L 536 ; after filtering through the filter circuit, the voice signals output by LOUT_L end pass through the DC blocking capacitor C 875 and then are output to the power amplification chip U 543 ; after having been amplified by the power amplification chip U 543 as one group, the voice signals are respectively output to the speaker through the filter inductors L 531 and L 533 .