Patent Document ID: 20130014384
Application ID: 13522419
Patent Flag: 0

Claim One:
1. A single phase inverter topology method comprising: selecting a number of desired inverter output levels m, where m≧5, is an integer and an odd number; determining a number of equal DC sources n, where n = m - 1 2 ; coupling the n DC sources in series, wherein the source series has a first DC source that defines a positive node P and a last DC source that defines a negative node N; defining one or more source series nodes between each DC source in the source series wherein the source series node after the first DC source that defines a positive node P is the first source series node and the source series node before the last DC source that defines a negative node N is the last source series node; determining a number of unidirectional controlled switches ucs; assembling one or more inverter cells, wherein an inverter cell comprises six unidirectional controlled switches and the quotient of ucs 6 determines the number of inverter cells required for the selected number of inverter output levels m; arranging four of the unidirectional controlled switches for each inverter cell as two bidirectional controlled switches; for each inverter cell, coupling two bidirectional controlled switches together forming a cell series node and coupling the other terminal of each bidirectional controlled switch to the emitter terminal of one unidirectional controlled switch forming two cell nodes; coupling the cell series node of a cell to the first source series node and coupling the collector terminals of the cell's two unidirectional controlled switches to the node P; for each remaining inverter cell, coupling the cell series node to a following source series node and coupling each unidirectional controlled switch's collector terminal to a respective cell node of a previous inverter cell; and coupling the emitter terminal for each of the two remaining unidirectional controlled switches to the node N and coupling the each collector terminal to a respective cell node of the last inverter cell.