Patent Document ID: 8386984
Application ID: 12347902
Patent Flag: 1

Claim One:
1. A method of routing an integrated circuit (IC) design, comprising: accessing the IC design including a plurality of objects; accessing a plurality of routing algorithms including an area based routing algorithm, a grid based routing algorithm, and a graph based routing algorithm; interconnecting, with a first plurality of interconnections, two or more of the plurality of objects, at least partly in response to a first combination of two or more routing algorithms of the plurality of routing algorithms; storing the first plurality of interconnections; automatically determining a second combination of two or more routing algorithms of the plurality of routing algorithms, wherein the second combination differs from the first combination; interconnecting, with a second plurality of interconnections, the two or more of the plurality of objects, at least partly in response to the second combination of one or more routing algorithms of the plurality of routing algorithms; comparing results of the first plurality of interconnections and the second plurality of interconnections; and if results of the second plurality of interconnections are worse than results of the first plurality of interconnections, restoring the first plurality of interconnections; wherein one or more of the interconnecting, the determining, and comparing are performed with a processor.