Patent Document ID: 7653519
Application ID: 11404636
Patent Flag: 1

Claim One:
1. A computer-implemented method for performing interconnect modeling for an integrated circuit design, comprising: identifying a test structure, the test structure comprising a two-dimensional test pattern which comprises at least three local interconnects and at least three distant interconnects on at least one side of the at least three local interconnects, in which the at least three local interconnects are associated with a local interconnect width value and a local interconnect spacing value and the at least three distant interconnects are associated with a distant interconnect width value and a distant interconnect spacing value, where either or both of the local interconnect width and local interconnect spacing values are respectively different from the distant interconnect width and distant interconnect spacing values; measuring electrical characteristics of one or more of the at least three local interconnects; forming an interconnect model based at least in part upon results of the act of measuring the electrical characteristics, in which the act of forming an interconnect model is performed by at least one processor, and the at least three distant interconnects represent a second set of interconnects which are not the at least three local interconnects and are used for an environment surrounding the at least three local interconnects; and displaying the electrical characteristics on a display apparatus or storing the electrical characteristics in a computer readable storage medium or a storage device.