Patent Document ID: 20100102825
Application ID: 12454476
Patent Flag: 0

Claim One:
1. A method for inserting test points and scan flip flops into a digital circuit comprising: computing a median location of the digital circuit; specifying a range within the digital circuit around the median location to be considered as test point sites; randomly selecting test point sites within the range for inserting test points; determining suitability of the randomly selected test point sites by performing a spectral analysis for scan flip-flop selection of the digital circuit using the randomly selected test point sites; determining suitability of the randomly selected test point sites by performing an entropy analysis for test point selection of the digital circuit using the randomly selected test point sites; selecting a plurality of test point sites from the randomly selected test point sites if the spectral analysis and the entropy analysis determine that the plurality of test point sites are suitable; performing primary input overlap analysis to remove as many dependent test point sites as possible from the plurality of test points site to make the digital circuit easier to test; and inserting remaining test point sites into the digital circuit.