Patent Document ID: 5450554
Application ID: 07981002
Patent Flag: 1

Claim One:
1. An apparatus for detecting whether iterations of a program loop can be processed in parallel, comprising: simulation means for simulating each iteration of the program loop comprising: a variable detector for one side for detecting variables on one side of assignment statements during each simulated iteration as the defined variables; an iteration identification means for identifying the numbers of the simulated iterations in which each defined variable is defined; and registration means for registering to the variable storage means information on each defined variable detected by the variable detector along with information on the number of the simulated iteration identified by the iteration identification means; variable storage means for storing values of variables, which are defined in program statements executed during simulation of the iterations, each value being stored with information showing both a location in the program where the value of the variable is defined and a number of the simulated iteration in which the variable is defined; and judgement means for judging that parallel processing is possible when, for each simulated iteration, variables appearing undefined in any program statements of that iteration are defined in preceding program statements within that iteration.