Patent Document ID: 5408194
Application ID: 08083905
Patent Flag: 1

Claim One:
1. A multi-channel minimum selector and subtractor circuit, including: a plurality of input nodes; a plurality of output nodes; a plurality of current sources a common conductive line; a plurality of P-Channel MOS transistors, each of said P-Channel MOS transistors having a gate connected to a different one of said input nodes, a source connected to a different one of said current sources, and a drain connected to a fixed voltage source at a potential more negative than the potential at said source of said P-Channel MOS transistor; a plurality of first switches, each of said first switches connected between said common conductive line and the source of one of a different one of said P-Channel transistors; a plurality of transconductance amplifiers, each of said transconductance amplifiers having an output connected to a different one of said output nodes, an inverting input, and a non-inverting input connected to the source of a different one of said P-Channel MOS transistors; a plurality of capacitors, each of said capacitors connected between a fixed voltage source and the inverting input of a different one of said transconductance amplifiers; a plurality of second switches, each of said second switches connected between the output and the inverting input of a different one of said transconductance amplifiers; and means for closing all of said first and second switches during a first operating phase of said minimum selector and subtractor circuit, and for opening all of said first and second switches during a second operating phase of said minimum selector and subtractor circuit.