Patent Document ID: 20050060633
Application ID: 10922205
Patent Flag: 0

Claim One:
1. A method for implementing a M-parallel Viterbi decoder by combining M trellis steps of a trellis, generated by a convolutional code encoder containing (K−1) memory elements, as a pipeline structure, comprising: (i) a M-step look-ahead add-compare-select precomputation unit, (ii) an add-compare-select recursion unit, (iii) a survivor path management circuit, and (iv) flip-flops or registers for inter-stage pipelining, wherein: the M-step look-ahead add-compare-select precomputation unit is obtained by: (a) forming an initial add-compare-select circuit which combines the branch metrics of the first K inputs, and replicating this M/K times for processing of all M parallel inputs, (b) forming a log 2 (M/W) layered intermediate add-compare-select circuit, where inputs of each add-compare-select unit are coupled to the outputs of the previous layer, and each of its outputs is coupled to an input of the add-compare-select unit of the next layer. and wherein: the inputs of the add-compare-select recursion unit are coupled to the outputs generated by the final layer of the intermediate circuit and the outputs generated by the said add-compare-select recursion unit in the past clock cycle, and wherein: the survivor path management circuit is implemented as a pipeline structure, obtained by: (c) forming a log 2 (M/K) layered survivor path circuit corresponding to the log 2 (M/K) layered intermediate add-compare-select circuit, where each input of this circuit is coupled to a parallel path select output generated by the add-compare-select units of the previous layer and is controlled by a parallel path select output generated by the add-compare-select units of the current layer, and each of its outputs is coupled to the inputs of the survivor path circuit of the next layer, and wherein the first layer inputs are the parallel path select outputs generated by the initial add-compare-select circuit, (d) a final survivor path circuit associated with the add-compare-select recursion unit, wherein its inputs are coupled to the parallel path select signals of the last layer of the log 2 (M/K) layered survivor path circuit and the control signals are coupled to the path select signals generated by the add-compare-select recursion unit.