Patent Document ID: 8954905
Application ID: 14053049
Patent Flag: 1

Claim One:
1. A method for estimating timing delays in an integrated circuit design to optimize a circuit design during synthesis, the method comprising: generating a physical wire-load model to model parasitic capacitance and parasitic resistance per unit length of a net, the physical wire-load model responsive to a physical library; estimating a net length for each of the plurality of nets in the netlist of the integrated circuit design; and calculating, with a processor, a timing delay for each of the plurality of nets in the netlist in response to the parasitic capacitance per unit length, the parasitic resistance per unit length, and the net length estimate, wherein the calculating of the timing delay for each of the plurality of nets includes indexing into a parasitic capacitance look-up table with the net length estimate to determine the parasitic capacitance of each of the plurality of nets, and indexing into a parasitic resistance look-up table with the net length estimate to determine the parasitic resistance of each of the plurality of nets; and multiplying together the parasitic capacitance and the parasitic resistance for each of the plurality of nets.