Patent Document ID: 6044214
Application ID: 09057505
Patent Flag: 1

Claim One:
1. A method for fault simulation comprising: a first step of preparing a plurality of fault circuits represented by gate models, which are equal in number to the number of internal faults, with the internal faults assumed in an entire circuit represented by said gate model; a second step of dividing each of the fault circuits represented by said gate models into a plurality of partial circuits each of which is represented by said gate model; a third step of replacing internal faults in the partial circuits represented by said gate models with external faults out of the partial circuits that are equivalent to the internal faults; a fourth step of translating the partial circuits represented by said gate models into translated partial circuits represented by superior models which have an operation speed faster than said gate models; a fifth step of simultaneously simulating circuits including circuits without internal faults and circuits having said translated partial circuits represented by said superior models that correspond to the partial circuits having the internal faults replaced with said external faults, said simulating determining whether the internal faults can be detected; and a sixth step of outputting data indicative of whether said internal faults can be detected.