Patent Document ID: 20090288050
Application ID: 11918760
Patent Flag: 0

Claim One:
1. A method for determining statistical delay in static timing analysis of integrated circuits, the method comprising the step of: a) calculating the statistical driving circuit 80 including the sub-steps of 1. calculating the statistical compact interconnect load 82 ; 2. using the results of sub-step 1, calculating the nominal effective capacitance through an equilibrium equation 84 ; and 3. using the results of sub-steps 1 and 2, calculating the statistical driving Thevenin/Norton circuit 86 ; and b) calculating the statistical delay and transition 90 including the substeps of: 4. calculating statistical transfer function to fanout pins 92 using the statistical interconnect information; 5. calculating statistical voltage waveforms at fanout pins 94 using the statistical transfer function of substep 4; and 6. calculating, using the results of step 5—the statistical voltage waveforms at the fanout pins—, the statistical delay and transition from the statistical voltage waveforms 96 the results of which determine the statistical delay useful in timing analysis of integrated circuits.