Patent Document ID: 20100058256
Application ID: 12202500
Patent Flag: 0

Claim One:
1. A method for minimizing hardware components within an embedded design having a plurality of hardware and software components, wherein each of the plurality of hardware and software components includes a plurality of component structures, the method comprising: utilizing symbolic execution to analyze the plurality of software components to define a limited set of values that the plurality of software components provide to the plurality of hardware components as constraints, the utilizing symbolic execution comprising: selecting, for each of the plurality of software components, substantially all possible paths of execution specifying a hardware component; accumulating a plurality of path conditions, wherein each of the plurality of path conditions is associated with a corresponding branch of code specifying the hardware component and comprises the conjunction of conditions over input and state variables required for the branch of code to execute; annotating each of the plurality of path conditions to the corresponding branch of code specifying the hardware component; and providing the annotated branches of code to a design synthesis tool; and employing the provided annotated branches of code to reduce the plurality of component structures of the hardware component to optimize the embedded design.