Patent Document ID: 9538928
Application ID: 14108118
Patent Flag: 1

Claim One:
1. A fully integrated neural amplifier of neural signals, comprising: (a) a first stage amplifier within a neural amplifier, said first stage amplifier configured for connection to a working electrode and a counter electrode, each said electrode connected to a direct current (DC) blocking capacitor (Cin) as input capacitor; (b) a capacitive feedback circuit within said first stage amplifier configured for setting a gain of said neural amplifier as a ratio of said input capacitor (Cin) and a feedback capacitor (Cf); and (c) a folded-cascode (FC) amplifier having an auxiliary gain stage incorporated in said first stage amplifier to increase open loop gain by using a gain booster; (d) wherein said gain booster comprises a first common-source (CS) amplifier, and a second common-source (CS) amplifier; (e) wherein said first common-source (CS) amplifier is formed by a differential pair of transistors with diode-connected load, and provides said auxiliary gain stage with additional transistors so that a first differential input is coupled to input gates of a first pair of common drain coupled transistors M 1c , M 1a , with a second differential input coupled to input gates of a second pair of common drain coupled transistors M 1b , M 1d , source connections from transistors M 1c , M 1d , are coupled to gates of following transistors in that same stage, while source connections from transistors M 1a , M 1b are output to the folded cascode stage in said second common-source (CS) amplifier in order to increase gain and reduce noise; (f) wherein the differential outputs of said first common-source (CS) amplifier are connected to gates of separate PMOS current source transistors M 4a , M 4b within said folded-cascode (FC) amplifier, which are used as the second common-source (CS) amplifier; (g) wherein said second common-source (CS) amplifier is embedded into a folded branch of said folded-cascode (FC) amplifier in order to minimize current consumption; (h) wherein said differential pair of transistors of said first common-source (CS) amplifier shares a same source with a differential pair of transistors of said auxiliary gain stage, but said auxiliary gain stage drains current with a different ratio than in said first common-source (CS) amplifier; and (i) wherein outputs from said auxiliary gain stage are coupled to said second common source amplifier at a complementary input stage providing it with increased pate-source voltage which increases transconductance.