Patent Document ID: 5493723
Application ID: 08330222
Patent Flag: 1

Claim One:
1. A processor emulation system for testing processor operation, said system comprising: first and second processors, each of the processors including a program counter which contains a program counter value comprising a plurality of program counter bits which represent an instruction address which corresponds to a processor instruction currently being executed by the processors, with each of said processors further including (a) a multiplicity of processor terminals which function to provide an interface for signals exchanged between the processor and an environment external to the processor, with the processor terminals including a first group of terminals to exclusively output signals from the processor, a second group of terminals which function exclusively to input signals to the processor and a third group of terminals which function to both input signals to the processor and output signals from the processor; (b) select means for selectively parallel coupling either a first group of processor signals to predetermined ones of the first group of processor terminals or a second group of processor signals to the same predetermined ones of the first group of processor terminals in response to a mode control signal, with the second group of processor signals representing at least a majority of the program counter bits; wherein the mode control signal can be used to produce the at least a majority of program counter bits at the same predetermined ones of the first group of processor terminals when the processor operating in an in-system emulation mode and can also be used to produce the first group of processor signals at the same predetermined ones of the first group of processor terminals when the processor operating in a normal operation mode; and said processor emulation system further including a target system which includes at least one input/output device and, said target system receives target system input signals from one of the first and second processors and produces target system output signals; wherein the first processor is provided with said mode control signal such that the first processor is operating in the in-system emulation mode and the second processor is provided with the mode control signal such that the second processor is operating in the normal operating mode and wherein the output signals of the target system are coupled to terminals included in the second group of terminals of the first and second processors whereby operation of the second processor can be monitored by way of the majority of program counter bits provided at the first group of processor terminals of the first processor.