Patent Document ID: 9373073
Application ID: 13725463
Patent Flag: 1

Claim One:
1. A neurosynaptic device, comprising: a memory device that maintains neuron attributes for multiple neurons; multiple bit maps, wherein each bit map corresponds to a period of delay of different periods of delay, the bit map comprises at least one axon vector, each index of the at least one axon vector corresponds to an incoming axon of multiple incoming axons, and the index comprises a bit value indicating whether the corresponding incoming axon receives an incoming firing event in a future time step that occurs after the corresponding period of delay has elapsed; and a multi-way processor including a memory array that maintains a plurality of synaptic weights, wherein the multi-way processor is configured to: for each period of delay of the different periods of delay: in response to elapse of the period of delay, integrate one or more incoming firing events in accordance with a bit map corresponding to the period of delay in a time-division multiplexing manner, wherein the incoming firing events are integrated based on the neuron attributes and the synaptic weights; and generate an update vector representing firing activity of the multiple neurons based on the integrated incoming firing events, wherein at least one of the multiple bit maps is updated based on the update vector.