Patent Document ID: 4131941
Application ID: 05823360
Patent Flag: 1

Claim One:
1. A processor network comprising at least first and second microprogrammed digital processors, 1. each of said processors including: a. microprogram control means; b. control memory address bus for carrying microprogram sequencing information; c. an operation code mapping memory for generating an address code for addressing said microprogram control means via said control memory address bus; d. an arithmetic logic unit for receiving input data to be processed; e. data transfer means coupled between the output circuit of said microprogram control means and an input control circuit of said arithmetic logic unit; f. microprogram sequencer source means for sequencing said microprogram control means via the address bus; g. next control memory address source designator coupled to said arithmetic logic unit for selectively coupling said microprogram sequencer source means or said operation code mapping memory of one or the other(s) of said processors to said address bus depending upon the nature of the data generated by said arithmetic logic unit and/or other conditional input data transmitted to said memory address source designator; 2.