Patent Document ID: 9087176
Application ID: 14220665
Patent Flag: 1

Claim One:
1. A computer system comprising: a processor; memory connected to the processor; and computer executable program code configured to execute on the processor, wherein the computer executable program code configures the processor to: receive one or more training wafer profiles corresponding to one or more error correlated parameters of one or more training wafers, such error correlated parameters comprising at least one of a wafer shape, a wafer flatness, a chip layout, a film stack thickness, and a lithography scanner setting; apply a plurality of overlay error predictive models to the training wafer profiles to produce corresponding predicted overlay error profiles; receive one or more training wafer error profiles; compare the training wafer error profiles to the plurality of predicted overlay error profiles to determine a best fit overlay error predictive model from the plurality of overlay error predictive models; and determine a correction to a lithographic overlay process based on the best fit overlay error predictive model.