Patent Document ID: 5489857
Application ID: 07924201
Patent Flag: 1

Claim One:
1. In an integrated circuit, a structure comprising a programmable logic block including a plurality of programmable logic block cells wherein each programmable logic block cell is programmably configurable as one of a synchronous programmable logic block cell and an asynchronous programmable logic block cell; and each programmable logic block cell further comprises: a plurality of product terms; a first logic gate having a plurality of input lines and a output line; wherein one product term in said plurality of product terms is programmably connectable to and disconnectable from one of said first logic gate input lines; and the remaining product terms in said plurality of product terms are fixedly connected to input lines of said first logic gate; a programmable logic macrocell having at least one input line and an output line wherein said programmable logic macrocell further comprises: a programmable logic element, operatively coupled to said programmable logic macrocell input line, having an input terminal and an output terminal; and a logic signal polarity control element operatively coupled to said programmable logic element; wherein in a first mode of operation, said logic signal polarity control element generates a first output signal in response to an input signal; in a second mode of operation, said logic signal polarity control element generates a second output signal in response to said input signal and said second output signal is the inverse of said first output signal; and further wherein said logic signal polarity control element further comprises: a polarity control element logic gate having (i) a first input terminal connected to said programmable logic macrocell input line, (ii) a second input terminal connected to a line carrying one of a first signal and a second signal, and (iii) an output line for said polarity control element logic gate output signal wherein said output line is connected to said input terminal of said programmable logic element; and said line carrying one of said first and second signals is coupled to said one programmably connectable and disconnectable product term from said first logic gate; and a logic allocator element, selectively operatively coupled to and decoupled from said at least one input line of said programmable logic macrocell, having an input line coupled to the output line of said first logic gate and a plurality of output lines wherein said logic allocator element programmably connects said input line to one output line in said plurality of output lines and disconnects said input line from the remaining output lines in said plurality of output lines.