Patent Document ID: 7509243
Application ID: 11148086
Patent Flag: 1

Claim One:
1. A method of determining and building a high-speed VLSI reduced-order interconnect, comprising: a) accessing an interconnect in VLSI to be analyzed and creating a mathematical model based on electrical parameters including resistance, capacitance, inductance, coupling capacitance, and mutual inductance of the interconnect; b) feeding an expand frequency point based on a predetermined operating frequency; c) performing a non-symmetric Lanczos Algorithm; d) determining an order of reduced model for model reduction based on iteration termination conditions; e) performing a projection algorithm; f) creating a reduced system; g) inputting the reduced system into a signal analyzer for a high-speed and very-large IC interconnect; and h) analyzing the reduced system and building an interconnect using the reduced system, wherein the model reduction method has a transfer function of the perturbed system equal to the transfer function H(s) of original system, and a transfer function H Δ (s) of modified nodal analysis expressed as follows: ( A - Δ ) ⁢ ⅆ x Δ ⁡ ( t ) ⅆ t = x Δ ⁡ ( t ) - ru ⁡ ( t ) , ⁢ y Δ ⁡ ( t ) = c T ⁢ x Δ ⁡ ( t ) where, Δ=v q+1 δ q+1 w q ′+v q β q=1 w q=1 ′, q is the order of reduced model employed the non-symmetric Lanczos Algorithm comprising: 1) inputting a state equation of a target system; 2) selecting an expand frequency point of a reduced system; 3) determining an order of the reduced system; 4) performing the non-symmetric Lanczos Algorithm to create a projection matrix; 5) performing a double projection on state variables by means of the projection matrix to obtain a state equation of the reduced system; and 6) simulating by applying the state equation of the reduced system, while δ q+1 and β q+1 are obtained from computational process of reduced system; and the transfer function H Δ (s) of perturbed system is equal to transfer function Ĥ(s) of reduced system.