Patent Document ID: 5497334
Application ID: 08019924
Patent Flag: 1

Claim One:
1. A computer-implemented method for design verification of a physical design of a very large scale integrated (VLSI) circuit expressed in the form of hierarchical circuit design data, said method for design verification checking the hierarchical circuit design data in its most nested form and comprising the steps of: receiving a set of directives to be performed on the hierarchical circuit design data, said directives embodying design rule definitions for use in verifying compliance with design rules of the circuit design; performing a functional decomposition of the directives into primitive functions to perform the directives; establishing a primary iteration level for each directive; determining a data flow dependency for the directives; organizing the primitive functions based on the data flow dependency; generating an application program representative of the primitive functions by grouping together in clusters design rule checks and mask analysis operations that use a same base shape level, and establishing within each cluster a set of lists of shape instances (LISAs) required to perform design checks, the LISAs representing VLSI design component instances necessary to perform a set of directives on the hierarchical circuit accessing the hierarchical circuit design data; detecting intrusions between shape instances in the accessed hierarchical circuit design data; based on intrusions detected, processing LISAs for each checking cluster and dispatching checking functions; and outputting results of the checking functions indicating errors in the physical design of the VLSI circuit.