Patent Document ID: 9430599
Application ID: 14601312
Patent Flag: 1

Claim One:
1. A computer-implemented method comprising: obtaining a representation of a circuit, wherein the circuit comprises nodes, wherein the nodes comprise at least one critical node; obtaining a trace, wherein the trace comprises recorded values of the nodes in a plurality of cycles; determining, by a processor, a Soft Error Infliction Probability (SEIP) of a node, wherein the SEIP is a value representing a probability that a Single Event Upset (SEU) effecting the node in a cycle will inflict a soft error by propagating through the circuit to the at least one critical node, wherein said determining comprises simulating a propagation of the SEU from the cycle to consecutive cycles, wherein the consecutive cycles are successive cycles after the cycle, wherein said simulating utilizes values from the trace which are associated with the consecutive cycles, wherein the critical node is a conditional critical node having a condition on values of the circuit, wherein the condition is enabled in an enabling cycle, wherein the condition is held at the enabling cycle; wherein a discrepancy between a simulated value and a recorded value of a conditional critical node at the enabling cycle indicates a soft error; and outputting the SEIP of the node.