Patent Document ID: 8990281
Application ID: 13624469
Patent Flag: 1

Claim One:
1. A mixed-radix Fast Fourier Transform (FFT) implementation method for vector processors, the method comprising the steps of: decomposing input data into segments of factors based on a size of the input data, wherein the decomposing is performed in one or more stages, and wherein at each of the stages the input data is processed in blocks using one or more FFT butterfly computations for each of the blocks; reordering the stages in which the decomposing is performed to insure complete utilization of the vector processors, wherein the step of reordering the stages in which the decomposing is performed is carried out using a reordering unit configured to reorder the stages; and reordering the butterfly computations for one or more of the blocks to insure that the input data have memory addresses which are next to each other and contiguous, wherein the step of reordering the butterfly computations for one or more of the blocks is carried out using one or more other reordering units configured to reorder the butterfly computations at each of the stages.