Patent Document ID: 5461574
Application ID: 08373451
Patent Flag: 1

Claim One:
1. A computer-implemented method for optimizing a logic circuit in a multistage logic circuit optimizing process system for performing removal or scale-down modification of redundant circuit parts without changing the output logic of the circuit, said method comprising the steps of: (a) determining, by a computer, the order of a plurality of input variables of the multistage logic circuit; (b) creating a binary decision diagram representing a logic function for each gate and net of the multistage logic circuit, the binary decision diagram containing (1,0) as output logic; (c) creating a binary decision diagram representing a permissible function of a tree structure in which branches are linked to leaves for providing output logic (1, 0, don't care) for each gate and net of the multistage logic circuit; (d) performing an optimizing process involving removal of redundant parts of the multistage logic circuit and merge gates using the binary decision diagram representing the logic function and the binary decision diagram representing the permissible function; (e) determining whether or not a change has been made in the multistage logic circuit as a result of the optimizing process; and (f) repeating the above steps (a)-(e) when a change is made and terminating the processing when no change is made in the multistage logic circuit.