Patent Document ID: 20070038430
Application ID: 11428995
Patent Flag: 0

Claim One:
1. A method comprising: accessing: a description of a chip comprising a plurality of sequential elements and a clock mesh, the description identifying the sequential elements, indicating locations of the sequential elements on the chip, specifying interconnections among the sequential elements on the chip, and specifying a layout of the chip; information for modeling the sequential elements and interconnections; and a set of parameters of the clock mesh; using the description of the chip, the information for modeling the sequential elements and interconnections, and the set of parameters of the clock mesh: determining a plurality of original window locations covering the clock mesh, each original window location comprising one or more of the sequential elements on the chip; and for each original window location: expanding the original window location in one or more directions to generate a larger window location; generating a mesh simulation model comprising a detailed model inside the larger window location and an approximate model outside the larger window location; simulating the mesh simulation model; and measuring clock timing for the sequential elements in the original window location based on the simulation of the mesh simulation model; and collecting timing information on all the sequential elements on the chip based on the measured clock timing for the sequential elements in the original window locations.