Patent Document ID: 20030016822
Application ID: 09800145
Patent Flag: 0

Claim One:
1. A squaring circuit comprising: a host processor to compute the square of a long integer value by recursively reducing the square of said long integer value to a combination of the squares of reduced length integer values of a predetermined length, wherein at each step of said recursion said host processor reduces starting integer values to a combination of squares of three ending integer values of one-half the length of said starting integer values; a co-processor connected to said host processor to compute the squares of said reduced length integer values by further recursively reducing the squares of said reduced integer values into a combination of squares of hardware-length integer values that can be squared by hardware logic circuits, wherein at each step of said recursion said co-processor reduces starting integer values to a combination of squares of three ending integer values of one-half the length of said starting integer values; and one or more hardware logic circuits to square said hardware-length integer values.