Patent Document ID: 5463563
Application ID: 08085658
Patent Flag: 1

Claim One:
1. Method of generating logic and timing models in an integrated circuit design station having a computer, a graphic display device displaying signals generated by the computer, a graphic input device for making inputs to the computer, comprising performing the following steps in the integrated design station: operating on the inputs and storing in the computer a net-list interconnection representation of a graphical representation of a circuit; providing stimulus data corresponding to patterns of input stimuli for the circuit; simulating performance of a logic-level model of the circuit according to the stimulus data and providing logic simulation results, and representing the logic-level model of the circuit as interconnected logic blocks; simulating, at the circuit-level, performance of a transistor-level model of the circuit according to the stimulus data and providing simulated performance results; providing layout information to the transistor-level model of the circuit; providing timing and delay information obtained from the simulation performance of transistor-level simulation to the logic blocks used in the simulation of the logic-level model; comparing the logic simulation results with the simulated performance results according to pre-determined criteria for success; and providing an indication of a result of said comparison for automatic verification of the functional and timing accuracy of the generated logic-level model.