Patent Document ID: 9483648
Application ID: 13951837
Patent Flag: 1

Claim One:
1. A system including instructions recorded on a non-transitory computer-readable medium, and executable by at least one processor, the system comprising: a mapping engine configured to cause the at least one processor to access, from at least one computer memory, an attack model enumerating software attacks, the software attacks being represented by linked attack components, access, from the at least one computer memory, a software architecture to be tested, the software architecture including a plurality of components and being represented by linked architectural components in an architecture diagram, including at least a first architectural component and a second architectural component representing corresponding components of the plurality of components, access a tag database storing a plurality of attack tags, and select individual attack tags therefrom for attachment to individual components of the attack model and of the architecture diagram, and link, within the at least one computer memory, each attack component and each architectural component with at least one attack tag characterizing attack requirements; a global test plan engine configured to cause the at least one processor to construct an attack test model, including generating a first instance of the attack model for the first architectural component and a second instance of the attack model for the second architectural component and linking, within the at least one memory, at least a first attack component of the first instance with the first architectural component and at least a second attack component of the second instance with the second architectural component and further configured to cause the at least one processor to generate an executable attack test workflow from the attack test model; and a test execution engine configured to cause the at least one processor to execute the attack test workflow to thereby test the software architecture, wherein the global test plan generator includes a scope down engine configured to cause the at least one processor to filter the first instance and the second instance of the attack model, based on correspondence of attack tags of each instance with its corresponding architectural component.