Patent Document ID: 9721059
Application ID: 15002808
Patent Flag: 1

Claim One:
1. A method comprising: accessing, by a processor from a memory, a design layout of an integrated circuit; analyzing, by the processor, the design layout to extract an electrical netlist, the electrical netlist identifying all elements, input nodes, output nodes, power supply nodes and interconnects in the design layout and further associating all the interconnects with electrical resistors; extracting, by the processor, a thermal netlist based on the electrical netlist and using a one-to-one mapping technique such that the thermal netlist identifies thermal resistors, external thermal nodes and internal thermal nodes and such that each thermal resistor corresponds to a single electrical resistor, each external thermal node corresponds to a single one of an input node, an output node and a power supply node, and each internal thermal node corresponds to a single element; combining, by the processor, the electrical netlist and the thermal netlist into a combined thermal-electrical netlist by electrically connecting the internal thermal nodes of the thermal netlist to corresponding elements of the electrical netlist; performing, by the processor, simulations using the combined thermal-electrical netlist to generate a thermal-aware performance model of the integrated circuit; determining, based on the thermal-aware performance model, whether the integrated circuit meets a performance requirement; when the integrated circuit meets the performance requirement, releasing the design layout as a final design layout for manufacturing; when the integrated circuit fails to meet the performance requirement, modifying the design layout to meet the performance requirement and releasing the final design layout for manufacturing; and, manufacturing integrated circuits according to the final design layout.