Patent Document ID: 20140266347
Application ID: 14205208
Patent Flag: 0

Claim One:
1. A data interface circuit, comprising: a calibration controller circuit; two parallel data capture paths that capture a common data bit value, where each path includes a programmable DLL controlled by the calibration controller, said two data capture paths comprising a mission path that performs data capture for a functional circuit, and a reference path that performs data capture solely for calibration purposes; wherein one programmable DLL delays the common data bit for the mission path and one DLL delays the common data bit for the reference path; and wherein the data interface circuit is capable of performing continuous timing calibration and is operated by a method comprising: performing an initial calibration operation for both reference and mission paths to establish optimal delay settings, and determining a delta value between the optimal delay settings for the reference and mission paths; operating the functional circuit including operation of the mission path; from time to time and without interfering with operation of the functional circuit or the mission path, performing an additional calibration of the reference data path to determine a new optimal delay setting for the reference path; and if the new optimal delay setting for the reference data path differs from a previous delay setting by an amount greater than a change threshold value, setting the delay setting for the mission path to be equal to the new optimal delay setting for the reference path adjusted by the delta value.