Patent Document ID: 20110209108
Application ID: 12303638
Patent Flag: 0

Claim One:
1. An LSI design apparatus ( 170 ) for designing an LSI ( 140 ) having a normal system for performing normal functions, and a diagnosis system for communicating with a diagnosis program which is executed externally and diagnosing said normal system, comprising: a behavior model design device ( 180 ) which generates first behavior level design data ( 192 ), in which the logic of said normal system in said LSI ( 140 ) is described, and including a plurality of variables ( 167 ); a high level synthesis device ( 182 ) which inputs said first behavior level design data ( 192 ), and, on the basis of said first behavior level design data, generates first register transfer level (RTL) design data ( 194 ) in which the logic of said normal system is described and in which a plurality of hardware registers are included, and a high level synthesis log ( 196 ) which specifies said plurality of hardware registers within said first RTL design data; a diagnosis candidate analysis device ( 184 ) which inputs said first behavior level design data ( 194 ) and said high level synthesis log ( 196 ), and, on the basis of said first behavior level design data and said high level synthesis log, detects, from a plurality of variables ( 167 ) within said first behavior level design data, a plurality of diagnosis candidate variables which respectively correspond to said plurality of hardware registers ( 130 ) within said first RTL design data, and generates diagnosis candidate information ( 198 ) in which said mutually corresponding plurality of diagnosis candidate variables and said plurality of hardware registers are specified; a register address setting device ( 186 ) which inputs said diagnosis candidate information ( 198 ), maps said plurality of hardware registers ( 130 ) which are specified in said diagnosis candidate information onto a software address space which is used by said diagnosis program, and generates diagnosis address definition information ( 202 ) which specifies the address positions of a plurality of registers in said software address space; and a diagnostic logic automatic generation device ( 188 ) which inputs said first behavior level design data ( 192 ) and said diagnostic address definition information ( 202 ), and, on the basis of said first behavior level design data and said diagnostic address definition information, generates second behavior level design data ( 204 ) for said LSI, in which both said normal system and said diagnosis system are included; wherein said high level synthesis device ( 182 ) further inputs said second behavior level design data ( 204 ), and, on the basis of said second behavior level design data, generates second RTL design data ( 206 ), in which is described completed logic which includes both logic for said normal system and logic for said diagnosis system; and said LSI design apparatus ( 170 ) further comprising a logic synthesis device ( 190 ) which inputs said second RTL design data ( 206 ), and, on the basis of said second RTL design data, generates gate level design data ( 208 ) in which said completed logic is described.