Patent Document ID: 20050262409
Application ID: 10850460
Patent Flag: 0

Claim One:
1. A method for generating stimuli and test responses for testing faults in a scan-based integrated circuit in a selected scan-test mode or a selected self-test mode, the scan-based integrated circuit containing a plurality of scan chains, N clock domains, and C cross-clock domain blocks, each scan chain comprising multiple scan cells coupled in series, each clock domain having one capture clock, each cross-clock domain block comprising a combinational logic network; said method comprising the computer implemented steps of: (a) compiling a HDL (hardware description language) code modeled at RTL (register-transfer level) or at gate-level that represents said scan-based integrated circuit into a sequential circuit model; (b) specifying input constraints on said scan-based integrated circuit during a shift and capture operation; (c) specifying a clock grouping to map said N clock domains into G clock domain groups, where N>G>1; (d) transforming said sequential circuit model into an equivalent combinational circuit model according to said input constraints and said clock grouping, by selectively performing circuit expansion on selected cross-clock domain blocks and selected clock domains embedded completely within selected clock domain groups, and selectively performing circuit expansion on selected cross-clock domain blocks across selected clock domain groups, said selected clock domain groups in said G clock domain groups, said selected clock domains in said N clock domains, and said selected cross-clock domain blocks in said C cross-clock domain blocks; and (e) generating said stimuli and said test responses on said equivalent combinational circuit model according to said input constraints.