Patent Document ID: 8719761
Application ID: 13625682
Patent Flag: 1

Claim One:
1. A computer-implemented method of generating memory built-in-self-test (MBIST) circuitry to be disposed on an integrated circuit, comprising: (a) receiving an integrated circuit design that has a plurality of memory devices, wherein a plurality of memory factors are associated with each memory device; (b) selecting a weight for each grouping parameter of a plurality of grouping parameters associated with MBIST circuitry; (c) calculating an estimate for each grouping parameter of the plurality of grouping parameters using a compact model, wherein the compact model models a relationship between the plurality of grouping parameters and the plurality of memory factors, and wherein the compact model is formulated from test data of a plurality of test memory devices; (d) applying the weights to each estimated grouping parameter to create a cost function comprising a sum of weighted grouping parameters; (e) minimizing the cost function using an optimization technique; (f) generating an optimized grouping of MBIST circuitry based on the minimized cost function; and (g) inserting MBIST circuitry into the integrated circuit design according to the optimized grouping to generate a modified integrated circuit design; wherein at least the receiving, calculating, applying, minimizing, and generating are implemented by a computer.