Patent Document ID: 8255857
Application ID: 12347871
Patent Flag: 1

Claim One:
1. A method of designing an integrated circuit (IC), the method comprising: forming a first plurality of nodes for positioning objects of the IC design in a first layer, wherein the first plurality of nodes includes a first plurality of graph common nodes and a first plurality of graph uncommon nodes; and forming a second plurality of nodes for positioning objects of the IC design in a second layer, wherein the second layer is at least substantially parallel to the first layer and the second layer is spaced apart from the first layer by about a layer distance along a layer axis, the second plurality of nodes includes a second plurality of graph common nodes, the first plurality of graph common nodes and the second plurality of graph common nodes share positions, such that if the second plurality of graph common nodes were shifted toward the first plurality of graph common nodes by about the layer distance along the layer axis, the first plurality of graph common nodes and the second plurality of graph common nodes would be substantially identical, and if the second plurality of graph common nodes were shifted toward the first plurality of graph uncommon nodes by about the layer distance along the layer axis, then no node of the first plurality of graph uncommon nodes and no node of the second plurality of graph common nodes would be substantially identical; wherein the forming of the first plurality of nodes or the forming of the second plurality of nodes is performed with a processing unit.