Patent Document ID: 20170132344
Application ID: 15291459
Patent Flag: 0

Claim One:
1. A system for optimizing micro-benchmark analysis of a microprocessor design, the system comprising: a non-transient memory having stored thereon an architectural power model of the microprocessor design; a first computer-implemented circuit simulator that operates to: identify a suite of micro-benchmarks, each corresponding to a micro-benchmark workload condition for the microprocessor design; and simulate, under each micro-benchmark workload condition, fine-grained operation of the architectural power model to generate a set of micro-benchmark activity factors for the micro-benchmark workload condition, each micro-benchmark activity factor indicating an amount of activity monitored for a respective one of a plurality of sub-units of the architectural power model under the micro-benchmark workload condition; a second computer-implemented circuit simulator that operates to simulate coarse-grained operation of the architectural power model to generate a set of commercial workload activity factors, each commercial workload activity factor indicating an amount of activity monitored for each respective one of the plurality of sub-units of the architectural power model under a commercial workload condition; and a computer-implemented solver that operates to calculate a set of weighting factors as a function of the micro-benchmark activity factors and the commercial workload activity factors to apply to the suite of micro-benchmarks to yield a weighted aggregate micro-benchmark workload condition that substantially approximates the commercial workload condition.