Patent Document ID: 20120198409
Application ID: 13019280
Patent Flag: 0

Claim One:
1. A method of generating optimized input/output (IO) pair and inter-chip connection combinations for two chips, the method comprising: specifying a first design for a first chip and a second design for a second chip; specifying inter-chip signals based on the first and second designs; establishing IO pairs for the first and second chips based on the inter-chip signals; forming electrical contacts between micro-bumps (MBs) of the first and second chips; forming inter-chip paths with through-silicon-vias (TSVs) and MBs of the first and second chips; determining costs of assigning the IO pairs to the inter-chip paths; building a cost matrix based on the costs; using a computer, applying a bipartite matching algorithm to the cost matrix to determine the optimized IO pair and inter-chip path combinations.