Patent Document ID: 10073939
Application ID: 15344441
Patent Flag: 1

Claim One:
1. A method of designing communication interfaces between multiple components of an application specific integrated circuit (ASIC) chip, comprising: identifying, with a processor, interfaces and communication protocols used between pairs of components of the multiple components of the ASIC chip; determining, with the processor, timing estimates between the pairs of components of the multiple components of the ASIC chip; based on the identified communication protocols and the determined timing estimates between the pairs of components of the multiple components of the ASIC chip, configuring, with the processor, gaskets to insert into the interfaces of the multiple components of the ASIC chip, the gaskets configured to provide control of timing requirements of a communications link between the pairs of components of the multiple components of the ASIC chip; wherein the communications link utilizes a communication protocol method comprising: using delay insensitive (DI) codes to encode information to be communicated between the pairs of components of the multiple components of the ASIC chip, using quasi-delay-insensitive-logic to communicate the encoded information between the pairs of components of the multiple components of the ASIC chip, using temporal compression between the pairs of components of the multiple components of the ASIC chip, and using signals to indicate availability and readiness of information to be communicated between the pairs of components of the multiple components of the ASIC chip; and wherein the designed communication interfaces are usable in fabrication of the ASIC chip.