Patent Document ID: 10140396
Application ID: 14978721
Patent Flag: 1

Claim One:
1. A method comprising: providing a system graph of an electronic circuit comprising impedance components; identifying each branch of the system graph as at least one of a tree branch or a link, wherein the tree branches form a tree of the system graph; partitioning the tree into at least a first subtree and a second subtree; identifying links of the system graph as at least one of a global link or a local link, wherein a global link forms a path from a branch of the first subtree to a branch of the second subtree; forming the first subtree by repeatedly adding branches of the tree to the first subtree when a number of branches in the first subtree is less than a first predefined count and there are branches in the tree which have not yet been assigned to a subtree; forming the second subtree by repeatedly adding branches of the tree, not already assigned to the first subtree, to the second subtree when a number of branches in the second subtree is less than a second predefined count and there are branches in the tree which have not yet been assigned to a subtree; using a first processor, calculating a first current solution for each branch of the first subtree without global links; using a second processor, calculating a second current solution for each branch of the second subtree without global links; calculating an interblock solution comprising a junction current for a global link between the first subtree and the second subtree; and updating the solutions for the first subtree and the second subtree with a contribution from the interblock solution.