Patent Document ID: 20020065938
Application ID: 09858323
Patent Flag: 0

Claim One:
1. An architecture for intercepting and processing packets transmitted from a source to a destination over a network, the architecture comprising: a packet interceptor coupled with said network and operative to selectively intercept said packets prior to receipt by said destination; at least one primary processor coupled with said packet interceptor and operative to perform primary processing tasks on said intercepted packets, said at least one stateless processor including: at least two primary packet processors coupled in parallel, said processing of said intercepted packets being distributed among said at least two primary packet processors; at least one secondary processor coupled with said at least one stateless processor and operative to perform stateful processing tasks on said intercepted packets, said at least one secondary processor including: at least two secondary packet processors coupled in series with each other, each of said at least two secondary packet processors operative to perform a portion of said stateful processing tasks on said intercepted packets, a last one in said series of said at least two secondary packet processors being coupled with said network and operative to selectively release said intercepted packet back to said network.