Patent Document ID: 6046603
Application ID: 08989980
Patent Flag: 1

Claim One:
1. A method for partially reconfiguring an array of configurable logic blocks (CLBs) arranged in a plurality of rows and columns, the method comprising the steps of: connecting each column of CLBs to a corresponding column select line; connecting each row of CLBs to a corresponding row select line; selecting a rectangular set of CLBs to be reconfigured, wherein the rectangular set of CLBs is defined by the intersection of one or more consecutive columns of CLBs and one or more consecutive rows of CLBs; asserting column select signals on the column select lines associated with the one or more consecutive columns of CLBs; asserting row select signals on the row select lines associated with the one or more consecutive rows of CLBs; and enabling reconfiguration circuits within each CLB which receives both an asserted column select signal and an asserted row select signal; wherein the step of asserting the column select signals further comprises the steps of: asserting a first column select signal on a first column select line; propagating the first column select signal to one or more consecutive column select lines; and generating a control signal for stopping the propagation of the first column select signal.