Patent Document ID: 5586143
Application ID: 08499978
Patent Flag: 1

Claim One:
1. A digital signal processor for use in a receiver in a digital communications system, the digital signal processor comprising: a non-equaliser detector having an input for receiving a first input signal and delivering to a first output a first quality estimate and delivering to a second output a first bit decision; an equaliser having at least one input for receiving the first input signal and delivering to a third output a second quality estimate and delivering to a fourth output a second bit decision; comparison means for comparing the first quality estimate with the second quality estimate and delivering to a final output a third bit decision based on the comparison; and decision means for determining retraining of the equaliser based on the comparison of the first quality estimate and the second quality estimate, wherein the first quality estimate and the second quality estimate are measured over a sub-block of input signal duration and the third bit decision and retraining decision are made at the end of the sub-block.