Patent Document ID: 20170085255
Application ID: 14858749
Patent Flag: 0

Claim One:
1. A processor including a homogenous array of cells, with each of the cells capable of receiving an analog input, communicating with adjacent cells, and producing a digital output, each of the cells comprising: a comparator; a first input to the comparator that includes a voltage ramp that is shared by the homogenous array of cells and is applied to the first input in a recurring manner; a second input to the comparator, the second input alternating between a reference voltage and an analog input voltage, wherein the comparator generates an output voltage based on a comparison of at least two of the voltage ramp, the reference voltage, and the analog input voltage; and a gated counter for measuring pulse-widths of a signal that is based at least in part on the output voltage of the comparator, wherein the pulse-widths of the signal carry information about a magnitude of the analog input voltage.