Patent Document ID: 9348796
Application ID: 14031854
Patent Flag: 1

Claim One:
1. A data processing unit, comprising: approximate result computation circuit that iteratively computes an approximate result of an arithmetic operation performed on at least first and second operands each having a respective sign; supplementary value computation circuitry including two data registers in which at least two supplementary values of the arithmetic operation are computed concurrently with iterative computation of the approximate result; selection circuitry that selects a final result of the arithmetic operation from among a set of data inputs including the approximate result and the at least two supplementary values depending on a result of a last iteration of iterative computation by the approximate result computation circuit, wherein the selection circuitry receives, as control inputs, operand sign signals representing the signs of the at least first and second operands and selects the final result in response to the operand sign signals.