Patent Document ID: 20040123230
Application ID: 10696897
Patent Flag: 0

Claim One:
1. A message-passing decoder for low-density parity-check (LDPC) codes, which is for decoding block codes encoded with LDPC codes by a message-passing decoding algorithm, the message-passing decoder comprising: a log likelihood ratio calculator for receiving a code word having a consecutive value from block codes encoded with the LDPC codes, and calculating a log likelihood ratio; a bit node function unit for calculating a bit message using the log likelihood ratio calculated by the log likelihood ratio calculator and an input parity-check message; a check node function unit for calculating the parity-check message using the bit message calculated by the bit node function unit, and outputting the calculated parity-check message to the bit node function unit; and a parity checker for receiving a code word decoded by the bit node function unit from the final parity-check message calculated by a repeated decoding of the bit node function unit and the check node function unit, and checking a parity, wherein the parity-check message corresponding to a logic function output for an input from the bit node function unit is calculated according to a linear approximation function determined for each divided interval of the logic function.