Patent Document ID: 20030149712
Application ID: 10062378
Patent Flag: 0

Claim One:
1. A floating point unit comprising: a multiplier configured to generate a first result; an approximation circuit coupled to receive the first result and configured to generate an approximation of a difference of the first result from a constant; and a control circuit coupled to the multiplier and the approximation circuit, wherein the control circuit is configured to approximate a function specified by a floating point instruction provided to the floating point unit for execution using an approximation algorithm, the approximation algorithm comprising at least two iterations through the multiplier and optionally the approximation circuit, wherein the control circuit is configured to correct the approximation from the approximation circuit from a first iteration of the approximation algorithm during a second iteration of the approximation algorithm by supplying a correction vector to the multiplier during the second iteration; wherein the multiplier is configured to incorporate the correction vector into the first result during the second iteration.