Patent Document ID: 8850267
Application ID: 13565137
Patent Flag: 1

Claim One:
1. An apparatus comprising: a hardware circuit including memory configured to store middleware; and a plurality of processors coupled to said memory, wherein (i) one or more of said processors is configured to (a) generate a plurality of initial test vectors to test one or more software modules executed on said processors and (b) generate a plurality of modified test vectors translated from said initial test vectors by executing said middleware, (ii) a format of said modified test vectors matches (a) a plurality of hardware dependencies of said processors and (b) a plurality of software dependencies of a plurality of operating systems executed by said processors, (iii) said initial test vectors have another format that is independent of (a) said hardware dependencies of said processors and (b) said software dependencies of said operating systems and (iv) said processors are configured to generate a plurality of test results by exercising said software modules with said modified test vectors.