Patent Document ID: 7996193
Application ID: 12106948
Patent Flag: 1

Claim One:
1. A computer-implemented method, comprising: receiving a system model of a circuit design having a first system order, wherein the system model contains a plurality of system nodes and a plurality of system matrices; determining an expansion frequency of the system model; factorizing the plurality of system matrices at the expansion frequency by a matrix decomposition, wherein each of the plurality of system matrices is decomposed into a plurality of submatrices including an identity matrix; constructing a decomposition matrix (L (i) ) from the plurality of submatrices; constructing a sparse implicit projection matrix (M (i) ) from the decomposition matrix; constructing a plurality of reduced order system matrices from the sparse implicit projection matrix without explicitly calculating a projection matrix (M) directly from the plurality of system matrices; constructing a reduced order system model of the circuit design having a second system order with the plurality of reduced order system matrices, wherein the second system order is lower than the first system order; and running simulation of the circuit design using the reduced order system model.