Patent Document ID: 20160048755
Application ID: 14459577
Patent Flag: 0

Claim One:
1. A weighted sum system, comprising: a plurality of floating-gate transistors interconnected and arranged into subsets of transistors, wherein, for each subset of transistors, one of a source terminal or a drain terminal for each floating-gate transistor in a subset of transistors is electrically connected together at a select node and the other of the source terminal and the drain terminal for each floating-gate transistor in a subset of transistors is electrically connected to one of a plurality of output nodes, wherein the threshold voltage of the floating-gate transistors varies amongst the plurality of floating-gate transistors and each floating-gate transistor in the plurality of floating-gate transistors passes a current having a value that is a function of its gate voltage, its threshold voltage, and a voltage between its source terminal and its drain terminal such that current flowing through a given floating-gate transistor is unaffected by operation of remainder of the floating-gate transistors in the plurality of floating-gate transistors; a control circuit electrically connected to the select node for each subset of transistors and operates to selectively activate a given subset of floating-gate transistors in the plurality of floating-gate transistors; an input circuit electrically connected to each floating-gate transistor and operates to activate one or more floating-gate transistors in the given subset of floating-gate transistors; and an output circuit electrically connected, at a common output node, to the plurality of output nodes, the output circuit operates, substantially independently from amount of current that is being sourced, to maintain voltage at the common output node at a reference voltage and generates an output which is correlated to current that is being sourced collectively by the plurality of floating-gate transistors.