Patent Document ID: 20160203242
Application ID: 14593903
Patent Flag: 0

Claim One:
1. In an electronic design automation (EDA) tool, a method for placing a circuit design, the method comprising: receiving a netlist for the circuit design, wherein the netlist describes interconnections between a plurality of cells; representing the netlist as a graph; performing, using one or more processors, fuzzy clustering on the graph to obtain a set of clusters and a set of probability values, wherein each probability value corresponds to a probability of a given cell belonging to a given cluster; partitioning the netlist based on the set of clusters and the set of probability values to obtain a partitioned netlist; placing the partitioned netlist to obtain a placed circuit design, wherein cells of each partition are placed in a layout bin corresponding to the partition; and optimizing the placed circuit design, wherein said optimizing reassigns at least one cell to a different layout bin based on the set of probability values.