Patent Document ID: 20080312896
Application ID: 12228587
Patent Flag: 0

Claim One:
1. A method for running samples in a hardware assisted simulator including a bus functional model, said bus functional model including a cycle-count feedback register enabling binary-convergence to achieve optimal bus-operation performance in a logic simulation environment, comprising the steps of: counting on a software readable feedback register a first number of samples taken by said bus functional model from said hardware assisted simulator in execution of a first transaction on said bus functional model; storing a last actual sampling value given said hardware assisted simulator for said first transaction; encoding in a command register bus cycles for execution in a second transaction; setting a status flat to start said second transaction on said bus functional model; applying a binary convergence algorithm to generate a new sampling value for said second transaction based on said last sampling value given to said hardware assisted simulator and said last actual sampling value taken by said bus functional model for said first transaction; resetting said software readable feedback register; counting in said software readable feedback resister the number of sampling values taken by said bus functional model in executing said second transaction; and resetting said status flag to end said second transaction.