Patent Document ID: 8933742
Application ID: 13890649
Patent Flag: 1

Claim One:
1. A time mode device comprising: a switchable delay unit comprising: a first input port for receiving a signal comprising at least a first rising edge; a second input port for receiving a switch signal comprising at least a first falling edge and a second rising edge; a first circuit portion for receiving the signal and charging a capacitor from a predetermined supply voltage when the signal is low and discharging the capacitor when the signal is high; a second circuit portion for selectively coupling the capacitor to ground to enable its discharge when the switch signal is high and disable the discharge when the signal is high; an inverter circuit coupled to the capacitor, the inverter having a predetermined threshold voltage; wherein receipt of the second rising edge by the second circuit portion results in the voltage on the capacitor dropping below the predetermined threshold such that the inverter generates an output rising edge having a time delay with respect to the first rising edge; and the signal is coupled to the first input port in dependence upon a write signal applied to a first gate; the first falling edge of the switch signal is generated in dependence upon at least a receipt of a rising edge of a reference signal; and the second rising edge of the switch signal is generated in dependent upon at least a receipt of a read signal.