Patent Document ID: 4484259
Application ID: 06341703
Patent Flag: 1

Claim One:
1. An improvement in a numeric processor having a fraction bus, said processor for performing arithmetic calculations comprising: an adder having a first input coupled to said fraction bus; sum means for storing and shifting numeric quantities, the input of said sum means coupled to an output of said adder, the output of said sum means coupled to said fraction bus; a multiplexed register having its output coupled to a second input of said adder, the input of said multiplexed register coupled to said fraction bus; a skip shifter having a first output coupled to a third input of said adder; and control means coupled to said sum means and multiplexed register to selectively control said sum means and said multiplexed register depending on the arithmetic operation to be performed, a second output of said skip shifter being coupled to said control means to selectively provide control information thereto, whereby multiplication operations may be selectively performed.