Patent Document ID: 10146896
Application ID: 15344346
Patent Flag: 1

Claim One:
1. A method for fabricating a transistor meeting a leakage current specification at a plurality of operating temperatures, the method comprising: generating a third function, the third function being a function of a first plurality of design parameters, the third function being configured to return a value of a first design parameter, the first design parameter not being one of the first plurality of design parameters, the value returned by the third function being a value of the first design parameter for which a modeled leakage current equals the leakage current specification; generating a seventh function, the seventh function being a function of the first plurality of design parameters, the seventh function being a model of a minimum, over the operating temperatures of the plurality of operating temperatures, of an effective drive current of the transistor: at a fast-fast process corner; and at a value of the first design parameter for which a modeled leakage current equals the leakage current specification; finding a first set of respective values for the first plurality of design parameters for which the seventh function has a greatest value; and fabricating the transistor, the transistor having, as design parameters: the first set of respective values, for the first plurality of design parameters; and a value returned by the third function evaluated at the first set of respective values for the first plurality of design parameters, for the first design parameter, the generating of the third function comprising generating a first function, the first function being a function of: the first plurality of design parameters; and the first design parameter, the first function being an approximate model of a leakage current of the transistor at a typical-typical process corner, wherein the generating of the first function comprises: performing a plurality of technology computer aided design simulations, each resulting in a simulated leakage current; and generating a response surface methodology model to fit the results of the plurality of technology computer aided design simulations.