Patent Document ID: 6141283
Application ID: 09285998
Patent Flag: 1

Claim One:
1. A method for reducing the power-consumption of a system memory comprising a plurality of units of memory components that may independently one from another be placed in a reduced power-consumption state, wherein: a separate clock enable signal is provided to each of said plurality of units of memory components; respective idle or active states of each of said memory components are tracked based on requests by a requesting agent to access the respective memory components; the power-consumption of units of memory components is reduced by deasserting said clock enable signals provided to those units, if said memory components of those units of memory components are in an idle state; power is provided to those units which are in an active state by asserting said clock enable signal provided to those units; wherein said units are rows of memory components, wherein each row comprises a plurality of memory components and wherein a separate clock enable signal is provided to each row of memory components; and a row of memory components is placed in a reduced power consumption state by deasserting the corresponding clock enable signal, if all memory components of said row are in an idle state, and power is supplied to said memory components of said row by asserting said clock enable signal, if at least one of the memory components of said row is in an active state.