Patent Document ID: 20170219651
Application ID: 15010591
Patent Flag: 0

Claim One:
1. A method for an interactive logic diagnostic process, the method comprising: applying test patterns to a device under test in order to generate results; determining that a critical failure has occurred in the device from the results; and performing a diagnostic iteration loop, comprising: checking whether the critical failure has a diagnostic resolution that meets a predefined diagnostic resolution for physical failure analysis; in response to the critical failure not having the diagnostic resolution that meets the predefined diagnostic resolution for physical failure analysis, isolating potential faults related to the critical failure; in response to the critical failure having the diagnostic resolution that meets the predefined diagnostic resolution for physical failure analysis, ending the diagnostic iteration loop; applying path focused fault test patterns to the device in order to generate updated results of the path focused fault test patterns, such that the diagnostic resolution has been increased because of at least one of: a number of the potential faults related to the critical failure has decreased, and a size of a physical area of the potential faults related to the critical failure has decreased; and returning to performing the diagnostic iteration loop.