Patent Document ID: 5440162
Application ID: 08280417
Patent Flag: 1

Claim One:
1. An ESD protection circuit for an integrated circuit ("IC") employing silicide-clad N+ and P+ regions having a plurality of contact pads, said IC being coupled to first Vdd and first Vss, and substrate ground, comprising: a first N+ diode whose cathode is coupled to one of the contact pads forming a first node and whose anode is coupled to said substrate ground, said first diode comprising: a substrate of one of P.sup.- -type and P.sup.- -on-P.sup.+ epitaxial type; N+ regions disposed over said substrate to form a diode; P+ regions disposed over said substrate and connected to substrate ground; field oxide regions formed to electrically insulate said N+ regions from said P+ regions; N-well formed within said substrate enclosing the perimeter of said N+ regions, such that the first robust diode is prevented from avalanching below a predetermined voltage level applied to said pad.