Patent Document ID: 6117180
Application ID: 09024605
Patent Flag: 1

Claim One:
1. A computer-implemented method for designing the architecture of an embedded system, comprising: (a) a pre-processing phase comprising the steps of: (1) parsing one or more task graphs, one or more system/task constraints, and a resource library for the embedded system; and (2) assigning one or more fault detection tasks to one or more original tasks in the task graphs to enable the embedded system to perform fault detection for the one or more original tasks; and (b) a synthesis phase, following the pre-processing phase, comprising the steps of allocating the fault detection tasks and one or more groups of one or more original tasks to one or more processing elements (PEs) in the resource library and allocating one or more edges in the task graphs to one or more communication links in the resource library, based on performance evaluation of one or more possible allocations for each of the groups, edges, and fault detection tasks in light of the system/task constraints, wherein the pre-processing phase comprises the step of performing task clustering on the one or more task graphs to form one or more clusters for the embedded system, wherein task clustering comprises the steps of: (i) assigning a fault tolerance (FT) level to each original task based on execution time, communication time, and any associated fault detection tasks; and (ii) determining an appropriate cluster for each original task based on the FT level in order to reduce FT overhead.