Patent Document ID: 10102604
Application ID: 15083689
Patent Flag: 1

Claim One:
1. A heterogeneous three-dimensional circuit stack comprising: a first processor; a second processor vertically stacked with the first processor, the second processor communicatively coupled with the first processor through one or more through-silicon-vias (TSVs), wherein the second processor is a graphics processor; and a fabric interconnect including interconnect logic to communicatively couple the first processor and the second processor with a shared resource, the fabric interconnect to couple with the first processor and the second processor via corresponding on-chip interconnects in each of the first processor and the second processor, wherein the interconnect logic is to enable coherent access to the shared resource for execution threads of the graphics processor, wherein to enable coherent access to the shared resource, the interconnect logic is to route traffic that originates from a single execution thread of the graphics processor within the same traffic class; wherein the fabric interconnect additionally includes bandwidth sharing logic to adjust bandwidth to the shared resource; and wherein the shared resource includes memory to cache data to be received via the fabric interconnect.