Patent Document ID: 5463591
Application ID: 08225450
Patent Flag: 1

Claim One:
1. A dual port memory comprising: n memory cell arrays each having a plurality of word lines, a plurality of bit lines intersecting said plurality of word lines while insulated therefrom, and a plurality of memory cells, disposed correspondingly to intersections between said bit lines and said word lines, each for outputting data stored therein to corresponding one of said bit lines and for receiving data therefrom, said plurality of bit lines divided into k bit line groups, each of said k bit line groups including m bit lines; k data buses each operatively connected to each of said k bit line groups of each of said n memory cell arrays; n bit selecting circuits, disposed correspondingly to said n memory cell arrays, for selecting one of said m bit lines in each of said k bit line groups of said corresponding memory cell array in accordance with bit selection signals thereby effecting data transfer between said one of said m bit lines and said k data buses; at least one serial access port; and a shift register circuit connected to said serial access port, wherein said shift register circuit has p serially connected partial shift registers each including k serially connected individual registers operatively connected to each of said k data buses, respectively, said partial shift registers operating for receiving serial bit data from outside through said serial access port and storing said serial data in said individual registers or for transferring serial data stored in said partial shift registers through said k data buses to said one of said n memory cell arrays; wherein each of said n, k, m and p is an integer not less than two.