Patent Document ID: 9003342
Application ID: 14230931
Patent Flag: 1

Claim One:
1. A system for analyzing the timing of a circuit design, the system comprising: a memory to store the design including instances of a plurality of nets; a processor configured to: identify a victim net in the plurality of nets, identify a plurality of aggressor nets for the victim in the plurality of nets, for each aggressor net in the plurality of identified aggressor nets: estimate a glitch created by the aggressor net, for an aggressor net having a glitch below a predetermined threshold, add the aggressor net to a lumped aggressor model such that each aggressor net in the lumped aggressor model is electrically connected to a shared node; for an aggressor net having a glitch above a predetermined threshold, model the aggressor net separately; and simulate the victim net, with reference to the lumped aggressor model or the separately modeled aggressor nets, to estimate the timing for the victim net; wherein during simulation, for each aggressor net in the lumped aggressor model, the glitch for each aggressor is simulated individually using an associated driver waveform.