Patent Document ID: 7606322
Application ID: 11150445
Patent Flag: 1

Claim One:
1. A linearizer for a circuit comprising: characterizer means coupled to an input to and an output from said circuit for generating a set of coefficients and predistortion means responsive to said coefficients for predistorting a signal input to said circuit whereby said circuit generates a linearized output in response thereto, and the predistortion means comprising circuitry configured for: filtering the signal through a linear digital filter having one or more linear digital filter taps, each linear digital filter tap other than a first linear digital filter tap being successively delayed by one delay unit; generating one or more powers of the signal; inputting one or more of the generated powers of the signal through one or more tapped delay lines, each tapped delay line having one or more nonlinear digital filter taps, each nonlinear digital filter tap other than a first nonlinear digital filter tap being successively delayed by one delay unit; applying said coefficients to the linear and nonlinear digital filter taps; summing each of the nonlinear digital filter taps corresponding to a certain number of delay units; and adding the sum of each of the delay units from the summing step to a particular linear digital filter tap.