Patent Document ID: 9633151
Application ID: 14675699
Patent Flag: 1

Claim One:
1. A computer implemented method for verifying an electronic design with clock domain crossing paths, comprising: executing a process with at least one micro-processor of a computing system, the process comprising: identifying, at a clock domain crossing (CDC) identification module including or coupled with a design traversal module and at least one micro-processor of a computing system, a first electronic design component for verification of the electronic design at least by traversing at least a portion of the electronic design; generating a representation of the electronic design at least by interconnecting one or more duplicated electronic design components, which are duplicated from one or more corresponding electronic design components in the electronic design, with the first electronic design component; injecting one or more CDC effect models into the presentation at least by reducing a set of injection candidates into a reduced set of injection candidates with an application of one or more CDC rules and by adding the one or more CDC effect models along one or more paths associated with the reduced set of injection candidates in the representation of the electronic design; and generating proof results at least via proving or disproving one or more checkers for the electronic design by verifying or simulating the representation with the one or more CDC effect models.