Patent Document ID: 8880382
Application ID: 13352713
Patent Flag: 1

Claim One:
1. A computer-implemented method comprising: accessing results of forward simulations of circuit yield on a set of configurations that are drawn from at least variation ranges, the results comprising at least circuit yield results comprising simulated device shapes, the variation ranges for mask features in one or more lithographic masks used in a lithographic patterning process to create a portion of an integrated circuit comprising electrical devices that are patterned by imaging the mask features to create device shapes; using the circuit yield results, determining high-level traits of at least the simulated device shapes; constructing, based on the determined high-level traits and using the circuit yield results, a compact model for predicted yield, the compact model comprising a plurality of adjustable parameters, and the constructing the compact model for predicted yield comprising adjusting the adjustable parameters until at least one first predetermined criterion is met, wherein the compact model for predicted yield has a form of a truncated Taylor series and adjusting the adjustable parameters further comprises calculating coefficients of the truncated Taylor series by finite-differencing the predictions of yield from the compact model for predicted yield and the circuit yield results until finite-differences meet the at least one first criterion; constructing an optimization problem comprising at least the compact model for yield, an objective, and a plurality of constraints; and using the optimization problem, modifying the objective subject to the plurality of constraints until at least one second predetermined criterion is met.