Patent Document ID: 20020133776
Application ID: 09808325
Patent Flag: 0

Claim One:
1. A method of maximising the fault coverage on an integrated digital circuit by re-ordering a number of test vectors for testing the digital circuit, said method comprising: a) providing an initial set of test vectors T 0 ; b) providing an original set of faults F 0 ; c) selecting faults at random from the original fault list to form a sample fault list F N ; d) forming a vector set T N−1 and simulating the vector set T N−1 against fault list F N ; e) discarding any vector from the vector set T N−1 which does not detect any faults, and f) saving the remaining vectors as vector set T N, repeating the above steps a) to e) N times with N having a value of 1 to M so that the end of N steps saving test vectors T 0 to T M ; g) removing duplicate vector patterns in each vector set T N, and h) initialising the final vector set and appending vector sets V M to V 0 to produce a final vector set T F.