Patent Document ID: 20030030479
Application ID: 10156731
Patent Flag: 0

Claim One:
1. A logarithmic amplifier, comprising: a high gain section having plural gain paths, each gain path including an amplifier and a signal limiter in series, and each gain path being connected in parallel to a common input, each of the gain paths having an output and a gain; the outputs of the plural gain paths being connected to a signal summation circuit and summed to form an output signal; a low gain section connected between the common input and the signal summation circuit; delay elements in plural gain paths of the high gain section and the low gain section, the delays of the delay elements being selected to compensate for variation between group and phase delay of the gain paths, the delay elements of at least two of the plural gain paths sharing a common amplifier; and the gain of each of the plural gain paths and the low gain section being selected so that the output signal varies logarithmically with the input voltage.