Patent Document ID: 9779359
Application ID: 13420247
Patent Flag: 1

Claim One:
1. A method for performing modular addition using a constant-depth carry-save adder circuit in a two dimensional nearest-neighbor quantum architecture, the method comprising: receiving n-bit binary numbers a, b, and c at associated adjacent qubits, wherein the n-bit binary numbers a, b, and c have respective bits a i , b i , and c i , wherein i indicates a bit position with significance 2 i ; performing an addition of a, b, and c by coupling the qubits associated with each of a, b, and c to corresponding nearest-neighbor qubits associated with one or more of a, b and c using n parallel carry-save adder circuits, wherein each parallel carry-save adder circuit sums corresponding bits a i , b i , and c i to produce bits u i , and v i , of output numbers u and v, respectively, by coupling a i , b i , and c i to two nearest-neighbor ancilla qubits associated with output numbers u and v; truncating v n−1 , u n−1 , and v n , from u and v; and distributing a modular residue c vn−1 controlled on v n−1 to u and v to produce a first result.