Patent Document ID: 10063262
Application ID: 15000978
Patent Flag: 1

Claim One:
1. A decoder for decoding forward error correcting codewords using a parity check matrix comprising a plurality of sub-matrices, the decoder comprising: a plurality of check node processing units to receive a forward error correction codeword and to each perform, in parallel, a check node computation on the forward error correction codeword using a different row of the parity check matrix, each of the plurality of check node processing units comprising: an input computation stage to compute initial computation values from a plurality of variable node messages, the input computation stage comprising, a minimum computation unit determining a first minimum value and a second minimum value of the variable node messages and determining an identity of a variable node corresponding to the first minimum value; and a sign product computation unit determining a product of signs of the variable node messages received from the plurality of variable nodes; a pipelined message memory having at least two memory stages, the pipelined message memory to receive the initial computation values at an initial memory stage of the message memory and to shift the initial computation values to a subsequent memory stage in the pipelined message memory at a predefined clock interval; an output computation stage to receive the initial computation values from a final memory stage of the pipelined message memory and to generate a plurality of check node output messages; a plurality of variable node processing units, each variable node processing unit to receive the plurality of check node messages and to perform variable node update computations corresponding to different columns belonging to a same sub-matrix of the parity check matrix to generate the variable node messages; and an output circuit to receive the variable node messages and to generate a decoded codeword based on the variable node messages.