Patent Document ID: 9075941
Application ID: 13894420
Patent Flag: 1

Claim One:
1. A method for optimizing an electrodeposition process of one or more vias, comprising: simulating a wafer electroplating uniformity with one or more first input parameters to generate one or more output parameters; determining one or more critical parameters governing difficulty in achieving good via filling, wherein the critical parameters comprises the output parameters; calculating one or more critical factors for one or more of the vias based on the critical parameters; selecting a representative via from the vias for reduction of simulation time based on a value of the critical factor; obtaining a sampling point by an optimizer, wherein the sampling point comprises one or more sampling values of one or more process parameters; simulating a filling process of the representative via with the sampling point to determine one or more void lengths and/or one or more effective seam lengths appeared within the representative via; calculating a filling goodness based on the void lengths and/or the effective seam lengths determined in the simulated filling process; repeating the steps from obtaining the sampling point by the optimizer to calculating the filling goodness with other sampling points until all of the sampling points are processed; and generating a process window of the process parameters based on the calculated filling goodness; wherein the filling goodness (FG) is calculated by below equation: FG = ∑ ⁢ hv + ∑ ⁢ h _ ⁢ s h ⁢ ⁢ FG ∈ [ 0 , 1 ] where hv is the void length, h s is the effective seam length and h is a via depth.