Patent Document ID: 8589855
Application ID: 13484111
Patent Flag: 1

Claim One:
1. A computer-implemented method of extracting datapath logic from an integrated circuit design, comprising: receiving a circuit description for the integrated circuit design which includes a plurality of cells interconnected to form a plurality of nets, by executing first instructions in a computer system; generating cell clusters from the circuit description, by executing second instructions in the computer system; evaluating the cell clusters to identify one or more cluster features in the cell clusters, by executing third instructions in the computer system; and selectively classifying the cell clusters as either datapath logic or non-datapath logic using one or more machine-learning models based on the one or more cluster features, by executing fourth instructions in the computer system wherein said classifying uses at least two machine-learning models each providing an indication of whether a given one of the cell clusters is datapath logic, and the given cell cluster is classified as datapath only when both of the two machine-learning models indicate that the given cell cluster is datapath logic wherein a first one of the machine-learning models is a support vector machine, and a second one of the machine-learning models is a neural network.