Patent Document ID: 7844926
Application ID: 11345554
Patent Flag: 1

Claim One:
1. A method for identifying specification window violations for an integrated circuit, the method comprising: generating a pseudo-random sample set of input parameters for the integrated circuit; simulating the integrated circuit using the pseudo-random sample set of input parameters to generate an output set; fitting a mathematical model to the output set; optimizing the mathematical model by identifying areas where the mathematical model does not fit the output set, and re-fitting the mathematical model after removing a least statistically significant term; defining a set of desirability functions to an out-of-spec condition, the desirability functions are set based on an analysis of the output set; searching the mathematical model using the desirability functions to identify a worst-case data point; determining whether the worst-case data point is within specification or out of specification; and implementing the worst-case data point for defining an integrated circuit design to be used to make the integrated circuit when the worst-case data point is within specification.