Patent Document ID: 20100167184
Application ID: 12644790
Patent Flag: 0

Claim One:
1. A method comprising: simulating a photolithography process using a mask layout to produce a first simulated resist image; perturbing each edge segment in the mask layout by a selected amount to produce an initial perturbed layout; simulating the photolithography process using the initial perturbed layout to produce a second simulated resist image; determining a difference resist image value between the first simulated resist image and the second simulated resist image for each edge segment; creating an n×n matrix J such that ΔRI=JΔC, where ΔRI is an n×1 vector of changes in resist image values and ΔC is an n×1 vector of changes in segment locations; initializing the matrix J using the difference in resist image values divided by the perturbed amount; determining a correction delta vector ΔC by minimizing |JΔC+RI| 2 +α|ΔC 2 subject to constraints imposed on ΔC, wherein the correction delta vector includes a correction delta value for each edge segment and α is a non-negative scalar; perturbing each edge segment in the perturbed layout by the corresponding correction delta value in the correction delta vector ΔC to create a further perturbed layout; simulating the photolithography process using the further perturbed layout to produce a third simulated resist image; using information from the third simulated resist image and the matrix J to produce an updated matrix J; and updating the correction delta vector ΔC by minimizing |JΔC+RI| 2 +α|ΔC| 2 subject to constraints imposed on ΔC, where the updated matrix J is used in the minimization.