Patent Document ID: 20060064271
Application ID: 10947090
Patent Flag: 0

Claim One:
1. A method for semiconductor fabrication fault analysis, the method comprising the steps of: receiving a wafer lot identity as a study lot identity, the wafer lot identify having at least one corresponding test record; acquiring at least one suspect fabrication issue corresponding to the study lot identity; acquiring a number of comparative wafer lot identities which have been processed by the same fabrication tool and fabrication recipe as the study lot identity, each of the comparative wafer lot identities having at least one corresponding test record; comparing the test records of the study lot identity with the test records of the comparative wafer lot identities to identify comparative wafer lot identities having a failure relating to the suspect fabrication issue which is similar to a failure of the study lot identity; calculating a similarity score for each comparative wafer lot identity having the similar failure; and calculating a causal score according to the similarity scores of the comparative wafer lot identities having the similar failure for the suspect fabrication issue.