Patent Document ID: 7493248
Application ID: 11382088
Patent Flag: 1

Claim One:
1. A method of simulation processing in a data processing system, said method comprising: building an instrumented simulation executable model of a design, said building including compiling one or more hardware description language (HDL) files specifying one or more design entities within the design and one or more instrumentation entities and instantiating instances of the one or more instrumentation entities within instances of the one or more design entities, wherein said step of instantiating comprises instantiating each of the instances within a particular design entity indicated by the one or more HDL files, and wherein said instrumented simulation executable model includes a plurality of instances of said one or more design entities; simulating operation of the design utilizing the instrumented simulation executable model, wherein said simulating includes: each of multiple instantiations of the one or more instrumentation entities generating from one or more signals in at least one instance of the one or more design entities a respective external phase signal representing an occurrence of a particular phase of operation, wherein said particular phase is an end-of-testcase phase indicating that an end of a simulation testcase has been reached; identifying each of a plurality of phases of operation of said instrumented simulation executable model with a respective phasename; restricting application of at least one phasename to a region of the instrumented simulation executable model defined by one of said plurality of instances of said one or more design entities; instrumentation combining logic generating from external phase signals of the multiple instantiations of the one or more instrumentation entities an aggregate phase signal representing an occurrence of the particular phase; and the data processing system automatically halting simulation of the design in response to the aggregate phase signal indicating an occurrence of the end-of-testcase phase.