Patent Document ID: 20070044052
Application ID: 11506668
Patent Flag: 0

Claim One:
1. A method of verifying the power off effect of a design entity of a digital system, the method comprising: in a hardware definition language, specifying a device model at a register transfer level (RTL), the device model describing function blocks for performing predetermined functions using a plurality of power sources, and including a model for a case where all of the power sources are supplied and a model for a case where one or more of the power sources are blocked; specifying a test input signal model at the RTL describing a test input signal to be input to the design entity to verify the case where all of the power sources are supplied and the case where one or more of the power sources are blocked; and specifying a test output signal model at the RTL describing a test output signal to be output from the design entity in response to the test input signal.