Patent Document ID: 6124820
Application ID: 08975435
Patent Flag: 1

Claim One:
1. An apparatus including an error correction stage in a pipeline analog to digital converter, comprising: an input terminal for receiving an input signal; and a plurality of stages including a first stage coupled to said input terminal and a last stage, each of said plurality of stages including an additive error level and a local error correction level, said last stage configured to be a first error correction stage; wherein said additive error level of said each subsequent stage from said first stage is accumulated and compared with said local error correction level at each stage until said accumulated error level exceeds said local error correction level in one of said stages so that said stage immediately prior to said one stage in which said accumulated error level exceeds said local error correction level is configured to be another error correction stage and said accumulated error level is initialized to zero; and further wherein said error level accumulation, said comparison with said local error correction level at said each stage, said configuration of said stage immediately prior to said another stage in which said accumulated error level exceeds said local error correction level as yet another error correction stage, and said initialization of said accumulated error level are repeated until said last stage.