Patent Document ID: 20170063576
Application ID: 14840500
Patent Flag: 0

Claim One:
1. A decision feedback circuit comprising: a plurality of decision feedback equalizer (DFE) branches, each DFE branch including: a pre-computation stage configured to generate a set of tap-adjusted inputs, each tap-adjusted input corresponding to a possible value of a previous output for the same DFE branch; and a decision feedback stage comprising a multiplexer circuit configured to select at least one output from the set of tap-adjusted inputs based on tap-adjusted inputs from other DFE branches; where for at least a first DFE branch of the plurality of DFE branches, at least one selection line for the multiplexer circuit in the decision feedback stage of at least the first DFE branch of the plurality of DFE branches is an intermediate value from a multiplexer circuit for a second DFE branch of the plurality of DFE branches, wherein the intermediate value is an output from a first multiplexer in the second DFE branch, where the output of the first multiplexer is an input to a second multiplexer in the multiplexer circuit of the second DFE branch.