Patent Document ID: 9280412
Application ID: 13890698
Patent Flag: 1

Claim One:
1. A memory device including: a non-volatile memory array storing data and ECCs; error correcting logic; and logic to read a data set from the memory array by performing iterations including sensing data in selected cells using a read bias, and producing an indication of errors in the sensed data, where a first iteration uses a first read bias; then if the indication in a current iteration is less than a threshold number of bits correctable using the ECCs, then outputting the data from the selected cells sensed in the present iteration; if the indication in the current iteration exceeds the threshold, then moving the read bias and performing another iteration, unless the indication in the current iteration shows an increase in errors relative to a previous iteration, in which case then outputting data from the selected cells sensed in the previous iteration; and double buffering logic to store sensed data during a current and a previous iteration; logic to provide the sensed data from the double buffering logic to error correcting logic for correction of errors, where the memory comprises an array of memory cells having threshold voltages that indicate stored data values, said read bias includes a word line voltage, and the moved read bias includes a changed word line voltage.