Patent Document ID: 6035106
Application ID: 08840338
Patent Flag: 1

Claim One:
1. For configuring a logic array integrated circuit having a plurality of function blocks to implement a logic design, the logic design comprising a plurality of interconnected logic cells, each occurrence of a logic cell in the design being an instance of the logic cell, each of said logic cells being defined by a functional definition common to all instances of said logic cell, and each of said defined logic cells having a default physical layout, a method of using a computer to place said logic design in said logic array while at least partially maintaining a hierarchical relationship among logic cell instances and a logic cell functional definition, said method comprising the steps of: generating a first alternative physical layout of a first logic cell, said first alternative layout having a functional definition identical to that of said default layout of said first logic cell; determining whether said first alternative layout is preferable to said default layout of said first logic cell when one or more instances of said first logic cell is placed; selecting either of said first alternative layout and said default layout for placement in at least one of said function blocks; placing said plurality of logic cells, including said first logic cell having said selected layout, among said function blocks, thereby allowing selective placement of the logic design while at least partially maintaining the hierarchical relationship among the plurality of logic cell instances and the logic cell functional definition.