Patent Document ID: 3962706
Application ID: 05456488
Patent Flag: 1

Claim One:
1. A data processing apparatus for highly parallel execution of stored programs, comprising: memory means for holding instructions of a data processing program and data items for processing under direction by said program, said memory means comprising a plurality of cells, each cell comprising plural registers, each register comprising means for holding an instruction or a data item, each register of said memory means having a unique address, and each instruction comprising an operation code specifying a computational operation and zero or more addresses; functional means including at least one functional unit for performing computational operations on data items. arbitration means for transmitting instruction packets from any cell of said memory means to functional units, an instruction packet comprising an instruction and at least one data item, said arbitration means delivering the data item parts of each instruction packet and the plural address parts of each instruction packet to functional units capable of performing the computational operation specified by the operation part of said instruction packet; said arbitration means beng capable of transmitting a plurality of instruction packets at the same time; distribution means for transmitting result pockets from said functional units to registers of said cells, a result packet comprising a data item and an address, said distribution means delivering the data item part of each result packet to the register specified by the address part of the result packet, said distribution means being capable of transmitting a plurality of result packets at the same time; said functional means further comprising: means for separating the data items and address parts of instruction packets received from said arbitration means; means for performing a computational operation on the data items to produce a new data item; means for holding addresses during the performance of computational operations on the associated data items; means for combining a data item and one or more addresses into one or more result packets for transmission through said distribution means; each register of each cell indicating whether it contains an instruction or data item and whether it is full or empty; and each register accepting a data item delivered to it by said distribution means as said register becomes empty, each register further indicating that it is full when an instruction or data item has been transferred into said register, each cell presenting to said arbitration means an instruction and data items held in its registers just as all registers of said cell are full; each register contributing its contents as part of an instruction packet transmitted to said arbitration means while retaining the instruction or data item and maintaining a full indication or otherwise becoming empty and changing to an empty indication; and means for setting up instruction and initial data items in said memory means, for controlling the number of cycles of program execution, and for altering stored instructions and data items at intermediate points during program execution.