Patent Document ID: 9767868
Application ID: 14589145
Patent Flag: 1

Claim One:
1. A method for providing memory training for a dynamic random access memory (DRAM) system, comprising: disabling memory operations on a first port of the DRAM system and a second port of the DRAM system of a plurality of ports of the DRAM system; configuring the first port of the DRAM system and the second port of the DRAM system to communicate via a loopback connection; receiving, by the first port of the DRAM system, a training signal from a System-on-Chip (SoC); providing, by the first port of the DRAM system, the training signal to the second port of the DRAM system via the loopback connection; and providing, by the second port of the DRAM system, the training signal to the SoC.