Patent Document ID: 5491650
Application ID: 08049829
Patent Flag: 1

Claim One:
1. An MVM processing comprising: an array of N rows and M columns of CCD matrix cell groups corresponding to a matrix of N rows and M columns of matrix elements, each of said matrix elements representable with b binary bits of precision, each of said matrix cell groups comprising a column of b CCD cells storing b CCD charge packets representing the b binary bits of the corresponding matrix element, the amount of charge in each packet corresponding to one of two predetermined amounts of charge wherein each of said CCD cells comprising a holding site and a charge sensing site, each charge packet initially residing at the respective holding site; means for sensing, for each row, an analog signal corresponding to a total amount of charge residing under all charge sensing sites of the CCD cells in the row; an array of c rows and M columns CCD vector cells corresponding to a vector of M elements representable with c binary bits of precision, each one of said M columns of CCD vector cells storing a plurality of c charge packets representing the c binary bits of the corresponding vector element, the amount of charge in each packet corresponding to one of two predetermined amounts of charge; and multiplying means operative for each one of said c rows of said CCD vector cells for temporarily transferring to said charge sensing site the charge packet in each one of said M columns of matrix cells for which the charge packet in the corresponding one of said M columns and said one row of said CCD vector cells has an amount of charge corresponding to a predetermined binary value.