Patent Document ID: 9154146
Application ID: 14295037
Patent Flag: 1

Claim One:
1. A method for calibrating split analog-to-digital (ADC) architecture, comprising: receiving, along a first signal path comprising a first input buffer associated with a first ADC of said split ADC, an input signal; receiving, along a second signal path comprising a second input buffer associated with a second ADC of said split ADC, said input signal, said input signal split between said first signal path and said second signal path; applying an offset to the first signal path; determining, via each split ADC, conversion results for the first signal path and the second signal path, said conversion result for the first signal path is based upon said applied offset; and determining a difference between each conversion result, wherein if said difference corresponds to a non-constant value, calibrating the split ADC via application of a learning algorithm, and wherein if said difference corresponds to a constant value, identifying the split ADC as a linear system.