Patent Document ID: 4878200
Application ID: 07139450
Patent Flag: 1

Claim One:
1. An erasable programmable logic device (EPLD) having a programmable memory array coupled to receive a plurality of input signals and, by providing a plurality of output signals which depend on said input signals and information stored in said memory array, said output from said memory array coupled to a plurality of macrocells, wherein product terms are shared between adjacent macrocells, each macrocell comprising: a first OR'ing means coupled to receive a first predetermined number of output lines from said memory array; a second OR'ing means coupled to receive a second predetermined number of output lines from said memory array; said first and second OR'ing means each for providing an OR'ing function of its coupled predetermined number of output lines from said memory array; a first multiplexor coupled to said first OR'ing means for receiving a first OR'ed output of said first OR'ing means; a second multiplexor coupled to said second OR'ing means for receiving a second OR'ed output of said second OR'ing means; said first OR'ed output of said first OR'ing means is also coupled to a subsequently adjacent macrocell; said second OR'ed output of said second OR'ing means also is coupled to a previously adjacent macrocell; a third multiplexor coupled to receive a second OR'ed output of said second OR'ing means of said subsequently adjacent macrocell; and a fourth multiplexor coupled to receive a first OR'ed output of said first OR'ing means of said previously adjacent macrocell; a third OR'ing means coupled to receive outputs of said first, second, third and fourth multiplexors such that each of said OR'ed outputs is coupled to said third OR'ing means when said respective multiplexor is selected; an input/output (I/O) circuit coupled to receive an output of said third OR'ing means, said I/O circuit for emulating logic functions and providing an output from said macrocell.