Patent Document ID: 5517654
Application ID: 07888936
Patent Flag: 1

Claim One:
1. A method of operating a plurality of digital processors wherein a root processor interfaces with a user and a PICO system operates in interemdiacy between said root processor and a network of multiprocessors to solve enumerative problems and the like using a shadow node system generated under a speculative node expansion mode, in said PICO system, to use idle processor capacity within said network of processors and said shadow node to be prospectively integrated into a successor node by the user and convergence between said shadow nodes and said successor nodes is confirmed, comprising the steps of: storing a root node on a list of nodes on an expansion queue in a node generation subsystem of the PICO system: allocating said expanded nodes to the network of multiprocessors; hashing said expanded nodes; generating offsprings forming shadow nodes to occupy idle capacity of the network of multiprocessors; interacting with a message subsystem, initialized by the user, to refine said shadow nodes comprising the steps of: routing shadow node offsprings via a message channel subsystem in the PICO system; removing nodes to curtail offspring generation: broadcasting bounds, values and upper and lower limits of said offspring to thereby compare with said root node and determine convergence; and routing said broadcast to deploy message to the network of processors via a message channel subsystem in the PICO system; connecting the PICO system to said root processor via a state vector; and managing memory and shutdown operation of the PICO system by an auxiliary function means.