Patent Document ID: 8397199
Application ID: 12762861
Patent Flag: 1

Claim One:
1. A method comprising: simulating a first model of a circuit using a first stress vector that specifies a constant input stimulus that places the circuit under aging stress, the simulating performed on one or more computers to produce a first simulation result; processing the first simulation result to automatically identify one or more first transistors in the circuit that are aged under the first stress vector, the processing performed by the one or more computers; receiving a list of nets that experience high rates of switching during operation; identifying one or more second transistors in the circuit that are connected to one or more of the listed nets, the identifying performed by the one or more computers; modifying a netlist representation of the circuit to replace nominal transistors corresponding to the one or more first transistors and the one or more second transistors with aged transistors that exhibit aging effects, the modifying performed by the one or more computers, wherein nominal transistors remain in the netlist representation subsequent to the modifying for transistors other than the first one or more transistors and the second one or more transistors; and processing the netlist to ensure that the circuit meets design requirements with the aged transistors in the circuit, the processing performed by the one or more computers.