Patent Document ID: 8290761
Application ID: 12478312
Patent Flag: 1

Claim One:
1. A method of operating a computing system to model and simulate an integrated circuit, comprising: for each parameter of one or more parameters that vary over an integrated circuit die, generating, by the computing system, a model of an intra-die variation of the parameter such that a number of random variables for the model is compressed to a reduced number (r) of random variables based on a spatial correlation of the intra-die variation of the parameter; and for each run of a plurality of runs for a simulation for the integrated circuit: generating, by the computing system, sample values for the reduced number of random variables for each of the one or more parameters using a Quasi-Monte Carlo (QMC) technique; for each parameter of the one or more parameters, computing, by the computing system, values for the parameter for at least a subset of a plurality of locations on the integrated circuit die using the sample values for the reduced number (r) of random variables for the parameter and the model of the intra-die variation of the parameter; and performing, by the computing system, the run for the simulation using the values computed for each parameter of the one or more parameters.