Patent Document ID: 9407472
Application ID: 14308461
Patent Flag: 1

Claim One:
1. An apparatus comprising: a circuit including: a first input to receive a first signal; a second input to receive a second signal, the second input different and distinct from the first input; a first filter circuit adapted to determine first weighting coefficients and second weighting coefficients based on the first signal, the second signal, and an error signal, and a recursive least square (RLS) process; a second filter circuit adapted to modify the first signal via the first weighting coefficients to produce a first filtered signal, and modify the second signal via the second weighting coefficients to produce a second filtered signal; a first combiner circuit adapted to combine the first filtered signal and the second filtered signal to produce a combined signal; a reference signal generator circuit configured to generate a reference signal based on a bit sequence; a second combiner circuit adapted to combine the reference signal and the combined signal to produce the error signal; and an output to provide the combined signal.