Patent Document ID: 10031987
Application ID: 15182655
Patent Flag: 1

Claim One:
1. A method comprising: receiving design logic comprising an untimed net, wherein the untimed net is indicated as being excluded from timing constraints; generating, using one or more computer processors, an upstream event network using shadow logic, wherein the upstream event network comprises at least one untimed transition detector (UTD) corresponding to a first sequential element upstream from the untimed net in the design logic; generating a downstream event network using shadow logic coupled to an output of the upstream event network, wherein the downstream event network comprises at least one metastability timer (MT) corresponding to a second sequential element downstream from the untimed net in the design logic; generating a metastability network using shadow logic, wherein the metastability network is coupled to an output of the MT; verifying the design logic using the upstream event network shadow logic, the downstream event network shadow logic, and the metastability network shadow logic; and manufacturing an integrated circuit based on the verified design logic.