Patent Document ID: 9310433
Application ID: 14689596
Patent Flag: 1

Claim One:
1. A method comprising: receiving a file describing a system-on-a-chip (SoC); parsing the file to determine one or more functions to be performed by one or more hardware components of the SoC, wherein the SoC is fabricated on a chip; receiving a desired output of the SoC; generating a test scenario model based on the desired output of the SoC and the one or more functions to be performed, wherein the test scenario model includes one or more module representations of the functions, wherein the test scenario model further includes one or more connections between two of the module representations, wherein each connection provides a direction of flow of data between the two module representations, wherein the desired output acts as a performance constraint for the test scenario model, wherein the test scenario model further includes an input of the SoC that is generated based on the desired output, the module representations, and the one or more connections, wherein the test scenario model includes a path from the input via the module representations and the connections to the desired output, wherein receiving the file, parsing the file, receiving the desired output, and generating the test scenario model are executed by one or more processors, generating one or more test files for the test scenario model and an application scenario model; compiling the one or more test files to generate a compiled file; generating multiple results by executing the compiled file within a test bench program, wherein the test bench program is executed by at least one of the one or more processors, wherein the compiled file includes the test scenario model and an application scenario model, wherein one of the results is associated with an application of the test scenario model and another one of the results is associated with an application of the application scenario model, wherein the application scenario model includes at least two of the module representations and one or more connections between the at least two module representations; and comparing the results with pre-stored results to determine whether the SoC passed a test.