Patent Document ID: 5502729
Application ID: 08010180
Patent Flag: 1

Claim One:
1. A method of testing for stuck-at faults of a synchronous circuit comprising a memory element and at least one combinational circuit, said method comprising the steps of: expanding said synchronous circuit into a plurality of combinational circuits which are provided over time; generating a test pattern for each of said combinational circuits, each test pattern comprising an input value and a primary input value for said each combinational circuit, the input value having an internal input value received from said memory element, said each test pattern being used to detect faults by being applied to said each combinational circuit, said each test pattern being formed in a sequence in an order in which the test pattern is applied to said synchronous circuit over time; and generating an expanded test pattern with other primary input values for detecting other faults with regard to said each test pattern, such that the internal input value to be applied from said memory element is fixed; sequentially supplying each said test pattern having the internal input value and the primary input value to said each combinational circuit; sequentially supplying each expanded test pattern generated for a corresponding test pattern to said each combinational circuit with the internal input value of the corresponding test pattern fixed when each said test pattern is applied to said each combinational circuit; and observing a primary output of said each combinational circuit when the test pattern and the expanded test pattern are applied to said each combinational circuit.