Patent Document ID: 4802119
Application ID: 07026511
Patent Flag: 1

Claim One:
1. A single chip microcomputer comprising: a central processing unit adapted to serially execute a plurality of instructions; an internal address bus connected to said central processing unit; an internal data bus connected to said central processing unit; at least one memory block coupled to said internal address and data busses; at least one patch memory block connected to said internal address and data busses decode means connected to said internal address bus for examining a portion of an address thereon and responding thereto by enabling an indicated one of said at least one memory block; at least one register means for containing at least one starting address of said at least one patch memory block; patch means connected to said internal address bus and to said at least one register means for comparing a portion of an address on said address bus and said at least one starting address and for responding thereto by enabling said at least one patch block and disabling said indicated one of said at least one memory block.