Patent Document ID: 9361416
Application ID: 13994882
Patent Flag: 1

Claim One:
1. A method to dynamically assign coprocessor regions in a Field Programmable Gate Array (FPGA), the method comprising: dynamically executing a placement algorithm to determine at least one resource efficient arrangement of coprocessor regions within the FPGA, wherein the at least one resource efficient arrangement of coprocessor regions is at least more resource efficient than a starting arrangement of coprocessor regions by using more of the FPGA for coprocessor regions than is used by the starting arrangement of coprocessor regions; dynamically executing a path finding algorithm to determine multiple path finding operations to transition the FPGA from the starting arrangement of coprocessor regions to the resource efficient arrangement of coprocessor regions, each path finding operation comprising: establishing a different reconfiguration region of the FPGA, different from reconfiguration regions for other path finding operations, wherein at least one coprocessor region is outside the different reconfiguration region, and wherein at least one coprocessor region is inside the different reconfiguration region; disabling coprocessors having coprocessor regions in the different reconfiguration region while allowing coprocessors having coprocessor regions outside the different reconfiguration region to continue to operate; assigning one or more new coprocessor regions in the different reconfiguration region; and loading coprocessors in each of the one or more new coprocessor regions; and dynamically performing the multiple path finding operations to transition the FPGA from the starting arrangement of coprocessor regions to the resource efficient arrangement of coprocessor regions.