Patent Document ID: 10002079
Application ID: 15380066
Patent Flag: 1

Claim One:
1. A method for predicting a datum to be preloaded into a cache memory, said method comprising: a) for each instant t at which a microprocessor executes an instruction to read a datum necessary for the execution of a program, calculating a difference, called delta, between the address of the datum to be read contained in said read instruction executed at the instant t and the address of the datum to be read contained in said read instruction during its previous execution at an instant t−1, two read instructions being the same if they both correspond to a same value of the program counter of the microprocessor, b) storing an observed access sequence containing only the N deltas calculated successively for each instant t lying within a sliding window [t 1 ; t 0 ], where the instants t 0 and t 1 are equal to the most recent and the oldest instants t, respectively, for which a delta of the observed access sequence has been calculated, and the number N is a predetermined integer number greater than or equal to two, wherein the method also comprises: c) acquiring a, so-called “model”, statistical distribution of the deltas of a model access sequence, said model statistical distribution comprising: classes of possible values for the deltas, and associated with each of these classes, a number dependent on the number of occurrences of said class in the model access sequence, d) the construction of a, so-called “observed”, statistical distribution of the deltas of the observed access sequence, e) identifying in the observed statistical distribution, by comparing it with the model statistical distribution, of a most deficient class for which the difference NoDSM−NoDSO is maximal, where NoDSM and NoDSO are the numbers of occurrences of said class that are deduced, respectively, from the model statistical distribution and from the observed statistical distribution, f) providing as prediction of the datum to be preloaded into the cache memory before the next execution of the same read instruction, of at least one predicted address where the datum to be preloaded is contained, said predicted address being constructed on the basis of the most deficient class identified during step e).