Patent Document ID: 7519939
Application ID: 11680090
Patent Flag: 1

Claim One:
1. A computer implemented method for supporting a register-transfer-level (RTL) design of a semiconductor integrated circuit, comprising: storing a RTL description related to the semiconductor integrated circuit into a first memory, the RTL description including a description of a compound block containing a mixture of logics of combinational and non-combinational circuit descriptions; extracting a logic of the non-combinational circuit description from the compound block description by checking the mixture of the logics of the combinational and the non-combinational circuit descriptions; storing a RTL library including cells into a second memory; comparing the logic of the extracted non-combinational circuit description with a logic of each cell, and; if the comparison results show that one of the cells has the same logic as the logic of the extracted non-combinational circuit description, replacing the extracted non-combinational circuit description with the cell having the same logic of the extracted non-combinational circuit decription; and if the comparison results show that the logic of the extracted non-combinational circuit description is not the same as the logic of any of the cells, dividing the extracted non-combinational circuit description into a replaceable part and a remaining part, wherein the remaining part comprises a combinational circuit, and replacing the replaceable part with one of the cells.