Patent Document ID: 20030093742
Application ID: 10202509
Patent Flag: 0

Claim One:
1. A turbo decoder extrinsic calculation block comprising: a plurality of alpha metric inputs, each alpha metric input having a predetermined number of bits; an alpha circle boundary detector receiving said plurality of alpha metric inputs and generating an alpha circle boundary cross signal indicating whether the two's complement format of any alpha metric input is either a two's complement positive number or a two's complement negative number in a most negative quadrant or not; a plurality of alpha metrics precision extend block, each alpha metrics precision extend block receiving said alpha circle boundary cross signal and a most significant bit of a corresponding alpha metric input and generating a two bit precision extension for said corresponding alpha metric input dependent upon said alpha circle boundary cross signal and said most significant bit of said alpha metrics input; a plurality of beta metric inputs, each beta metric input having said predetermined number of bits; a beta circle boundary detector receiving said plurality of beta metric inputs and generating a beta circle boundary cross signal indicating whether the two's complement format of any beta metric input is either a two's complement positive number or a two's complement negative number in a most negative quadrant or not; a plurality of beta metrics precision extend blocks, each beta metrics precision extend block receiving said beta circle boundary cross signal and a most significant bit of a corresponding beta metric input and generating a two bit precision extension for said corresponding beta metric input dependent upon said beta circle boundary cross signal and said most significant bit of said beta metrics input; and an extrinsics block receiving said alpha metrics inputs as precision extended by said corresponding alpha precision extend block and said beta metrics inputs as precision extended by said corresponding beta precision extend block, said extrinsics block including an adder constructed to operate on two's complement numbers having two more than said predetermined number of bits.