Patent Document ID: 4393468
Application ID: 06247675
Patent Flag: 1

Claim One:
1. An integrated circuit device for processing digital data in response to instruction signals in connection with a digital memory means and multiplier means, said device comprising: a plurality of storage registers for storing said data; an arithmetic logic unit for performing preselectable arithmetic and logic operations on said data in response to said instruction signals; first means for selectively coupling said digital memory means and preselectable ones of said storage registers for moving data between said memory means and said preselected storage registers in response to said instruction signals; second means for selectively coupling preselectable ones of said storage registers and said arithmetic logic unit to said multiplier means for moving data from said preselected storage registers and said arithmetic logic unit to said multiplier means in response to said instruction signals; third means for selectively coupling said multiplier means to preselectable ones of said storage register means and said arithmetic logic unit for moving data from said multiplier means to said preselected storage registers and said arithmetic logic means in response to said instruction signals; and fourth means for selectively coupling preselectable ones of said storage registers for moving data through said preselected storage registers in response to said instruction signals, wherein said first, second, third and fourth selective coupling means and said arithmetic logic unit are simultaneously operable in response to said instruction signals.