Patent Document ID: 8180821
Application ID: 12407271
Patent Flag: 1

Claim One:
1. A digital logic circuit for performing mathematical computations using residue arithmetic, comprising: a first circuit adapted for converting residues from Complex Residue Number System to Quadratic Residue Number System, wherein each Complex Residue Number System residue comprises an imaginary residue operand, b i , wherein the first circuit adapted for converting said residues from Complex Residue Number System to Quadratic Residue Number System comprises a second circuit adapted for multiplying the imaginary residue operand of the Complex Residue Number System input, b i , by ĵ, wherein the second circuit adapted for multiplying the imaginary residue operand of the Complex Residue Number System input, b i , by ĵ comprises a plurality of logic gates, wherein the plurality of logic gates is selected by: computing a value of the product of b i , and ĵ, modulo p i for each possible modular data operand; extracting logical equations representing computed values of the multiply by ĵ function; and mapping the logical equations to the plurality of logic gates.