Patent Document ID: 8032349
Application ID: 11626915
Patent Flag: 1

Claim One:
1. A method of generating a model, said method comprising: receiving, by a processor, measurement data collected from devices in scribe-lines of a production wafer manufactured in a specific manufacturing environment selected from amongst multiple manufacturing environments, said devices comprising field effect transistors, said specific manufacturing environment comprising at least a specific factory, and said measurement data comprising, for each device, an effective channel length measurement and current and voltage measurements; sorting, by said processor, said measurement data so as to identify and select at least the following: a first channel length which is a longest channel length measured, said first channel length being associated with first current and voltage measurements; and a second channel length which is a shortest channel length measured, said second channel length being associated with second current and voltage measurements; performing, by said processor, an optimization process based on said measurement data in order to generate customized modeling parameters for a field effect transistor, said customized modeling parameters associated with said specific manufacturing environment and said performing of said optimization process comprising performing a multi-step optimization process comprising: performing a first optimization process in order to generate a first set of modeling parameters for said field effect transistor, said first set being based on supplied starting values and said first current and voltage measurements associated with said first channel length; performing a second optimization process in order to generate a second set of modeling parameters for said field effect transistor, said second set being based on said first set and on said second current and voltage measurements associated with said second channel length; combining said first set and said second set to form a combined set; and performing a third optimization process in order to generate said customized modeling parameters for said field effect transistor, said customized modeling parameters being based on said combined set; and developing, by said processor, a model for said field effect transistor based on said customized modeling parameters, said model being representative of said specific manufacturing environment.