Patent Document ID: 9712146
Application ID: 14858749
Patent Flag: 1

Claim One:
1. A processor including a homogenous array of cells, with each of the cells capable of receiving an analog input, communicating with adjacent cells, and producing a digital output, each of the cells comprising: a comparator; a first input to the comparator that includes a voltage ramp that is shared by the homogenous array of cells and is applied to the first input in a recurring manner; a second input to the comparator, the second input alternating between a reference voltage and an analog input voltage, wherein the comparator generates an output voltage based on a comparison of at least two of the voltage ramp, the reference voltage, and the analog input voltage; an AND gate in each of the cells wherein an output of the AND gate comprises a pulse signal, the AND gate receiving as input the output voltage of the comparator and a logic signal, wherein the output voltage of the comparator, the logic signal, and the pulse signal are, respectively, only capable of a high-level and a low-level, wherein the logic signal is set to a high-level only when the voltage ramp is applied to the first input of the comparator, wherein the pulse signal is set to a high-level only when both the output voltage of the comparator and the logic signal are set to their respective high-levels; a logic unit with an input signal from each of the adjacent cells, where the input signal is the pulse signal of the adjacent cell, and an additional input signal which is the pulse signal of the present cell, and with an output voltage which corresponds to an aggregate of the input signals; and a gated counter for measuring pulse-widths of a signal that is based at least in part on the output signal of the logic unit, a digital output of the gated counter reflecting information about a output voltage of the logic unit.