Patent Document ID: 20150317126
Application ID: 14701818
Patent Flag: 0

Claim One:
1. A binary logic circuit configured to approximate a mathematical function over a predefined range as a series of linear segments, each linear segment having one of a predetermined set of fixed gradients and a corresponding base value, the binary logic circuit comprising: an input for receiving an input variable in the predefined range; a plurality of logic chains each comprising: a binary multiplier adapted to perform multiplication by a respective one of the set of fixed gradients using h−1 binary adders, where h is the minimum Hamming weight of: a binary representation of the fixed gradient; a trinary representation of the fixed gradient; and a representation of the fixed gradient as a product of two binary numbers, two trinary numbers, or a binary and a trinary number; the h−1 binary adders being logically configured to perform the multiplication using the representation of the fixed gradient having that minimum Hamming weight h; and a binary adder adapted to add a base value to one of the input and output of the binary multiplier; and selection logic configured to select one of the logic chains in dependence on the input variable so as to provide as an output for the received input variable, an approximate value of the mathematical function.