Patent Document ID: 20080180292
Application ID: 11822565
Patent Flag: 0

Claim One:
1. A digital-to-analogue converter, comprising: a plurality of pairs of digital-to-analogue converter elements; and an adder, connected to form an analogue output signal as the sum of the outputs of the pairs of digital-to-analogue converter elements; and further comprising: an element matching circuit, connected to receive a digital input signal, and apply respective inputs to the pairs of digital-to-analogue converter elements, wherein the element matching circuit comprises a dynamic element matching stage associated with each of the pairs of digital-to-analogue converter elements, and wherein each dynamic element matching stage comprises: an input for a respective stage remainder value, the remainder value having a parity determined by a value of a least significant bit thereof; first and second quantizers, for forming a pair of quantizer outputs, a sum of said quantizer outputs being constrained to be equal to the parity of the remainder value; first and second feedback loops, associated with the first and second quantizers respectively, for forming respective first and second loop values and applying said loop values as inputs to the first and second quantizers respectively, and at least one integrator, for producing an output signal based on at least one of the quantizer outputs during time periods when said first and second loop values are substantially equal, wherein, during subsequent time periods when said first and second loop values are substantially equal, said quantizer outputs are controlled based on the output signal of the at least one integrator.