Patent Document ID: 20180004496
Application ID: 15200053
Patent Flag: 0

Claim One:
1. A computing device for optimizing sparse matrix code, the computing device comprising: an analysis module to identify a performance-critical loop in a sparse matrix source code; and an optimization module to generate optimized executable code for the sparse matrix source code, wherein the optimized executable code includes processor code and field-programmable gate array (FPGA) code, wherein: the processor code is to cause a processor of a target computing device to (i) execute a first iteration of the performance-critical loop and (ii) generate reusable optimization data of the performance-critical loop in response to execution of the first iteration; and the FPGA code is to cause an FPGA of the target computing device to (i) execute one or more additional iterations of the performance-critical loop and (ii) optimize the one or more additional iterations of the loop based on the reusable optimization data.