Patent Document ID: 4763289
Application ID: 06815435
Patent Flag: 1

Claim One:
1. In a method operable on an electronic data processing system for generating Boolean gate level logic models of complementary metal oxide semiconductor circuits wherein the complete logic description of all of the transistors making up the CMOS circuit (to be modeled) specifying all logic functions and including the interconnectivity of the transistors is stored in machine readable form in system memory as a series of Boolean gate level descriptions and access to each individual CMOS gate making up said overall logic circuit description is available, the improvement which comprises a procedure for accurately representing the operation of the circuits to be modeled by considering all static hazard and charge storage effects inherent in the circuits in turn, utilizing Boolean logic equations to reflect a series of logic transformations in the gate level logic descriptions in accordance with a series of predetermined logic transformations and simplifications and including generating models for both faultless and faulty circuits and storing same in memory for use in analyzing the performance of the simulated CMOS circuits said procedure including a method for modeling a faultless CMOS gate circuit comprising both nFET and pFET networks wherein the nFET and pFET networks both contain identical static hazards, comprising generating a Boolean logic network for a function Tp derived from the combinatorial logic description of the circuit accessed from memory wherein the inputs to the network are the logical inputs to the circuit such that Tp is represented functionally as the output of an OR function, defining said OR function for Tp as having an input for each acyclic path from the circuit power source VDD to the CMOS gate's output net, such that said input is the output of an AND function with a complemented literal for each input to the CMOS gate that gates a transistor on said acyclic path from VDD, successively substituting in the resultant network only static hazard preserving transformations in the logic defining the circuit to simplify same, and representing the output F of the simulated circuit as being represented by the output of the generated logic circuit which produces Tp.