Patent Document ID: 9262307
Application ID: 13253089
Patent Flag: 1

Claim One:
1. A method executable on one or more processors for modeling a test space for verifying a behavior of a computing system, the method comprising: defining a coverage model associated with verifying the computing system, wherein the defined coverage model includes a set of variables, further comprising: one or more variables within at least one subset of a plurality of subsets of the set of variables are selected according to an interaction level requirement defined for at least one or more of the subsets, wherein the interaction level corresponds to a coverage of the test space that covers a plurality of possible combinations of the one or more variables at multiple levels, wherein respective values for the one or more selected variables within the subset of the set of variables are assigned, and one or more definitions for value combinations for said variables with assigned values, wherein at least one of said value combinations is defined as optional, and zero or more value combinations are defined as forbidden or mandatory for purpose of generating test scenarios to test a system for which the coverage model is defined, wherein the at least one of said value combinations defined as optional can increase the coverage of the test space, and wherein the at least one of the value combinations are defined as optional and the zero or more value combinations are defined as forbidden or mandatory by a pre-defined list of logical Boolean operations or indicators, wherein the pre-defined list of logical operations or indicators comprises a plurality of binary flags associated with a logical computing language; and generating a plurality of test scenarios to test the computing system for which the coverage model is defined.