Patent Document ID: 5481499
Application ID: 08405566
Patent Flag: 1

Claim One:
1. An integrated matrix memory comprising a circuit arrangement for testing the addressing of at a matrix, comprising storage elements which are arranged at intersections of row conductors and column conductors, the addressing taking place by way of a multibit address, via a decoder which comprises at least one row decoder and one column decoder, each of which is arranged to receive and decode a different part of the address bits and to drive each time a different row conductor or to select at least one column conductor, via selection switches, for connection to at least one output terminal, characterized in that the memory comprises a test bus and in that at the side of the matrix which is remote from the row decoder each row conductor can be coupled to a different conductor of the test bus and that at the side of the matrix which is remote from the selection switches each column conductor can be coupled to a different conductor of the test bus.