Patent Document ID: 7594209
Application ID: 11741042
Patent Flag: 1

Claim One:
1. A method for accurately timing an integrated circuit (IC) incorporating effects of Miller capacitance, the IC consisting of a plurality of stages consisting of gates and interconnects, the method comprising: a) selecting a primitive gate and its respective fan-out gates, first interconnects being attached to the primitive gate output and second interconnects being respectively connected to each of the fan-out gates outputs; b) replacing the selected primitive gate with its nonlinear model equivalent, and replacing selected ones of the respective fan-out gates with their nonlinear model equivalents maintaining the fan-out gates connected to their respective second interconnects and replacing the non-selected respective fan-out gates with a linear capacitance; c) performing a simulation on the modified IC said simulation being executed by a computer, generating voltage waveforms at the output of the selected primitive gates, propagation delays or transition times at an output of the primitive gate and an input of its fan-out gates; d) propagating the generated voltage waveforms, propagation delays or transition times to a next stage thereof, and e) repeating steps a) through c) until all the primary outputs of the IC are reached.