Patent Document ID: 8328694
Application ID: 13455531
Patent Flag: 1

Claim One:
1. A computer program product, comprising a computer readable tangible storage device having computer readable program code stored therein, said program code configured to be executed by a processor to implement a method of training, said method comprising: said processor receiving signals from a training transducer at a first interface; said processor receiving training schedule data from a remote correspondent at a second interface, the training schedule data defining times by which a specified exercise is to be performed by a user; said processor storing said training schedule data in a first memory; said processor outputting a human perceptible signal in accordance with a feedback template, said human perceptible signal comprising data content relating to performance of the exercise by the user, said feedback template specifying a manner in which the data content is to be conveyed to the user; said processor storing, in a second memory, output status data from which the human perceptible signal is generated; said processor continuously (i) carrying out a determination, in real time as the user is performing the exercise, of whether said signals received at said first interface satisfy criteria of conforming to said training schedule data with regard to a time value obtained from a clock; and (ii) updating said training schedule data as a function of a result of said determination; wherein a training device comprises the first interface, the second interface, the first memory, the second memory, the processor, and the clock; wherein the processor is directly connected to the first interface via a unidirectional first link in which data can flow only from the first interface to the processor; wherein the processor is directly connected to the second interface via a bidirectional second link in which data can flow from the second interface to the processor or from the processor to the second interface; wherein the processor is directly connected to the first output via a unidirectional third link in which data can flow only from the from the processor to the first output; wherein the processor is directly connected to the first memory via a bidirectional fourth link in which data can flow from the first memory to the processor or from the processor to the first memory; wherein the processor is directly connected to the second memory via a unidirectional fifth link in which data can flow only from the second memory to the processor; wherein the processor is directly connected to the clock via a unidirectional sixth link in which data can flow only from the clock to the processor.