Patent Document ID: 9177093
Application ID: 13753374
Patent Flag: 1

Claim One:
1. A method of routing an integrated circuit (IC) design, comprising: accessing the IC design including a plurality of objects on one or more layers; forming a plurality of levels, wherein the plurality of levels includes a first level representing the IC design at a first grid density, a second level representing the IC design at a second grid density finer than at least the first grid density, and a third level representing the IC design at a third grid density finer than at least the first grid density and the second grid density; based at least partly on the IC design, populating each level of the plurality of levels with the plurality of objects; interconnecting the plurality of objects at one or more of the first level, the second level, and the third level; and initiating generation of an integrated circuit from the IC design based on the accessing, forming, populating, and interconnecting; wherein one or more of the accessing, forming, populating, and interconnecting is performed using a computer.