Patent Document ID: 6043719
Application ID: 09270028
Patent Flag: 1

Claim One:
1. A low-voltage, low-jitter voltage controlled oscillator for receiving a control voltage and generating an output signal and a complementary output signal each with a frequency proportional to the control voltage, the voltage controlled oscillator comprising: a first delay unit, a second delay unit and a third delay unit each having an input terminal, a complementary input terminal, an output terminal, a complementary output terminal and a voltage control terminal, the input terminal and the complementary input terminal of the first delay unit electrically connected to the complementary output terminal and the output terminal of the third delay unit, the input terminal and the complementary input terminal of the second delay unit electrically connected to the complementary output terminal and the output terminal of the first delay unit, the input terminal and the complementary input terminal of the third delay unit electrically connected to the complementary output terminal and the output terminal of the second delay unit, and the control voltage applied to the voltage control terminal of each delay unit to control the delay time between the input and the complementary input terminals, and the output and the complementary output terminals of each delay unit, wherein each delay unit comprises: a first MOS FET of which the source is electrically connected to a power source; a second MOS FET of which the source is electrically connected to the power source, the gate is electrically connected to the drain of the first MOS FET, and the drain is electrically connected to the gate of the first MOS FET; a first load device, both terminals of which are electrically connected to the source and the drain of the first MOS FET, respectively; a second load device, both terminals of which are electrically connected to the source and the drain of the second MOS FET, respectively; a third MOS FET of which the source is electrically connected to the power source, the drain is electrically connected to the drain of the first MOS FET, and the gate serves as the input terminal of each delay unit; a fourth MOS FET of which the source is electrically connected to the power source, the drain is electrically connected to the drain of the second MOS FET, and the gate serves as the complementary input terminal of the delay unit; a first current source having a first terminal, a second terminal and a control terminal for generating a current proportional to the control voltage between the first terminal and the second terminal, the first terminal electrically connected to the drain of the first MOS FET, the second terminal electrically connected to ground, and the control terminal serving as the voltage control terminal for receiving the control voltage; and a second current source having a first terminal, a second terminal and a control terminal for generating a current proportional to the control voltage between the first terminal and the second terminal, the first terminal electrically connected to the drain of the second MOS FET, the second terminal electrically connected to ground, and the control terminal serving as the voltage control terminal for receiving the control voltage.