Patent Document ID: 8479130
Application ID: 13607787
Patent Flag: 1

Claim One:
1. A method of designing a semiconductor integrated circuit (‘IC’), including: providing a library of standard cells each having respective definitions of inter-connected devices and pins for connection to other cells and/or ports, the library containing layout and performance data for respective cells; providing a device activity file (DAF) of electrical activity of devices in the respective standard cells as a function of electrical activity at the pins of the standard cells; providing a standard cell evolution file (SCEF) evolution of electrical characteristics of respective standard cells as a function of aging evolution of electrical characteristics of devices in the standard cells; providing an instance activity file (IAF) simulating electrical activity at the pins of individual instances of the cells in the IC; using said IAF and said DAF to provide a simulation of activity of said devices in the IC and consequent aging evolution of electrical characteristics of said devices; using said SCEF and said simulation of consequent aging evolution of electrical characteristics of said devices to generate data for consequent aging evolution of electrical characteristics of said instances; using said data for consequent aging evolution of electrical characteristics of said instances to generate data for consequent aging evolution of electrical characteristics of the IC, wherein generating data for consequent aging evolution of electrical characteristics of said instances includes generating a schematic view of aged instances corresponding to a schematic view of fresh instances and using said schematic view of the aged instances in generating data for consequent aging evolution of electrical characteristics of the IC, wherein said generating the consequent aging evolution data is performed by a computer; and wherein simulating said electrical activity in said IAF includes providing numbers of electrical switching and of mark-to-space ratios at the pins of individual instances of the cells in the IC.