Patent Document ID: 20020099748
Application ID: 09891203
Patent Flag: 0

Claim One:
1. A processing apparatus which performs a preconditioning process for an iteration method used to solve simultaneous linear equations through performing multilevel block incomplete factorization, comprising: a coefficient storage unit storing a coefficient matrix at a certain level in the block incomplete factorization; a determination unit determining a set of variable numbers of variables to be removed so that a block matrix comprising elements, which have the variable numbers of the variables to be removed as row numbers and column numbers, of the coefficient matrix stored in said coefficient storage unit can be diagonal dominant; a set storage unit storing information about the determined set of variable numbers; an inverse matrix unit obtaining an approximate inverse matrix of the block matrix according to the information stored in said set storage unit; a coefficient matrix unit obtaining a coefficient matrix at a coarse level from a block matrix comprising elements, which have variable numbers of remaining variables as row numbers and column numbers, of the coefficient matrix stored in said coefficient storage unit; a factorization unit storing the coefficient matrix at the coarse level in said coefficient storage unit to perform subsequent block incomplete factorization; and a computation unit computing a matrix-vector product in the iteration method using the approximate inverse matrix.