Patent Document ID: 4622648
Application ID: 06732125
Patent Flag: 1

Claim One:
1. A logic circuit including as its basic element PASS transistors wherein each PASS transistor comprises an input lead, an output lead and a control lead for controlling the transmission of signals from said input lead to said output lead, said logic circuit comprising: an output node; and a plurality of PASS transistors connected to receive a first input function, a second input function and a third input function supplied to said input leads and to receive a plurality of selected control signals applied to said control leads of said PASS transistors; where said first, second and third input functions are a reference voltage VSS, a supply voltage VDD and a carry variable C.sub.i+1, said carry variable C.sub.i+1 input function being supplied to said input leads of two of said PASS transistors, said VSS and said VDD input functions being separately supplied to said input leads of two other of said PASS transistors, and said selected control signals are input variables to be added, A.sub.i, B.sub.i, said selected control signals, along with their complements A.sub.i and B.sub.i, being supplied to said control leads of said transistors, said input functions and said selected control signals being selectively combined in said PASS transistors, to produce a full adder carry out function at said output node.