Patent Document ID: 5519854
Application ID: 08303325
Patent Flag: 1

Claim One:
1. Apparatus for processing data, said apparatus being selectably operable at one of an internal clock frequency and an external clock frequency, said internal clock frequency being asynchronous with said external clock frequency, said apparatus comprising: (i) means for generating write request signals, said write request signals comprising internal clock write request signals at said internal clock frequency and external clock write request signals at said external clock frequency; (ii) an internal clock write request signal buffer for buffering one or more internal clock write request signals to be written from said internal clock write request buffer at said external clock frequency; (iii) a synchroniser operable following generation of an internal clock write request signal to impose a minimum delay between receipt of said internal clock write request signal by said internal clock write request signal buffer and writing of said internal clock write request signal from said internal clock write request signal buffer at said external clock frequency; (iv) a signal bus for passing said external clock write request signals from said means for generating to an external receiver operating at said external frequency and for passing said internal clock write request signals from said internal clock write request signal buffer to said external receiver operating at said external clock frequency after said synchroniser has imposed said minimum delay; and (v) means for inhibiting passing of any external clock write request signals via said signal bus while said internal clock write request signal buffer is buffering any internal clock write request signals.