Patent Document ID: 4397029
Application ID: 06235213
Patent Flag: 1

Claim One:
1. Equalizer apparatus comprising: a number of successively coupled lattice stages, each of said stages comprising a selected configuration of adjustable electrical components, the input to the first stage of said successively coupled lattice stages comprising the output of a data transmission channel; error generating means coupled to said lattice stages for providing a succession of error terms, each of said error terms comprising an accumulation of error quantities, each of said error terms representing the difference between an undistorted training signal, in a sequence of undistorted training signals which are received by said error generating means, and the same training signal after it has traveled through said data transmission channel and been received by said lattice stages; and component adjust means for iteratively adjusting said electrical components in response to said training signals, said error generating means providing an error term which is within a prespecified limit when said components are iteratively adjusted in response to the final training signal in said sequence.