Patent Document ID: 20100037192
Application ID: 12534970
Patent Flag: 0

Claim One:
1. A delay analyzing apparatus for analyzing a delay that occurs in a plurality of paths between flip-flops in a logic circuit of semiconductor integrated circuit, comprising: a delay calculation unit that performs delay calculation and generates a delay calculation result based upon wiring and layout information with respect to the logic circuit; a delay analyzing unit that performs delay analysis about statistic analysis for each delay results, and generates delay analysis results for the plurality of paths by adding delay information with respect to logic elements and flip-flops included in the logic circuit based upon the delay calculation results, and by multiplying the sum thus calculated by a predetermined scattering coefficient that corresponds to the semiconductor integrated circuit; a delay analysis result sorting unit that stores the delay analysis results for the plurality of paths in order of the maximum delay, thereby generating a maximum delay sorting result; a probability density path calculation unit that generates probability density functions for a plurality of paths between the flip-flops based upon a predetermined condition by repeatedly performing processing in which a path is selected from among the plurality of paths in order of the maximum delay based upon the maximum delay sorting result, and a probability density function is generated for the path thus selected between the flip-flops; and a statistical maximum value calculation unit that performs statistical maximum value calculation for the probability density functions for all the paths between the flip-flops thus generated.