Patent Document ID: 4602210
Application ID: 06687357
Patent Flag: 1

Claim One:
1. A testable digital integrated circuit chip having input and output pins, respectively, comprising (a) a plurality of bistable circuit elements; (b) a plurality of combinational circuit elements; (c) first means operable in a mission mode for connecting said bistable and combinational circuit elements to define mission logic means having input and output ends; (d) second means operable in a test mode for connecting groups of said bistable elements in series to define a plurality of serial scan paths isolated from said combinational circuit elements, each of said scan paths having input and output ends; (e) first level demultiplexer means having outputs connected with the input ends of said serial scan paths, respectively, said first demultiplexer means having input means; (f) second level demultiplexer means having first outputs connected with said first demultiplexer input means, respectively, and second outputs connected with the input end of said mission logic functions, respectively, said second demultiplexer means having input means connected with the chip input pins; (g) first level multiplexer means having a plurality of inputs connected with the output ends of said scan paths, respectively, said first multiplexer means having output means; (h) second level multiplexer means having first inputs connected with the first multiplexer output means, respectively, and a second set of inputs connected with the output ends of said mission logic functions, respectively, said second multiplexer means having output means connected with the chip output pins; (i) mode control means for operating said demultiplexing and multiplexing means to switch said integrated circuit between said mission and test modes; (j) means for applying a test signal to said input pins when said integrated circuit is in the test mode; and (k) means for monitoring the resultant test signal appearing at the integrated circuit output pins.