Patent Document ID: 9779786
Application ID: 15334746
Patent Flag: 1

Claim One:
1. A system comprising: global memory circuitry configured to store input tensors and output tensors; row data paths, each row data path connected to an output port of the global memory circuitry; column data paths, each column data path connected to an input port of the global memory circuitry; processing elements arranged in rows and columns along the row data paths and column data paths, respectively, the processing elements including: local memory circuitry configured to store multiple masks; processing circuitry configured to: receive portions of the input tensors from one of the row data paths at a first rate; receive masks from the local memory circuitry at a second rate that is faster than the first rate; perform multiple tensor operations on a same received portion of the input tensors by applying a different retrieved mask for each tensor operation; and generate, using results of the multiple tensor operations, an output from a processing element for a corresponding column data path.