Patent Document ID: 6167364
Application ID: 09153754
Patent Flag: 1

Claim One:
1. A method for generating circuit parameters for a plurality of interconnect line circuit models, the plurality of circuit models representing a plurality of interconnect lines in a programmable logic device (PLD), the method comprising: generating design description data corresponding to the PLD at least in part from interconnect line data representing the plurality of interconnect lines; generating a device model for the PLD using estimated circuit parameters and a plurality of mathematical equations representing the plurality of interconnect line circuit models; simulating operation of the PLD using the device model and the design description data thereby generating modeled delay data corresponding to the estimated circuit parameters; comparing the modeled delay data with measured delay data corresponding to the plurality of interconnect lines; and where all of the modeled delay data are within an error limit of corresponding measured delay data, designating the estimated circuit parameters as the circuit parameters.