Patent Document ID: 20100269078
Application ID: 12425597
Patent Flag: 0

Claim One:
1. A method to verify a circuit design by determining whether the circuit design satisfies a set of assertions when a first set of assumptions is satisfied, wherein the set of assertions models a desired behavior of the circuit design, and wherein the set of assumptions specifies logical functions which are expected to be satisfied during normal circuit operation, the method comprising: simplifying the first set of assumptions to obtain a second set of assumptions which is logically equivalent to the first set of assumptions; associating a first subset of assumptions with an assertion in the set of assertions, wherein the first subset of assumptions is a subset of the second set of assumptions; modifying the first subset of assumptions to obtain a second subset of assumptions which is not logically equivalent to the first subset of assumptions; and verifying the circuit design by at least determining whether the circuit design satisfies the assertion when the second subset of assumptions is satisfied.