Patent Document ID: 7554847
Application ID: 11730291
Patent Flag: 1

Claim One:
1. A flash memory device, comprising: a memory cell array comprising a plurality of NAND strings respectively connected to a plurality of bit lines, and further comprising first and second disturbed strings respectively coupled to first and second disturbed bit lines, wherein each of the plurality of NAND strings comprises a plurality of memory cells and each of the first and second disturbed strings comprises a plurality of memory cells; a row selector adapted to drive word lines respectively connected to the plurality of memory cells within each of the plurality of NAND strings and within the first disturbed string; a page buffer circuit electrically connected to the bit lines and the first and second disturbed bit lines; a bias circuit configured to drive a common gate line connected to the memory cells in the second disturbed string; and a controller configured to control operation of the row selector, the page buffer circuit, and the bias circuit; wherein during a program operation, the controller operates to control the page buffer circuit and the bias circuit such that one or more memory cells in the first disturbed string assume states indicative of program voltage disturbance and one or more memory cells in the second disturbed string assume states indicative of pass voltage disturbance.