Patent Document ID: 6099580
Application ID: 09021973
Patent Flag: 1

Claim One:
1. A method for optimizing a layout design based on a first gate-level design, comprising: (a) partitioning circuit elements of said first gate-level design into a first plurality of clusters; (b) mapping each cluster to a portion of said layout design so as to obtain a placement; (c) based on said placement, providing routing or routing estimates between circuit elements of each cluster and between circuit elements of different clusters; (d) based on said routing or routing estimates, performing a timing analysis to provide estimates of interconnect delays between circuit elements within each cluster and between circuit elements of different clusters; (e) performing a logic optimization operation on a selected one of said clusters to obtain a second gate-level logic design based on a cost function, said cost function being a function of said estimates of interconnect delays; (f) partitioning said second gate-level logic design to obtain a second plurality of clusters; and (g) repeating (b)-(f) until said cost function is less than a predetermined value.