Patent Document ID: 8463589
Application ID: 12159831
Patent Flag: 1

Claim One:
1. A method of transforming a transformable virtual processor model to a user virtual processor model to simulate a user target processor, the method comprising: receiving a transformable virtual processor model, the transformable virtual processor model configured to perform, on a host processor system, a behavior and timing accurate simulation of a seed target processor, the transformable virtual processor model having a transformable instruction set and a transformable pipeline; receiving one or more user-provided descriptions of the user target processor, wherein the one or more user-provided descriptions includes a description of a new instruction, including a description of an opcode pattern for a decoder part of the user virtual processor model to select the new instruction, a description of behavior for a functionality of the new instruction, and a description of timing of the new instruction; and transforming the received transformable virtual processor model to the user virtual processor model, wherein the user virtual processor model is configured to perform, on the host processor system, a behavior and timing accurate simulation of the user target processor according to the user-provided descriptions by performing at least one of: adding the new instruction associated with the user virtual processor model to the transformable instruction set; modifying a definition of one or more instructions in the transformable instruction set according to the user virtual processor model; and modifying a processor structure of the transformable virtual processor model by performing at least one of: adding an additional pipeline associated with the user virtual processor model to the transformable virtual processor model; and modifying the transformable pipeline of the transformable virtual processor model according to the user virtual processor model; wherein the user target processor is to be simulated using binary translation of target code associated with the user virtual processor model into host code associated with the host processor system, including caching translated target code for re-use during simulation of the user target processor, and wherein at least one of the receiving, and transforming is performed by a processor.