Patent Document ID: 10073934
Application ID: 15290362
Patent Flag: 1

Claim One:
1. A computerized method for timing analysis of a circuit design, the method comprising: determining from at least a design file associated with the circuit design, using one or more hardware processors, an input slew and an output load for a timing path of the circuit design; accessing, using the one or more hardware processors, a first set of statistical values associated with at least a skewness value and a standard deviation value generated from a timing delay probability distribution function (PDF) of a first element of the circuit design, the timing delay PDF having an asymmetric distribution, wherein the first set of statistical values comprises a normalized skewness value which is a normalized cube-root of skewness calculated as: γ normalized = E ⁡ [ ( D ⁡ ( x ) - μ ) 3 ] 3 Var ⁡ [ D ⁡ ( x ) ] for the first PDF D(x), variance function Var, mean value function E, and a mean shift value μ; scaling, using the one or more processors, the standard deviation value and the skewness value for a bound of the timing delay PDF to generate a first scaled timing delay value for the bound; and calculating, using the one or more processors, a first timing value based on the first scaled timing delay value; wherein the timing analysis and circuit design is provided for fabricating semiconductor devices.