Patent Document ID: 5500823
Application ID: 08221074
Patent Flag: 1

Claim One:
1. In a semiconductor integrated circuit static random access memory including a plurality of memory cells arranged in rows and columns, each memory cell comprising respective first and second inverters, and respective first and second bit lines associated with each column of said memory cells, a testing arrangement for defects in individual said inverters comprising: means for applying to each of the memory cells of a column a supply voltage selectively of a first or normal operating supply voltage value and a second or test supply voltage value lower than said first value; means selectively for applying a sequence of test signal voltages to said first bit line associated with the column of memory cells; detector circuit means; and means operatively connected to said detector circuit means, and operative for selectively connecting said second bit line associated with said column of memory cells to apply to said detector circuit means any change in signal voltage on said second bit line in response to said sequence of test signal voltages.