Patent Document ID: 7934134
Application ID: 12133830
Patent Flag: 1

Claim One:
1. A method for performing a logic built-in self-test (LBIST) on an integrated circuit, said method comprising: performing a flush and scan test on an integrated circuit having functional combinational logic and a plurality of scan chains selectively driven by design-for-test logic for supporting LBIST, to determine whether or not each of said plurality of scan chains functions correctly; in response to a determination that one of said plurality of scan chains does not function correctly, terminating said LBIST; in response to a determination that each of said plurality of scan chains functions correctly, performing a structural test on said design-for-test logic to determine whether or not said design-for-test logic functions correctly; in response to a determination that said design-for-test logic does not function correctly, terminating said LBIST; in response to a determination that said design-for-test logic functions correctly, performing a level sensitive scan design (LSSD) test on said functional combinational logic using said design-for-test logic to determine whether or not said integrated circuit functions correctly.