Patent Document ID: 7797648
Application ID: 11480235
Patent Flag: 1

Claim One:
1. A computer implemented method for performing word-level ATPG justification on a target circuit, the target circuit comprising one or more control signals, comprising: providing a representation of a circuit, the representation comprising a control logic component and a datapath logic component; reading one or more vector generation targets; performing word-level ATPG justification on the control logic component to obtain a control logic solution, wherein the act of performing word-level ATPG justification on the control logic component comprises: identifying an internal control signal of the target circuit; making a decision on the identified internal control signal; performing word-level implication on one or more circuit components related to the target circuit; determining if a conflict arises from the word-level implication; and determining if the internal control signal is justified; extracting one or more arithmetic functions for the datapath logic component based on the control logic solution; solving the one or more arithmetic functions using a modular constraint solver, the modular constraint solver being based on a modular number system, wherein the act of solving the one or more arithmetic functions is performed by a processor; and displaying a result of the act of solving the one or more arithmetic functions using a modular constraint solver on a display apparatus or storing the result in a tangible and non-transitory computer readable storage medium.