Patent Document ID: 4849925
Application ID: 07144141
Patent Flag: 1

Claim One:
1. A circuit comprising: a plurality of n amplifiers, called variable plane amplifiers, the outputs of respective ones of said variable plane amplifiers being V.sub.1 through V.sub.n, said V.sub.1 through V.sub.n being the elements of a vector V; a plurality of m amplifiers, called constraint plane amplifiers; a plurality of transconductances D.sub.ji interconnecting various inputs and outputs of said amplifiers, the values of the elements of said plurality of transconductances being arrangable in an mxn matrix D; a plurality of inputs A.sub.1 through A.sub.n to respective ones of said variable plane amplifiers, said A.sub.1 through A.sub.n being the elements of vector A; a plurality of inputs B.sub.1 through B.sub.m to respective constraint plane amplifiers, said B.sub.1 through B.sub.m being the elements of vector B; a plurality of n impedances, each of said n impedances connected to the input of a respective one of said n variable plane amplifiers, the real portion of each said n impedances being respectively R.sub.1 through R.sub.n ; said circuit being adapted to have a total circuit energy E according to: ##EQU15## where D.sub.j is the jth column vector of said D, and EQU F(0)=0, and F&gt;0 for z.noteq.0; wherein said circuit is adapted to reduce said circuit energy E to: ##EQU16##