Patent Document ID: 10060976
Application ID: 15151263
Patent Flag: 1

Claim One:
1. An automatic test pattern generation (ATPG) method, the method comprising: generating, with a first circuit simulator, a plurality of test patterns, wherein the first circuit simulator is based on a structural model; simulating, with a second circuit simulator, the plurality of test patterns, wherein the second circuit simulator is based on a behavioral model; validating, with the second circuit simulator, the plurality of test patterns by comparing the plurality of test patterns to the simulated plurality of test patterns; and upon determining a mis-compare between the plurality of test patterns and the simulated plurality of test patterns during the validating, identifying an origin of the mis-compare through diagnosis, with a processor, of the plurality of test patterns and the simulated plurality of test patterns, wherein the diagnosis comprises: determining, with the processor, (i) a test pattern of the plurality of test patterns including the mis-compare and (ii) a first logical event of the test pattern, wherein the first logical event includes the mis-compare; simulating, with the first circuit simulator, the test pattern including the mis-compare, wherein the test pattern is simulated until the first logical event is reached; performing, with the processor, a back-cone logical trace on a measurable latch associated with the mis-compare; and determining, with the processor, a plurality of pins of an integrated circuit chip in a back-cone of the measurable latch based on the back-cone logical trace, wherein the origin of the mis-compare is identified based on the determined plurality of pins.