Patent Document ID: 8560906
Application ID: 13285899
Patent Flag: 1

Claim One:
1. A method of generating test patterns for testing an integrated circuit, comprising: identifying two or more possible fault activation conditions in an integrated circuit design, the possible fault activation conditions being capable of activating a targeted delay fault at a fault site through a gate in the integrated circuit design; selecting one of the possible fault activation conditions using a weighted random selection procedure in which the weight w i for a respective possible fault activation condition I in the weighted random selection procedure corresponds to either: w i = AT i s ∑ i = 1 n ⁢ AT i s , ( a ) where n is the number of possible fault activation conditions, i is an index value, and AT i s is the longest static arrival time to the ith choice to justify the gate; or w i = 1 HAT i s ∑ i = 1 n ⁢ 1 HAT i s , ( b ) where n is the number of possible fault activation conditions, i is an index value, and HAT i s is the shortest static arrival time to the ith choice to justify the gate; generating test pattern values that activate the targeted delay fault at the fault site with the selected fault activation conditions; and storing the test pattern values.