Patent Document ID: 20030145263
Application ID: 10058485
Patent Flag: 0

Claim One:
1. A method of testing a combinational and sequential logic circuit with shift register latches of individual logic units coupled together to form a shift register scan path for testing logic circuits and uncoupled to disable the scan path while the logic circuit is performing its designed logic fiction, a method for reducing the heating of the circuit elements during testing comprising: (a) dividing the circuits at least into two group cores; (b) performing simulation testing by shifting a plurality of pseudo random pulse patterns through at least one of the cores to detect faults in said at least one of the cores; (c) simultaneously performing simulation testing in other of said at least two cores using a weighted pseudo-random pulse pattern with the weighting selected to maintain the heating of the circuits below acceptable limits; and (d) changing switching the cores subjected to the testing of the pseudo-random and the weighted pseudo-random test patterns so that pseudo-random and weighted pseudo-random test patterns are applied to all cores.