Patent Document ID: 8477888
Application ID: 12145322
Patent Flag: 1

Claim One:
1. A method comprising: evaluating an in-phase noise variance for a pilot signal in the presence of a phase noise by a processor of an electronic device; evaluating a quadrature noise variance for the pilot signal in the presence of the phase noise by the processor; and estimating a net noise variance for the pilot signal based at least in part on the evaluated in-phase noise variance or the evaluated quadrature noise variance by the processor, wherein estimating a net noise variance for the pilot signal based at least in part on the evaluated in-phase noise variance or the evaluated quadrature noise variance comprises combining the evaluated in-phase noise variance and the evaluated quadrature noise variance by: computing a running average (<N (I) >) of a set of in-phase noise variance estimates; computing a running average (<N (Q) >) of a set of quadrature noise variance estimates; assigning <N (I) > to the net noise variance estimate when a ratio of <N (Q) > to <N (I) > is greater than a threshold; and assigning a weighted average of <N (Q) > and <N (I) > to the net noise variance estimate when the ratio of <N (Q) > to <N (I) > is one of lower than or equal to the threshold.