Patent Document ID: 20030177453
Application ID: 10098136
Patent Flag: 0

Claim One:
1. A method of optimizing speed and predicted power consumption of a design for an integrated circuit, the design for an integrated circuit comprising at least one path further comprising at least one gate, the method comprising the steps of: creating a parent state representing devices of the integrated circuit design, where for each device in a path of the integrated circuit the state further comprises device size information and device type information, where the device type information further comprises selection between at least one fast-but-leaky type and at least one slow-but-not-leaky type; creating a population of individual states from at least one parent state; scoring individual states of the population for timing and power dissipation to create a score for each individual state; selecting survivor individual states of the population based upon their scores; iterating the steps of creating a population, scoring individual states, and selecting survivor individual states, where the survivor individual states of each iteration become parent states of the next iteration; and selecting a best individual survivor state as an optimized state and updating the integrated circuit netlist therefrom.