Patent Document ID: 20160188295
Application ID: 14584948
Patent Flag: 0

Claim One:
1. A multi-precision Single Instruction Multiple Data (SIMD) multiply unit comprising: a carry save adder (CSA) configured to obtain based, in part, on a plurality of partial products of a first multiplier operand and a second modified booth encoded multiplicand operand, a first partial result and a second partial result; and an addition module coupled to the CSA, the addition module comprising: a full adder to obtain an intermediate sum result and an intermediate carry result by adding the first partial result and second partial result to a third operand, and a first carry lookahead adder (CLA) to operate on integer and fixed point operands and coupled to the full adder, the first CLA to add the intermediate sum result and the intermediate carry result, wherein the first CLA comprises, in addition to columns for bits in the intermediate sum result and intermediate carry result, one or more additional columns, wherein each additional column comprises bit values that: prevent carry propagation across the additional column, or propagate carries across the additional column, wherein, a determination to propagate carries, or to prevent carry propagation across each of the one or more additional columns is based, in part, on a current instruction being executed by the arithmetic unit, a number of concurrent operations specified in the current instruction, and a precision of the current instruction.