Patent Document ID: 8136076
Application ID: 12439132
Patent Flag: 1

Claim One:
1. A system for generating configuration data for reconfiguring a reconfigurable device, wherein the device includes a plurality of processing elements and a routing matrix for connecting the plurality of processing elements and is reconfigured by changing functions of respective processing elements in the plurality of processing elements and/or changing at least some connections of the routing matrix, the plurality of processing elements are divided into a plurality of groups, processing elements included in each group are connected in a range of a first delay by a first-level routing matrix included in the routing matrix, and processing elements included in different groups are connected with a different delay to the first delay via a second-level routing matrix included in the routing matrix, and the system comprises: a database for storing hardware information that includes definition data for the plurality of processing elements included in respective groups and definition data for the routing matrix; and a mapping apparatus that is generative a mapping of a circuit design onto the plurality of processing elements for implementing the circuit design in the device by the configuration data, wherein the mapping apparatus generates the mapping of the circuit design onto the plurality of processing elements by carrying out an iterative algorithm that minimizes a cost function based on the hardware information, the cost function including an item that minimizes usage of the second-level routing matrix, wherein the circuit design includes a data flow graph in which functions to be implemented in the device are expressed as a plurality of functional blocks that are capable of being implemented in processing elements out of the plurality of processing elements and connections between the plurality of functional blocks, the plurality of functional blocks including a plurality of types of functional block, and the plurality of processing elements including a plurality of types of processing element that configurable respectively correspond to restricted types of functional block out of the plurality of types of functional block, and wherein the mapping apparatus includes: a functional unit that provisionally assigns the plurality of functional blocks to processing elements out of the plurality of processing elements divided into the plurality of groups, and includes a function that assigns the plurality of functional blocks with priority given to a type of processing element with a low number of elements included in the plurality of processing elements out of the plurality of types of processing element, and when doing so, assigns a plurality of functional blocks that can be assigned to a plurality of processing elements of a first type randomly to the plurality of processing elements of the first type; and a functional unit that changes assignments of the plurality of functional blocks to the plurality of processing elements using the iterative algorithm, and includes a function that finds a value of the cost function based on a route that connects a plurality of assigned processing elements that have been respectively assigned the plurality of functional blocks.