Patent Document ID: 7882473
Application ID: 11945465
Patent Flag: 1

Claim One:
1. A method, in a data processing system, for performing asynchronous verification of an integrated circuit design, comprising: receiving a first model of the integrated circuit design; unfolding paths within the first model that have asynchronous crossings to generate an unfolded integrated circuit design model; inserting asynchronous crossing logic into the unfolded integrated circuit design model to generate a second model; correlating outputs of the first model with outputs of the second model; applying one or more exclusive OR operations to the correlated outputs of the first model and the second model; and performing, by the data processing system, sequential equivalence checking on the first model and second model utilizing the applied one or more exclusive OR operations, wherein the asynchronous crossing logic comprises skewing logic for selecting a phase difference between clocks of asynchronous domains of asynchronous crossings in the unfolded integrated circuit design.