Patent Document ID: 7735047
Application ID: 11998337
Patent Flag: 1

Claim One:
1. A processor-implemented method for technology mapping a logic network onto programmable logic resources of a programmable integrated circuit, the method comprising: determining respective Boolean flexibility values for a plurality of functionally equivalent mappings of the logic network onto the programmable logic resources; wherein the determining respective Boolean flexibility values includes counting, for one or more programmable logic resources in each mapping, a number of functionally equivalent options of the one or more programmable logic resources in the mapping, and the respective Boolean flexibility value is at least in part a function of the number of functionally equivalent options; selecting one of the mappings as a function of the respective Boolean flexibility values; and storing the selected mapping in an electronic storage device wherein the determining respective Boolean flexibility values comprises determining the functionally equivalent options for each functionally equivalent mapping, and placing a value on one or more characteristics of the functionally equivalent options.