Patent Document ID: 9225591
Application ID: 14637238
Patent Flag: 1

Claim One:
1. A method implemented by a network topology design system including a processing device, the method comprising the steps of: graphing, by the processing device, a topology of a network with a split architecture as a graph G=(V, E), wherein the split architecture network contains control plane components and data plane components, where the control plane components of the split architecture network are executed by a controller and the control plane components are separate from the data plane components of the split architecture network, with links in the split architecture network represented as a set of bidirectional edges (E) in the graph and network elements in the split architecture network represented as a set of nodes (V) in the graph; traversing, by the processing device, the set of nodes within the graph to calculate a protection metric for each node, wherein the protection metric measures resilience of the split architecture network as a degree of node failure protection within the split architecture network for a potential controller placement, the degree of node failure protection based on determining a subset of protected nodes in the set of nodes, where a protected node in the subset of protected nodes is capable of redirecting control traffic over a tunnel to an intermediate node in the graph that is not downstream of the protected node, and where the tunnel traverses at least one downstream node of the protected node, the tunnel for carrying encapsulated control traffic to the intermediate node that is to be de-capsulated by the intermediate node and forwarded to the controller by the intermediate node; and selecting, by the processing device, a network element corresponding to a node with a best protection metric to be the controller for the split architecture network to minimize disruption of the split architecture network caused by a link failure, a switch failure or a connectivity loss between the controller and the data plane components.