Patent Document ID: 9792397
Application ID: 15499832
Patent Flag: 1

Claim One:
1. A computer implemented method comprising computer-readable instructions stored on a non-transitory computer readable medium and executed on a computing device comprising a hardware processor and a memory for chip designing using Artificial intelligence with reinforcement learning technique, the method comprising: receiving a SoC specification input; initializing a chip design by extracting details regarding chip, chip skeleton, clock, Input outputs, partitions that are retrieved from the received SoC specification input and a chip database library; creating a plurality of domains and a plurality of subdomains artificial intelligence (AI) setup in form of Markov Decision Process (MDP), Semi Markov Decision Process (SMDP)s, Hierarchical Abstract Machines (HAM)s and MAX-Q to generate chip specific graph library, and wherein the artificial intelligence setup comprises a combination of an AI agent, an AI environment, and a task, wherein the AI setup is created using pre-defined exploration and exploitation algorithms, and reinforcement learning techniques; generating Q values for each domain using AI agent, wherein the AI agent is configured to interact with AI environment through task to extract Q values for each domain; storing the extracted Q values of each domain and subdomain in a hierarchical SMDP structure in a form of SMDP Q table in a big data database for optimization for planning SoC; acquiring optimal chip architecture corresponding to a maximum Q value of a top level in the SMDP Q table; storing the optimal chip architecture in a database for learning and inference; and optimizing and generating desired SoC configuration based on the optimal chip architecture and the generated chip specific graph library.