Patent Document ID: 20050143966
Application ID: 11058859
Patent Flag: 0

Claim One:
1. A method for simulating analog behavior of a circuit in a simulation system, comprising: representing the circuit as a hierarchically arranged set of branches, including a root branch and a plurality of other branches logically organized in a graph; the hierarchically arranged set of branches including a first branch that includes one or more subcircuits and a second branch that includes one or more subcircuits; wherein the first branch and second branch are interconnected in the graph through a third branch at a higher hierarchical level in the graph than the first and second branches; determining whether the one or more subcircuits having states substantially equivalent to one another; selecting an appointed leader for representing behaviors of the one or more subcircuits having states substantially equivalent to one another, wherein the appointed leader conforms to a set of predefined criteria, and wherein the remaining one or more subcircuits having states substantially equivalent to one another are deemed as followers; simulating analog behavior of the appointed leader; and replicating simulation results of the appointed leader to the followers.