Patent Document ID: 9231887
Application ID: 13777725
Patent Flag: 1

Claim One:
1. A system, comprising: a memory to store computer-executable components; and a processor, coupled to the memory, that executes or facilitates execution of at least one of the computer-executable components, the computer-executable components comprising: a switch component that comprises multiple stages of switches and intermediate-stage shared buffering of packets of information to facilitate communication of the packets in a communication network, wherein the switch component comprises an input component comprising a set of input switches associated with an input stage of the multiple stages, an intermediate component comprising a set of switches associated with an intermediate stage of the multiple stages, and an output component comprising a set of output switches associated with an output stage of the multiple stages; and a memory component that comprises a set of memory sub-components and is associated with the intermediate component of the intermediate stage, wherein memory sub-components of the set of memory sub-components are shared with the set of input switches of the input component and the set of output switches of the output component to facilitate buffering of the packets via the intermediate-stage shared buffering and scheduling of the packets for output from the switch component, wherein an unmatched memory sub-component of the set of memory sub-components selects an unmatched communication link of a set of unmatched communication links associated with an intermediate module of a first set of intermediate modules that is linked to the unmatched memory sub-component, and sends a request for use of the unmatched communication link to the unmatched communication link, in accordance with a defined scheduling criterion.