Patent Document ID: 5471596
Application ID: 08338267
Patent Flag: 1

Claim One:
1. A memory device in a computing system, said memory device holding a data structure for allowing a processor to adapt a specified function, said function requiting a specified set of data for execution, to one or more input interfaces and one or more output interfaces, the data structure comprising: (a) an operational data structure, the operational data structure containing said specified set of data; (b) a pointer to the operational data structure; (c) one or more machine executable input routines for obtaining at least a portion of said set of data, each input routine receiving as an argument the pointer to the operational data structure and each input routine configured to receive data through a particular input interface; (d) one or more machine executable output routines for outputting at least a portion of said set of data, each output routine receiving as an argument the pointer to the operational data structure and each output routine configured to output data through a particular output interface; (e) respective pointers to each input and output routine; (f) a variant number; and (g) a routine matrix array having at least one entry, wherein each entry associates (1) a pointer to a specified input routine with (2) a pointer to a specified output routine, the variant number serving as an index into the routine matrix array for selecting the entry.