Patent Document ID: 7590952
Application ID: 11563704
Patent Flag: 1

Claim One:
1. A computer implemented method for reducing a chip package model, the computer implemented method comprising: responsive to receiving the chip package model, creating an inductor model of the chip package model and a resistor model of the chip package model, using a computer; measuring a plurality of inductance node voltages of the inductor model of the chip package model, wherein the inductance node voltages are measured using only a set of external nodes of the inductor model of the chip package model, and wherein the measured inductance node voltages are used to form a reduced node inductance matrix; measuring a plurality of resistance node voltages of the resistor model of the chip package model, wherein the resistance node voltages are measured using only the set of external nodes of the resistor model of the chip package model, and wherein the measured resistance node voltages are used to form a reduced node resistance matrix; creating a reduced node inductor model and a reduced node resistor model from the inductance matrix and the resistance matrix, respectively; and combining the reduced node resistor model and the reduced node inductor model to form a combined reduced node resistor-inductor chip package model.