Patent Document ID: 7689957
Application ID: 11853009
Patent Flag: 1

Claim One:
1. A method of generating circuits in a design flow for an implementation process, the method comprising: receiving library data for a design including timing models; defining a robust circuit based on at least one of worst negative slack and total negative slack as well as at least one of endpoint slack distribution and number of timing constraint violations; and using statistical timing analysis, by processor, to drive logic changes that generate improved robust circuits in the design, wherein the statistical timing analysis models a statistical delay distribution on an arc of the design in static timing analysis, and wherein the statistical delay distribution on the arc includes: using a static timing delay associated with the arc in statistical timing analysis as a mean; and using a specified percentage of the mean as the standard deviation, wherein the specified percentage is obtained from one of an estimate of a clock budget for variations and an estimate of delay variations on a gate.