Patent Document ID: 6012836
Application ID: 08760550
Patent Flag: 1

Claim One:
1. A computer operable method for increasing the efficiency of computer code generated by a circuit compiler for simulating the response of a synchronous digital logic circuit, comprising the steps of: (a) providing said circuit compiler with a net list having nodes and gates which describes a digital logic circuit, said net list also comprises at least a first gate having a first output node, said first output node being represented by a first output node variable, and wherein said first gate requires a first boolean logic function having a first result and a boolean complement of said first result to simulate the operation of said first gate; (b) generating computer code which simulates the operation of said first gate by storing said firs result in said first output node variable; and (c) setting a first flag associated with said first output node variable to indicate said first output node variable will be stored in a complemented form.