Patent Document ID: 7536662
Application ID: 11426936
Patent Flag: 1

Claim One:
1. A method for recognizing first-in-first-out (FIFO) structures in integrated circuit (IC) designs, comprising: identifying at least one seed in an IC design that indicates the existence of a FIFO structure; and checking locally to the identified at least one seed the existence of the FIFO structure in the IC design; wherein the seed is a logic element included in the FIFO structure; wherein the seed comprises at least one of: a memory unit, a synchronizer, an equal operator, a less-than (LT) operator, a less-than-or-equal (LTE) operator, a greater-than (GT) operator, a greater-than-or-equal (GTE) operator, or incremental operators of read and write counters; wherein the memory-seed based recognition comprises: identifying all memory units in the IC design, and for each identified memory unit, traversing forward from the memory until encountering a read pointer; traversing backward from the memory until encountering a write pointer; and traversing from the read pointer and the write pointer until encountering increment operators; and wherein the step of traversing forward further comprises: searching for select signals of multiplexers (MUXes) in a read decoder connected to the memory unit; and determining the select signal that is not an internal signal and having minimum distance from the memory unit to its MUX to be the read pointer; and /or wherein the step of traversing backward further comprises: searching for select signals of MUXes in a write decoder connected to the memory unit; and determining the select signal that is not an internal signal and having minimum distance from the memory unit to its MUX to be the write pointer.