Patent Document ID: 8726205
Application ID: 13862492
Patent Flag: 1

Claim One:
1. A method comprising: reading, through a processor of a computing device communicatively coupled to a memory, a design of an electronic circuit at a first level higher than a second level at which at least one of design verification and design simulation of the electronic circuit is to be conducted; representing instances of elements of the electronic circuit in a data structure; parsing, through the processor at the first level, the design of the electronic circuit to automatically generate a list of regular expressions related to text-matching strings with the elements of the electronic circuit based on removing undesired instances related to the elements of the electronic circuit from the data structure; pruning, through the processor at the second level, connectivity descriptors of the electronic circuit based on the automatically generated list of regular expressions at the first level; and optimizing the at least one of the design verification and the design simulation of the electronic circuit at the second level based on the pruned connectivity descriptors thereof.