Patent Document ID: 9667199
Application ID: 15178545
Patent Flag: 1

Claim One:
1. A Doherty amplifier comprising: an output combining network with N combining network inputs, multiple summing nodes, and a combining network output, wherein N is an integer greater than two, and the output combining network is configured to combine signals received at the N combining network inputs into a combined signal that is provided at the combining network output; a main amplifier path with an output coupled to a first combining network input of the N combining network inputs, wherein the main amplifier path includes a main amplifier stage and a first output matching network coupled to an output of the main amplifier stage, and wherein the first output matching network imparts a phase delay of 90 degrees and provides a single impedance inversion to a first RF signal conveyed through the main amplifier path; and N−1 peaking amplifier paths, wherein each peaking amplifier path has an output that is coupled to one of N−1 different combining network inputs of the N combining network inputs, and wherein each of the N−1 peaking amplifier paths includes a peaking amplifier stage and an output matching network coupled to an output of the peaking amplifier stage, wherein the output matching network of each of N-2 of the peaking amplifier paths imparts a phase delay of 90 degrees and provides a single impedance inversion to an RF signal conveyed through each of the N-2 peaking amplifier paths, and wherein a lowest-order peaking amplifier path is coupled to a lowest-order combining network input of the N combining network inputs, and wherein the multiple summing nodes of the output combining network include a final summing node and N-2 intermediate summing nodes, wherein the final summing node is coupled to the combining network output and is directly coupled to the first combining network input, the N-2 intermediate summing nodes each are directly coupled to a different one of N-2 other combining network inputs of the N combining network inputs, and wherein the output combining network further includes N-2 impedance transformers each coupled between different sets of adjacent summing nodes of the multiple summing nodes, and an offset line coupled between the lowest-order combining network input and a lowest-order summing node of the N-2 intermediate summing nodes.