Patent Document ID: 7714610
Application ID: 11566573
Patent Flag: 1

Claim One:
1. An integrated circuit field programmable gate array (FPGA), comprising: a plurality of logic blocks configured for performing combinational or sequential logic operations based on programming of said FPGA in response to one or more logic inputs; a plurality of programmable routing channels configured for interconnecting said logic blocks for routing input signals to said logic blocks and output signals from said logic blocks based on programming of said FPGA; a plurality of memory cells within said FPGA for configuring logic block operation and signal routing within said programmable routing channels; and supply voltage selection means for operating said logic blocks and/or switching elements within said programmable routing channels which are either or both taken from a supply voltage V dd selected from a plurality of discrete supply voltage levels; wherein said supply voltage selection means comprises transistor geometries designed within the specific blocks to operate at different voltage levels, or at same voltage levels, and inclusion of level converters for shifting from lower voltage referenced signals to higher voltage referenced signals as determined during routing and configuration of the FPGA.