Patent Document ID: 20030005393
Application ID: 10180297
Patent Flag: 0

Claim One:
1. A method for converting an RT (Register Transfer)-level model of a logic circuit block into a high abstraction-level operation model, comprising the steps of: setting one or more states of the logic circuit block as operation start states and operation end states by using input/output instruction information that represents a relation between an input/output instruction of the logic circuit block and an input/output signal corresponding to the input/output instruction; and analyzing operation of the logic circuit block, the operation analyzing step being conducted by selecting one input instruction to be analyzed from those included in the input/output instruction information, applying an input signal corresponding to the selected input instruction to the RT-level model that is in a first state selected from the operation start states, and analyzing the RT-level model and extracting an operation of the logic circuit block by varying the input signal, until the RT-level model reaches a second state of the operation end states, wherein the operation analyzing step is repeatedly conducted for at least one or all combinations of the operation start state and the input instruction included in the input/output instruction information, and the operation model of the logic circuit block is produced based on the extracted operations.