Title: AutoFloorplan: Evolving Heuristics for Chip Floorplanning with Large Language Models and Textual Gradient-Guided Repair
Primary area: optimization
Keywords: Heuristic Search, Evaluation and Analysis, Algorithm Design Automation, Chip Floorplan

Abstract: Chip floorplanning is the cornerstone of modern Very Large Scale Integration (VLSI) design, but it remains an impenetrable NP-hard combinatorial optimization problem. Designing effective heuristic algorithms to explore its large solution space under complex constraints is a challenging task that traditionally relies on rich human expertise. In this study, we propose AutoFloorplan, a novel evolutionary learning framework that automatically discovers complex floorplanning heuristics. We utilize Large Language Models (LLMs) as intelligent population generators capable of creating diverse and semantically rich heuristics expressed as code. However, a fundamental challenge is that many LLM-generated heuristics are invalid and do not conform to the strict geometric and topological constraints of floorplanning. To address this problem, we design a novel repair operator based on textual gradients. This operator analyzes the causes of inefficiencies in the generated heuristics and provides corrective feedback to steer the algorithmic structure towards effective and high-performance alternatives. Our framework significantly improves the speed of discovering legitimate and effective heuristics and iterating on algorithm performance. Extensive experiments on eight different public circuits show that AutoFloorplan outperforms current State-of-the-Art floorplanning algorithms. The code of AutoFloorplan can be found at https://anonymous.4open.science/r/AutoFloorplan-main.

TL;DR: This paper presents FloorplanEvo, an AI framework using Large Language Models to automatically generate chip floorplanning heuristics. A novel repair mechanism fixes invalid AI-generated code, creating algorithms that outperform SOTA methods.