Title: Learning A Linear Delay Surrogate Model for Timing-Driven Chip Global Placement
Primary area: applications to robotics, autonomy, planning
Keywords: Electronic Design Automation, Chip Placement, Timing-Driven Global Placement

Abstract: Timing-driven global placement (GP) is a critical step in chip physical design, where the objective is to determine the physical locations of millions of cells to optimize signal delays and satisfy timing constraints. Existing GP algorithms commonly rely on gradient-based optimization, which requires the placement objective to be differentiable with respect to cell coordinates. However, timing evaluation---particularly the delay computation---is inherently complex and typically non-differentiable, making it difficult to integrate into gradient-based GP algorithms. To address this challenge, we propose **LiTPlace**, a **L**earn**i**ng-based **T**iming-driven global placement framework, which learns a differentiable surrogate model to predict signal delays for timing-aware gradient-based optimization. To the best of our knowledge, the application of machine learning (ML) in timing-driven GP remains underexplored in previous works. At the core of LiTPlace is a graph neural network (GNN) inspired by the signal propagation in chip circuits, which predicts signal delays based on the netlist graph structure and the placement geometry. To ensure compatibility with gradient-based optimization, we design the GNN architecture so that its output is approximately a linear function of a set of geometric distance statistics, enabling efficient and stable gradient computation with respect to cell coordinates. Experiments on $28$ chip designs from widely used benchmarks demonstrate that LiTPlace significantly improves timing quality, achieving an average improvement of $19.2\\%$ in TNS and $7.7\\%$ in WNS, which are two key metrics to quantify the chip timing quality.

TL;DR: We propose a learning-based timing-driven global placement method.