Engineering domain: Digital Hardware Design

# SLC-3 CPU Design

This assessment evaluate the SLC-3 CPU's control logic and state machine implementation.

## PART 1: Control Signal Settings

For each instruction, determine the precise configuration of all control signals during the execution phase. 

The response MUST be structured as follows:

"ports_table": {
  "ADD": {
    "ld_reg": "",
    "ld_ir": "",
    "ld_pc": "",
    "ld_cc": "",
    "gateALU": "",
    "gateMDR": "",
    "mem_en": "",
    "mem_we": ""
  },
  "AND": {
    // Control signals for AND
  },
  // Continue for each instruction...
}


## PART 2: State Machine Implementation

The SLC-3 CPU uses the following key states in its finite state machine:

- s_18: Common fetch cycle state
- s_32: Decode state
- s_1: ADD execution state
- s_5: AND execution state
- s_9: NOT execution state
- s_0: BR evaluation state
- s_22: BR taken state
- s_12: JMP execution state
- s_4: JSR execution state
- s_21: JSR linkage state
- s_6: LDR address calculation state
- s_25_1, s_25_2, s_25_3: LDR memory access sequence states
- s_27: LDR data ready state
- s_7: STR address calculation state
- s_23: STR memory prepare state
- s_16_1, s_16_2, s_16_3: STR memory write sequence states

Your state_transitions MUST use this exact format:

"state_transitions": {
  "ADD": {
    "current": "s_1",
    "next": ""
  },
  "AND": {
    "current": "s_5",
    "next": ""
  },
  // For BR, use this special format
  "BR": {
    "current": "s_0",
    "next_taken": "",
    "next_not_taken": "",
    "sequence_taken": ","
  },
  // Multi-cycle example (use comma-separated string)
  "LDR": {
    "current": "s_6",
    "next": "",
    "sequence": ",,,,"
  }
}

IMPORTANT: For multi-cycle instructions and branch paths, use comma-separated strings (NOT arrays or nested objects).

## PART 3: Explanations

You must also provide a detailed explanation for each instruction:
"explanation": {
  "ADD": "Explanation for ADD instruction...",
  "AND": "Explanation for AND instruction...",
  // Continue for each instruction...
}

## Instructions to Analyze:

1. ADD - Arithmetic addition
2. AND - Bitwise AND
3. NOT - Bitwise complement
4. LDR - Load from memory to register
5. STR - Store register to memory
6. BR - Conditional branch
7. JMP - Unconditional jump
8. JSR - Jump to subroutine
9. SWAP - Exchange registers (custom instruction)

## Critical Design Constraints:

Hardware safety: No multiple components may drive the bus simultaneously
Control accuracy: PC updates occur only during branch and jump operations
State consistency: All execution paths must eventually return to s_18 (fetch cycle)
Cycle requirements: Memory operations must follow proper sequence states
Instruction integrity: JSR must save return address to R7 before jumping
Power efficiency: Minimize active control signals whenever possible

## REQUIRED OUTPUT FORMAT:

Your complete response MUST follow this exact structure:
{
  "config": {
    "ports_table": {
      "ADD": { "ld_reg": "1", "ld_ir": "0", ... },
      "AND": { ... },
      // All instructions
    },
    "explanation": {
      "ADD": "Explanation text...",
      "AND": "Explanation text...",
      // All instructions
    },
    "state_transitions": {
      "ADD": { "current": "s_1", "next": "" },
      "AND": { "current": "s_5", "next": "" },
      "BR": { "current": "s_0", "next_taken": "s_22", "next_not_taken": "", "sequence_taken": "," },
      "LDR": { "current": "s_6", "next": "", "sequence": "" },
      // All instructions
    }
  }
}

Ensure you follow this structure exactly. Use strings for all values, and comma-separated strings (not arrays) for sequences. Any validation errors will result in automatic failure.