Engineering domain: Analog Integrated Circuit Design

## Task Description (FC‑OTA Sizing Only)
You are given a folded‑cascode OTA topology whose schematic has already been instantiated.  
The full netlist is shown in the code block **<FC_OTA_TEMPLATE>** below, where every
MOSFET width/length placeholder appears as symbols `W0…W17`, `L0…L17`, etc.
The output should be only the FC_OTA_TEMPLATE format provided under.

### Task 1 — Device Sizing
**Process Rule**  
All MOSFETs must instantiate **exactly** the foundry models  
`tsmc18dP` (PMOS) and `tsmc18dN` (NMOS).  
You **may only adjust** the parameters `W`, `L`, and `m` (multiplier).  
Do **not** edit or override any other model settings, corners, or temperatures.

Replace every `W*`, `L*`, `R*`, and `M*` placeholder in the template with concrete numeric
values (µm or Ω) so that the design meets the required performance.  
**Do not** change device connectivity, add/delete devices, or alter pin names.

### Task 2 — Performance Verification
Using the provided Cadence/SPECTRE testbench (unity‑gain buffer, CL = 1 pF, VDD = 1.4 V,
VCM = 600 mV), verify that the sized design satisfies:

| Spec | Target |
|------|--------|
| DC gain AV0 | ≥ 60 dB |
| Unity‑gain frequency fUGF | ≥ 50 MHz |
| Phase margin PM | ≥ 60° |
| DC input‑to‑output error \|vip,DC – vout,DC\| | ≤ 0.6 mV |
| Total DC current | ≤ 150 µA |
| Input common‑mode range (ICMR) | ≥ 600 mV* |

\*ICMR pass rule: for VCM ∈ {VSS, VSS+25 mV, …, VDD‑25 mV}, each point must achieve  
AV0 ≥ 50 dB, fUGF ≥ 40 MHz, PM ≥ 45°, and \|vip,DC – vout,DC\| ≤ 1.8 mV.

---

### <FC_OTA_TEMPLATE>
```spice
// Library name: MP4
// Cell name: fc_ota
// View name: schematic
.subckt fc_ota VDD VSS ibn10u vin vip vout
* --- PMOS devices ---
P17 (BP2 ibn10u net22 VDD) tsmc18dP w=W17 l=L17 as=W17*2.5*(180n) ad=W17*2.5*(180n) ps=(2*W17)+(5*180n) pd=(2*W17)+(5*180n) m=M17 region=sat
P0  (net1 BP2 VDD VDD)     tsmc18dP w=W0  l=L0  as=W0 *2.5*(180n) ad=W0 *2.5*(180n) ps=(2*W0 )+(5*180n) pd=(2*W0 )+(5*180n) m=M0  region=sat
P16 (net22 BP2 VDD VDD)    tsmc18dP w=W16 l=L16 as=W16*2.5*(180n) ad=W16*2.5*(180n) ps=(2*W16)+(5*180n) pd=(2*W16)+(5*180n) m=M16 region=sat
P13 (BN2 ibn10u net18 VDD) tsmc18dP w=W13 l=L13 as=W13*2.5*(180n) ad=W13*2.5*(180n) ps=(2*W13)+(5*180n) pd=(2*W13)+(5*180n) m=M13 region=sat
P12 (net18 BP2 VDD VDD)    tsmc18dP w=W12 l=L12 as=W12*2.5*(180n) ad=W12*2.5*(180n) ps=(2*W12)+(5*180n) pd=(2*W12)+(5*180n) m=M12 region=sat
P1  (net12 ibn10u net1 VDD)tsmc18dP w=W1  l=L1  as=W1 *2.5*(180n) ad=W1 *2.5*(180n) ps=(2*W1 )+(5*180n) pd=(2*W1 )+(5*180n) m=M1  region=sat
P3  (net3 vip net12 VDD)   tsmc18dP w=W3  l=L3  as=W3 *2.5*(180n) ad=W3 *2.5*(180n) ps=(2*W3 )+(5*180n) pd=(2*W3 )+(5*180n) m=M3  region=sat
P2  (net4 vin net12 VDD)   tsmc18dP w=W2  l=L2  as=W2 *2.5*(180n) ad=W2 *2.5*(180n) ps=(2*W2 )+(5*180n) pd=(2*W2 )+(5*180n) m=M2  region=sat
P7  (vout ibn10u net16 VDD)tsmc18dP w=W7  l=L7  as=W7 *2.5*(180n) ad=W7 *2.5*(180n) ps=(2*W7 )+(5*180n) pd=(2*W7 )+(5*180n) m=M7  region=sat
P6  (net2 ibn10u net13 VDD)tsmc18dP w=W6  l=L6  as=W6 *2.5*(180n) ad=W6 *2.5*(180n) ps=(2*W6 )+(5*180n) pd=(2*W6 )+(5*180n) m=M6  region=sat
P5  (net16 net2 VDD VDD)   tsmc18dP w=W5  l=L5  as=W5 *2.5*(180n) ad=W5 *2.5*(180n) ps=(2*W5 )+(5*180n) pd=(2*W5 )+(5*180n) m=M5  region=sat
P4  (net13 net2 VDD VDD)   tsmc18dP w=W4  l=L4  as=W4 *2.5*(180n) ad=W4 *2.5*(180n) ps=(2*W4 )+(5*180n) pd=(2*W4 )+(5*180n) m=M4  region=sat
* --- NMOS devices ---
N15 (net11 BN1 VSS VSS)    tsmc18dN w=W15 l=L15 as=W15*2.5*(180n) ad=W15*2.5*(180n) ps=(2*W15)+(5*180n) pd=(2*W15)+(5*180n) m=M15 region=sat
N14 (BN1 BN2 net11 VSS)    tsmc18dN w=W14 l=L14 as=W14*2.5*(180n) ad=W14*2.5*(180n) ps=(2*W14)+(5*180n) pd=(2*W14)+(5*180n) m=M14 region=sat
N11 (net4 BN1 VSS VSS)     tsmc18dN w=W11 l=L11 as=W11*2.5*(180n) ad=W11*2.5*(180n) ps=(2*W11)+(5*180n) pd=(2*W11)+(5*180n) m=M11 region=sat
N10 (net3 BN1 VSS VSS)     tsmc18dN w=W10 l=L10 as=W10*2.5*(180n) ad=W10*2.5*(180n) ps=(2*W10)+(5*180n) pd=(2*W10)+(5*180n) m=M10 region=sat
N9  (vout BN2 net4 VSS)    tsmc18dN w=W9  l=L9  as=W9 *2.5*(180n) ad=W9 *2.5*(180n) ps=(2*W9 )+(5*180n) pd=(2*W9 )+(5*180n) m=M9  region=sat
N8  (net2 BN2 net3 VSS)    tsmc18dN w=W8  l=L8  as=W8 *2.5*(180n) ad=W8 *2.5*(180n) ps=(2*W8 )+(5*180n) pd=(2*W8 )+(5*180n) m=M8  region=sat
* --- Passive devices ---
R1 (BP2 ibn10u) resistor r=R1 m=MR1
R0 (BN2 BN1)  resistor r=R0 m=MR0
.ends fc_ota

// Top‑level instantiation
// Library name: MP4
// Cell name: dut
// View name: schematic
I1 (net1 net2 net5 net3 net4 net6) fc_ota