Intel Core i3處理器列表

**[[Intel]] [[Core i3]]** 是「Core i品牌」四個子系列之一。

從Sandy Bridge微架構開始，Intel把微架構和代號改成相同名字。

## 桌上型處理器

### [[Westmere微架構]]

#### "Clarkdale" (32 nm)

### [[Sandy Bridge微架構]]

#### "Sandy Bridge" (32 nm)

### [[Ivy Bridge微架構]]

#### "Ivy Bridge" (22 nm)

### [[Haswell微架構]]

#### "Haswell-DT" (22 nm)

### [[Skylake微架構]]

#### "Skylake-S" (14 nm)

### [[Kaby Lake微架構]]

#### "Kaby Lake-S" (14 nm)

### [[Coffee Lake微架構]]

#### "Coffee Lake-S" (14 nm)

#### "Coffee Lake-H" (14 nm)

### [[Comet Lake微架構]]

## 移動型處理器

### [[Westmere微架構]]（第一代）

#### "Arrandale" (MCP, 32 nm)

*所有型號支援: *[[MMX]],[[SSE]],[[SSE2]], [[SSE3]],[[SSSE3]],[[SSE4.1]], [[SSE4.2]], [[EIST]], [[Intel 64]], [[XD bit]], [[Intel VT-x]],[[超執行緒]],[[Smart Cache]].*
* 整合Intel HD Graphics

### [[Sandy Bridge|Sandy Bridge microarchitecture (2nd generation)]]

#### "Sandy Bridge" (32 nm)

* All models support: *[[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4.1]], [[SSE4.2]], [[Advanced Vector Extensions|AVX]], Enhanced Intel [[SpeedStep]] Technology (EIST), [[Intel 64]], XD bit (an [[NX bit]] implementation), [[Intel VT-x]], [[Hyper-threading]], Smart Cache, [[Intel Insider]].*
* Core i3-2310E, Core i3-2340UE have support for ECC memory.
* Core i3-2310E, Core i3-2330E and Core i3-2340UE do not have support for *[[Intel Insider]]*
* Transistors: 624 million
* Die size: 149&nbsp;mm²

### [[Ivy Bridge (microarchitecture)|Ivy Bridge microarchitecture (3rd generation)]]

#### "Ivy Bridge" (22 nm)

* All models support: *[[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4.1]], [[SSE4.2]], [[Advanced Vector Extensions|AVX]], Enhanced Intel [[SpeedStep]] Technology (EIST), [[Intel 64]], XD bit (an [[NX bit]] implementation), [[Intel VT-x]], [[Hyper-threading]], Smart Cache, [[Intel Insider]].*
* Core i3-3120ME, i3-3217UE have support for ECC memory.
* Core i3-3120ME, i3-3217UE do not have support for *[[Intel Insider]].*
* Core i3-3229Y supports *[[AES instruction set|AES-NI]]*.
* Die size: 94&nbsp;mm²

### [[Haswell (microarchitecture)|Haswell microarchitecture (4th generation)]]

#### "Haswell-MB" (22 nm)
* All models support: *[[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4.1]], [[SSE4.2]], [[Advanced Vector Extensions|AVX]], [[Advanced Vector Extensions 2|AVX2]], [[FMA3]], Enhanced Intel [[SpeedStep]] Technology (EIST), [[Intel 64]], XD bit (an [[NX bit]] implementation), [[Intel VT-x]], [[Hyper-threading]], Smart Cache.*

#### "Haswell-ULT" ([[system in package|SiP]], 22 nm)

* All models support: *[[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4.1]], [[SSE4.2]], [[Advanced Vector Extensions|AVX]], [[Advanced Vector Extensions 2|AVX2]], [[FMA3]], Enhanced Intel [[SpeedStep]] Technology (EIST), [[Intel 64]], XD bit (an [[NX bit]] implementation), [[Intel VT-x]], [[Hyper-threading]], [[AES instruction set|AES-NI]], Smart Cache.*
* Core i3-4010U and higher also support *[[Intel VT-d]]*
* Transistors: 1.3 billion
* Die size: 181&nbsp;mm²

#### "Haswell-ULX" ([[system in package|SiP]], 22 nm)

* All models support: *[[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4.1]], [[SSE4.2]], [[Advanced Vector Extensions|AVX]], [[Advanced Vector Extensions 2|AVX2]], [[FMA3]], Enhanced Intel [[SpeedStep]] Technology (EIST), [[Intel 64]], XD bit (an [[NX bit]] implementation), [[Intel VT-x]], [[Hyper-threading]], [[AES instruction set|AES-NI]], Smart Cache.*
* Transistors: 1.3 billion
* Die size: 181&nbsp;mm²

#### "Haswell-H" (22 nm)

* All models support: *[[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4.1]], [[SSE4.2]], [[Advanced Vector Extensions|AVX]], [[Advanced Vector Extensions 2|AVX2]], [[FMA3]], Enhanced Intel [[SpeedStep]] Technology (EIST), [[Intel 64]], XD bit (an [[NX bit]] implementation), [[Intel VT-x]], [[Hyper-threading]], Smart Cache.*
* Transistors: 1.3 billion
* Die size: 181&nbsp;mm²
* Embedded models support ECC memory

### [[Broadwell (microarchitecture)|Broadwell microarchitecture (5th generation)]]
#### "Broadwell-U" (14 nm)
* All models support: *[[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4.1]], [[SSE4.2]], [[Advanced Vector Extensions|AVX]], [[Advanced Vector Extensions 2|AVX2]], [[FMA3]], Enhanced Intel [[SpeedStep]] Technology (EIST), [[Intel 64]], XD bit (an [[NX bit]] implementation), [[Intel VT-x]], [[Intel VT-d]], [[Hyper-threading]], [[AES instruction set|AES-NI]], Smart Cache*, and configurable TDP (cTDP) down

### [[Skylake (microarchitecture)|Skylake microarchitecture (6th generation)]]

#### "Skylake-H" (14 nm)
* All models support: *[[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4.1]], [[SSE4.2]], [[Advanced Vector Extensions|AVX]], [[Advanced Vector Extensions 2|AVX2]], [[FMA3]], Enhanced Intel [[SpeedStep]] Technology (EIST), [[Intel 64]], XD bit (an [[NX bit]] implementation), [[Intel VT-x]], [[Intel VT-d]], [[Hyper-threading]], [[AES instruction set|AES-NI]], Smart Cache.*
* Transistors: TBD
* Die size: TBD
* Embedded models support ECC memory

#### "Skylake-U" (14 nm)
* All models support: *[[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4.1]], [[SSE4.2]], [[Advanced Vector Extensions|AVX]], [[Advanced Vector Extensions 2|AVX2]], [[FMA3]], Enhanced Intel [[SpeedStep]] Technology (EIST), [[Intel 64]], XD bit (an [[NX bit]] implementation), [[Intel VT-x]], [[Intel VT-d]], [[Hyper-threading]], [[AES instruction set|AES-NI]], Smart Cache*, and configurable TDP (cTDP) down (except 6006U)

### [[Kaby Lake|Kaby Lake microarchitecture (7th generation)]]

#### "Kaby Lake-H" (14 nm)
* All models support: *[[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4.1]], [[SSE4.2]], [[Advanced Vector Extensions|AVX]], [[Advanced Vector Extensions 2|AVX2]], [[FMA3]], [[Software Guard Extensions|SGX]], [[Intel MPX|MPX]], Enhanced Intel [[SpeedStep]] Technology (EIST), [[Intel 64]], XD bit (an [[NX bit]] implementation), [[Intel VT-x]], [[Intel VT-d]], [[Hyper-threading]], [[AES instruction set|AES-NI]], Smart Cache.*
* Transistors: TBD
* Die size: TBD
* Embedded models support ECC memory

#### "Kaby Lake-U" (14 nm)
* 全系列支援指令: *[[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4.1]], [[SSE4.2]], [[Advanced Vector Extensions|AVX]], [[Advanced Vector Extensions 2|AVX2]], [[FMA3]], [[Software Guard Extensions|SGX]], [[Intel MPX|MPX]], Enhanced Intel [[SpeedStep]] Technology (EIST), [[Intel 64]], XD bit (an [[NX bit]] implementation), [[Intel VT-x]], [[Intel VT-d]], [[Hyper-threading]], [[AES instruction set|AES-NI]], [[Smart Cache]]*, and configurable TDP (cTDP) down.

### [[Ice Lake微架構|Ice Lake microarchitecture (10th generation)]]
### [[Comet Lake微架構|Comet Lake microarchitecture (10th generation)]]
#### "Comet Lake-U" (dual-core, 14 nm)

#### "Comet Lake-Y" (dual-core, 14 nm)

### [[Ice Lake微架构]]

#### "Ice Lake-U" (dual-core, 10 nm)
* All models support: *[[MMX]], [[SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4.1]], [[SSE4]], [[Advanced Vector Extensions|AVX]], [[AVX指令集]], [[AVX-512]], [[FMA指令集]], [[英特尔软件防护扩展]], [[SpeedStep]] (SST), [[X86-64]], XD bit (an [[NX位元]] implementation), [[Intel VT-x]], [[X86虚拟化]], [[Intel睿频加速]], [[超執行緒]], [[AES指令集]], [[CPU缓存]], [[深度学习]]*, and 热设计功耗 (cTDP).

#### "Ice Lake-Y" (dual-core, 10 nm)
* All models support: *[[MMX]], [[SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4.1]], [[SSE4]], [[Advanced Vector Extensions|AVX]], [[AVX指令集]], [[AVX-512]], [[FMA指令集]], [[英特尔软件防护扩展]], [[SpeedStep]] (SST), [[X86-64]], XD bit (an [[NX位元]] implementation), [[Intel VT-x]], [[X86虚拟化]], [[Intel睿频加速]], [[超執行緒]], [[AES指令集]], [[CPU缓存]], [[深度学习]]*, and 热设计功耗 (cTDP) (except 1000NG4).

### [[Tiger Lake (microprocessor)|Willow Cove microarchitecture (11th generation)]]

#### "Tiger Lake-UP3" (10 nm SuperFin)
* All models support: *[[SSE4.1]], [[SSE4.2]], [[Advanced Vector Extensions 2|AVX2]], [[AVX-512]], [[FMA3]], [[SpeedStep|Speed Shift Technology]] (SST), [[Intel 64]], [[Intel VT-x]], [[Intel VT-d]], [[Intel Turbo Boost|Turbo Boost]], [[Hyper-threading]], [[AES instruction set|AES-NI]], [[Smart Cache]], [[deep learning|DL Boost]], [[3D XPoint|Optane]] *memory*, GNA 2.0, [[Image processor|IPU6]]* (except SRK08)*, [[Thunderbolt (interface)#Thunderbolt 4|TB4]]*, and configurable TDP (cTDP).
* -RE models support ECC memory.

#### "Tiger Lake-UP4" (10 nm SuperFin)
* All models support: *[[SSE4.1]], [[SSE4.2]], [[Advanced Vector Extensions 2|AVX2]], [[AVX-512]], [[FMA3]], [[SpeedStep|Speed Shift Technology]] (SST), [[Intel 64]], [[Intel VT-x]], [[Intel VT-d]], [[Intel Turbo Boost|Turbo Boost]], [[Hyper-threading]], [[AES instruction set|AES-NI]], [[Smart Cache]], [[deep learning|DL Boost]], [[3D XPoint|Optane]] *memory*, GNA 2.0, [[Image processor|IPU6]], [[Thunderbolt (interface)#Thunderbolt 4|TB4]]*, and configurable TDP (cTDP).

## 參考資料

## 外部連結
* Intel 產品規格資料庫