Title: Verification techniques for system-level design
First published: 2008
Subjects: Formal methods (Computer science), Testing, Verification, Integrated circuits, Systems on a chip, Circuits & components, Electrical engineering, Technology & Engineering, Technology & Industrial Arts, Science/Mathematics, Electricity, Electronics - Circuits - Integrated, Electronics - Microelectronics, Nonfiction, Technology / Engineering / Electrical, Formal methods (Computer science), Integrated circuits, Systems on a chip, Testing, Verification, System design
LC classification: TK7895.E42 F95 2008