Title: Timing optimization through clock skew scheduling
First published: 2000
Subjects: Design and construction, Very large scale integration, Synchronization, Timing circuits, Integrated circuits, Circuits & components, General Theory of Computing, Science/Mathematics, Very-Large-Scale Integration (Vlsi), Technology, Technology & Industrial Arts, Electronics - Circuits - VLSI, Engineering - Electrical & Electronic, Clock Timing, EDA, Placement Methodologies, Skew Scheduling, Technology / Electronics / Circuits / General, Technology / Electronics / Circuits / VLSI, Technology-Engineering - Electrical & Electronic, Electronics - Circuits - General, Integrated circuits, very large scale integration, Electronic circuit design
LC classification: TK7874.75 .K68 2000, TK7874.75 .K68 2000