Title: Design of High Speed I/O Interfaces for High Performance Microprocessors
Description: Advances in CMOS process technology have enabled high performance microprocessors that run multiple threads in parallel at multi-gigahertz clock frequencies. The off-chip input/output (I/O) bandwidth of these chips should scale along with the on-chip computation capacity in order for the entire system to reap performance benefits. However, scaling of off-chip I/O bandwidth is constrained by limited physical pin resources, legacy interconnect technology and increasingly noisy on-chip environment. Limited power budgets and process/voltage/temperature (PVT) variations present additional challenges to the design of I/O circuits. This thesis focuses on the need to improve timing margin at the data samplers in the receivers, to enable higher symbol-rates per channel. The first part of this thesis describes a technique to reclaim timing margin lost to jitter both in the transmitted data and sampling clock. The second part discusses two techniques to correct for static phase errors in the sampling clocks that can degrade timing margin. Two test-chips, designed and fabricated in 0.13µm CMOS technology, demonstrate the efficacy of these techniques.

An 8-channel, 5 Gb/s per channel receiver demonstrates a collaborative timing recovery architecture. The receiver architecture exploits synchrony in transmitted data streams in a parallel interface and combines error information from multiple phase detectors in the receiver to produce one global synthesized clock. Experimental results from the prototype test-chip confirm the enhanced jitter tracking bandwidth and lower dithering jitter on the recovered clock. This chip also enables measurements that demonstrate the advantages and disadvantages of employing delay-locked loops (DLL) in the receivers. Two techniques to condition the clock signals entering the DLL are proposed that reduce the errors in phase-spacing matching between adjacent phases of the DLL and improve receiver timing margins. A digital calibration technique takes a more general and inclusive approach towards correcting phase-spacing mismatches in multi-phase clock generators. A shared-DAC scheme reduces the area consumption of phase-correction circuits by more than 60%. This technique is implemented to correct phase-spacing mismatches in a 8-phase 1.6 GHz DLL. Experiments performed on the test-chip demonstrate reduction in peak differential non-linearity (DNL) from 37 ps to 0.45 ps, while avoiding any additional jitter penalties from the shared-DAC scheme.