Title: Local Oscillator (LO)-Based Analog Signal Processing in Integrated Circuits and Systems
Description: Wireless systems, ranging from radio to optical frequencies, typically comprise two domains: the signal path and the local oscillator (LO) path. While signal processing is conventionally performed in the signal path, more recently, techniques that exploit LO-based signal processing are becoming increasingly popular. LO-based analog signal processing can be utilized for solving fundamental problems and for improving the performance of systems in a wide variety of applications that span radio to optical frequencies. In this dissertation, I explore LO-based signal processing to enable new functionalities and enhance performance in electrical, optical, and electro-optical circuits and systems. In the electro-optical domain, I use LO-based signal processing to improve the performance of a long-range Frequency-Modulated Continuous-Wave (FMCW) Light Detection and Ranging (LiDAR) system. As laser nonlinearity degrades the performance of ranging and imaging systems, it is essential to address this problem.

In this dissertation, to linearize a laser, an integrated continuous-time Electro-Optical Phase-Locked Loop (EOPLL) is presented with a loop bandwidth equal to its reference frequency. Despite the high bandwidth, the proposed system is spurless, which is enabled by using Single-Sideband (SSB) and Harmonic-Reject mixing (HRM) techniques. These techniques are explored in Phase-Locked Loop (PLL) design for the first time. These features result in less area consumption and loss associated with the optical part of the system and increase the precision and accuracy of our long-range FMCW LIDAR significantly. In the electrical domain, I use LO engineering to address some of the challenges that exist in three different electrical systems including mm-wave Multi-Input Multi-Output (MIMO) systems, ultra-low power RF systems, and wideband mm-wave systems. In the first project, to alleviate the challenge of supporting a high data rate Input/Output (I/O) interface in a large-scale tiled mm-wave MIMO array, a single-wire interface (SWI) is used in this dissertation, and a 60GHz 4-element scalable MIMO transmitter (TX) prototype is designed.

In our work, we use frequency-domain multiplexing (FDM) to simultaneously support the signals of four MIMO channels. Then, in our proposed FDM, HRM is utilized to generate the different frequencies at which the various IF signals are multiplexed. This enables us to multiplex and de-multiplex the four modulated signals simultaneously to/from the single-wire using multiple phases of only one LO. The technique proposed in this research significantly reduces the number of lines needed for LO and signal routing in a massive MIMO system. The second electrical project in this dissertation targets ultra-low power receivers at RF frequency. Wake-up receivers (WURX) are integral to reducing the power consumed by the main or primary RX in ultra-low power systems. Thus, the ability to share one antenna for both RXs is essential and results in a compact hybrid system. Furthermore, linearity and sensitivity are two fundamental criteria in these RXs. In order to improve the linearity of these systems, mixer-first RX architecture can be used for both RXs.

However, mixer-first architecture has some drawbacks, like low gain and high noise figure (NF), which degrade the sensitivity of the system. Here, in our research, we implement a hybrid primary RX and WURX in which, first, a Quadrature Hybrid Coupler (QHC) is used to share one antenna between the two RXs and to achieve wideband input matching. Secondly, to address the problem of sensitivity in the mixer-first structure, we exploit a LO-assisted noise-canceling technique combined with a bottom-plate capacitor mixer-first receiver. This structure exploits implicit capacitive stacking which enables us to achieve passive LO-defined voltage gain, high linearity, and a low NF. In the last electrical project in this dissertation, I present a novel frequency-interleaved (FI) channel aggregation architecture for wideband mm-wave systems that relaxes the requirements of their Analog-to-Digital/Digital-to-Analog Converters (ADC/DAC) and consequently reduces the total cost and power consumption. In our proposed architecture, the input bandwidth is channelized into four sub-channels, which are individually up/downconverted from/to baseband, where they can be digitized with multiple lower rate subconverters.

We use the idea of HRM in the channelizer to simultaneously down(up)convert four sub-channels with only one LO. Four chips, including two mm-wave RX and TX chips and two baseband RX and TX chips, are designed and tested to show the functionality of the entire system as a transceiver. Finally, I conclude this dissertation with an optical project which is a Silicon Photonic (SiP) simultaneous Mode and Wavelength Division (De)Multiplexer (MWD(De)MUX) for optical frequencies at C-band. I use an advanced 3D simulation tool, RSOFT software, to design and test this novel compact SiP structure. Our circuit uses a cascade of Mode Division Multiplexer (MDM) and Wavelength Division Multiplexer (WDM) stages for (de)multiplexing. A novel phase shifter introduced and used in this work is designed using two close waveguides on a CMOS compatible SiP platform, which results in reduced loss and size compared to conventional techniques.