Title: Formal techniques, modelling and analysis of timed and fault-tolerant systems
Description: This volume contains the proceedings of the joint conference on Formal M- elling and Analysis of Timed Systems (FORMATS) and Formal Techniques in Real-Time and Fault Tolerant Systems (FTRTFT), held in Grenoble,France,on September 22–24,2004. The conference united two previously independently - ganized conferences FORMATS and FTRTFT. FORMATS 2003 was organized asasatelliteworkshopofCONCUR2003andwasrelatedtothreeindependently started workshop series: MTCS (held as a satellite event of CONCUR 2000 and CONCUR 2002), RT-TOOLS (held as a satellite event of CONCUR 2001 and FLoC 2002) and TPTS (held at ETAPS 2002). FTRTFT is a symposium that was held seven times before: in Warwick 1988, Nijmegen 1992, Lu ¨beck 1994, Uppsala 1996, Lyngby 1998, Pune 2000 and Oldenburg 2002. The proceedings of these symposia were published as volumes 331, 571, 863, 1135, 1486, 1926, and 2469 in the LNCS series by Springer. Thisjointconferenceis dedicatedtotheadvancementofthetheoryandpr- ticeofthe modelling,designandanalysisofreal-timeandfault-tolerantsystems. Indeed,computersystemsarebecomingincreasinglywidespreadinreal-timeand safety-critical applications such as embedded systems. Such systems are char- terized by the crucial need to manage their complexity in order to produce reliable designs and implementations. The importance of timing aspects, p- formance and fault-tolerance is continuously growing. Formal techniques o?er a foundation for systematic design of complex systems. They have bene?cial - plications throughout the engineering process, from the capture of requirements through speci?cation, design, coding and compilation, down to the hardware that embeds the system into its environment.
Subjects: Computer simulation, Congresses, Fault-tolerant computing, Formal methods (Computer science), Machine theory, Real-time data processing, Robots, Temporal automata, Computers, Computer science, Memory management (Computer science), Software engineering, Logic design