Title: SystemVerilog for Verification
Subjects: Systems engineering, Circuits and Systems, Computer input-output equipment, Computers, Engineering, Computer-Aided Engineering (CAD, CAE) and Design, Computer engineering, Computer-aided design, Electrical engineering, Verification, Integrated circuits, SystemVerilog (Computer hardware description language), Verilog (computer hardware description language), Object-oriented programming (computer science), Computer hardware description languages, Object-oriented programming (Computer science), Ingénierie