Title: Modeling, fabrication, and characterization of 2D devices for electronic and photonic applications
Description: Over the last two decades, two-dimensional (2D) materials such as graphene and transition metal dichalcogenides (TMDCs) have invoked tremendous interest of the scientific community due to their unique electronic and optical properties. While TMDCs hold great promise as a potential replacement for silicon for scaling transistors beyond sub-3 nm technology node, graphene holds great potential as transparent electrodes and optical phase-modulators for next-generation photonic devices. In addition to the aforementioned applications, these 2D devices also provide a great platform for studying novel physical phenomena associated with 2D materials such as Moiré interactions, valley-dependent spintronics, and correlated electron physics. In order to realize high-performance 2D material based devices, advancement of three key aspects are imperative - (1) analytical modeling to gauge insights into the electrostatics and current transport in 2D devices, (2) development of efficient techniques for fabricating 2D devices, and (3) understanding the fundamental limitations of the existing characterization techniques and developing better methods.

We started by modeling the unique electrostatics of the 2D lateral p-n junctions, wherein we developed analytical expressions for the electric field, electrostatic potential, and depletion width across 2D lateral p-n junctions. We extend these expressions for use in lateral 3D metal-2D semiconductor junctions and lateral 2D heterojunctions. The results show a significantly larger depletion width (~ 2 to 20x) for 2D junctions compared to conventional 3D junctions. Further, we show that the depletion widths at metal-2D semiconductor junctions can be significantly modulated by the surrounding dielectric environment and semiconductor doping density. Finally, we derived a minimal dielectric thickness for a symmetrically-doped 2D lateral p-n junction, above which the out-of-plane simulation region boundaries minimally affect the simulation results. After electrostatics, we attempted to understand the current transport in 2D material-based devices. Typically used back-gated field-effect transistors (BGFETs) are often modeled as Schottky barrier (SB)-MOSFETs assuming that the current flow is limited by the source-contact in the OFF state, while the channel limits the current in the ON state.

Here, using an analytical model and drift-diffusion simulations, we show that the channel limits the overall current in the OFF state and vice versa, contrary to past studies. For top-contacted BGFETs, we modeled different current paths at a top-contacted metal-2D semiconductor junction and illustrated the unique “corner effect”—where the potential change and current transport are dominated by the metal-2D semiconductor edge and the associated lateral region. We determined that the edge transport supersedes the vertical current injection in monolayer TMDCs and hence, to reduce contact resistance in 2D devices degenerate doping of channel region next to contact regions is of paramount importance. After developing models to theoretically analyze these devices, we focused on understanding the shortcomings in the existing characterization techniques affecting the extraction of important device parameters such as contact resistance, SBH, and channel mobility. We prove that the transfer length estimated using the standard TLM measurement techniquecan severely overestimate the true transfer length.

We also discuss the large discrepancy in SBH values extracted using the Arrhenius method compared to their theoretical values. Using our analytical modeling, we attribute this to the presence of long channel regions in experimental devices. Furthermore, we highlight that the presence of large contact resistance results in underestimation of channel mobilities which renders Kelvin measurements such as four-probe and Hall-bar measurements imperative for 2D devices. Finally, we introduced a unique etch and doping method using self-limiting oxidation which allows us to design and fabricate various high-performance 2D devices. We first used the method to demonstrate a selective, damage-free atomic layer etch (ALE) that enables layer-by-layer removal of monolayer WSe₂ without altering the physical, optical, and electronic properties of the underlying layers. Using a comprehensive set of characterization techniques, we show that the quality of our ALE processed layers is comparable to that of pristine layers of similar thickness.

Further, using graphene as a testbed, we demonstrate the use of a sacrificial monolayer WSe₂ layer to protect the channel, which is etched in the final process step in a technique we call Sacrificial WSe₂ with ALE Processing (SWAP). Furthermore, the top oxidized layer acts like an atomically thin degenerate p-type dopant for a large variety of semiconductors such as graphene, carbon nanotubes, and WSe2. We show that the TOS-doped graphene yields a low sheet resistance due to high mobility at a very high hole density that remains active even at 1.5 K. We apply this principle to improve the transmittance of graphene (>99%) at telecommunication bandwidth (1.5 to 1.6 𝜇m), that makes it a suitable replacement for Indium tin oxide (ITO) as a transparent electrode.