Title: High-Performance Reconfigurable Radio-Frequency Integrated-Circuit Receiver Architectures for Concurrent Signal Reception
Description: The ever-increasing demand for wireless throughput requires modern handset receivers to aggregate signals from multiple non-contiguously allocated RF carriers. This poses significant receiver design challenges, including concurrent signal reception, RF input interface, out-of-band (OB) linearity, and suppression of spurious responses. Commercial solutions use external antenna switches and off-chip RF multiplexers to provide non-tunable, narrowband filtering and impedance matching. The RF signal is then divided into separate signal chains, each with a dedicated receiver for signal reception. Although this solution allows the selection of any carrier combinations supported by the available RF filters, as the number of aggregation band combinations increases, the scale of the passive front-end module grows rapidly, leading to increased system complexity, extra signal loss, and degraded performance. This thesis presents the design and implementation of two receiver architectures that support reconfigurable operations and flexible, concurrent reception from two inter-band carriers with a tuned RF interface.

We first present a multi-branch receiver with modulated mixer clocks (MMC). It unifies the functions of single-carrier and dual-carrier reception, as well as compressive-sampling spectrum scanning into a single architecture. With continuous-wave-modulated mixer clocks, the receiver supports concurrent reception from two distinct bands and realizes tuned impedance matching that greatly improves the OB linearity. With pseudo-noise-modulated mixer clocks, the receiver supports spectrum scanning. Disabling modulation reverts the receiver into a single-carrier receiver with good OB linearity. The 65nm CMOS prototype is developed that operates from 300 to 1300MHz and offers 2.7dB minimum NF, -1.3dBm B1dB, and +8.0dBm IIP3 for single-carrier reception. Concurrent dual-carrier reception is demonstrated that offers -8.4dBm B1dB and sub-6dB NF with the two carriers separated from 200 to 600MHz apart. For spectrum scanning, the receiver achieves a 66dB dynamic range with -75dBm sensitivity over a 630MHz RF span.

In addition, a discussion of the higher-order MMC technique is included to improve the receiver’s spurious and noise performance by suppressing the higher-order responses and mitigating the noise-folding effect. Next, we present an IF-filterless, double-conversion receiver. The concurrent, narrowband RF interface is realized with two layers of passive mixing in its mixer-first branches, which translate the low-pass, baseband impedance twice to two distinct bands and improve the OB linearity. Branches with DDS-modulated LNTAs for multi-phase, switched-Gm mixing offer rejection of spurious responses and improved noise performance. The 65nm CMOS prototype is developed that operates from 100 to 1200MHz. For single-carrier reception, the receiver delivers 4.8dB minimum NF, +7.9dBm B1dB, and +22.8dBm IIP3. For concurrent signal reception, two arbitrarily-allocated RF carriers, separated from 200 to 600MHz apart, can be received concurrently. The receiver delivers a +1.9dBm B1dB and supports 8-/16-phase DDS modulation with a 30dB spurious rejection across its operating range.

In addition, a theoretical study of a modified, mixer-first branch is included. By re-arranging the connections of the baseband termination resistors, the baseband noise can be fully cancelled, thus improving the receiver’s noise performance.