VLSI design for pipelined FFT processors
By: David Charles Stuart
Contributors: Naval Postgraduate School (U.S.)
Publisher: Naval Postgraduate School
Published: 1990
Place of publication: Monterey, California
Language: eng
Number of pages: 194
Description: A system of custom cell building blocks utilizing scaleable CMOS technology is decribed. The cells are design to support the high speed, pipelined addition, subtraction, and multiplication operations neccessary in a cyclic spectral analyser or other applications involving the FFT. The cells are structured in such a manner as to permit a designer to tailor the bit-length of the operations and the number of pipline stages used. Both fixed and floating operations are supported by the system. The size and performance characteristics of devices produced using the cells are compared with previously produced Genesil Silicon Complier pipelined desings. The appendix contains designs of 16-bit mantissa, 12-bit exponent floating point multiplier and adder produced from the standard cells. If fabricated in 1.2(symbol) feature size technology, the theoretical maximum clock speed and throughput rate is 102 MHz with an asymmetric clock and 61 MHz using a symmetric clock waveform. Devices with clock speeds up to 178 MHz are possible if the number of logic cells between a pipeline stage is reduced to one.
Notes: Thesis Advisor(s): Loomis, Herschel H. ; Second Reader: Cotton, Mitchell L.

"June 1990."

Author(s) subject terms: VLSI Multipliers, VLSI Adders, Pipelined Arrays, Floating-point Multipliers, Floating-point Adders, FFT Processors.

Description based on title screen as viewed on October 16, 2009.

Thesis (M.S. in Electrical Engineering and Electrical Engineer)--Naval Postgraduate School, June 2009.

Includes bibliographical references (p. 192-193).

"Approved for public release, distribution unlimited"--Cover.

US Navy (USN) author.

rb/rb original 10/20/09.