Field programmable gate array implementation of a multi-rate phase locked loop.
Published: 2005
Language: eng
Number of pages: 88
Description: Synchronization technique can be employed in various applications, many of which are based on three-phase signals; therefore, synchronization to three-phase signals is required. Because the positive sequence signal is the closest signal associated with the generating source, it is employed for synchronization purposes. One such existing synchronization scheme is the multi-rate phase locked loop (MPLL). The MPLL stabilities are impacted by amplitude variations. An amplitude estimation module (E) and an automatic gain control module are used to decouple this impact. The previous work implemented the E module based on a fast Fourier transform (FFT) algorithm, which is complicated and utilizes many hardware resources. Peak detection is developed to replace the FFT algorithm. The integrated system consisting of a MPLL and a positive sequence detector has been implemented on a field programmable gate array (FPGA) platform and its performances are compared with the previous work.
Notes: Source: Masters Abstracts International, Volume: 44-02, page: 0986.

Thesis (M.A.Sc.)--University of Toronto, 2005.

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