SACS
Subtitle: a cache simulator incorporating timing analysis with buffer and memory management
By:  William G. Smith
Publisher: Naval Postgraduate School; Available from National Technical Information Service
Published: 1994
Place of publication: Monterey, Calif; Springfield, Va
Language: eng
Number of pages: 257
Description: SACS is a cache simulator that provides the user with a wide range of timing information, in addition to providing typical information such as hit and miss rates. The SACS model includes read and write buffers, main memory, and cache memory. In addition. SACS supports a number of buffer and data forwarding policies, as well as the traditional block replacement, write. and write miss policies. SACS also includes a self-testing mode which can be used to debug the program after source-code modification.
Notes: Thesis advisor(s): Douglas J. Fouts.

"March 1994."

Thesis (M.S. in Electrical Engineering) Naval Postgraduate School, March 1994.

Bibliography: p. 256.

Approved for public release; distribution unlimited.

Also available online.

Mode of access: World Wide Web.

System requirements: Adobe Acrobat Reader.

US Naval Reserve (USNR) author.